GCC,nvptx,0,"Predict the next statement of this code snippet:
 <s> ptx_dumpbase = concat ( dumppfx , <STR_LIT> , NULL ) ; if ( save_temps ) ptx_cfile_name = ptx_dumpbase ; else ptx_cfile_name = make_temp_file ( <STR_LIT> ) ; out = fopen ( ptx_cfile_name , <STR_LIT> ) ; if ( ! out ) fatal_error ( input_location , <STR_LIT> , ptx_cfile_name ) ; if ( offload_abi == OFFLOAD_ABI_LP64 ) { char * mko_dumpbase = concat ( dumppfx , <STR_LIT> , NULL ) ; if ( save_temps ) ptx_name = mko_dumpbase ; else ptx_name = make_temp_file ( <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , mko_dumpbase ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , ptx_name ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; const char * * new_argv = XOBFINISH ( & argv_obstack , const char * * ) ; char * execpath = getenv ( <STR_LIT> ) ; char * cpath = getenv ( <STR_LIT> ) ; char * lpath = getenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; if ( save_temps ) omp_requires_file = concat ( dumppfx , <STR_LIT> , NULL ) ; else omp_requires_file = make_temp_file ( <STR_LIT> ) ; xputenv ( concat ( <STR_LIT> , omp_requires_file , NULL ) ) ; fork_execute ( new_argv [ <NUM_LIT> ] , CONST_CAST ( char * * , new_argv ) , true , <STR_LIT> ) ; obstack_free ( & argv_obstack , NULL ) ; unsetenv ( <STR_LIT> ) ; xputenv ( concat ( <STR_LIT> , execpath , NULL ) ) ; xputenv ( concat ( <STR_LIT> , cpath , NULL ) ) ; xputenv ( concat ( <STR_LIT> , lpath , NULL ) ) ; in = fopen ( omp_requires_file , <STR_LIT> ) ; if ( ! in ) fatal_error ( input_location , <STR_LIT> , omp_requires_file ) ; uint32_t omp_requires ; if ( fread ( & omp_requires , sizeof ( omp_requires ) , <NUM_LIT> , in ) != <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> , omp_requires_file ) ; fclose ( in ) ; in = fopen ( ptx_name , <STR_LIT> ) ; if ( ! in ) fatal_error ( input_location , <STR_LIT> ) ; process ( in , out , omp_requires ) ;"
GCC,nvptx,1,"Predict the next statement of this code snippet:
 <s> if ( output_fn_ptr && ( omp_requires & GOMP_REQUIRES_REVERSE_OFFLOAD ) != <NUM_LIT> ) { if ( sm_ver && sm_ver [ <NUM_LIT> ] == '3' && sm_ver [ <NUM_LIT> ] == '0' && sm_ver [ <NUM_LIT> ] == '\n' ) { warning_at ( input_location , <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ) ; fflush ( out ) ; ftruncate ( fileno ( out ) , <NUM_LIT> ) ; return ; } sm_ver2 = sm_ver ; version2 = version ; } } if ( func_ids && ( omp_requires & GOMP_REQUIRES_REVERSE_OFFLOAD ) != <NUM_LIT> ) { const char needle [ ] = <STR_LIT> ; fprintf ( out , <STR_LIT> , obj_count ++ ) ; fprintf ( out , <STR_LIT> ) ; for ( size_t i = <NUM_LIT> ; version2 [ i ] != '\0' && version2 [ i ] != '\n' ; i ++ ) fputc ( version2 [ i ] , out ) ; fprintf ( out , <STR_LIT> ) ; for ( size_t i = <NUM_LIT> ; version2 [ i ] != '\0' && sm_ver2 [ i ] != '\n' ; i ++ ) fputc ( sm_ver2 [ i ] , out ) ; fprintf ( out , <STR_LIT> ) ; size_t fidx = <NUM_LIT> ; for ( id = func_ids ; id ; id = id -> next ) { if ( ! endswith ( id -> ptx_name , <STR_LIT> ) && ! strstr ( id -> ptx_name , <STR_LIT> ) ) continue ; fprintf ( out , <STR_LIT> ) ; const char * p = input + file_idx [ fidx ] ; while ( true ) { p = strstr ( p , needle ) ; if ( ! p ) { fidx ++ ; if ( fidx >= file_cnt ) break ; p = input + file_idx [ fidx ] ; continue ; } p += strlen ( needle ) ; if ( ! startswith ( p , id -> ptx_name ) ) continue ; p += strlen ( id -> ptx_name ) ; if ( * p != '\n' ) continue ; p ++ ;"
GCC,nvptx,2,"Predict the next statement of this code snippet:
 <s> if ( ptx_name ) maybe_unlink ( ptx_name ) ;"
GCC,nvptx,3,"Predict the next statement of this code snippet:
 <s> if ( ptx_name ) maybe_unlink ( ptx_name ) ; if ( omp_requires_file ) maybe_unlink ( omp_requires_file ) ;"
GCC,nvptx,4,"Predict the next statement of this code snippet:
 <s> static unsigned alloc = <NUM_LIT> ; static Stmt * heap = <NUM_LIT> ; if ( ! alloc ) { alloc = <NUM_LIT> ; heap = XNEWVEC ( Stmt , alloc ) ; } Stmt * stmt = heap ++ ;"
GCC,nvptx,5,"Predict the next statement of this code snippet:
 <s> static unsigned alloc = <NUM_LIT> ; static Stmt * heap = <NUM_LIT> ; if ( ! alloc ) { alloc = <NUM_LIT> ; heap = XNEWVEC ( Stmt , alloc ) ; } Stmt * stmt = heap ++ ; alloc -- ; tokens -> space = <NUM_LIT> ; stmt -> next = <NUM_LIT> ; stmt -> vis = vis ; stmt -> tokens = tokens ; stmt -> len = end - tokens ;"
GCC,nvptx,6,"Predict the next statement of this code snippet:
 <s> const char * collect_gcc_options = getenv ( <STR_LIT> ) ; if ( ! collect_gcc_options ) fatal_error ( input_location , <STR_LIT> ) ; struct obstack argv_obstack ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , compiler ) ; obstack_ptr_grow ( & argv_obstack , infile ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , outfile ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; const char * * new_argv = XOBFINISH ( & argv_obstack , const char * * ) ; fork_execute ( new_argv [ <NUM_LIT> ] , CONST_CAST ( char * * , new_argv ) , true ) ; obstack_free ( & argv_obstack , NULL ) ;"
GCC,nvptx,7,"Predict the next statement of this code snippet:
 <s> if ( ! collect_gcc_options ) fatal_error ( input_location , <STR_LIT> ) ; struct obstack argv_obstack ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , compiler ) ; obstack_ptr_grow ( & argv_obstack , infile ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ;"
GCC,nvptx,8,"Predict the next statement of this code snippet:
 <s> size_t len = ( strlen ( gcc_path ) + <NUM_LIT> + strlen ( GCC_INSTALL_NAME ) + <NUM_LIT> ) ; char * driver = XALLOCAVEC ( char , len ) ; if ( strcmp ( gcc_exec , collect_gcc ) == <NUM_LIT> ) gcc_path = NULL ; int driver_used = <NUM_LIT> ; if ( gcc_path != NULL ) driver_used = sprintf ( driver , <STR_LIT> , gcc_path ) ; sprintf ( driver + driver_used , <STR_LIT> , GCC_INSTALL_NAME ) ; bool found = false ; if ( gcc_path == NULL ) found = true ; else if ( access_check ( driver , X_OK ) == <NUM_LIT> ) found = true ; else { driver = NULL ; char * * paths = NULL ; unsigned n_paths ; n_paths = parse_env_var ( getenv ( <STR_LIT> ) , & paths ) ; for ( unsigned i = <NUM_LIT> ; i < n_paths ; i ++ ) { len = strlen ( paths [ i ] ) + <NUM_LIT> + strlen ( GCC_INSTALL_NAME ) + <NUM_LIT> ; driver = XRESIZEVEC ( char , driver , len ) ; sprintf ( driver , <STR_LIT> , paths [ i ] , GCC_INSTALL_NAME ) ; if ( access_check ( driver , X_OK ) == <NUM_LIT> ) { found = true ; break ; } }"
GCC,nvptx,9,"Predict the next statement of this code snippet:
 <s> tok ++ ; } comment = alloc_comment ( start , tok ) ; comment -> vis |= V_prefix_comment ; } if ( tok -> kind == K_dotted ) { if ( is_keyword ( tok , <STR_LIT> ) || is_keyword ( tok , <STR_LIT> ) || is_keyword ( tok , <STR_LIT> ) ) { if ( comment ) append_stmt ( & decls , comment ) ; tok = parse_list_nosemi ( tok ) ; } else { unsigned vis = <NUM_LIT> ; const Token * def = <NUM_LIT> ; unsigned is_decl = <NUM_LIT> ; Token * start ; for ( start = tok ; tok -> kind && tok -> kind != '=' && tok -> kind != K_comment && tok -> kind != '{' && tok -> kind != ';' ; tok ++ ) { if ( is_keyword ( tok , <STR_LIT> ) || is_keyword ( tok , <STR_LIT> ) ) vis |= V_var ; else if ( is_keyword ( tok , <STR_LIT> ) || is_keyword ( tok , <STR_LIT> ) ) vis |= V_func ; else if ( is_keyword ( tok , <STR_LIT> ) ) vis |= V_global ; else if ( is_keyword ( tok , <STR_LIT> ) ) is_decl = <NUM_LIT> ; else if ( is_keyword ( tok , <STR_LIT> ) ) vis |= V_weak ; if ( tok -> kind == '(' ) { tok [ <NUM_LIT> ] . space = <NUM_LIT> ; tok [ <NUM_LIT> ] . space = <NUM_LIT> ; } else if ( tok -> kind == ')' && tok [ <NUM_LIT> ] . kind != ';' ) tok [ <NUM_LIT> ] . space = <NUM_LIT> ; if ( tok -> kind == K_symbol ) def = tok ;"
GCC,nvptx,10,"Predict the next statement of this code snippet:
 <s> tok [ <NUM_LIT> ] . space = <NUM_LIT> ; tok [ <NUM_LIT> ] . space = <NUM_LIT> ; } else if ( tok -> kind == ')' && tok [ <NUM_LIT> ] . kind != ';' ) tok [ <NUM_LIT> ] . space = <NUM_LIT> ; if ( tok -> kind == K_symbol ) def = tok ; } if ( ! tok -> kind ) { if ( comment ) append_stmt ( & fns , comment ) ; } else if ( tok -> kind == '{' || tok -> kind == K_comment ) { Stmt * stmt = alloc_stmt ( vis , start , tok , def ) ; if ( comment ) { append_stmt ( & fns , comment ) ; stmt -> vis |= V_prefix_comment ; } append_stmt ( & fns , stmt ) ; tok = parse_insn ( tok ) ; } else { int assign = tok -> kind == '=' ; tok ++ -> end = <NUM_LIT> ; if ( ( vis & V_mask ) == V_var && ! is_decl ) { Stmt * stmt = alloc_stmt ( vis , start , tok , def ) ; if ( comment ) { append_stmt ( & vars , comment ) ; stmt -> vis |= V_prefix_comment ; } append_stmt ( & vars , stmt ) ; if ( assign ) tok = parse_init ( tok ) ; } else { Stmt * stmt = alloc_stmt ( vis , start , tok , <NUM_LIT> ) ; if ( comment ) { append_stmt ( & decls , comment ) ; stmt -> vis |= V_prefix_comment ; } append_stmt ( & decls , stmt ) ; }"
GCC,nvptx,11,"Predict the next statement of this code snippet:
 <s> if ( tok [ - <NUM_LIT> ] . ptr [ <NUM_LIT> ] != '$' ) sym = tok - <NUM_LIT> ; tok [ - <NUM_LIT> ] . end = <NUM_LIT> ; s = V_label ; break ; case '@' : tok -> space = <NUM_LIT> ; if ( tok -> kind == '!' ) tok ++ ; if ( tok -> kind == K_symbol ) sym = tok ; tok ++ ; s = V_pred ; break ; default : for ( ; tok -> kind != ';' ; tok ++ ) { if ( tok -> kind == ',' ) tok [ <NUM_LIT> ] . space = <NUM_LIT> ; else if ( tok -> kind == K_symbol ) sym = tok ; } tok ++ -> end = <NUM_LIT> ; break ; } stmt = alloc_stmt ( s , start , tok , sym ) ; append_stmt ( & fns , stmt ) ; if ( ! tok [ - <NUM_LIT> ] . end && tok [ <NUM_LIT> ] . kind == K_comment ) { stmt -> vis |= V_no_eol ; stmt = alloc_comment ( tok , tok + <NUM_LIT> ) ; append_stmt ( & fns , stmt ) ; tok ++ ; }"
GCC,nvptx,12,"Predict the next statement of this code snippet:
 <s> while ( ( ++ tok ) -> kind == ',' ) ; tok [ - <NUM_LIT> ] . end = <NUM_LIT> ; Stmt * stmt = alloc_stmt ( V_dot , start , tok , <NUM_LIT> ) ;"
GCC,nvptx,13,"Predict the next statement of this code snippet:
 <s> write_stmts ( out , rev_stmts ( fns ) ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; for ( id_map * id = var_ids ; id ; id = id -> next , nvars ++ ) fprintf ( out , <STR_LIT> , id -> ptx_name , id -> next ? <STR_LIT> : <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; for ( id_map * id = func_ids ; id ; id = id -> next , nfuncs ++ ) fprintf ( out , <STR_LIT> , id -> ptx_name , id -> next ? <STR_LIT> : <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> <STR_LIT> , nvars , nfuncs ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> , GOMP_DEVICE_NVIDIA_PTX ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ;"
GCC,nvptx,14,"Predict the next statement of this code snippet:
 <s> unsigned int nvars = <NUM_LIT> , nfuncs = <NUM_LIT> ; do tok = parse_file ( tok ) ; while ( tok -> kind ) ; fprintf ( out , <STR_LIT> ) ; write_stmts ( out , rev_stmts ( decls ) ) ; write_stmts ( out , rev_stmts ( vars ) ) ; write_stmts ( out , rev_stmts ( fns ) ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; for ( id_map * id = var_ids ; id ; id = id -> next , nvars ++ ) fprintf ( out , <STR_LIT> , id -> ptx_name , id -> next ? <STR_LIT> : <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; for ( id_map * id = func_ids ; id ; id = id -> next , nfuncs ++ ) fprintf ( out , <STR_LIT> , id -> ptx_name , id -> next ? <STR_LIT> : <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> <STR_LIT> , nvars , nfuncs ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> , GOMP_DEVICE_NVIDIA_PTX ) ; fprintf ( out , <STR_LIT> ) ;"
GCC,nvptx,15,"Predict the next statement of this code snippet:
 <s> char * buffer ; if ( ! fseek ( stream , <NUM_LIT> , SEEK_END ) ) { long s = ftell ( stream ) ; if ( s >= <NUM_LIT> ) alloc = s + <NUM_LIT> ; fseek ( stream , <NUM_LIT> , SEEK_SET ) ; } buffer = XNEWVEC ( char , alloc ) ; for ( ; ; ) { size_t n = fread ( buffer + base , <NUM_LIT> , alloc - base - <NUM_LIT> , stream ) ; if ( ! n ) break ; base += n ; if ( base + <NUM_LIT> == alloc ) { alloc *= <NUM_LIT> ; buffer = XRESIZEVEC ( char , buffer , alloc ) ; }"
GCC,nvptx,16,"Predict the next statement of this code snippet:
 <s> Stmt * prev = <NUM_LIT> ; Stmt * next ; while ( stmt ) { next = stmt -> next ; stmt -> next = prev ; prev = stmt ; stmt = next ; }"
GCC,nvptx,17,"Predict the next statement of this code snippet:
 <s> else break ; } break ; case '""' : kind = K_string ; while ( * ptr ) if ( * ptr == '""' ) { ptr ++ ; break ; } else if ( * ptr ++ == '\\' ) ptr ++ ; break ; case '.' : if ( * ptr < '0' || * ptr > '9' ) { kind = K_dotted ; ws = not_comment ; goto ident ; } case '0' ... '9' : kind = K_number ; goto ident ; break ; case '$' : case '%' : kind = K_ident ; goto ident ; case 'a' ... 'z' : case 'A' ... 'Z' : case '_' : kind = K_symbol ; ident : for ( ; * ptr ; ptr ++ ) { if ( * ptr >= 'A' && * ptr <= 'Z' ) continue ; if ( * ptr >= 'a' && * ptr <= 'z' ) continue ; if ( * ptr >= '0' && * ptr <= '9' ) continue ; if ( * ptr == '_' || * ptr == '$' ) continue ; if ( * ptr == '.' && kind != K_dotted ) continue ; if ( ( * ptr == '+' || * ptr == '-' ) && kind == K_number && ( ptr [ - <NUM_LIT> ] == 'e' || ptr [ - <NUM_LIT> ] == 'E' || ptr [ - <NUM_LIT> ] == 'p' || ptr [ - <NUM_LIT> ] == 'P' ) ) continue ; break ; } if ( * ptr == ':' ) { ptr ++ ; kind = K_label ; } break ; } if ( alloc == num ) { alloc *= <NUM_LIT> ; toks = XRESIZEVEC ( Token , toks , alloc ) ; } Token * tok = toks + num ; tok -> kind = kind ; tok -> space = ws ; tok -> end = <NUM_LIT> ; tok -> ptr = base ; tok -> len = ptr - base - in_comment ; in_comment &= <NUM_LIT> ; not_comment = kind != K_comment ; if ( eol && num ) tok [ - <NUM_LIT> ] . end = <NUM_LIT> ; if ( ! kind ) break ;"
GCC,nvptx,18,"Predict the next statement of this code snippet:
 <s> eol = in_comment ; in_comment = <NUM_LIT> ; for ( ; * ptr ; ptr ++ ) { if ( * ptr == '\n' ) { ptr ++ ; break ; } if ( ptr [ <NUM_LIT> ] == '*' && ptr [ <NUM_LIT> ] == '/' ) { in_comment = <NUM_LIT> ; ptr += <NUM_LIT> ; break ; } } kind = K_comment ; } else break ; } break ; case '""' : kind = K_string ; while ( * ptr ) if ( * ptr == '""' ) { ptr ++ ; break ; } else if ( * ptr ++ == '\\' ) ptr ++ ; break ; case '.' : if ( * ptr < '0' || * ptr > '9' ) { kind = K_dotted ; ws = not_comment ; goto ident ; } case '0' ... '9' : kind = K_number ; goto ident ; break ; case '$' : case '%' : kind = K_ident ; goto ident ; case 'a' ... 'z' : case 'A' ... 'Z' : case '_' : kind = K_symbol ; ident : for ( ; * ptr ; ptr ++ ) { if ( * ptr >= 'A' && * ptr <= 'Z' ) continue ; if ( * ptr >= 'a' && * ptr <= 'z' ) continue ; if ( * ptr >= '0' && * ptr <= '9' ) continue ; if ( * ptr == '_' || * ptr == '$' ) continue ; if ( * ptr == '.' && kind != K_dotted ) continue ; if ( ( * ptr == '+' || * ptr == '-' ) && kind == K_number && ( ptr [ - <NUM_LIT> ] == 'e' || ptr [ - <NUM_LIT> ] == 'E' || ptr [ - <NUM_LIT> ] == 'p' || ptr [ - <NUM_LIT> ] == 'P' ) ) continue ; break ; } if ( * ptr == ':' ) { ptr ++ ; kind = K_label ; } break ; } if ( alloc == num ) { alloc *= <NUM_LIT> ; toks = XRESIZEVEC ( Token , toks , alloc ) ; } Token * tok = toks + num ; tok -> kind = kind ; tok -> space = ws ; tok -> end = <NUM_LIT> ;"
GCC,nvptx,19,"Predict the next statement of this code snippet:
 <s> void tool_cleanup ( bool ) {"
GCC,nvptx,20,"Predict the next statement of this code snippet:
 <s> void tool_cleanup ( bool ) {"
GCC,nvptx,21,"Predict the next statement of this code snippet:
 <s> static void write_stmt ( FILE * out , const Stmt * stmt ) { if ( ( stmt -> vis & V_mask ) != V_comment ) { write_tokens ( out , stmt -> tokens , stmt -> len , ( stmt -> vis & V_mask ) == V_pred ) ;"
GCC,nvptx,22,"Predict the next statement of this code snippet:
 <s> if ( tok -> space ) fputc ( ' ' , out ) ; switch ( tok -> kind ) { case K_string : { const char * c = tok -> ptr + <NUM_LIT> ; size_t len = tok -> len - <NUM_LIT> ; fputs ( <STR_LIT> , out ) ; while ( len ) { const char * bs = ( const char * ) memchr ( c , '\\' , len ) ; size_t l = bs ? bs - c : len ; fprintf ( out , <STR_LIT> , ( int ) l , c ) ; len -= l ;"
GCC,nvptx,23,"Predict the next statement of this code snippet:
 <s> fputs ( <STR_LIT> , out ) ; for ( ; len -- ; toks ++ ) write_token ( out , toks ) ;"
GCC,nvptx,24,"Predict the next statement of this code snippet:
 <s> for ( ; len -- ; toks ++ ) write_token ( out , toks ) ; if ( spc ) fputs ( <STR_LIT> , out ) ;"
GCC,nvptx,25,"Predict the next statement of this code snippet:
 <s> const char * gcc_path = dirname ( ASTRDUP ( collect_gcc ) ) ; const char * gcc_exec = basename ( ASTRDUP ( collect_gcc ) ) ; size_t len = ( strlen ( gcc_path ) + <NUM_LIT> + strlen ( GCC_INSTALL_NAME ) + <NUM_LIT> ) ; char * driver = XALLOCAVEC ( char , len ) ; if ( strcmp ( gcc_exec , collect_gcc ) == <NUM_LIT> ) gcc_path = NULL ; int driver_used = <NUM_LIT> ; if ( gcc_path != NULL ) driver_used = sprintf ( driver , <STR_LIT> , gcc_path ) ; sprintf ( driver + driver_used , <STR_LIT> , GCC_INSTALL_NAME ) ; bool found = false ; if ( gcc_path == NULL ) found = true ; else if ( access_check ( driver , X_OK ) == <NUM_LIT> ) found = true ; else { driver = NULL ; char * * paths = NULL ; unsigned n_paths ; n_paths = parse_env_var ( getenv ( <STR_LIT> ) , & paths ) ; for ( unsigned i = <NUM_LIT> ; i < n_paths ; i ++ ) { len = strlen ( paths [ i ] ) + <NUM_LIT> + strlen ( GCC_INSTALL_NAME ) + <NUM_LIT> ; driver = XRESIZEVEC ( char , driver , len ) ; sprintf ( driver , <STR_LIT> , paths [ i ] , GCC_INSTALL_NAME ) ; if ( access_check ( driver , X_OK ) == <NUM_LIT> ) { found = true ; break ; } } free_array_of_ptrs ( ( void * * ) paths , n_paths ) ; } if ( ! found ) fatal_error ( input_location , <STR_LIT> , GCC_INSTALL_NAME ) ; expandargv ( & argc , & argv ) ; bool fopenmp = false ; for ( int i = <NUM_LIT> ; i < argc ; i ++ ) { if ( strncmp ( argv [ i ] , STR , strlen ( STR ) ) == <NUM_LIT> ) { if ( strcmp ( argv [ i ] + strlen ( STR ) , <STR_LIT> ) == <NUM_LIT> ) offload_abi = OFFLOAD_ABI_LP64 ; else if ( strcmp ( argv [ i ] + strlen ( STR ) , <STR_LIT> ) == <NUM_LIT> ) offload_abi = OFFLOAD_ABI_ILP32 ; else fatal_error ( input_location , <STR_LIT> STR ) ; } else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) fopenmp = true ; else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) save_temps = true ; else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) verbose = true ; } struct obstack argv_obstack ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , driver ) ; if ( save_temps ) obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ;"
GCC,nvptx,26,"Predict the next statement of this code snippet:
 <s> case '\n' : fprintf ( out , <STR_LIT> ) ; while ( strncmp ( input + i , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { i += <NUM_LIT> ; if ( strncmp ( input + i , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) record_id ( input + i + <NUM_LIT> , & vars_tail ) ; else if ( strncmp ( input + i , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) record_id ( input + i + <NUM_LIT> , & funcs_tail ) ; else abort ( ) ; while ( input [ i ++ ] != '\n' ) continue ; } continue ; case '""' : case '\\' : putc ( '\\' , out ) ; break ; default : break ; } putc ( c , out ) ; } fprintf ( out , <STR_LIT> ) ; } fprintf ( out , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ) ; for ( comma = <STR_LIT> , ix = <NUM_LIT> ; ix != obj_count ; comma = <STR_LIT> , ix ++ ) fprintf ( out , <STR_LIT> , comma , ix , ix ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; for ( comma = <STR_LIT> , id = var_ids ; id ; comma = <STR_LIT> , id = id -> next ) fprintf ( out , <STR_LIT> , comma , id -> ptx_name ) ;"
GCC,nvptx,27,"Predict the next statement of this code snippet:
 <s> struct stat st ; if ( stat ( name , & st ) < <NUM_LIT> || S_ISDIR ( st . st_mode ) ) return - <NUM_LIT> ; } return access ( name , mode ) ;"
GCC,nvptx,28,"Predict the next statement of this code snippet:
 <s> obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( & argv_obstack , infile ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , outfile ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; const char * * new_argv = XOBFINISH ( & argv_obstack , const char * * ) ; fork_execute ( new_argv [ <NUM_LIT> ] , CONST_CAST ( char * * , new_argv ) , true , <STR_LIT> ) ;"
GCC,nvptx,29,"Predict the next statement of this code snippet:
 <s> for ( i = <NUM_LIT> ; i < n ; i ++ ) { if ( ! ptr [ i ] ) break ; free ( ptr [ i ] ) ; } free ( ptr ) ; return ;"
GCC,nvptx,30,"Predict the next statement of this code snippet:
 <s> void maybe_unlink ( const char * file ) { if ( ! save_temps ) {"
GCC,nvptx,31,"Predict the next statement of this code snippet:
 <s> tool_cleanup ( false ) ;"
GCC,nvptx,32,"Predict the next statement of this code snippet:
 <s> char * * values ; unsigned num = <NUM_LIT> , i ; curval = strchr ( str , ':' ) ; while ( curval ) { num ++ ; curval = strchr ( curval + <NUM_LIT> , ':' ) ; } values = ( char * * ) xmalloc ( num * sizeof ( char * ) ) ; curval = str ; nextval = strchr ( curval , ':' ) ; if ( nextval == NULL ) nextval = strchr ( curval , '\0' ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) {"
GCC,nvptx,33,"Predict the next statement of this code snippet:
 <s> while ( input [ i ++ ] != '\n' ) continue ; } continue ; case '""' : case '\\' : putc ( '\\' , out ) ; break ; default : break ; } putc ( c , out ) ; } fprintf ( out , <STR_LIT> ) ; } fprintf ( out , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ) ; for ( comma = <STR_LIT> , ix = <NUM_LIT> ; ix != obj_count ; comma = <STR_LIT> , ix ++ ) fprintf ( out , <STR_LIT> , comma , ix , ix ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> ) ; for ( comma = <STR_LIT> , id = var_ids ; id ; comma = <STR_LIT> , id = id -> next ) fprintf ( out , <STR_LIT> , comma , id -> ptx_name ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , GOMP_DIM_MAX ) ; for ( comma = <STR_LIT> , id = func_ids ; id ; comma = <STR_LIT> , id = id -> next ) fprintf ( out , <STR_LIT> , comma , id -> ptx_name ) ; fprintf ( out , <STR_LIT> ) ; fprintf ( out , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ) ;"
GCC,nvptx,34,"Predict the next statement of this code snippet:
 <s> if ( ! fseek ( stream , <NUM_LIT> , SEEK_END ) ) { long s = ftell ( stream ) ; if ( s >= <NUM_LIT> ) alloc = s + <NUM_LIT> ; fseek ( stream , <NUM_LIT> , SEEK_SET ) ; } buffer = XNEWVEC ( char , alloc ) ; for ( ; ; ) { size_t n = fread ( buffer + base , <NUM_LIT> , alloc - base - <NUM_LIT> , stream ) ; if ( ! n ) break ; base += n ; if ( base + <NUM_LIT> == alloc ) { alloc *= <NUM_LIT> ;"
GCC,nvptx,35,"Predict the next statement of this code snippet:
 <s> } buffer = XNEWVEC ( char , alloc ) ; for ( ; ; ) { size_t n = fread ( buffer + base , <NUM_LIT> , alloc - base - <NUM_LIT> , stream ) ; if ( ! n ) break ; base += n ; if ( base + <NUM_LIT> == alloc ) { alloc *= <NUM_LIT> ; buffer = XRESIZEVEC ( char , buffer , alloc ) ; } } buffer [ base ] = <NUM_LIT> ; * plen = base ;"
GCC,nvptx,36,"Predict the next statement of this code snippet:
 <s> if ( ptx_name ) maybe_unlink ( ptx_name ) ;"
GCC,nvptx,37,"Predict the next statement of this code snippet:
 <s> if ( ptx_name ) maybe_unlink ( ptx_name ) ;"
GCC,nvptx,38,"Predict the next statement of this code snippet:
 <s> if ( verbose ) fprintf ( stderr , <STR_LIT> , string ) ; putenv ( CONST_CAST ( char * , string ) ) ;"
GCC,nvptx,39,"Predict the next statement of this code snippet:
 <s> putenv ( CONST_CAST ( char * , string ) ) ;"
GCC,nvptx,40,"Predict the next statement of this code snippet:
 <s> if ( TARGET_UNIFORM_SIMT ) cpp_define ( parse_in , <STR_LIT> ) ; const char * ptx_sm = NULL ; { \ if ( TARGET_SM ## XX ) \ ptx_sm = <STR_LIT> # XX <STR_LIT> ; \ } cpp_define ( parse_in , ptx_sm ) ; { unsigned major = ptx_version_to_number ( ( ptx_version ) ptx_version_option , true ) ; unsigned minor = ptx_version_to_number ( ( ptx_version ) ptx_version_option , false ) ; cpp_define_formatted ( parse_in , <STR_LIT> , major ) ;"
GCC,nvptx,41,"Predict the next statement of this code snippet:
 <s> if ( TARGET_UNIFORM_SIMT ) cpp_define ( parse_in , <STR_LIT> ) ; const char * ptx_sm = NULL ; { \ if ( TARGET_SM ## XX ) \ ptx_sm = <STR_LIT> # XX <STR_LIT> ; \ } cpp_define ( parse_in , ptx_sm ) ; { unsigned major = ptx_version_to_number ( ( ptx_version ) ptx_version_option , true ) ; unsigned minor = ptx_version_to_number ( ( ptx_version ) ptx_version_option , false ) ;"
GCC,nvptx,42,"Predict the next statement of this code snippet:
 <s> argno = write_arg_type ( s , <NUM_LIT> , argno , type , prototyped ) ; } if ( stdarg_p ( fntype ) ) argno = write_arg_type ( s , ARG_POINTER_REGNUM , argno , ptr_type_node , true ) ; if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> has_chain ) write_arg_type ( s , STATIC_CHAIN_REGNUM , DECL_STATIC_CHAIN ( decl ) ? argno : - <NUM_LIT> , ptr_type_node , true ) ; fprintf ( file , <STR_LIT> , s . str ( ) . c_str ( ) ) ; if ( ! crtl -> is_leaf ) crtl -> is_leaf = leaf_function_p ( ) ; HOST_WIDE_INT sz = get_frame_size ( ) ; bool need_frameptr = sz || cfun -> machine -> has_chain ; int alignment = crtl -> stack_alignment_needed / BITS_PER_UNIT ; if ( ! TARGET_SOFT_STACK ) { if ( cfun -> machine -> has_varadic ) init_frame ( file , STACK_POINTER_REGNUM , UNITS_PER_WORD , crtl -> outgoing_args_size ) ; if ( need_frameptr ) init_frame ( file , FRAME_POINTER_REGNUM , alignment , ROUND_UP ( sz , GET_MODE_SIZE ( DImode ) ) ) ; } else if ( need_frameptr || cfun -> machine -> has_varadic || cfun -> calls_alloca || ( cfun -> machine -> has_simtreg && ! crtl -> is_leaf ) ) init_softstack_frame ( file , alignment , sz ) ; if ( cfun -> machine -> has_simtreg ) { unsigned HOST_WIDE_INT & simtsz = cfun -> machine -> simt_stack_size ; unsigned HOST_WIDE_INT & align = cfun -> machine -> simt_stack_align ; align = MAX ( align , GET_MODE_SIZE ( DImode ) ) ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) simtsz = HOST_WIDE_INT_M1U ; if ( simtsz == HOST_WIDE_INT_M1U ) simtsz = nvptx_softstack_size ; if ( cfun -> machine -> has_softstack ) simtsz += POINTER_SIZE / <NUM_LIT> ; simtsz = ROUND_UP ( simtsz , GET_MODE_SIZE ( DImode ) ) ; if ( align > GET_MODE_SIZE ( DImode ) ) simtsz += align - GET_MODE_SIZE ( DImode ) ; if ( simtsz ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , simtsz ) ; } if ( cfun -> machine -> red_partition ) regno_reg_rtx [ REGNO ( cfun -> machine -> red_partition ) ] = cfun -> machine -> red_partition ; int maxregs = max_reg_num ( ) ; for ( int i = LAST_VIRTUAL_REGISTER + <NUM_LIT> ; i < maxregs ; i ++ ) { if ( regno_reg_rtx [ i ] != const0_rtx ) { machine_mode mode = PSEUDO_REGNO_MODE ( i ) ; machine_mode split = maybe_split_mode ( mode ) ;"
GCC,nvptx,43,"Predict the next statement of this code snippet:
 <s> if ( ! TARGET_SOFT_STACK ) { if ( cfun -> machine -> has_varadic ) init_frame ( file , STACK_POINTER_REGNUM , UNITS_PER_WORD , crtl -> outgoing_args_size ) ; if ( need_frameptr ) init_frame ( file , FRAME_POINTER_REGNUM , alignment , ROUND_UP ( sz , GET_MODE_SIZE ( DImode ) ) ) ; } else if ( need_frameptr || cfun -> machine -> has_varadic || cfun -> calls_alloca || ( cfun -> machine -> has_simtreg && ! crtl -> is_leaf ) ) init_softstack_frame ( file , alignment , sz ) ; if ( cfun -> machine -> has_simtreg ) { unsigned HOST_WIDE_INT & simtsz = cfun -> machine -> simt_stack_size ; unsigned HOST_WIDE_INT & align = cfun -> machine -> simt_stack_align ; align = MAX ( align , GET_MODE_SIZE ( DImode ) ) ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) simtsz = HOST_WIDE_INT_M1U ; if ( simtsz == HOST_WIDE_INT_M1U ) simtsz = nvptx_softstack_size ; if ( cfun -> machine -> has_softstack ) simtsz += POINTER_SIZE / <NUM_LIT> ; simtsz = ROUND_UP ( simtsz , GET_MODE_SIZE ( DImode ) ) ; if ( align > GET_MODE_SIZE ( DImode ) ) simtsz += align - GET_MODE_SIZE ( DImode ) ; if ( simtsz ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , simtsz ) ; } if ( cfun -> machine -> red_partition ) regno_reg_rtx [ REGNO ( cfun -> machine -> red_partition ) ] = cfun -> machine -> red_partition ; int maxregs = max_reg_num ( ) ; for ( int i = LAST_VIRTUAL_REGISTER + <NUM_LIT> ; i < maxregs ; i ++ ) { if ( regno_reg_rtx [ i ] != const0_rtx ) { machine_mode mode = PSEUDO_REGNO_MODE ( i ) ; machine_mode split = maybe_split_mode ( mode ) ; if ( split_mode_p ( mode ) ) mode = split ; fprintf ( file , <STR_LIT> , nvptx_ptx_type_from_mode ( mode , true ) ) ; output_reg ( file , i , split , - <NUM_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } }"
GCC,nvptx,44,"Predict the next statement of this code snippet:
 <s> if ( ! CONST_INT_P ( cpl ) ) { error_at ( EXPR_LOCATION ( exp ) , <STR_LIT> ) ; return const0_rtx ; } pred = gen_reg_rtx ( BImode ) ; if ( ! REG_P ( redop ) ) redop = copy_to_mode_reg ( SImode , redop ) ; emit_insn ( gen_rtx_SET ( pred , gen_rtx_NE ( BImode , redop , GEN_INT ( <NUM_LIT> ) ) ) ) ; redop = pred ; rtx pat ; switch ( code ) { case NVPTX_BUILTIN_BAR_RED_AND : dst = gen_reg_rtx ( BImode ) ; pat = gen_nvptx_barred_and ( dst , bar , nthr , cpl , redop ) ; break ; case NVPTX_BUILTIN_BAR_RED_OR : dst = gen_reg_rtx ( BImode ) ; pat = gen_nvptx_barred_or ( dst , bar , nthr , cpl , redop ) ; break ; case NVPTX_BUILTIN_BAR_RED_POPC : dst = gen_reg_rtx ( SImode ) ; pat = gen_nvptx_barred_popc ( dst , bar , nthr , cpl , redop ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( pat ) ; if ( GET_MODE ( dst ) == BImode ) { rtx tmp = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_NE ( mode , dst , GEN_INT ( <NUM_LIT> ) ) ) ) ;"
GCC,nvptx,45,"Predict the next statement of this code snippet:
 <s> case NVPTX_BUILTIN_SHUFFLE : case NVPTX_BUILTIN_SHUFFLELL : return nvptx_expand_shuffle ( exp , target , mode , ignore ) ; case NVPTX_BUILTIN_WORKER_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , false ) ; case NVPTX_BUILTIN_VECTOR_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , true ) ; case NVPTX_BUILTIN_CMP_SWAP : case NVPTX_BUILTIN_CMP_SWAPLL : return nvptx_expand_cmp_swap ( exp , target , mode , ignore ) ;"
GCC,nvptx,46,"Predict the next statement of this code snippet:
 <s> tree lhs = gimple_call_lhs ( call ) ; tree ref_to_res = gimple_call_arg ( call , <NUM_LIT> ) ; tree var = gimple_call_arg ( call , <NUM_LIT> ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; enum tree_code op = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; gimple_seq seq = NULL ; tree r = NULL_TREE ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR && oa -> vector_length == PTX_WARP_SIZE ) { for ( int shfl = PTX_WARP_SIZE / <NUM_LIT> ; shfl > <NUM_LIT> ; shfl = shfl >> <NUM_LIT> ) { tree other_var = make_ssa_name ( TREE_TYPE ( var ) ) ; nvptx_generate_vector_shuffle ( gimple_location ( call ) , other_var , var , shfl , & seq ) ; r = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( r , fold_build2 ( op , TREE_TYPE ( var ) , var , other_var ) , & seq ) ; var = r ;"
GCC,nvptx,47,"Predict the next statement of this code snippet:
 <s> DEF ( MEMBAR_CTA , <STR_LIT> , ( VOID , VOID , NULL_TREE ) ) ; DEF ( BAR_RED_AND , <STR_LIT> , ( UINT , UINT , UINT , UINT , UINT , NULL_TREE ) ) ; DEF ( BAR_RED_OR , <STR_LIT> , ( UINT , UINT , UINT , UINT , UINT , NULL_TREE ) ) ; DEF ( BAR_RED_POPC , <STR_LIT> , ( UINT , UINT , UINT , UINT , UINT , NULL_TREE ) ) ;"
GCC,nvptx,48,"Predict the next statement of this code snippet:
 <s> flag_var_tracking = <NUM_LIT> ; if ( nvptx_optimize < <NUM_LIT> ) nvptx_optimize = optimize > <NUM_LIT> ; declared_fndecls_htab = hash_table < tree_hasher > :: create_ggc ( <NUM_LIT> ) ; needed_fndecls_htab = hash_table < tree_hasher > :: create_ggc ( <NUM_LIT> ) ; declared_libfuncs_htab = hash_table < declared_libfunc_hasher > :: create_ggc ( <NUM_LIT> ) ; oacc_bcast_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( oacc_bcast_sym , DATA_AREA_SHARED ) ; oacc_bcast_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; oacc_bcast_partition = <NUM_LIT> ; worker_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( worker_red_sym , DATA_AREA_SHARED ) ; worker_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; vector_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( vector_red_sym , DATA_AREA_SHARED ) ; vector_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ;"
GCC,nvptx,49,"Predict the next statement of this code snippet:
 <s> declared_libfuncs_htab = hash_table < declared_libfunc_hasher > :: create_ggc ( <NUM_LIT> ) ; oacc_bcast_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( oacc_bcast_sym , DATA_AREA_SHARED ) ; oacc_bcast_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; oacc_bcast_partition = <NUM_LIT> ; worker_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( worker_red_sym , DATA_AREA_SHARED ) ; worker_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; vector_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( vector_red_sym , DATA_AREA_SHARED ) ; vector_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; vector_red_partition = <NUM_LIT> ; gang_private_shared_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( gang_private_shared_sym , DATA_AREA_SHARED ) ; gang_private_shared_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; diagnose_openacc_conflict ( TARGET_GOMP , <STR_LIT> ) ; diagnose_openacc_conflict ( TARGET_SOFT_STACK , <STR_LIT> ) ; diagnose_openacc_conflict ( TARGET_UNIFORM_SIMT , <STR_LIT> ) ;"
GCC,nvptx,50,"Predict the next statement of this code snippet:
 <s> if ( is_defn ) write_fn_proto_1 ( s , false , name , decl , force_public ) ; write_fn_proto_1 ( s , is_defn , name , decl , force_public ) ; if ( replaced_dots ) XDELETE ( replaced_dots ) ;"
GCC,nvptx,51,"Predict the next statement of this code snippet:
 <s> s << ( write_as_kernel ( DECL_ATTRIBUTES ( decl ) ) ? <STR_LIT> : <STR_LIT> ) ; tree fntype = TREE_TYPE ( decl ) ; tree result_type = TREE_TYPE ( fntype ) ; int not_atomic_weak_arg = - <NUM_LIT> ; if ( DECL_BUILT_IN_CLASS ( decl ) == BUILT_IN_NORMAL ) switch ( DECL_FUNCTION_CODE ( decl ) ) { case BUILT_IN_ATOMIC_COMPARE_EXCHANGE_1 : case BUILT_IN_ATOMIC_COMPARE_EXCHANGE_2 : case BUILT_IN_ATOMIC_COMPARE_EXCHANGE_4 : case BUILT_IN_ATOMIC_COMPARE_EXCHANGE_8 : case BUILT_IN_ATOMIC_COMPARE_EXCHANGE_16 : not_atomic_weak_arg = <NUM_LIT> ; break ; default : break ; } bool return_in_mem = write_return_type ( s , true , result_type ) ; s << name ; int argno = <NUM_LIT> ; if ( return_in_mem ) argno = write_arg_type ( s , - <NUM_LIT> , argno , ptr_type_node , true ) ; tree args = TYPE_ARG_TYPES ( fntype ) ; bool prototyped = true ; if ( ! args ) { args = DECL_ARGUMENTS ( decl ) ; prototyped = false ; } for ( ; args ; args = TREE_CHAIN ( args ) , not_atomic_weak_arg -- ) {"
GCC,nvptx,52,"Predict the next statement of this code snippet:
 <s> static void begin_decl_field ( void ) { if ( decl_offset == decl_chunk_size ) fprintf ( asm_out_file , <STR_LIT> ) ; else fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,nvptx,53,"Predict the next statement of this code snippet:
 <s> static void begin_decl_field ( void ) { if ( decl_offset == decl_chunk_size ) fprintf ( asm_out_file , <STR_LIT> ) ; else fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,nvptx,54,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> , is_public ? <STR_LIT> : <STR_LIT> ) ; assemble_name_raw ( file , name ) ; fputc ( '\n' , file ) ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ;"
GCC,nvptx,55,"Predict the next statement of this code snippet:
 <s> else if ( mode == TImode ) { * pmode = DImode ; return <NUM_LIT> ; } return <NUM_LIT> ;"
GCC,nvptx,56,"Predict the next statement of this code snippet:
 <s> addr_space_t nvptx_addr_space_from_address ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) != SYMBOL_REF ) return ADDR_SPACE_GENERIC ; tree decl = SYMBOL_REF_DECL ( addr ) ; if ( decl == NULL_TREE || TREE_CODE ( decl ) == FUNCTION_DECL ) return ADDR_SPACE_GENERIC ; bool is_const = ( CONSTANT_CLASS_P ( decl ) || TREE_CODE ( decl ) == CONST_DECL || TREE_READONLY ( decl ) ) ; if ( is_const ) return ADDR_SPACE_CONST ; return ADDR_SPACE_GLOBAL ;"
GCC,nvptx,57,"Predict the next statement of this code snippet:
 <s> bool is_const = ( CONSTANT_CLASS_P ( decl ) || TREE_CODE ( decl ) == CONST_DECL || TREE_READONLY ( decl ) ) ; if ( is_const ) return ADDR_SPACE_CONST ;"
GCC,nvptx,58,"Predict the next statement of this code snippet:
 <s> tree type = TREE_TYPE ( exp ) ; init_output_initializer ( file , name , type , false ) ; fprintf ( file , <STR_LIT> , TYPE_ALIGN ( TREE_TYPE ( exp ) ) / BITS_PER_UNIT , decl_chunk_size * BITS_PER_UNIT ) ;"
GCC,nvptx,59,"Predict the next statement of this code snippet:
 <s> if ( decl_offset != <NUM_LIT> ) { if ( ! object_finished && decl_offset % decl_chunk_size != <NUM_LIT> ) nvptx_assemble_value ( <NUM_LIT> , decl_chunk_size ) ; fprintf ( asm_out_file , <STR_LIT> ) ; }"
GCC,nvptx,60,"Predict the next statement of this code snippet:
 <s> output_address ( x ) ; fprintf ( asm_out_file , <STR_LIT> ) ; } if ( off != <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , off ) ; return true ; } HOST_WIDE_INT val ; switch ( GET_CODE ( x ) ) { case CONST_INT : val = INTVAL ( x ) ; break ; case CONST_DOUBLE : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } nvptx_assemble_value ( val , size ) ; return true ;"
GCC,nvptx,61,"Predict the next statement of this code snippet:
 <s> } if ( off != <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , off ) ; return true ; } HOST_WIDE_INT val ; switch ( GET_CODE ( x ) ) { case CONST_INT : val = INTVAL ( x ) ; break ; case CONST_DOUBLE : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } nvptx_assemble_value ( val , size ) ; return true ;"
GCC,nvptx,62,"Predict the next statement of this code snippet:
 <s> assemble_name_raw ( file , name ) ; fputs ( <STR_LIT> , file ) ; HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; fprintf ( file , <STR_LIT> , section ) ; assemble_name_raw ( file , name ) ; if ( size > <NUM_LIT> ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , size ) ; fprintf ( file , <STR_LIT> ) ;"
GCC,nvptx,63,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT mask = <NUM_LIT> ; mask <<= this_part * BITS_PER_UNIT - <NUM_LIT> ; val_part = val & ( mask - <NUM_LIT> ) ; init_part |= val_part << ( BITS_PER_UNIT * chunk_offset ) ; val >>= BITS_PER_UNIT * this_part ;"
GCC,nvptx,64,"Predict the next statement of this code snippet:
 <s> if ( arg == pc_rtx ) return ; rtx_expr_list * args_so_far = cfun -> machine -> call_args ;"
GCC,nvptx,65,"Predict the next statement of this code snippet:
 <s> void nvptx_declare_object_name ( FILE * file , const char * name , const_tree decl ) { if ( decl && DECL_SIZE ( decl ) ) { tree type = TREE_TYPE ( decl ) ; unsigned HOST_WIDE_INT size ; init_output_initializer ( file , name , type , TREE_PUBLIC ( decl ) ) ; size = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; const char * section = nvptx_section_for_decl ( decl ) ; fprintf ( file , <STR_LIT> , TREE_PUBLIC ( decl ) ? <STR_LIT> : <STR_LIT> , section , DECL_ALIGN ( decl ) / BITS_PER_UNIT , decl_chunk_size * BITS_PER_UNIT ) ; assemble_name ( file , name ) ;"
GCC,nvptx,66,"Predict the next statement of this code snippet:
 <s> static void nvptx_end_call_args ( void ) {"
GCC,nvptx,67,"Predict the next statement of this code snippet:
 <s> } } if ( cfun -> machine -> funtype && ( TREE_CODE ( cfun -> machine -> funtype ) == FUNCTION_TYPE || TREE_CODE ( cfun -> machine -> funtype ) == METHOD_TYPE ) && stdarg_p ( cfun -> machine -> funtype ) ) { has_varargs = true ; cfun -> machine -> has_call_with_varargs = true ; } vec = rtvec_alloc ( nargs + <NUM_LIT> + ( has_varargs ? <NUM_LIT> : <NUM_LIT> ) ) ; pat = gen_rtx_PARALLEL ( VOIDmode , vec ) ; if ( has_varargs ) { rtx this_arg = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_move_insn ( this_arg , stack_pointer_rtx ) ; else emit_move_insn ( this_arg , stack_pointer_rtx ) ; XVECEXP ( pat , <NUM_LIT> , nargs + <NUM_LIT> ) = gen_rtx_USE ( VOIDmode , this_arg ) ; } int i ; rtx arg ; for ( i = <NUM_LIT> , arg = cfun -> machine -> call_args ; arg ; arg = XEXP ( arg , <NUM_LIT> ) , i ++ ) { rtx this_arg = XEXP ( arg , <NUM_LIT> ) ; XVECEXP ( pat , <NUM_LIT> , i ) = gen_rtx_USE ( VOIDmode , this_arg ) ; } rtx tmp_retval = retval ; t = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; if ( retval != NULL_RTX ) { if ( ! nvptx_register_operand ( retval , GET_MODE ( retval ) ) ) tmp_retval = gen_reg_rtx ( GET_MODE ( retval ) ) ; t = gen_rtx_SET ( VOIDmode , tmp_retval , t ) ; } XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) = t ; if ( ! REG_P ( callee ) && ( decl_type == NULL_TREE || ( external_decl && TYPE_ARG_TYPES ( decl_type ) == NULL_TREE ) ) ) { rtx * slot = declared_libfuncs_htab -> find_slot ( callee , INSERT ) ; if ( * slot == NULL ) { * slot = callee ;"
GCC,nvptx,68,"Predict the next statement of this code snippet:
 <s> if ( cfun -> machine -> funtype && ( TREE_CODE ( cfun -> machine -> funtype ) == FUNCTION_TYPE || TREE_CODE ( cfun -> machine -> funtype ) == METHOD_TYPE ) && stdarg_p ( cfun -> machine -> funtype ) ) { has_varargs = true ; cfun -> machine -> has_call_with_varargs = true ; } vec = rtvec_alloc ( nargs + <NUM_LIT> + ( has_varargs ? <NUM_LIT> : <NUM_LIT> ) ) ; pat = gen_rtx_PARALLEL ( VOIDmode , vec ) ; if ( has_varargs ) { rtx this_arg = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_move_insn ( this_arg , stack_pointer_rtx ) ; else emit_move_insn ( this_arg , stack_pointer_rtx ) ; XVECEXP ( pat , <NUM_LIT> , nargs + <NUM_LIT> ) = gen_rtx_USE ( VOIDmode , this_arg ) ; } int i ; rtx arg ; for ( i = <NUM_LIT> , arg = cfun -> machine -> call_args ; arg ; arg = XEXP ( arg , <NUM_LIT> ) , i ++ ) { rtx this_arg = XEXP ( arg , <NUM_LIT> ) ; XVECEXP ( pat , <NUM_LIT> , i ) = gen_rtx_USE ( VOIDmode , this_arg ) ; } rtx tmp_retval = retval ; t = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; if ( retval != NULL_RTX ) { if ( ! nvptx_register_operand ( retval , GET_MODE ( retval ) ) ) tmp_retval = gen_reg_rtx ( GET_MODE ( retval ) ) ; t = gen_rtx_SET ( VOIDmode , tmp_retval , t ) ; } XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) = t ; if ( ! REG_P ( callee ) && ( decl_type == NULL_TREE || ( external_decl && TYPE_ARG_TYPES ( decl_type ) == NULL_TREE ) ) ) { rtx * slot = declared_libfuncs_htab -> find_slot ( callee , INSERT ) ; if ( * slot == NULL ) { * slot = callee ;"
GCC,nvptx,69,"Predict the next statement of this code snippet:
 <s> fputs ( func_decls . str ( ) . c_str ( ) , asm_out_file ) ;"
GCC,nvptx,70,"Predict the next statement of this code snippet:
 <s> FOR_EACH_HASH_TABLE_ELEMENT ( * needed_fndecls_htab , decl , tree , iter ) nvptx_record_fndecl ( decl , true ) ;"
GCC,nvptx,71,"Predict the next statement of this code snippet:
 <s> fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ;"
GCC,nvptx,72,"Predict the next statement of this code snippet:
 <s> fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fprintf ( asm_out_file , <STR_LIT> , GET_MODE_BITSIZE ( Pmode ) ) ;"
GCC,nvptx,73,"Predict the next statement of this code snippet:
 <s> if ( named ) return gen_reg_rtx ( mode ) ;"
GCC,nvptx,74,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_function_arg ( cumulative_args_t , machine_mode mode , const_tree , bool named ) { if ( mode == VOIDmode ) return NULL_RTX ; if ( named ) return gen_reg_rtx ( mode ) ;"
GCC,nvptx,75,"Predict the next statement of this code snippet:
 <s> if ( mode == TImode ) cum -> count += <NUM_LIT> ; else cum -> count ++ ;"
GCC,nvptx,76,"Predict the next statement of this code snippet:
 <s> if ( boundary < BITS_PER_WORD ) { if ( size >= <NUM_LIT> ) return BITS_PER_WORD ; if ( size >= <NUM_LIT> ) return <NUM_LIT> * BITS_PER_UNIT ; } }"
GCC,nvptx,77,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> ) ;"
GCC,nvptx,78,"Predict the next statement of this code snippet:
 <s> if ( ! named ) return NULL_RTX ; return gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , GEN_INT ( <NUM_LIT> + cum -> count ) ) , UNSPEC_ARG_REG ) ;"
GCC,nvptx,79,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_function_value ( const_tree type , const_tree func ATTRIBUTE_UNUSED , bool outgoing ) { int unsignedp = TYPE_UNSIGNED ( type ) ; machine_mode orig_mode = TYPE_MODE ( type ) ; machine_mode mode = promote_function_mode ( type , orig_mode , & unsignedp , NULL_TREE , <NUM_LIT> ) ;"
GCC,nvptx,80,"Predict the next statement of this code snippet:
 <s> machine_mode mode = promote_function_mode ( type , orig_mode , & unsignedp , NULL_TREE , <NUM_LIT> ) ; if ( outgoing ) return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ; if ( cfun -> machine -> start_call == NULL_RTX ) return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ;"
GCC,nvptx,81,"Predict the next statement of this code snippet:
 <s> } else if ( TREE_TYPE ( TREE_TYPE ( decl ) ) != void_type_node ) { error ( <STR_LIT> , name ) ; * no_add_attrs = true ;"
GCC,nvptx,82,"Predict the next statement of this code snippet:
 <s> bool nvptx_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( regno != NVPTX_RETURN_REGNUM || cfun == NULL || cfun -> machine -> ret_reg_mode == VOIDmode ) return true ; return mode == cfun -> machine -> ret_reg_mode ;"
GCC,nvptx,83,"Predict the next statement of this code snippet:
 <s> if ( regno != NVPTX_RETURN_REGNUM || cfun == NULL || cfun -> machine -> ret_reg_mode == VOIDmode ) return true ; return mode == cfun -> machine -> ret_reg_mode ;"
GCC,nvptx,84,"Predict the next statement of this code snippet:
 <s> struct machine_function * p = ggc_cleared_alloc < machine_function > ( ) ; p -> ret_reg_mode = VOIDmode ;"
GCC,nvptx,85,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_libcall_value ( machine_mode mode , const_rtx ) {"
GCC,nvptx,86,"Predict the next statement of this code snippet:
 <s> nvptx_record_needed_fndecl ( decl ) ; return orig_op ; } addr_space_t as = nvptx_addr_space_from_address ( op ) ; if ( as == ADDR_SPACE_GENERIC ) return orig_op ; enum unspec code ; code = ( as == ADDR_SPACE_GLOBAL ? UNSPEC_FROM_GLOBAL : as == ADDR_SPACE_LOCAL ? UNSPEC_FROM_LOCAL : as == ADDR_SPACE_SHARED ? UNSPEC_FROM_SHARED : as == ADDR_SPACE_CONST ? UNSPEC_FROM_CONST : UNSPEC_FROM_PARAM ) ;"
GCC,nvptx,87,"Predict the next statement of this code snippet:
 <s> rtx nvptx_maybe_convert_symbolic_operand ( rtx orig_op ) { if ( GET_MODE ( orig_op ) != Pmode ) return orig_op ; rtx op = orig_op ; while ( GET_CODE ( op ) == PLUS || GET_CODE ( op ) == CONST ) op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) != SYMBOL_REF ) return orig_op ; tree decl = SYMBOL_REF_DECL ( op ) ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) { nvptx_record_needed_fndecl ( decl ) ; return orig_op ; } addr_space_t as = nvptx_addr_space_from_address ( op ) ; if ( as == ADDR_SPACE_GENERIC ) return orig_op ;"
GCC,nvptx,88,"Predict the next statement of this code snippet:
 <s> init_machine_status = nvptx_init_machine_status ; flag_toplevel_reorder = <NUM_LIT> ; flag_var_tracking = <NUM_LIT> ; write_symbols = NO_DEBUG ;"
GCC,nvptx,89,"Predict the next statement of this code snippet:
 <s> } for ( int i = <NUM_LIT> , argno = <NUM_LIT> ; i < nargs ; i ++ ) { rtx t = XEXP ( XVECEXP ( pat , <NUM_LIT> , i + <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( REG_P ( t ) ) ; machine_mode mode = GET_MODE ( t ) ; int count = maybe_split_mode ( & mode ) ; if ( count == <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> , nvptx_ptx_type_from_mode ( mode , false ) , argno ++ , REGNO ( t ) ) ; else { int n = <NUM_LIT> ; while ( count -- > <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> , nvptx_ptx_type_from_mode ( mode , false ) , argno ++ , REGNO ( t ) , n ++ ) ; } } fprintf ( asm_out_file , <STR_LIT> ) ; if ( result != NULL_RTX ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( decl ) { const char * name = get_fnname_from_decl ( decl ) ; name = nvptx_name_replacement ( name ) ; assemble_name ( asm_out_file , name ) ; } else output_address ( callee ) ; if ( nargs > <NUM_LIT> || ( decl && DECL_STATIC_CHAIN ( decl ) ) ) { fprintf ( asm_out_file , <STR_LIT> ) ; int i , argno ; for ( i = <NUM_LIT> , argno = <NUM_LIT> ; i < nargs ; i ++ ) { rtx t = XEXP ( XVECEXP ( pat , <NUM_LIT> , i + <NUM_LIT> ) , <NUM_LIT> ) ; machine_mode mode = GET_MODE ( t ) ; int count = maybe_split_mode ( & mode ) ; while ( count -- > <NUM_LIT> ) { fprintf ( asm_out_file , <STR_LIT> , argno ++ ) ; if ( i + <NUM_LIT> < nargs || count > <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> ) ; } } if ( decl && DECL_STATIC_CHAIN ( decl ) ) { if ( i > <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ OUTGOING_STATIC_CHAIN_REGNUM ] ) ; } fprintf ( asm_out_file , <STR_LIT> ) ; } if ( needs_tgt ) { fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , buf ) ; } fprintf ( asm_out_file , <STR_LIT> ) ; if ( result != NULL_RTX ) return <STR_LIT> ;"
GCC,nvptx,90,"Predict the next statement of this code snippet:
 <s> tree fntype = TREE_TYPE ( current_function_decl ) ; tree result_type = TREE_TYPE ( fntype ) ;"
GCC,nvptx,91,"Predict the next statement of this code snippet:
 <s> if ( RETURN_IN_REG_P ( mode ) ) { mode = arg_promotion ( mode ) ;"
GCC,nvptx,92,"Predict the next statement of this code snippet:
 <s> if ( decl_offset % decl_chunk_size != <NUM_LIT> ) nvptx_assemble_value ( <NUM_LIT> , decl_chunk_size ) ; object_finished = true ; return ; } while ( size > decl_chunk_size ) { nvptx_assemble_value ( <NUM_LIT> , decl_chunk_size ) ; size -= decl_chunk_size ; } while ( size -- > <NUM_LIT> ) nvptx_assemble_value ( <NUM_LIT> , <NUM_LIT> ) ;"
GCC,nvptx,93,"Predict the next statement of this code snippet:
 <s> return ! PASS_IN_REG_P ( mode , type ) ;"
GCC,nvptx,94,"Predict the next statement of this code snippet:
 <s> static void nvptx_print_address_operand ( FILE * file , rtx x , machine_mode ) { rtx off ; if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , <NUM_LIT> ) ; switch ( GET_CODE ( x ) ) {"
GCC,nvptx,95,"Predict the next statement of this code snippet:
 <s> rtx off ; if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , <NUM_LIT> ) ; switch ( GET_CODE ( x ) ) { case PLUS : off = XEXP ( x , <NUM_LIT> ) ; output_address ( XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ; output_address ( off ) ; break ; case SYMBOL_REF : case LABEL_REF : output_addr_const ( file , x ) ; break ; default : gcc_assert ( GET_CODE ( x ) != MEM ) ; nvptx_print_operand ( file , x , <NUM_LIT> ) ; break ; }"
GCC,nvptx,96,"Predict the next statement of this code snippet:
 <s> fputs ( <STR_LIT> , file ) ; if ( GET_CODE ( x ) == EQ ) fputs ( <STR_LIT> , file ) ; fputs ( reg_names [ regno ] , file ) ; fputs ( <STR_LIT> , file ) ; } return ; } else if ( code == '#' ) { fputs ( <STR_LIT> , file ) ; return ; } enum rtx_code x_code = GET_CODE ( x ) ; switch ( code ) { case 'A' : { addr_space_t as = nvptx_addr_space_from_address ( XEXP ( x , <NUM_LIT> ) ) ; fputs ( nvptx_section_from_addr_space ( as ) , file ) ; } break ; case 'd' : gcc_assert ( x_code == CONST_INT ) ; if ( INTVAL ( x ) == <NUM_LIT> ) fputs ( <STR_LIT> , file ) ; else if ( INTVAL ( x ) == <NUM_LIT> ) fputs ( <STR_LIT> , file ) ; else if ( INTVAL ( x ) == <NUM_LIT> ) fputs ( <STR_LIT> , file ) ; else gcc_unreachable ( ) ; break ; case 't' : op_mode = nvptx_underlying_object_mode ( x ) ; fprintf ( file , <STR_LIT> , nvptx_ptx_type_from_mode ( op_mode , true ) ) ; break ; case 'u' : op_mode = nvptx_underlying_object_mode ( x ) ; fprintf ( file , <STR_LIT> , nvptx_ptx_type_from_mode ( op_mode , false ) ) ; break ; case 'T' : fprintf ( file , <STR_LIT> , GET_MODE_BITSIZE ( GET_MODE ( x ) ) ) ; break ; case 'j' : fprintf ( file , <STR_LIT> ) ; goto common ; case 'J' : fprintf ( file , <STR_LIT> ) ; goto common ; case 'c' : op_mode = GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ; switch ( x_code ) { case EQ : fputs ( <STR_LIT> , file ) ; break ; case NE : if ( FLOAT_MODE_P ( op_mode ) ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; break ; case LE : fputs ( <STR_LIT> , file ) ; break ; case GE : fputs ( <STR_LIT> , file ) ; break ; case LT : fputs ( <STR_LIT> , file ) ; break ; case GT : fputs ( <STR_LIT> , file ) ; break ; case LEU : fputs ( <STR_LIT> , file ) ; break ; case GEU : fputs ( <STR_LIT> , file ) ; break ; case LTU : fputs ( <STR_LIT> , file ) ; break ; case GTU : fputs ( <STR_LIT> , file ) ; break ; case LTGT : fputs ( <STR_LIT> , file ) ; break ; case UNEQ : fputs ( <STR_LIT> , file ) ; break ;"
GCC,nvptx,97,"Predict the next statement of this code snippet:
 <s> nvptx_print_address_operand ( file , addr , VOIDmode ) ;"
GCC,nvptx,98,"Predict the next statement of this code snippet:
 <s> if ( TYPE_ARG_TYPES ( funtype ) == NULL_TREE && type != NULL_TREE && ! AGGREGATE_TYPE_P ( type ) ) { if ( mode == SFmode ) mode = DFmode ; mode = arg_promotion ( mode ) ;"
GCC,nvptx,99,"Predict the next statement of this code snippet:
 <s> if ( TYPE_ARG_TYPES ( funtype ) == NULL_TREE && type != NULL_TREE && ! AGGREGATE_TYPE_P ( type ) ) { if ( mode == SFmode ) mode = DFmode ; mode = arg_promotion ( mode ) ; }"
GCC,nvptx,100,"Predict the next statement of this code snippet:
 <s> if ( promote ) return <STR_LIT> ; else return <STR_LIT> ; case HImode : return <STR_LIT> ; case SImode : return <STR_LIT> ; case DImode : return <STR_LIT> ; case SFmode :"
GCC,nvptx,101,"Predict the next statement of this code snippet:
 <s> static bool nvptx_record_fndecl ( tree decl , bool force = false ) {"
GCC,nvptx,102,"Predict the next statement of this code snippet:
 <s> tree * slot = declared_fndecls_htab -> find_slot ( decl , INSERT ) ; if ( * slot == NULL ) { * slot = decl ; const char * name = get_fnname_from_decl ( decl ) ;"
GCC,nvptx,103,"Predict the next statement of this code snippet:
 <s> void nvptx_record_needed_fndecl ( tree decl ) {"
GCC,nvptx,104,"Predict the next statement of this code snippet:
 <s> if ( nvptx_record_fndecl ( decl ) ) return ;"
GCC,nvptx,105,"Predict the next statement of this code snippet:
 <s> fprintf ( asm_out_file , <STR_LIT> , TREE_CODE ( decl ) == VAR_DECL ? <STR_LIT> : <STR_LIT> , IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ;"
GCC,nvptx,106,"Predict the next statement of this code snippet:
 <s> fprintf ( asm_out_file , <STR_LIT> , TREE_CODE ( decl ) == VAR_DECL ? <STR_LIT> : <STR_LIT> , IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ;"
GCC,nvptx,107,"Predict the next statement of this code snippet:
 <s> compute_bb_for_insn ( ) ; df_clear_flags ( DF_LR_RUN_DCE ) ; df_analyze ( ) ; thread_prologue_and_epilogue_insns ( ) ; qiregs . n_allocated = <NUM_LIT> ; hiregs . n_allocated = <NUM_LIT> ; siregs . n_allocated = <NUM_LIT> ; diregs . n_allocated = <NUM_LIT> ; qiregs . mode = QImode ; hiregs . mode = HImode ; siregs . mode = SImode ; diregs . mode = DImode ; for ( insn = get_insns ( ) ; insn ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( ! NONDEBUG_INSN_P ( insn ) || asm_noperands ( insn ) >= <NUM_LIT> || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) continue ; qiregs . n_in_use = <NUM_LIT> ; hiregs . n_in_use = <NUM_LIT> ; siregs . n_in_use = <NUM_LIT> ; diregs . n_in_use = <NUM_LIT> ; extract_insn ( insn ) ; enum attr_subregs_ok s_ok = get_attr_subregs_ok ( insn ) ; for ( int i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) { rtx op = recog_data . operand [ i ] ; if ( GET_CODE ( op ) != SUBREG ) continue ; rtx inner = SUBREG_REG ( op ) ; machine_mode outer_mode = GET_MODE ( op ) ; machine_mode inner_mode = GET_MODE ( inner ) ; gcc_assert ( s_ok ) ; if ( s_ok && ( GET_MODE_PRECISION ( inner_mode ) >= GET_MODE_PRECISION ( outer_mode ) ) ) continue ; gcc_assert ( SCALAR_INT_MODE_P ( outer_mode ) ) ; struct reg_replace * r = ( outer_mode == QImode ? & qiregs : outer_mode == HImode ? & hiregs : outer_mode == SImode ? & siregs : & diregs ) ; rtx new_reg = get_replacement ( r ) ; if ( recog_data . operand_type [ i ] != OP_OUT ) {"
GCC,nvptx,108,"Predict the next statement of this code snippet:
 <s> struct reg_replace qiregs , hiregs , siregs , diregs ; rtx_insn * insn , * next ; compute_bb_for_insn ( ) ; df_clear_flags ( DF_LR_RUN_DCE ) ; df_analyze ( ) ; thread_prologue_and_epilogue_insns ( ) ; qiregs . n_allocated = <NUM_LIT> ; hiregs . n_allocated = <NUM_LIT> ; siregs . n_allocated = <NUM_LIT> ; diregs . n_allocated = <NUM_LIT> ; qiregs . mode = QImode ; hiregs . mode = HImode ; siregs . mode = SImode ; diregs . mode = DImode ; for ( insn = get_insns ( ) ; insn ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( ! NONDEBUG_INSN_P ( insn ) || asm_noperands ( insn ) >= <NUM_LIT> || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) continue ; qiregs . n_in_use = <NUM_LIT> ; hiregs . n_in_use = <NUM_LIT> ; siregs . n_in_use = <NUM_LIT> ; diregs . n_in_use = <NUM_LIT> ; extract_insn ( insn ) ; enum attr_subregs_ok s_ok = get_attr_subregs_ok ( insn ) ; for ( int i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) { rtx op = recog_data . operand [ i ] ; if ( GET_CODE ( op ) != SUBREG ) continue ; rtx inner = SUBREG_REG ( op ) ; machine_mode outer_mode = GET_MODE ( op ) ; machine_mode inner_mode = GET_MODE ( inner ) ; gcc_assert ( s_ok ) ; if ( s_ok && ( GET_MODE_PRECISION ( inner_mode ) >= GET_MODE_PRECISION ( outer_mode ) ) ) continue ; gcc_assert ( SCALAR_INT_MODE_P ( outer_mode ) ) ; struct reg_replace * r = ( outer_mode == QImode ? & qiregs : outer_mode == HImode ? & hiregs : outer_mode == SImode ? & siregs : & diregs ) ; rtx new_reg = get_replacement ( r ) ; if ( recog_data . operand_type [ i ] != OP_OUT ) { enum rtx_code code ; if ( GET_MODE_PRECISION ( inner_mode ) < GET_MODE_PRECISION ( outer_mode ) ) code = ZERO_EXTEND ; else code = TRUNCATE ; rtx pat = gen_rtx_SET ( VOIDmode , new_reg , gen_rtx_fmt_e ( code , outer_mode , inner ) ) ; emit_insn_before ( pat , insn ) ; } if ( recog_data . operand_type [ i ] != OP_IN ) { enum rtx_code code ; if ( GET_MODE_PRECISION ( inner_mode ) < GET_MODE_PRECISION ( outer_mode ) ) code = TRUNCATE ; else code = ZERO_EXTEND ; rtx pat = gen_rtx_SET ( VOIDmode , inner , gen_rtx_fmt_e ( code , inner_mode , new_reg ) ) ; emit_insn_after ( pat , insn ) ; } validate_change ( insn , recog_data . operand_loc [ i ] , new_reg , false ) ; } } int maxregs = max_reg_num ( ) ; regstat_init_n_sets_and_refs ( ) ;"
GCC,nvptx,109,"Predict the next statement of this code snippet:
 <s> if ( ! RETURN_IN_REG_P ( mode ) ) return true ; return false ;"
GCC,nvptx,110,"Predict the next statement of this code snippet:
 <s> static bool nvptx_return_in_memory ( const_tree type , const_tree ) { machine_mode mode = TYPE_MODE ( type ) ; if ( ! RETURN_IN_REG_P ( mode ) ) return true ;"
GCC,nvptx,111,"Predict the next statement of this code snippet:
 <s> const char * nvptx_section_for_decl ( const_tree decl ) { bool is_const = ( CONSTANT_CLASS_P ( decl ) || TREE_CODE ( decl ) == CONST_DECL || TREE_READONLY ( decl ) ) ; if ( is_const ) return <STR_LIT> ; return <STR_LIT> ;"
GCC,nvptx,112,"Predict the next statement of this code snippet:
 <s> bool is_const = ( CONSTANT_CLASS_P ( decl ) || TREE_CODE ( decl ) == CONST_DECL || TREE_READONLY ( decl ) ) ; if ( is_const ) return <STR_LIT> ; return <STR_LIT> ;"
GCC,nvptx,113,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case ADDR_SPACE_SHARED : return <STR_LIT> ; case ADDR_SPACE_GENERIC :"
GCC,nvptx,114,"Predict the next statement of this code snippet:
 <s> if ( mode == TImode ) return true ;"
GCC,nvptx,115,"Predict the next statement of this code snippet:
 <s> if ( ! DECL_STATIC_CHAIN ( fndecl ) ) return NULL ; if ( incoming_p ) return gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; else return gen_rtx_REG ( Pmode , OUTGOING_STATIC_CHAIN_REGNUM ) ;"
GCC,nvptx,116,"Predict the next statement of this code snippet:
 <s> if ( ! DECL_STATIC_CHAIN ( fndecl ) ) return NULL ;"
GCC,nvptx,117,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( obj ) == SUBREG ) obj = SUBREG_REG ( obj ) ; machine_mode mode = GET_MODE ( obj ) ;"
GCC,nvptx,118,"Predict the next statement of this code snippet:
 <s> machine_mode mode = GET_MODE ( obj ) ; if ( mode == TImode ) return DImode ; if ( COMPLEX_MODE_P ( mode ) ) return GET_MODE_INNER ( mode ) ; return mode ;"
GCC,nvptx,119,"Predict the next statement of this code snippet:
 <s> tree result_type = TREE_TYPE ( fntype ) ; tree args = TYPE_ARG_TYPES ( fntype ) ; tree attrs = DECL_ATTRIBUTES ( decl ) ; bool kernel = write_as_kernel ( attrs ) ; bool is_main = strcmp ( name , <STR_LIT> ) == <NUM_LIT> ; bool args_from_decl = false ; if ( args == <NUM_LIT> ) { args = DECL_ARGUMENTS ( decl ) ; args_from_decl = true ; } if ( DECL_EXTERNAL ( decl ) ) s << <STR_LIT> ; else if ( TREE_PUBLIC ( decl ) ) s << <STR_LIT> ; if ( kernel ) s << <STR_LIT> ; else s << <STR_LIT> ; bool return_in_mem = false ; if ( TYPE_MODE ( result_type ) != VOIDmode ) { machine_mode mode = TYPE_MODE ( result_type ) ; if ( ! RETURN_IN_REG_P ( mode ) ) return_in_mem = true ; else { mode = arg_promotion ( mode ) ; s << <STR_LIT> << nvptx_ptx_type_from_mode ( mode , false ) << <STR_LIT> ; } } if ( name [ <NUM_LIT> ] == '*' ) s << ( name + <NUM_LIT> ) ; else s << name ; if ( ( args != NULL_TREE && ! ( TREE_CODE ( args ) == TREE_LIST && TREE_VALUE ( args ) == void_type_node ) ) || is_main || return_in_mem || DECL_STATIC_CHAIN ( decl ) ) { s << <STR_LIT> ; int i = <NUM_LIT> ; bool any_args = false ; if ( return_in_mem ) { s << <STR_LIT> << GET_MODE_BITSIZE ( Pmode ) << <STR_LIT> ; i ++ ; } while ( args != NULL_TREE ) { tree type = args_from_decl ? TREE_TYPE ( args ) : TREE_VALUE ( args ) ; machine_mode mode = TYPE_MODE ( type ) ; if ( mode != VOIDmode ) { i = write_one_arg ( s , type , i , mode , TYPE_ARG_TYPES ( fntype ) == <NUM_LIT> ) ; any_args = true ; i ++ ; } args = TREE_CHAIN ( args ) ; } if ( stdarg_p ( fntype ) ) {"
GCC,nvptx,120,"Predict the next statement of this code snippet:
 <s> begin_decl_field ( ) ;"
GCC,nvptx,121,"Predict the next statement of this code snippet:
 <s> if ( argtypes == <NUM_LIT> ) args_from_decl = true ; else args = argtypes ; for ( i = return_in_mem ? <NUM_LIT> : <NUM_LIT> ; args != NULL_TREE ; args = TREE_CHAIN ( args ) ) { tree type = args_from_decl ? TREE_TYPE ( args ) : TREE_VALUE ( args ) ; machine_mode mode = TYPE_MODE ( type ) ; if ( mode == VOIDmode ) break ; if ( ! PASS_IN_REG_P ( mode , type ) ) mode = Pmode ; int count = maybe_split_mode ( & mode ) ; if ( count == <NUM_LIT> ) { if ( argtypes == NULL && ! AGGREGATE_TYPE_P ( type ) ) {"
GCC,nvptx,122,"Predict the next statement of this code snippet:
 <s> static bool write_as_kernel ( tree attrs ) { return ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE || lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE ) ;"
GCC,nvptx,123,"Predict the next statement of this code snippet:
 <s> static void write_function_decl_and_comment ( std :: stringstream & s , const char * name , const_tree decl ) { s << <STR_LIT> ; if ( TREE_PUBLIC ( decl ) ) s << <STR_LIT> ;"
GCC,nvptx,124,"Predict the next statement of this code snippet:
 <s> static void write_function_decl_and_comment ( std :: stringstream & s , const char * name , const_tree decl ) { s << <STR_LIT> ;"
GCC,nvptx,125,"Predict the next statement of this code snippet:
 <s> name = nvptx_name_replacement ( name ) ; s << <STR_LIT> << name << <STR_LIT> ; } s << ( callprototype ? <STR_LIT> : <STR_LIT> ) ; if ( result != NULL_RTX ) { s << <STR_LIT> ; s << nvptx_ptx_type_from_mode ( arg_promotion ( GET_MODE ( result ) ) , false ) ; s << <STR_LIT> ; if ( callprototype ) s << <STR_LIT> ; else s << <STR_LIT> ; s << <STR_LIT> ; } s << name ; int nargs = XVECLEN ( pat , <NUM_LIT> ) - <NUM_LIT> ; if ( nargs > <NUM_LIT> ) { s << <STR_LIT> ; for ( int i = <NUM_LIT> ; i < nargs ; i ++ ) { rtx t = XEXP ( XVECEXP ( pat , <NUM_LIT> , i + <NUM_LIT> ) , <NUM_LIT> ) ; machine_mode mode = GET_MODE ( t ) ; int count = maybe_split_mode ( & mode ) ; while ( count -- > <NUM_LIT> ) { s << <STR_LIT> ; s << nvptx_ptx_type_from_mode ( mode , false ) ; s << <STR_LIT> ; if ( callprototype ) s << <STR_LIT> ; else s << <STR_LIT> << i ; if ( mode == QImode || mode == HImode ) s << <STR_LIT> ; if ( i + <NUM_LIT> < nargs || count > <NUM_LIT> ) s << <STR_LIT> ; } } s << <STR_LIT> ;"
GCC,nvptx,126,"Predict the next statement of this code snippet:
 <s> if ( callprototype ) s << <STR_LIT> ; else s << <STR_LIT> ; s << <STR_LIT> ; } s << name ; int nargs = XVECLEN ( pat , <NUM_LIT> ) - <NUM_LIT> ; if ( nargs > <NUM_LIT> ) { s << <STR_LIT> ; for ( int i = <NUM_LIT> ; i < nargs ; i ++ ) { rtx t = XEXP ( XVECEXP ( pat , <NUM_LIT> , i + <NUM_LIT> ) , <NUM_LIT> ) ; machine_mode mode = GET_MODE ( t ) ; int count = maybe_split_mode ( & mode ) ; while ( count -- > <NUM_LIT> ) { s << <STR_LIT> ; s << nvptx_ptx_type_from_mode ( mode , false ) ; s << <STR_LIT> ; if ( callprototype ) s << <STR_LIT> ;"
GCC,nvptx,127,"Predict the next statement of this code snippet:
 <s> int count = maybe_split_mode ( & mode ) ; if ( count == <NUM_LIT> ) { write_one_arg ( s , NULL_TREE , i , mode , false ) ; write_one_arg ( s , NULL_TREE , i + <NUM_LIT> , mode , false ) ; return i + <NUM_LIT> ; } if ( no_arg_types && ! AGGREGATE_TYPE_P ( type ) ) { if ( mode == SFmode ) mode = DFmode ; mode = arg_promotion ( mode ) ;"
GCC,nvptx,128,"Predict the next statement of this code snippet:
 <s> write_one_arg ( s , NULL_TREE , i + <NUM_LIT> , mode , false ) ; return i + <NUM_LIT> ; } if ( no_arg_types && ! AGGREGATE_TYPE_P ( type ) ) { if ( mode == SFmode ) mode = DFmode ; mode = arg_promotion ( mode ) ; } if ( i > <NUM_LIT> ) s << <STR_LIT> ; s << <STR_LIT> << nvptx_ptx_type_from_mode ( mode , false ) << <STR_LIT> << ( i + <NUM_LIT> ) << ( mode == QImode || mode == HImode ? <STR_LIT> : <STR_LIT> ) ;"
GCC,nvptx,129,"Predict the next statement of this code snippet:
 <s> block -> flags &= ~ BB_VISITED ;"
GCC,nvptx,130,"Predict the next statement of this code snippet:
 <s> elt_size |= GET_MODE_SIZE ( elt_mode ) ; elt_size &= - elt_size ; init_frag . size = elt_size ; init_frag . mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( elt_size * BITS_PER_UNIT - <NUM_LIT> ) ) - <NUM_LIT> ; init_frag . val = <NUM_LIT> ; init_frag . offset = <NUM_LIT> ; init_frag . started = false ; init_frag . remaining = ( size + elt_size - <NUM_LIT> ) / elt_size ; fprintf ( file , <STR_LIT> , section , align / BITS_PER_UNIT , elt_size * BITS_PER_UNIT ) ; assemble_name ( file , name ) ;"
GCC,nvptx,131,"Predict the next statement of this code snippet:
 <s> static void nvptx_assemble_decl_begin ( FILE * file , const char * name , const char * section , const_tree type , HOST_WIDE_INT size , unsigned align ) { while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; if ( TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == COMPLEX_TYPE ) type = TREE_TYPE ( type ) ; unsigned elt_size = int_size_in_bytes ( type ) ; machine_mode elt_mode = TYPE_MODE ( type ) == BLKmode ? Pmode : DImode ; elt_size |= GET_MODE_SIZE ( elt_mode ) ; elt_size &= - elt_size ; init_frag . size = elt_size ; init_frag . mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( elt_size * BITS_PER_UNIT - <NUM_LIT> ) ) - <NUM_LIT> ; init_frag . val = <NUM_LIT> ; init_frag . offset = <NUM_LIT> ; init_frag . started = false ; init_frag . remaining = ( size + elt_size - <NUM_LIT> ) / elt_size ; fprintf ( file , <STR_LIT> , section , align / BITS_PER_UNIT , elt_size * BITS_PER_UNIT ) ;"
GCC,nvptx,132,"Predict the next statement of this code snippet:
 <s> if ( DECL_IN_CONSTANT_POOL ( decl ) ) return ; write_var_marker ( file , false , TREE_PUBLIC ( decl ) , name ) ; fprintf ( file , <STR_LIT> ) ; tree size = DECL_SIZE_UNIT ( decl ) ;"
GCC,nvptx,133,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> ) ; tree size = DECL_SIZE_UNIT ( decl ) ;"
GCC,nvptx,134,"Predict the next statement of this code snippet:
 <s> val >>= part * BITS_PER_UNIT ; part = init_frag . size - init_frag . offset ; if ( part > size ) part = size ; unsigned HOST_WIDE_INT partial = val << ( init_frag . offset * BITS_PER_UNIT ) ; init_frag . val |= partial & init_frag . mask ; init_frag . offset += part ; if ( init_frag . offset == init_frag . size ) output_init_frag ( NULL ) ;"
GCC,nvptx,135,"Predict the next statement of this code snippet:
 <s> tree result_type = TREE_TYPE ( fntype ) ; int argno = <NUM_LIT> ; std :: stringstream s ; write_fn_proto ( s , true , name , decl ) ; s << <STR_LIT> ; bool return_in_mem = write_return_type ( s , false , result_type ) ; if ( return_in_mem ) argno = write_arg_type ( s , <NUM_LIT> , argno , ptr_type_node , true ) ; tree args = TYPE_ARG_TYPES ( fntype ) ; bool prototyped = true ; if ( ! args ) { args = DECL_ARGUMENTS ( decl ) ; prototyped = false ; } for ( ; args != NULL_TREE ; args = TREE_CHAIN ( args ) ) { tree type = prototyped ? TREE_VALUE ( args ) : TREE_TYPE ( args ) ; argno = write_arg_type ( s , <NUM_LIT> , argno , type , prototyped ) ; } if ( stdarg_p ( fntype ) ) argno = write_arg_type ( s , ARG_POINTER_REGNUM , argno , ptr_type_node , true ) ; if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> has_chain ) write_arg_type ( s , STATIC_CHAIN_REGNUM , DECL_STATIC_CHAIN ( decl ) ? argno : - <NUM_LIT> , ptr_type_node , true ) ; fprintf ( file , <STR_LIT> , s . str ( ) . c_str ( ) ) ; if ( cfun -> machine -> has_varadic ) init_frame ( file , STACK_POINTER_REGNUM , UNITS_PER_WORD , crtl -> outgoing_args_size ) ; HOST_WIDE_INT sz = get_frame_size ( ) ; if ( sz || cfun -> machine -> has_chain ) init_frame ( file , FRAME_POINTER_REGNUM , crtl -> stack_alignment_needed / BITS_PER_UNIT , sz ) ; int maxregs = max_reg_num ( ) ;"
GCC,nvptx,136,"Predict the next statement of this code snippet:
 <s> args = DECL_ARGUMENTS ( decl ) ; prototyped = false ; } for ( ; args != NULL_TREE ; args = TREE_CHAIN ( args ) ) { tree type = prototyped ? TREE_VALUE ( args ) : TREE_TYPE ( args ) ; argno = write_arg_type ( s , <NUM_LIT> , argno , type , prototyped ) ; } if ( stdarg_p ( fntype ) ) argno = write_arg_type ( s , ARG_POINTER_REGNUM , argno , ptr_type_node , true ) ; if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> has_chain ) write_arg_type ( s , STATIC_CHAIN_REGNUM , DECL_STATIC_CHAIN ( decl ) ? argno : - <NUM_LIT> , ptr_type_node , true ) ; fprintf ( file , <STR_LIT> , s . str ( ) . c_str ( ) ) ; if ( cfun -> machine -> has_varadic ) init_frame ( file , STACK_POINTER_REGNUM , UNITS_PER_WORD , crtl -> outgoing_args_size ) ; HOST_WIDE_INT sz = get_frame_size ( ) ; if ( sz || cfun -> machine -> has_chain ) init_frame ( file , FRAME_POINTER_REGNUM , crtl -> stack_alignment_needed / BITS_PER_UNIT , sz ) ; int maxregs = max_reg_num ( ) ; for ( int i = LAST_VIRTUAL_REGISTER + <NUM_LIT> ; i < maxregs ; i ++ ) { if ( regno_reg_rtx [ i ] != const0_rtx ) { machine_mode mode = PSEUDO_REGNO_MODE ( i ) ; machine_mode split = maybe_split_mode ( mode ) ; if ( split != VOIDmode ) mode = split ; fprintf ( file , <STR_LIT> , nvptx_ptx_type_from_mode ( mode , true ) ) ; output_reg ( file , i , split , - <NUM_LIT> ) ; fprintf ( file , <STR_LIT> ) ;"
GCC,nvptx,137,"Predict the next statement of this code snippet:
 <s> switch ( axis ) { case GOMP_DIM_WORKER : return PTX_WORKER_LENGTH ; case GOMP_DIM_VECTOR : return PTX_VECTOR_LENGTH ; default : break ;"
GCC,nvptx,138,"Predict the next statement of this code snippet:
 <s> case GOMP_DIM_VECTOR : return PTX_VECTOR_LENGTH ; default : break ;"
GCC,nvptx,139,"Predict the next statement of this code snippet:
 <s> rtx op = GEN_INT ( mask | ( is_call << GOMP_DIM_MAX ) ) ;"
GCC,nvptx,140,"Predict the next statement of this code snippet:
 <s> if ( ! is_call ) emit_insn ( gen_nvptx_joining ( op ) ) ;"
GCC,nvptx,141,"Predict the next statement of this code snippet:
 <s> default_encode_section_info ( decl , rtl , first ) ; if ( first && MEM_P ( rtl ) ) { nvptx_data_area area = DATA_AREA_GENERIC ; if ( TREE_CONSTANT ( decl ) ) area = DATA_AREA_CONST ; else if ( TREE_CODE ( decl ) == VAR_DECL ) area = TREE_READONLY ( decl ) ? DATA_AREA_CONST : DATA_AREA_GLOBAL ; SET_SYMBOL_DATA_AREA ( XEXP ( rtl , <NUM_LIT> ) , area ) ;"
GCC,nvptx,142,"Predict the next statement of this code snippet:
 <s> tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case NVPTX_BUILTIN_SHUFFLE : case NVPTX_BUILTIN_SHUFFLELL : return nvptx_expand_shuffle ( exp , target , mode , ignore ) ;"
GCC,nvptx,143,"Predict the next statement of this code snippet:
 <s> } if ( GET_CODE ( callee ) == SYMBOL_REF ) { tree decl = SYMBOL_REF_DECL ( callee ) ; if ( decl != NULL_TREE ) { if ( DECL_STATIC_CHAIN ( decl ) ) cfun -> machine -> has_chain = true ; tree attr = get_oacc_fn_attrib ( decl ) ; if ( attr ) { tree dims = TREE_VALUE ( attr ) ; parallel = GOMP_DIM_MASK ( GOMP_DIM_MAX ) - <NUM_LIT> ; for ( int ix = <NUM_LIT> ; ix != GOMP_DIM_MAX ; ix ++ ) { if ( TREE_PURPOSE ( dims ) && ! integer_zerop ( TREE_PURPOSE ( dims ) ) ) break ; parallel ^= GOMP_DIM_MASK ( ix ) ; dims = TREE_CHAIN ( dims ) ; } } } } unsigned nargs = cfun -> machine -> num_args ; if ( cfun -> machine -> is_varadic ) { varargs = gen_reg_rtx ( Pmode ) ; emit_move_insn ( varargs , stack_pointer_rtx ) ; } rtvec vec = rtvec_alloc ( nargs + <NUM_LIT> ) ; rtx pat = gen_rtx_PARALLEL ( VOIDmode , vec ) ; int vec_pos = <NUM_LIT> ; rtx call = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; rtx tmp_retval = retval ; if ( retval ) { if ( ! nvptx_register_operand ( retval , GET_MODE ( retval ) ) ) tmp_retval = gen_reg_rtx ( GET_MODE ( retval ) ) ; call = gen_rtx_SET ( tmp_retval , call ) ;"
GCC,nvptx,144,"Predict the next statement of this code snippet:
 <s> if ( align > worker_red_align ) worker_red_align = align ; unsigned offset = TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; unsigned size = TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( size + offset > worker_red_size ) worker_red_size = size + offset ; rtx addr = worker_red_sym ; if ( offset ) { addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( offset ) ) ; addr = gen_rtx_CONST ( Pmode , addr ) ;"
GCC,nvptx,145,"Predict the next statement of this code snippet:
 <s> unsigned offset = TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; unsigned size = TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( size + offset > worker_red_size ) worker_red_size = size + offset ; rtx addr = worker_red_sym ; if ( offset ) { addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( offset ) ) ; addr = gen_rtx_CONST ( Pmode , addr ) ;"
GCC,nvptx,146,"Predict the next statement of this code snippet:
 <s> if ( worker_bcast_size ) write_worker_buffer ( asm_out_file , worker_bcast_sym , worker_bcast_align , worker_bcast_size ) ;"
GCC,nvptx,147,"Predict the next statement of this code snippet:
 <s> static void nvptx_file_end ( void ) { hash_table < tree_hasher > :: iterator iter ; tree decl ; FOR_EACH_HASH_TABLE_ELEMENT ( * needed_fndecls_htab , decl , tree , iter ) nvptx_record_fndecl ( decl ) ; fputs ( func_decls . str ( ) . c_str ( ) , asm_out_file ) ; if ( worker_bcast_size ) write_worker_buffer ( asm_out_file , worker_bcast_sym , worker_bcast_align , worker_bcast_size ) ; if ( worker_red_size ) write_worker_buffer ( asm_out_file , worker_red_sym , worker_red_align , worker_red_size ) ;"
GCC,nvptx,148,"Predict the next statement of this code snippet:
 <s> case CODE_FOR_nvptx_forked : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , <NUM_LIT> , <NUM_LIT> ) ) ; gcc_assert ( mask ) ; par = new parallel ( par , mask ) ; par -> forked_block = block ; par -> forked_insn = end ; if ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) && ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) ) par -> fork_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_fork ) ; } break ; case CODE_FOR_nvptx_join : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , <NUM_LIT> , <NUM_LIT> ) ) ; gcc_assert ( par -> mask == mask ) ; par -> join_block = block ; par -> join_insn = end ; if ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) && ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) ) par -> joining_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_joining ) ; par = par -> parent ; } break ; default : gcc_unreachable ( ) ; } }"
GCC,nvptx,149,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_function_arg ( cumulative_args_t ARG_UNUSED ( cum_v ) , machine_mode mode , const_tree , bool named ) {"
GCC,nvptx,150,"Predict the next statement of this code snippet:
 <s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> count ++ ;"
GCC,nvptx,151,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_function_value ( const_tree type , const_tree ARG_UNUSED ( func ) , bool outgoing ) {"
GCC,nvptx,152,"Predict the next statement of this code snippet:
 <s> return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ; } return nvptx_libcall_value ( mode , NULL_RTX ) ;"
GCC,nvptx,153,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_gen_pack ( rtx dst , rtx src0 , rtx src1 ) { rtx res ; switch ( GET_MODE ( dst ) ) { case DImode : res = gen_packsidi2 ( dst , src0 , src1 ) ; break ; case DFmode : res = gen_packsidf2 ( dst , src0 , src1 ) ; break ;"
GCC,nvptx,154,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_gen_pack ( rtx dst , rtx src0 , rtx src1 ) { rtx res ; switch ( GET_MODE ( dst ) ) { case DImode :"
GCC,nvptx,155,"Predict the next statement of this code snippet:
 <s> rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; emit_insn ( nvptx_gen_unpack ( tmp0 , tmp1 , src ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp0 , tmp0 , idx , kind ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp1 , tmp1 , idx , kind ) ) ; emit_insn ( nvptx_gen_pack ( dst , tmp0 , tmp1 ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; case BImode : { rtx tmp = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; emit_insn ( gen_sel_truesi ( tmp , src , GEN_INT ( <NUM_LIT> ) , const0_rtx ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp , tmp , idx , kind ) ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_NE ( BImode , tmp , const0_rtx ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ;"
GCC,nvptx,156,"Predict the next statement of this code snippet:
 <s> case DFmode : res = gen_unpackdfsi2 ( dst0 , dst1 , src ) ; break ; default : gcc_unreachable ( ) ; }"
GCC,nvptx,157,"Predict the next statement of this code snippet:
 <s> return nvptx_gen_shuffle ( reg , reg , const0_rtx , SHUFFLE_IDX ) ;"
GCC,nvptx,158,"Predict the next statement of this code snippet:
 <s> } break ; default : { rtx addr = data -> ptr ; if ( ! addr ) { unsigned align = GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ; if ( align > worker_bcast_align ) worker_bcast_align = align ; data -> offset = ( data -> offset + align - <NUM_LIT> ) & ~ ( align - <NUM_LIT> ) ; addr = data -> base ; if ( data -> offset ) addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( data -> offset ) ) ; } addr = gen_rtx_MEM ( mode , addr ) ; if ( pm == PM_read ) res = gen_rtx_SET ( addr , reg ) ; else if ( pm == PM_write ) res = gen_rtx_SET ( reg , addr ) ; else gcc_unreachable ( ) ; if ( data -> ptr ) { start_sequence ( ) ;"
GCC,nvptx,159,"Predict the next statement of this code snippet:
 <s> static tree nvptx_get_worker_red_addr ( tree type , tree offset ) { machine_mode mode = TYPE_MODE ( type ) ; tree fndecl = nvptx_builtin_decl ( NVPTX_BUILTIN_WORKER_ADDR , true ) ; tree size = build_int_cst ( unsigned_type_node , GET_MODE_SIZE ( mode ) ) ; tree align = build_int_cst ( unsigned_type_node , GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ) ;"
GCC,nvptx,160,"Predict the next statement of this code snippet:
 <s> break ; case IFN_GOACC_REDUCTION_FINI : nvptx_goacc_reduction_fini ( call ) ; break ; case IFN_GOACC_REDUCTION_TEARDOWN : nvptx_goacc_reduction_teardown ( call ) ; break ; default : gcc_unreachable ( ) ; }"
GCC,nvptx,161,"Predict the next statement of this code snippet:
 <s> case IFN_GOACC_REDUCTION_INIT : nvptx_goacc_reduction_init ( call ) ; break ; case IFN_GOACC_REDUCTION_FINI : nvptx_goacc_reduction_fini ( call ) ; break ; case IFN_GOACC_REDUCTION_TEARDOWN : nvptx_goacc_reduction_teardown ( call ) ; break ; default :"
GCC,nvptx,162,"Predict the next statement of this code snippet:
 <s> enum tree_code op = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; gimple_seq seq = NULL ; tree r = NULL_TREE ; ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR ) { for ( int shfl = PTX_VECTOR_LENGTH / <NUM_LIT> ; shfl > <NUM_LIT> ; shfl = shfl >> <NUM_LIT> ) { tree other_var = make_ssa_name ( TREE_TYPE ( var ) ) ; nvptx_generate_vector_shuffle ( gimple_location ( call ) , other_var , var , shfl , & seq ) ; r = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( r , fold_build2 ( op , TREE_TYPE ( var ) , var , other_var ) , & seq ) ; var = r ; } } else { tree accum = NULL_TREE ; if ( level == GOMP_DIM_WORKER ) { tree offset = gimple_call_arg ( call , <NUM_LIT> ) ; tree call = nvptx_get_worker_red_addr ( TREE_TYPE ( var ) , offset ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; accum = ptr ; } else if ( integer_zerop ( ref_to_res ) ) r = var ; else accum = ref_to_res ; if ( accum ) { gsi_insert_seq_before ( & gsi , seq , GSI_SAME_STMT ) ;"
GCC,nvptx,163,"Predict the next statement of this code snippet:
 <s> gimple * cond_stmt = gimple_build_cond ( NE_EXPR , tid , integer_zero_node , NULL_TREE , NULL_TREE ) ; gimple_call_set_lhs ( tid_call , tid ) ; gimple_seq_add_stmt ( & seq , tid_call ) ; gimple_seq_add_stmt ( & seq , cond_stmt ) ; edge init_edge = split_block ( gsi_bb ( gsi ) , call ) ; basic_block init_bb = init_edge -> dest ; basic_block call_bb = init_edge -> src ; init_edge -> flags ^= EDGE_FALLTHRU | EDGE_TRUE_VALUE ; gimple_seq init_seq = NULL ; tree init_var = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( init_var , init , & init_seq ) ; gsi = gsi_start_bb ( init_bb ) ; gsi_insert_seq_before ( & gsi , init_seq , GSI_SAME_STMT ) ; gsi_prev ( & gsi ) ;"
GCC,nvptx,164,"Predict the next statement of this code snippet:
 <s> static void nvptx_goacc_reduction_setup ( gcall * call ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , <NUM_LIT> ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level != GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , <NUM_LIT> ) ; if ( ! integer_zerop ( ref_to_res ) ) var = build_simple_mem_ref ( ref_to_res ) ; } if ( level == GOMP_DIM_WORKER ) { tree offset = gimple_call_arg ( call , <NUM_LIT> ) ; tree call = nvptx_get_worker_red_addr ( TREE_TYPE ( var ) , offset ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; tree ref = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( ref ) = <NUM_LIT> ; gimplify_assign ( ref , var , & seq ) ; } if ( lhs ) gimplify_assign ( lhs , var , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ;"
GCC,nvptx,165,"Predict the next statement of this code snippet:
 <s> tree call = nvptx_get_worker_red_addr ( TREE_TYPE ( var ) , offset ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; tree ref = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( ref ) = <NUM_LIT> ; gimplify_assign ( ref , var , & seq ) ; } if ( lhs ) gimplify_assign ( lhs , var , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ;"
GCC,nvptx,166,"Predict the next statement of this code snippet:
 <s> gimplify_assign ( ptr , call , & seq ) ; var = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( var ) = <NUM_LIT> ; } if ( level != GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , <NUM_LIT> ) ; if ( ! integer_zerop ( ref_to_res ) ) gimplify_assign ( build_simple_mem_ref ( ref_to_res ) , var , & seq ) ; }"
GCC,nvptx,167,"Predict the next statement of this code snippet:
 <s> static bool nvptx_goacc_validate_dims ( tree decl , int dims [ ] , int fn_level ) { bool changed = false ; if ( fn_level <= GOMP_DIM_VECTOR && fn_level >= - <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] >= <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] != PTX_VECTOR_LENGTH ) { if ( fn_level < <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] >= <NUM_LIT> ) warning_at ( decl ? DECL_SOURCE_LOCATION ( decl ) : UNKNOWN_LOCATION , <NUM_LIT> , dims [ GOMP_DIM_VECTOR ] ? <STR_LIT> : <STR_LIT> , PTX_VECTOR_LENGTH , dims [ GOMP_DIM_VECTOR ] ) ; dims [ GOMP_DIM_VECTOR ] = PTX_VECTOR_LENGTH ; changed = true ; } if ( dims [ GOMP_DIM_WORKER ] > PTX_WORKER_LENGTH ) { warning_at ( decl ? DECL_SOURCE_LOCATION ( decl ) : UNKNOWN_LOCATION , <NUM_LIT> , <STR_LIT> , PTX_WORKER_LENGTH , dims [ GOMP_DIM_WORKER ] ) ; dims [ GOMP_DIM_WORKER ] = PTX_WORKER_LENGTH ;"
GCC,nvptx,168,"Predict the next statement of this code snippet:
 <s> static void nvptx_init_axis_predicate ( FILE * file , int regno , const char * name ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , name ) ; fprintf ( file , <STR_LIT> , name , name ) ; fprintf ( file , <STR_LIT> , regno , name ) ; fprintf ( file , <STR_LIT> ) ;"
GCC,nvptx,169,"Predict the next statement of this code snippet:
 <s> DEF ( SHUFFLELL , <STR_LIT> , ( LLUINT , LLUINT , UINT , UINT , NULL_TREE ) ) ; DEF ( WORKER_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAP , <STR_LIT> , ( UINT , PTRVOID , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAPLL , <STR_LIT> , ( LLUINT , PTRVOID , LLUINT , LLUINT , NULL_TREE ) ) ;"
GCC,nvptx,170,"Predict the next statement of this code snippet:
 <s> DEF ( WORKER_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAP , <STR_LIT> , ( UINT , PTRVOID , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAPLL , <STR_LIT> , ( LLUINT , PTRVOID , LLUINT , LLUINT , NULL_TREE ) ) ;"
GCC,nvptx,171,"Predict the next statement of this code snippet:
 <s> if ( ! cfun -> machine -> doing_call ) return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ;"
GCC,nvptx,172,"Predict the next statement of this code snippet:
 <s> if ( ! cfun -> machine -> doing_call ) return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ; return gen_reg_rtx ( mode ) ;"
GCC,nvptx,173,"Predict the next statement of this code snippet:
 <s> locked_edge -> flags ^= EDGE_TRUE_VALUE | EDGE_FALLTHRU ; make_edge ( lock_bb , lock_bb , EDGE_FALSE_VALUE ) ; set_immediate_dominator ( CDI_DOMINATORS , lock_bb , entry_bb ) ; set_immediate_dominator ( CDI_DOMINATORS , update_bb , lock_bb ) ; loop * lock_loop = alloc_loop ( ) ; lock_loop -> header = lock_bb ; lock_loop -> latch = lock_bb ; lock_loop -> nb_iterations_estimate = <NUM_LIT> ; lock_loop -> any_estimate = true ; add_loop ( lock_loop , entry_bb -> loop_father ) ; gimple_seq red_seq = NULL ; tree acc_in = make_ssa_name ( var_type ) ; tree ref_in = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( ref_in ) = <NUM_LIT> ; gimplify_assign ( acc_in , ref_in , & red_seq ) ; tree acc_out = make_ssa_name ( var_type ) ; tree update_expr = fold_build2 ( op , var_type , ref_in , var ) ; gimplify_assign ( acc_out , update_expr , & red_seq ) ; tree ref_out = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( ref_out ) = <NUM_LIT> ; gimplify_assign ( ref_out , acc_out , & red_seq ) ; gsi_insert_seq_before ( gsi , red_seq , GSI_SAME_STMT ) ;"
GCC,nvptx,174,"Predict the next statement of this code snippet:
 <s> basic_block pre_bb = gsi_bb ( * gsi ) ; edge pre_edge = split_block ( pre_bb , init_end ) ; basic_block loop_bb = pre_edge -> dest ; pre_bb = pre_edge -> src ; * gsi = gsi_for_stmt ( gsi_stmt ( * gsi ) ) ; tree expect_var = make_ssa_name ( arg_type ) ; tree actual_var = make_ssa_name ( arg_type ) ; tree write_var = make_ssa_name ( arg_type ) ; gimple_seq red_seq = NULL ; tree write_expr = fold_build1 ( code , var_type , expect_var ) ; write_expr = fold_build2 ( op , var_type , write_expr , var ) ; write_expr = fold_build1 ( code , arg_type , write_expr ) ; gimplify_assign ( write_var , write_expr , & red_seq ) ; gsi_insert_seq_before ( gsi , red_seq , GSI_SAME_STMT ) ; gimple_seq latch_seq = NULL ; tree swap_expr = build_call_expr_loc ( loc , swap_fn , <NUM_LIT> , ptr , expect_var , write_var ) ; gimplify_assign ( actual_var , swap_expr , & latch_seq ) ; gcond * cond = gimple_build_cond ( EQ_EXPR , actual_var , expect_var , NULL_TREE , NULL_TREE ) ; gimple_seq_add_stmt ( & latch_seq , cond ) ; gimple * latch_end = gimple_seq_last ( latch_seq ) ; gsi_insert_seq_before ( gsi , latch_seq , GSI_SAME_STMT ) ; edge post_edge = split_block ( loop_bb , latch_end ) ; basic_block post_bb = post_edge -> dest ; loop_bb = post_edge -> src ; * gsi = gsi_for_stmt ( gsi_stmt ( * gsi ) ) ; post_edge -> flags ^= EDGE_TRUE_VALUE | EDGE_FALLTHRU ; edge loop_edge = make_edge ( loop_bb , loop_bb , EDGE_FALSE_VALUE ) ; set_immediate_dominator ( CDI_DOMINATORS , loop_bb , pre_bb ) ; set_immediate_dominator ( CDI_DOMINATORS , post_bb , loop_bb ) ; gphi * phi = create_phi_node ( expect_var , loop_bb ) ; add_phi_arg ( phi , init_var , pre_edge , loc ) ;"
GCC,nvptx,175,"Predict the next statement of this code snippet:
 <s> worker_bcast_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( worker_bcast_sym , DATA_AREA_SHARED ) ; worker_bcast_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; worker_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( worker_red_sym , DATA_AREA_SHARED ) ; worker_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ;"
GCC,nvptx,176,"Predict the next statement of this code snippet:
 <s> static int labelno ; bool needs_tgt = register_operand ( callee , Pmode ) ; rtx pat = PATTERN ( insn ) ; int arg_end = XVECLEN ( pat , <NUM_LIT> ) ; tree decl = NULL_TREE ; fprintf ( asm_out_file , <STR_LIT> ) ; if ( result != NULL ) fprintf ( asm_out_file , <STR_LIT> , nvptx_ptx_type_from_mode ( GET_MODE ( result ) , false ) , reg_names [ NVPTX_RETURN_REGNUM ] ) ; if ( GET_CODE ( callee ) == SYMBOL_REF ) { decl = SYMBOL_REF_DECL ( callee ) ; if ( ! decl || ( DECL_EXTERNAL ( decl ) && ! TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ) ) nvptx_record_libfunc ( callee , result , pat ) ; else if ( DECL_EXTERNAL ( decl ) ) nvptx_record_fndecl ( decl ) ; } if ( needs_tgt ) { ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; labelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; std :: stringstream s ; write_fn_proto_from_insn ( s , NULL , result , pat ) ; fputs ( s . str ( ) . c_str ( ) , asm_out_file ) ; } for ( int argno = <NUM_LIT> ; argno < arg_end ; argno ++ ) { rtx t = XEXP ( XVECEXP ( pat , <NUM_LIT> , argno ) , <NUM_LIT> ) ; machine_mode mode = GET_MODE ( t ) ; const char * ptx_type = nvptx_ptx_type_from_mode ( mode , false ) ; fprintf ( asm_out_file , <STR_LIT> <STR_LIT> , ptx_type , argno , ptx_type , argno ) ; output_reg ( asm_out_file , REGNO ( t ) , VOIDmode ) ; fprintf ( asm_out_file , <STR_LIT> ) ; } fprintf ( asm_out_file , <STR_LIT> ) ; if ( result != NULL_RTX ) fprintf ( asm_out_file , <STR_LIT> , reg_names [ NVPTX_RETURN_REGNUM ] ) ; if ( decl ) { const char * name = get_fnname_from_decl ( decl ) ; name = nvptx_name_replacement ( name ) ; assemble_name ( asm_out_file , name ) ; } else output_address ( VOIDmode , callee ) ; const char * open = <STR_LIT> ; for ( int argno = <NUM_LIT> ; argno < arg_end ; argno ++ ) { fprintf ( asm_out_file , <STR_LIT> , open , argno ) ; open = <STR_LIT> ; } if ( decl && DECL_STATIC_CHAIN ( decl ) ) { fprintf ( asm_out_file , <STR_LIT> , open , reg_names [ STATIC_CHAIN_REGNUM ] ) ; open = <STR_LIT> ; }"
GCC,nvptx,177,"Predict the next statement of this code snippet:
 <s> machine_mode dst_inner = ( GET_CODE ( dst ) == SUBREG ? GET_MODE ( XEXP ( dst , <NUM_LIT> ) ) : dst_mode ) ; machine_mode src_inner = ( GET_CODE ( src ) == SUBREG ? GET_MODE ( XEXP ( src , <NUM_LIT> ) ) : dst_mode ) ; rtx sym = src ; if ( GET_CODE ( sym ) == CONST ) sym = XEXP ( XEXP ( sym , <NUM_LIT> ) , <NUM_LIT> ) ; if ( SYMBOL_REF_P ( sym ) ) { if ( SYMBOL_DATA_AREA ( sym ) != DATA_AREA_GENERIC ) return <STR_LIT> ; nvptx_maybe_record_fnsym ( sym ) ; } if ( src_inner == dst_inner ) return <STR_LIT> ; if ( CONSTANT_P ( src ) ) return ( GET_MODE_CLASS ( dst_inner ) == MODE_INT && GET_MODE_CLASS ( src_inner ) != MODE_FLOAT ? <STR_LIT> : <STR_LIT> ) ; if ( GET_MODE_SIZE ( dst_inner ) == GET_MODE_SIZE ( src_inner ) ) return <STR_LIT> ;"
GCC,nvptx,178,"Predict the next statement of this code snippet:
 <s> return pass_in_memory ( mode , type , false ) ;"
GCC,nvptx,179,"Predict the next statement of this code snippet:
 <s> unsigned inner_mask = par -> mask ; if ( par -> inner ) { par -> inner_mask = nvptx_process_pars ( par -> inner ) ; inner_mask |= par -> inner_mask ; } if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) ; else if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) { nvptx_wpropagate ( false , par -> forked_block , par -> forked_insn ) ;"
GCC,nvptx,180,"Predict the next statement of this code snippet:
 <s> par -> inner_mask = nvptx_process_pars ( par -> inner ) ; inner_mask |= par -> inner_mask ; } if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) ; else if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) { nvptx_wpropagate ( false , par -> forked_block , par -> forked_insn ) ; nvptx_wpropagate ( true , par -> forked_block , par -> fork_insn ) ; emit_insn_after ( nvptx_wsync ( false ) , par -> forked_insn ) ; emit_insn_before ( nvptx_wsync ( true ) , par -> joining_insn ) ; } else if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) nvptx_vpropagate ( par -> forked_block , par -> forked_insn ) ;"
GCC,nvptx,181,"Predict the next statement of this code snippet:
 <s> bitmap live = DF_LIVE_IN ( block ) ; bitmap_iterator iterator ; unsigned ix ; HOST_WIDE_INT fs = get_frame_size ( ) ; if ( fs ) { rtx tmp = gen_reg_rtx ( DImode ) ; rtx idx = NULL_RTX ; rtx ptr = gen_reg_rtx ( Pmode ) ; rtx pred = NULL_RTX ; rtx_code_label * label = NULL ; gcc_assert ( ! ( fs & ( GET_MODE_SIZE ( DImode ) - <NUM_LIT> ) ) ) ; fs /= GET_MODE_SIZE ( DImode ) ; if ( fs == <NUM_LIT> ) fs = <NUM_LIT> ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( ptr , frame_pointer_rtx ) ) ; if ( fs ) { idx = gen_reg_rtx ( SImode ) ; pred = gen_reg_rtx ( BImode ) ; label = gen_label_rtx ( ) ; emit_insn ( gen_rtx_SET ( idx , GEN_INT ( fs ) ) ) ; rtx init = fn ( tmp , PM_loop_begin , fs , data ) ; if ( init ) emit_insn ( init ) ; emit_label ( label ) ; LABEL_NUSES ( label ) ++ ; emit_insn ( gen_addsi3 ( idx , idx , GEN_INT ( - <NUM_LIT> ) ) ) ;"
GCC,nvptx,182,"Predict the next statement of this code snippet:
 <s> if ( fs ) { idx = gen_reg_rtx ( SImode ) ; pred = gen_reg_rtx ( BImode ) ; label = gen_label_rtx ( ) ; emit_insn ( gen_rtx_SET ( idx , GEN_INT ( fs ) ) ) ; rtx init = fn ( tmp , PM_loop_begin , fs , data ) ; if ( init ) emit_insn ( init ) ; emit_label ( label ) ; LABEL_NUSES ( label ) ++ ; emit_insn ( gen_addsi3 ( idx , idx , GEN_INT ( - <NUM_LIT> ) ) ) ; } if ( rw & PM_read ) emit_insn ( gen_rtx_SET ( tmp , gen_rtx_MEM ( DImode , ptr ) ) ) ; emit_insn ( fn ( tmp , rw , fs , data ) ) ; if ( rw & PM_write ) emit_insn ( gen_rtx_SET ( gen_rtx_MEM ( DImode , ptr ) , tmp ) ) ; if ( fs ) { emit_insn ( gen_rtx_SET ( pred , gen_rtx_NE ( BImode , idx , const0_rtx ) ) ) ; emit_insn ( gen_adddi3 ( ptr , ptr , GEN_INT ( GET_MODE_SIZE ( DImode ) ) ) ) ; emit_insn ( gen_br_true_uni ( pred , label ) ) ; rtx fini = fn ( tmp , PM_loop_end , fs , data ) ; if ( fini ) emit_insn ( fini ) ; emit_insn ( gen_rtx_CLOBBER ( GET_MODE ( idx ) , idx ) ) ; } emit_insn ( gen_rtx_CLOBBER ( GET_MODE ( tmp ) , tmp ) ) ; emit_insn ( gen_rtx_CLOBBER ( GET_MODE ( ptr ) , ptr ) ) ; rtx cpy = get_insns ( ) ; end_sequence ( ) ; insn = emit_insn_after ( cpy , insn ) ; }"
GCC,nvptx,183,"Predict the next statement of this code snippet:
 <s> tree dims = TREE_VALUE ( attr ) ; unsigned ix ; fprintf ( asm_out_file , <STR_LIT> , IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ; for ( ix = <NUM_LIT> ; ix != GOMP_DIM_MAX ; ix ++ , dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; gcc_assert ( ! TREE_PURPOSE ( dims ) ) ; fprintf ( asm_out_file , <STR_LIT> , size ) ; }"
GCC,nvptx,184,"Predict the next statement of this code snippet:
 <s> for ( int i = LAST_VIRTUAL_REGISTER + <NUM_LIT> ; i < max_regs ; i ++ ) if ( REG_N_SETS ( i ) == <NUM_LIT> && REG_N_REFS ( i ) == <NUM_LIT> ) regno_reg_rtx [ i ] = const0_rtx ; tree attr = get_oacc_fn_attrib ( current_function_decl ) ; if ( attr ) { unsigned mask = <NUM_LIT> ; tree dims = TREE_VALUE ( attr ) ; unsigned ix ; for ( ix = <NUM_LIT> ; ix != GOMP_DIM_MAX ; ix ++ , dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; tree allowed = TREE_PURPOSE ( dims ) ; if ( size != <NUM_LIT> && ! ( allowed && integer_zerop ( allowed ) ) ) mask |= GOMP_DIM_MASK ( ix ) ; } gcc_assert ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ; parallel * pars = nvptx_discover_pars ( & bb_insn_map ) ; nvptx_process_pars ( pars ) ; nvptx_neuter_pars ( pars , mask , <NUM_LIT> ) ; delete pars ; } nvptx_reorg_subreg ( ) ;"
GCC,nvptx,185,"Predict the next statement of this code snippet:
 <s> compute_bb_for_insn ( ) ; thread_prologue_and_epilogue_insns ( ) ; bb_insn_map_t bb_insn_map ; nvptx_split_blocks ( & bb_insn_map ) ; df_clear_flags ( DF_LR_RUN_DCE ) ; df_set_flags ( DF_NO_INSN_RESCAN | DF_NO_HARD_REGS ) ; df_live_add_problem ( ) ; df_live_set_all_dirty ( ) ; df_analyze ( ) ; regstat_init_n_sets_and_refs ( ) ; if ( dump_file ) df_dump ( dump_file ) ; int max_regs = max_reg_num ( ) ; for ( int i = LAST_VIRTUAL_REGISTER + <NUM_LIT> ; i < max_regs ; i ++ ) if ( REG_N_SETS ( i ) == <NUM_LIT> && REG_N_REFS ( i ) == <NUM_LIT> ) regno_reg_rtx [ i ] = const0_rtx ; tree attr = get_oacc_fn_attrib ( current_function_decl ) ; if ( attr ) { unsigned mask = <NUM_LIT> ; tree dims = TREE_VALUE ( attr ) ; unsigned ix ; for ( ix = <NUM_LIT> ; ix != GOMP_DIM_MAX ; ix ++ , dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; tree allowed = TREE_PURPOSE ( dims ) ; if ( size != <NUM_LIT> && ! ( allowed && integer_zerop ( allowed ) ) ) mask |= GOMP_DIM_MASK ( ix ) ;"
GCC,nvptx,186,"Predict the next statement of this code snippet:
 <s> for ( unsigned ix = <NUM_LIT> ; ix ; ix -- ) { vec < edge , va_gc > * edges = dir > <NUM_LIT> ? b -> succs : b -> preds ; size_t offset = ( dir > <NUM_LIT> ? offsetof ( edge_def , dest ) : offsetof ( edge_def , src ) ) ; edge e ; edge_iterator ( ei ) ; FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( target -> flags & BB_VISITED ) n = nvptx_sese_number ( n , p , dir , target , list ) ;"
GCC,nvptx,187,"Predict the next statement of this code snippet:
 <s> edge e ; edge_iterator ( ei ) ; FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( target -> flags & BB_VISITED ) n = nvptx_sese_number ( n , p , dir , target , list ) ; } dir = - dir ; } return n ;"
GCC,nvptx,188,"Predict the next statement of this code snippet:
 <s> sese -> remove ( pseudo_node_t ( me , dir ) ) ; FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( bb_sese * t_sese = BB_GET_SESE ( target ) ) { if ( t_sese -> node < sese -> node + dir && ! ( dir < <NUM_LIT> && sese -> parent == t_sese -> node ) ) sese -> push ( pseudo_node_t ( target , usd * t_sese -> dir ) ) ; } else { sese -> push ( pseudo_node_t ( <NUM_LIT> , <NUM_LIT> ) ) ; } } if ( ! sese -> brackets . length ( ) || ! edges || ! edges -> length ( ) ) { hi_back = <NUM_LIT> ; node_back = pseudo_node_t ( <NUM_LIT> , <NUM_LIT> ) ; sese -> push ( node_back ) ; } sese -> high = hi_back < hi_child ? node_back : node_child ; if ( num_children > <NUM_LIT> ) { hi_child = depth ; if ( dir < <NUM_LIT> && child ) { node_child = sese -> high ; hi_child = node_child . second ; if ( node_child . first ) hi_child += BB_GET_SESE ( node_child . first ) -> node ; } FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( target == child ) continue ; bb_sese * t_sese = BB_GET_SESE ( target ) ; if ( ! t_sese ) continue ; if ( t_sese -> parent != sese -> node ) continue ; int t_hi = t_sese -> high . second ; if ( basic_block child_hi_block = t_sese -> high . first ) t_hi += BB_GET_SESE ( child_hi_block ) -> node ; if ( hi_child > t_hi ) { hi_child = t_hi ; node_child = t_sese -> high ; } } sese -> push ( node_child ) ;"
GCC,nvptx,189,"Predict the next statement of this code snippet:
 <s> node_back = pseudo_node_t ( <NUM_LIT> , <NUM_LIT> ) ; } } sese -> remove ( pseudo_node_t ( me , dir ) ) ; FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( bb_sese * t_sese = BB_GET_SESE ( target ) ) { if ( t_sese -> node < sese -> node + dir && ! ( dir < <NUM_LIT> && sese -> parent == t_sese -> node ) ) sese -> push ( pseudo_node_t ( target , usd * t_sese -> dir ) ) ; } else { sese -> push ( pseudo_node_t ( <NUM_LIT> , <NUM_LIT> ) ) ; } } if ( ! sese -> brackets . length ( ) || ! edges || ! edges -> length ( ) ) { hi_back = <NUM_LIT> ; node_back = pseudo_node_t ( <NUM_LIT> , <NUM_LIT> ) ; sese -> push ( node_back ) ; } sese -> high = hi_back < hi_child ? node_back : node_child ; if ( num_children > <NUM_LIT> ) { hi_child = depth ; if ( dir < <NUM_LIT> && child ) { node_child = sese -> high ; hi_child = node_child . second ; if ( node_child . first ) hi_child += BB_GET_SESE ( node_child . first ) -> node ; } FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( target == child ) continue ; bb_sese * t_sese = BB_GET_SESE ( target ) ; if ( ! t_sese ) continue ; if ( t_sese -> parent != sese -> node ) continue ; int t_hi = t_sese -> high . second ; if ( basic_block child_hi_block = t_sese -> high . first ) t_hi += BB_GET_SESE ( child_hi_block ) -> node ; if ( hi_child > t_hi ) { hi_child = t_hi ; node_child = t_sese -> high ;"
GCC,nvptx,190,"Predict the next statement of this code snippet:
 <s> else { cond_branch = SET_SRC ( tail_branch ) ; if ( GET_CODE ( cond_branch ) != IF_THEN_ELSE ) cond_branch = NULL_RTX ; } } if ( tail == head ) { if ( ! head || ! INSN_P ( head ) ) return ; switch ( recog_memoized ( head ) ) { default : break ; case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : return ; } if ( cond_branch ) { if ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) skip_mask = <NUM_LIT> ; } else if ( tail_branch ) return ; } unsigned mode ; rtx_insn * before = tail ; for ( mode = GOMP_DIM_WORKER ; mode <= GOMP_DIM_VECTOR ; mode ++ ) if ( GOMP_DIM_MASK ( mode ) & skip_mask ) { rtx_code_label * label = gen_label_rtx ( ) ; rtx pred = cfun -> machine -> axis_predicate [ mode - GOMP_DIM_WORKER ] ; if ( ! pred ) { pred = gen_reg_rtx ( BImode ) ; cfun -> machine -> axis_predicate [ mode - GOMP_DIM_WORKER ] = pred ; } rtx br ; if ( mode == GOMP_DIM_VECTOR ) br = gen_br_true ( pred , label ) ; else br = gen_br_true_uni ( pred , label ) ; emit_insn_before ( br , head ) ; LABEL_NUSES ( label ) ++ ; if ( tail_branch ) before = emit_label_before ( label , before ) ; else emit_label_after ( label , tail ) ; } if ( cond_branch ) { rtx pvar = XEXP ( XEXP ( cond_branch , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) == mask ) { emit_insn_before ( nvptx_gen_vcast ( pvar ) , tail ) ; } else { wcast_data_t data ; data . base = worker_bcast_sym ; data . ptr = <NUM_LIT> ; if ( worker_bcast_size < GET_MODE_SIZE ( SImode ) ) worker_bcast_size = GET_MODE_SIZE ( SImode ) ; data . offset = <NUM_LIT> ; emit_insn_before ( nvptx_gen_wcast ( pvar , PM_read , <NUM_LIT> , & data ) , before ) ; emit_insn_before ( nvptx_wsync ( false ) , tail ) ;"
GCC,nvptx,191,"Predict the next statement of this code snippet:
 <s> } if ( tail == head ) { if ( ! head || ! INSN_P ( head ) ) return ; switch ( recog_memoized ( head ) ) { default : break ; case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : return ; } if ( cond_branch ) { if ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) skip_mask = <NUM_LIT> ; } else if ( tail_branch ) return ; } unsigned mode ; rtx_insn * before = tail ; for ( mode = GOMP_DIM_WORKER ; mode <= GOMP_DIM_VECTOR ; mode ++ ) if ( GOMP_DIM_MASK ( mode ) & skip_mask ) { rtx_code_label * label = gen_label_rtx ( ) ; rtx pred = cfun -> machine -> axis_predicate [ mode - GOMP_DIM_WORKER ] ; if ( ! pred ) { pred = gen_reg_rtx ( BImode ) ; cfun -> machine -> axis_predicate [ mode - GOMP_DIM_WORKER ] = pred ; } rtx br ; if ( mode == GOMP_DIM_VECTOR ) br = gen_br_true ( pred , label ) ; else br = gen_br_true_uni ( pred , label ) ; emit_insn_before ( br , head ) ; LABEL_NUSES ( label ) ++ ; if ( tail_branch ) before = emit_label_before ( label , before ) ; else emit_label_after ( label , tail ) ; } if ( cond_branch ) { rtx pvar = XEXP ( XEXP ( cond_branch , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) == mask ) { emit_insn_before ( nvptx_gen_vcast ( pvar ) , tail ) ; } else { wcast_data_t data ; data . base = worker_bcast_sym ; data . ptr = <NUM_LIT> ; if ( worker_bcast_size < GET_MODE_SIZE ( SImode ) ) worker_bcast_size = GET_MODE_SIZE ( SImode ) ; data . offset = <NUM_LIT> ; emit_insn_before ( nvptx_gen_wcast ( pvar , PM_read , <NUM_LIT> , & data ) , before ) ; emit_insn_before ( nvptx_wsync ( false ) , tail ) ; data . offset = <NUM_LIT> ; emit_insn_before ( nvptx_gen_wcast ( pvar , PM_write , <NUM_LIT> , & data ) , tail ) ; emit_insn_before ( nvptx_wsync ( true ) , tail ) ;"
GCC,nvptx,192,"Predict the next statement of this code snippet:
 <s> static void nvptx_vpropagate ( basic_block block , rtx_insn * insn ) { nvptx_propagate ( block , insn , PM_read_write , vprop_gen , <NUM_LIT> ) ;"
GCC,nvptx,193,"Predict the next statement of this code snippet:
 <s> rtx init = gen_rtx_SET ( data . base , worker_bcast_sym ) ; emit_insn_after ( init , insn ) ; if ( worker_bcast_size < data . offset ) worker_bcast_size = data . offset ; }"
GCC,nvptx,194,"Predict the next statement of this code snippet:
 <s> data . ptr = NULL_RTX ; nvptx_propagate ( block , insn , pre_p ? PM_read : PM_write , wprop_gen , & data ) ; if ( data . offset ) {"
GCC,nvptx,195,"Predict the next statement of this code snippet:
 <s> return gen_nvptx_barsync ( GEN_INT ( after ) ) ;"
GCC,nvptx,196,"Predict the next statement of this code snippet:
 <s> if ( sym ) { fprintf ( asm_out_file , <STR_LIT> ) ; output_address ( VOIDmode , sym ) ; fprintf ( asm_out_file , val ? <STR_LIT> : <STR_LIT> ) ;"
GCC,nvptx,197,"Predict the next statement of this code snippet:
 <s> if ( ! ( pm & PM_read_write ) ) return <NUM_LIT> ; return nvptx_gen_vcast ( reg ) ;"
GCC,nvptx,198,"Predict the next statement of this code snippet:
 <s> static rtx wprop_gen ( rtx reg , propagate_mask pm , unsigned rep , void * data_ ) { wcast_data_t * data = ( wcast_data_t * ) data_ ; if ( pm & PM_loop_begin ) { unsigned align = GET_MODE_ALIGNMENT ( GET_MODE ( reg ) ) / BITS_PER_UNIT ; if ( align > worker_bcast_align ) worker_bcast_align = align ; data -> offset = ( data -> offset + align - <NUM_LIT> ) & ~ ( align - <NUM_LIT> ) ; data -> ptr = gen_reg_rtx ( Pmode ) ;"
GCC,nvptx,199,"Predict the next statement of this code snippet:
 <s> if ( flag_openacc && optval ) error ( <STR_LIT> , optname ) ;"
GCC,nvptx,200,"Predict the next statement of this code snippet:
 <s> if ( flag_openacc && optval ) error ( <STR_LIT> , optname ) ;"
GCC,nvptx,201,"Predict the next statement of this code snippet:
 <s> write_var_marker ( file , false , TREE_PUBLIC ( decl ) , name ) ; fprintf ( file , <STR_LIT> ) ; tree size = DECL_SIZE_UNIT ( decl ) ; nvptx_assemble_decl_begin ( file , name , section_for_decl ( decl ) , TREE_TYPE ( decl ) , size ? tree_to_shwi ( size ) : <NUM_LIT> , DECL_ALIGN ( decl ) ) ; nvptx_assemble_decl_end ( ) ;"
GCC,nvptx,202,"Predict the next statement of this code snippet:
 <s> if ( DECL_WEAK ( decl ) ) error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> <STR_LIT> ) ; write_var_marker ( file , false , TREE_PUBLIC ( decl ) , name ) ; fprintf ( file , <STR_LIT> ) ; tree size = DECL_SIZE_UNIT ( decl ) ;"
GCC,nvptx,203,"Predict the next statement of this code snippet:
 <s> if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> has_chain ) write_arg_type ( s , STATIC_CHAIN_REGNUM , DECL_STATIC_CHAIN ( decl ) ? argno : - <NUM_LIT> , ptr_type_node , true ) ; fprintf ( file , <STR_LIT> , s . str ( ) . c_str ( ) ) ; if ( ! crtl -> is_leaf ) crtl -> is_leaf = leaf_function_p ( ) ; HOST_WIDE_INT sz = get_frame_size ( ) ; bool need_frameptr = sz || cfun -> machine -> has_chain ; int alignment = crtl -> stack_alignment_needed / BITS_PER_UNIT ; if ( ! TARGET_SOFT_STACK ) { if ( cfun -> machine -> has_varadic ) init_frame ( file , STACK_POINTER_REGNUM , UNITS_PER_WORD , crtl -> outgoing_args_size ) ; if ( need_frameptr ) init_frame ( file , FRAME_POINTER_REGNUM , alignment , ROUND_UP ( sz , GET_MODE_SIZE ( DImode ) ) ) ; } else if ( need_frameptr || cfun -> machine -> has_varadic || cfun -> calls_alloca || ( cfun -> machine -> has_simtreg && ! crtl -> is_leaf ) ) init_softstack_frame ( file , alignment , sz ) ; if ( cfun -> machine -> has_simtreg ) { unsigned HOST_WIDE_INT & simtsz = cfun -> machine -> simt_stack_size ; unsigned HOST_WIDE_INT & align = cfun -> machine -> simt_stack_align ; align = MAX ( align , GET_MODE_SIZE ( DImode ) ) ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) simtsz = HOST_WIDE_INT_M1U ; if ( simtsz == HOST_WIDE_INT_M1U ) simtsz = nvptx_softstack_size ; if ( cfun -> machine -> has_softstack ) simtsz += POINTER_SIZE / <NUM_LIT> ; simtsz = ROUND_UP ( simtsz , GET_MODE_SIZE ( DImode ) ) ; if ( align > GET_MODE_SIZE ( DImode ) ) simtsz += align - GET_MODE_SIZE ( DImode ) ; if ( simtsz ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , simtsz ) ; } int maxregs = max_reg_num ( ) ; for ( int i = LAST_VIRTUAL_REGISTER + <NUM_LIT> ; i < maxregs ; i ++ ) { if ( regno_reg_rtx [ i ] != const0_rtx ) { machine_mode mode = PSEUDO_REGNO_MODE ( i ) ; machine_mode split = maybe_split_mode ( mode ) ;"
GCC,nvptx,204,"Predict the next statement of this code snippet:
 <s> if ( worker_red_size ) write_worker_buffer ( asm_out_file , worker_red_sym , worker_red_align , worker_red_size ) ; if ( need_softstack_decl ) { write_var_marker ( asm_out_file , false , true , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , POINTER_SIZE ) ; } if ( need_unisimt_decl ) { write_var_marker ( asm_out_file , false , true , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,nvptx,205,"Predict the next statement of this code snippet:
 <s> nvptx_function_end ( STREAM ) { \ <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , \ <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> \ }"
GCC,nvptx,206,"Predict the next statement of this code snippet:
 <s> nvptx_function_end ( STREAM ) { \ <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , \ <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> \ }"
GCC,nvptx,207,"Predict the next statement of this code snippet:
 <s> case DImode : case DFmode : { rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; emit_insn ( nvptx_gen_unpack ( tmp0 , tmp1 , src ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp0 , tmp0 , idx , kind ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp1 , tmp1 , idx , kind ) ) ; emit_insn ( nvptx_gen_pack ( dst , tmp0 , tmp1 ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; case BImode : { rtx tmp = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; emit_insn ( gen_sel_truesi ( tmp , src , GEN_INT ( <NUM_LIT> ) , const0_rtx ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp , tmp , idx , kind ) ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_NE ( BImode , tmp , const0_rtx ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ;"
GCC,nvptx,208,"Predict the next statement of this code snippet:
 <s> bool changed = false ; if ( fn_level <= GOMP_DIM_VECTOR && fn_level >= - <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] >= <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] != PTX_VECTOR_LENGTH ) { if ( fn_level < <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] >= <NUM_LIT> ) warning_at ( decl ? DECL_SOURCE_LOCATION ( decl ) : UNKNOWN_LOCATION , <NUM_LIT> , dims [ GOMP_DIM_VECTOR ] ? G_ ( <STR_LIT> ) : G_ ( <STR_LIT> ) , PTX_VECTOR_LENGTH , dims [ GOMP_DIM_VECTOR ] ) ; dims [ GOMP_DIM_VECTOR ] = PTX_VECTOR_LENGTH ; changed = true ; } if ( dims [ GOMP_DIM_WORKER ] > PTX_WORKER_LENGTH ) { warning_at ( decl ? DECL_SOURCE_LOCATION ( decl ) : UNKNOWN_LOCATION , <NUM_LIT> , <STR_LIT> , PTX_WORKER_LENGTH , dims [ GOMP_DIM_WORKER ] ) ; dims [ GOMP_DIM_WORKER ] = PTX_WORKER_LENGTH ; changed = true ; } if ( ! decl ) {"
GCC,nvptx,209,"Predict the next statement of this code snippet:
 <s> if ( fn_level <= GOMP_DIM_VECTOR && fn_level >= - <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] >= <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] != PTX_VECTOR_LENGTH ) { if ( fn_level < <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] >= <NUM_LIT> ) warning_at ( decl ? DECL_SOURCE_LOCATION ( decl ) : UNKNOWN_LOCATION , <NUM_LIT> , dims [ GOMP_DIM_VECTOR ] ? G_ ( <STR_LIT> ) : G_ ( <STR_LIT> ) , PTX_VECTOR_LENGTH , dims [ GOMP_DIM_VECTOR ] ) ; dims [ GOMP_DIM_VECTOR ] = PTX_VECTOR_LENGTH ; changed = true ; } if ( dims [ GOMP_DIM_WORKER ] > PTX_WORKER_LENGTH ) {"
GCC,nvptx,210,"Predict the next statement of this code snippet:
 <s> if ( ! global_options_set . x_flag_no_common ) flag_no_common = <NUM_LIT> ; flag_var_tracking = <NUM_LIT> ; if ( nvptx_optimize < <NUM_LIT> ) nvptx_optimize = optimize > <NUM_LIT> ; declared_fndecls_htab = hash_table < tree_hasher > :: create_ggc ( <NUM_LIT> ) ; needed_fndecls_htab = hash_table < tree_hasher > :: create_ggc ( <NUM_LIT> ) ; declared_libfuncs_htab = hash_table < declared_libfunc_hasher > :: create_ggc ( <NUM_LIT> ) ; worker_bcast_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( worker_bcast_sym , DATA_AREA_SHARED ) ; worker_bcast_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; worker_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( worker_red_sym , DATA_AREA_SHARED ) ; worker_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; diagnose_openacc_conflict ( TARGET_GOMP , <STR_LIT> ) ; diagnose_openacc_conflict ( TARGET_SOFT_STACK , <STR_LIT> ) ;"
GCC,nvptx,211,"Predict the next statement of this code snippet:
 <s> } else output_address ( VOIDmode , callee ) ; const char * open = <STR_LIT> ; for ( int argno = <NUM_LIT> ; argno < arg_end ; argno ++ ) { fprintf ( asm_out_file , <STR_LIT> , open , argno ) ; open = <STR_LIT> ; } if ( decl && DECL_STATIC_CHAIN ( decl ) ) { fprintf ( asm_out_file , <STR_LIT> , open , reg_names [ STATIC_CHAIN_REGNUM ] ) ; open = <STR_LIT> ; } if ( ! open [ <NUM_LIT> ] ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( needs_tgt ) { fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , buf ) ; } fprintf ( asm_out_file , <STR_LIT> ) ; if ( find_reg_note ( insn , REG_NORETURN , NULL ) ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( result ) { static char rval [ sizeof ( <STR_LIT> ) + <NUM_LIT> ] ; if ( ! rval [ <NUM_LIT> ] ) sprintf ( rval , <STR_LIT> , reg_names [ NVPTX_RETURN_REGNUM ] ) ; return rval ; } return <STR_LIT> ;"
GCC,nvptx,212,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> , bits , regno , regno ) ; if ( CONST_INT_P ( size ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC , ROUND_UP ( UINTVAL ( size ) , GET_MODE_SIZE ( DImode ) ) ) ; else output_reg ( file , REGNO ( size ) , VOIDmode ) ; fputs ( <STR_LIT> , file ) ; if ( ! CONST_INT_P ( size ) || UINTVAL ( align ) > GET_MODE_SIZE ( DImode ) ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , bits , regno , regno , UINTVAL ( align ) ) ; } if ( cfun -> machine -> has_softstack ) { const char * reg_stack = reg_names [ STACK_POINTER_REGNUM ] ; if ( entering ) { fprintf ( file , <STR_LIT> , bits , regno , bits / <NUM_LIT> , reg_stack ) ; fprintf ( file , <STR_LIT> , bits , reg_stack , regno , bits / <NUM_LIT> ) ;"
GCC,nvptx,213,"Predict the next statement of this code snippet:
 <s> if ( rw & PM_write ) emit_insn ( gen_rtx_SET ( gen_rtx_MEM ( DImode , ptr ) , tmp ) ) ; if ( fs ) { emit_insn ( gen_rtx_SET ( pred , gen_rtx_NE ( BImode , idx , const0_rtx ) ) ) ; emit_insn ( gen_adddi3 ( ptr , ptr , GEN_INT ( GET_MODE_SIZE ( DImode ) ) ) ) ; emit_insn ( gen_br_true_uni ( pred , label ) ) ; rtx fini = fn ( tmp , PM_loop_end , fs , data ) ; if ( fini ) emit_insn ( fini ) ; emit_insn ( gen_rtx_CLOBBER ( GET_MODE ( idx ) , idx ) ) ; } emit_insn ( gen_rtx_CLOBBER ( GET_MODE ( tmp ) , tmp ) ) ; emit_insn ( gen_rtx_CLOBBER ( GET_MODE ( ptr ) , ptr ) ) ; rtx cpy = get_insns ( ) ; end_sequence ( ) ; insn = emit_insn_after ( cpy , insn ) ; } EXECUTE_IF_SET_IN_BITMAP ( live , <NUM_LIT> , ix , iterator ) {"
GCC,nvptx,214,"Predict the next statement of this code snippet:
 <s> tree attr = oacc_get_fn_attrib ( current_function_decl ) ; if ( attr ) { unsigned mask = <NUM_LIT> ; tree dims = TREE_VALUE ( attr ) ; unsigned ix ; for ( ix = <NUM_LIT> ; ix != GOMP_DIM_MAX ; ix ++ , dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; tree allowed = TREE_PURPOSE ( dims ) ; if ( size != <NUM_LIT> && ! ( allowed && integer_zerop ( allowed ) ) ) mask |= GOMP_DIM_MASK ( ix ) ; } gcc_assert ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ; parallel * pars = nvptx_discover_pars ( & bb_insn_map ) ;"
GCC,nvptx,215,"Predict the next statement of this code snippet:
 <s> unsigned ix ; for ( ix = <NUM_LIT> ; ix != GOMP_DIM_MAX ; ix ++ , dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; tree allowed = TREE_PURPOSE ( dims ) ; if ( size != <NUM_LIT> && ! ( allowed && integer_zerop ( allowed ) ) ) mask |= GOMP_DIM_MASK ( ix ) ; } gcc_assert ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ; parallel * pars = nvptx_discover_pars ( & bb_insn_map ) ; nvptx_process_pars ( pars ) ; nvptx_neuter_pars ( pars , mask , <NUM_LIT> ) ; delete pars ; } nvptx_reorg_subreg ( ) ; if ( TARGET_UNIFORM_SIMT ) nvptx_reorg_uniform_simt ( ) ; regstat_free_n_sets_and_refs ( ) ;"
GCC,nvptx,216,"Predict the next statement of this code snippet:
 <s> static int nvptx_simt_vf ( ) { return PTX_VECTOR_LENGTH ;"
GCC,nvptx,217,"Predict the next statement of this code snippet:
 <s> static int nvptx_simt_vf ( ) {"
GCC,nvptx,218,"Predict the next statement of this code snippet:
 <s> if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> has_chain ) write_arg_type ( s , STATIC_CHAIN_REGNUM , DECL_STATIC_CHAIN ( decl ) ? argno : - <NUM_LIT> , ptr_type_node , true ) ; fprintf ( file , <STR_LIT> , s . str ( ) . c_str ( ) ) ; if ( ! crtl -> is_leaf ) crtl -> is_leaf = leaf_function_p ( ) ; HOST_WIDE_INT sz = get_frame_size ( ) ; bool need_frameptr = sz || cfun -> machine -> has_chain ; int alignment = crtl -> stack_alignment_needed / BITS_PER_UNIT ; if ( ! TARGET_SOFT_STACK ) { if ( cfun -> machine -> has_varadic ) init_frame ( file , STACK_POINTER_REGNUM , UNITS_PER_WORD , crtl -> outgoing_args_size ) ; if ( need_frameptr ) init_frame ( file , FRAME_POINTER_REGNUM , alignment , ROUND_UP ( sz , GET_MODE_SIZE ( DImode ) ) ) ; } else if ( need_frameptr || cfun -> machine -> has_varadic || cfun -> calls_alloca || ( cfun -> machine -> has_simtreg && ! crtl -> is_leaf ) ) init_softstack_frame ( file , alignment , sz ) ; if ( cfun -> machine -> has_simtreg ) { unsigned HOST_WIDE_INT & simtsz = cfun -> machine -> simt_stack_size ; unsigned HOST_WIDE_INT & align = cfun -> machine -> simt_stack_align ; align = MAX ( align , GET_MODE_SIZE ( DImode ) ) ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) simtsz = HOST_WIDE_INT_M1U ;"
GCC,nvptx,219,"Predict the next statement of this code snippet:
 <s> write_omp_entry ( file , name , buf ) ; name = buf ; } std :: stringstream s ; write_fn_proto ( s , true , name , decl ) ; s << <STR_LIT> ; bool return_in_mem = write_return_type ( s , false , result_type ) ; if ( return_in_mem ) argno = write_arg_type ( s , <NUM_LIT> , argno , ptr_type_node , true ) ; tree args = TYPE_ARG_TYPES ( fntype ) ; bool prototyped = true ; if ( ! args ) { args = DECL_ARGUMENTS ( decl ) ; prototyped = false ; } for ( ; args != NULL_TREE ; args = TREE_CHAIN ( args ) ) { tree type = prototyped ? TREE_VALUE ( args ) : TREE_TYPE ( args ) ; argno = write_arg_type ( s , <NUM_LIT> , argno , type , prototyped ) ; } if ( stdarg_p ( fntype ) ) argno = write_arg_type ( s , ARG_POINTER_REGNUM , argno , ptr_type_node , true ) ; if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> has_chain ) write_arg_type ( s , STATIC_CHAIN_REGNUM , DECL_STATIC_CHAIN ( decl ) ? argno : - <NUM_LIT> , ptr_type_node , true ) ; fprintf ( file , <STR_LIT> , s . str ( ) . c_str ( ) ) ; if ( ! crtl -> is_leaf ) crtl -> is_leaf = leaf_function_p ( ) ; HOST_WIDE_INT sz = get_frame_size ( ) ; bool need_frameptr = sz || cfun -> machine -> has_chain ; int alignment = crtl -> stack_alignment_needed / BITS_PER_UNIT ; if ( ! TARGET_SOFT_STACK ) { if ( cfun -> machine -> has_varadic ) init_frame ( file , STACK_POINTER_REGNUM , UNITS_PER_WORD , crtl -> outgoing_args_size ) ; if ( need_frameptr ) init_frame ( file , FRAME_POINTER_REGNUM , alignment , ROUND_UP ( sz , GET_MODE_SIZE ( DImode ) ) ) ; } else if ( need_frameptr || cfun -> machine -> has_varadic || cfun -> calls_alloca || ( cfun -> machine -> has_simtreg && ! crtl -> is_leaf ) ) init_softstack_frame ( file , alignment , sz ) ; if ( cfun -> machine -> has_simtreg ) { unsigned HOST_WIDE_INT & simtsz = cfun -> machine -> simt_stack_size ; unsigned HOST_WIDE_INT & align = cfun -> machine -> simt_stack_align ; align = MAX ( align , GET_MODE_SIZE ( DImode ) ) ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) simtsz = HOST_WIDE_INT_M1U ; if ( simtsz == HOST_WIDE_INT_M1U ) simtsz = nvptx_softstack_size ; if ( cfun -> machine -> has_softstack ) simtsz += POINTER_SIZE / <NUM_LIT> ; simtsz = ROUND_UP ( simtsz , GET_MODE_SIZE ( DImode ) ) ; if ( align > GET_MODE_SIZE ( DImode ) ) simtsz += align - GET_MODE_SIZE ( DImode ) ; if ( simtsz ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , simtsz ) ;"
GCC,nvptx,220,"Predict the next statement of this code snippet:
 <s> return par ; case CODE_FOR_nvptx_forked : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , <NUM_LIT> , <NUM_LIT> ) ) ; gcc_assert ( mask ) ; par = new parallel ( par , mask ) ; par -> forked_block = block ; par -> forked_insn = end ; if ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) par -> fork_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_fork ) ; } break ; case CODE_FOR_nvptx_join : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , <NUM_LIT> , <NUM_LIT> ) ) ; gcc_assert ( par -> mask == mask ) ; par -> join_block = block ; par -> join_insn = end ; if ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) par -> joining_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_joining ) ; par = par -> parent ; } break ; default : gcc_unreachable ( ) ; } }"
GCC,nvptx,221,"Predict the next statement of this code snippet:
 <s> break ; default : { rtx addr = data -> ptr ; if ( ! addr ) { unsigned align = GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ; if ( align > worker_bcast_align ) worker_bcast_align = align ; data -> offset = ( data -> offset + align - <NUM_LIT> ) & ~ ( align - <NUM_LIT> ) ; addr = data -> base ; if ( data -> offset ) addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( data -> offset ) ) ; } addr = gen_rtx_MEM ( mode , addr ) ; if ( pm == PM_read ) res = gen_rtx_SET ( addr , reg ) ; else if ( pm == PM_write ) res = gen_rtx_SET ( reg , addr ) ; else gcc_unreachable ( ) ; if ( data -> ptr ) { start_sequence ( ) ; emit_insn ( res ) ;"
GCC,nvptx,222,"Predict the next statement of this code snippet:
 <s> { rtx tmp = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; if ( pm & PM_read ) emit_insn ( gen_sel_truesi ( tmp , reg , GEN_INT ( <NUM_LIT> ) , const0_rtx ) ) ; emit_insn ( nvptx_gen_wcast ( tmp , pm , rep , data ) ) ; if ( pm & PM_write ) emit_insn ( gen_rtx_SET ( reg , gen_rtx_NE ( BImode , tmp , const0_rtx ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; default : { rtx addr = data -> ptr ; if ( ! addr ) { unsigned align = GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ; if ( align > worker_bcast_align ) worker_bcast_align = align ; data -> offset = ( data -> offset + align - <NUM_LIT> ) & ~ ( align - <NUM_LIT> ) ; addr = data -> base ; if ( data -> offset ) addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( data -> offset ) ) ; }"
GCC,nvptx,223,"Predict the next statement of this code snippet:
 <s> gimple * cond_stmt = gimple_build_cond ( NE_EXPR , tid , integer_zero_node , NULL_TREE , NULL_TREE ) ; gimple_call_set_lhs ( tid_call , tid ) ; gimple_seq_add_stmt ( & seq , tid_call ) ; gimple_seq_add_stmt ( & seq , cond_stmt ) ; edge init_edge = split_block ( gsi_bb ( gsi ) , call ) ; basic_block init_bb = init_edge -> dest ; basic_block call_bb = init_edge -> src ; init_edge -> flags ^= EDGE_FALLTHRU | EDGE_TRUE_VALUE ; init_edge -> probability = profile_probability :: even ( ) ; gimple_seq init_seq = NULL ; tree init_var = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( init_var , init , & init_seq ) ; gsi = gsi_start_bb ( init_bb ) ; gsi_insert_seq_before ( & gsi , init_seq , GSI_SAME_STMT ) ; gsi_prev ( & gsi ) ; edge inited_edge = split_block ( gsi_bb ( gsi ) , gsi_stmt ( gsi ) ) ; basic_block dst_bb = inited_edge -> dest ; edge nop_edge = make_edge ( call_bb , dst_bb , EDGE_FALSE_VALUE ) ; nop_edge -> probability = profile_probability :: even ( ) ; gphi * phi = create_phi_node ( lhs , dst_bb ) ; add_phi_arg ( phi , init_var , inited_edge , gimple_location ( call ) ) ; add_phi_arg ( phi , var , nop_edge , gimple_location ( call ) ) ; set_immediate_dominator ( CDI_DOMINATORS , dst_bb , call_bb ) ; gsi = gsi_for_stmt ( call ) ; } else {"
GCC,nvptx,224,"Predict the next statement of this code snippet:
 <s> tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , <NUM_LIT> ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; enum tree_code rcode = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; tree init = omp_reduction_init_op ( gimple_location ( call ) , rcode , TREE_TYPE ( var ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR ) { tree tid = make_ssa_name ( integer_type_node ) ; tree dim_vector = gimple_call_arg ( call , <NUM_LIT> ) ; gimple * tid_call = gimple_build_call_internal ( IFN_GOACC_DIM_POS , <NUM_LIT> , dim_vector ) ; gimple * cond_stmt = gimple_build_cond ( NE_EXPR , tid , integer_zero_node , NULL_TREE , NULL_TREE ) ; gimple_call_set_lhs ( tid_call , tid ) ; gimple_seq_add_stmt ( & seq , tid_call ) ; gimple_seq_add_stmt ( & seq , cond_stmt ) ; edge init_edge = split_block ( gsi_bb ( gsi ) , call ) ; basic_block init_bb = init_edge -> dest ; basic_block call_bb = init_edge -> src ; init_edge -> flags ^= EDGE_FALLTHRU | EDGE_TRUE_VALUE ; init_edge -> probability = profile_probability :: even ( ) ; gimple_seq init_seq = NULL ; tree init_var = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( init_var , init , & init_seq ) ; gsi = gsi_start_bb ( init_bb ) ; gsi_insert_seq_before ( & gsi , init_seq , GSI_SAME_STMT ) ; gsi_prev ( & gsi ) ; edge inited_edge = split_block ( gsi_bb ( gsi ) , gsi_stmt ( gsi ) ) ; basic_block dst_bb = inited_edge -> dest ;"
GCC,nvptx,225,"Predict the next statement of this code snippet:
 <s> static void nvptx_option_override ( void ) { init_machine_status = nvptx_init_machine_status ; if ( ! global_options_set . x_flag_toplevel_reorder ) flag_toplevel_reorder = <NUM_LIT> ; debug_nonbind_markers_p = <NUM_LIT> ; if ( ! global_options_set . x_flag_no_common ) flag_no_common = <NUM_LIT> ; if ( function_entry_patch_area_size > <NUM_LIT> ) sorry ( <STR_LIT> ) ; flag_var_tracking = <NUM_LIT> ; if ( nvptx_optimize < <NUM_LIT> ) nvptx_optimize = optimize > <NUM_LIT> ; declared_fndecls_htab = hash_table < tree_hasher > :: create_ggc ( <NUM_LIT> ) ; needed_fndecls_htab = hash_table < tree_hasher > :: create_ggc ( <NUM_LIT> ) ; declared_libfuncs_htab = hash_table < declared_libfunc_hasher > :: create_ggc ( <NUM_LIT> ) ; worker_bcast_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( worker_bcast_sym , DATA_AREA_SHARED ) ; worker_bcast_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; worker_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( worker_red_sym , DATA_AREA_SHARED ) ; worker_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ;"
GCC,nvptx,226,"Predict the next statement of this code snippet:
 <s> if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) { nvptx_wpropagate ( false , is_call , par -> forked_block , par -> forked_insn ) ; bool empty = nvptx_wpropagate ( true , is_call , par -> forked_block , par -> fork_insn ) ; if ( ! empty || ! is_call ) { emit_insn_before ( nvptx_wsync ( false ) , par -> forked_insn ) ; emit_insn_before ( nvptx_wsync ( true ) , par -> join_insn ) ; } }"
GCC,nvptx,227,"Predict the next statement of this code snippet:
 <s> start_sequence ( ) ; emit_insn ( gen_rtx_SET ( ptr , frame_pointer_rtx ) ) ; if ( fs ) { idx = gen_reg_rtx ( SImode ) ; pred = gen_reg_rtx ( BImode ) ; label = gen_label_rtx ( ) ; emit_insn ( gen_rtx_SET ( idx , GEN_INT ( fs ) ) ) ; rtx init = fn ( tmp , PM_loop_begin , fs , data ) ; if ( init ) emit_insn ( init ) ; emit_label ( label ) ; LABEL_NUSES ( label ) ++ ; emit_insn ( gen_addsi3 ( idx , idx , GEN_INT ( - <NUM_LIT> ) ) ) ; } if ( rw & PM_read ) emit_insn ( gen_rtx_SET ( tmp , gen_rtx_MEM ( DImode , ptr ) ) ) ; emit_insn ( fn ( tmp , rw , fs , data ) ) ; if ( rw & PM_write ) emit_insn ( gen_rtx_SET ( gen_rtx_MEM ( DImode , ptr ) , tmp ) ) ; if ( fs ) { emit_insn ( gen_rtx_SET ( pred , gen_rtx_NE ( BImode , idx , const0_rtx ) ) ) ; emit_insn ( gen_adddi3 ( ptr , ptr , GEN_INT ( GET_MODE_SIZE ( DImode ) ) ) ) ; emit_insn ( gen_br_true_uni ( pred , label ) ) ;"
GCC,nvptx,228,"Predict the next statement of this code snippet:
 <s> emit_insn ( gen_rtx_SET ( ptr , frame_pointer_rtx ) ) ; if ( fs ) { idx = gen_reg_rtx ( SImode ) ; pred = gen_reg_rtx ( BImode ) ; label = gen_label_rtx ( ) ; emit_insn ( gen_rtx_SET ( idx , GEN_INT ( fs ) ) ) ; rtx init = fn ( tmp , PM_loop_begin , fs , data ) ; if ( init ) emit_insn ( init ) ; emit_label ( label ) ; LABEL_NUSES ( label ) ++ ; emit_insn ( gen_addsi3 ( idx , idx , GEN_INT ( - <NUM_LIT> ) ) ) ; } if ( rw & PM_read ) emit_insn ( gen_rtx_SET ( tmp , gen_rtx_MEM ( DImode , ptr ) ) ) ; emit_insn ( fn ( tmp , rw , fs , data ) ) ; if ( rw & PM_write ) emit_insn ( gen_rtx_SET ( gen_rtx_MEM ( DImode , ptr ) , tmp ) ) ; if ( fs ) { emit_insn ( gen_rtx_SET ( pred , gen_rtx_NE ( BImode , idx , const0_rtx ) ) ) ; emit_insn ( gen_adddi3 ( ptr , ptr , GEN_INT ( GET_MODE_SIZE ( DImode ) ) ) ) ; emit_insn ( gen_br_true_uni ( pred , label ) ) ; rtx fini = fn ( tmp , PM_loop_end , fs , data ) ;"
GCC,nvptx,229,"Predict the next statement of this code snippet:
 <s> unsigned mask = <NUM_LIT> ; tree dims = TREE_VALUE ( attr ) ; unsigned ix ; for ( ix = <NUM_LIT> ; ix != GOMP_DIM_MAX ; ix ++ , dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; tree allowed = TREE_PURPOSE ( dims ) ; if ( size != <NUM_LIT> && ! ( allowed && integer_zerop ( allowed ) ) ) mask |= GOMP_DIM_MASK ( ix ) ; } gcc_assert ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ; parallel * pars = nvptx_discover_pars ( & bb_insn_map ) ; nvptx_process_pars ( pars ) ; nvptx_neuter_pars ( pars , mask , <NUM_LIT> ) ; delete pars ; }"
GCC,nvptx,230,"Predict the next statement of this code snippet:
 <s> df_live_set_all_dirty ( ) ; df_analyze ( ) ; regstat_init_n_sets_and_refs ( ) ; if ( dump_file ) df_dump ( dump_file ) ; int max_regs = max_reg_num ( ) ; for ( int i = LAST_VIRTUAL_REGISTER + <NUM_LIT> ; i < max_regs ; i ++ ) if ( REG_N_SETS ( i ) == <NUM_LIT> && REG_N_REFS ( i ) == <NUM_LIT> ) regno_reg_rtx [ i ] = const0_rtx ; tree attr = oacc_get_fn_attrib ( current_function_decl ) ; if ( attr ) {"
GCC,nvptx,231,"Predict the next statement of this code snippet:
 <s> static bool nvptx_vpropagate ( bool is_call , basic_block block , rtx_insn * insn ) { return nvptx_propagate ( is_call , block , insn , PM_read_write , vprop_gen , <NUM_LIT> ) ;"
GCC,nvptx,232,"Predict the next statement of this code snippet:
 <s> static bool nvptx_wpropagate ( bool pre_p , bool is_call , basic_block block , rtx_insn * insn ) { wcast_data_t data ; data . base = gen_reg_rtx ( Pmode ) ; data . offset = <NUM_LIT> ; data . ptr = NULL_RTX ; bool empty = nvptx_propagate ( is_call , block , insn , pre_p ? PM_read : PM_write , wprop_gen , & data ) ; gcc_assert ( empty == ! data . offset ) ; if ( data . offset ) { rtx init = gen_rtx_SET ( data . base , worker_bcast_sym ) ; emit_insn_after ( init , insn ) ; if ( worker_bcast_size < data . offset ) worker_bcast_size = data . offset ; }"
GCC,nvptx,233,"Predict the next statement of this code snippet:
 <s> switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case NVPTX_BUILTIN_SHUFFLE : case NVPTX_BUILTIN_SHUFFLELL : return nvptx_expand_shuffle ( exp , target , mode , ignore ) ; case NVPTX_BUILTIN_WORKER_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , false ) ; case NVPTX_BUILTIN_VECTOR_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , true ) ; case NVPTX_BUILTIN_CMP_SWAP : case NVPTX_BUILTIN_CMP_SWAPLL : return nvptx_expand_cmp_swap ( exp , target , mode , ignore ) ; default : gcc_unreachable ( ) ;"
GCC,nvptx,234,"Predict the next statement of this code snippet:
 <s> case NVPTX_BUILTIN_SHUFFLE : case NVPTX_BUILTIN_SHUFFLELL : return nvptx_expand_shuffle ( exp , target , mode , ignore ) ; case NVPTX_BUILTIN_WORKER_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , false ) ; case NVPTX_BUILTIN_VECTOR_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , true ) ; case NVPTX_BUILTIN_CMP_SWAP : case NVPTX_BUILTIN_CMP_SWAPLL : return nvptx_expand_cmp_swap ( exp , target , mode , ignore ) ; default : gcc_unreachable ( ) ; }"
GCC,nvptx,235,"Predict the next statement of this code snippet:
 <s> int ix ; if ( dump_file ) { for ( ix = <NUM_LIT> ; ix < len ; ix ++ ) { const pseudo_node_t & pseudo = child -> brackets [ ix ] . back ; fprintf ( dump_file , <STR_LIT> , child -> node , pseudo . first ? pseudo . first -> index : <NUM_LIT> , pseudo . second ) ; } } if ( ! brackets . length ( ) ) std :: swap ( brackets , child -> brackets ) ; else { brackets . reserve ( len ) ; for ( ix = <NUM_LIT> ; ix < len ; ix ++ ) brackets . quick_push ( child -> brackets [ ix ] ) ; }"
GCC,nvptx,236,"Predict the next statement of this code snippet:
 <s> rtx_insn * insn ;"
GCC,nvptx,237,"Predict the next statement of this code snippet:
 <s> rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( INSN_P ( insn ) ) return insn ;"
GCC,nvptx,238,"Predict the next statement of this code snippet:
 <s> bb_sese ( unsigned node_ , unsigned p , int dir_ ) : node ( node_ ) , parent ( p ) , dir ( dir_ ) {"
GCC,nvptx,239,"Predict the next statement of this code snippet:
 <s> bb_sese ( unsigned node_ , unsigned p , int dir_ ) : node ( node_ ) , parent ( p ) , dir ( dir_ ) {"
GCC,nvptx,240,"Predict the next statement of this code snippet:
 <s> bracket ( pseudo_node_t back_ ) : back ( back_ ) , color ( ~ <NUM_LIT> ) , size ( ~ <NUM_LIT> ) {"
GCC,nvptx,241,"Predict the next statement of this code snippet:
 <s> bracket ( pseudo_node_t back_ ) : back ( back_ ) , color ( ~ <NUM_LIT> ) , size ( ~ <NUM_LIT> ) {"
GCC,nvptx,242,"Predict the next statement of this code snippet:
 <s> static enum ptx_version default_ptx_version_option ( void ) { enum ptx_version first = first_ptx_version_supporting_sm ( ( enum ptx_isa ) ptx_isa_option ) ; enum ptx_version res = first ;"
GCC,nvptx,243,"Predict the next statement of this code snippet:
 <s> res = MAX ( res , PTX_VERSION_3_1 ) ; res = MAX ( res , PTX_VERSION_6_0 ) ; gcc_assert ( first <= res ) ;"
GCC,nvptx,244,"Predict the next statement of this code snippet:
 <s> switch ( sm ) { case PTX_ISA_SM30 : return PTX_VERSION_3_0 ; case PTX_ISA_SM35 : return PTX_VERSION_3_1 ; case PTX_ISA_SM53 : return PTX_VERSION_4_2 ; case PTX_ISA_SM70 : return PTX_VERSION_6_0 ; case PTX_ISA_SM75 : return PTX_VERSION_6_3 ; case PTX_ISA_SM80 : return PTX_VERSION_7_0 ; default :"
GCC,nvptx,245,"Predict the next statement of this code snippet:
 <s> case PTX_ISA_SM70 : return PTX_VERSION_6_0 ; case PTX_ISA_SM75 : return PTX_VERSION_6_3 ; case PTX_ISA_SM80 : return PTX_VERSION_7_0 ; default : gcc_unreachable ( ) ; }"
GCC,nvptx,246,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( type ) != RECORD_TYPE ) return false ; const_tree last_field = NULL_TREE ; for ( const_tree f = TYPE_FIELDS ( type ) ; f ; f = TREE_CHAIN ( f ) ) last_field = f ; if ( ! last_field ) return false ; const_tree last_field_type = TREE_TYPE ( last_field ) ; if ( TREE_CODE ( last_field_type ) != ARRAY_TYPE ) return false ;"
GCC,nvptx,247,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( last_field_type ) != ARRAY_TYPE ) return false ;"
GCC,nvptx,248,"Predict the next statement of this code snippet:
 <s> FOR_ALL_BB_FN ( block , cfun ) {"
GCC,nvptx,249,"Predict the next statement of this code snippet:
 <s> FOR_ALL_BB_FN ( block , cfun ) { block -> flags &= ~ BB_VISITED ; BB_SET_SESE ( block , <NUM_LIT> ) ;"
GCC,nvptx,250,"Predict the next statement of this code snippet:
 <s> case CODE_FOR_return : break ; } if ( seen_insn ) worklist . safe_push ( insn_bb_t ( insn , block ) ) ; else map -> get_or_insert ( block ) = insn ; seen_insn = true ;"
GCC,nvptx,251,"Predict the next statement of this code snippet:
 <s> } if ( seen_insn ) worklist . safe_push ( insn_bb_t ( insn , block ) ) ; else map -> get_or_insert ( block ) = insn ; seen_insn = true ;"
GCC,nvptx,252,"Predict the next statement of this code snippet:
 <s> else have_false = true ; } if ( have_false ^ have_true ) continue ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { if ( bitmap_bit_p ( DF_LIVE_OUT ( e -> src ) , ix ) ) continue ; rtx reg = regno_reg_rtx [ ix ] ; gcc_assert ( CONST0_RTX ( GET_MODE ( reg ) ) ) ; start_sequence ( ) ; emit_move_insn ( reg , CONST0_RTX ( GET_MODE ( reg ) ) ) ; rtx_insn * inits = get_insns ( ) ; end_sequence ( ) ; if ( dump_file && ( dump_flags & TDF_DETAILS ) ) for ( rtx_insn * init = inits ; init != NULL ; init = NEXT_INSN ( init ) ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , ix , e -> src -> index , e -> dest -> index , INSN_UID ( init ) ) ; insert_insn_on_edge ( inits , e ) ;"
GCC,nvptx,253,"Predict the next statement of this code snippet:
 <s> edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { if ( bitmap_bit_p ( DF_LIVE_OUT ( e -> src ) , ix ) ) have_true = true ; else have_false = true ; } if ( have_false ^ have_true ) continue ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { if ( bitmap_bit_p ( DF_LIVE_OUT ( e -> src ) , ix ) ) continue ; rtx reg = regno_reg_rtx [ ix ] ; gcc_assert ( CONST0_RTX ( GET_MODE ( reg ) ) ) ; start_sequence ( ) ; emit_move_insn ( reg , CONST0_RTX ( GET_MODE ( reg ) ) ) ; rtx_insn * inits = get_insns ( ) ;"
GCC,nvptx,254,"Predict the next statement of this code snippet:
 <s> FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( bb_sese * t_sese = BB_GET_SESE ( target ) ) { if ( t_sese -> node < sese -> node + dir && ! ( dir < <NUM_LIT> && sese -> parent == t_sese -> node ) ) sese -> push ( pseudo_node_t ( target , usd * t_sese -> dir ) ) ; } else {"
GCC,nvptx,255,"Predict the next statement of this code snippet:
 <s> const char * sep = <STR_LIT> ;"
GCC,nvptx,256,"Predict the next statement of this code snippet:
 <s> static rtx gen_comment ( const char * s ) { const char * sep = <STR_LIT> ; size_t len = strlen ( ASM_COMMENT_START ) + strlen ( sep ) + strlen ( s ) + <NUM_LIT> ; char * comment = ( char * ) alloca ( len ) ; snprintf ( comment , len , <STR_LIT> , ASM_COMMENT_START , sep , s ) ;"
GCC,nvptx,257,"Predict the next statement of this code snippet:
 <s> color = color_counts . length ( ) ; color_counts . quick_push ( <NUM_LIT> ) ; }"
GCC,nvptx,258,"Predict the next statement of this code snippet:
 <s> unsigned get_color ( auto_vec < unsigned > & color_counts , unsigned length ) { if ( length != size ) { size = length ; color = color_counts . length ( ) ; color_counts . quick_push ( <NUM_LIT> ) ;"
GCC,nvptx,259,"Predict the next statement of this code snippet:
 <s> if ( r -> n_allocated == r -> n_in_use ) r -> replacement [ r -> n_allocated ++ ] = gen_reg_rtx ( r -> mode ) ;"
GCC,nvptx,260,"Predict the next statement of this code snippet:
 <s> } enum ptx_version first = first_ptx_version_supporting_sm ( ( enum ptx_isa ) ptx_isa_option ) ; if ( ptx_version_option < first ) error ( <STR_LIT> <STR_LIT> , ptx_version_to_string ( first ) , sm_version_to_string ( ( enum ptx_isa ) ptx_isa_option ) ) ;"
GCC,nvptx,261,"Predict the next statement of this code snippet:
 <s> static hashval_t hash ( tree t ) { return htab_hash_pointer ( t ) ;"
GCC,nvptx,262,"Predict the next statement of this code snippet:
 <s> gimple * stmt = gsi_stmt ( i ) ; if ( gimple_code ( stmt ) != GIMPLE_CALL ) continue ; tree callee = gimple_call_fndecl ( stmt ) ; if ( ! callee ) continue ; tree attrs = oacc_get_fn_attrib ( callee ) ; if ( attrs == NULL_TREE ) return false ; int partition_level = oacc_fn_attrib_level ( attrs ) ;"
GCC,nvptx,263,"Predict the next statement of this code snippet:
 <s> else max_workers = oa . num_workers ; cfun -> machine -> axis_dim [ MACH_VECTOR_LENGTH ] = oa . vector_length ;"
GCC,nvptx,264,"Predict the next statement of this code snippet:
 <s> static void init_axis_dim ( void ) { offload_attrs oa ; int max_workers ; populate_offload_attrs ( & oa ) ; if ( oa . num_workers == <NUM_LIT> ) max_workers = PTX_CTA_SIZE / oa . vector_length ;"
GCC,nvptx,265,"Predict the next statement of this code snippet:
 <s> if ( size ) fprintf ( file , <STR_LIT> , align , reg_names [ regno ] , size ) ; fprintf ( file , <STR_LIT> , POINTER_SIZE , reg_names [ regno ] ) ;"
GCC,nvptx,266,"Predict the next statement of this code snippet:
 <s> fprintf ( file , ( size ? <STR_LIT> : <STR_LIT> ) , POINTER_SIZE , reg_names [ regno ] , reg_names [ regno ] ) ;"
GCC,nvptx,267,"Predict the next statement of this code snippet:
 <s> const char * reg_frame = reg_names [ FRAME_POINTER_REGNUM ] ; const char * reg_sspslot = reg_names [ SOFTSTACK_SLOT_REGNUM ] ; const char * reg_sspprev = reg_names [ SOFTSTACK_PREV_REGNUM ] ; fprintf ( file , <STR_LIT> , bits , reg_stack ) ; fprintf ( file , <STR_LIT> , bits , reg_frame ) ; fprintf ( file , <STR_LIT> , bits , reg_sspslot ) ; fprintf ( file , <STR_LIT> , bits , reg_sspprev ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits ) ; fprintf ( file , <STR_LIT> , bits ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , bits / <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , bits ) ; fprintf ( file , <STR_LIT> , bits , reg_sspslot ) ; fprintf ( file , <STR_LIT> , bits , reg_sspprev , reg_sspslot ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , bits , reg_frame , reg_sspprev , size ) ; if ( alignment > keep_align ) fprintf ( file , <STR_LIT> , bits , reg_frame , reg_frame , - alignment ) ; size = crtl -> outgoing_args_size ; gcc_assert ( size % keep_align == <NUM_LIT> ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , bits , reg_stack , reg_frame , size ) ; if ( ! crtl -> is_leaf ) fprintf ( file , <STR_LIT> , bits , reg_sspslot , reg_stack ) ;"
GCC,nvptx,268,"Predict the next statement of this code snippet:
 <s> static machine_mode maybe_split_mode ( machine_mode mode ) {"
GCC,nvptx,269,"Predict the next statement of this code snippet:
 <s> if ( COMPLEX_MODE_P ( mode ) ) return GET_MODE_INNER ( mode ) ;"
GCC,nvptx,270,"Predict the next statement of this code snippet:
 <s> if ( ! INSN_P ( insn ) ) return false ; switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : case CODE_FOR_nvptx_barsync : return false ; default : return true ;"
GCC,nvptx,271,"Predict the next statement of this code snippet:
 <s> if ( dims [ GOMP_DIM_WORKER ] > <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] > <NUM_LIT> && dims [ GOMP_DIM_WORKER ] * dims [ GOMP_DIM_VECTOR ] > PTX_CTA_SIZE ) dims [ GOMP_DIM_VECTOR ] = PTX_WARP_SIZE ;"
GCC,nvptx,272,"Predict the next statement of this code snippet:
 <s> static void nvptx_asm_declare_constant_name ( FILE * file , const char * name , const_tree exp , HOST_WIDE_INT obj_size ) { write_var_marker ( file , true , false , name ) ; fprintf ( file , <STR_LIT> ) ; tree type = TREE_TYPE ( exp ) ;"
GCC,nvptx,273,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> ) ; tree type = TREE_TYPE ( exp ) ; nvptx_assemble_decl_begin ( file , name , <STR_LIT> , type , obj_size , TYPE_ALIGN ( type ) ) ;"
GCC,nvptx,274,"Predict the next statement of this code snippet:
 <s> error_at ( DECL_SOURCE_LOCATION ( name ) , <STR_LIT> ) ; TREE_ASM_WRITTEN ( name ) = <NUM_LIT> ; return ; } if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( name ) ) ) { error_at ( DECL_SOURCE_LOCATION ( name ) , <STR_LIT> ) ; TREE_ASM_WRITTEN ( name ) = <NUM_LIT> ; return ; } if ( TREE_CODE ( name ) != FUNCTION_DECL ) { error_at ( DECL_SOURCE_LOCATION ( name ) , <STR_LIT> <STR_LIT> ) ;"
GCC,nvptx,275,"Predict the next statement of this code snippet:
 <s> TREE_ASM_WRITTEN ( name ) = <NUM_LIT> ; return ; } if ( TREE_CODE ( name ) != FUNCTION_DECL ) { error_at ( DECL_SOURCE_LOCATION ( name ) , <STR_LIT> <STR_LIT> ) ; TREE_ASM_WRITTEN ( name ) = <NUM_LIT> ; return ; } if ( ! cgraph_node :: get ( name ) -> referred_to_p ( ) ) return ; std :: stringstream s ; write_fn_proto ( s , false , get_fnname_from_decl ( name ) , name ) ; fputs ( s . str ( ) . c_str ( ) , stream ) ; tree id = DECL_ASSEMBLER_NAME ( name ) ; NVPTX_ASM_OUTPUT_DEF ( stream , IDENTIFIER_POINTER ( id ) , IDENTIFIER_POINTER ( value ) ) ;"
GCC,nvptx,276,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == COMPLEX_TYPE ) type = TREE_TYPE ( type ) ; unsigned HOST_WIDE_INT elt_size = int_size_in_bytes ( type ) ; machine_mode elt_mode = TYPE_MODE ( type ) == BLKmode ? Pmode : DImode ; elt_size |= GET_MODE_SIZE ( elt_mode ) ; elt_size &= - elt_size ; init_frag . size = elt_size ; init_frag . mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( elt_size * BITS_PER_UNIT - <NUM_LIT> ) ) - <NUM_LIT> ; init_frag . val = <NUM_LIT> ; init_frag . offset = <NUM_LIT> ; init_frag . started = false ;"
GCC,nvptx,277,"Predict the next statement of this code snippet:
 <s> } while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; if ( TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == COMPLEX_TYPE ) type = TREE_TYPE ( type ) ; unsigned HOST_WIDE_INT elt_size = int_size_in_bytes ( type ) ; machine_mode elt_mode = TYPE_MODE ( type ) == BLKmode ? Pmode : DImode ; elt_size |= GET_MODE_SIZE ( elt_mode ) ; elt_size &= - elt_size ; init_frag . size = elt_size ; init_frag . mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( elt_size * BITS_PER_UNIT - <NUM_LIT> ) ) - <NUM_LIT> ;"
GCC,nvptx,278,"Predict the next statement of this code snippet:
 <s> static void nvptx_assemble_decl_end ( void ) { if ( init_frag . offset ) nvptx_assemble_value ( <NUM_LIT> , init_frag . size - init_frag . offset ) ; fprintf ( asm_out_file , init_frag . started ? <STR_LIT> : <STR_LIT> ) ;"
GCC,nvptx,279,"Predict the next statement of this code snippet:
 <s> nvptx_assemble_value ( INTVAL ( x ) , size ) ; break ; case CONST : x = XEXP ( x , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( x ) == PLUS ) ; val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; x = XEXP ( x , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; gcc_fallthrough ( ) ; case SYMBOL_REF : gcc_assert ( size == init_frag . size ) ; if ( init_frag . offset ) sorry ( <STR_LIT> ) ; nvptx_maybe_record_fnsym ( x ) ; init_frag . val = val ; output_init_frag ( x ) ; break ; }"
GCC,nvptx,280,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> ) ; tree size = DECL_SIZE_UNIT ( decl ) ;"
GCC,nvptx,281,"Predict the next statement of this code snippet:
 <s> part = MIN ( part , size ) ; unsigned HOST_WIDE_INT partial = val << ( init_frag . offset * BITS_PER_UNIT ) ; init_frag . val |= partial & init_frag . mask ; init_frag . offset += part ;"
GCC,nvptx,282,"Predict the next statement of this code snippet:
 <s> static void nvptx_assemble_value ( unsigned HOST_WIDE_INT val , unsigned size ) { bool negative_p = val & ( HOST_WIDE_INT_1U << ( HOST_BITS_PER_WIDE_INT - <NUM_LIT> ) ) ; if ( size * BITS_PER_UNIT < HOST_BITS_PER_WIDE_INT ) val &= ( HOST_WIDE_INT_1U << ( size * BITS_PER_UNIT ) ) - <NUM_LIT> ; for ( unsigned part = <NUM_LIT> ; size ; size -= part ) { if ( part * BITS_PER_UNIT == HOST_BITS_PER_WIDE_INT ) val = negative_p ? - <NUM_LIT> : <NUM_LIT> ; else val >>= ( part * BITS_PER_UNIT ) ; part = init_frag . size - init_frag . offset ; part = MIN ( part , size ) ;"
GCC,nvptx,283,"Predict the next statement of this code snippet:
 <s> static tree nvptx_builtin_decl ( unsigned code , bool ARG_UNUSED ( initialize_p ) ) { if ( code >= NVPTX_BUILTIN_MAX ) return error_mark_node ; return nvptx_builtin_decls [ code ] ;"
GCC,nvptx,284,"Predict the next statement of this code snippet:
 <s> if ( fntype && stdarg_p ( fntype ) ) { cfun -> machine -> is_varadic = true ; cfun -> machine -> has_varadic = true ; cfun -> machine -> num_args ++ ; } } if ( REG_P ( arg ) && arg != pc_rtx ) {"
GCC,nvptx,285,"Predict the next statement of this code snippet:
 <s> static bool nvptx_call_insn_is_syscall_p ( rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; gcc_checking_assert ( GET_CODE ( pat ) == PARALLEL ) ; pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( pat ) == SET ) pat = SET_SRC ( pat ) ; gcc_checking_assert ( GET_CODE ( pat ) == CALL && GET_CODE ( XEXP ( pat , <NUM_LIT> ) ) == MEM ) ; rtx addr = XEXP ( XEXP ( pat , <NUM_LIT> ) , <NUM_LIT> ) ;"
GCC,nvptx,286,"Predict the next statement of this code snippet:
 <s> case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : return true ; default : return false ;"
GCC,nvptx,287,"Predict the next statement of this code snippet:
 <s> case CODE_FOR_nvptx_shufflesf : case CODE_FOR_nvptx_barsync : case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : return true ;"
GCC,nvptx,288,"Predict the next statement of this code snippet:
 <s> static bool nvptx_can_change_mode_class ( machine_mode , machine_mode , reg_class_t ) { return false ;"
GCC,nvptx,289,"Predict the next statement of this code snippet:
 <s> if ( ! x ) return NULL_RTX ; x = SET_SRC ( x ) ; if ( GET_CODE ( x ) == LABEL_REF ) return x ; if ( GET_CODE ( x ) != IF_THEN_ELSE ) return NULL_RTX ; if ( XEXP ( x , <NUM_LIT> ) == pc_rtx && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == LABEL_REF ) return XEXP ( x , <NUM_LIT> ) ; if ( XEXP ( x , <NUM_LIT> ) == pc_rtx && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == LABEL_REF ) return XEXP ( x , <NUM_LIT> ) ; return NULL_RTX ;"
GCC,nvptx,290,"Predict the next statement of this code snippet:
 <s> unsigned HOST_WIDE_INT size = tree_to_uhwi ( TYPE_SIZE_UNIT ( type ) ) ; if ( size == GET_MODE_SIZE ( TImode ) ) return GET_MODE_BITSIZE ( maybe_split_mode ( TImode ) ) ; } return basic_align ;"
GCC,nvptx,291,"Predict the next statement of this code snippet:
 <s> write_var_marker ( file , true , TREE_PUBLIC ( decl ) , name ) ; fprintf ( file , <STR_LIT> , ( ! TREE_PUBLIC ( decl ) ? <STR_LIT> : DECL_WEAK ( decl ) ? <STR_LIT> : <STR_LIT> ) ) ; tree type = TREE_TYPE ( decl ) ; HOST_WIDE_INT obj_size = tree_to_shwi ( DECL_SIZE_UNIT ( decl ) ) ;"
GCC,nvptx,292,"Predict the next statement of this code snippet:
 <s> write_var_marker ( file , true , TREE_PUBLIC ( decl ) , name ) ; fprintf ( file , <STR_LIT> , ( ! TREE_PUBLIC ( decl ) ? <STR_LIT> : DECL_WEAK ( decl ) ? <STR_LIT> : <STR_LIT> ) ) ; tree type = TREE_TYPE ( decl ) ;"
GCC,nvptx,293,"Predict the next statement of this code snippet:
 <s> case GOMP_DIM_VECTOR : return PTX_MAX_VECTOR_LENGTH ; default : break ;"
GCC,nvptx,294,"Predict the next statement of this code snippet:
 <s> if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; nvptx_dump_pars ( par , <NUM_LIT> ) ; fprintf ( dump_file , <STR_LIT> ) ;"
GCC,nvptx,295,"Predict the next statement of this code snippet:
 <s> gcc_assert ( block -> preds -> length ( ) == <NUM_LIT> ) ;"
GCC,nvptx,296,"Predict the next statement of this code snippet:
 <s> gcc_assert ( block -> preds -> length ( ) == <NUM_LIT> ) ; basic_block pre_block = ( * block -> preds ) [ <NUM_LIT> ] -> src ; rtx_insn * pre_insn ; for ( pre_insn = BB_END ( pre_block ) ; ! INSN_P ( pre_insn ) ; pre_insn = PREV_INSN ( pre_insn ) ) gcc_assert ( pre_insn != BB_HEAD ( pre_block ) ) ; gcc_assert ( recog_memoized ( pre_insn ) == expected ) ; return pre_insn ;"
GCC,nvptx,297,"Predict the next statement of this code snippet:
 <s> fprintf ( dump_file , <STR_LIT> , depth , par -> mask , par -> forked_block ? par -> forked_block -> index : - <NUM_LIT> , par -> join_block ? par -> join_block -> index : - <NUM_LIT> ) ; fprintf ( dump_file , <STR_LIT> ) ; basic_block block ; for ( unsigned ix = <NUM_LIT> ; par -> blocks . iterate ( ix , & block ) ; ix ++ ) fprintf ( dump_file , <STR_LIT> , block -> index ) ; fprintf ( dump_file , <STR_LIT> ) ; if ( par -> inner ) nvptx_dump_pars ( par -> inner , depth + <NUM_LIT> ) ;"
GCC,nvptx,298,"Predict the next statement of this code snippet:
 <s> rtx op = GEN_INT ( mask | ( is_call << GOMP_DIM_MAX ) ) ; emit_insn ( gen_nvptx_fork ( op ) ) ;"
GCC,nvptx,299,"Predict the next statement of this code snippet:
 <s> if ( mask ) { rtx op = GEN_INT ( mask | ( is_call << GOMP_DIM_MAX ) ) ;"
GCC,nvptx,300,"Predict the next statement of this code snippet:
 <s> mask &= ( GOMP_DIM_MASK ( GOMP_DIM_WORKER ) | GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ;"
GCC,nvptx,301,"Predict the next statement of this code snippet:
 <s> area = DATA_AREA_SHARED ; if ( DECL_INITIAL ( decl ) ) error ( <STR_LIT> <STR_LIT> , decl ) ; } else area = TREE_READONLY ( decl ) ? DATA_AREA_CONST : DATA_AREA_GLOBAL ; } SET_SYMBOL_DATA_AREA ( XEXP ( rtl , <NUM_LIT> ) , area ) ;"
GCC,nvptx,302,"Predict the next statement of this code snippet:
 <s> cfun -> machine -> doing_call = false ;"
GCC,nvptx,303,"Predict the next statement of this code snippet:
 <s> free_EXPR_LIST_list ( & cfun -> machine -> call_args ) ;"
GCC,nvptx,304,"Predict the next statement of this code snippet:
 <s> return nvptx_expand_cmp_swap ( exp , target , mode , ignore ) ; case NVPTX_BUILTIN_MEMBAR_GL : emit_insn ( gen_nvptx_membar_gl ( ) ) ; return NULL_RTX ; case NVPTX_BUILTIN_MEMBAR_CTA : emit_insn ( gen_nvptx_membar_cta ( ) ) ; return NULL_RTX ; default : gcc_unreachable ( ) ; }"
GCC,nvptx,305,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_expand_builtin ( tree exp , rtx target , rtx ARG_UNUSED ( subtarget ) , machine_mode mode , int ignore ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; switch ( DECL_MD_FUNCTION_CODE ( fndecl ) ) { case NVPTX_BUILTIN_SHUFFLE : case NVPTX_BUILTIN_SHUFFLELL : return nvptx_expand_shuffle ( exp , target , mode , ignore ) ; case NVPTX_BUILTIN_WORKER_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , false ) ; case NVPTX_BUILTIN_VECTOR_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , true ) ;"
GCC,nvptx,306,"Predict the next statement of this code snippet:
 <s> int vec_pos = <NUM_LIT> ; rtx call = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; rtx tmp_retval = retval ; if ( retval ) { if ( ! nvptx_register_operand ( retval , GET_MODE ( retval ) ) ) tmp_retval = gen_reg_rtx ( GET_MODE ( retval ) ) ; call = gen_rtx_SET ( tmp_retval , call ) ; } XVECEXP ( pat , <NUM_LIT> , vec_pos ++ ) = call ; for ( rtx arg = cfun -> machine -> call_args ; arg ; arg = XEXP ( arg , <NUM_LIT> ) ) XVECEXP ( pat , <NUM_LIT> , vec_pos ++ ) = gen_rtx_USE ( VOIDmode , XEXP ( arg , <NUM_LIT> ) ) ; if ( varargs ) XVECEXP ( pat , <NUM_LIT> , vec_pos ++ ) = gen_rtx_USE ( VOIDmode , varargs ) ; gcc_assert ( vec_pos = XVECLEN ( pat , <NUM_LIT> ) ) ; nvptx_emit_forking ( parallel , true ) ; emit_call_insn ( pat ) ;"
GCC,nvptx,307,"Predict the next statement of this code snippet:
 <s> rtx mem = expand_expr ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) , NULL_RTX , Pmode , EXPAND_NORMAL ) ; rtx cmp = expand_expr ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) , NULL_RTX , mode , EXPAND_NORMAL ) ; rtx src = expand_expr ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) , NULL_RTX , mode , EXPAND_NORMAL ) ; rtx pat ;"
GCC,nvptx,308,"Predict the next statement of this code snippet:
 <s> rtx nvptx_expand_compare ( rtx compare ) { rtx pred = gen_reg_rtx ( BImode ) ; rtx cmp = gen_rtx_fmt_ee ( GET_CODE ( compare ) , BImode , XEXP ( compare , <NUM_LIT> ) , XEXP ( compare , <NUM_LIT> ) ) ;"
GCC,nvptx,309,"Predict the next statement of this code snippet:
 <s> rtx pred = gen_reg_rtx ( BImode ) ; rtx cmp = gen_rtx_fmt_ee ( GET_CODE ( compare ) , BImode , XEXP ( compare , <NUM_LIT> ) , XEXP ( compare , <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( pred , cmp ) ) ;"
GCC,nvptx,310,"Predict the next statement of this code snippet:
 <s> nvptx_emit_forking ( GOMP_DIM_MASK ( mode ) , false ) ;"
GCC,nvptx,311,"Predict the next statement of this code snippet:
 <s> void nvptx_expand_oacc_join ( unsigned mode ) { nvptx_emit_joining ( GOMP_DIM_MASK ( mode ) , false ) ;"
GCC,nvptx,312,"Predict the next statement of this code snippet:
 <s> nvptx_emit_joining ( GOMP_DIM_MASK ( mode ) , false ) ;"
GCC,nvptx,313,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_expand_shuffle ( tree exp , rtx target , machine_mode mode , int ignore ) { if ( ignore ) return target ; rtx src = expand_expr ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) , NULL_RTX , mode , EXPAND_NORMAL ) ; if ( ! REG_P ( src ) ) src = copy_to_mode_reg ( mode , src ) ;"
GCC,nvptx,314,"Predict the next statement of this code snippet:
 <s> if ( ! REG_P ( src ) ) src = copy_to_mode_reg ( mode , src ) ; rtx idx = expand_expr ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) , NULL_RTX , SImode , EXPAND_NORMAL ) ; rtx op = expand_expr ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) , NULL_RTX , SImode , EXPAND_NORMAL ) ; if ( ! REG_P ( idx ) && GET_CODE ( idx ) != CONST_INT ) idx = copy_to_mode_reg ( SImode , idx ) ;"
GCC,nvptx,315,"Predict the next statement of this code snippet:
 <s> fputs ( ptx_version_to_string ( ( enum ptx_version ) ptx_version_option ) , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( sm_version_to_string ( ( enum ptx_isa ) ptx_isa_option ) , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fprintf ( asm_out_file , <STR_LIT> , GET_MODE_BITSIZE ( Pmode ) ) ; fputs ( <STR_LIT> , asm_out_file ) ;"
GCC,nvptx,316,"Predict the next statement of this code snippet:
 <s> fputs ( <STR_LIT> , asm_out_file ) ; fputs ( sm_version_to_string ( ( enum ptx_isa ) ptx_isa_option ) , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fprintf ( asm_out_file , <STR_LIT> , GET_MODE_BITSIZE ( Pmode ) ) ;"
GCC,nvptx,317,"Predict the next statement of this code snippet:
 <s> par -> forked_block = block ; par -> forked_insn = end ; if ( nvptx_needs_shared_bcast ( mask ) ) par -> fork_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_fork ) ; } break ; case CODE_FOR_nvptx_join : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , <NUM_LIT> , <NUM_LIT> ) ) ; gcc_assert ( par -> mask == mask ) ; gcc_assert ( par -> join_block == NULL ) ; par -> join_block = block ; par -> join_insn = end ; if ( nvptx_needs_shared_bcast ( mask ) ) par -> joining_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_joining ) ; par = par -> parent ; } break ; default : gcc_unreachable ( ) ;"
GCC,nvptx,318,"Predict the next statement of this code snippet:
 <s> auto_vec < basic_block > spanlist ; spanlist . reserve ( blocks . length ( ) ) ; for ( ix = <NUM_LIT> ; blocks . iterate ( ix , & block ) ; ix ++ ) { if ( BB_GET_SESE ( block ) ) continue ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , block -> index ) ; int depth = nvptx_sese_number ( <NUM_LIT> , <NUM_LIT> , + <NUM_LIT> , block , & spanlist ) ; while ( spanlist . length ( ) ) { block = spanlist . pop ( ) ; bb_sese * sese = BB_GET_SESE ( block ) ; nvptx_sese_pseudo ( block , sese , depth , + <NUM_LIT> , sese -> dir > <NUM_LIT> ? block -> succs : block -> preds , ( sese -> dir > <NUM_LIT> ? offsetof ( edge_def , dest ) : offsetof ( edge_def , src ) ) ) ; sese -> set_color ( color_counts ) ; nvptx_sese_pseudo ( block , sese , depth , - <NUM_LIT> , sese -> dir < <NUM_LIT> ? block -> succs : block -> preds , ( sese -> dir < <NUM_LIT> ? offsetof ( edge_def , dest ) : offsetof ( edge_def , src ) ) ) ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; } if ( dump_file ) { unsigned count ; const char * comma = <STR_LIT> ; fprintf ( dump_file , <STR_LIT> , color_counts . length ( ) ) ; for ( ix = <NUM_LIT> ; color_counts . iterate ( ix , & count ) ; ix ++ ) { fprintf ( dump_file , <STR_LIT> , comma , ix , count ) ; comma = <STR_LIT> ; for ( unsigned jx = <NUM_LIT> ; blocks . iterate ( jx , & block ) ; jx ++ ) if ( BB_GET_SESE ( block ) -> color == ix ) { block -> flags |= BB_VISITED ; fprintf ( dump_file , <STR_LIT> , comma , block -> index ) ; comma = <STR_LIT> ; }"
GCC,nvptx,319,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_function_arg ( cumulative_args_t , const function_arg_info & arg ) {"
GCC,nvptx,320,"Predict the next statement of this code snippet:
 <s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;"
GCC,nvptx,321,"Predict the next statement of this code snippet:
 <s> static void nvptx_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & ) {"
GCC,nvptx,322,"Predict the next statement of this code snippet:
 <s> static unsigned nvptx_function_arg_boundary ( machine_mode mode , const_tree ARG_UNUSED ( type ) ) { return GET_MODE_ALIGNMENT ( mode ) ;"
GCC,nvptx,323,"Predict the next statement of this code snippet:
 <s> static unsigned nvptx_function_arg_boundary ( machine_mode mode , const_tree ARG_UNUSED ( type ) ) { return GET_MODE_ALIGNMENT ( mode ) ;"
GCC,nvptx,324,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> ) ;"
GCC,nvptx,325,"Predict the next statement of this code snippet:
 <s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( arg . end_marker_p ( ) || ! arg . named ) return NULL_RTX ;"
GCC,nvptx,326,"Predict the next statement of this code snippet:
 <s> if ( arg . end_marker_p ( ) || ! arg . named ) return NULL_RTX ;"
GCC,nvptx,327,"Predict the next statement of this code snippet:
 <s> return false ;"
GCC,nvptx,328,"Predict the next statement of this code snippet:
 <s> static bool nvptx_function_ok_for_sibcall ( tree , tree ) {"
GCC,nvptx,329,"Predict the next statement of this code snippet:
 <s> gcc_assert ( cfun ) ; cfun -> machine -> return_mode = mode ; return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ;"
GCC,nvptx,330,"Predict the next statement of this code snippet:
 <s> return regno == NVPTX_RETURN_REGNUM ;"
GCC,nvptx,331,"Predict the next statement of this code snippet:
 <s> static bool nvptx_function_value_regno_p ( const unsigned int regno ) { return regno == NVPTX_RETURN_REGNUM ;"
GCC,nvptx,332,"Predict the next statement of this code snippet:
 <s> tree bits = build_int_cst ( unsigned_type_node , shift ) ; tree kind = build_int_cst ( unsigned_type_node , SHUFFLE_DOWN ) ; tree expr ; if ( var_type != dest_type ) { tree real = fold_build1 ( REALPART_EXPR , var_type , var ) ; real = fold_build1 ( code , arg_type , real ) ; real = build_call_expr_loc ( loc , call , <NUM_LIT> , real , bits , kind ) ; real = fold_build1 ( code , var_type , real ) ; tree imag = fold_build1 ( IMAGPART_EXPR , var_type , var ) ; imag = fold_build1 ( code , arg_type , imag ) ; imag = build_call_expr_loc ( loc , call , <NUM_LIT> , imag , bits , kind ) ; imag = fold_build1 ( code , var_type , imag ) ; expr = fold_build2 ( COMPLEX_EXPR , dest_type , real , imag ) ; } else { expr = fold_build1 ( code , arg_type , var ) ; expr = build_call_expr_loc ( loc , call , <NUM_LIT> , expr , bits , kind ) ; expr = fold_build1 ( code , dest_type , expr ) ; } gimplify_assign ( dest_var , expr , seq ) ;"
GCC,nvptx,333,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_gen_pack ( rtx dst , rtx src0 , rtx src1 ) { rtx res ; switch ( GET_MODE ( dst ) ) {"
GCC,nvptx,334,"Predict the next statement of this code snippet:
 <s> data -> offset = ROUND_UP ( data -> offset , align ) ; addr = data -> base ; gcc_assert ( data -> base != NULL ) ; if ( data -> offset ) addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( data -> offset ) ) ; } addr = gen_rtx_MEM ( mode , addr ) ; if ( pm == PM_read ) res = gen_rtx_SET ( addr , reg ) ; else if ( pm == PM_write ) res = gen_rtx_SET ( reg , addr ) ; else gcc_unreachable ( ) ; if ( data -> ptr ) { start_sequence ( ) ; emit_insn ( res ) ; emit_insn ( gen_adddi3 ( data -> ptr , data -> ptr , GEN_INT ( GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } else rep = <NUM_LIT> ; data -> offset += rep * GET_MODE_SIZE ( GET_MODE ( reg ) ) ; } break ;"
GCC,nvptx,335,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_gen_unpack ( rtx dst0 , rtx dst1 , rtx src ) { rtx res ; switch ( GET_MODE ( src ) ) { case E_DImode : res = gen_unpackdisi2 ( dst0 , dst1 , src ) ; break ; case E_DFmode : res = gen_unpackdfsi2 ( dst0 , dst1 , src ) ; break ; default : gcc_unreachable ( ) ; }"
GCC,nvptx,336,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_get_drap_rtx ( void ) { if ( TARGET_SOFT_STACK && stack_realign_drap ) return arg_pointer_rtx ;"
GCC,nvptx,337,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_get_drap_rtx ( void ) { if ( TARGET_SOFT_STACK && stack_realign_drap ) return arg_pointer_rtx ; return NULL_RTX ;"
GCC,nvptx,338,"Predict the next statement of this code snippet:
 <s> tree align = build_int_cst ( unsigned_type_node , GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ) ;"
GCC,nvptx,339,"Predict the next statement of this code snippet:
 <s> return master ? master : master = gen_reg_rtx ( SImode ) ;"
GCC,nvptx,340,"Predict the next statement of this code snippet:
 <s> return master ? master : master = gen_reg_rtx ( SImode ) ;"
GCC,nvptx,341,"Predict the next statement of this code snippet:
 <s> return pred ? pred : pred = gen_reg_rtx ( BImode ) ;"
GCC,nvptx,342,"Predict the next statement of this code snippet:
 <s> static void nvptx_globalize_label ( FILE * , const char * ) {"
GCC,nvptx,343,"Predict the next statement of this code snippet:
 <s> static void nvptx_globalize_label ( FILE * , const char * ) {"
GCC,nvptx,344,"Predict the next statement of this code snippet:
 <s> tree type = build_qualified_type ( unsigned_type_node , TYPE_QUAL_VOLATILE ) ; v = build_decl ( BUILTINS_LOCATION , VAR_DECL , name , type ) ; global_lock_var = v ; DECL_ARTIFICIAL ( v ) = <NUM_LIT> ; DECL_EXTERNAL ( v ) = <NUM_LIT> ; TREE_STATIC ( v ) = <NUM_LIT> ; TREE_PUBLIC ( v ) = <NUM_LIT> ; TREE_USED ( v ) = <NUM_LIT> ; mark_addressable ( v ) ; mark_decl_referenced ( v ) ; }"
GCC,nvptx,345,"Predict the next statement of this code snippet:
 <s> gcc_checking_assert ( ! lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) ; if ( level == GOMP_DIM_GANG ) { tree id = get_identifier ( <STR_LIT> ) ; tree loc_tree = build_empty_stmt ( loc ) ; DECL_ATTRIBUTES ( decl ) = tree_cons ( id , loc_tree , DECL_ATTRIBUTES ( decl ) ) ; } return decl ;"
GCC,nvptx,346,"Predict the next statement of this code snippet:
 <s> static tree nvptx_goacc_adjust_private_decl ( location_t loc , tree decl , int level ) { gcc_checking_assert ( ! lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) ; if ( level == GOMP_DIM_GANG ) { tree id = get_identifier ( <STR_LIT> ) ; tree loc_tree = build_empty_stmt ( loc ) ; DECL_ATTRIBUTES ( decl ) = tree_cons ( id , loc_tree , DECL_ATTRIBUTES ( decl ) ) ; }"
GCC,nvptx,347,"Predict the next statement of this code snippet:
 <s> gang_private_shared_size = ( gang_private_shared_size + align - <NUM_LIT> ) & ~ ( align - <NUM_LIT> ) ; if ( gang_private_shared_align < align ) gang_private_shared_align = align ; offset = gang_private_shared_size ; bool existed = gang_private_shared_hmap . put ( var , offset ) ; gcc_checking_assert ( ! existed ) ; gang_private_shared_size += tree_to_uhwi ( DECL_SIZE_UNIT ( var ) ) ; location_t loc = EXPR_LOCATION ( TREE_VALUE ( attr ) ) ; if ( dump_enabled_p ( ) ) { dump_flags_t l_dump_flags = get_openacc_privatization_dump_flags ( ) ; const dump_user_location_t d_u_loc = dump_user_location_t :: from_location_t ( loc ) ; dump_printf_loc ( l_dump_flags , d_u_loc , <STR_LIT> <STR_LIT> , var , <STR_LIT> ) ; } if ( param_openacc_privatization != OPENACC_PRIVATIZATION_QUIET ) inform ( loc , <STR_LIT> <STR_LIT> , var , <STR_LIT> ) ; if ( dump_file && ( dump_flags & TDF_DETAILS ) ) { fprintf ( dump_file , <STR_LIT> , LOCATION_FILE ( loc ) , LOCATION_LINE ( loc ) , LOCATION_COLUMN ( loc ) ) ; fprintf ( dump_file , <STR_LIT> , <STR_LIT> ) ;"
GCC,nvptx,348,"Predict the next statement of this code snippet:
 <s> unsigned axis = TREE_INT_CST_LOW ( arg ) ; if ( axis < GOMP_DIM_WORKER ) return false ;"
GCC,nvptx,349,"Predict the next statement of this code snippet:
 <s> nvptx_goacc_reduction_init ( call , & oa ) ; break ; case IFN_GOACC_REDUCTION_FINI : nvptx_goacc_reduction_fini ( call , & oa ) ; break ; case IFN_GOACC_REDUCTION_TEARDOWN : nvptx_goacc_reduction_teardown ( call , & oa ) ; break ; default : gcc_unreachable ( ) ;"
GCC,nvptx,350,"Predict the next statement of this code snippet:
 <s> case IFN_GOACC_REDUCTION_INIT : nvptx_goacc_reduction_init ( call , & oa ) ; break ; case IFN_GOACC_REDUCTION_FINI : nvptx_goacc_reduction_fini ( call , & oa ) ; break ; case IFN_GOACC_REDUCTION_TEARDOWN : nvptx_goacc_reduction_teardown ( call , & oa ) ;"
GCC,nvptx,351,"Predict the next statement of this code snippet:
 <s> static void nvptx_goacc_reduction_fini ( gcall * call , offload_attrs * oa ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree ref_to_res = gimple_call_arg ( call , <NUM_LIT> ) ; tree var = gimple_call_arg ( call , <NUM_LIT> ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; enum tree_code op = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; gimple_seq seq = NULL ; tree r = NULL_TREE ; ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR && oa -> vector_length == PTX_WARP_SIZE ) { for ( int shfl = PTX_WARP_SIZE / <NUM_LIT> ; shfl > <NUM_LIT> ; shfl = shfl >> <NUM_LIT> ) { tree other_var = make_ssa_name ( TREE_TYPE ( var ) ) ; nvptx_generate_vector_shuffle ( gimple_location ( call ) , other_var , var , shfl , & seq ) ; r = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( r , fold_build2 ( op , TREE_TYPE ( var ) , var , other_var ) , & seq ) ; var = r ; } } else { tree accum = NULL_TREE ; if ( level == GOMP_DIM_WORKER || level == GOMP_DIM_VECTOR ) { tree offset = gimple_call_arg ( call , <NUM_LIT> ) ; tree call = nvptx_get_shared_red_addr ( TREE_TYPE ( var ) , offset , level == GOMP_DIM_VECTOR ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; accum = ptr ; } else if ( integer_zerop ( ref_to_res ) ) r = var ; else accum = ref_to_res ;"
GCC,nvptx,352,"Predict the next statement of this code snippet:
 <s> push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR && oa -> vector_length == PTX_WARP_SIZE ) { for ( int shfl = PTX_WARP_SIZE / <NUM_LIT> ; shfl > <NUM_LIT> ; shfl = shfl >> <NUM_LIT> ) { tree other_var = make_ssa_name ( TREE_TYPE ( var ) ) ; nvptx_generate_vector_shuffle ( gimple_location ( call ) , other_var , var , shfl , & seq ) ; r = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( r , fold_build2 ( op , TREE_TYPE ( var ) , var , other_var ) , & seq ) ; var = r ; } } else { tree accum = NULL_TREE ; if ( level == GOMP_DIM_WORKER || level == GOMP_DIM_VECTOR ) { tree offset = gimple_call_arg ( call , <NUM_LIT> ) ; tree call = nvptx_get_shared_red_addr ( TREE_TYPE ( var ) , offset , level == GOMP_DIM_VECTOR ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; accum = ptr ; } else if ( integer_zerop ( ref_to_res ) ) r = var ; else accum = ref_to_res ; if ( accum ) {"
GCC,nvptx,353,"Predict the next statement of this code snippet:
 <s> init_edge -> probability = profile_probability :: even ( ) ; gimple_seq init_seq = NULL ; tree init_var = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( init_var , init , & init_seq ) ; gsi = gsi_start_bb ( init_bb ) ; gsi_insert_seq_before ( & gsi , init_seq , GSI_SAME_STMT ) ; gsi_prev ( & gsi ) ; edge inited_edge = split_block ( gsi_bb ( gsi ) , gsi_stmt ( gsi ) ) ; basic_block dst_bb = inited_edge -> dest ; edge nop_edge = make_edge ( call_bb , dst_bb , EDGE_FALSE_VALUE ) ; nop_edge -> probability = profile_probability :: even ( ) ; gphi * phi = create_phi_node ( lhs , dst_bb ) ; add_phi_arg ( phi , init_var , inited_edge , gimple_location ( call ) ) ; add_phi_arg ( phi , var , nop_edge , gimple_location ( call ) ) ; set_immediate_dominator ( CDI_DOMINATORS , dst_bb , call_bb ) ; gsi = gsi_for_stmt ( call ) ; } else { if ( level == GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , <NUM_LIT> ) ; if ( integer_zerop ( ref_to_res ) ) init = var ; } if ( lhs != NULL_TREE ) gimplify_assign ( lhs , init , & seq ) ; }"
GCC,nvptx,354,"Predict the next statement of this code snippet:
 <s> tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , <NUM_LIT> ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; enum tree_code rcode = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; tree init = omp_reduction_init_op ( gimple_location ( call ) , rcode , TREE_TYPE ( var ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR && oa -> vector_length == PTX_WARP_SIZE ) { tree tid = make_ssa_name ( integer_type_node ) ; tree dim_vector = gimple_call_arg ( call , <NUM_LIT> ) ; gimple * tid_call = gimple_build_call_internal ( IFN_GOACC_DIM_POS , <NUM_LIT> , dim_vector ) ; gimple * cond_stmt = gimple_build_cond ( NE_EXPR , tid , integer_zero_node , NULL_TREE , NULL_TREE ) ; gimple_call_set_lhs ( tid_call , tid ) ;"
GCC,nvptx,355,"Predict the next statement of this code snippet:
 <s> tree call = nvptx_get_shared_red_addr ( TREE_TYPE ( var ) , offset , level == GOMP_DIM_VECTOR ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; tree ref = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( ref ) = <NUM_LIT> ; gimplify_assign ( ref , var , & seq ) ; } if ( lhs ) gimplify_assign ( lhs , var , & seq ) ;"
GCC,nvptx,356,"Predict the next statement of this code snippet:
 <s> gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , <NUM_LIT> ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_WORKER || ( level == GOMP_DIM_VECTOR && oa -> vector_length > PTX_WARP_SIZE ) ) { tree offset = gimple_call_arg ( call , <NUM_LIT> ) ; tree call = nvptx_get_shared_red_addr ( TREE_TYPE ( var ) , offset , level == GOMP_DIM_VECTOR ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; var = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( var ) = <NUM_LIT> ; } if ( level != GOMP_DIM_GANG ) {"
GCC,nvptx,357,"Predict the next statement of this code snippet:
 <s> static bool nvptx_goacc_validate_dims ( tree decl , int dims [ ] , int fn_level , unsigned used ) { int old_dims [ GOMP_DIM_MAX ] ; unsigned int i ; for ( i = <NUM_LIT> ; i < GOMP_DIM_MAX ; ++ i ) old_dims [ i ] = dims [ i ] ; nvptx_goacc_validate_dims_1 ( decl , dims , fn_level , used ) ; gcc_assert ( dims [ GOMP_DIM_VECTOR ] != <NUM_LIT> ) ; if ( dims [ GOMP_DIM_WORKER ] > <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] > <NUM_LIT> ) gcc_assert ( dims [ GOMP_DIM_WORKER ] * dims [ GOMP_DIM_VECTOR ] <= PTX_CTA_SIZE ) ; for ( i = <NUM_LIT> ; i < GOMP_DIM_MAX ; ++ i ) if ( old_dims [ i ] != dims [ i ] ) return true ;"
GCC,nvptx,358,"Predict the next statement of this code snippet:
 <s> bool routine_seq_p = false ; int default_vector_length = - <NUM_LIT> ; if ( decl == NULL_TREE ) { if ( fn_level == - <NUM_LIT> ) oacc_default_dims_p = true ; else if ( fn_level == - <NUM_LIT> ) oacc_min_dims_p = true ; else gcc_unreachable ( ) ; } else if ( fn_level == - <NUM_LIT> ) offload_region_p = true ; else if ( <NUM_LIT> <= fn_level && fn_level <= GOMP_DIM_MAX ) { routine_p = true ; routine_seq_p = fn_level == GOMP_DIM_MAX ; } else gcc_unreachable ( ) ; if ( oacc_min_dims_p ) { gcc_assert ( dims [ GOMP_DIM_VECTOR ] == <NUM_LIT> ) ; gcc_assert ( dims [ GOMP_DIM_WORKER ] == <NUM_LIT> ) ; gcc_assert ( dims [ GOMP_DIM_GANG ] == <NUM_LIT> ) ; dims [ GOMP_DIM_VECTOR ] = PTX_WARP_SIZE ; return ; } if ( routine_p ) { if ( ! routine_seq_p ) dims [ GOMP_DIM_VECTOR ] = PTX_WARP_SIZE ; return ; } if ( oacc_default_dims_p ) { gcc_assert ( dims [ GOMP_DIM_VECTOR ] >= - <NUM_LIT> ) ; gcc_assert ( dims [ GOMP_DIM_WORKER ] >= - <NUM_LIT> ) ; gcc_assert ( dims [ GOMP_DIM_GANG ] >= - <NUM_LIT> ) ; gcc_assert ( dims [ GOMP_DIM_VECTOR ] != <NUM_LIT> ) ; gcc_assert ( dims [ GOMP_DIM_WORKER ] != <NUM_LIT> ) ; gcc_assert ( dims [ GOMP_DIM_GANG ] != <NUM_LIT> ) ; } if ( offload_region_p ) { gcc_assert ( dims [ GOMP_DIM_VECTOR ] >= - <NUM_LIT> ) ; gcc_assert ( dims [ GOMP_DIM_WORKER ] >= - <NUM_LIT> ) ; gcc_assert ( dims [ GOMP_DIM_GANG ] >= - <NUM_LIT> ) ; } if ( offload_region_p ) default_vector_length = oacc_get_default_dim ( GOMP_DIM_VECTOR ) ; else default_vector_length = PTX_DEFAULT_VECTOR_LENGTH ; int old_dims [ GOMP_DIM_MAX ] ; unsigned int i ; for ( i = <NUM_LIT> ; i < GOMP_DIM_MAX ; ++ i ) old_dims [ i ] = dims [ i ] ; const char * vector_reason = NULL ; if ( offload_region_p && has_vector_partitionable_routine_calls_p ( decl ) ) { default_vector_length = PTX_WARP_SIZE ; if ( dims [ GOMP_DIM_VECTOR ] > PTX_WARP_SIZE ) { vector_reason = G_ ( <STR_LIT> <STR_LIT> ) ; dims [ GOMP_DIM_VECTOR ] = PTX_WARP_SIZE ; }"
GCC,nvptx,359,"Predict the next statement of this code snippet:
 <s> * no_add_attrs = true ; } else if ( ! VOID_TYPE_P ( TREE_TYPE ( TREE_TYPE ( decl ) ) ) ) { error ( <STR_LIT> , name ) ; * no_add_attrs = true ;"
GCC,nvptx,360,"Predict the next statement of this code snippet:
 <s> tree decl = * node ; if ( TREE_CODE ( decl ) != VAR_DECL ) { error ( <STR_LIT> , name ) ; * no_add_attrs = true ; } else if ( ! ( TREE_PUBLIC ( decl ) || TREE_STATIC ( decl ) ) ) {"
GCC,nvptx,361,"Predict the next statement of this code snippet:
 <s> static unsigned int nvptx_hard_regno_nregs ( unsigned int , machine_mode ) {"
GCC,nvptx,362,"Predict the next statement of this code snippet:
 <s> static unsigned int nvptx_hard_regno_nregs ( unsigned int , machine_mode ) { return <NUM_LIT> ;"
GCC,nvptx,363,"Predict the next statement of this code snippet:
 <s> if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> && cfun -> machine -> red_partition ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> <STR_LIT> , REGNO ( cfun -> machine -> red_partition ) , vector_red_partition ) ; } gcc_assert ( vector_red_partition * nvptx_mach_max_workers ( ) <= vector_red_size ) ;"
GCC,nvptx,364,"Predict the next statement of this code snippet:
 <s> static void nvptx_init_builtins ( void ) { ( nvptx_builtin_decls [ NVPTX_BUILTIN_ ## ID ] \ = add_builtin_function ( <STR_LIT> NAME , \ build_function_type_list T , \ NVPTX_BUILTIN_ ## ID , BUILT_IN_MD , NULL , NULL ) ) DEF ( SHUFFLE , <STR_LIT> , ( UINT , UINT , UINT , UINT , NULL_TREE ) ) ; DEF ( SHUFFLELL , <STR_LIT> , ( LLUINT , LLUINT , UINT , UINT , NULL_TREE ) ) ; DEF ( WORKER_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( VECTOR_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAP , <STR_LIT> , ( UINT , PTRVOID , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAPLL , <STR_LIT> , ( LLUINT , PTRVOID , LLUINT , LLUINT , NULL_TREE ) ) ; DEF ( MEMBAR_GL , <STR_LIT> , ( VOID , VOID , NULL_TREE ) ) ;"
GCC,nvptx,365,"Predict the next statement of this code snippet:
 <s> DEF ( SHUFFLELL , <STR_LIT> , ( LLUINT , LLUINT , UINT , UINT , NULL_TREE ) ) ; DEF ( WORKER_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( VECTOR_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAP , <STR_LIT> , ( UINT , PTRVOID , UINT , UINT , NULL_TREE ) ) ;"
GCC,nvptx,366,"Predict the next statement of this code snippet:
 <s> p -> return_mode = VOIDmode ; return p ;"
GCC,nvptx,367,"Predict the next statement of this code snippet:
 <s> p -> return_mode = VOIDmode ; return p ;"
GCC,nvptx,368,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> ) ; if ( cfun -> machine -> bcast_partition ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> <STR_LIT> , REGNO ( cfun -> machine -> bcast_partition ) , oacc_bcast_partition ) ; } gcc_assert ( oacc_bcast_partition * ( nvptx_mach_max_workers ( ) + <NUM_LIT> ) <= oacc_bcast_size ) ; if ( cfun -> machine -> sync_bar ) fprintf ( file , <STR_LIT> <STR_LIT> , REGNO ( cfun -> machine -> sync_bar ) ) ; fprintf ( file , <STR_LIT> ) ;"
GCC,nvptx,369,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits , loc ) ; fprintf ( file , <STR_LIT> , bits , loc , loc ) ; if ( cfun -> machine -> unisimt_predicate ) { int master = REGNO ( cfun -> machine -> unisimt_master ) ; int pred = REGNO ( cfun -> machine -> unisimt_predicate ) ; fprintf ( file , <STR_LIT> , master , loc ) ; if ( cfun -> machine -> unisimt_outside_simt_predicate ) { int pred_outside_simt = REGNO ( cfun -> machine -> unisimt_outside_simt_predicate ) ; fprintf ( file , <STR_LIT> , pred_outside_simt , master ) ; }"
GCC,nvptx,370,"Predict the next statement of this code snippet:
 <s> enum rtx_code code = GET_CODE ( x ) ; switch ( code ) { case REG : return true ; case PLUS : if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return true ; return false ; case CONST : case SYMBOL_REF :"
GCC,nvptx,371,"Predict the next statement of this code snippet:
 <s> case PLUS : if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return true ; return false ; case CONST : case SYMBOL_REF : case LABEL_REF : return true ; default : return false ;"
GCC,nvptx,372,"Predict the next statement of this code snippet:
 <s> static rtx nvptx_libcall_value ( machine_mode mode , const_rtx ) { if ( ! cfun || ! cfun -> machine -> doing_call ) return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ;"
GCC,nvptx,373,"Predict the next statement of this code snippet:
 <s> if ( fn_class == function_sincos ) { if ( type != NULL_TREE ) return type == float_type_node || type == double_type_node ; else return true ; }"
GCC,nvptx,374,"Predict the next statement of this code snippet:
 <s> static bool nvptx_libgcc_floating_mode_supported_p ( scalar_float_mode mode ) { if ( nvptx_experimental && mode == HFmode && TARGET_SM53 ) return true ;"
GCC,nvptx,375,"Predict the next statement of this code snippet:
 <s> static bool nvptx_libgcc_floating_mode_supported_p ( scalar_float_mode mode ) { if ( nvptx_experimental && mode == HFmode && TARGET_SM53 ) return true ;"
GCC,nvptx,376,"Predict the next statement of this code snippet:
 <s> lock_expr = build_call_expr_loc ( loc , swap_fn , <NUM_LIT> , lock_expr , uns_unlocked , uns_locked ) ; gimplify_assign ( lock_var , lock_expr , & lock_seq ) ; gcond * cond = gimple_build_cond ( EQ_EXPR , lock_var , uns_unlocked , NULL_TREE , NULL_TREE ) ; gimple_seq_add_stmt ( & lock_seq , cond ) ; gimple * lock_end = gimple_seq_last ( lock_seq ) ; gsi_insert_seq_before ( gsi , lock_seq , GSI_SAME_STMT ) ; edge locked_edge = split_block ( lock_bb , lock_end ) ; basic_block update_bb = locked_edge -> dest ; lock_bb = locked_edge -> src ; * gsi = gsi_for_stmt ( gsi_stmt ( * gsi ) ) ; locked_edge -> flags ^= EDGE_TRUE_VALUE | EDGE_FALLTHRU ; locked_edge -> probability = profile_probability :: even ( ) ; edge loop_edge = make_edge ( lock_bb , lock_bb , EDGE_FALSE_VALUE ) ; loop_edge -> probability = profile_probability :: even ( ) ; set_immediate_dominator ( CDI_DOMINATORS , lock_bb , entry_bb ) ; set_immediate_dominator ( CDI_DOMINATORS , update_bb , lock_bb ) ; loop * lock_loop = alloc_loop ( ) ; lock_loop -> header = lock_bb ;"
GCC,nvptx,377,"Predict the next statement of this code snippet:
 <s> gimple * lock_end = gimple_seq_last ( lock_seq ) ; gsi_insert_seq_before ( gsi , lock_seq , GSI_SAME_STMT ) ; edge locked_edge = split_block ( lock_bb , lock_end ) ; basic_block update_bb = locked_edge -> dest ; lock_bb = locked_edge -> src ; * gsi = gsi_for_stmt ( gsi_stmt ( * gsi ) ) ; locked_edge -> flags ^= EDGE_TRUE_VALUE | EDGE_FALLTHRU ; locked_edge -> probability = profile_probability :: even ( ) ; edge loop_edge = make_edge ( lock_bb , lock_bb , EDGE_FALSE_VALUE ) ; loop_edge -> probability = profile_probability :: even ( ) ; set_immediate_dominator ( CDI_DOMINATORS , lock_bb , entry_bb ) ; set_immediate_dominator ( CDI_DOMINATORS , update_bb , lock_bb ) ; loop * lock_loop = alloc_loop ( ) ; lock_loop -> header = lock_bb ; lock_loop -> latch = lock_bb ; lock_loop -> nb_iterations_estimate = <NUM_LIT> ; lock_loop -> any_estimate = true ; add_loop ( lock_loop , entry_bb -> loop_father ) ; gimple_seq red_seq = NULL ; enum nvptx_builtins barrier_builtin = ( level == GOMP_DIM_GANG ? NVPTX_BUILTIN_MEMBAR_GL : NVPTX_BUILTIN_MEMBAR_CTA ) ; tree barrier_fn = nvptx_builtin_decl ( barrier_builtin , true ) ; tree barrier_expr = build_call_expr_loc ( loc , barrier_fn , <NUM_LIT> ) ; gimplify_stmt ( & barrier_expr , & red_seq ) ; tree acc_in = make_ssa_name ( var_type ) ; tree ref_in = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( ref_in ) = <NUM_LIT> ; gimplify_assign ( acc_in , ref_in , & red_seq ) ;"
GCC,nvptx,378,"Predict the next statement of this code snippet:
 <s> pre_bb = pre_edge -> src ; * gsi = gsi_for_stmt ( gsi_stmt ( * gsi ) ) ; tree expect_var = make_ssa_name ( arg_type ) ; tree actual_var = make_ssa_name ( arg_type ) ; tree write_var = make_ssa_name ( arg_type ) ; gimple_seq red_seq = NULL ; tree write_expr = fold_build1 ( code , var_type , expect_var ) ; write_expr = fold_build2 ( op , var_type , write_expr , var ) ; write_expr = fold_build1 ( code , arg_type , write_expr ) ; gimplify_assign ( write_var , write_expr , & red_seq ) ; gsi_insert_seq_before ( gsi , red_seq , GSI_SAME_STMT ) ; gimple_seq latch_seq = NULL ; tree swap_expr = build_call_expr_loc ( loc , swap_fn , <NUM_LIT> , ptr , expect_var , write_var ) ; gimplify_assign ( actual_var , swap_expr , & latch_seq ) ; gcond * cond = gimple_build_cond ( EQ_EXPR , actual_var , expect_var , NULL_TREE , NULL_TREE ) ; gimple_seq_add_stmt ( & latch_seq , cond ) ; gimple * latch_end = gimple_seq_last ( latch_seq ) ;"
GCC,nvptx,379,"Predict the next statement of this code snippet:
 <s> static int ATTRIBUTE_UNUSED nvptx_mach_max_workers ( ) {"
GCC,nvptx,380,"Predict the next statement of this code snippet:
 <s> return cfun -> machine -> axis_dim [ MACH_VECTOR_LENGTH ] ;"
GCC,nvptx,381,"Predict the next statement of this code snippet:
 <s> static int ATTRIBUTE_UNUSED nvptx_mach_vector_length ( ) { if ( ! cfun -> machine -> axis_dim_init_p ) init_axis_dim ( ) ;"
GCC,nvptx,382,"Predict the next statement of this code snippet:
 <s> if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL && DECL_EXTERNAL ( decl ) ) nvptx_record_needed_fndecl ( decl ) ;"
GCC,nvptx,383,"Predict the next statement of this code snippet:
 <s> if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL && DECL_EXTERNAL ( decl ) ) nvptx_record_needed_fndecl ( decl ) ;"
GCC,nvptx,384,"Predict the next statement of this code snippet:
 <s> gcc_assert ( GET_CODE ( x ) == MEM ) ; const_rtx addr = XEXP ( x , <NUM_LIT> ) ; subrtx_iterator :: array_type array ;"
GCC,nvptx,385,"Predict the next statement of this code snippet:
 <s> static nvptx_data_area nvptx_mem_data_area ( const_rtx x ) { gcc_assert ( GET_CODE ( x ) == MEM ) ; const_rtx addr = XEXP ( x , <NUM_LIT> ) ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , addr , ALL ) if ( SYMBOL_REF_P ( * iter ) ) return SYMBOL_DATA_AREA ( * iter ) ;"
GCC,nvptx,386,"Predict the next statement of this code snippet:
 <s> bool nvptx_mem_local_p ( rtx mem ) { gcc_assert ( GET_CODE ( mem ) == MEM ) ; struct address_info info ; decompose_mem_address ( & info , mem ) ; if ( info . base != NULL && REG_P ( * info . base ) && REGNO_PTR_FRAME_P ( REGNO ( * info . base ) ) ) { if ( TARGET_SOFT_STACK ) {"
GCC,nvptx,387,"Predict the next statement of this code snippet:
 <s> bool nvptx_mem_maybe_shared_p ( const_rtx x ) { nvptx_data_area area = nvptx_mem_data_area ( x ) ;"
GCC,nvptx,388,"Predict the next statement of this code snippet:
 <s> return area == DATA_AREA_SHARED || area == DATA_AREA_GENERIC ;"
GCC,nvptx,389,"Predict the next statement of this code snippet:
 <s> return false ;"
GCC,nvptx,390,"Predict the next statement of this code snippet:
 <s> if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ;"
GCC,nvptx,391,"Predict the next statement of this code snippet:
 <s> if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ;"
GCC,nvptx,392,"Predict the next statement of this code snippet:
 <s> bool worker = mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ;"
GCC,nvptx,393,"Predict the next statement of this code snippet:
 <s> bool worker = mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ; bool large_vector = ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) && nvptx_mach_vector_length ( ) != PTX_WARP_SIZE ;"
GCC,nvptx,394,"Predict the next statement of this code snippet:
 <s> else if ( ! ( modes & GOMP_DIM_MASK ( mode ) ) ) { } else if ( par -> inner_mask & GOMP_DIM_MASK ( mode ) || ! par -> forked_insn ) neuter_mask |= GOMP_DIM_MASK ( mode ) ; else if ( ! par -> parent || ! par -> parent -> forked_insn || par -> parent -> inner_mask & GOMP_DIM_MASK ( mode ) ) skip_mask |= GOMP_DIM_MASK ( mode ) ; else { } } if ( neuter_mask ) { int ix , len ; if ( nvptx_optimize ) { bb_pair_vec_t regions ; nvptx_find_sese ( par -> blocks , regions ) ;"
GCC,nvptx,395,"Predict the next statement of this code snippet:
 <s> gcc_checking_assert ( recog_memoized ( fork ) == CODE_FOR_nvptx_fork ) ; rtx_insn * joining = par -> joining_insn ; rtx_insn * join = inner -> join_insn ; if ( NEXT_INSN ( join ) != joining ) return ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , inner -> mask , inner -> forked_block -> index , inner -> join_block -> index , par -> mask , par -> forked_block -> index , par -> join_block -> index ) ;"
GCC,nvptx,396,"Predict the next statement of this code snippet:
 <s> rtx_insn * join = inner -> join_insn ; if ( NEXT_INSN ( join ) != joining ) return ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , inner -> mask , inner -> forked_block -> index , inner -> join_block -> index , par -> mask , par -> forked_block -> index , par -> join_block -> index ) ; par -> mask |= inner -> mask & ( GOMP_DIM_MASK ( GOMP_DIM_MAX ) - <NUM_LIT> ) ; par -> blocks . reserve ( inner -> blocks . length ( ) ) ; while ( inner -> blocks . length ( ) ) par -> blocks . quick_push ( inner -> blocks . pop ( ) ) ; par -> inner = inner -> inner ; inner -> inner = NULL ; delete inner ;"
GCC,nvptx,397,"Predict the next statement of this code snippet:
 <s> if ( ! OPTION_SET_P ( flag_toplevel_reorder ) ) flag_toplevel_reorder = <NUM_LIT> ; debug_nonbind_markers_p = <NUM_LIT> ; if ( ! OPTION_SET_P ( flag_no_common ) ) flag_no_common = <NUM_LIT> ; HOST_WIDE_INT patch_area_size , patch_area_entry ; parse_and_check_patch_area ( flag_patchable_function_entry , false , & patch_area_size , & patch_area_entry ) ; if ( patch_area_size > <NUM_LIT> ) sorry ( <STR_LIT> ) ; flag_var_tracking = <NUM_LIT> ; if ( nvptx_optimize < <NUM_LIT> ) nvptx_optimize = optimize > <NUM_LIT> ; declared_fndecls_htab = hash_table < tree_hasher > :: create_ggc ( <NUM_LIT> ) ; needed_fndecls_htab = hash_table < tree_hasher > :: create_ggc ( <NUM_LIT> ) ; declared_libfuncs_htab = hash_table < declared_libfunc_hasher > :: create_ggc ( <NUM_LIT> ) ; oacc_bcast_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( oacc_bcast_sym , DATA_AREA_SHARED ) ; oacc_bcast_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; oacc_bcast_partition = <NUM_LIT> ; worker_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( worker_red_sym , DATA_AREA_SHARED ) ; worker_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; vector_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( vector_red_sym , DATA_AREA_SHARED ) ; vector_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; vector_red_partition = <NUM_LIT> ; gang_private_shared_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( gang_private_shared_sym , DATA_AREA_SHARED ) ; gang_private_shared_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; diagnose_openacc_conflict ( TARGET_GOMP , <STR_LIT> ) ; diagnose_openacc_conflict ( TARGET_SOFT_STACK , <STR_LIT> ) ; diagnose_openacc_conflict ( TARGET_UNIFORM_SIMT , <STR_LIT> ) ; if ( TARGET_GOMP ) target_flags |= MASK_SOFT_STACK | MASK_UNIFORM_SIMT ;"
GCC,nvptx,398,"Predict the next statement of this code snippet:
 <s> flag_var_tracking = <NUM_LIT> ; if ( nvptx_optimize < <NUM_LIT> ) nvptx_optimize = optimize > <NUM_LIT> ; declared_fndecls_htab = hash_table < tree_hasher > :: create_ggc ( <NUM_LIT> ) ; needed_fndecls_htab = hash_table < tree_hasher > :: create_ggc ( <NUM_LIT> ) ; declared_libfuncs_htab = hash_table < declared_libfunc_hasher > :: create_ggc ( <NUM_LIT> ) ; oacc_bcast_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( oacc_bcast_sym , DATA_AREA_SHARED ) ; oacc_bcast_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; oacc_bcast_partition = <NUM_LIT> ; worker_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( worker_red_sym , DATA_AREA_SHARED ) ; worker_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; vector_red_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( vector_red_sym , DATA_AREA_SHARED ) ; vector_red_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; vector_red_partition = <NUM_LIT> ; gang_private_shared_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SET_SYMBOL_DATA_AREA ( gang_private_shared_sym , DATA_AREA_SHARED ) ; gang_private_shared_align = GET_MODE_ALIGNMENT ( SImode ) / BITS_PER_UNIT ; diagnose_openacc_conflict ( TARGET_GOMP , <STR_LIT> ) ; diagnose_openacc_conflict ( TARGET_SOFT_STACK , <STR_LIT> ) ; diagnose_openacc_conflict ( TARGET_UNIFORM_SIMT , <STR_LIT> ) ;"
GCC,nvptx,399,"Predict the next statement of this code snippet:
 <s> void nvptx_output_aligned_decl ( FILE * file , const char * name , const_tree decl , HOST_WIDE_INT size , unsigned align ) { write_var_marker ( file , true , TREE_PUBLIC ( decl ) , name ) ; fprintf ( file , <STR_LIT> , TREE_PUBLIC ( decl ) ? <STR_LIT> : <STR_LIT> ) ; nvptx_assemble_decl_begin ( file , name , section_for_decl ( decl ) , TREE_TYPE ( decl ) , size , align ) ; nvptx_assemble_decl_end ( ) ;"
GCC,nvptx,400,"Predict the next statement of this code snippet:
 <s> output_asm_insn ( asm_template , operands ) ; nvptx_output_barrier ( & operands [ mem_pos ] , INTVAL ( operands [ memmodel_pos ] ) , false ) ;"
GCC,nvptx,401,"Predict the next statement of this code snippet:
 <s> bool post_p = ! pre_p ; switch ( memmodel ) { case MEMMODEL_RELAXED : return ; case MEMMODEL_CONSUME : case MEMMODEL_ACQUIRE : case MEMMODEL_SYNC_ACQUIRE : if ( post_p ) break ; return ; case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : if ( pre_p ) break ; return ; case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : if ( pre_p || post_p ) break ; return ; default : gcc_unreachable ( ) ;"
GCC,nvptx,402,"Predict the next statement of this code snippet:
 <s> if ( result != NULL ) fprintf ( asm_out_file , <STR_LIT> , nvptx_ptx_type_from_mode ( GET_MODE ( result ) , false ) , reg_names [ NVPTX_RETURN_REGNUM ] ) ; if ( GET_CODE ( callee ) == SYMBOL_REF ) { decl = SYMBOL_REF_DECL ( callee ) ; if ( ! decl || ( DECL_EXTERNAL ( decl ) && ! TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ) ) nvptx_record_libfunc ( callee , result , pat ) ; else if ( DECL_EXTERNAL ( decl ) ) nvptx_record_fndecl ( decl ) ; } if ( needs_tgt ) { ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; labelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; std :: stringstream s ; write_fn_proto_from_insn ( s , NULL , result , pat ) ; fputs ( s . str ( ) . c_str ( ) , asm_out_file ) ; } for ( int argno = <NUM_LIT> ; argno < arg_end ; argno ++ ) { rtx t = XEXP ( XVECEXP ( pat , <NUM_LIT> , argno ) , <NUM_LIT> ) ; machine_mode mode = GET_MODE ( t ) ; const char * ptx_type = nvptx_ptx_type_from_mode ( mode , false ) ; fprintf ( asm_out_file , <STR_LIT> <STR_LIT> , ptx_type , argno , ptx_type , argno ) ; output_reg ( asm_out_file , REGNO ( t ) , VOIDmode ) ; fprintf ( asm_out_file , <STR_LIT> ) ; } nvptx_print_operand ( asm_out_file , NULL_RTX , '.' ) ; fprintf ( asm_out_file , <STR_LIT> ) ; if ( result != NULL_RTX ) fprintf ( asm_out_file , <STR_LIT> , reg_names [ NVPTX_RETURN_REGNUM ] ) ; if ( decl ) { char * replaced_dots = NULL ; const char * name = get_fnname_from_decl ( decl ) ; const char * replacement = nvptx_name_replacement ( name ) ; if ( replacement != name ) name = replacement ; else { replaced_dots = nvptx_replace_dot ( name ) ; if ( replaced_dots ) name = replaced_dots ; } assemble_name ( asm_out_file , name ) ; if ( replaced_dots ) XDELETE ( replaced_dots ) ; } else output_address ( VOIDmode , callee ) ; const char * open = <STR_LIT> ; for ( int argno = <NUM_LIT> ; argno < arg_end ; argno ++ ) { fprintf ( asm_out_file , <STR_LIT> , open , argno ) ; open = <STR_LIT> ; } if ( decl && DECL_STATIC_CHAIN ( decl ) ) { fprintf ( asm_out_file , <STR_LIT> , open , reg_names [ STATIC_CHAIN_REGNUM ] ) ; open = <STR_LIT> ; } if ( ! open [ <NUM_LIT> ] ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( needs_tgt ) { fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,nvptx,403,"Predict the next statement of this code snippet:
 <s> bool needs_tgt = register_operand ( callee , Pmode ) ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) pat = COND_EXEC_CODE ( pat ) ; int arg_end = XVECLEN ( pat , <NUM_LIT> ) ; tree decl = NULL_TREE ; fprintf ( asm_out_file , <STR_LIT> ) ; if ( result != NULL ) fprintf ( asm_out_file , <STR_LIT> , nvptx_ptx_type_from_mode ( GET_MODE ( result ) , false ) , reg_names [ NVPTX_RETURN_REGNUM ] ) ; if ( GET_CODE ( callee ) == SYMBOL_REF ) { decl = SYMBOL_REF_DECL ( callee ) ; if ( ! decl || ( DECL_EXTERNAL ( decl ) && ! TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ) ) nvptx_record_libfunc ( callee , result , pat ) ; else if ( DECL_EXTERNAL ( decl ) ) nvptx_record_fndecl ( decl ) ; } if ( needs_tgt ) { ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; labelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; std :: stringstream s ; write_fn_proto_from_insn ( s , NULL , result , pat ) ; fputs ( s . str ( ) . c_str ( ) , asm_out_file ) ; } for ( int argno = <NUM_LIT> ; argno < arg_end ; argno ++ ) { rtx t = XEXP ( XVECEXP ( pat , <NUM_LIT> , argno ) , <NUM_LIT> ) ; machine_mode mode = GET_MODE ( t ) ; const char * ptx_type = nvptx_ptx_type_from_mode ( mode , false ) ; fprintf ( asm_out_file , <STR_LIT> <STR_LIT> , ptx_type , argno , ptx_type , argno ) ; output_reg ( asm_out_file , REGNO ( t ) , VOIDmode ) ; fprintf ( asm_out_file , <STR_LIT> ) ; } nvptx_print_operand ( asm_out_file , NULL_RTX , '.' ) ; fprintf ( asm_out_file , <STR_LIT> ) ; if ( result != NULL_RTX ) fprintf ( asm_out_file , <STR_LIT> , reg_names [ NVPTX_RETURN_REGNUM ] ) ; if ( decl ) { char * replaced_dots = NULL ; const char * name = get_fnname_from_decl ( decl ) ; const char * replacement = nvptx_name_replacement ( name ) ; if ( replacement != name ) name = replacement ; else { replaced_dots = nvptx_replace_dot ( name ) ; if ( replaced_dots ) name = replaced_dots ; } assemble_name ( asm_out_file , name ) ; if ( replaced_dots ) XDELETE ( replaced_dots ) ; } else output_address ( VOIDmode , callee ) ; const char * open = <STR_LIT> ; for ( int argno = <NUM_LIT> ; argno < arg_end ; argno ++ ) { fprintf ( asm_out_file , <STR_LIT> , open , argno ) ; open = <STR_LIT> ;"
GCC,nvptx,404,"Predict the next statement of this code snippet:
 <s> machine_mode src_inner = ( GET_CODE ( src ) == SUBREG ? GET_MODE ( XEXP ( src , <NUM_LIT> ) ) : dst_mode ) ; rtx sym = src ; if ( GET_CODE ( sym ) == CONST ) sym = XEXP ( XEXP ( sym , <NUM_LIT> ) , <NUM_LIT> ) ; if ( SYMBOL_REF_P ( sym ) ) { if ( SYMBOL_DATA_AREA ( sym ) != DATA_AREA_GENERIC ) return <STR_LIT> ; nvptx_maybe_record_fnsym ( sym ) ; } if ( src_inner == dst_inner ) return <STR_LIT> ; if ( CONSTANT_P ( src ) ) return ( GET_MODE_CLASS ( dst_inner ) == MODE_INT && GET_MODE_CLASS ( src_inner ) != MODE_FLOAT ? <STR_LIT> : <STR_LIT> ) ; if ( GET_MODE_SIZE ( dst_inner ) == GET_MODE_SIZE ( src_inner ) ) { if ( GET_MODE_BITSIZE ( dst_mode ) == <NUM_LIT> && GET_MODE_BITSIZE ( src_mode ) == <NUM_LIT> ) { if ( dst_inner == V2DImode && src_inner == TImode ) return <STR_LIT> ; else if ( dst_inner == TImode && src_inner == V2DImode ) return <STR_LIT> ; gcc_unreachable ( ) ; } return <STR_LIT> ; } if ( GET_MODE_BITSIZE ( src_inner ) == <NUM_LIT> && GET_MODE_BITSIZE ( src_mode ) == <NUM_LIT> ) return <STR_LIT> ;"
GCC,nvptx,405,"Predict the next statement of this code snippet:
 <s> else fprintf ( asm_out_file , with_offset , REGNO ( dst ) , REGNO ( cfun -> machine -> red_partition ) , UINTVAL ( offset ) ) ; return <STR_LIT> ;"
GCC,nvptx,406,"Predict the next statement of this code snippet:
 <s> const char * with_offset = <STR_LIT> ; if ( offset == const0_rtx ) fprintf ( asm_out_file , zero_offset , REGNO ( dst ) , REGNO ( cfun -> machine -> red_partition ) ) ; else fprintf ( asm_out_file , with_offset , REGNO ( dst ) , REGNO ( cfun -> machine -> red_partition ) , UINTVAL ( offset ) ) ; return <STR_LIT> ;"
GCC,nvptx,407,"Predict the next statement of this code snippet:
 <s> if ( mode != VOIDmode ) fprintf ( asm_out_file , <STR_LIT> , nvptx_ptx_type_from_mode ( mode , false ) , reg_names [ NVPTX_RETURN_REGNUM ] , reg_names [ NVPTX_RETURN_REGNUM ] ) ; return <STR_LIT> ;"
GCC,nvptx,408,"Predict the next statement of this code snippet:
 <s> const char * nvptx_output_set_softstack ( unsigned src_regno ) { if ( cfun -> machine -> has_softstack && ! crtl -> is_leaf ) {"
GCC,nvptx,409,"Predict the next statement of this code snippet:
 <s> nvptx_output_softstack_switch ( asm_out_file , true , dest , size , align ) ;"
GCC,nvptx,410,"Predict the next statement of this code snippet:
 <s> nvptx_output_unisimt_switch ( asm_out_file , false ) ; nvptx_output_softstack_switch ( asm_out_file , false , src , NULL_RTX , NULL_RTX ) ; return <STR_LIT> ;"
GCC,nvptx,411,"Predict the next statement of this code snippet:
 <s> nvptx_output_softstack_switch ( asm_out_file , false , src , NULL_RTX , NULL_RTX ) ;"
GCC,nvptx,412,"Predict the next statement of this code snippet:
 <s> } if ( size < init_frag . remaining * init_frag . size ) { while ( size >= init_frag . size ) { size -= init_frag . size ; output_init_frag ( NULL_RTX ) ;"
GCC,nvptx,413,"Predict the next statement of this code snippet:
 <s> } if ( cfun -> machine -> has_softstack ) { const char * reg_stack = reg_names [ STACK_POINTER_REGNUM ] ; if ( entering ) { fprintf ( file , <STR_LIT> , bits , regno , bits / <NUM_LIT> , reg_stack ) ; fprintf ( file , <STR_LIT> , bits , reg_stack , regno , bits / <NUM_LIT> ) ; } else { fprintf ( file , <STR_LIT> , bits , reg_stack , regno , bits / <NUM_LIT> ) ; } nvptx_output_set_softstack ( REGNO ( stack_pointer_rtx ) ) ;"
GCC,nvptx,414,"Predict the next statement of this code snippet:
 <s> static bool nvptx_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) {"
GCC,nvptx,415,"Predict the next statement of this code snippet:
 <s> rtx pat ; if ( ( strict && ! JUMP_P ( insn ) ) || ( ! strict && ! INSN_P ( insn ) ) ) return NULL_RTX ; pat = PATTERN ( insn ) ;"
GCC,nvptx,416,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_DEST ( pat ) ) == PC ) return pat ; return NULL_RTX ;"
GCC,nvptx,417,"Predict the next statement of this code snippet:
 <s> return V2DImode ; case E_SImode : return V2SImode ; default :"
GCC,nvptx,418,"Predict the next statement of this code snippet:
 <s> case SYMBOL_REF : case LABEL_REF : output_addr_const ( file , x ) ; break ; default : gcc_assert ( GET_CODE ( x ) != MEM ) ; nvptx_print_operand ( file , x , <NUM_LIT> ) ; break ; }"
GCC,nvptx,419,"Predict the next statement of this code snippet:
 <s> x = XEXP ( x , <NUM_LIT> ) ; gcc_fallthrough ( ) ; case 'D' : if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == PLUS ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) fputs ( section_for_sym ( x ) , file ) ; break ; case 't' : case 'u' : if ( x_code == SUBREG ) { machine_mode inner_mode = GET_MODE ( SUBREG_REG ( x ) ) ; if ( VECTOR_MODE_P ( inner_mode ) && ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( GET_MODE_INNER ( inner_mode ) ) ) ) mode = GET_MODE_INNER ( inner_mode ) ; else if ( split_mode_p ( inner_mode ) ) mode = maybe_split_mode ( inner_mode ) ; else mode = inner_mode ; } fprintf ( file , <STR_LIT> , nvptx_ptx_type_from_mode ( mode , code == 't' ) ) ; break ; case 'H' : case 'L' : { rtx inner_x = SUBREG_REG ( x ) ; machine_mode inner_mode = GET_MODE ( inner_x ) ; machine_mode split = maybe_split_mode ( inner_mode ) ; output_reg ( file , REGNO ( inner_x ) , split , ( code == 'H' ? GET_MODE_SIZE ( inner_mode ) / <NUM_LIT> : <NUM_LIT> ) ) ; } break ; case 'S' : { nvptx_shuffle_kind kind = ( nvptx_shuffle_kind ) UINTVAL ( x ) ; static const char * const kinds [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; fputs ( kinds [ kind ] , file ) ; } break ; case 'T' : fprintf ( file , <STR_LIT> , GET_MODE_BITSIZE ( mode ) ) ; break ; case 'j' : fprintf ( file , <STR_LIT> ) ; goto common ; case 'J' : fprintf ( file , <STR_LIT> ) ; goto common ; case 'c' : mode = GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ; switch ( x_code ) { case EQ : fputs ( <STR_LIT> , file ) ; break ; case NE : if ( FLOAT_MODE_P ( mode ) ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; break ; case LE : case LEU : fputs ( <STR_LIT> , file ) ; break ; case GE : case GEU : fputs ( <STR_LIT> , file ) ; break ; case LT : case LTU : fputs ( <STR_LIT> , file ) ; break ; case GT : case GTU : fputs ( <STR_LIT> , file ) ; break ; case LTGT : fputs ( <STR_LIT> , file ) ; break ; case UNEQ : fputs ( <STR_LIT> , file ) ; break ; case UNLE : fputs ( <STR_LIT> , file ) ; break ; case UNGE : fputs ( <STR_LIT> , file ) ; break ; case UNLT : fputs ( <STR_LIT> , file ) ; break ; case UNGT : fputs ( <STR_LIT> , file ) ; break ;"
GCC,nvptx,420,"Predict the next statement of this code snippet:
 <s> break ; case 't' : case 'u' : if ( x_code == SUBREG ) { machine_mode inner_mode = GET_MODE ( SUBREG_REG ( x ) ) ; if ( VECTOR_MODE_P ( inner_mode ) && ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( GET_MODE_INNER ( inner_mode ) ) ) ) mode = GET_MODE_INNER ( inner_mode ) ; else if ( split_mode_p ( inner_mode ) ) mode = maybe_split_mode ( inner_mode ) ; else mode = inner_mode ; } fprintf ( file , <STR_LIT> , nvptx_ptx_type_from_mode ( mode , code == 't' ) ) ; break ; case 'H' : case 'L' : { rtx inner_x = SUBREG_REG ( x ) ; machine_mode inner_mode = GET_MODE ( inner_x ) ; machine_mode split = maybe_split_mode ( inner_mode ) ; output_reg ( file , REGNO ( inner_x ) , split , ( code == 'H' ? GET_MODE_SIZE ( inner_mode ) / <NUM_LIT> : <NUM_LIT> ) ) ; } break ; case 'S' : { nvptx_shuffle_kind kind = ( nvptx_shuffle_kind ) UINTVAL ( x ) ; static const char * const kinds [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; fputs ( kinds [ kind ] , file ) ; } break ; case 'T' : fprintf ( file , <STR_LIT> , GET_MODE_BITSIZE ( mode ) ) ; break ; case 'j' : fprintf ( file , <STR_LIT> ) ; goto common ; case 'J' : fprintf ( file , <STR_LIT> ) ; goto common ; case 'c' : mode = GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ; switch ( x_code ) { case EQ : fputs ( <STR_LIT> , file ) ; break ; case NE : if ( FLOAT_MODE_P ( mode ) ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; break ; case LE : case LEU : fputs ( <STR_LIT> , file ) ; break ; case GE : case GEU : fputs ( <STR_LIT> , file ) ; break ; case LT : case LTU : fputs ( <STR_LIT> , file ) ; break ; case GT : case GTU : fputs ( <STR_LIT> , file ) ; break ; case LTGT : fputs ( <STR_LIT> , file ) ; break ; case UNEQ : fputs ( <STR_LIT> , file ) ; break ; case UNLE : fputs ( <STR_LIT> , file ) ;"
GCC,nvptx,421,"Predict the next statement of this code snippet:
 <s> nvptx_print_address_operand ( file , addr , mode ) ;"
GCC,nvptx,422,"Predict the next statement of this code snippet:
 <s> nvptx_print_address_operand ( file , addr , mode ) ;"
GCC,nvptx,423,"Predict the next statement of this code snippet:
 <s> return c == '.' || c == '#' ;"
GCC,nvptx,424,"Predict the next statement of this code snippet:
 <s> return c == '.' || c == '#' ;"
GCC,nvptx,425,"Predict the next statement of this code snippet:
 <s> nvptx_shared_propagate ( false , is_call , par -> forked_block , par -> forked_insn , ! worker ) ; bool no_prop_p = nvptx_shared_propagate ( true , is_call , par -> forked_block , par -> fork_insn , ! worker ) ; bool empty_loop_p = ! is_call && ( NEXT_INSN ( par -> forked_insn ) && NEXT_INSN ( par -> forked_insn ) == par -> joining_insn ) ; rtx barrier = GEN_INT ( <NUM_LIT> ) ; int threads = <NUM_LIT> ; if ( ! worker && cfun -> machine -> sync_bar ) { barrier = cfun -> machine -> sync_bar ;"
GCC,nvptx,426,"Predict the next statement of this code snippet:
 <s> static machine_mode nvptx_promote_function_mode ( const_tree type , machine_mode mode , int * ARG_UNUSED ( punsignedp ) , const_tree funtype , int for_return ) {"
GCC,nvptx,427,"Predict the next statement of this code snippet:
 <s> return promote_arg ( mode , for_return || ! type || TYPE_ARG_TYPES ( funtype ) ) ;"
GCC,nvptx,428,"Predict the next statement of this code snippet:
 <s> static bool nvptx_propagate ( bool is_call , basic_block block , rtx_insn * insn , propagate_mask rw , propagator_fn fn , void * data , bool vector ) { bitmap live = DF_LIVE_IN ( block ) ; bitmap_iterator iterator ; unsigned ix ; bool empty = true ; HOST_WIDE_INT fs = get_frame_size ( ) ; if ( fs ) { rtx tmp = gen_reg_rtx ( DImode ) ; rtx idx = NULL_RTX ; rtx ptr = gen_reg_rtx ( Pmode ) ; rtx pred = NULL_RTX ; rtx_code_label * label = NULL ; empty = false ; fs = ( fs + GET_MODE_SIZE ( DImode ) - <NUM_LIT> ) / GET_MODE_SIZE ( DImode ) ; if ( fs == <NUM_LIT> ) fs = <NUM_LIT> ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( ptr , frame_pointer_rtx ) ) ; if ( fs ) { idx = gen_reg_rtx ( SImode ) ; pred = gen_reg_rtx ( BImode ) ; label = gen_label_rtx ( ) ; emit_insn ( gen_rtx_SET ( idx , GEN_INT ( fs ) ) ) ; rtx init = fn ( tmp , PM_loop_begin , fs , data , vector ) ; if ( init ) emit_insn ( init ) ; emit_label ( label ) ; LABEL_NUSES ( label ) ++ ; emit_insn ( gen_addsi3 ( idx , idx , GEN_INT ( - <NUM_LIT> ) ) ) ; }"
GCC,nvptx,429,"Predict the next statement of this code snippet:
 <s> switch ( mode ) { case E_BLKmode : return <STR_LIT> ; case E_BImode : return <STR_LIT> ; case E_QImode : if ( promote ) return <STR_LIT> ; else return <STR_LIT> ; case E_HImode : return <STR_LIT> ; case E_SImode : return <STR_LIT> ; case E_DImode : return <STR_LIT> ;"
GCC,nvptx,430,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case E_DImode : return <STR_LIT> ; case E_HFmode : return <STR_LIT> ; case E_SFmode : return <STR_LIT> ; case E_DFmode : return <STR_LIT> ; case E_V2SImode : return <STR_LIT> ; case E_V2DImode : return <STR_LIT> ; default : gcc_unreachable ( ) ;"
GCC,nvptx,431,"Predict the next statement of this code snippet:
 <s> tree * slot = declared_fndecls_htab -> find_slot ( decl , INSERT ) ; if ( * slot == NULL ) { * slot = decl ;"
GCC,nvptx,432,"Predict the next statement of this code snippet:
 <s> const char * name = get_fnname_from_decl ( decl ) ;"
GCC,nvptx,433,"Predict the next statement of this code snippet:
 <s> rtx * slot = declared_libfuncs_htab -> find_slot ( callee , INSERT ) ; if ( * slot == NULL ) { * slot = callee ; const char * name = XSTR ( callee , <NUM_LIT> ) ;"
GCC,nvptx,434,"Predict the next statement of this code snippet:
 <s> if ( TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) == NULL_TREE ) { tree * slot = needed_fndecls_htab -> find_slot ( decl , INSERT ) ;"
GCC,nvptx,435,"Predict the next statement of this code snippet:
 <s> void nvptx_record_needed_fndecl ( tree decl ) { if ( TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) == NULL_TREE ) { tree * slot = needed_fndecls_htab -> find_slot ( decl , INSERT ) ; if ( * slot == NULL ) * slot = decl ; }"
GCC,nvptx,436,"Predict the next statement of this code snippet:
 <s> tree attr = oacc_get_fn_attrib ( decl ) ; tree dims = attr ? TREE_VALUE ( attr ) : NULL_TREE ; fprintf ( asm_out_file , <STR_LIT> , IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ; for ( ; dims ; dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; gcc_assert ( ! TREE_PURPOSE ( dims ) ) ; fprintf ( asm_out_file , <STR_LIT> , size ) ; } fprintf ( asm_out_file , <STR_LIT> ) ; } break ;"
GCC,nvptx,437,"Predict the next statement of this code snippet:
 <s> tree dims = attr ? TREE_VALUE ( attr ) : NULL_TREE ; fprintf ( asm_out_file , <STR_LIT> , IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ; for ( ; dims ; dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; gcc_assert ( ! TREE_PURPOSE ( dims ) ) ; fprintf ( asm_out_file , <STR_LIT> , size ) ; } fprintf ( asm_out_file , <STR_LIT> ) ; } break ; default :"
GCC,nvptx,438,"Predict the next statement of this code snippet:
 <s> tree type = TREE_TYPE ( var ) ; tree size = TYPE_SIZE ( type ) ; if ( size == TYPE_SIZE ( unsigned_type_node ) || size == TYPE_SIZE ( long_long_unsigned_type_node ) ) return nvptx_lockless_update ( loc , gsi , ptr , var , op ) ;"
GCC,nvptx,439,"Predict the next statement of this code snippet:
 <s> populate_offload_attrs ( & oa ) ; gcc_assert ( ! ( oa . mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( oa . mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ; parallel * pars = nvptx_discover_pars ( & bb_insn_map ) ; nvptx_process_pars ( pars ) ; nvptx_neuter_pars ( pars , oa . mask , <NUM_LIT> ) ; delete pars ; } nvptx_reorg_subreg ( ) ; if ( TARGET_UNIFORM_SIMT ) nvptx_reorg_uniform_simt ( ) ; prevent_branch_around_nothing ( ) ; workaround_barsyncs ( ) ;"
GCC,nvptx,440,"Predict the next statement of this code snippet:
 <s> populate_offload_attrs ( & oa ) ; gcc_assert ( ! ( oa . mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( oa . mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ; parallel * pars = nvptx_discover_pars ( & bb_insn_map ) ; nvptx_process_pars ( pars ) ; nvptx_neuter_pars ( pars , oa . mask , <NUM_LIT> ) ; delete pars ; } nvptx_reorg_subreg ( ) ;"
GCC,nvptx,441,"Predict the next statement of this code snippet:
 <s> static void nvptx_reorg_subreg ( void ) { struct reg_replace qiregs , hiregs , siregs , diregs ; rtx_insn * insn , * next ; qiregs . n_allocated = <NUM_LIT> ; hiregs . n_allocated = <NUM_LIT> ; siregs . n_allocated = <NUM_LIT> ; diregs . n_allocated = <NUM_LIT> ; qiregs . mode = QImode ; hiregs . mode = HImode ; siregs . mode = SImode ; diregs . mode = DImode ; for ( insn = get_insns ( ) ; insn ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( ! NONDEBUG_INSN_P ( insn ) || asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) continue ; qiregs . n_in_use = <NUM_LIT> ; hiregs . n_in_use = <NUM_LIT> ; siregs . n_in_use = <NUM_LIT> ; diregs . n_in_use = <NUM_LIT> ;"
GCC,nvptx,442,"Predict the next statement of this code snippet:
 <s> gcc_unreachable ( ) ; } if ( shuffle_p && TARGET_PTX_6_0 ) { } else { if ( TARGET_PTX_6_0 ) { gcc_assert ( ! shuffle_p ) ; emit_insn_after ( gen_nvptx_warpsync ( ) , insn ) ; } else { emit_insn_after ( gen_nvptx_uniform_warp_check ( ) , insn ) ; } } rtx pred = nvptx_get_unisimt_predicate ( ) ; predicate_insn ( insn , pred ) ; pred = NULL_RTX ; for ( rtx_insn * post = NEXT_INSN ( insn ) ; post != next ; post = NEXT_INSN ( post ) ) { if ( pred == NULL_RTX ) pred = nvptx_get_unisimt_outside_simt_predicate ( ) ; predicate_insn ( post , pred ) ; }"
GCC,nvptx,443,"Predict the next statement of this code snippet:
 <s> for ( size_t i = <NUM_LIT> ; i < strlen ( p ) ; ++ i ) if ( p [ i ] == '.' ) p [ i ] = '$' ; return p ;"
GCC,nvptx,444,"Predict the next statement of this code snippet:
 <s> static bool nvptx_return_in_memory ( const_tree type , const_tree ) {"
GCC,nvptx,445,"Predict the next statement of this code snippet:
 <s> if ( nvptx_experimental && mode == HFmode && TARGET_SM53 ) return true ; return default_scalar_mode_supported_p ( mode ) ;"
GCC,nvptx,446,"Predict the next statement of this code snippet:
 <s> } else sese -> color = coloring ; } else gcc_assert ( coloring < <NUM_LIT> ) ; if ( block -> succs && block -> succs -> length ( ) ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , block -> succs ) nvptx_sese_color ( color_counts , regions , e -> dest , coloring ) ;"
GCC,nvptx,447,"Predict the next statement of this code snippet:
 <s> list -> quick_push ( b ) ; for ( unsigned ix = <NUM_LIT> ; ix ; ix -- ) { vec < edge , va_gc > * edges = dir > <NUM_LIT> ? b -> succs : b -> preds ;"
GCC,nvptx,448,"Predict the next statement of this code snippet:
 <s> list -> quick_push ( b ) ; for ( unsigned ix = <NUM_LIT> ; ix ; ix -- ) { vec < edge , va_gc > * edges = dir > <NUM_LIT> ? b -> succs : b -> preds ; size_t offset = ( dir > <NUM_LIT> ? offsetof ( edge_def , dest ) : offsetof ( edge_def , src ) ) ; edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , edges ) {"
GCC,nvptx,449,"Predict the next statement of this code snippet:
 <s> num_children ++ ; sese -> append ( t_sese ) ; int t_hi = t_sese -> high . second ; if ( basic_block child_hi_block = t_sese -> high . first ) t_hi += BB_GET_SESE ( child_hi_block ) -> node ; if ( hi_child > t_hi ) { hi_child = t_hi ; node_child = t_sese -> high ; child = target ; } } else if ( t_sese -> node < sese -> node + dir && ! ( dir < <NUM_LIT> && sese -> parent == t_sese -> node ) ) { int d = usd * t_sese -> dir ; int back = t_sese -> node + d ; if ( hi_back > back ) { hi_back = back ; node_back = pseudo_node_t ( target , d ) ; } } } else { hi_back = <NUM_LIT> ; node_back = pseudo_node_t ( nullptr , <NUM_LIT> ) ; } } sese -> remove ( pseudo_node_t ( me , dir ) ) ; FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( bb_sese * t_sese = BB_GET_SESE ( target ) ) { if ( t_sese -> node < sese -> node + dir && ! ( dir < <NUM_LIT> && sese -> parent == t_sese -> node ) ) sese -> push ( pseudo_node_t ( target , usd * t_sese -> dir ) ) ; } else { sese -> push ( pseudo_node_t ( nullptr , <NUM_LIT> ) ) ; } } if ( ! sese -> brackets . length ( ) || ! edges || ! edges -> length ( ) ) { hi_back = <NUM_LIT> ; node_back = pseudo_node_t ( nullptr , <NUM_LIT> ) ; sese -> push ( node_back ) ; } sese -> high = hi_back < hi_child ? node_back : node_child ; if ( num_children > <NUM_LIT> ) { hi_child = depth ; if ( dir < <NUM_LIT> && child ) { node_child = sese -> high ;"
GCC,nvptx,450,"Predict the next statement of this code snippet:
 <s> nvptx_previous_fndecl = fndecl ; vector_red_partition = <NUM_LIT> ;"
GCC,nvptx,451,"Predict the next statement of this code snippet:
 <s> if ( vector && nvptx_mach_max_workers ( ) > <NUM_LIT> ) { if ( ! cfun -> machine -> bcast_partition ) { cfun -> machine -> bcast_partition = gen_reg_rtx ( DImode ) ; } if ( ! cfun -> machine -> sync_bar ) cfun -> machine -> sync_bar = gen_reg_rtx ( SImode ) ; bcast_sym = cfun -> machine -> bcast_partition ; } rtx init = gen_rtx_SET ( data . base , bcast_sym ) ; emit_insn_after ( init , insn ) ; unsigned int psize = ROUND_UP ( data . offset , oacc_bcast_align ) ; unsigned int pnum = ( nvptx_mach_vector_length ( ) > PTX_WARP_SIZE ? nvptx_mach_max_workers ( ) + <NUM_LIT> : <NUM_LIT> ) ; oacc_bcast_partition = MAX ( oacc_bcast_partition , psize ) ; oacc_bcast_size = MAX ( oacc_bcast_size , psize * pnum ) ;"
GCC,nvptx,452,"Predict the next statement of this code snippet:
 <s> broadcast_data_t data ; data . base = gen_reg_rtx ( Pmode ) ; data . offset = <NUM_LIT> ; data . ptr = NULL_RTX ; bool empty = nvptx_propagate ( is_call , block , insn , pre_p ? PM_read : PM_write , shared_prop_gen , & data , vector ) ; gcc_assert ( empty == ! data . offset ) ; if ( data . offset ) { rtx bcast_sym = oacc_bcast_sym ; if ( vector && nvptx_mach_max_workers ( ) > <NUM_LIT> ) { if ( ! cfun -> machine -> bcast_partition ) { cfun -> machine -> bcast_partition = gen_reg_rtx ( DImode ) ; } if ( ! cfun -> machine -> sync_bar ) cfun -> machine -> sync_bar = gen_reg_rtx ( SImode ) ; bcast_sym = cfun -> machine -> bcast_partition ; } rtx init = gen_rtx_SET ( data . base , bcast_sym ) ;"
GCC,nvptx,453,"Predict the next statement of this code snippet:
 <s> static int nvptx_simt_vf ( ) { return PTX_WARP_SIZE ;"
GCC,nvptx,454,"Predict the next statement of this code snippet:
 <s> static int nvptx_simt_vf ( ) { return PTX_WARP_SIZE ;"
GCC,nvptx,455,"Predict the next statement of this code snippet:
 <s> else warp_sync = emit_insn_after ( gen_nvptx_uniform_warp_check ( ) , label_insn ) ; } if ( ( mode == GOMP_DIM_VECTOR || mode == GOMP_DIM_WORKER ) && CALL_P ( tail ) && find_reg_note ( tail , REG_NORETURN , NULL ) ) emit_insn_after ( gen_exit ( ) , label_insn ) ; } * mode_label = label_insn ; } if ( cond_branch ) { rtx pvar = XEXP ( XEXP ( cond_branch , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) == mask && nvptx_mach_vector_length ( ) == PTX_WARP_SIZE ) { rtx_insn * label = PREV_INSN ( tail ) ; if ( label == warp_sync ) label = PREV_INSN ( label ) ; gcc_assert ( label && LABEL_P ( label ) ) ; rtx tmp = gen_reg_rtx ( BImode ) ; emit_insn_before ( gen_movbi ( tmp , const0_rtx ) , bb_first_real_insn ( from ) ) ; emit_insn_before ( gen_rtx_SET ( tmp , pvar ) , label ) ; emit_insn_before ( gen_rtx_SET ( pvar , tmp ) , tail ) ; emit_insn_before ( nvptx_gen_warp_bcast ( pvar ) , tail ) ; } else { broadcast_data_t data ; unsigned size = GET_MODE_SIZE ( SImode ) ; bool vector = ( GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) == mask ) != <NUM_LIT> ; bool worker = ( GOMP_DIM_MASK ( GOMP_DIM_WORKER ) == mask ) != <NUM_LIT> ; rtx barrier = GEN_INT ( <NUM_LIT> ) ; int threads = <NUM_LIT> ; data . base = oacc_bcast_sym ; data . ptr = <NUM_LIT> ; bool use_partitioning_p = ( vector && ! worker && nvptx_mach_max_workers ( ) > <NUM_LIT> && cfun -> machine -> bcast_partition ) ; if ( use_partitioning_p ) { data . base = cfun -> machine -> bcast_partition ; barrier = cfun -> machine -> sync_bar ; threads = nvptx_mach_vector_length ( ) ; } gcc_assert ( data . base != NULL ) ; gcc_assert ( barrier ) ; unsigned int psize = ROUND_UP ( size , oacc_bcast_align ) ; unsigned int pnum = ( nvptx_mach_vector_length ( ) > PTX_WARP_SIZE ? nvptx_mach_max_workers ( ) + <NUM_LIT> : <NUM_LIT> ) ; oacc_bcast_partition = MAX ( oacc_bcast_partition , psize ) ; oacc_bcast_size = MAX ( oacc_bcast_size , psize * pnum ) ; data . offset = <NUM_LIT> ; emit_insn_before ( nvptx_gen_shared_bcast ( pvar , PM_read , <NUM_LIT> , & data , vector ) , before ) ; emit_insn_before ( nvptx_cta_sync ( barrier , threads ) , tail ) ; data . offset = <NUM_LIT> ; emit_insn_before ( nvptx_gen_shared_bcast ( pvar , PM_write , <NUM_LIT> , & data , vector ) , tail ) ; emit_insn_before ( nvptx_cta_sync ( barrier , threads ) , tail ) ; } extract_insn ( tail ) ; rtx unsp = gen_rtx_UNSPEC ( BImode , gen_rtvec ( <NUM_LIT> , pvar ) , UNSPEC_BR_UNIFIED ) ; validate_change ( tail , recog_data . operand_loc [ <NUM_LIT> ] , unsp , false ) ; }"
GCC,nvptx,456,"Predict the next statement of this code snippet:
 <s> gcc_assert ( pre_tail -> succs -> length ( ) == <NUM_LIT> ) ; nvptx_single ( mask , par -> forked_block , pre_tail ) ;"
GCC,nvptx,457,"Predict the next statement of this code snippet:
 <s> static void nvptx_skip_par ( unsigned mask , parallel * par ) { basic_block tail = par -> join_block ;"
GCC,nvptx,458,"Predict the next statement of this code snippet:
 <s> } if ( seen_insn ) worklist . safe_push ( insn_bb_t ( insn , block ) ) ; else map -> get_or_insert ( block ) = insn ; seen_insn = true ; } } unsigned ix ; insn_bb_t * elt ; basic_block remap = <NUM_LIT> ; for ( ix = <NUM_LIT> ; worklist . iterate ( ix , & elt ) ; ix ++ ) { if ( remap != elt -> second ) { block = elt -> second ; remap = block ; } edge e = split_block ( block , PREV_INSN ( elt -> first ) ) ; block = e -> dest ;"
GCC,nvptx,459,"Predict the next statement of this code snippet:
 <s> static void nvptx_split_blocks ( bb_insn_map_t * map ) { insn_bb_vec_t worklist ; basic_block block ; rtx_insn * insn ; FOR_ALL_BB_FN ( block , cfun ) { bool seen_insn = false ; block -> flags &= ~ BB_VISITED ; FOR_BB_INSNS ( block , insn ) { if ( ! INSN_P ( insn ) ) continue ; switch ( recog_memoized ( insn ) ) { default : seen_insn = true ; continue ; case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_join : break ; case CODE_FOR_return : break ; } if ( seen_insn ) worklist . safe_push ( insn_bb_t ( insn , block ) ) ; else map -> get_or_insert ( block ) = insn ; seen_insn = true ;"
GCC,nvptx,460,"Predict the next statement of this code snippet:
 <s> return cum -> fntype == NULL_TREE || stdarg_p ( cum -> fntype ) ;"
GCC,nvptx,461,"Predict the next statement of this code snippet:
 <s> static bool nvptx_truly_noop_truncation ( poly_uint64 , poly_uint64 ) { return false ;"
GCC,nvptx,462,"Predict the next statement of this code snippet:
 <s> static bool nvptx_truly_noop_truncation ( poly_uint64 , poly_uint64 ) {"
GCC,nvptx,463,"Predict the next statement of this code snippet:
 <s> emit_insn_after ( nvptx_gen_shuffle ( reg , reg , master , SHUFFLE_IDX ) , insn ) ; return true ; }"
GCC,nvptx,464,"Predict the next statement of this code snippet:
 <s> rtx reg ; if ( GET_CODE ( set ) == SET && REG_P ( reg = SET_DEST ( set ) ) && find_reg_note ( insn , REG_UNUSED , reg ) == NULL_RTX ) { emit_insn_after ( nvptx_gen_shuffle ( reg , reg , master , SHUFFLE_IDX ) , insn ) ;"
GCC,nvptx,465,"Predict the next statement of this code snippet:
 <s> static bool nvptx_use_anchors_for_symbol_p ( const_rtx ARG_UNUSED ( a ) ) { return false ;"
GCC,nvptx,466,"Predict the next statement of this code snippet:
 <s> static bool nvptx_use_anchors_for_symbol_p ( const_rtx ARG_UNUSED ( a ) ) {"
GCC,nvptx,467,"Predict the next statement of this code snippet:
 <s> } else align = BIGGEST_ALIGNMENT ; align = MAX ( align , GET_MODE_ALIGNMENT ( TYPE_MODE ( type ) ) ) ; return align ;"
GCC,nvptx,468,"Predict the next statement of this code snippet:
 <s> if ( tree_fits_uhwi_p ( size ) ) { align = tree_to_uhwi ( size ) ; align = MIN ( align , BIGGEST_ALIGNMENT ) ; } else align = BIGGEST_ALIGNMENT ; align = MAX ( align , GET_MODE_ALIGNMENT ( TYPE_MODE ( type ) ) ) ; return align ;"
GCC,nvptx,469,"Predict the next statement of this code snippet:
 <s> return nvptx_propagate ( is_call , block , insn , PM_read_write , warp_prop_gen , <NUM_LIT> , false ) ;"
GCC,nvptx,470,"Predict the next statement of this code snippet:
 <s> return nvptx_propagate ( is_call , block , insn , PM_read_write , warp_prop_gen , <NUM_LIT> , false ) ;"
GCC,nvptx,471,"Predict the next statement of this code snippet:
 <s> static bool nvptx_welformed_vector_length_p ( int l ) { gcc_assert ( l > <NUM_LIT> ) ;"
GCC,nvptx,472,"Predict the next statement of this code snippet:
 <s> static bool nvptx_welformed_vector_length_p ( int l ) { gcc_assert ( l > <NUM_LIT> ) ;"
GCC,nvptx,473,"Predict the next statement of this code snippet:
 <s> init_frag . remaining -- ; if ( sym ) { bool function = ( SYMBOL_REF_DECL ( sym ) && ( TREE_CODE ( SYMBOL_REF_DECL ( sym ) ) == FUNCTION_DECL ) ) ; if ( ! function ) fprintf ( asm_out_file , <STR_LIT> ) ; output_address ( VOIDmode , sym ) ; if ( ! function ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( val ) fprintf ( asm_out_file , <STR_LIT> ) ; } if ( ! sym || val ) fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , val ) ;"
GCC,nvptx,474,"Predict the next statement of this code snippet:
 <s> init_frag . offset = <NUM_LIT> ; init_frag . remaining -- ; if ( sym ) { bool function = ( SYMBOL_REF_DECL ( sym ) && ( TREE_CODE ( SYMBOL_REF_DECL ( sym ) ) == FUNCTION_DECL ) ) ; if ( ! function ) fprintf ( asm_out_file , <STR_LIT> ) ; output_address ( VOIDmode , sym ) ; if ( ! function ) fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,nvptx,475,"Predict the next statement of this code snippet:
 <s> } else { if ( subreg_offset == - <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; output_reg ( file , regno , inner_mode , GET_MODE_SIZE ( inner_mode ) ) ; fprintf ( file , <STR_LIT> ) ; output_reg ( file , regno , inner_mode , <NUM_LIT> ) ; if ( subreg_offset == - <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; }"
GCC,nvptx,476,"Predict the next statement of this code snippet:
 <s> fork_insn = joining_insn = <NUM_LIT> ; if ( parent ) { next = parent -> inner ; parent -> inner = this ;"
GCC,nvptx,477,"Predict the next statement of this code snippet:
 <s> if ( ! for_return && COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( GET_MODE_CLASS ( mode ) != MODE_INT && GET_MODE_CLASS ( mode ) != MODE_FLOAT ) return true ;"
GCC,nvptx,478,"Predict the next statement of this code snippet:
 <s> tree dims = TREE_VALUE ( attr ) ; unsigned ix ; oa -> mask = <NUM_LIT> ; for ( ix = <NUM_LIT> ; ix != GOMP_DIM_MAX ; ix ++ , dims = TREE_CHAIN ( dims ) ) { tree t = TREE_VALUE ( dims ) ; int size = ( t == NULL_TREE ) ? - <NUM_LIT> : TREE_INT_CST_LOW ( t ) ; tree allowed = TREE_PURPOSE ( dims ) ; if ( size != <NUM_LIT> && ! ( allowed && integer_zerop ( allowed ) ) ) oa -> mask |= GOMP_DIM_MASK ( ix ) ;"
GCC,nvptx,479,"Predict the next statement of this code snippet:
 <s> if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : case CODE_FOR_nop : continue ; case - <NUM_LIT> : if ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || GET_CODE ( PATTERN ( insn ) ) == ASM_OPERANDS || ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL && asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> ) ) continue ; default : seen_label = NULL ; continue ;"
GCC,nvptx,480,"Predict the next statement of this code snippet:
 <s> if ( ! prototyped && mode == SFmode ) mode = DFmode ; else if ( GET_MODE_SIZE ( mode ) < GET_MODE_SIZE ( SImode ) ) mode = SImode ; return mode ;"
GCC,nvptx,481,"Predict the next statement of this code snippet:
 <s> static machine_mode promote_arg ( machine_mode mode , bool prototyped ) { if ( ! prototyped && mode == SFmode ) mode = DFmode ; else if ( GET_MODE_SIZE ( mode ) < GET_MODE_SIZE ( SImode ) ) mode = SImode ;"
GCC,nvptx,482,"Predict the next statement of this code snippet:
 <s> static machine_mode promote_return ( machine_mode mode ) {"
GCC,nvptx,483,"Predict the next statement of this code snippet:
 <s> static machine_mode promote_return ( machine_mode mode ) { return promote_arg ( mode , true ) ;"
GCC,nvptx,484,"Predict the next statement of this code snippet:
 <s> switch ( v ) { case PTX_VERSION_3_0 : return major_p ? <NUM_LIT> : <NUM_LIT> ; case PTX_VERSION_3_1 : return major_p ? <NUM_LIT> : <NUM_LIT> ; case PTX_VERSION_4_2 : return major_p ? <NUM_LIT> : <NUM_LIT> ; case PTX_VERSION_6_0 : return major_p ? <NUM_LIT> : <NUM_LIT> ;"
GCC,nvptx,485,"Predict the next statement of this code snippet:
 <s> case PTX_VERSION_6_3 : return <STR_LIT> ; case PTX_VERSION_7_0 : return <STR_LIT> ; default : gcc_unreachable ( ) ;"
GCC,nvptx,486,"Predict the next statement of this code snippet:
 <s> if ( dump_file ) fprintf ( dump_file , <STR_LIT> , back . first ? back . first -> index : <NUM_LIT> , back . second ) ; brackets . safe_push ( bracket ( back ) ) ;"
GCC,nvptx,487,"Predict the next statement of this code snippet:
 <s> removed ++ ; } else if ( removed ) brackets [ ix - removed ] = brackets [ ix ] ; } while ( removed -- ) brackets . pop ( ) ;"
GCC,nvptx,488,"Predict the next statement of this code snippet:
 <s> for ( int ix = <NUM_LIT> ; ix < len ; ix ++ ) { if ( brackets [ ix ] . back == pseudo ) {"
GCC,nvptx,489,"Predict the next statement of this code snippet:
 <s> return section_for_sym ( XEXP ( DECL_RTL ( CONST_CAST ( tree , decl ) ) , <NUM_LIT> ) ) ;"
GCC,nvptx,490,"Predict the next statement of this code snippet:
 <s> void set_color ( auto_vec < unsigned > & color_counts ) {"
GCC,nvptx,491,"Predict the next statement of this code snippet:
 <s> return gen_adddi3 ( data -> ptr , data -> base , GEN_INT ( data -> offset ) ) ; } else if ( pm & PM_loop_end ) { rtx clobber = gen_rtx_CLOBBER ( GET_MODE ( data -> ptr ) , data -> ptr ) ; data -> ptr = NULL_RTX ; return clobber ;"
GCC,nvptx,492,"Predict the next statement of this code snippet:
 <s> case PTX_ISA_SM ## XX : \ return # XX ; default : gcc_unreachable ( ) ; }"
GCC,nvptx,493,"Predict the next statement of this code snippet:
 <s> static const char * sm_version_to_string ( enum ptx_isa sm ) {"
GCC,nvptx,494,"Predict the next statement of this code snippet:
 <s> return maybe_split_mode ( mode ) != VOIDmode ;"
GCC,nvptx,495,"Predict the next statement of this code snippet:
 <s> seen_vector_label = true ; gcc_assert ( vector_neutered ) ; vector_neutered = false ; } else if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_barsync : gcc_assert ( ! vector_neutered && ! worker_neutered ) ; break ; default : break ; } if ( insn != BB_END ( bb ) ) insn = NEXT_INSN ( insn ) ; else if ( JUMP_P ( insn ) && single_succ_p ( bb ) && ! seen_vector_jump && ! seen_worker_jump ) { bb = single_succ ( bb ) ; insn = BB_HEAD ( bb ) ; } else break ; } gcc_assert ( ! ( vector_jump && ! seen_vector_jump ) ) ; gcc_assert ( ! ( worker_jump && ! seen_worker_jump ) ) ;"
GCC,nvptx,496,"Predict the next statement of this code snippet:
 <s> seen_vector_jump = true ; vector_neutered = true ; } else if ( insn == worker_label ) { seen_worker_label = true ; gcc_assert ( worker_neutered ) ; worker_neutered = false ; } else if ( insn == vector_label ) { seen_vector_label = true ; gcc_assert ( vector_neutered ) ; vector_neutered = false ; } else if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_barsync : gcc_assert ( ! vector_neutered && ! worker_neutered ) ; break ; default : break ; } if ( insn != BB_END ( bb ) ) insn = NEXT_INSN ( insn ) ; else if ( JUMP_P ( insn ) && single_succ_p ( bb ) && ! seen_vector_jump && ! seen_worker_jump ) { bb = single_succ ( bb ) ; insn = BB_HEAD ( bb ) ; } else break ; } gcc_assert ( ! ( vector_jump && ! seen_vector_jump ) ) ; gcc_assert ( ! ( worker_jump && ! seen_worker_jump ) ) ; if ( seen_vector_label || seen_worker_label ) {"
GCC,nvptx,497,"Predict the next statement of this code snippet:
 <s> while ( true ) { if ( insn == worker_label ) { seen_worker_label = true ; gcc_assert ( ! seen_vector_label ) ; } else if ( insn == vector_label ) seen_vector_label = true ; else if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_barsync :"
GCC,nvptx,498,"Predict the next statement of this code snippet:
 <s> seen_worker_label = true ; gcc_assert ( ! seen_vector_label ) ; } else if ( insn == vector_label ) seen_vector_label = true ; else if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_barsync : gcc_assert ( ! seen_vector_label && ! seen_worker_label ) ; break ; } if ( insn != BB_HEAD ( bb ) ) insn = PREV_INSN ( insn ) ; else break ; } gcc_assert ( ! ( vector_label && ! seen_vector_label ) ) ; gcc_assert ( ! ( worker_label && ! seen_worker_label ) ) ;"
GCC,nvptx,499,"Predict the next statement of this code snippet:
 <s> static rtx warp_prop_gen ( rtx reg , propagate_mask pm , unsigned ARG_UNUSED ( count ) , void * ARG_UNUSED ( data ) , bool ARG_UNUSED ( vector ) ) { if ( ! ( pm & PM_read_write ) ) return <NUM_LIT> ;"
GCC,nvptx,500,"Predict the next statement of this code snippet:
 <s> static rtx warp_prop_gen ( rtx reg , propagate_mask pm , unsigned ARG_UNUSED ( count ) , void * ARG_UNUSED ( data ) , bool ARG_UNUSED ( vector ) ) {"
GCC,nvptx,501,"Predict the next statement of this code snippet:
 <s> if ( seen_barsync ) { emit_insn_before ( gen_nvptx_membar_cta ( ) , insn ) ; emit_insn_before ( gen_nvptx_membar_cta ( ) , insn ) ; } seen_barsync = true ; continue ; } if ( ! seen_barsync ) continue ;"
GCC,nvptx,502,"Predict the next statement of this code snippet:
 <s> seen_barsync = true ; continue ; } if ( ! seen_barsync ) continue ; if ( NOTE_P ( insn ) || DEBUG_INSN_P ( insn ) ) continue ; else if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : continue ; default : break ; }"
GCC,nvptx,503,"Predict the next statement of this code snippet:
 <s> case <NUM_LIT> : workaround_uninit_method_2 ( ) ; break ; case <NUM_LIT> : workaround_uninit_method_3 ( ) ; break ; default : gcc_unreachable ( ) ; }"
GCC,nvptx,504,"Predict the next statement of this code snippet:
 <s> workaround_uninit_method_2 ( ) ; break ; case <NUM_LIT> : workaround_uninit_method_3 ( ) ; break ; default :"
GCC,nvptx,505,"Predict the next statement of this code snippet:
 <s> emit_move_insn ( reg , CONST0_RTX ( GET_MODE ( reg ) ) ) ; rtx_insn * inits = get_insns ( ) ; end_sequence ( ) ; if ( dump_file && ( dump_flags & TDF_DETAILS ) ) for ( rtx_insn * init = inits ; init != NULL ; init = NEXT_INSN ( init ) ) fprintf ( dump_file , <STR_LIT> , ix , INSN_UID ( init ) ) ; if ( first != NULL ) { insert_here = emit_insn_before ( inits , first ) ; first = NULL ;"
GCC,nvptx,506,"Predict the next statement of this code snippet:
 <s> rtx_insn * inits = get_insns ( ) ; end_sequence ( ) ; if ( dump_file && ( dump_flags & TDF_DETAILS ) ) for ( rtx_insn * init = inits ; init != NULL ; init = NEXT_INSN ( init ) ) fprintf ( dump_file , <STR_LIT> , ix , INSN_UID ( init ) ) ; if ( first != NULL ) { insert_here = emit_insn_before ( inits , first ) ; first = NULL ; } else insert_here = emit_insn_after ( inits , insert_here ) ;"
GCC,nvptx,507,"Predict the next statement of this code snippet:
 <s> bitmap entry_lr_in = DF_LR_IN ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; bitmap_and_compl ( entry_pseudo_uninit , entry_lr_in , not_pseudo ) ; } rtx_insn * first = get_insns ( ) ; rtx_insn * insert_here = NULL ; bitmap_iterator iterator ; unsigned ix ; EXECUTE_IF_SET_IN_BITMAP ( entry_pseudo_uninit , <NUM_LIT> , ix , iterator ) { rtx reg = regno_reg_rtx [ ix ] ; gcc_assert ( CONST0_RTX ( GET_MODE ( reg ) ) ) ; start_sequence ( ) ;"
GCC,nvptx,508,"Predict the next statement of this code snippet:
 <s> gcc_assert ( CONST0_RTX ( GET_MODE ( reg ) ) ) ; start_sequence ( ) ; emit_move_insn ( reg , CONST0_RTX ( GET_MODE ( reg ) ) ) ; rtx_insn * inits = get_insns ( ) ; end_sequence ( ) ; if ( dump_file && ( dump_flags & TDF_DETAILS ) ) for ( rtx_insn * init = inits ; init != NULL ; init = NEXT_INSN ( init ) ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , ix , e -> src -> index , e -> dest -> index , INSN_UID ( init ) ) ; insert_insn_on_edge ( inits , e ) ; } } } if ( nvptx_comment ) FOR_EACH_BB_FN ( bb , cfun ) { if ( single_pred_p ( bb ) ) continue ; edge e ; edge_iterator ei ;"
GCC,nvptx,509,"Predict the next statement of this code snippet:
 <s> basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { if ( single_pred_p ( bb ) ) continue ; auto_bitmap bb_pseudo_uninit ; bitmap_and_compl ( bb_pseudo_uninit , DF_LIVE_IN ( bb ) , DF_MIR_IN ( bb ) ) ; bitmap_and_compl_into ( bb_pseudo_uninit , not_pseudo ) ; bitmap_iterator iterator ; unsigned ix ; EXECUTE_IF_SET_IN_BITMAP ( bb_pseudo_uninit , <NUM_LIT> , ix , iterator ) { bool have_false = false ; bool have_true = false ; edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { if ( bitmap_bit_p ( DF_LIVE_OUT ( e -> src ) , ix ) ) have_true = true ; else have_false = true ; } if ( have_false ^ have_true ) continue ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { if ( bitmap_bit_p ( DF_LIVE_OUT ( e -> src ) , ix ) ) continue ; rtx reg = regno_reg_rtx [ ix ] ; gcc_assert ( CONST0_RTX ( GET_MODE ( reg ) ) ) ; start_sequence ( ) ; emit_move_insn ( reg , CONST0_RTX ( GET_MODE ( reg ) ) ) ;"
GCC,nvptx,510,"Predict the next statement of this code snippet:
 <s> if ( pass_in_memory ( mode , type , false ) ) mode = Pmode ; else { bool split = TREE_CODE ( type ) == COMPLEX_TYPE ; if ( split ) { type = TREE_TYPE ( type ) ; mode = TYPE_MODE ( type ) ;"
GCC,nvptx,511,"Predict the next statement of this code snippet:
 <s> static bool write_as_kernel ( tree attrs ) { return ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE || ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE && lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE ) ) ;"
GCC,nvptx,512,"Predict the next statement of this code snippet:
 <s> static bool write_as_kernel ( tree attrs ) { return ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE || ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE && lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE ) ) ;"
GCC,nvptx,513,"Predict the next statement of this code snippet:
 <s> s << <STR_LIT> << ( is_defn ? <STR_LIT> : <STR_LIT> ) ; s << name << <STR_LIT> ;"
GCC,nvptx,514,"Predict the next statement of this code snippet:
 <s> if ( replaced_dots ) name = replaced_dots ; } if ( name [ <NUM_LIT> ] == '*' ) name ++ ;"
GCC,nvptx,515,"Predict the next statement of this code snippet:
 <s> char * replaced_dots = NULL ; if ( replacement != name ) name = replacement ; else { replaced_dots = nvptx_replace_dot ( name ) ; if ( replaced_dots ) name = replaced_dots ; }"
GCC,nvptx,516,"Predict the next statement of this code snippet:
 <s> break ; default : break ; } bool return_in_mem = write_return_type ( s , true , result_type ) ; s << name ; int argno = <NUM_LIT> ; if ( return_in_mem ) argno = write_arg_type ( s , - <NUM_LIT> , argno , ptr_type_node , true ) ; tree args = TYPE_ARG_TYPES ( fntype ) ; bool prototyped = true ; if ( ! args ) { args = DECL_ARGUMENTS ( decl ) ; prototyped = false ; } for ( ; args ; args = TREE_CHAIN ( args ) , not_atomic_weak_arg -- ) { tree type = prototyped ? TREE_VALUE ( args ) : TREE_TYPE ( args ) ; if ( not_atomic_weak_arg ) argno = write_arg_type ( s , - <NUM_LIT> , argno , type , prototyped ) ; else gcc_assert ( TREE_CODE ( type ) == BOOLEAN_TYPE ) ; }"
GCC,nvptx,517,"Predict the next statement of this code snippet:
 <s> } else { const char * replacement = nvptx_name_replacement ( name ) ; if ( replacement != name ) name = replacement ; else { replaced_dots = nvptx_replace_dot ( name ) ; if ( replaced_dots ) name = replaced_dots ; } write_fn_marker ( s , false , true , name ) ; s << <STR_LIT> ; } if ( result != NULL_RTX ) write_return_mode ( s , true , GET_MODE ( result ) ) ; s << name ; if ( replaced_dots ) XDELETE ( replaced_dots ) ; int arg_end = XVECLEN ( pat , <NUM_LIT> ) ;"
GCC,nvptx,518,"Predict the next statement of this code snippet:
 <s> char * replaced_dots = NULL ; if ( ! name ) { s << <STR_LIT> ; name = <STR_LIT> ; } else { const char * replacement = nvptx_name_replacement ( name ) ; if ( replacement != name ) name = replacement ; else { replaced_dots = nvptx_replace_dot ( name ) ; if ( replaced_dots ) name = replaced_dots ; } write_fn_marker ( s , false , true , name ) ; s << <STR_LIT> ; }"
GCC,nvptx,519,"Predict the next statement of this code snippet:
 <s> if ( for_proto ) pfx = <STR_LIT> , sfx = <STR_LIT> ; s << pfx << ptx_type << <STR_LIT> << reg_names [ NVPTX_RETURN_REGNUM ] << sfx ;"
GCC,nvptx,520,"Predict the next statement of this code snippet:
 <s> const char * ptx_type = nvptx_ptx_type_from_mode ( mode , false ) ; const char * pfx = <STR_LIT> ; const char * sfx = <STR_LIT> ;"
GCC,nvptx,521,"Predict the next statement of this code snippet:
 <s> static bool write_return_type ( std :: stringstream & s , bool for_proto , tree type ) { machine_mode mode = TYPE_MODE ( type ) ; if ( mode == VOIDmode ) return false ; bool return_in_mem = pass_in_memory ( mode , type , true ) ; if ( return_in_mem ) { if ( for_proto ) return return_in_mem ; mode = ( machine_mode ) cfun -> machine -> return_mode ; if ( mode == VOIDmode ) return return_in_mem ; cfun -> machine -> return_mode = VOIDmode ;"
GCC,nvptx,522,"Predict the next statement of this code snippet:
 <s> const char * name = XSTR ( sym , <NUM_LIT> ) ; write_var_marker ( file , true , false , name ) ; fprintf ( file , <STR_LIT> , align , name , size ) ;"
GCC,nvptx,523,"Predict the next statement of this code snippet:
 <s> const char * name = XSTR ( sym , <NUM_LIT> ) ; write_var_marker ( file , true , false , name ) ; fprintf ( file , <STR_LIT> , align , name , size ) ;"
GCC,nvptx,524,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> , globalize ? <STR_LIT> : <STR_LIT> , is_defn ? <STR_LIT> : <STR_LIT> ) ; assemble_name_raw ( file , name ) ; fputs ( <STR_LIT> , file ) ;"
GCC,nvptx,525,"Predict the next statement of this code snippet:
 <s> bb_sese :: ~ bb_sese ( ) {"
GCC,nvptx,526,"Predict the next statement of this code snippet:
 <s> bb_sese :: ~ bb_sese ( ) {"
GCC,riscv,527,"Predict the next statement of this code snippet:
 <s> if ( ! valid_type ( sew , lmul_log2 , true ) ) return <STR_LIT> ; std :: stringstream mode ; mode << <STR_LIT> << sew << to_lmul ( lmul_log2 ) << <STR_LIT> ;"
GCC,riscv,0,"Predict the next statement of this code snippet:
 <s> std :: string inttype ( unsigned sew , int lmul_log2 , bool unsigned_p ) { if ( ! valid_type ( sew , lmul_log2 , false ) ) return <STR_LIT> ;"
GCC,riscv,1,"Predict the next statement of this code snippet:
 <s> else mlen = sew * ( <NUM_LIT> << - lmul_log2 ) ; mode << <STR_LIT> << mlen << <STR_LIT> ;"
GCC,riscv,2,"Predict the next statement of this code snippet:
 <s> std :: stringstream mode ; int mlen ; if ( lmul_log2 >= <NUM_LIT> ) mlen = sew / ( <NUM_LIT> << lmul_log2 ) ; else mlen = sew * ( <NUM_LIT> << - lmul_log2 ) ; mode << <STR_LIT> << mlen << <STR_LIT> ;"
GCC,riscv,3,"Predict the next statement of this code snippet:
 <s> else elmul_log2 = lmul_log2 + std :: log2 ( eew / sew ) ; if ( float_p ) return floattype ( eew , elmul_log2 ) ; else return inttype ( eew , elmul_log2 , unsigned_p ) ;"
GCC,riscv,4,"Predict the next statement of this code snippet:
 <s> int elmul_log2 ; if ( sew == eew ) elmul_log2 = lmul_log2 ; else if ( sew > eew ) elmul_log2 = lmul_log2 - std :: log2 ( sew / eew ) ; else elmul_log2 = lmul_log2 + std :: log2 ( eew / sew ) ;"
GCC,riscv,5,"Predict the next statement of this code snippet:
 <s> else { lmul_str << <STR_LIT> ; lmul_log2 = - lmul_log2 ; }"
GCC,riscv,6,"Predict the next statement of this code snippet:
 <s> case <NUM_LIT> : return lmul_log2 >= - <NUM_LIT> && ! float_p ; case <NUM_LIT> : return lmul_log2 >= - <NUM_LIT> && ! float_p ; case <NUM_LIT> : return lmul_log2 >= - <NUM_LIT> ; case <NUM_LIT> : return lmul_log2 >= <NUM_LIT> ; default : return false ;"
GCC,riscv,7,"Predict the next statement of this code snippet:
 <s> void riscv_atomic_assign_expand_fenv ( tree * hold , tree * clear , tree * update ) { if ( ! ( TARGET_HARD_FLOAT || TARGET_ZFINX ) ) return ; tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ; tree fsflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_fsflags ) ; tree old_flags = create_tmp_var_raw ( RISCV_ATYPE_USI ) ;"
GCC,riscv,8,"Predict the next statement of this code snippet:
 <s> case RISCV_BUILTIN_GENERAL : if ( subcode >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ; return riscv_builtin_decls [ subcode ] ; case RISCV_BUILTIN_VECTOR :"
GCC,riscv,9,"Predict the next statement of this code snippet:
 <s> unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = fcode >> RISCV_BUILTIN_SHIFT ; switch ( fcode & RISCV_BUILTIN_CLASS ) { case RISCV_BUILTIN_VECTOR : return <STR_LIT> ( subcode , exp , target ) ; case RISCV_BUILTIN_GENERAL : { const struct riscv_builtin_description * d = & riscv_builtins [ subcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ;"
GCC,riscv,10,"Predict the next statement of this code snippet:
 <s> <STR_LIT> ( ) ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) {"
GCC,riscv,11,"Predict the next statement of this code snippet:
 <s> <STR_LIT> ( ) ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) { const struct riscv_builtin_description * d = & riscv_builtins [ i ] ; if ( d -> avail ( ) ) { tree type = riscv_build_function_type ( d -> prototype ) ; riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , ( i << RISCV_BUILTIN_SHIFT ) + RISCV_BUILTIN_GENERAL , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode ] = i ; } }"
GCC,riscv,12,"Predict the next statement of this code snippet:
 <s> static void riscv_init_builtin_types ( void ) { if ( ! float16_type_node ) { riscv_float16_type_node = make_node ( REAL_TYPE ) ;"
GCC,riscv,13,"Predict the next statement of this code snippet:
 <s> static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned argno ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( op , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } static rtx riscv_expand_builtin_insn ( enum insn_code icode , unsigned int n_ops , struct expand_operand * ops , bool has_target_p ) { if ( ! maybe_expand_insn ( icode , n_ops , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; } return has_target_p ? ops [ <NUM_LIT> ] . value : const0_rtx ; } static rtx riscv_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno = <NUM_LIT> ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( int argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) riscv_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return riscv_expand_builtin_insn ( icode , opno , ops , has_target_p ) ; } rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ; case RISCV_BUILTIN_DIRECT_NO_TARGET : return riscv_expand_builtin_direct ( d -> icode , target , exp , false ) ; } gcc_unreachable ( ) ; } void riscv_atomic_assign_expand_fenv ( tree * hold , tree * clear , tree * update ) { if ( ! TARGET_HARD_FLOAT ) return ;"
GCC,riscv,14,"Predict the next statement of this code snippet:
 <s> } return types [ ( int ) type ] ; } void riscv_init_builtins ( void ) { for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) { const struct riscv_builtin_description * d = & riscv_builtins [ i ] ; if ( d -> avail ( ) ) { tree type = riscv_build_function_type ( d -> prototype ) ; riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode ] = i ; } } } tree riscv_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ; return riscv_builtin_decls [ code ] ; } static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned argno ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( op , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } static rtx riscv_expand_builtin_insn ( enum insn_code icode , unsigned int n_ops , struct expand_operand * ops , bool has_target_p ) { if ( ! maybe_expand_insn ( icode , n_ops , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; } return has_target_p ? ops [ <NUM_LIT> ] . value : const0_rtx ; } static rtx riscv_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno = <NUM_LIT> ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( int argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) riscv_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return riscv_expand_builtin_insn ( icode , opno , ops , has_target_p ) ; } rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type ) {"
GCC,riscv,15,"Predict the next statement of this code snippet:
 <s> rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ;"
GCC,riscv,16,"Predict the next statement of this code snippet:
 <s> const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ; case RISCV_BUILTIN_DIRECT_NO_TARGET : return riscv_expand_builtin_direct ( d -> icode , target , exp , false ) ; }"
GCC,riscv,17,"Predict the next statement of this code snippet:
 <s> case RISCV_FTYPE_NAME ## NUM ARGS : \ types [ ( int ) type ] \ = build_function_type_list ( RISCV_FTYPE_ATYPES ## NUM ARGS , \ NULL_TREE ) ; \ break ; default : gcc_unreachable ( ) ; } return types [ ( int ) type ] ; } void riscv_init_builtins ( void ) { for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) { const struct riscv_builtin_description * d = & riscv_builtins [ i ] ; if ( d -> avail ( ) ) { tree type = riscv_build_function_type ( d -> prototype ) ; riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode ] = i ; } } } tree riscv_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ; return riscv_builtin_decls [ code ] ; } static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned argno ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( op , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } static rtx riscv_expand_builtin_insn ( enum insn_code icode , unsigned int n_ops , struct expand_operand * ops , bool has_target_p ) { if ( ! maybe_expand_insn ( icode , n_ops , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; } return has_target_p ? ops [ <NUM_LIT> ] . value : const0_rtx ; } static rtx riscv_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno = <NUM_LIT> ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( int argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) riscv_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return riscv_expand_builtin_insn ( icode , opno , ops , has_target_p ) ; } rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ;"
GCC,riscv,18,"Predict the next statement of this code snippet:
 <s> AVAIL ( hard_float , TARGET_HARD_FLOAT ) { CODE_FOR_riscv_ ## INSN , <STR_LIT> NAME , \ BUILTIN_TYPE , FUNCTION_TYPE , riscv_builtin_avail_ ## AVAIL } RISCV_BUILTIN ( INSN , # INSN , RISCV_BUILTIN_DIRECT , FUNCTION_TYPE , AVAIL ) RISCV_BUILTIN ( INSN , # INSN , RISCV_BUILTIN_DIRECT_NO_TARGET , \ FUNCTION_TYPE , AVAIL ) RISCV_ATYPE_ ## A RISCV_ATYPE_ ## A , RISCV_ATYPE_ ## B static const struct riscv_builtin_description riscv_builtins [ ] = { DIRECT_BUILTIN ( frflags , RISCV_USI_FTYPE , hard_float ) , DIRECT_NO_TARGET_BUILTIN ( fsflags , RISCV_VOID_FTYPE_USI , hard_float ) } ; static GTY ( ( ) ) tree riscv_builtin_decls [ ARRAY_SIZE ( riscv_builtins ) ] ; static GTY ( ( ) ) int riscv_builtin_decl_index [ NUM_INSN_CODES ] ; riscv_builtin_decls [ riscv_builtin_decl_index [ ( CODE ) ] ] static tree riscv_build_function_type ( enum riscv_function_type type ) { static tree types [ ( int ) RISCV_MAX_FTYPE_MAX ] ; if ( types [ ( int ) type ] == NULL_TREE ) switch ( type ) { case RISCV_FTYPE_NAME ## NUM ARGS : \ types [ ( int ) type ] \ = build_function_type_list ( RISCV_FTYPE_ATYPES ## NUM ARGS , \ NULL_TREE ) ; \ break ; default : gcc_unreachable ( ) ; } return types [ ( int ) type ] ; } void riscv_init_builtins ( void ) { for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) { const struct riscv_builtin_description * d = & riscv_builtins [ i ] ; if ( d -> avail ( ) ) { tree type = riscv_build_function_type ( d -> prototype ) ; riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode ] = i ; } } } tree riscv_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ; return riscv_builtin_decls [ code ] ; } static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned argno ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( op , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } static rtx riscv_expand_builtin_insn ( enum insn_code icode , unsigned int n_ops , struct expand_operand * ops , bool has_target_p ) { if ( ! maybe_expand_insn ( icode , n_ops , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; }"
GCC,riscv,19,"Predict the next statement of this code snippet:
 <s> tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ; tree fsflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_fsflags ) ; tree old_flags = create_tmp_var_raw ( RISCV_ATYPE_USI ) ; * hold = build4 ( TARGET_EXPR , RISCV_ATYPE_USI , old_flags , build_call_expr ( frflags , <NUM_LIT> ) , NULL_TREE , NULL_TREE ) ; * clear = build_call_expr ( fsflags , <NUM_LIT> , old_flags ) ;"
GCC,riscv,20,"Predict the next statement of this code snippet:
 <s> if ( ! TARGET_HARD_FLOAT ) return ; tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ; tree fsflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_fsflags ) ; tree old_flags = create_tmp_var_raw ( RISCV_ATYPE_USI ) ; * hold = build4 ( TARGET_EXPR , RISCV_ATYPE_USI , old_flags , build_call_expr ( frflags , <NUM_LIT> ) , NULL_TREE , NULL_TREE ) ; * clear = build_call_expr ( fsflags , <NUM_LIT> , old_flags ) ; * update = NULL_TREE ;"
GCC,riscv,21,"Predict the next statement of this code snippet:
 <s> if ( types [ ( int ) type ] == NULL_TREE ) switch ( type ) { case RISCV_FTYPE_NAME ## NUM ARGS : \ types [ ( int ) type ] \ = build_function_type_list ( RISCV_FTYPE_ATYPES ## NUM ARGS , \ NULL_TREE ) ; \ break ;"
GCC,riscv,22,"Predict the next statement of this code snippet:
 <s> if ( types [ ( int ) type ] == NULL_TREE ) switch ( type ) { case RISCV_FTYPE_NAME ## NUM ARGS : \ types [ ( int ) type ] \ = build_function_type_list ( RISCV_FTYPE_ATYPES ## NUM ARGS , \ NULL_TREE ) ; \ break ; default : gcc_unreachable ( ) ;"
GCC,riscv,23,"Predict the next statement of this code snippet:
 <s> tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ;"
GCC,riscv,24,"Predict the next statement of this code snippet:
 <s> for ( int argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) riscv_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ;"
GCC,riscv,25,"Predict the next statement of this code snippet:
 <s> error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; }"
GCC,riscv,26,"Predict the next statement of this code snippet:
 <s> tree type = riscv_build_function_type ( d -> prototype ) ; riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ;"
GCC,riscv,27,"Predict the next statement of this code snippet:
 <s> riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode ] = i ; }"
GCC,riscv,28,"Predict the next statement of this code snippet:
 <s> switch ( code & RISCV_BUILTIN_CLASS ) { case RISCV_BUILTIN_GENERAL : return true ; case RISCV_BUILTIN_VECTOR : return <STR_LIT> ( loc , arg_loc , subcode , orig_fndecl , nargs , args ) ;"
GCC,riscv,29,"Predict the next statement of this code snippet:
 <s> if ( ( TARGET_HARD_FLOAT || TARGET_ZFINX ) && TARGET_FDIV ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } switch ( riscv_abi ) { case ABI_ILP32E : builtin_define ( <STR_LIT> ) ; gcc_fallthrough ( ) ; case ABI_ILP32 : case ABI_LP64 : builtin_define ( <STR_LIT> ) ; break ; case ABI_ILP32F : case ABI_LP64F : builtin_define ( <STR_LIT> ) ; break ; case ABI_ILP32D : case ABI_LP64D : builtin_define ( <STR_LIT> ) ; break ; } switch ( riscv_cmodel ) { case CM_MEDLOW : builtin_define ( <STR_LIT> ) ; break ; case CM_PIC : case CM_MEDANY : builtin_define ( <STR_LIT> ) ; break ; } if ( TARGET_MIN_VLEN != <NUM_LIT> ) builtin_define_with_int_value ( <STR_LIT> , TARGET_MIN_VLEN ) ; if ( TARGET_VECTOR_ELEN_64 ) builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; else if ( TARGET_VECTOR_ELEN_32 ) builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; if ( TARGET_VECTOR_ELEN_FP_64 ) builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; else if ( TARGET_VECTOR_ELEN_FP_32 ) builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; else if ( TARGET_MIN_VLEN != <NUM_LIT> ) builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; if ( TARGET_MIN_VLEN ) { builtin_define ( <STR_LIT> ) ; builtin_define_with_int_value ( <STR_LIT> , riscv_ext_version_value ( <NUM_LIT> , <NUM_LIT> ) ) ; } builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; const riscv_subset_list * subset_list = riscv_current_subset_list ( ) ; if ( ! subset_list ) return ; size_t max_ext_len = <NUM_LIT> ; for ( const riscv_subset_t * subset = subset_list -> begin ( ) ; subset != subset_list -> end ( ) ; subset = subset -> next ) max_ext_len = MAX ( max_ext_len , subset -> name . length ( ) ) ; char * buf = ( char * ) alloca ( max_ext_len + <NUM_LIT> ) ; for ( const riscv_subset_t * subset = subset_list -> begin ( ) ; subset != subset_list -> end ( ) ; subset = subset -> next ) { int version_value = riscv_ext_version_value ( subset -> major_version , subset -> minor_version ) ; if ( ( subset -> name == <STR_LIT> || subset -> name == <STR_LIT> ) && version_value == <NUM_LIT> ) version_value = riscv_ext_version_value ( <NUM_LIT> , <NUM_LIT> ) ; sprintf ( buf , <STR_LIT> , subset -> name . c_str ( ) ) ; builtin_define_with_int_value ( buf , version_value ) ;"
GCC,riscv,30,"Predict the next statement of this code snippet:
 <s> return ( major * <NUM_LIT> ) + ( minor * <NUM_LIT> ) ;"
GCC,riscv,31,"Predict the next statement of this code snippet:
 <s> if ( pragma_lex ( & x ) != CPP_STRING ) { error ( <STR_LIT> ) ; return ; } const char * name = TREE_STRING_POINTER ( x ) ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) { if ( ! TARGET_VECTOR ) { error ( <STR_LIT> <STR_LIT> , name ) ; return ; } <STR_LIT> ( ) ;"
GCC,riscv,32,"Predict the next statement of this code snippet:
 <s> targetm . check_builtin_call = riscv_check_builtin_call ; c_register_pragma ( <STR_LIT> , <STR_LIT> , riscv_pragma_intrinsic ) ;"
GCC,riscv,33,"Predict the next statement of this code snippet:
 <s> if ( TARGET_HARD_FLOAT && TARGET_FDIV ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } switch ( riscv_abi ) { case ABI_ILP32 : case ABI_LP64 : builtin_define ( <STR_LIT> ) ; break ; case ABI_ILP32F : case ABI_LP64F : builtin_define ( <STR_LIT> ) ; break ; case ABI_ILP32D : case ABI_LP64D : builtin_define ( <STR_LIT> ) ;"
GCC,riscv,34,"Predict the next statement of this code snippet:
 <s> builtin_define ( <STR_LIT> ) ; break ; case ABI_ILP32D : case ABI_LP64D : builtin_define ( <STR_LIT> ) ; break ; } switch ( riscv_cmodel ) { case CM_MEDLOW : builtin_define ( <STR_LIT> ) ; break ; case CM_PIC : builtin_define ( <STR_LIT> ) ; case CM_MEDANY : builtin_define ( <STR_LIT> ) ; break ; } if ( TARGET_MIN_VLEN != <NUM_LIT> ) builtin_define_with_int_value ( <STR_LIT> , TARGET_MIN_VLEN ) ; if ( TARGET_VECTOR_ELEN_64 ) builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; else if ( TARGET_VECTOR_ELEN_32 ) builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; if ( TARGET_VECTOR_ELEN_FP_64 ) builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; else if ( TARGET_VECTOR_ELEN_FP_32 ) builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; else if ( TARGET_MIN_VLEN != <NUM_LIT> ) builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; if ( TARGET_MIN_VLEN ) builtin_define ( <STR_LIT> ) ; builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; const riscv_subset_list * subset_list = riscv_current_subset_list ( ) ; if ( ! subset_list ) return ; size_t max_ext_len = <NUM_LIT> ; for ( const riscv_subset_t * subset = subset_list -> begin ( ) ; subset != subset_list -> end ( ) ; subset = subset -> next ) max_ext_len = MAX ( max_ext_len , subset -> name . length ( ) ) ; char * buf = ( char * ) alloca ( max_ext_len + <NUM_LIT> ) ; for ( const riscv_subset_t * subset = subset_list -> begin ( ) ; subset != subset_list -> end ( ) ; subset = subset -> next ) { int version_value = ( subset -> major_version * <NUM_LIT> ) + ( subset -> minor_version * <NUM_LIT> ) ; if ( ( subset -> name == <STR_LIT> || subset -> name == <STR_LIT> ) && version_value == <NUM_LIT> ) version_value = <NUM_LIT> ; sprintf ( buf , <STR_LIT> , subset -> name . c_str ( ) ) ; builtin_define_with_int_value ( buf , version_value ) ; }"
GCC,riscv,35,"Predict the next statement of this code snippet:
 <s> abi = <STR_LIT> ; break ; case ABI_ILP32D : case ABI_LP64D : abi = <STR_LIT> ; break ; default :"
GCC,riscv,36,"Predict the next statement of this code snippet:
 <s> void riscv_d_register_target_info ( void ) {"
GCC,riscv,37,"Predict the next statement of this code snippet:
 <s> else d_add_builtin_version ( <STR_LIT> ) ;"
GCC,riscv,38,"Predict the next statement of this code snippet:
 <s> void riscv_d_target_versions ( void ) { if ( TARGET_64BIT ) d_add_builtin_version ( <STR_LIT> ) ; else d_add_builtin_version ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT ) d_add_builtin_version ( <STR_LIT> ) ; else d_add_builtin_version ( <STR_LIT> ) ;"
GCC,riscv,39,"Predict the next statement of this code snippet:
 <s> gcc_assert ( REG_P ( dest ) ) ; rtx note = find_reg_equal_equiv_note ( insn ) ; unsigned regno = REGNO ( dest ) ; if ( note ) regno_to_rtx [ regno ] = XEXP ( note , <NUM_LIT> ) ; else regno_to_rtx [ regno ] = SET_SRC ( pat ) ; } return eval_value ( reg , regno_to_rtx ) ;"
GCC,riscv,40,"Predict the next statement of this code snippet:
 <s> } if ( BINARY_P ( expr ) ) { op1_val = eval_value ( XEXP ( expr , <NUM_LIT> ) , regno_to_rtx ) ; op2_val = eval_value ( XEXP ( expr , <NUM_LIT> ) , regno_to_rtx ) ; } switch ( GET_CODE ( expr ) ) { case CONST_POLY_INT : return rtx_to_poly_int64 ( expr ) ; case CONST_INT : return INTVAL ( expr ) ; case MULT : if ( op1_val . is_constant ( ) ) return op1_val . to_constant ( ) * op2_val ;"
GCC,riscv,41,"Predict the next statement of this code snippet:
 <s> rtx_insn * insn = get_last_insn ( ) ; rtx src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; ASSERT_TRUE ( rtx_equal_p ( src , CONSTM1_RTX ( mode ) ) ) ;"
GCC,riscv,42,"Predict the next statement of this code snippet:
 <s> run_poly_int_selftests ( ) ;"
GCC,riscv,43,"Predict the next statement of this code snippet:
 <s> riscv_selftest_arch_abi_setter ( const char * arch , enum riscv_abi_type abi ) : m_arch_backup ( riscv_arch_str ( ) ) , m_abi_backup ( riscv_abi ) { riscv_parse_arch_string ( arch , & global_options , UNKNOWN_LOCATION ) ; riscv_abi = abi ; riscv_reinit ( ) ;"
GCC,riscv,44,"Predict the next statement of this code snippet:
 <s> else ASSERT_TRUE ( rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; end_sequence ( ) ; } } } FOR_EACH_MODE_IN_CLASS ( mode , MODE_VECTOR_FLOAT ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { scalar_mode inner_mode = GET_MODE_INNER ( mode ) ; REAL_VALUE_TYPE f = REAL_VALUE_ATOF ( <STR_LIT> , inner_mode ) ; rtx ele = const_double_from_real_value ( f , inner_mode ) ; start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; rtx dup = gen_const_vec_duplicate ( mode , ele ) ; emit_move_insn ( dest , dup ) ; rtx_insn * insn = get_last_insn ( ) ; rtx src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; ASSERT_TRUE ( rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; end_sequence ( ) ; } } FOR_EACH_MODE_IN_CLASS ( mode , MODE_VECTOR_BOOL ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ;"
GCC,riscv,45,"Predict the next statement of this code snippet:
 <s> if ( riscv_v_ext_vector_mode_p ( mode ) ) { scalar_mode inner_mode = GET_MODE_INNER ( mode ) ; REAL_VALUE_TYPE f = REAL_VALUE_ATOF ( <STR_LIT> , inner_mode ) ; rtx ele = const_double_from_real_value ( f , inner_mode ) ; start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; rtx dup = gen_const_vec_duplicate ( mode , ele ) ; emit_move_insn ( dest , dup ) ; rtx_insn * insn = get_last_insn ( ) ; rtx src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; ASSERT_TRUE ( rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; end_sequence ( ) ; } } FOR_EACH_MODE_IN_CLASS ( mode , MODE_VECTOR_BOOL ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; emit_move_insn ( dest , CONSTM1_RTX ( mode ) ) ;"
GCC,riscv,46,"Predict the next statement of this code snippet:
 <s> gcc_unreachable ( ) ; } for ( const poly_int64 & poly_val : worklist ) { start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; emit_move_insn ( dest , gen_int_mode ( poly_val , mode ) ) ; ASSERT_TRUE ( known_eq ( calculate_x_in_sequence ( dest ) , poly_val ) ) ;"
GCC,riscv,47,"Predict the next statement of this code snippet:
 <s> static void run_poly_int_selftests ( void ) { std :: vector < poly_int64 > worklist = { BYTES_PER_RISCV_VECTOR , BYTES_PER_RISCV_VECTOR * <NUM_LIT> , BYTES_PER_RISCV_VECTOR * <NUM_LIT> , - BYTES_PER_RISCV_VECTOR * <NUM_LIT> , - BYTES_PER_RISCV_VECTOR * <NUM_LIT> , BYTES_PER_RISCV_VECTOR * <NUM_LIT> , BYTES_PER_RISCV_VECTOR * <NUM_LIT> , - BYTES_PER_RISCV_VECTOR * <NUM_LIT> , - BYTES_PER_RISCV_VECTOR * <NUM_LIT> , BYTES_PER_RISCV_VECTOR * <NUM_LIT> , BYTES_PER_RISCV_VECTOR * <NUM_LIT> , - BYTES_PER_RISCV_VECTOR * <NUM_LIT> , - BYTES_PER_RISCV_VECTOR * <NUM_LIT> , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( - <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , - <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , <NUM_LIT> ) , poly_int64 ( <NUM_LIT> , - <NUM_LIT> ) } ;"
GCC,riscv,48,"Predict the next statement of this code snippet:
 <s> rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( <STR_LIT> ) ) ; set_new_first_and_last_insn ( NULL , NULL ) ;"
GCC,riscv,49,"Predict the next statement of this code snippet:
 <s> static void simple_poly_selftest ( const char * arch , enum riscv_abi_type abi , const std :: vector < machine_mode > & modes ) { riscv_selftest_arch_abi_setter rv ( arch , abi ) ; rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( <STR_LIT> ) ) ;"
GCC,riscv,50,"Predict the next statement of this code snippet:
 <s> ~ riscv_selftest_arch_abi_setter ( ) { riscv_parse_arch_string ( m_arch_backup . c_str ( ) , & global_options , UNKNOWN_LOCATION ) ;"
GCC,riscv,51,"Predict the next statement of this code snippet:
 <s> riscv_parse_arch_string ( m_arch_backup . c_str ( ) , & global_options , UNKNOWN_LOCATION ) ;"
GCC,riscv,52,"Predict the next statement of this code snippet:
 <s> rtx_insn * insn ; regstat_init_n_sets_and_refs ( ) ; FOR_BB_INSNS ( bb , insn ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx mem = XEXP ( pat , i ) ; rtx addr ; bool extend = false ; if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) { if ( XEXP ( pat , <NUM_LIT> ) == CONST0_RTX ( GET_MODE ( XEXP ( pat , <NUM_LIT> ) ) ) ) continue ; } if ( REG_N_REFS ( regno ) < <NUM_LIT> ) continue ;"
GCC,riscv,53,"Predict the next statement of this code snippet:
 <s> if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) { if ( XEXP ( pat , <NUM_LIT> ) == CONST0_RTX ( GET_MODE ( XEXP ( pat , <NUM_LIT> ) ) ) ) continue ; } if ( REG_N_REFS ( regno ) < <NUM_LIT> ) continue ;"
GCC,riscv,54,"Predict the next statement of this code snippet:
 <s> unsigned int pass_shorten_memrefs :: execute ( function * fn ) { basic_block bb ; FOR_ALL_BB_FN ( bb , fn ) { regno_map * m ; if ( optimize_bb_for_speed_p ( bb ) ) continue ; m = analyze ( bb ) ;"
GCC,riscv,55,"Predict the next statement of this code snippet:
 <s> unsigned int pass_shorten_memrefs :: execute ( function * fn ) { basic_block bb ; FOR_ALL_BB_FN ( bb , fn ) { regno_map * m ; if ( optimize_bb_for_speed_p ( bb ) ) continue ; m = analyze ( bb ) ; transform ( m , bb ) ;"
GCC,riscv,56,"Predict the next statement of this code snippet:
 <s> FOR_ALL_BB_FN ( bb , fn ) {"
GCC,riscv,57,"Predict the next statement of this code snippet:
 <s> if ( optimize_bb_for_speed_p ( bb ) ) continue ;"
GCC,riscv,58,"Predict the next statement of this code snippet:
 <s> FOR_BB_INSNS ( bb , insn ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx mem = XEXP ( pat , i ) ; rtx addr ; bool extend = false ; if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) { if ( XEXP ( pat , <NUM_LIT> ) == CONST0_RTX ( GET_MODE ( XEXP ( pat , <NUM_LIT> ) ) ) ) continue ; } if ( m -> get_or_insert ( regno ) > <NUM_LIT> ) { if ( extend ) { addr = targetm . legitimize_address ( addr , addr , GET_MODE ( XEXP ( mem , <NUM_LIT> ) ) ) ; XEXP ( XEXP ( pat , i ) , <NUM_LIT> ) = replace_equiv_address ( XEXP ( mem , <NUM_LIT> ) , addr ) ; } else { addr = targetm . legitimize_address ( addr , addr , GET_MODE ( mem ) ) ;"
GCC,riscv,59,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx mem = XEXP ( pat , i ) ; rtx addr ; bool extend = false ; if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ;"
GCC,riscv,60,"Predict the next statement of this code snippet:
 <s> virtual bool gate ( function * ) { return TARGET_RVC && riscv_mshorten_memrefs && optimize > <NUM_LIT> ;"
GCC,riscv,61,"Predict the next statement of this code snippet:
 <s> return TARGET_RVC && riscv_mshorten_memrefs && optimize > <NUM_LIT> ;"
GCC,riscv,62,"Predict the next statement of this code snippet:
 <s> * extend = true ; mem = XEXP ( mem , <NUM_LIT> ) ; } if ( ! MEM_P ( mem ) || GET_MODE ( mem ) != SImode ) return false ;"
GCC,riscv,63,"Predict the next statement of this code snippet:
 <s> * addr = XEXP ( mem , <NUM_LIT> ) ; return GET_CODE ( * addr ) == PLUS && REG_P ( XEXP ( * addr , <NUM_LIT> ) ) ;"
GCC,riscv,64,"Predict the next statement of this code snippet:
 <s> rtl_opt_pass * make_pass_shorten_memrefs ( gcc :: context * ctxt ) {"
GCC,riscv,65,"Predict the next statement of this code snippet:
 <s> pass_shorten_memrefs ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_shorten_memrefs , ctxt ) {"
GCC,riscv,66,"Predict the next statement of this code snippet:
 <s> pass_shorten_memrefs ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_shorten_memrefs , ctxt ) {"
GCC,riscv,67,"Predict the next statement of this code snippet:
 <s> rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx mem = XEXP ( pat , i ) ; rtx addr ; bool extend = false ; if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) { if ( XEXP ( pat , <NUM_LIT> ) == CONST0_RTX ( GET_MODE ( XEXP ( pat , <NUM_LIT> ) ) ) ) continue ; } if ( m -> get_or_insert ( regno ) > <NUM_LIT> ) { if ( extend ) { addr = targetm . legitimize_address ( addr , addr , GET_MODE ( XEXP ( mem , <NUM_LIT> ) ) ) ; XEXP ( XEXP ( pat , i ) , <NUM_LIT> ) = replace_equiv_address ( XEXP ( mem , <NUM_LIT> ) , addr ) ; }"
GCC,riscv,68,"Predict the next statement of this code snippet:
 <s> if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; rtx_insn * tmp = NEXT_INSN ( prologue ) ; if ( ! NOTE_P ( tmp ) || NOTE_KIND ( tmp ) != NOTE_INSN_PROLOGUE_END ) return ; do { tmp = NEXT_INSN ( tmp ) ; } while ( tmp != NULL && NOTE_P ( tmp ) ) ; if ( tmp == NULL || ! INSN_P ( tmp ) ) return ;"
GCC,riscv,69,"Predict the next statement of this code snippet:
 <s> } if ( ! INSN_P ( insn ) ) continue ; if ( CALL_P ( insn ) ) ++ call_count ; else if ( insn == prologue_matched ) ; else { df_ref use ; FOR_EACH_INSN_USE ( use , insn ) { if ( ! call_used_regs [ DF_REF_REGNO ( use ) ] ) {"
GCC,riscv,70,"Predict the next statement of this code snippet:
 <s> if ( ! INSN_P ( insn ) ) continue ; if ( CALL_P ( insn ) ) ++ call_count ; else if ( insn == prologue_matched ) ; else { df_ref use ; FOR_EACH_INSN_USE ( use , insn ) { if ( ! call_used_regs [ DF_REF_REGNO ( use ) ] ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) ) ; good_use = false ; break ; }"
GCC,riscv,71,"Predict the next statement of this code snippet:
 <s> break ; } if ( ! INSN_P ( insn ) ) continue ; if ( CALL_P ( insn ) ) ++ call_count ; else if ( insn == prologue_matched ) ; else { df_ref use ; FOR_EACH_INSN_USE ( use , insn ) { if ( ! call_used_regs [ DF_REF_REGNO ( use ) ] ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) ) ; good_use = false ; break ; } }"
GCC,riscv,72,"Predict the next statement of this code snippet:
 <s> if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) ) ; good_use = false ; break ; }"
GCC,riscv,73,"Predict the next statement of this code snippet:
 <s> if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) ) ; good_use = false ;"
GCC,riscv,74,"Predict the next statement of this code snippet:
 <s> } if ( ! good_use ) return ; if ( epilogue_count != <NUM_LIT> ) return ; if ( call_count > <NUM_LIT> ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; return ; } rtx_insn * epilogue_begin_note = PREV_INSN ( epilogue_matched ) ; gcc_assert ( NOTE_P ( epilogue_begin_note ) && NOTE_KIND ( epilogue_begin_note ) == NOTE_INSN_EPILOGUE_BEG ) ; df_finish_pass ( false ) ; rtx_insn * insn_before_epilogue ; for ( insn_before_epilogue = PREV_INSN ( epilogue_begin_note ) ; NOTE_P ( insn_before_epilogue ) ; insn_before_epilogue = PREV_INSN ( insn_before_epilogue ) ) ; if ( GET_CODE ( insn_before_epilogue ) != CALL_INSN ) return ; rtx_insn * call = insn_before_epilogue ; rtx callpat = PATTERN ( call ) ; gcc_assert ( GET_CODE ( callpat ) == PARALLEL ) ; rtx target_call = NULL ; rtx tmp_rtx = XVECEXP ( callpat , <NUM_LIT> , <NUM_LIT> ) ; rtx set_target = NULL ; switch ( GET_CODE ( tmp_rtx ) ) { case CALL : target_call = tmp_rtx ; break ; case SET : { set_target = XEXP ( tmp_rtx , <NUM_LIT> ) ; tmp_rtx = XEXP ( tmp_rtx , <NUM_LIT> ) ; if ( GET_CODE ( tmp_rtx ) != CALL ) return ; target_call = tmp_rtx ; break ; } default : return ; } rtx target_mem = XEXP ( target_call , <NUM_LIT> ) ; if ( GET_CODE ( target_mem ) != MEM ) return ; rtx target = XEXP ( target_mem , <NUM_LIT> ) ; if ( GET_CODE ( target ) != SYMBOL_REF && GET_CODE ( target ) != REG ) return ;"
GCC,riscv,75,"Predict the next statement of this code snippet:
 <s> static rtx_insn * riscv_sr_match_epilogue ( void ) { rtx_insn * insn , * start ; for ( insn = get_insns ( ) ; insn != NULL ; insn = NEXT_INSN ( insn ) ) if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_EPILOGUE_BEG ) { insn = NEXT_INSN ( insn ) ; break ; } if ( insn == NULL ) return NULL ; start = insn ; if ( INSN_CODE ( insn ) != CODE_FOR_stack_tiesi && INSN_CODE ( insn ) != CODE_FOR_stack_tiedi ) return NULL ; insn = NEXT_INSN ( insn ) ;"
GCC,riscv,76,"Predict the next statement of this code snippet:
 <s> if ( INSN_P ( insn ) && INSN_CODE ( insn ) == CODE_FOR_gpr_save && GET_CODE ( PATTERN ( insn ) ) == PARALLEL && GET_CODE ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) == UNSPEC_VOLATILE && ( GET_CODE ( XVECEXP ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ) == CONST_INT ) && INTVAL ( XVECEXP ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ) == <NUM_LIT> ) return insn ; return NULL ;"
GCC,riscv,77,"Predict the next statement of this code snippet:
 <s> bool apply_mask_policy_p ( ) const override { return false ;"
GCC,riscv,78,"Predict the next statement of this code snippet:
 <s> bool apply_mask_policy_p ( ) const override {"
GCC,riscv,79,"Predict the next statement of this code snippet:
 <s> return false ;"
GCC,riscv,80,"Predict the next statement of this code snippet:
 <s> return CP_READ_MEMORY | CP_WRITE_CSR ;"
GCC,riscv,81,"Predict the next statement of this code snippet:
 <s> return CP_READ_MEMORY | CP_WRITE_CSR ;"
GCC,riscv,82,"Predict the next statement of this code snippet:
 <s> return pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu ;"
GCC,riscv,83,"Predict the next statement of this code snippet:
 <s> bool can_be_overloaded_p ( enum predication_type_index pred ) const override {"
GCC,riscv,84,"Predict the next statement of this code snippet:
 <s> machine_mode mode = GET_MODE ( e . target ) ;"
GCC,riscv,85,"Predict the next statement of this code snippet:
 <s> rtx expand ( function_expander & e ) const override { machine_mode mode = GET_MODE ( e . target ) ; rtx vlenb = gen_int_mode ( BYTES_PER_RISCV_VECTOR , mode ) ;"
GCC,riscv,86,"Predict the next statement of this code snippet:
 <s> gimple_call_set_lhs ( g , tmp_var ) ; tree indirect = fold_build2 ( MEM_REF , size_type_node , gimple_call_arg ( f . call , gimple_call_num_args ( f . call ) - <NUM_LIT> ) , build_int_cst ( build_pointer_type ( size_type_node ) , <NUM_LIT> ) ) ; gassign * assign = gimple_build_assign ( indirect , tmp_var ) ; gsi_insert_after ( f . gsi , assign , GSI_SAME_STMT ) ; gsi_insert_after ( f . gsi , g , GSI_SAME_STMT ) ;"
GCC,riscv,87,"Predict the next statement of this code snippet:
 <s> if ( integer_zerop ( new_vl ) ) { return repl ; } tree tmp_var = create_tmp_var ( size_type_node , <STR_LIT> ) ; tree decl = get_read_vl_decl ( ) ; gimple * g = gimple_build_call ( decl , <NUM_LIT> ) ; gimple_call_set_lhs ( g , tmp_var ) ; tree indirect = fold_build2 ( MEM_REF , size_type_node , gimple_call_arg ( f . call , gimple_call_num_args ( f . call ) - <NUM_LIT> ) , build_int_cst ( build_pointer_type ( size_type_node ) , <NUM_LIT> ) ) ; gassign * assign = gimple_build_assign ( indirect , tmp_var ) ;"
GCC,riscv,88,"Predict the next statement of this code snippet:
 <s> if ( UNSPEC == UNSPEC_VSLIDEUP ) return false ; return true ;"
GCC,riscv,89,"Predict the next statement of this code snippet:
 <s> bool use_mask_predication_p ( ) const override { return false ;"
GCC,riscv,90,"Predict the next statement of this code snippet:
 <s> bool use_mask_predication_p ( ) const override { return false ;"
GCC,riscv,91,"Predict the next statement of this code snippet:
 <s> function_instance function_instance ( group . base_name , * group . base , * group . shape , group . ops_infos . types [ <NUM_LIT> ] , group . preds [ <NUM_LIT> ] , & group . ops_infos ) ; b . add_unique_function ( function_instance , ( * group . shape ) , long_unsigned_type_node , argument_types ) ;"
GCC,riscv,92,"Predict the next statement of this code snippet:
 <s> for ( unsigned int pred_idx = <NUM_LIT> ; group . preds [ pred_idx ] != NUM_PRED_TYPES ;"
GCC,riscv,93,"Predict the next statement of this code snippet:
 <s> for ( unsigned int pred_idx = <NUM_LIT> ; group . preds [ pred_idx ] != NUM_PRED_TYPES ;"
GCC,riscv,94,"Predict the next statement of this code snippet:
 <s> auto_vec < tree , <NUM_LIT> > argument_types ; function_instance function_instance ( group . base_name , * group . base , * group . shape , group . ops_infos . types [ vec_type_idx ] , group . preds [ pred_idx ] , & group . ops_infos ) ; tree return_type = group . ops_infos . ret . get_tree_type ( group . ops_infos . types [ vec_type_idx ] . index ) ;"
GCC,riscv,95,"Predict the next statement of this code snippet:
 <s> auto_vec < tree , <NUM_LIT> > argument_types ;"
GCC,riscv,96,"Predict the next statement of this code snippet:
 <s> bool check ( function_checker & c ) const override { poly_int64 outer_size = GET_MODE_SIZE ( c . arg_mode ( <NUM_LIT> ) ) ; poly_int64 inner_size = GET_MODE_SIZE ( c . ret_mode ( ) ) ; unsigned int nvecs = exact_div ( outer_size , inner_size ) . to_constant ( ) ; return c . require_immediate ( <NUM_LIT> , <NUM_LIT> , nvecs - <NUM_LIT> ) ;"
GCC,riscv,97,"Predict the next statement of this code snippet:
 <s> b . append_name ( <STR_LIT> ) ; if ( ! overloaded_p ) { b . append_name ( operand_suffixes [ instance . op_info -> op ] ) ; b . append_name ( type_suffixes [ instance . type . index ] . vector ) ; } if ( overloaded_p && instance . pred == PRED_TYPE_m ) return b . finish_name ( ) ; b . append_name ( predication_suffixes [ instance . pred ] ) ;"
GCC,riscv,98,"Predict the next statement of this code snippet:
 <s> add_input_operand ( mode , CONSTM1_RTX ( mode ) ) ;"
GCC,riscv,99,"Predict the next statement of this code snippet:
 <s> static tree add_attribute ( const char * name , tree attrs ) { return tree_cons ( get_identifier ( name ) , NULL_TREE , attrs ) ;"
GCC,riscv,100,"Predict the next statement of this code snippet:
 <s> return tree_cons ( get_identifier ( name ) , NULL_TREE , attrs ) ;"
GCC,riscv,101,"Predict the next statement of this code snippet:
 <s> create_fixed_operand ( & m_ops [ opno ++ ] , x ) ;"
GCC,riscv,102,"Predict the next statement of this code snippet:
 <s> registered_function & function_builder :: add_function ( const function_instance & instance , const char * name , tree fntype , tree attrs , bool placeholder_p ) { unsigned int code = vec_safe_length ( registered_functions ) ; code = ( code << RISCV_BUILTIN_SHIFT ) + RISCV_BUILTIN_VECTOR ; tree decl = placeholder_p ? integer_zero_node : simulate_builtin_function_decl ( input_location , name , fntype , code , NULL , attrs ) ; registered_function & rfn = * ggc_alloc < registered_function > ( ) ; rfn . instance = instance ; rfn . decl = decl ; vec_safe_push ( registered_functions , & rfn ) ; return rfn ;"
GCC,riscv,103,"Predict the next statement of this code snippet:
 <s> inline void function_expander :: add_input_operand ( machine_mode mode , rtx op ) {"
GCC,riscv,104,"Predict the next statement of this code snippet:
 <s> create_input_operand ( & m_ops [ opno ++ ] , op , mode ) ;"
GCC,riscv,105,"Predict the next statement of this code snippet:
 <s> inline void function_expander :: add_integer_operand ( rtx x ) { create_integer_operand ( & m_ops [ opno ++ ] , INTVAL ( x ) ) ;"
GCC,riscv,106,"Predict the next statement of this code snippet:
 <s> create_integer_operand ( & m_ops [ opno ++ ] , INTVAL ( x ) ) ;"
GCC,riscv,107,"Predict the next statement of this code snippet:
 <s> rtx mem = gen_rtx_MEM ( mode , memory_address ( mode , addr ) ) ;"
GCC,riscv,108,"Predict the next statement of this code snippet:
 <s> inline void function_expander :: add_output_operand ( machine_mode mode , rtx target ) { create_output_operand ( & m_ops [ opno ++ ] , target , mode ) ;"
GCC,riscv,109,"Predict the next statement of this code snippet:
 <s> inline void function_expander :: add_scalar_move_mask_operand ( machine_mode mode ) { add_input_operand ( mode , gen_scalar_move_mask ( mode ) ) ;"
GCC,riscv,110,"Predict the next statement of this code snippet:
 <s> static void add_vector_type_attribute ( tree type , const char * mangled_name ) { tree mangled_name_tree = get_identifier ( mangled_name ) ; tree value = tree_cons ( NULL_TREE , mangled_name_tree , NULL_TREE ) ; TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , value , TYPE_ATTRIBUTES ( type ) ) ;"
GCC,riscv,111,"Predict the next statement of this code snippet:
 <s> tree value = tree_cons ( NULL_TREE , mangled_name_tree , NULL_TREE ) ; TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , value , TYPE_ATTRIBUTES ( type ) ) ;"
GCC,riscv,112,"Predict the next statement of this code snippet:
 <s> void function_expander :: add_vundef_operand ( machine_mode mode ) {"
GCC,riscv,113,"Predict the next statement of this code snippet:
 <s> for ( unsigned int i = <NUM_LIT> ;"
GCC,riscv,114,"Predict the next statement of this code snippet:
 <s> void function_builder :: allocate_argument_types ( const function_instance & instance , vec < tree > & argument_types ) const {"
GCC,riscv,115,"Predict the next statement of this code snippet:
 <s> for ( int i = <NUM_LIT> ; op_info -> args [ i ] . base_type != NUM_BASE_TYPES ; ++ i ) if ( FLOAT_MODE_P ( TYPE_MODE ( get_arg_type ( i ) ) ) ) return true ;"
GCC,riscv,116,"Predict the next statement of this code snippet:
 <s> append_name ( <STR_LIT> ) ; append_name ( name ) ;"
GCC,riscv,117,"Predict the next statement of this code snippet:
 <s> void function_builder :: append_base_name ( const char * name ) { append_name ( <STR_LIT> ) ;"
GCC,riscv,118,"Predict the next statement of this code snippet:
 <s> obstack_grow ( & m_string_obstack , name , strlen ( name ) ) ;"
GCC,riscv,119,"Predict the next statement of this code snippet:
 <s> obstack_grow ( & m_string_obstack , name , strlen ( name ) ) ;"
GCC,riscv,120,"Predict the next statement of this code snippet:
 <s> break ; case <NUM_LIT> : append_name ( <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; }"
GCC,riscv,121,"Predict the next statement of this code snippet:
 <s> inline bool function_base :: apply_mask_policy_p ( ) const { return true ;"
GCC,riscv,122,"Predict the next statement of this code snippet:
 <s> inline bool function_base :: apply_mask_policy_p ( ) const { return true ;"
GCC,riscv,123,"Predict the next statement of this code snippet:
 <s> void function_builder :: apply_predication ( const function_instance & instance , tree return_type , vec < tree > & argument_types ) const { if ( instance . base -> has_merge_operand_p ( ) ) if ( instance . pred == PRED_TYPE_tu || instance . pred == PRED_TYPE_tum || instance . pred == PRED_TYPE_tumu || instance . pred == PRED_TYPE_mu ) argument_types . quick_insert ( <NUM_LIT> , return_type ) ; vector_type_index mask_type_index = function_types [ instance . type . index ] . type_indexes [ RVV_BASE_mask ] ; tree mask_type = builtin_types [ mask_type_index ] . vector ; if ( instance . pred == PRED_TYPE_m || instance . pred == PRED_TYPE_tum || instance . pred == PRED_TYPE_tumu || instance . pred == PRED_TYPE_mu ) argument_types . quick_insert ( <NUM_LIT> , mask_type ) ;"
GCC,riscv,124,"Predict the next statement of this code snippet:
 <s> return true ;"
GCC,riscv,125,"Predict the next statement of this code snippet:
 <s> inline bool function_base :: apply_vl_p ( ) const { return true ;"
GCC,riscv,126,"Predict the next statement of this code snippet:
 <s> return TYPE_MODE ( TREE_TYPE ( m_args [ argno ] ) ) ;"
GCC,riscv,127,"Predict the next statement of this code snippet:
 <s> static tree build_const_pointer ( tree t ) { return build_pointer_type ( build_qualified_type ( t , TYPE_QUAL_CONST ) ) ;"
GCC,riscv,128,"Predict the next statement of this code snippet:
 <s> return build_pointer_type ( build_qualified_type ( t , TYPE_QUAL_CONST ) ) ;"
GCC,riscv,129,"Predict the next statement of this code snippet:
 <s> inline unsigned int function_base :: call_properties ( const function_instance & instance ) const {"
GCC,riscv,130,"Predict the next statement of this code snippet:
 <s> if ( instance . any_type_float_p ( ) ) return flags | CP_READ_FPCR | CP_RAISE_FP_EXCEPTIONS ;"
GCC,riscv,131,"Predict the next statement of this code snippet:
 <s> inline bool function_base :: can_be_overloaded_p ( enum predication_type_index ) const { return true ;"
GCC,riscv,132,"Predict the next statement of this code snippet:
 <s> inline bool function_base :: can_be_overloaded_p ( enum predication_type_index ) const { return true ;"
GCC,riscv,133,"Predict the next statement of this code snippet:
 <s> return true ;"
GCC,riscv,134,"Predict the next statement of this code snippet:
 <s> bool check_builtin_call ( location_t location , vec < location_t > , unsigned int code , tree fndecl , unsigned int nargs , tree * args ) { const registered_function & rfn = * ( * registered_functions ) [ code ] ;"
GCC,riscv,135,"Predict the next statement of this code snippet:
 <s> if ( required_extensions_p ( op_info -> ret . base_type ) ) { enum vector_type_index ret_type_idx = op_info -> ret . get_function_type_index ( type_info . index ) ; if ( ret_type_idx == NUM_VECTOR_TYPES ) return false ; required_extensions |= get_required_extensions ( ret_type_idx ) ; } for ( unsigned i = <NUM_LIT> ; op_info -> args [ i ] . base_type != NUM_BASE_TYPES ; ++ i ) { if ( ! required_extensions_p ( op_info -> args [ i ] . base_type ) ) continue ; enum vector_type_index vector_type = op_info -> args [ i ] . get_function_type_index ( type_info . index ) ; if ( vector_type == NUM_VECTOR_TYPES ) return false ; required_extensions |= get_required_extensions ( vector_type ) ; if ( op_info -> args [ i ] . base_type == RVV_BASE_eew64_index ) required_extensions |= RVV_REQUIRE_RV64BIT ; } uint64_t riscv_isa_flags = <NUM_LIT> ; if ( TARGET_VECTOR_ELEN_FP_32 ) riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_32 ; if ( TARGET_VECTOR_ELEN_FP_64 ) riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_64 ; if ( TARGET_VECTOR_ELEN_64 ) riscv_isa_flags |= RVV_REQUIRE_ELEN_64 ;"
GCC,riscv,136,"Predict the next statement of this code snippet:
 <s> if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( CP_READ_MEMORY | CP_WRITE_MEMORY ) ) return true ; return false ;"
GCC,riscv,137,"Predict the next statement of this code snippet:
 <s> bool function_instance :: could_trap_p ( ) const { unsigned int flags = call_properties ( ) ;"
GCC,riscv,138,"Predict the next statement of this code snippet:
 <s> inline bool registered_function_hasher :: equal ( value_type value , const compare_type & key ) {"
GCC,riscv,139,"Predict the next statement of this code snippet:
 <s> inline rtx function_expander :: expand ( ) { return base -> expand ( * this ) ;"
GCC,riscv,140,"Predict the next statement of this code snippet:
 <s> return base -> expand ( * this ) ;"
GCC,riscv,141,"Predict the next statement of this code snippet:
 <s> rtx expand_builtin ( unsigned int code , tree exp , rtx target ) {"
GCC,riscv,142,"Predict the next statement of this code snippet:
 <s> rtx expand_builtin ( unsigned int code , tree exp , rtx target ) { registered_function & rfn = * ( * registered_functions ) [ code ] ; return function_expander ( rfn . instance , rfn . decl , exp , target ) . expand ( ) ;"
GCC,riscv,143,"Predict the next statement of this code snippet:
 <s> return ( char * ) obstack_finish ( & m_string_obstack ) ;"
GCC,riscv,144,"Predict the next statement of this code snippet:
 <s> char * function_builder :: finish_name ( ) { obstack_1grow ( & m_string_obstack , <NUM_LIT> ) ;"
GCC,riscv,145,"Predict the next statement of this code snippet:
 <s> m_direct_overloads = lang_GNU_CXX ( ) ; gcc_obstack_init ( & m_string_obstack ) ;"
GCC,riscv,146,"Predict the next statement of this code snippet:
 <s> function_builder :: function_builder ( ) { m_direct_overloads = lang_GNU_CXX ( ) ;"
GCC,riscv,147,"Predict the next statement of this code snippet:
 <s> function_call_info :: function_call_info ( location_t location_in , const function_instance & instance_in , tree fndecl_in ) : function_instance ( instance_in ) , location ( location_in ) , fndecl ( fndecl_in ) {"
GCC,riscv,148,"Predict the next statement of this code snippet:
 <s> function_call_info :: function_call_info ( location_t location_in , const function_instance & instance_in , tree fndecl_in ) : function_instance ( instance_in ) , location ( location_in ) , fndecl ( fndecl_in ) {"
GCC,riscv,149,"Predict the next statement of this code snippet:
 <s> function_checker :: function_checker ( location_t location , const function_instance & instance , tree fndecl , tree fntype , unsigned int nargs , tree * args ) : function_call_info ( location , instance , fndecl ) , m_fntype ( fntype ) , m_nargs ( nargs ) , m_args ( args ) {"
GCC,riscv,150,"Predict the next statement of this code snippet:
 <s> function_checker :: function_checker ( location_t location , const function_instance & instance , tree fndecl , tree fntype , unsigned int nargs , tree * args ) : function_call_info ( location , instance , fndecl ) , m_fntype ( fntype ) , m_nargs ( nargs ) , m_args ( args ) {"
GCC,riscv,151,"Predict the next statement of this code snippet:
 <s> function_expander :: function_expander ( const function_instance & instance , tree fndecl_in , tree exp_in , rtx target_in ) : function_call_info ( EXPR_LOCATION ( exp_in ) , instance , fndecl_in ) , exp ( exp_in ) , target ( target_in ) , opno ( <NUM_LIT> ) { if ( ! function_returns_void_p ( ) ) create_output_operand ( & m_ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ;"
GCC,riscv,152,"Predict the next statement of this code snippet:
 <s> function_instance :: function_instance ( const char * base_name_in , const function_base * base_in , const function_shape * shape_in , rvv_type_info type_in , predication_type_index pred_in , const rvv_op_info * op_info_in ) : base_name ( base_name_in ) , base ( base_in ) , shape ( shape_in ) , type ( type_in ) , pred ( pred_in ) , op_info ( op_info_in ) {"
GCC,riscv,153,"Predict the next statement of this code snippet:
 <s> function_instance :: function_instance ( const char * base_name_in , const function_base * base_in , const function_shape * shape_in , rvv_type_info type_in , predication_type_index pred_in , const rvv_op_info * op_info_in ) : base_name ( base_name_in ) , base ( base_in ) , shape ( shape_in ) , type ( type_in ) , pred ( pred_in ) , op_info ( op_info_in ) {"
GCC,riscv,154,"Predict the next statement of this code snippet:
 <s> inline bool function_call_info :: function_returns_void_p ( ) {"
GCC,riscv,155,"Predict the next statement of this code snippet:
 <s> rtx function_expander :: generate_insn ( insn_code icode ) { gcc_assert ( opno == insn_data [ icode ] . n_generator_args ) ; if ( ! maybe_expand_insn ( icode , opno , m_ops ) ) {"
GCC,riscv,156,"Predict the next statement of this code snippet:
 <s> if ( ! maybe_expand_insn ( icode , opno , m_ops ) ) { error ( <STR_LIT> ) ; return NULL_RTX ; }"
GCC,riscv,157,"Predict the next statement of this code snippet:
 <s> return op_info -> args [ opno ] . get_tree_type ( type . index ) ;"
GCC,riscv,158,"Predict the next statement of this code snippet:
 <s> tree function_builder :: get_attributes ( const function_instance & instance ) { tree attrs = NULL_TREE ; if ( ! instance . modifies_global_state_p ( ) ) { if ( instance . reads_global_state_p ( ) ) attrs = add_attribute ( <STR_LIT> , attrs ) ; else attrs = add_attribute ( <STR_LIT> , attrs ) ;"
GCC,riscv,159,"Predict the next statement of this code snippet:
 <s> tree type = builtin_types [ function_types [ type_idx ] . type_indexes [ base_type ] ] . vector ; return type ? function_types [ type_idx ] . type_indexes [ base_type ] : NUM_VECTOR_TYPES ;"
GCC,riscv,160,"Predict the next statement of this code snippet:
 <s> vector_type_index <STR_LIT> ( vector_type_index type_idx ) const { tree type = builtin_types [ function_types [ type_idx ] . type_indexes [ base_type ] ] . vector ; return type ? function_types [ type_idx ] . type_indexes [ base_type ] : NUM_VECTOR_TYPES ;"
GCC,riscv,161,"Predict the next statement of this code snippet:
 <s> if ( pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu ) return gen_int_mode ( MASK_UNDISTURBED , Pmode ) ; return gen_int_mode ( get_prefer_mask_policy ( ) , Pmode ) ;"
GCC,riscv,162,"Predict the next statement of this code snippet:
 <s> if ( pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu ) return gen_int_mode ( MASK_UNDISTURBED , Pmode ) ; return gen_int_mode ( get_prefer_mask_policy ( ) , Pmode ) ;"
GCC,riscv,163,"Predict the next statement of this code snippet:
 <s> function_instance instance = get_read_vl_instance ( ) ; hashval_t hash = instance . hash ( ) ;"
GCC,riscv,164,"Predict the next statement of this code snippet:
 <s> return function_instance ( <STR_LIT> , bases :: read_vl , shapes :: read_vl , none_ops [ <NUM_LIT> ] , PRED_TYPE_none , & p_none_void_ops ) ;"
GCC,riscv,165,"Predict the next statement of this code snippet:
 <s> for ( unsigned int i = <NUM_LIT> ; all_ops [ i ] . index != NUM_VECTOR_TYPES ; i ++ ) if ( type_idx == all_ops [ i ] . index ) return all_ops [ i ] . required_extensions ; for ( unsigned int i = <NUM_LIT> ; b_ops [ i ] . index != NUM_VECTOR_TYPES ; i ++ ) if ( type_idx == b_ops [ i ] . index ) return b_ops [ i ] . required_extensions ;"
GCC,riscv,166,"Predict the next statement of this code snippet:
 <s> tree <STR_LIT> ( vector_type_index type_idx ) const { if ( type_idx >= VECTOR_TYPE_vbool64_t && type_idx <= VECTOR_TYPE_vbool1_t ) return builtin_types [ VECTOR_TYPE_vuint8mf8_t ] . scalar_ptr ; else return builtin_types [ type_idx ] . scalar_ptr ;"
GCC,riscv,167,"Predict the next statement of this code snippet:
 <s> if ( type_idx >= VECTOR_TYPE_vbool64_t && type_idx <= VECTOR_TYPE_vbool1_t ) return builtin_types [ VECTOR_TYPE_vuint8mf8_t ] . scalar_ptr ;"
GCC,riscv,168,"Predict the next statement of this code snippet:
 <s> return get_function_type_index ( type_idx ) == VECTOR_TYPE_INVALID ? NULL_TREE : builtin_types [ get_function_type_index ( type_idx ) ] . scalar ;"
GCC,riscv,169,"Predict the next statement of this code snippet:
 <s> inline tree <STR_LIT> ( vector_type_index type_idx ) const { return get_function_type_index ( type_idx ) == VECTOR_TYPE_INVALID ? NULL_TREE : builtin_types [ get_function_type_index ( type_idx ) ] . scalar ;"
GCC,riscv,170,"Predict the next statement of this code snippet:
 <s> if ( pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu ) return gen_int_mode ( TAIL_UNDISTURBED , Pmode ) ;"
GCC,riscv,171,"Predict the next statement of this code snippet:
 <s> if ( pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu ) return gen_int_mode ( TAIL_UNDISTURBED , Pmode ) ;"
GCC,riscv,172,"Predict the next statement of this code snippet:
 <s> case RVV_BASE_ ## NAME : \ return TYPE ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ;"
GCC,riscv,173,"Predict the next statement of this code snippet:
 <s> return get_function_type_index ( type_idx ) == VECTOR_TYPE_INVALID ? NULL_TREE : builtin_types [ get_function_type_index ( type_idx ) ] . vector ;"
GCC,riscv,174,"Predict the next statement of this code snippet:
 <s> return get_function_type_index ( type_idx ) == VECTOR_TYPE_INVALID ? NULL_TREE : builtin_types [ get_function_type_index ( type_idx ) ] . vector ;"
GCC,riscv,175,"Predict the next statement of this code snippet:
 <s> gimple_folder :: gimple_folder ( const function_instance & instance , tree fndecl , gimple_stmt_iterator * gsi_in , gcall * call_in ) : function_call_info ( gimple_location ( call_in ) , instance , fndecl ) , gsi ( gsi_in ) , call ( call_in ) , lhs ( gimple_call_lhs ( call_in ) ) {"
GCC,riscv,176,"Predict the next statement of this code snippet:
 <s> gimple_folder :: gimple_folder ( const function_instance & instance , tree fndecl , gimple_stmt_iterator * gsi_in , gcall * call_in ) : function_call_info ( gimple_location ( call_in ) , instance , fndecl ) , gsi ( gsi_in ) , call ( call_in ) , lhs ( gimple_call_lhs ( call_in ) ) {"
GCC,riscv,177,"Predict the next statement of this code snippet:
 <s> gimple * gimple_fold_builtin ( unsigned int code , gimple_stmt_iterator * gsi , gcall * stmt ) {"
GCC,riscv,178,"Predict the next statement of this code snippet:
 <s> gimple * gimple_fold_builtin ( unsigned int code , gimple_stmt_iterator * gsi , gcall * stmt ) { registered_function & rfn = * ( * registered_functions ) [ code ] ;"
GCC,riscv,179,"Predict the next statement of this code snippet:
 <s> inline void gt_ggc_mx ( function_instance * ) {"
GCC,riscv,180,"Predict the next statement of this code snippet:
 <s> inline void gt_ggc_mx ( function_instance * ) {"
GCC,riscv,181,"Predict the next statement of this code snippet:
 <s> inline void gt_pch_nx ( function_instance * , gt_pointer_operator , void * ) {"
GCC,riscv,182,"Predict the next statement of this code snippet:
 <s> inline void gt_pch_nx ( function_instance * , gt_pointer_operator , void * ) {"
GCC,riscv,183,"Predict the next statement of this code snippet:
 <s> function_table = new hash_table < registered_function_hasher > ( <NUM_LIT> ) ; function_builder builder ;"
GCC,riscv,184,"Predict the next statement of this code snippet:
 <s> for ( unsigned int type_i = <NUM_LIT> ; type_i < NUM_VECTOR_TYPES ; ++ type_i ) register_vector_type ( ( enum vector_type_index ) type_i ) ; function_table = new hash_table < registered_function_hasher > ( <NUM_LIT> ) ;"
GCC,riscv,185,"Predict the next statement of this code snippet:
 <s> return value -> instance . hash ( ) ;"
GCC,riscv,186,"Predict the next statement of this code snippet:
 <s> return true ;"
GCC,riscv,187,"Predict the next statement of this code snippet:
 <s> return true ;"
GCC,riscv,188,"Predict the next statement of this code snippet:
 <s> rvv_switcher rvv ; if ( ! TARGET_VECTOR ) return ;"
GCC,riscv,189,"Predict the next statement of this code snippet:
 <s> rvv_switcher rvv ; if ( ! TARGET_VECTOR ) return ; register_builtin_types ( ) ; if ( in_lto_p ) handle_pragma_vector ( ) ;"
GCC,riscv,190,"Predict the next statement of this code snippet:
 <s> static void make_type_sizeless ( tree type ) { TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ;"
GCC,riscv,191,"Predict the next statement of this code snippet:
 <s> const char * mangle_builtin_type ( const_tree type ) {"
GCC,riscv,192,"Predict the next statement of this code snippet:
 <s> if ( TYPE_NAME ( type ) && TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL ) type = TREE_TYPE ( TYPE_NAME ( type ) ) ; if ( tree attr = lookup_vector_type_attribute ( type ) ) if ( tree id = TREE_VALUE ( chain_index ( <NUM_LIT> , TREE_VALUE ( attr ) ) ) ) return IDENTIFIER_POINTER ( id ) ;"
GCC,riscv,193,"Predict the next statement of this code snippet:
 <s> return TYPE_MODE ( builtin_types [ mask_type_index ] . vector ) ;"
GCC,riscv,194,"Predict the next statement of this code snippet:
 <s> if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; return flags & ( CP_WRITE_MEMORY | CP_WRITE_CSR ) ;"
GCC,riscv,195,"Predict the next statement of this code snippet:
 <s> unsigned int flags = call_properties ( ) ; if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; return flags & ( CP_WRITE_MEMORY | CP_WRITE_CSR ) ;"
GCC,riscv,196,"Predict the next statement of this code snippet:
 <s> bool function_instance :: reads_global_state_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_READ_FPCR ) return true ;"
GCC,riscv,197,"Predict the next statement of this code snippet:
 <s> bool function_instance :: reads_global_state_p ( ) const { unsigned int flags = call_properties ( ) ;"
GCC,riscv,198,"Predict the next statement of this code snippet:
 <s> builtin_types [ type ] . scalar_ptr = build_pointer_type ( eltype ) ; builtin_types [ type ] . scalar_const_ptr = build_const_pointer ( eltype ) ; if ( ! riscv_v_ext_vector_mode_p ( mode ) ) return ; tree vectype = build_vector_type_for_mode ( eltype , mode ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && TYPE_MODE ( vectype ) == mode && TYPE_MODE_RAW ( vectype ) == mode && TYPE_ALIGN ( vectype ) <= <NUM_LIT> && known_eq ( tree_to_poly_uint64 ( TYPE_SIZE ( vectype ) ) , GET_MODE_BITSIZE ( mode ) ) ) ; vectype = build_distinct_type_copy ( vectype ) ; gcc_assert ( vectype == TYPE_MAIN_VARIANT ( vectype ) ) ; SET_TYPE_STRUCTURAL_EQUALITY ( vectype ) ; TYPE_ARTIFICIAL ( vectype ) = <NUM_LIT> ; TYPE_INDIVISIBLE_P ( vectype ) = <NUM_LIT> ; add_vector_type_attribute ( vectype , vector_types [ type ] . mangled_name ) ; make_type_sizeless ( vectype ) ;"
GCC,riscv,199,"Predict the next statement of this code snippet:
 <s> gcc_assert ( vectype == TYPE_MAIN_VARIANT ( vectype ) ) ; SET_TYPE_STRUCTURAL_EQUALITY ( vectype ) ; TYPE_ARTIFICIAL ( vectype ) = <NUM_LIT> ; TYPE_INDIVISIBLE_P ( vectype ) = <NUM_LIT> ; add_vector_type_attribute ( vectype , vector_types [ type ] . mangled_name ) ; make_type_sizeless ( vectype ) ; abi_vector_types [ type ] = vectype ; lang_hooks . types . register_builtin_type ( vectype , vector_types [ type ] . abi_name ) ;"
GCC,riscv,200,"Predict the next statement of this code snippet:
 <s> static void register_builtin_types ( ) { tree int8_type_node = get_typenode_from_name ( INT8_TYPE ) ; tree uint8_type_node = get_typenode_from_name ( UINT8_TYPE ) ; tree int16_type_node = get_typenode_from_name ( INT16_TYPE ) ;"
GCC,riscv,201,"Predict the next statement of this code snippet:
 <s> ( * group . shape ) -> build ( * this , group ) ;"
GCC,riscv,202,"Predict the next statement of this code snippet:
 <s> tree id = get_identifier ( vector_types [ type ] . name ) ; tree decl = build_decl ( input_location , TYPE_DECL , id , vectype ) ; decl = lang_hooks . decls . pushdecl ( decl ) ;"
GCC,riscv,203,"Predict the next statement of this code snippet:
 <s> error_at ( location , <STR_LIT> <STR_LIT> , argno + <NUM_LIT> , fndecl ) ;"
GCC,riscv,204,"Predict the next statement of this code snippet:
 <s> void function_checker :: report_non_ice ( unsigned int argno ) const { error_at ( location , <STR_LIT> <STR_LIT> , argno + <NUM_LIT> , fndecl ) ;"
GCC,riscv,205,"Predict the next statement of this code snippet:
 <s> void function_checker :: report_out_of_range ( unsigned int argno , HOST_WIDE_INT actual , HOST_WIDE_INT min , HOST_WIDE_INT max ) const { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl , min , max ) ;"
GCC,riscv,206,"Predict the next statement of this code snippet:
 <s> static bool required_extensions_p ( enum rvv_base_type type ) { return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index || type == RVV_BASE_float_vector || type == RVV_BASE_double_trunc_float_vector || type == RVV_BASE_double_trunc_vector || type == RVV_BASE_widen_lmul1_vector || type == RVV_BASE_eew8_interpret || type == RVV_BASE_eew16_interpret || type == RVV_BASE_eew32_interpret || type == RVV_BASE_eew64_interpret || type == RVV_BASE_vlmul_ext_x2 || type == RVV_BASE_vlmul_ext_x4 || type == RVV_BASE_vlmul_ext_x8 || type == RVV_BASE_vlmul_ext_x16 || type == RVV_BASE_vlmul_ext_x32 || type == RVV_BASE_vlmul_ext_x64 ;"
GCC,riscv,207,"Predict the next statement of this code snippet:
 <s> bool function_checker :: require_immediate ( unsigned int argno , HOST_WIDE_INT min , HOST_WIDE_INT max ) const { gcc_assert ( argno < m_nargs ) ; tree arg = m_args [ argno ] ; if ( ! tree_fits_uhwi_p ( arg ) ) { report_non_ice ( argno ) ; return false ;"
GCC,riscv,208,"Predict the next statement of this code snippet:
 <s> bool function_checker :: require_immediate ( unsigned int argno , HOST_WIDE_INT min , HOST_WIDE_INT max ) const { gcc_assert ( argno < m_nargs ) ; tree arg = m_args [ argno ] ; if ( ! tree_fits_uhwi_p ( arg ) ) { report_non_ice ( argno ) ; return false ; }"
GCC,riscv,209,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT actual = tree_to_uhwi ( arg ) ; if ( ! IN_RANGE ( actual , min , max ) ) { report_out_of_range ( argno , actual , min , max ) ; return false ;"
GCC,riscv,210,"Predict the next statement of this code snippet:
 <s> gcc_assert ( argno < m_nargs ) ; tree arg = m_args [ argno ] ; HOST_WIDE_INT actual = tree_to_uhwi ( arg ) ; if ( ! IN_RANGE ( actual , min , max ) ) { report_out_of_range ( argno , actual , min , max ) ; return false ; }"
GCC,riscv,211,"Predict the next statement of this code snippet:
 <s> inline machine_mode function_checker :: ret_mode ( ) const {"
GCC,riscv,212,"Predict the next statement of this code snippet:
 <s> return TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) ) ;"
GCC,riscv,213,"Predict the next statement of this code snippet:
 <s> CONSTEXPR rvv_arg_type_info ( rvv_base_type base_type_in ) : base_type ( base_type_in ) {"
GCC,riscv,214,"Predict the next statement of this code snippet:
 <s> CONSTEXPR rvv_arg_type_info ( rvv_base_type base_type_in ) : base_type ( base_type_in ) {"
GCC,riscv,215,"Predict the next statement of this code snippet:
 <s> memcpy ( m_old_have_regs_of_mode , have_regs_of_mode , sizeof ( have_regs_of_mode ) ) ;"
GCC,riscv,216,"Predict the next statement of this code snippet:
 <s> if ( type == error_mark_node ) return NULL_TREE ;"
GCC,riscv,217,"Predict the next statement of this code snippet:
 <s> else add_vundef_operand ( mask_mode ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx op2 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; if ( ! insn_operand_matches ( icode , opno + <NUM_LIT> , op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! insn_operand_matches ( icode , opno + <NUM_LIT> , op2 ) ) { if ( VECTOR_MODE_P ( GET_MODE ( op2 ) ) ) op2 = force_reg ( mode , op2 ) ; else op2 = force_reg ( GET_MODE_INNER ( mode ) , op2 ) ; } rtx comparison = gen_rtx_fmt_ee ( rcode , mask_mode , op1 , op2 ) ;"
GCC,riscv,218,"Predict the next statement of this code snippet:
 <s> int arg_offset = <NUM_LIT> ; add_mem_operand ( mode , use_real_mask_p ( pred ) ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,riscv,219,"Predict the next statement of this code snippet:
 <s> int arg_offset = <NUM_LIT> ; if ( base -> use_mask_predication_p ( ) ) { if ( use_real_mask_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_all_one_mask_operand ( mask_mode ( ) ) ; } if ( ! function_returns_void_p ( ) && base -> has_merge_operand_p ( ) ) { if ( use_real_merge_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_vundef_operand ( mode ) ; } for ( int argno = arg_offset ; argno < call_expr_nargs ( exp ) ; argno ++ ) add_input_operand ( argno ) ; if ( base -> apply_tail_policy_p ( ) ) add_input_operand ( Pmode , get_tail_policy_for_pred ( pred ) ) ;"
GCC,riscv,220,"Predict the next statement of this code snippet:
 <s> } for ( int argno = arg_offset ; argno < call_expr_nargs ( exp ) ; argno ++ ) add_input_operand ( argno ) ; if ( base -> apply_tail_policy_p ( ) ) add_input_operand ( Pmode , get_tail_policy_for_pred ( pred ) ) ; if ( base -> apply_mask_policy_p ( ) ) add_input_operand ( Pmode , get_mask_policy_for_pred ( pred ) ) ;"
GCC,riscv,221,"Predict the next statement of this code snippet:
 <s> return true ;"
GCC,riscv,222,"Predict the next statement of this code snippet:
 <s> return pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu ;"
GCC,riscv,223,"Predict the next statement of this code snippet:
 <s> rtx vd = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx vs1 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx vs2 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; if ( VECTOR_MODE_P ( GET_MODE ( vs1 ) ) ) { if ( ! vd_accum_p ) add_input_operand ( mode , vd ) ; add_input_operand ( mode , vs1 ) ; add_input_operand ( mode , vs2 ) ; if ( vd_accum_p ) add_input_operand ( mode , vd ) ; add_input_operand ( mode , vd ) ; } else { add_input_operand ( GET_MODE_INNER ( mode ) , vs1 ) ; if ( vd_accum_p ) { add_input_operand ( mode , vs2 ) ; add_input_operand ( mode , vd ) ; } else { add_input_operand ( mode , vd ) ; add_input_operand ( mode , vs2 ) ; } add_input_operand ( mode , vd ) ;"
GCC,riscv,224,"Predict the next statement of this code snippet:
 <s> else add_all_one_mask_operand ( mask_mode ( ) ) ; rtx vd = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx vs1 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx vs2 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; if ( VECTOR_MODE_P ( GET_MODE ( vs1 ) ) ) { if ( ! vd_accum_p ) add_input_operand ( mode , vd ) ; add_input_operand ( mode , vs1 ) ; add_input_operand ( mode , vs2 ) ; if ( vd_accum_p ) add_input_operand ( mode , vd ) ;"
GCC,riscv,225,"Predict the next statement of this code snippet:
 <s> add_input_operand ( Pmode , get_mask_policy_for_pred ( pred ) ) ; add_input_operand ( Pmode , get_avl_type_rtx ( avl_type :: NONVLMAX ) ) ; return generate_insn ( icode ) ;"
GCC,riscv,226,"Predict the next statement of this code snippet:
 <s> return TYPE_MODE ( builtin_types [ type . index ] . vector ) ;"
GCC,riscv,227,"Predict the next statement of this code snippet:
 <s> inline machine_mode function_expander :: vector_mode ( void ) const { return TYPE_MODE ( builtin_types [ type . index ] . vector ) ;"
GCC,riscv,228,"Predict the next statement of this code snippet:
 <s> function_builder :: ~ function_builder ( ) { obstack_free ( & m_string_obstack , NULL ) ;"
GCC,riscv,229,"Predict the next statement of this code snippet:
 <s> <STR_LIT> rvv_switcher ( ) {"
GCC,riscv,230,"Predict the next statement of this code snippet:
 <s> gcc_assert ( ! JUMP_P ( rinsn ) ) ; add_reg_note ( rinsn , REG_LABEL_OPERAND , label_ref_label ( x ) ) ; if ( LABEL_P ( label_ref_label ( x ) ) ) LABEL_NUSES ( label_ref_label ( x ) ) ++ ; return ; } for ( i = GET_RTX_LENGTH ( code ) - <NUM_LIT> , fmt = GET_RTX_FORMAT ( code ) ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'e' ) add_label_notes ( XEXP ( x , i ) , rinsn ) ; else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) add_label_notes ( XVECEXP ( x , i , j ) , rinsn ) ; }"
GCC,riscv,231,"Predict the next statement of this code snippet:
 <s> if ( bitmap_empty_p ( bitdata ) ) return false ; const auto & block_info = vector_block_infos [ cfg_bb -> index ] ; if ( ! block_info . local_dem . demand_p ( DEMAND_AVL ) ) return true ; avl_info avl = block_info . local_dem . get_avl_info ( ) ; unsigned int bb_index ; sbitmap_iterator sbi ; EXECUTE_IF_SET_IN_BITMAP ( bitdata , <NUM_LIT> , bb_index , sbi ) { if ( vector_exprs [ bb_index ] -> get_avl_info ( ) != avl ) return false ; } return true ;"
GCC,riscv,232,"Predict the next statement of this code snippet:
 <s> if ( bitmap_empty_p ( bitdata ) ) return false ; int ratio = - <NUM_LIT> ; unsigned int bb_index ; sbitmap_iterator sbi ; EXECUTE_IF_SET_IN_BITMAP ( bitdata , <NUM_LIT> , bb_index , sbi ) {"
GCC,riscv,233,"Predict the next statement of this code snippet:
 <s> } } if ( vsetvl_insn_p ( insn -> rtl ( ) ) ) { rtx dest = get_vl ( insn -> rtl ( ) ) ; for ( insn_info * i = insn -> prev_nondebug_insn ( ) ; real_insn_and_same_bb_p ( i , bb ) ; i = i -> prev_nondebug_insn ( ) ) { if ( find_access ( i -> uses ( ) , REGNO ( dest ) ) ) return false ; if ( find_access ( i -> defs ( ) , REGNO ( dest ) ) ) return false ; } }"
GCC,riscv,234,"Predict the next statement of this code snippet:
 <s> for ( const set_info * set : sets ) if ( set -> bb ( ) -> index ( ) == bb -> index ( ) ) return true ;"
GCC,riscv,235,"Predict the next statement of this code snippet:
 <s> static bool any_set_in_bb_p ( hash_set < set_info * > sets , const bb_info * bb ) {"
GCC,riscv,236,"Predict the next statement of this code snippet:
 <s> static bool available_occurrence_p ( const bb_info * bb , const vector_insn_info dem ) { insn_info * insn = dem . get_insn ( ) ; if ( dem . has_avl_reg ( ) ) { if ( ! vlmax_avl_p ( dem . get_avl ( ) ) ) { rtx dest = NULL_RTX ; if ( vsetvl_insn_p ( insn -> rtl ( ) ) ) dest = get_vl ( insn -> rtl ( ) ) ; for ( const insn_info * i = insn ; real_insn_and_same_bb_p ( i , bb ) ; i = i -> next_nondebug_insn ( ) ) { if ( read_vl_insn_p ( i -> rtl ( ) ) ) continue ;"
GCC,riscv,237,"Predict the next statement of this code snippet:
 <s> if ( read_vl_insn_p ( i -> rtl ( ) ) ) continue ; if ( find_access ( i -> defs ( ) , REGNO ( dem . get_avl ( ) ) ) ) return false ; if ( dest && find_access ( i -> defs ( ) , REGNO ( dest ) ) ) return false ;"
GCC,riscv,238,"Predict the next statement of this code snippet:
 <s> bool vector_insn_info :: available_p ( const vector_insn_info & other ) const {"
GCC,riscv,239,"Predict the next statement of this code snippet:
 <s> avl_info ( ) : m_value ( NULL_RTX ) , m_source ( nullptr ) {"
GCC,riscv,240,"Predict the next statement of this code snippet:
 <s> avl_info ( ) : m_value ( NULL_RTX ) , m_source ( nullptr ) {"
GCC,riscv,241,"Predict the next statement of this code snippet:
 <s> if ( e -> src -> index == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> index ) continue ; if ( vsetvl_insn_p ( prop . get_insn ( ) -> rtl ( ) ) && propagate_avl_across_demands_p ( prop , block_info . reaching_out ) ) continue ; if ( block_info . reaching_out . unknown_p ( ) ) continue ; else if ( block_info . reaching_out . hard_empty_p ( ) ) continue ; else if ( block_info . reaching_out . empty_p ( ) ) { enum fusion_type type = get_backward_fusion_type ( crtl -> ssa -> bb ( e -> src ) , prop ) ; if ( type == INVALID_FUSION ) continue ; block_info . reaching_out = prop ; block_info . reaching_out . set_dirty ( type ) ; if ( prop . has_avl_reg ( ) && ! vlmax_avl_p ( prop . get_avl ( ) ) ) { hash_set < set_info * > sets = get_all_sets ( prop . get_avl_source ( ) , true , true , true ) ; set_info * set = get_same_bb_set ( sets , e -> src ) ; if ( set ) block_info . reaching_out . set_avl_info ( avl_info ( prop . get_avl ( ) , set ) ) ; } block_info . local_dem = block_info . reaching_out ; block_info . probability = curr_block_info . probability ; changed_p = true ; } else if ( block_info . reaching_out . dirty_p ( ) ) { vector_insn_info new_info ; if ( block_info . reaching_out . compatible_p ( prop ) ) { if ( block_info . reaching_out . available_p ( prop ) ) continue ; new_info = block_info . reaching_out . merge ( prop , GLOBAL_MERGE ) ; new_info . set_dirty ( block_info . reaching_out . dirty_with_killed_avl_p ( ) ) ; block_info . probability += curr_block_info . probability ; } else { if ( curr_block_info . probability > block_info . probability ) { enum fusion_type type = get_backward_fusion_type ( crtl -> ssa -> bb ( e -> src ) , prop ) ; if ( type == INVALID_FUSION ) continue ; new_info = prop ; new_info . set_dirty ( type ) ; block_info . probability = curr_block_info . probability ; } else continue ; } if ( propagate_avl_across_demands_p ( prop , block_info . reaching_out ) ) { rtx reg = new_info . get_avl_reg_rtx ( ) ; if ( find_reg_killed_by ( crtl -> ssa -> bb ( e -> src ) , reg ) ) new_info . set_dirty ( true ) ; }"
GCC,riscv,242,"Predict the next statement of this code snippet:
 <s> if ( prop . has_avl_reg ( ) && ! vlmax_avl_p ( prop . get_avl ( ) ) ) { hash_set < set_info * > sets = get_all_sets ( prop . get_avl_source ( ) , true , true , true ) ; set_info * set = get_same_bb_set ( sets , e -> src ) ; if ( set ) block_info . reaching_out . set_avl_info ( avl_info ( prop . get_avl ( ) , set ) ) ; } block_info . local_dem = block_info . reaching_out ; block_info . probability = curr_block_info . probability ; changed_p = true ; } else if ( block_info . reaching_out . dirty_p ( ) ) { vector_insn_info new_info ; if ( block_info . reaching_out . compatible_p ( prop ) ) { if ( block_info . reaching_out . available_p ( prop ) ) continue ; new_info = block_info . reaching_out . merge ( prop , GLOBAL_MERGE ) ; new_info . set_dirty ( block_info . reaching_out . dirty_with_killed_avl_p ( ) ) ; block_info . probability += curr_block_info . probability ; } else { if ( curr_block_info . probability > block_info . probability ) { enum fusion_type type = get_backward_fusion_type ( crtl -> ssa -> bb ( e -> src ) , prop ) ; if ( type == INVALID_FUSION ) continue ; new_info = prop ; new_info . set_dirty ( type ) ; block_info . probability = curr_block_info . probability ; } else continue ; } if ( propagate_avl_across_demands_p ( prop , block_info . reaching_out ) ) { rtx reg = new_info . get_avl_reg_rtx ( ) ; if ( find_reg_killed_by ( crtl -> ssa -> bb ( e -> src ) , reg ) ) new_info . set_dirty ( true ) ; } block_info . local_dem = new_info ; block_info . reaching_out = new_info ; changed_p = true ; } else { gcc_assert ( block_info . reaching_out . valid_p ( ) ) ;"
GCC,riscv,243,"Predict the next statement of this code snippet:
 <s> else { if ( support_relaxed_compatible_p ( block_info . reaching_out , block_info . local_dem ) ) return true ; return false ; } } else { gcc_assert ( block_info . reaching_out . unknown_p ( ) ) ; return false ;"
GCC,riscv,244,"Predict the next statement of this code snippet:
 <s> static bool before_p ( const insn_info * insn1 , const insn_info * insn2 ) { return insn1 -> compare_with ( insn2 ) < <NUM_LIT> ;"
GCC,riscv,245,"Predict the next statement of this code snippet:
 <s> static vlmul_type calculate_vlmul ( unsigned int sew , unsigned int ratio ) { for ( const vlmul_type vlmul : ALL_LMUL ) if ( calculate_ratio ( sew , vlmul ) == ratio ) return vlmul ; return LMUL_RESERVED ;"
GCC,riscv,246,"Predict the next statement of this code snippet:
 <s> static vlmul_type calculate_vlmul ( unsigned int sew , unsigned int ratio ) {"
GCC,riscv,247,"Predict the next statement of this code snippet:
 <s> if ( ! m_vector_manager -> all_same_ratio_p ( m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ) return false ; if ( ! m_vector_manager -> all_same_avl_p ( cfg_bb , m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ) return false ; size_t expr_id = bitmap_first_set_bit ( m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ; if ( ! m_vector_manager -> vector_exprs [ expr_id ] -> same_vlmax_p ( info ) ) return false ; if ( ! m_vector_manager -> vector_exprs [ expr_id ] -> compatible_avl_p ( info ) ) return false ; edge e ; edge_iterator ei ; bool all_valid_p = true ; FOR_EACH_EDGE ( e , ei , cfg_bb -> preds ) { if ( bitmap_empty_p ( m_vector_manager -> vector_avout [ e -> src -> index ] ) ) { all_valid_p = false ; break ; }"
GCC,riscv,248,"Predict the next statement of this code snippet:
 <s> bool pass_vsetvl :: can_refine_vsetvl_p ( const basic_block cfg_bb , const vector_insn_info & info ) const { if ( ! m_vector_manager -> all_same_ratio_p ( m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ) return false ; if ( ! m_vector_manager -> all_same_avl_p ( cfg_bb , m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ) return false ; size_t expr_id = bitmap_first_set_bit ( m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ; if ( ! m_vector_manager -> vector_exprs [ expr_id ] -> same_vlmax_p ( info ) ) return false ; if ( ! m_vector_manager -> vector_exprs [ expr_id ] -> compatible_avl_p ( info ) ) return false ; edge e ; edge_iterator ei ; bool all_valid_p = true ;"
GCC,riscv,249,"Predict the next statement of this code snippet:
 <s> } insn_change_watermark watermark ; validate_change ( rinsn , & PATTERN ( rinsn ) , new_pat , true ) ; if ( ! recog ( attempt , change ) || ! change_is_worthwhile ( change , false ) ) return false ; remove_reg_equal_equiv_notes ( rinsn ) ; confirm_change_group ( ) ;"
GCC,riscv,250,"Predict the next statement of this code snippet:
 <s> rtx_insn * rinsn ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { rinsn = insn -> rtl ( ) ; gcc_assert ( vsetvl_insn_p ( rinsn ) && <STR_LIT> ) ; } else { gcc_assert ( has_vtype_op ( insn -> rtl ( ) ) ) ;"
GCC,riscv,251,"Predict the next statement of this code snippet:
 <s> const auto & prop = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . reaching_out ; if ( ! prop . valid_or_dirty_p ( ) ) continue ; if ( hard_empty_block_p ( bb , prop ) ) { m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . local_dem = vector_insn_info :: get_hard_empty ( ) ; m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . reaching_out = vector_insn_info :: get_hard_empty ( ) ; changed_p = true ; continue ; } } return changed_p ;"
GCC,riscv,252,"Predict the next statement of this code snippet:
 <s> continue ; } if ( ! has_vl_op ( rinsn ) || ! REG_P ( get_vl ( rinsn ) ) ) continue ; rtx avl = get_vl ( rinsn ) ; if ( count_occurrences ( PATTERN ( rinsn ) , avl , <NUM_LIT> ) == <NUM_LIT> ) { auto attempt = crtl -> ssa -> new_change_attempt ( ) ; insn_change change ( insn ) ; access_array_builder uses_builder ( attempt ) ; uses_builder . reserve ( insn -> num_uses ( ) - <NUM_LIT> ) ; for ( use_info * use : insn -> uses ( ) ) if ( use != find_access ( insn -> uses ( ) , REGNO ( avl ) ) ) uses_builder . quick_push ( use ) ; use_array new_uses = use_array ( uses_builder . finish ( ) ) ; change . new_uses = new_uses ; change . move_range = insn -> ebb ( ) -> insn_range ( ) ;"
GCC,riscv,253,"Predict the next statement of this code snippet:
 <s> void pass_vsetvl :: cleanup_insns ( void ) const { for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { for ( insn_info * insn : bb -> real_nondebug_insns ( ) ) { rtx_insn * rinsn = insn -> rtl ( ) ; if ( vlmax_avl_insn_p ( rinsn ) ) { eliminate_insn ( rinsn ) ; continue ; } if ( ! has_vl_op ( rinsn ) || ! REG_P ( get_vl ( rinsn ) ) ) continue ; rtx avl = get_vl ( rinsn ) ; if ( count_occurrences ( PATTERN ( rinsn ) , avl , <NUM_LIT> ) == <NUM_LIT> ) { auto attempt = crtl -> ssa -> new_change_attempt ( ) ; insn_change change ( insn ) ; access_array_builder uses_builder ( attempt ) ; uses_builder . reserve ( insn -> num_uses ( ) - <NUM_LIT> ) ; for ( use_info * use : insn -> uses ( ) ) if ( use != find_access ( insn -> uses ( ) , REGNO ( avl ) ) ) uses_builder . quick_push ( use ) ; use_array new_uses = use_array ( uses_builder . finish ( ) ) ; change . new_uses = new_uses ; change . move_range = insn -> ebb ( ) -> insn_range ( ) ;"
GCC,riscv,254,"Predict the next statement of this code snippet:
 <s> basic_block cfg_bb ; FOR_EACH_BB_FN ( cfg_bb , cfun ) { auto & info = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . reaching_out ; gcc_assert ( m_vector_manager -> expr_set_num ( m_vector_manager -> vector_del [ cfg_bb -> index ] ) <= <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < m_vector_manager -> vector_exprs . length ( ) ; i ++ ) { if ( bitmap_bit_p ( m_vector_manager -> vector_del [ cfg_bb -> index ] , i ) ) { if ( info . dirty_p ( ) ) info . set_unknown ( ) ; else { const auto dem = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . local_dem ; gcc_assert ( dem == * m_vector_manager -> vector_exprs [ i ] ) ; insn_info * insn = dem . get_insn ( ) ; gcc_assert ( insn && insn -> rtl ( ) ) ; rtx_insn * rinsn ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { m_vector_manager -> to_delete_vsetvls . add ( insn -> rtl ( ) ) ; continue ; } gcc_assert ( has_vtype_op ( insn -> rtl ( ) ) ) ; rinsn = PREV_INSN ( insn -> rtl ( ) ) ; gcc_assert ( vector_config_insn_p ( PREV_INSN ( insn -> rtl ( ) ) ) ) ; eliminate_insn ( rinsn ) ; } } }"
GCC,riscv,255,"Predict the next statement of this code snippet:
 <s> gcc_assert ( dem == * m_vector_manager -> vector_exprs [ i ] ) ; insn_info * insn = dem . get_insn ( ) ; gcc_assert ( insn && insn -> rtl ( ) ) ; rtx_insn * rinsn ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { m_vector_manager -> to_delete_vsetvls . add ( insn -> rtl ( ) ) ; continue ; } gcc_assert ( has_vtype_op ( insn -> rtl ( ) ) ) ; rinsn = PREV_INSN ( insn -> rtl ( ) ) ; gcc_assert ( vector_config_insn_p ( PREV_INSN ( insn -> rtl ( ) ) ) ) ; eliminate_insn ( rinsn ) ; } }"
GCC,riscv,256,"Predict the next statement of this code snippet:
 <s> } } for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { basic_block cfg_bb = bb -> cfg_bb ( ) ; const auto reaching_out = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . reaching_out ; if ( ! reaching_out . dirty_p ( ) ) continue ; if ( reaching_out . dirty_with_killed_avl_p ( ) ) { if ( ! has_vsetvl_killed_avl_p ( bb , reaching_out ) ) continue ; unsigned int bb_index ; sbitmap_iterator sbi ; sbitmap avin = m_vector_manager -> vector_avin [ cfg_bb -> index ] ; bool available_p = false ; EXECUTE_IF_SET_IN_BITMAP ( avin , <NUM_LIT> , bb_index , sbi ) { if ( m_vector_manager -> vector_exprs [ bb_index ] -> available_p ( reaching_out ) ) { available_p = true ; break ; } } if ( available_p ) continue ; } rtx new_pat ; if ( ! reaching_out . demand_p ( DEMAND_AVL ) ) { vl_vtype_info new_info = reaching_out ; new_info . set_avl_info ( avl_info ( const0_rtx , nullptr ) ) ; new_pat = gen_vsetvl_pat ( VSETVL_DISCARD_RESULT , new_info , NULL_RTX ) ; } else if ( can_refine_vsetvl_p ( cfg_bb , reaching_out ) ) new_pat = gen_vsetvl_pat ( VSETVL_VTYPE_CHANGE_ONLY , reaching_out , NULL_RTX ) ; else if ( vlmax_avl_p ( reaching_out . get_avl ( ) ) ) new_pat = gen_vsetvl_pat ( VSETVL_NORMAL , reaching_out , reaching_out . get_avl_reg_rtx ( ) ) ; else new_pat = gen_vsetvl_pat ( VSETVL_DISCARD_RESULT , reaching_out , NULL_RTX ) ; start_sequence ( ) ; emit_insn ( new_pat ) ; rtx_insn * rinsn = get_insns ( ) ; end_sequence ( ) ; insert_insn_end_basic_block ( rinsn , cfg_bb ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , INSN_UID ( rinsn ) , cfg_bb -> index ) ; print_rtl_single ( dump_file , rinsn ) ; } } return need_commit ;"
GCC,riscv,257,"Predict the next statement of this code snippet:
 <s> if ( vlmul2 == LMUL_1 || vlmul2 == LMUL_2 || vlmul2 == LMUL_4 || vlmul2 == LMUL_8 ) return <NUM_LIT> ; else return - <NUM_LIT> ; case LMUL_F4 : if ( vlmul2 == LMUL_F2 || vlmul2 == LMUL_1 || vlmul2 == LMUL_2 || vlmul2 == LMUL_4 || vlmul2 == LMUL_8 ) return <NUM_LIT> ; else return - <NUM_LIT> ; case LMUL_F8 : return <NUM_LIT> ;"
GCC,riscv,258,"Predict the next statement of this code snippet:
 <s> gcc_assert ( valid_or_dirty_p ( ) && <STR_LIT> ) ; gcc_assert ( ! unknown_p ( ) && <STR_LIT> ) ; gcc_assert ( demand_p ( DEMAND_AVL ) && <STR_LIT> ) ; if ( ! demand_p ( DEMAND_AVL ) ) return true ;"
GCC,riscv,259,"Predict the next statement of this code snippet:
 <s> if ( ! demand_p ( DEMAND_AVL ) ) return true ; if ( demand_p ( DEMAND_NONZERO_AVL ) && other . has_non_zero_avl ( ) ) return true ;"
GCC,riscv,260,"Predict the next statement of this code snippet:
 <s> bool vector_insn_info :: compatible_p ( const vl_vtype_info & curr_info ) const { gcc_assert ( ! uninit_p ( ) && <STR_LIT> ) ; if ( empty_p ( ) ) return false ; if ( unknown_p ( ) ) return false ; if ( ! demand_p ( DEMAND_AVL ) ) if ( m_sew == curr_info . get_sew ( ) ) return true ; return compatible_avl_p ( curr_info ) && compatible_vtype_p ( curr_info ) ;"
GCC,riscv,261,"Predict the next statement of this code snippet:
 <s> if ( ! demand_p ( DEMAND_AVL ) ) if ( m_sew == curr_info . get_sew ( ) ) return true ; return compatible_avl_p ( curr_info ) && compatible_vtype_p ( curr_info ) ;"
GCC,riscv,262,"Predict the next statement of this code snippet:
 <s> if ( demand_p ( DEMAND_LMUL ) && m_vlmul != other . get_vlmul ( ) ) return false ; if ( demand_p ( DEMAND_RATIO ) && m_ratio != other . get_ratio ( ) ) return false ; if ( demand_p ( DEMAND_TAIL_POLICY ) && m_ta != other . get_ta ( ) ) return false ; if ( demand_p ( DEMAND_MASK_POLICY ) && m_ma != other . get_ma ( ) ) return false ; return true ;"
GCC,riscv,263,"Predict the next statement of this code snippet:
 <s> auto & info = m_vector_manager -> vector_insn_infos [ insn -> uid ( ) ] ; if ( info . uninit_p ( ) ) info = change ; else if ( info . unknown_p ( ) ) change = info ; else { gcc_assert ( info . valid_p ( ) && <STR_LIT> ) ; if ( change . valid_p ( ) ) { if ( ! ( propagate_avl_across_demands_p ( change , info ) && ! reg_available_p ( insn , change ) ) && change . compatible_p ( info ) ) { info = change . merge ( info ) ; if ( vsetvl_insn_p ( insn -> rtl ( ) ) ) change_vsetvl_insn ( insn , info ) ;"
GCC,riscv,264,"Predict the next statement of this code snippet:
 <s> if ( ! optimize ) return ; edge e ; edge_iterator ei ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { basic_block cfg_bb = bb -> cfg_bb ( ) ; auto & curr_prob = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . probability ; if ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) == cfg_bb ) curr_prob = profile_probability :: always ( ) ; if ( EXIT_BLOCK_PTR_FOR_FN ( cfun ) == cfg_bb ) continue ; gcc_assert ( curr_prob . initialized_p ( ) ) ; FOR_EACH_EDGE ( e , ei , cfg_bb -> succs ) { auto & new_prob = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . probability ;"
GCC,riscv,265,"Predict the next statement of this code snippet:
 <s> if ( ! optimize ) return ; edge e ; edge_iterator ei ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { basic_block cfg_bb = bb -> cfg_bb ( ) ; auto & curr_prob = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . probability ;"
GCC,riscv,266,"Predict the next statement of this code snippet:
 <s> vector_antic = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_transp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_comp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_avin = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_avout = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_kill = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; bitmap_vector_ones ( vector_transp , last_basic_block_for_fn ( cfun ) ) ;"
GCC,riscv,267,"Predict the next statement of this code snippet:
 <s> void vector_infos_manager :: create_bitmap_vectors ( void ) { vector_antic = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_transp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_comp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_avin = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_avout = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_kill = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; bitmap_vector_ones ( vector_transp , last_basic_block_for_fn ( cfun ) ) ;"
GCC,riscv,268,"Predict the next statement of this code snippet:
 <s> void vector_infos_manager :: create_expr ( vector_insn_info & info ) {"
GCC,riscv,269,"Predict the next statement of this code snippet:
 <s> info -> dump ( stderr ) ;"
GCC,riscv,270,"Predict the next statement of this code snippet:
 <s> DEBUG_FUNCTION void debug ( const vector_infos_manager * info ) {"
GCC,riscv,271,"Predict the next statement of this code snippet:
 <s> m_demands [ type ] = true ;"
GCC,riscv,272,"Predict the next statement of this code snippet:
 <s> } if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) if ( m_vector_manager -> vector_block_infos [ bb -> index ( ) ] . reaching_out . dirty_p ( ) ) fprintf ( dump_file , <STR_LIT> , bb -> index ( ) ) ; fprintf ( dump_file , <STR_LIT> ) ; }"
GCC,riscv,273,"Predict the next statement of this code snippet:
 <s> bool demand_p ( enum demand_type type ) const {"
GCC,riscv,274,"Predict the next statement of this code snippet:
 <s> return info1 . get_vlmul ( ) != info2 . get_vlmul ( ) ;"
GCC,riscv,275,"Predict the next statement of this code snippet:
 <s> return info1 . get_ma ( ) != info2 . get_ma ( ) ;"
GCC,riscv,276,"Predict the next statement of this code snippet:
 <s> static bool different_ratio_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) {"
GCC,riscv,277,"Predict the next statement of this code snippet:
 <s> return info1 . get_sew ( ) != info2 . get_sew ( ) ;"
GCC,riscv,278,"Predict the next statement of this code snippet:
 <s> static bool different_tail_policy_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return info1 . get_ta ( ) != info2 . get_ta ( ) ;"
GCC,riscv,279,"Predict the next statement of this code snippet:
 <s> return m_state == DIRTY || m_state == DIRTY_WITH_KILLED_AVL ;"
GCC,riscv,280,"Predict the next statement of this code snippet:
 <s> return m_state == DIRTY || m_state == DIRTY_WITH_KILLED_AVL ;"
GCC,riscv,281,"Predict the next statement of this code snippet:
 <s> delete crtl -> ssa ; crtl -> ssa = nullptr ; } m_vector_manager -> release ( ) ; delete m_vector_manager ; m_vector_manager = nullptr ;"
GCC,riscv,282,"Predict the next statement of this code snippet:
 <s> return ( ( pair . match_cond_p ( info1 . get_demands ( ) , info2 . get_demands ( ) ) && incompatible_p ( info1 , info2 ) ) || ( pair . match_cond_p ( info2 . get_demands ( ) , info1 . get_demands ( ) ) && incompatible_p ( info2 , info1 ) ) ) ;"
GCC,riscv,283,"Predict the next statement of this code snippet:
 <s> bool dual_incompatible_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) const { return ( ( pair . match_cond_p ( info1 . get_demands ( ) , info2 . get_demands ( ) ) && incompatible_p ( info1 , info2 ) ) || ( pair . match_cond_p ( info2 . get_demands ( ) , info1 . get_demands ( ) ) && incompatible_p ( info2 , info1 ) ) ) ;"
GCC,riscv,284,"Predict the next statement of this code snippet:
 <s> if ( vector_kill == nullptr ) fprintf ( file , <STR_LIT> ) ; else dump_bitmap_file ( file , vector_kill [ cfg_bb -> index ] ) ; } fprintf ( file , <STR_LIT> ) ; FOR_ALL_BB_FN ( cfg_bb , cfun ) { fprintf ( file , <STR_LIT> , cfg_bb -> index ) ; fprintf ( file , <STR_LIT> ) ; if ( vector_avin == nullptr ) fprintf ( file , <STR_LIT> ) ; else dump_bitmap_file ( file , vector_avin [ cfg_bb -> index ] ) ; fprintf ( file , <STR_LIT> ) ; if ( vector_avout == nullptr ) fprintf ( file , <STR_LIT> ) ; else dump_bitmap_file ( file , vector_avout [ cfg_bb -> index ] ) ; fprintf ( file , <STR_LIT> ) ; if ( vector_del == nullptr ) fprintf ( file , <STR_LIT> ) ; else dump_bitmap_file ( file , vector_del [ cfg_bb -> index ] ) ; } fprintf ( file , <STR_LIT> ) ;"
GCC,riscv,285,"Predict the next statement of this code snippet:
 <s> fprintf ( dump_file , <STR_LIT> , INSN_UID ( rinsn ) ) ; print_rtl_single ( dump_file , rinsn ) ; }"
GCC,riscv,286,"Predict the next statement of this code snippet:
 <s> auto & block_info = m_vector_manager -> vector_block_infos [ bb -> index ( ) ] ; if ( block_info . local_dem . empty_p ( ) ) return ; vector_insn_info curr_info ; for ( insn_info * insn : bb -> real_nondebug_insns ( ) ) { const vector_insn_info prev_info = curr_info ; enum vsetvl_type type = NUM_VSETVL_TYPE ; transfer_before ( curr_info , insn ) ; if ( has_vtype_op ( insn -> rtl ( ) ) ) { if ( static_cast < const vl_vtype_info & > ( prev_info ) != static_cast < const vl_vtype_info & > ( curr_info ) ) { const auto require = m_vector_manager -> vector_insn_infos [ insn -> uid ( ) ] ; if ( ! require . compatible_p ( static_cast < const vl_vtype_info & > ( prev_info ) ) ) type = insert_vsetvl ( EMIT_BEFORE , insn -> rtl ( ) , require , prev_info ) ; } } if ( type == VSETVL_VTYPE_CHANGE_ONLY ) { curr_info . set_avl_info ( prev_info . get_avl_info ( ) ) ;"
GCC,riscv,287,"Predict the next statement of this code snippet:
 <s> if ( emit_type == EMIT_DIRECT ) emit_insn ( pat ) ; else if ( emit_type == EMIT_BEFORE ) emit_insn_before ( pat , rinsn ) ; else emit_insn_after ( pat , rinsn ) ;"
GCC,riscv,288,"Predict the next statement of this code snippet:
 <s> fprintf ( dump_file , <STR_LIT> ) ; print_rtl_single ( dump_file , pat ) ; } if ( emit_type == EMIT_DIRECT ) emit_insn ( pat ) ; else if ( emit_type == EMIT_BEFORE ) emit_insn_before ( pat , rinsn ) ; else emit_insn_after ( pat , rinsn ) ;"
GCC,riscv,289,"Predict the next statement of this code snippet:
 <s> bool empty_p ( ) const { return m_state == EMPTY || m_state == HARD_EMPTY ;"
GCC,riscv,290,"Predict the next statement of this code snippet:
 <s> if ( ! has_vector_insn ( cfun ) ) return <NUM_LIT> ; init ( ) ; if ( ! optimize ) simple_vsetvl ( ) ; else lazy_vsetvl ( ) ; done ( ) ;"
GCC,riscv,291,"Predict the next statement of this code snippet:
 <s> size_t count = <NUM_LIT> ;"
GCC,riscv,292,"Predict the next statement of this code snippet:
 <s> if ( ! set -> insn ( ) -> is_phi ( ) ) return nullptr ; hash_set < set_info * > sets = get_all_sets ( set , true , false , true ) ; insn_info * first_insn = ( * sets . begin ( ) ) -> insn ( ) ;"
GCC,riscv,293,"Predict the next statement of this code snippet:
 <s> for ( insn_info * insn : bb -> reverse_real_nondebug_insns ( ) ) if ( find_access ( insn -> defs ( ) , REGNO ( x ) ) ) return insn ; return nullptr ;"
GCC,riscv,294,"Predict the next statement of this code snippet:
 <s> static insn_info * find_reg_killed_by ( const bb_info * bb , rtx x ) { if ( ! x || vlmax_avl_p ( x ) || ! REG_P ( x ) ) return nullptr ; for ( insn_info * insn : bb -> reverse_real_nondebug_insns ( ) ) if ( find_access ( insn -> defs ( ) , REGNO ( x ) ) ) return insn ;"
GCC,riscv,295,"Predict the next statement of this code snippet:
 <s> static unsigned first_ratio ( const vector_insn_info & info1 , const vector_insn_info & ) { return info1 . get_ratio ( ) ;"
GCC,riscv,296,"Predict the next statement of this code snippet:
 <s> return info1 . get_vlmul ( ) ;"
GCC,riscv,297,"Predict the next statement of this code snippet:
 <s> edge_iterator ei ; FOR_EACH_EDGE ( e , ei , cfg_bb -> succs ) { auto & local_dem = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . local_dem ; auto & reaching_out = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . reaching_out ; if ( e -> dest -> index == cfg_bb -> index ) continue ; if ( e -> flags & EDGE_COMPLEX ) continue ; if ( e -> dest -> index == EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> index ) continue ; if ( ! local_dem . valid_or_dirty_p ( ) ) continue ; if ( local_dem . available_p ( prop ) ) continue ; if ( ! local_dem . compatible_p ( prop ) ) continue ; if ( propagate_avl_across_demands_p ( prop , local_dem ) ) continue ; vector_insn_info new_info = local_dem . merge ( prop , GLOBAL_MERGE ) ; new_info . set_insn ( local_dem . get_insn ( ) ) ;"
GCC,riscv,298,"Predict the next statement of this code snippet:
 <s> const auto info = m_vector_manager -> vector_insn_infos [ INSN_UID ( rinsn ) ] ;"
GCC,riscv,299,"Predict the next statement of this code snippet:
 <s> if ( info . dirty_p ( ) ) info . set_unknown ( ) ; else { const auto dem = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . local_dem ; gcc_assert ( dem == * m_vector_manager -> vector_exprs [ i ] ) ; insn_info * insn = dem . get_insn ( ) ; gcc_assert ( insn && insn -> rtl ( ) ) ; rtx_insn * rinsn ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { m_vector_manager -> to_delete_vsetvls . add ( insn -> rtl ( ) ) ; continue ; } gcc_assert ( has_vtype_op ( insn -> rtl ( ) ) ) ; rinsn = PREV_INSN ( insn -> rtl ( ) ) ;"
GCC,riscv,300,"Predict the next statement of this code snippet:
 <s> FOR_EACH_BB_FN ( cfg_bb , cfun ) { auto & info = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . reaching_out ; gcc_assert ( m_vector_manager -> expr_set_num ( m_vector_manager -> vector_del [ cfg_bb -> index ] ) <= <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < m_vector_manager -> vector_exprs . length ( ) ; i ++ ) { if ( bitmap_bit_p ( m_vector_manager -> vector_del [ cfg_bb -> index ] , i ) ) { if ( info . dirty_p ( ) ) info . set_unknown ( ) ; else { const auto dem = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . local_dem ; gcc_assert ( dem == * m_vector_manager -> vector_exprs [ i ] ) ; insn_info * insn = dem . get_insn ( ) ; gcc_assert ( insn && insn -> rtl ( ) ) ;"
GCC,riscv,301,"Predict the next statement of this code snippet:
 <s> if ( vector_kill ) sbitmap_vector_free ( vector_kill ) ; if ( vector_antic ) sbitmap_vector_free ( vector_antic ) ; if ( vector_transp ) sbitmap_vector_free ( vector_transp ) ; if ( vector_comp ) sbitmap_vector_free ( vector_comp ) ; if ( vector_avin ) sbitmap_vector_free ( vector_avin ) ; if ( vector_avout ) sbitmap_vector_free ( vector_avout ) ; vector_edge_list = nullptr ;"
GCC,riscv,302,"Predict the next statement of this code snippet:
 <s> if ( info1 . demand_p ( DEMAND_AVL ) ) { if ( info1 . demand_p ( DEMAND_NONZERO_AVL ) ) { if ( info2 . demand_p ( DEMAND_AVL ) && ! info2 . demand_p ( DEMAND_NONZERO_AVL ) ) { set_avl_info ( info2 . get_avl_info ( ) ) ; set_demand ( DEMAND_AVL , true ) ; set_demand ( DEMAND_NONZERO_AVL , false ) ;"
GCC,riscv,303,"Predict the next statement of this code snippet:
 <s> if ( info2 . demand_p ( DEMAND_AVL ) && ! info2 . demand_p ( DEMAND_NONZERO_AVL ) ) { set_avl_info ( info2 . get_avl_info ( ) ) ; set_demand ( DEMAND_AVL , true ) ; set_demand ( DEMAND_NONZERO_AVL , false ) ; return ; } } set_avl_info ( info1 . get_avl_info ( ) ) ; set_demand ( DEMAND_NONZERO_AVL , info1 . demand_p ( DEMAND_NONZERO_AVL ) ) ; }"
GCC,riscv,304,"Predict the next statement of this code snippet:
 <s> else if ( info2 . demand_p ( DEMAND_MASK_POLICY ) ) { set_ma ( info2 . get_ma ( ) ) ; demand ( DEMAND_MASK_POLICY ) ; }"
GCC,riscv,305,"Predict the next statement of this code snippet:
 <s> if ( rule . pair . match_cond_p ( info2 . get_demands ( ) , info1 . get_demands ( ) ) ) { set_demand ( DEMAND_SEW , rule . demand_sew_p ) ; set_demand ( DEMAND_LMUL , rule . demand_lmul_p ) ; set_demand ( DEMAND_RATIO , rule . demand_ratio_p ) ; set_demand ( DEMAND_GE_SEW , rule . demand_ge_sew_p ) ; set_sew ( rule . new_sew ( info2 , info1 ) ) ; set_vlmul ( rule . new_vlmul ( info2 , info1 ) ) ; set_ratio ( rule . new_ratio ( info2 , info1 ) ) ; return ; } } gcc_unreachable ( ) ;"
GCC,riscv,306,"Predict the next statement of this code snippet:
 <s> if ( info1 . demand_p ( DEMAND_TAIL_POLICY ) ) { set_ta ( info1 . get_ta ( ) ) ; demand ( DEMAND_TAIL_POLICY ) ; } else if ( info2 . demand_p ( DEMAND_TAIL_POLICY ) ) {"
GCC,riscv,307,"Predict the next statement of this code snippet:
 <s> virtual bool gate ( function * ) final override { return TARGET_VECTOR ;"
GCC,riscv,308,"Predict the next statement of this code snippet:
 <s> rtx new_pat ; vl_vtype_info new_info = info ; if ( info . get_insn ( ) && info . get_insn ( ) -> rtl ( ) && fault_first_load_p ( info . get_insn ( ) -> rtl ( ) ) ) new_info . set_avl_info ( avl_info ( get_avl ( info . get_insn ( ) -> rtl ( ) ) , nullptr ) ) ; if ( vsetvl_insn_p ( rinsn ) || vlmax_avl_p ( info . get_avl ( ) ) ) { rtx dest = get_vl ( rinsn ) ; new_pat = gen_vsetvl_pat ( VSETVL_NORMAL , new_info , dest ) ; } else if ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_vtype_change_only ) new_pat = gen_vsetvl_pat ( VSETVL_VTYPE_CHANGE_ONLY , new_info , NULL_RTX ) ; else new_pat = gen_vsetvl_pat ( VSETVL_DISCARD_RESULT , new_info , NULL_RTX ) ; return new_pat ;"
GCC,riscv,309,"Predict the next statement of this code snippet:
 <s> if ( vsetvl_insn_p ( rinsn ) || vlmax_avl_p ( info . get_avl ( ) ) ) { rtx dest = get_vl ( rinsn ) ; new_pat = gen_vsetvl_pat ( VSETVL_NORMAL , new_info , dest ) ; } else if ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_vtype_change_only ) new_pat = gen_vsetvl_pat ( VSETVL_VTYPE_CHANGE_ONLY , new_info , NULL_RTX ) ;"
GCC,riscv,310,"Predict the next statement of this code snippet:
 <s> auto_vec < size_t > available_list ;"
GCC,riscv,311,"Predict the next statement of this code snippet:
 <s> auto_vec < size_t > available_list ;"
GCC,riscv,312,"Predict the next statement of this code snippet:
 <s> while ( ! work_list . is_empty ( ) ) { basic_block new_cfg_bb = work_list . pop ( ) ; visited_list . add ( new_cfg_bb ) ; edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , new_cfg_bb -> preds ) { if ( ! visited_list . contains ( e -> src ) ) work_list . safe_push ( e -> src ) ; blocks . add ( e -> src ) ;"
GCC,riscv,313,"Predict the next statement of this code snippet:
 <s> auto_vec < basic_block > work_list ; hash_set < basic_block > visited_list ; work_list . safe_push ( cfg_bb ) ; while ( ! work_list . is_empty ( ) ) {"
GCC,riscv,314,"Predict the next statement of this code snippet:
 <s> static hash_set < set_info * > get_all_sets ( set_info * set , bool real_p , bool phi_p , bool param_p ) {"
GCC,riscv,315,"Predict the next statement of this code snippet:
 <s> return m_avl . get_value ( ) ;"
GCC,riscv,316,"Predict the next statement of this code snippet:
 <s> const avl_info & get_avl_info ( ) const {"
GCC,riscv,317,"Predict the next statement of this code snippet:
 <s> return gen_rtx_REG ( Pmode , get_avl_source ( ) -> regno ( ) ) ;"
GCC,riscv,318,"Predict the next statement of this code snippet:
 <s> return m_avl . get_source ( ) ;"
GCC,riscv,319,"Predict the next statement of this code snippet:
 <s> static const insn_info * get_backward_fault_first_load_insn ( const insn_info * insn ) { const bb_info * bb = insn -> bb ( ) ; for ( const insn_info * i = insn -> prev_nondebug_insn ( ) ; real_insn_and_same_bb_p ( i , bb ) ; i = i -> prev_nondebug_insn ( ) ) {"
GCC,riscv,320,"Predict the next statement of this code snippet:
 <s> if ( ! prop . demand_p ( DEMAND_AVL ) ) return VALID_AVL_FUSION ; else { if ( prop . has_avl_imm ( ) ) return VALID_AVL_FUSION ; else { gcc_assert ( prop . has_avl_reg ( ) ) ; if ( vlmax_avl_p ( prop . get_avl ( ) ) ) reg = prop . get_avl_reg_rtx ( ) ; else reg = prop . get_avl ( ) ; } } gcc_assert ( reg ) ; if ( ! prop . get_avl_source ( ) -> insn ( ) -> is_phi ( ) && prop . get_avl_source ( ) -> insn ( ) -> bb ( ) == insn -> bb ( ) ) return INVALID_FUSION ; hash_set < set_info * > sets = get_all_sets ( prop . get_avl_source ( ) , true , true , true ) ; if ( any_set_in_bb_p ( sets , insn -> bb ( ) ) ) return INVALID_FUSION ; if ( vlmax_avl_p ( prop . get_avl ( ) ) ) { if ( find_reg_killed_by ( bb , reg ) ) return INVALID_FUSION ; else return VALID_AVL_FUSION ;"
GCC,riscv,321,"Predict the next statement of this code snippet:
 <s> return ( bool ) ( get_prefer_mask_policy ( ) & <NUM_LIT> || ( get_prefer_mask_policy ( ) >> <NUM_LIT> & <NUM_LIT> ) ) ;"
GCC,riscv,322,"Predict the next statement of this code snippet:
 <s> static bool get_default_ta ( ) {"
GCC,riscv,323,"Predict the next statement of this code snippet:
 <s> return m_demands ;"
GCC,riscv,324,"Predict the next statement of this code snippet:
 <s> const bool * get_demands ( void ) const { return m_demands ;"
GCC,riscv,325,"Predict the next statement of this code snippet:
 <s> size_t vector_infos_manager :: get_expr_id ( const vector_insn_info & info ) const { for ( size_t i = <NUM_LIT> ; i < vector_exprs . length ( ) ; i ++ ) if ( * vector_exprs [ i ] == info ) return i ;"
GCC,riscv,326,"Predict the next statement of this code snippet:
 <s> for ( const insn_info * i = insn -> next_nondebug_insn ( ) ; real_insn_and_same_bb_p ( i , bb ) ; i = i -> next_nondebug_insn ( ) ) { if ( find_access ( i -> defs ( ) , VL_REGNUM ) ) return nullptr ;"
GCC,riscv,327,"Predict the next statement of this code snippet:
 <s> const bb_info * bb = insn -> bb ( ) ; for ( const insn_info * i = insn -> next_nondebug_insn ( ) ; real_insn_and_same_bb_p ( i , bb ) ; i = i -> next_nondebug_insn ( ) ) { if ( find_access ( i -> defs ( ) , VL_REGNUM ) ) return nullptr ; if ( read_vl_insn_p ( i -> rtl ( ) ) ) return i ;"
GCC,riscv,328,"Predict the next statement of this code snippet:
 <s> static vector_insn_info get_hard_empty ( ) {"
GCC,riscv,329,"Predict the next statement of this code snippet:
 <s> static vector_insn_info get_hard_empty ( ) {"
GCC,riscv,330,"Predict the next statement of this code snippet:
 <s> return m_insn ;"
GCC,riscv,331,"Predict the next statement of this code snippet:
 <s> rtl_ssa :: insn_info * get_insn ( ) const { return m_insn ;"
GCC,riscv,332,"Predict the next statement of this code snippet:
 <s> bool get_ma ( ) const {"
GCC,riscv,333,"Predict the next statement of this code snippet:
 <s> return m_ratio ;"
GCC,riscv,334,"Predict the next statement of this code snippet:
 <s> uint8_t get_ratio ( ) const {"
GCC,riscv,335,"Predict the next statement of this code snippet:
 <s> for ( set_info * set : sets ) if ( set -> bb ( ) -> cfg_bb ( ) == cfg_bb ) return set ; return nullptr ;"
GCC,riscv,336,"Predict the next statement of this code snippet:
 <s> static set_info * get_same_bb_set ( hash_set < set_info * > & sets , const basic_block cfg_bb ) { for ( set_info * set : sets ) if ( set -> bb ( ) -> cfg_bb ( ) == cfg_bb ) return set ; return nullptr ;"
GCC,riscv,337,"Predict the next statement of this code snippet:
 <s> uint8_t get_sew ( ) const { return m_sew ;"
GCC,riscv,338,"Predict the next statement of this code snippet:
 <s> uint8_t get_sew ( ) const { return m_sew ;"
GCC,riscv,339,"Predict the next statement of this code snippet:
 <s> return m_source ;"
GCC,riscv,340,"Predict the next statement of this code snippet:
 <s> bool get_ta ( ) const {"
GCC,riscv,341,"Predict the next statement of this code snippet:
 <s> return m_ta ;"
GCC,riscv,342,"Predict the next statement of this code snippet:
 <s> info . set_unknown ( ) ; return info ;"
GCC,riscv,343,"Predict the next statement of this code snippet:
 <s> rtx get_value ( ) const { return m_value ;"
GCC,riscv,344,"Predict the next statement of this code snippet:
 <s> return recog_data . operand [ get_attr_vl_op_idx ( rinsn ) ] ; }"
GCC,riscv,345,"Predict the next statement of this code snippet:
 <s> return m_vlmul ;"
GCC,riscv,346,"Predict the next statement of this code snippet:
 <s> return m_vlmul ;"
GCC,riscv,347,"Predict the next statement of this code snippet:
 <s> else set = nullptr ; } uint8_t sew = get_sew ( insn -> rtl ( ) ) ; enum vlmul_type vlmul = get_vlmul ( insn -> rtl ( ) ) ; uint8_t ratio = get_attr_ratio ( insn -> rtl ( ) ) ; if ( ratio == INVALID_ATTRIBUTE ) ratio = calculate_ratio ( sew , vlmul ) ; bool ta = tail_agnostic_p ( insn -> rtl ( ) ) ; bool ma = mask_agnostic_p ( insn -> rtl ( ) ) ;"
GCC,riscv,348,"Predict the next statement of this code snippet:
 <s> static bool ge_sew_lmul_unavailable_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { if ( ! info2 . demand_p ( DEMAND_RATIO ) && info2 . demand_p ( DEMAND_GE_SEW ) ) return info1 . get_sew ( ) < info2 . get_sew ( ) ; return true ;"
GCC,riscv,349,"Predict the next statement of this code snippet:
 <s> if ( ! info2 . demand_p ( DEMAND_LMUL ) && info2 . demand_p ( DEMAND_GE_SEW ) ) return info1 . get_sew ( ) < info2 . get_sew ( ) ; return true ;"
GCC,riscv,350,"Predict the next statement of this code snippet:
 <s> static bool ge_sew_ratio_unavailable_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { if ( ! info2 . demand_p ( DEMAND_LMUL ) && info2 . demand_p ( DEMAND_GE_SEW ) ) return info1 . get_sew ( ) < info2 . get_sew ( ) ; return true ;"
GCC,riscv,351,"Predict the next statement of this code snippet:
 <s> static bool ge_sew_unavailable_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { if ( ! info2 . demand_p ( DEMAND_LMUL ) && ! info2 . demand_p ( DEMAND_RATIO ) && info2 . demand_p ( DEMAND_GE_SEW ) ) return info1 . get_sew ( ) < info2 . get_sew ( ) ;"
GCC,riscv,352,"Predict the next statement of this code snippet:
 <s> return std :: max ( info1 . get_sew ( ) , info2 . get_sew ( ) ) ;"
GCC,riscv,353,"Predict the next statement of this code snippet:
 <s> return std :: max ( info1 . get_sew ( ) , info2 . get_sew ( ) ) ;"
GCC,riscv,354,"Predict the next statement of this code snippet:
 <s> bool hard_empty_p ( ) const { return m_state == HARD_EMPTY ;"
GCC,riscv,355,"Predict the next statement of this code snippet:
 <s> return m_avl . has_avl_imm ( ) ;"
GCC,riscv,356,"Predict the next statement of this code snippet:
 <s> bool has_avl_imm ( ) const {"
GCC,riscv,357,"Predict the next statement of this code snippet:
 <s> bool has_avl_no_reg ( ) const {"
GCC,riscv,358,"Predict the next statement of this code snippet:
 <s> return m_avl . has_avl_no_reg ( ) ;"
GCC,riscv,359,"Predict the next statement of this code snippet:
 <s> return m_avl . has_avl_reg ( ) ;"
GCC,riscv,360,"Predict the next statement of this code snippet:
 <s> FOR_ALL_BB_FN ( cfg_bb , fn ) FOR_BB_INSNS ( cfg_bb , rinsn ) if ( NONDEBUG_INSN_P ( rinsn ) && has_vtype_op ( rinsn ) ) return true ; return false ;"
GCC,riscv,361,"Predict the next statement of this code snippet:
 <s> basic_block cfg_bb ; rtx_insn * rinsn ; FOR_ALL_BB_FN ( cfg_bb , fn ) FOR_BB_INSNS ( cfg_bb , rinsn ) if ( NONDEBUG_INSN_P ( rinsn ) && has_vtype_op ( rinsn ) ) return true ;"
GCC,riscv,362,"Predict the next statement of this code snippet:
 <s> return recog_memoized ( rinsn ) >= <NUM_LIT> && get_attr_has_vl_op ( rinsn ) ;"
GCC,riscv,363,"Predict the next statement of this code snippet:
 <s> static bool has_vsetvl_killed_avl_p ( const bb_info * bb , const vector_insn_info & info ) { if ( info . dirty_with_killed_avl_p ( ) ) { rtx avl = info . get_avl ( ) ; if ( vlmax_avl_p ( avl ) ) return find_reg_killed_by ( bb , info . get_avl_reg_rtx ( ) ) != nullptr ; for ( const insn_info * insn : bb -> reverse_real_nondebug_insns ( ) ) {"
GCC,riscv,364,"Predict the next statement of this code snippet:
 <s> set_info * set = safe_dyn_cast < set_info * > ( def ) ; if ( ! set ) return false ; rtx new_avl = gen_rtx_REG ( GET_MODE ( avl ) , REGNO ( avl ) ) ; gcc_assert ( new_avl != avl ) ; if ( ! info . compatible_avl_p ( avl_info ( new_avl , set ) ) ) return false ; return true ; } } } return false ;"
GCC,riscv,365,"Predict the next statement of this code snippet:
 <s> return recog_memoized ( rinsn ) >= <NUM_LIT> && get_attr_has_vtype_op ( rinsn ) ;"
GCC,riscv,366,"Predict the next statement of this code snippet:
 <s> static bool has_vtype_op ( rtx_insn * rinsn ) {"
GCC,riscv,367,"Predict the next statement of this code snippet:
 <s> return get_attr_type ( rinsn ) == TYPE_VIMOVVX || get_attr_type ( rinsn ) == TYPE_VFMOVVF || get_attr_type ( rinsn ) == TYPE_VIMOVXV || get_attr_type ( rinsn ) == TYPE_VFMOVFV ;"
GCC,riscv,368,"Predict the next statement of this code snippet:
 <s> static bool ignore_vlmul_insn_p ( rtx_insn * rinsn ) {"
GCC,riscv,369,"Predict the next statement of this code snippet:
 <s> m_vector_manager = new vector_infos_manager ( ) ; compute_probabilities ( ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; m_vector_manager -> dump ( dump_file ) ;"
GCC,riscv,370,"Predict the next statement of this code snippet:
 <s> } else if ( CALL_P ( end_rinsn ) && ( ! single_succ_p ( cfg_bb ) || single_succ_edge ( cfg_bb ) -> flags & EDGE_ABNORMAL ) ) { end_rinsn = find_first_parameter_load ( end_rinsn , BB_HEAD ( cfg_bb ) ) ; while ( LABEL_P ( end_rinsn ) || NOTE_INSN_BASIC_BLOCK_P ( end_rinsn ) ) end_rinsn = NEXT_INSN ( end_rinsn ) ; new_insn = emit_insn_before_noloc ( pat , end_rinsn , cfg_bb ) ; } else new_insn = emit_insn_after_noloc ( pat , end_rinsn , cfg_bb ) ; while ( <NUM_LIT> ) { if ( INSN_P ( pat ) ) add_label_notes ( PATTERN ( pat ) , new_insn ) ; if ( pat == pat_end ) break ; pat = NEXT_INSN ( pat ) ;"
GCC,riscv,371,"Predict the next statement of this code snippet:
 <s> pat_end = pat ; while ( NEXT_INSN ( pat_end ) != NULL_RTX ) pat_end = NEXT_INSN ( pat_end ) ; if ( JUMP_P ( end_rinsn ) || ( NONJUMP_INSN_P ( end_rinsn ) && ( ! single_succ_p ( cfg_bb ) || single_succ_edge ( cfg_bb ) -> flags & EDGE_ABNORMAL ) ) ) { new_insn = emit_insn_before_noloc ( pat , end_rinsn , cfg_bb ) ; } else if ( CALL_P ( end_rinsn ) && ( ! single_succ_p ( cfg_bb ) || single_succ_edge ( cfg_bb ) -> flags & EDGE_ABNORMAL ) ) { end_rinsn = find_first_parameter_load ( end_rinsn , BB_HEAD ( cfg_bb ) ) ; while ( LABEL_P ( end_rinsn ) || NOTE_INSN_BASIC_BLOCK_P ( end_rinsn ) ) end_rinsn = NEXT_INSN ( end_rinsn ) ; new_insn = emit_insn_before_noloc ( pat , end_rinsn , cfg_bb ) ; } else new_insn = emit_insn_after_noloc ( pat , end_rinsn , cfg_bb ) ; while ( <NUM_LIT> ) { if ( INSN_P ( pat ) ) add_label_notes ( PATTERN ( pat ) , new_insn ) ; if ( pat == pat_end ) break ; pat = NEXT_INSN ( pat ) ; }"
GCC,riscv,372,"Predict the next statement of this code snippet:
 <s> if ( insn -> is_real ( ) && ( types & REAL_SET ) ) return true ; if ( insn -> is_phi ( ) && ( types & PHI_SET ) ) return true ;"
GCC,riscv,373,"Predict the next statement of this code snippet:
 <s> static bool insn_should_be_added_p ( const insn_info * insn , unsigned int types ) { if ( insn -> is_real ( ) && ( types & REAL_SET ) ) return true ; if ( insn -> is_phi ( ) && ( types & PHI_SET ) ) return true ; if ( insn -> is_bb_head ( ) && ( types & BB_HEAD_SET ) ) return true ; if ( insn -> is_bb_end ( ) && ( types & BB_END_SET ) ) return true ; return false ;"
GCC,riscv,374,"Predict the next statement of this code snippet:
 <s> for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) compute_local_backward_infos ( bb ) ; if ( dump_file ) m_vector_manager -> dump ( dump_file ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) emit_local_forward_vsetvls ( bb ) ; if ( dump_file ) m_vector_manager -> dump ( dump_file ) ;"
GCC,riscv,375,"Predict the next statement of this code snippet:
 <s> if ( info1 . get_vlmul ( ) == info2 . get_vlmul ( ) && ! info2 . demand_p ( DEMAND_SEW ) && ! info2 . demand_p ( DEMAND_RATIO ) ) return false ; return true ;"
GCC,riscv,376,"Predict the next statement of this code snippet:
 <s> if ( info1 . get_vlmul ( ) == info2 . get_vlmul ( ) && ! info2 . demand_p ( DEMAND_SEW ) && ! info2 . demand_p ( DEMAND_RATIO ) ) return false ;"
GCC,riscv,377,"Predict the next statement of this code snippet:
 <s> edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , cfg_bb -> succs ) if ( e -> dest -> index == cfg_bb -> index ) return true ; }"
GCC,riscv,378,"Predict the next statement of this code snippet:
 <s> rtl_opt_pass * make_pass_vsetvl ( gcc :: context * ctxt ) { return new pass_vsetvl ( ctxt ) ;"
GCC,riscv,379,"Predict the next statement of this code snippet:
 <s> return ma == INVALID_ATTRIBUTE ? get_default_ma ( ) : IS_AGNOSTIC ( ma ) ;"
GCC,riscv,380,"Predict the next statement of this code snippet:
 <s> extract_insn_cached ( rinsn ) ; int ma = get_attr_ma ( rinsn ) ;"
GCC,riscv,381,"Predict the next statement of this code snippet:
 <s> bool match_cond_p ( const bool * dems1 , const bool * dems2 ) const { for ( unsigned i = <NUM_LIT> ; i < NUM_DEMAND ; i ++ ) {"
GCC,riscv,382,"Predict the next statement of this code snippet:
 <s> return m_source == other . get_source ( ) ;"
GCC,riscv,383,"Predict the next statement of this code snippet:
 <s> if ( ! curr_info . valid_p ( ) || curr_info . unknown_p ( ) || curr_info . uninit_p ( ) ) return true ; if ( require . compatible_p ( static_cast < const vl_vtype_info & > ( curr_info ) ) ) return false ; return true ;"
GCC,riscv,384,"Predict the next statement of this code snippet:
 <s> bool pass_vsetvl :: need_vsetvl ( const vector_insn_info & require , const vector_insn_info & curr_info ) const { if ( ! curr_info . valid_p ( ) || curr_info . unknown_p ( ) || curr_info . uninit_p ( ) ) return true ;"
GCC,riscv,385,"Predict the next statement of this code snippet:
 <s> m_demands [ DEMAND_SEW ] = true ; if ( ! ignore_vlmul_insn_p ( insn -> rtl ( ) ) ) m_demands [ DEMAND_LMUL ] = true ; } if ( get_attr_ta ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_TAIL_POLICY ] = true ; if ( get_attr_ma ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_MASK_POLICY ] = true ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) return ; if ( scalar_move_insn_p ( insn -> rtl ( ) ) ) { if ( m_avl . has_non_zero_avl ( ) ) m_demands [ DEMAND_NONZERO_AVL ] = true ; if ( m_ta ) m_demands [ DEMAND_GE_SEW ] = true ; } if ( ! m_avl . has_avl_reg ( ) || vlmax_avl_p ( get_avl ( ) ) || ! m_avl . get_source ( ) ) return ; if ( ! m_avl . get_source ( ) -> insn ( ) -> is_real ( ) && ! m_avl . get_source ( ) -> insn ( ) -> is_phi ( ) ) return ;"
GCC,riscv,386,"Predict the next statement of this code snippet:
 <s> return ; } if ( ! vector_config_insn_p ( insn -> rtl ( ) ) && ! has_vtype_op ( insn -> rtl ( ) ) && ( find_access ( insn -> defs ( ) , VL_REGNUM ) || find_access ( insn -> defs ( ) , VTYPE_REGNUM ) ) ) { set_unknown ( ) ; return ; } if ( ! vector_config_insn_p ( insn -> rtl ( ) ) && ! has_vtype_op ( insn -> rtl ( ) ) ) return ; vl_vtype_info :: operator = ( get_vl_vtype_info ( insn ) ) ; m_insn = insn ; m_state = VALID ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { m_demands [ DEMAND_AVL ] = true ; m_demands [ DEMAND_RATIO ] = true ; return ; } if ( has_vl_op ( insn -> rtl ( ) ) ) m_demands [ DEMAND_AVL ] = true ; if ( get_attr_ratio ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_RATIO ] = true ; else { m_demands [ DEMAND_SEW ] = true ; if ( ! ignore_vlmul_insn_p ( insn -> rtl ( ) ) ) m_demands [ DEMAND_LMUL ] = true ; } if ( get_attr_ta ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_TAIL_POLICY ] = true ; if ( get_attr_ma ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_MASK_POLICY ] = true ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) return ;"
GCC,riscv,387,"Predict the next statement of this code snippet:
 <s> pass_vsetvl ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_vsetvl , ctxt ) {"
GCC,riscv,388,"Predict the next statement of this code snippet:
 <s> pass_vsetvl ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_vsetvl , ctxt ) {"
GCC,riscv,389,"Predict the next statement of this code snippet:
 <s> return ! info1 . has_non_zero_avl ( ) || ! info2 . has_non_zero_avl ( ) ;"
GCC,riscv,390,"Predict the next statement of this code snippet:
 <s> compute_local_properties ( ) ; m_vector_manager -> vector_edge_list = pre_edge_lcm_avs ( m_vector_manager -> vector_exprs . length ( ) , m_vector_manager -> vector_transp , m_vector_manager -> vector_comp , m_vector_manager -> vector_antic , m_vector_manager -> vector_kill , m_vector_manager -> vector_avin , m_vector_manager -> vector_avout , & m_vector_manager -> vector_insert , & m_vector_manager -> vector_del ) ; if ( dump_file ) m_vector_manager -> dump ( dump_file ) ; refine_vsetvls ( ) ; cleanup_vsetvls ( ) ; bool need_commit = commit_vsetvls ( ) ;"
GCC,riscv,391,"Predict the next statement of this code snippet:
 <s> rtx vl = get_vl ( insn -> rtl ( ) ) ; rtx avl = get_avl ( insn -> rtl ( ) ) ; def_info * def = find_access ( insn -> defs ( ) , REGNO ( vl ) ) ; set_info * set = safe_dyn_cast < set_info * > ( def ) ; vector_insn_info info ; info . parse_insn ( insn ) ; gcc_assert ( set ) ; if ( m_vector_manager -> to_delete_vsetvls . contains ( insn -> rtl ( ) ) ) { m_vector_manager -> to_delete_vsetvls . remove ( insn -> rtl ( ) ) ; if ( m_vector_manager -> to_refine_vsetvls . contains ( insn -> rtl ( ) ) ) m_vector_manager -> to_refine_vsetvls . remove ( insn -> rtl ( ) ) ; if ( ! set -> has_nondebug_insn_uses ( ) ) { to_delete . add ( insn -> rtl ( ) ) ; continue ; } } if ( m_vector_manager -> to_refine_vsetvls . contains ( insn -> rtl ( ) ) ) { m_vector_manager -> to_refine_vsetvls . remove ( insn -> rtl ( ) ) ; if ( ! set -> has_nondebug_insn_uses ( ) ) { rtx new_pat = gen_vsetvl_pat ( VSETVL_VTYPE_CHANGE_ONLY , info , NULL_RTX ) ; change_insn ( insn -> rtl ( ) , new_pat ) ; continue ; } } if ( vlmax_avl_p ( avl ) ) continue ; rtx new_pat = gen_vsetvl_pat ( VSETVL_DISCARD_RESULT , info , NULL_RTX ) ; if ( ! set -> has_nondebug_insn_uses ( ) ) { validate_change ( insn -> rtl ( ) , & PATTERN ( insn -> rtl ( ) ) , new_pat , false ) ; continue ; } }"
GCC,riscv,392,"Predict the next statement of this code snippet:
 <s> if ( info2 . demand_p ( DEMAND_NONZERO_AVL ) ) return info1 . demand_p ( DEMAND_AVL ) && ! info1 . demand_p ( DEMAND_NONZERO_AVL ) && info1 . has_avl_reg ( ) ; }"
GCC,riscv,393,"Predict the next statement of this code snippet:
 <s> void pass_vsetvl :: prune_expressions ( void ) { for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { if ( m_vector_manager -> vector_block_infos [ bb -> index ( ) ] . local_dem . valid_or_dirty_p ( ) ) m_vector_manager -> create_expr ( m_vector_manager -> vector_block_infos [ bb -> index ( ) ] . local_dem ) ; if ( m_vector_manager -> vector_block_infos [ bb -> index ( ) ] . reaching_out . valid_or_dirty_p ( ) ) m_vector_manager -> create_expr ( m_vector_manager -> vector_block_infos [ bb -> index ( ) ] . reaching_out ) ; } if ( dump_file ) {"
GCC,riscv,394,"Predict the next statement of this code snippet:
 <s> return calculate_ratio ( info2 . get_sew ( ) , info1 . get_vlmul ( ) ) ;"
GCC,riscv,395,"Predict the next statement of this code snippet:
 <s> static bool read_vl_insn_p ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= <NUM_LIT> && get_attr_type ( rinsn ) == TYPE_RDVL ;"
GCC,riscv,396,"Predict the next statement of this code snippet:
 <s> static bool real_insn_and_same_bb_p ( const insn_info * insn , const bb_info * bb ) {"
GCC,riscv,397,"Predict the next statement of this code snippet:
 <s> if ( ! info . valid_p ( ) ) continue ; rtx_insn * rinsn = insn -> rtl ( ) ; if ( ! can_refine_vsetvl_p ( cfg_bb , info ) ) continue ; if ( vector_config_insn_p ( rinsn ) ) { m_vector_manager -> to_refine_vsetvls . add ( rinsn ) ; continue ; } rinsn = PREV_INSN ( rinsn ) ; rtx new_pat = gen_vsetvl_pat ( VSETVL_VTYPE_CHANGE_ONLY , info , NULL_RTX ) ; change_insn ( rinsn , new_pat ) ;"
GCC,riscv,398,"Predict the next statement of this code snippet:
 <s> if ( vector_config_insn_p ( rinsn ) ) { m_vector_manager -> to_refine_vsetvls . add ( rinsn ) ; continue ; } rinsn = PREV_INSN ( rinsn ) ; rtx new_pat = gen_vsetvl_pat ( VSETVL_VTYPE_CHANGE_ONLY , info , NULL_RTX ) ; change_insn ( rinsn , new_pat ) ; }"
GCC,riscv,399,"Predict the next statement of this code snippet:
 <s> static bool reg_available_p ( const insn_info * insn , const vector_insn_info & info ) { if ( info . has_avl_reg ( ) && ! info . get_avl_source ( ) ) return false ; insn_info * def_insn = info . get_avl_source ( ) -> insn ( ) ;"
GCC,riscv,400,"Predict the next statement of this code snippet:
 <s> if ( ! vector_block_infos . is_empty ( ) ) vector_block_infos . release ( ) ; if ( ! vector_exprs . is_empty ( ) ) vector_exprs . release ( ) ; gcc_assert ( to_refine_vsetvls . is_empty ( ) ) ; gcc_assert ( to_delete_vsetvls . is_empty ( ) ) ; if ( optimize > <NUM_LIT> ) free_bitmap_vectors ( ) ;"
GCC,riscv,401,"Predict the next statement of this code snippet:
 <s> void vector_infos_manager :: release ( void ) { if ( ! vector_insn_infos . is_empty ( ) ) vector_insn_infos . release ( ) ; if ( ! vector_block_infos . is_empty ( ) ) vector_block_infos . release ( ) ; if ( ! vector_exprs . is_empty ( ) ) vector_exprs . release ( ) ; gcc_assert ( to_refine_vsetvls . is_empty ( ) ) ; gcc_assert ( to_delete_vsetvls . is_empty ( ) ) ;"
GCC,riscv,402,"Predict the next statement of this code snippet:
 <s> bool vl_vtype_info :: same_avl_p ( const vl_vtype_info & other ) const { return get_avl ( ) == other . get_avl ( ) && get_avl_source ( ) == other . get_avl_source ( ) ;"
GCC,riscv,403,"Predict the next statement of this code snippet:
 <s> return dems1 [ DEMAND_SEW ] == dems2 [ DEMAND_SEW ] && dems1 [ DEMAND_LMUL ] == dems2 [ DEMAND_LMUL ] && dems1 [ DEMAND_RATIO ] == dems2 [ DEMAND_RATIO ] && ! dems1 [ DEMAND_GE_SEW ] && ! dems2 [ DEMAND_GE_SEW ] ;"
GCC,riscv,404,"Predict the next statement of this code snippet:
 <s> return get_ratio ( ) == other . get_ratio ( ) ;"
GCC,riscv,405,"Predict the next statement of this code snippet:
 <s> bool vl_vtype_info :: same_vtype_p ( const vl_vtype_info & other ) const { return get_sew ( ) == other . get_sew ( ) && get_vlmul ( ) == other . get_vlmul ( ) && get_ta ( ) == other . get_ta ( ) && get_ma ( ) == other . get_ma ( ) ;"
GCC,riscv,406,"Predict the next statement of this code snippet:
 <s> bool vl_vtype_info :: same_vtype_p ( const vl_vtype_info & other ) const {"
GCC,riscv,407,"Predict the next statement of this code snippet:
 <s> return get_attr_type ( rinsn ) == TYPE_VIMOVXV || get_attr_type ( rinsn ) == TYPE_VFMOVFV ;"
GCC,riscv,408,"Predict the next statement of this code snippet:
 <s> static bool second_lmul_less_than_first_lmul_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) {"
GCC,riscv,409,"Predict the next statement of this code snippet:
 <s> static unsigned second_ratio ( const vector_insn_info & , const vector_insn_info & info2 ) {"
GCC,riscv,410,"Predict the next statement of this code snippet:
 <s> static unsigned second_ratio ( const vector_insn_info & , const vector_insn_info & info2 ) {"
GCC,riscv,411,"Predict the next statement of this code snippet:
 <s> static bool second_ratio_invalid_for_first_lmul_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return calculate_sew ( info1 . get_vlmul ( ) , info2 . get_ratio ( ) ) == <NUM_LIT> ;"
GCC,riscv,412,"Predict the next statement of this code snippet:
 <s> static bool second_ratio_invalid_for_first_sew_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return calculate_vlmul ( info1 . get_sew ( ) , info2 . get_ratio ( ) ) == LMUL_RESERVED ;"
GCC,riscv,413,"Predict the next statement of this code snippet:
 <s> return info2 . get_ratio ( ) < info1 . get_ratio ( ) ;"
GCC,riscv,414,"Predict the next statement of this code snippet:
 <s> return info2 . get_sew ( ) ;"
GCC,riscv,415,"Predict the next statement of this code snippet:
 <s> static bool second_sew_less_than_first_sew_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) {"
GCC,riscv,416,"Predict the next statement of this code snippet:
 <s> static vlmul_type second_vlmul ( const vector_insn_info & , const vector_insn_info & info2 ) {"
GCC,riscv,417,"Predict the next statement of this code snippet:
 <s> m_avl = avl ;"
GCC,riscv,418,"Predict the next statement of this code snippet:
 <s> void set_avl_info ( const avl_info & avl ) { m_avl = avl ;"
GCC,riscv,419,"Predict the next statement of this code snippet:
 <s> void set_demand ( enum demand_type type , bool value ) { m_demands [ type ] = value ;"
GCC,riscv,420,"Predict the next statement of this code snippet:
 <s> m_demands [ type ] = value ;"
GCC,riscv,421,"Predict the next statement of this code snippet:
 <s> void set_dirty ( bool dirty_with_killed_avl_p ) {"
GCC,riscv,422,"Predict the next statement of this code snippet:
 <s> m_state = EMPTY ;"
GCC,riscv,423,"Predict the next statement of this code snippet:
 <s> void set_hard_empty ( ) { m_state = HARD_EMPTY ;"
GCC,riscv,424,"Predict the next statement of this code snippet:
 <s> void set_hard_empty ( ) {"
GCC,riscv,425,"Predict the next statement of this code snippet:
 <s> m_insn = insn ;"
GCC,riscv,426,"Predict the next statement of this code snippet:
 <s> m_insn = insn ;"
GCC,riscv,427,"Predict the next statement of this code snippet:
 <s> m_ma = ma ;"
GCC,riscv,428,"Predict the next statement of this code snippet:
 <s> void set_ma ( bool ma ) {"
GCC,riscv,429,"Predict the next statement of this code snippet:
 <s> m_ratio = ratio ;"
GCC,riscv,430,"Predict the next statement of this code snippet:
 <s> void set_ratio ( uint8_t ratio ) { m_ratio = ratio ;"
GCC,riscv,431,"Predict the next statement of this code snippet:
 <s> m_sew = sew ;"
GCC,riscv,432,"Predict the next statement of this code snippet:
 <s> void set_ta ( bool ta ) {"
GCC,riscv,433,"Predict the next statement of this code snippet:
 <s> void set_unknown ( ) {"
GCC,riscv,434,"Predict the next statement of this code snippet:
 <s> void set_valid ( ) { m_state = VALID ;"
GCC,riscv,435,"Predict the next statement of this code snippet:
 <s> m_vlmul = vlmul ;"
GCC,riscv,436,"Predict the next statement of this code snippet:
 <s> FOR_ALL_BB_FN ( cfg_bb , cfun ) { FOR_BB_INSNS ( cfg_bb , rinsn ) { if ( ! NONDEBUG_INSN_P ( rinsn ) ) continue ; if ( has_vtype_op ( rinsn ) ) { const auto info = m_vector_manager -> vector_insn_infos [ INSN_UID ( rinsn ) ] ; emit_vsetvl_insn ( VSETVL_DISCARD_RESULT , EMIT_BEFORE , info , NULL_RTX , rinsn ) ; } } }"
GCC,riscv,437,"Predict the next statement of this code snippet:
 <s> if ( ! NONDEBUG_INSN_P ( rinsn ) ) continue ; if ( has_vtype_op ( rinsn ) ) { const auto info = m_vector_manager -> vector_insn_infos [ INSN_UID ( rinsn ) ] ; emit_vsetvl_insn ( VSETVL_DISCARD_RESULT , EMIT_BEFORE , info , NULL_RTX , rinsn ) ; } } }"
GCC,riscv,438,"Predict the next statement of this code snippet:
 <s> insn_info * insn2 = extract_single_source ( set2 ) ; if ( ! insn1 || ! insn2 ) return false ;"
GCC,riscv,439,"Predict the next statement of this code snippet:
 <s> } if ( note1 && note2 && rtx_equal_p ( note1 , note2 ) ) return true ; if ( vsetvl_insn_p ( insn1 -> rtl ( ) ) && vsetvl_insn_p ( insn2 -> rtl ( ) ) ) { vector_insn_info insn1_info , insn2_info ; insn1_info . parse_insn ( insn1 ) ; insn2_info . parse_insn ( insn2 ) ; if ( insn1_info . same_vlmax_p ( insn2_info ) && insn1_info . compatible_avl_p ( insn2_info ) ) return true ; } if ( ! single_set1 || ! single_set2 ) return false ; if ( ! rtx_equal_p ( SET_SRC ( single_set1 ) , SET_SRC ( single_set2 ) ) ) return false ; gcc_assert ( insn1 -> uses ( ) . size ( ) == insn2 -> uses ( ) . size ( ) ) ;"
GCC,riscv,440,"Predict the next statement of this code snippet:
 <s> for ( set_info * set : sets ) { if ( read_vl_insn_p ( set -> insn ( ) -> rtl ( ) ) ) { const insn_info * insn = get_backward_fault_first_load_insn ( set -> insn ( ) ) ; if ( insn == info1 . get_insn ( ) ) return info2 . compatible_vtype_p ( info1 ) ; } } } return false ;"
GCC,riscv,441,"Predict the next statement of this code snippet:
 <s> extract_insn_cached ( rinsn ) ; int ta = get_attr_ta ( rinsn ) ; return ta == INVALID_ATTRIBUTE ? get_default_ta ( ) : IS_AGNOSTIC ( ta ) ;"
GCC,riscv,442,"Predict the next statement of this code snippet:
 <s> int ta = get_attr_ta ( rinsn ) ; return ta == INVALID_ATTRIBUTE ? get_default_ta ( ) : IS_AGNOSTIC ( ta ) ;"
GCC,riscv,443,"Predict the next statement of this code snippet:
 <s> info = m_vector_manager -> vector_insn_infos [ insn -> uid ( ) ] ; return ; }"
GCC,riscv,444,"Predict the next statement of this code snippet:
 <s> if ( insn -> is_call ( ) || insn -> is_asm ( ) || find_access ( insn -> defs ( ) , VL_REGNUM ) || find_access ( insn -> defs ( ) , VTYPE_REGNUM ) ) info = vector_insn_info :: get_unknown ( ) ;"
GCC,riscv,445,"Predict the next statement of this code snippet:
 <s> if ( info . valid_p ( ) && ! need_vsetvl ( require , info ) ) return ; info = require ;"
GCC,riscv,446,"Predict the next statement of this code snippet:
 <s> if ( info . valid_p ( ) && ! need_vsetvl ( require , info ) ) return ;"
GCC,riscv,447,"Predict the next statement of this code snippet:
 <s> bool uninit_p ( ) const { return m_state == UNINITIALIZED ;"
GCC,riscv,448,"Predict the next statement of this code snippet:
 <s> return m_state == UNINITIALIZED ;"
GCC,riscv,449,"Predict the next statement of this code snippet:
 <s> set_info * set = safe_dyn_cast < set_info * > ( def ) ; set_avl_info ( avl_info ( vl , set ) ) ; set_insn ( insn ) ; return true ; }"
GCC,riscv,450,"Predict the next statement of this code snippet:
 <s> return m_state == VALID || m_state == DIRTY || m_state == DIRTY_WITH_KILLED_AVL ;"
GCC,riscv,451,"Predict the next statement of this code snippet:
 <s> return m_state == VALID ;"
GCC,riscv,452,"Predict the next statement of this code snippet:
 <s> return m_state == VALID ;"
GCC,riscv,453,"Predict the next statement of this code snippet:
 <s> static bool valid_sew_p ( size_t sew ) { return exact_log2 ( sew ) && sew >= <NUM_LIT> && sew <= <NUM_LIT> ;"
GCC,riscv,454,"Predict the next statement of this code snippet:
 <s> return exact_log2 ( sew ) && sew >= <NUM_LIT> && sew <= <NUM_LIT> ;"
GCC,riscv,455,"Predict the next statement of this code snippet:
 <s> static bool vector_config_insn_p ( rtx_insn * rinsn ) {"
GCC,riscv,456,"Predict the next statement of this code snippet:
 <s> static bool vector_config_insn_p ( rtx_insn * rinsn ) {"
GCC,riscv,457,"Predict the next statement of this code snippet:
 <s> for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { vector_block_infos [ bb -> index ( ) ] . local_dem = vector_insn_info ( ) ; vector_block_infos [ bb -> index ( ) ] . reaching_out = vector_insn_info ( ) ; for ( insn_info * insn : bb -> real_insns ( ) ) vector_insn_infos [ insn -> uid ( ) ] . parse_insn ( insn ) ;"
GCC,riscv,458,"Predict the next statement of this code snippet:
 <s> vector_insn_info ( ) : vl_vtype_info ( ) , m_state ( UNINITIALIZED ) , m_demands { false } , m_insn ( nullptr ) {"
GCC,riscv,459,"Predict the next statement of this code snippet:
 <s> vector_insn_info ( ) : vl_vtype_info ( ) , m_state ( UNINITIALIZED ) , m_demands { false } , m_insn ( nullptr ) {"
GCC,riscv,460,"Predict the next statement of this code snippet:
 <s> return ( INSN_CODE ( rinsn ) == CODE_FOR_vlmax_avlsi || INSN_CODE ( rinsn ) == CODE_FOR_vlmax_avldi ) ;"
GCC,riscv,461,"Predict the next statement of this code snippet:
 <s> static bool vlmax_avl_insn_p ( rtx_insn * rinsn ) {"
GCC,riscv,462,"Predict the next statement of this code snippet:
 <s> return x && rtx_equal_p ( x , RVV_VLMAX ) ;"
GCC,riscv,463,"Predict the next statement of this code snippet:
 <s> return calculate_vlmul ( info1 . get_sew ( ) , info2 . get_ratio ( ) ) ;"
GCC,riscv,464,"Predict the next statement of this code snippet:
 <s> vl_vtype_info ( ) : m_avl ( avl_info ( ) ) , m_sew ( <NUM_LIT> ) , m_vlmul ( <STR_LIT> ) , m_ratio ( <NUM_LIT> ) , m_ta ( <NUM_LIT> ) , m_ma ( <NUM_LIT> ) {"
GCC,riscv,465,"Predict the next statement of this code snippet:
 <s> vl_vtype_info ( ) : m_avl ( avl_info ( ) ) , m_sew ( <NUM_LIT> ) , m_vlmul ( <STR_LIT> ) , m_ratio ( <NUM_LIT> ) , m_ta ( <NUM_LIT> ) , m_ma ( <NUM_LIT> ) {"
GCC,riscv,466,"Predict the next statement of this code snippet:
 <s> static bool vsetvl_discard_result_insn_p ( rtx_insn * rinsn ) { if ( ! vector_config_insn_p ( rinsn ) ) return false ; return ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_discard_resultdi || INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_discard_resultsi ) ;"
GCC,riscv,467,"Predict the next statement of this code snippet:
 <s> static bool vsetvl_discard_result_insn_p ( rtx_insn * rinsn ) { if ( ! vector_config_insn_p ( rinsn ) ) return false ; return ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_discard_resultdi || INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_discard_resultsi ) ;"
GCC,riscv,468,"Predict the next statement of this code snippet:
 <s> return ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvldi || INSN_CODE ( rinsn ) == CODE_FOR_vsetvlsi ) ;"
GCC,riscv,469,"Predict the next statement of this code snippet:
 <s> void add_all_one_mask_operand ( machine_mode mode ) { add_input_operand ( CONSTM1_RTX ( mode ) , mode ) ;"
GCC,riscv,470,"Predict the next statement of this code snippet:
 <s> void add_avl_type_operand ( avl_type type ) {"
GCC,riscv,471,"Predict the next statement of this code snippet:
 <s> void add_avl_type_operand ( avl_type type ) {"
GCC,riscv,472,"Predict the next statement of this code snippet:
 <s> rtx tail_policy_rtx = gen_int_mode ( vta , Pmode ) ; rtx mask_policy_rtx = gen_int_mode ( vma , Pmode ) ; add_input_operand ( tail_policy_rtx , Pmode ) ; add_input_operand ( mask_policy_rtx , Pmode ) ;"
GCC,riscv,473,"Predict the next statement of this code snippet:
 <s> void add_policy_operand ( enum tail_policy vta , enum mask_policy vma ) {"
GCC,riscv,474,"Predict the next statement of this code snippet:
 <s> void add_vundef_operand ( machine_mode mode ) {"
GCC,riscv,475,"Predict the next statement of this code snippet:
 <s> void add_vundef_operand ( machine_mode mode ) { add_input_operand ( RVV_VUNDEF ( mode ) , mode ) ;"
GCC,riscv,476,"Predict the next statement of this code snippet:
 <s> unsigned int calculate_ratio ( unsigned int sew , enum vlmul_type vlmul ) { unsigned int ratio ; switch ( vlmul ) { case LMUL_1 : ratio = sew ; break ; case LMUL_2 : ratio = sew / <NUM_LIT> ; break ;"
GCC,riscv,477,"Predict the next statement of this code snippet:
 <s> static unsigned compute_vlmax ( unsigned vector_bits , unsigned elt_size , unsigned min_size ) {"
GCC,riscv,478,"Predict the next statement of this code snippet:
 <s> return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && IN_RANGE ( INTVAL ( elt ) , minval , maxval ) ) ;"
GCC,riscv,479,"Predict the next statement of this code snippet:
 <s> unsigned int sew = get_sew ( vmode ) ;"
GCC,riscv,480,"Predict the next statement of this code snippet:
 <s> void emit_hard_vlmax_vsetvl ( machine_mode vmode , rtx vl ) { unsigned int sew = get_sew ( vmode ) ; emit_insn ( gen_vsetvl ( Pmode , vl , RVV_VLMAX , gen_int_mode ( sew , Pmode ) , gen_int_mode ( get_vlmul ( vmode ) , Pmode ) , const0_rtx , const0_rtx ) ) ;"
GCC,riscv,481,"Predict the next statement of this code snippet:
 <s> void emit_nonvlmax_op ( unsigned icode , rtx dest , rtx src , rtx len , machine_mode mask_mode ) { emit_pred_op ( icode , NULL_RTX , dest , src , len , mask_mode , false ) ;"
GCC,riscv,482,"Predict the next statement of this code snippet:
 <s> emit_pred_op ( icode , NULL_RTX , dest , src , len , mask_mode , false ) ;"
GCC,riscv,483,"Predict the next statement of this code snippet:
 <s> e . add_output_operand ( dest , mode ) ; if ( mask ) e . add_input_operand ( mask , GET_MODE ( mask ) ) ; else e . add_all_one_mask_operand ( mask_mode ) ; e . add_vundef_operand ( mode ) ; e . add_input_operand ( src , GET_MODE ( src ) ) ;"
GCC,riscv,484,"Predict the next statement of this code snippet:
 <s> emit_pred_op ( icode , NULL_RTX , dest , src , len , mask_mode , true ) ;"
GCC,riscv,485,"Predict the next statement of this code snippet:
 <s> void emit_vlmax_op ( unsigned icode , rtx dest , rtx src , rtx len , machine_mode mask_mode ) { emit_pred_op ( icode , NULL_RTX , dest , src , len , mask_mode , true ) ;"
GCC,riscv,486,"Predict the next statement of this code snippet:
 <s> unsigned int ratio = calculate_ratio ( sew , vlmul ) ; if ( ! optimize ) emit_hard_vlmax_vsetvl ( vmode , vl ) ;"
GCC,riscv,487,"Predict the next statement of this code snippet:
 <s> enum vlmul_type vlmul = get_vlmul ( vmode ) ; unsigned int ratio = calculate_ratio ( sew , vlmul ) ; if ( ! optimize ) emit_hard_vlmax_vsetvl ( vmode , vl ) ; else emit_insn ( gen_vlmax_avl ( Pmode , vl , gen_int_mode ( ratio , Pmode ) ) ) ;"
GCC,riscv,488,"Predict the next statement of this code snippet:
 <s> expand_insn ( icode , m_opno , m_ops ) ; }"
GCC,riscv,489,"Predict the next statement of this code snippet:
 <s> void expand ( enum insn_code icode , bool temporary_volatile_p = false ) { if ( temporary_volatile_p ) { temporary_volatile_ok v ( true ) ; expand_insn ( icode , m_opno , m_ops ) ;"
GCC,riscv,490,"Predict the next statement of this code snippet:
 <s> emit_vlmax_op ( code_for_pred_mov ( mode ) , target , src , mask_mode ) ; return ; } rtx elt ; if ( const_vec_duplicate_p ( src , & elt ) ) { rtx tmp = register_operand ( target , mode ) ? target : gen_reg_rtx ( mode ) ; if ( satisfies_constraint_vi ( src ) || satisfies_constraint_Wc0 ( src ) ) emit_vlmax_op ( code_for_pred_mov ( mode ) , tmp , src , mask_mode ) ; else emit_vlmax_op ( code_for_pred_broadcast ( mode ) , tmp , force_reg ( elt_mode , elt ) , mask_mode ) ; if ( tmp != target ) emit_move_insn ( target , tmp ) ; return ;"
GCC,riscv,491,"Predict the next statement of this code snippet:
 <s> if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) { rtx elt ; gcc_assert ( const_vec_duplicate_p ( src , & elt ) && ( rtx_equal_p ( elt , const0_rtx ) || rtx_equal_p ( elt , const1_rtx ) ) ) ; emit_vlmax_op ( code_for_pred_mov ( mode ) , target , src , mask_mode ) ; return ;"
GCC,riscv,492,"Predict the next statement of this code snippet:
 <s> rtx tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_fmt_ee ( GTU , Pmode , avl , const0_rtx ) ) ) ; return tmp ; }"
GCC,riscv,493,"Predict the next statement of this code snippet:
 <s> rtx tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_fmt_ee ( GTU , Pmode , avl , const0_rtx ) ) ) ;"
GCC,riscv,494,"Predict the next statement of this code snippet:
 <s> static rtx gen_no_side_effects_vsetvl_rtx ( machine_mode vmode , rtx vl , rtx avl ) { unsigned int sew = get_sew ( vmode ) ;"
GCC,riscv,495,"Predict the next statement of this code snippet:
 <s> return gen_vsetvl_no_side_effects ( Pmode , vl , avl , gen_int_mode ( sew , Pmode ) , gen_int_mode ( get_vlmul ( vmode ) , Pmode ) , const0_rtx , const0_rtx ) ;"
GCC,riscv,496,"Predict the next statement of this code snippet:
 <s> builder . quick_push ( const1_rtx ) ;"
GCC,riscv,497,"Predict the next statement of this code snippet:
 <s> return gen_int_mode ( type , Pmode ) ;"
GCC,riscv,498,"Predict the next statement of this code snippet:
 <s> int get_ma ( rtx ma ) {"
GCC,riscv,499,"Predict the next statement of this code snippet:
 <s> int get_ma ( rtx ma ) {"
GCC,riscv,500,"Predict the next statement of this code snippet:
 <s> return MASK_ANY ;"
GCC,riscv,501,"Predict the next statement of this code snippet:
 <s> enum mask_policy get_prefer_mask_policy ( ) {"
GCC,riscv,502,"Predict the next statement of this code snippet:
 <s> enum tail_policy get_prefer_tail_policy ( ) { return TAIL_ANY ;"
GCC,riscv,503,"Predict the next statement of this code snippet:
 <s> if ( TARGET_MIN_VLEN == <NUM_LIT> ) return mode_vtype_infos . ratio_for_min_vlen32 [ mode ] ; else return mode_vtype_infos . ratio_for_min_vlen64 [ mode ] ;"
GCC,riscv,504,"Predict the next statement of this code snippet:
 <s> if ( TARGET_MIN_VLEN == <NUM_LIT> ) return mode_vtype_infos . ratio_for_min_vlen32 [ mode ] ; else return mode_vtype_infos . ratio_for_min_vlen64 [ mode ] ;"
GCC,riscv,505,"Predict the next statement of this code snippet:
 <s> static unsigned get_sew ( machine_mode mode ) {"
GCC,riscv,506,"Predict the next statement of this code snippet:
 <s> static unsigned get_sew ( machine_mode mode ) { unsigned int sew = GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? <NUM_LIT> : GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ;"
GCC,riscv,507,"Predict the next statement of this code snippet:
 <s> int get_ta ( rtx ta ) { if ( INTVAL ( ta ) == TAIL_ANY ) return INVALID_ATTRIBUTE ;"
GCC,riscv,508,"Predict the next statement of this code snippet:
 <s> case LMUL_2 : return TARGET_MIN_VLEN * <NUM_LIT> ; case LMUL_4 : return TARGET_MIN_VLEN * <NUM_LIT> ; case LMUL_8 : return TARGET_MIN_VLEN * <NUM_LIT> ; default : gcc_unreachable ( ) ; }"
GCC,riscv,509,"Predict the next statement of this code snippet:
 <s> return TARGET_MIN_VLEN * <NUM_LIT> ; case LMUL_4 : return TARGET_MIN_VLEN * <NUM_LIT> ; case LMUL_8 : return TARGET_MIN_VLEN * <NUM_LIT> ; default :"
GCC,riscv,510,"Predict the next statement of this code snippet:
 <s> if ( inner_mode == E_BImode ) mclass = MODE_VECTOR_BOOL ; else if ( FLOAT_MODE_P ( inner_mode ) ) mclass = MODE_VECTOR_FLOAT ; else mclass = MODE_VECTOR_INT ; machine_mode mode ; FOR_EACH_MODE_IN_CLASS ( mode , mclass ) if ( inner_mode == GET_MODE_INNER ( mode ) && known_eq ( nunits , GET_MODE_NUNITS ( mode ) ) && riscv_v_ext_vector_mode_p ( mode ) ) return mode ;"
GCC,riscv,511,"Predict the next statement of this code snippet:
 <s> if ( TARGET_MIN_VLEN == <NUM_LIT> ) return mode_vtype_infos . vlmul_for_min_vlen32 [ mode ] ; else return mode_vtype_infos . vlmul_for_min_vlen64 [ mode ] ;"
GCC,riscv,512,"Predict the next statement of this code snippet:
 <s> rtx i32vl = NULL_RTX ; if ( CONST_INT_P ( avl ) ) { unsigned elt_size = GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ; unsigned min_size = get_unknown_min_value ( mode ) ; unsigned vlen_max = RVV_65536 ; unsigned vlmax_max = compute_vlmax ( vlen_max , elt_size , min_size ) ; unsigned vlen_min = TARGET_MIN_VLEN ; unsigned vlmax_min = compute_vlmax ( vlen_min , elt_size , min_size ) ; unsigned HOST_WIDE_INT avl_int = INTVAL ( avl ) ; if ( avl_int <= vlmax_min ) i32vl = gen_int_mode ( <NUM_LIT> * avl_int , Pmode ) ; else if ( avl_int >= <NUM_LIT> * vlmax_max ) { i32vl = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_no_side_effects_vsetvl_rtx ( demote_mode , i32vl , RVV_VLMAX ) ) ; } else { } } if ( ! i32vl ) {"
GCC,riscv,513,"Predict the next statement of this code snippet:
 <s> unsigned vlen_max = RVV_65536 ; unsigned vlmax_max = compute_vlmax ( vlen_max , elt_size , min_size ) ; unsigned vlen_min = TARGET_MIN_VLEN ; unsigned vlmax_min = compute_vlmax ( vlen_min , elt_size , min_size ) ; unsigned HOST_WIDE_INT avl_int = INTVAL ( avl ) ; if ( avl_int <= vlmax_min ) i32vl = gen_int_mode ( <NUM_LIT> * avl_int , Pmode ) ; else if ( avl_int >= <NUM_LIT> * vlmax_max ) { i32vl = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_no_side_effects_vsetvl_rtx ( demote_mode , i32vl , RVV_VLMAX ) ) ; } else { } } if ( ! i32vl ) { rtx i64vl = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_no_side_effects_vsetvl_rtx ( mode , i64vl , force_reg ( Pmode , avl ) ) ) ; i32vl = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( i32vl , gen_rtx_ASHIFT ( Pmode , i64vl , const1_rtx ) ) ) ;"
GCC,riscv,514,"Predict the next statement of this code snippet:
 <s> case US_PLUS : case EQ : case NE : case LE : case LEU : case GT : case GTU : return simm5_p ( x ) ; case LT :"
GCC,riscv,515,"Predict the next statement of this code snippet:
 <s> insn_expander ( ) : m_opno ( <NUM_LIT> ) {"
GCC,riscv,516,"Predict the next statement of this code snippet:
 <s> insn_expander ( ) : m_opno ( <NUM_LIT> ) {"
GCC,riscv,517,"Predict the next statement of this code snippet:
 <s> if ( ( known_lt ( GET_MODE_SIZE ( mode ) , BYTES_PER_RISCV_VECTOR ) || GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) && lra_in_progress ) { emit_insn ( gen_mov_lra ( mode , Pmode , dest , src ) ) ; return true ; } if ( known_ge ( GET_MODE_SIZE ( mode ) , BYTES_PER_RISCV_VECTOR ) && GET_MODE_CLASS ( mode ) != MODE_VECTOR_BOOL ) { if ( MEM_P ( dest ) && ! REG_P ( src ) ) src = force_reg ( mode , src ) ; return false ; } if ( register_operand ( src , mode ) && register_operand ( dest , mode ) ) { emit_insn ( gen_rtx_SET ( dest , src ) ) ; return true ; } if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ;"
GCC,riscv,518,"Predict the next statement of this code snippet:
 <s> } if ( known_ge ( GET_MODE_SIZE ( mode ) , BYTES_PER_RISCV_VECTOR ) && GET_MODE_CLASS ( mode ) != MODE_VECTOR_BOOL ) { if ( MEM_P ( dest ) && ! REG_P ( src ) ) src = force_reg ( mode , src ) ; return false ; } if ( register_operand ( src , mode ) && register_operand ( dest , mode ) ) { emit_insn ( gen_rtx_SET ( dest , src ) ) ; return true ; } if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) emit_vlmax_op ( code_for_pred_mov ( mode ) , tmp , src , mask_mode ) ; else emit_move_insn ( tmp , src ) ; src = tmp ; } if ( satisfies_constraint_vu ( src ) ) return false ; emit_vlmax_op ( code_for_pred_mov ( mode ) , dest , src , mask_mode ) ;"
GCC,riscv,519,"Predict the next statement of this code snippet:
 <s> VLMUL_FOR_MIN_VLEN64 , RATIO_FOR_MIN_VLEN64 ) \ vlmul_for_min_vlen32 [ MODE ## mode ] = VLMUL_FOR_MIN_VLEN32 ; \ ratio_for_min_vlen32 [ MODE ## mode ] = RATIO_FOR_MIN_VLEN32 ; \ vlmul_for_min_vlen64 [ MODE ## mode ] = VLMUL_FOR_MIN_VLEN64 ; \ ratio_for_min_vlen64 [ MODE ## mode ] = RATIO_FOR_MIN_VLEN64 ;"
GCC,riscv,520,"Predict the next statement of this code snippet:
 <s> bool neg_simm5_p ( rtx x ) { if ( ! CONST_INT_P ( x ) ) return false ;"
GCC,riscv,521,"Predict the next statement of this code snippet:
 <s> bool neg_simm5_p ( rtx x ) { if ( ! CONST_INT_P ( x ) ) return false ; return IN_RANGE ( INTVAL ( x ) , - <NUM_LIT> , <NUM_LIT> ) ;"
GCC,riscv,522,"Predict the next statement of this code snippet:
 <s> if ( immediate_operand ( * scalar_op , Pmode ) ) { if ( ! rtx_equal_p ( * scalar_op , const0_rtx ) ) * scalar_op = force_reg ( Pmode , * scalar_op ) ; * scalar_op = gen_rtx_SIGN_EXTEND ( scalar_mode , * scalar_op ) ; return false ; } if ( CONST_INT_P ( * scalar_op ) ) * scalar_op = force_reg ( scalar_mode , * scalar_op ) ; rtx tmp = gen_reg_rtx ( vector_mode ) ; <STR_LIT> ( code_for_pred_broadcast ( vector_mode ) , tmp , * scalar_op , vl , mask_mode ) ; emit_vector_func ( operands , tmp ) ; return true ;"
GCC,riscv,523,"Predict the next statement of this code snippet:
 <s> if ( ! CONST_INT_P ( x ) ) return false ; return IN_RANGE ( INTVAL ( x ) , - <NUM_LIT> , <NUM_LIT> ) ;"
GCC,riscv,524,"Predict the next statement of this code snippet:
 <s> if ( ! CONST_INT_P ( x ) ) return false ; return IN_RANGE ( INTVAL ( x ) , - <NUM_LIT> , <NUM_LIT> ) ;"
GCC,riscv,525,"Predict the next statement of this code snippet:
 <s> rtx ma = gen_int_mode ( get_prefer_mask_policy ( ) , Pmode ) ; rtx merge = RVV_VUNDEF ( demote_mode ) ; if ( register_operand ( ops [ <NUM_LIT> ] , mode ) && rtx_equal_p ( ops [ <NUM_LIT> ] , CONSTM1_RTX ( GET_MODE ( ops [ <NUM_LIT> ] ) ) ) ) { merge = gen_lowpart ( demote_mode , ops [ <NUM_LIT> ] ) ; ta = ops [ <NUM_LIT> ] ; ma = ops [ <NUM_LIT> ] ; } emit_insn ( gen_pred_slide ( unspec , demote_mode , temp , CONSTM1_RTX ( demote_mask_mode ) , merge , gen_lowpart ( demote_mode , ops [ <NUM_LIT> ] ) , demote_scalar_op1 , vl_x2 , ta , ma , ops [ <NUM_LIT> ] ) ) ; emit_insn ( gen_pred_slide ( unspec , demote_mode , gen_lowpart ( demote_mode , ops [ <NUM_LIT> ] ) , CONSTM1_RTX ( demote_mask_mode ) , merge , temp , demote_scalar_op2 , vl_x2 , ta , ma , ops [ <NUM_LIT> ] ) ) ;"
GCC,riscv,526,"Predict the next statement of this code snippet:
 <s> } if ( immediate_operand ( scalar_op , Pmode ) ) { ops [ <NUM_LIT> ] = gen_rtx_SIGN_EXTEND ( scalar_mode , force_reg ( Pmode , scalar_op ) ) ; ops [ <NUM_LIT> ] = force_vector_length_operand ( ops [ <NUM_LIT> ] ) ; return false ; } if ( CONST_INT_P ( scalar_op ) ) scalar_op = force_reg ( scalar_mode , scalar_op ) ; rtx vl_x2 = get_vl_x2_rtx ( avl , mode , demote_mode ) ; rtx demote_scalar_op1 , demote_scalar_op2 ; if ( unspec == UNSPEC_VSLIDE1UP ) { demote_scalar_op1 = gen_highpart ( Pmode , scalar_op ) ; demote_scalar_op2 = gen_lowpart ( Pmode , scalar_op ) ; } else { demote_scalar_op1 = gen_lowpart ( Pmode , scalar_op ) ; demote_scalar_op2 = gen_highpart ( Pmode , scalar_op ) ; } rtx temp = gen_reg_rtx ( demote_mode ) ; rtx ta = gen_int_mode ( get_prefer_tail_policy ( ) , Pmode ) ; rtx ma = gen_int_mode ( get_prefer_mask_policy ( ) , Pmode ) ; rtx merge = RVV_VUNDEF ( demote_mode ) ; if ( register_operand ( ops [ <NUM_LIT> ] , mode ) && rtx_equal_p ( ops [ <NUM_LIT> ] , CONSTM1_RTX ( GET_MODE ( ops [ <NUM_LIT> ] ) ) ) ) { merge = gen_lowpart ( demote_mode , ops [ <NUM_LIT> ] ) ;"
GCC,riscv,527,"Predict the next statement of this code snippet:
 <s> mask = <NUM_LIT> ; fmask = <NUM_LIT> ; save_libcall_adjustment = <NUM_LIT> ;"
GCC,riscv,528,"Predict the next statement of this code snippet:
 <s> int n = <NUM_LIT> ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) { return <NUM_LIT> ; } if ( ! riscv_v_ext_vector_mode_p ( mode ) && mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) . to_constant ( ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;"
GCC,riscv,529,"Predict the next statement of this code snippet:
 <s> }"
GCC,riscv,530,"Predict the next statement of this code snippet:
 <s> rtx dwarf = NULL_RTX ; rtx adjust_sp_rtx , reg ; int saved_size = cfun -> machine -> frame . save_libcall_adjustment ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( GET_MODE ( stack_pointer_rtx ) , stack_pointer_rtx , GEN_INT ( saved_size ) ) ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , adjust_sp_rtx , dwarf ) ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { reg = gen_rtx_REG ( SImode , regno ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; }"
GCC,riscv,531,"Predict the next statement of this code snippet:
 <s> reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; insn = gen_rtx_SET ( mem , reg ) ; dwarf = alloc_reg_note ( REG_CFA_OFFSET , insn , dwarf ) ; } adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( GET_MODE ( stack_pointer_rtx ) , stack_pointer_rtx , GEN_INT ( - saved_size ) ) ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , adjust_sp_rtx , dwarf ) ; return dwarf ;"
GCC,riscv,532,"Predict the next statement of this code snippet:
 <s> static int riscv_binary_cost ( rtx x , int single_insns , int double_insns ) { if ( ! riscv_v_ext_vector_mode_p ( GET_MODE ( x ) ) && GET_MODE_SIZE ( GET_MODE ( x ) ) . to_constant ( ) == UNITS_PER_WORD * <NUM_LIT> ) return COSTS_N_INSNS ( double_insns ) ;"
GCC,riscv,533,"Predict the next statement of this code snippet:
 <s> if ( ! riscv_v_ext_vector_mode_p ( GET_MODE ( x ) ) && GET_MODE_SIZE ( GET_MODE ( x ) ) . to_constant ( ) == UNITS_PER_WORD * <NUM_LIT> ) return COSTS_N_INSNS ( double_insns ) ; return COSTS_N_INSNS ( single_insns ) ;"
GCC,riscv,534,"Predict the next statement of this code snippet:
 <s> static void riscv_block_move_loop ( rtx dest , rtx src , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT bytes_per_iter ) { rtx label , src_reg , dest_reg , final_src , test ; unsigned HOST_WIDE_INT leftover ; leftover = length % bytes_per_iter ; length -= leftover ; riscv_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; riscv_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ;"
GCC,riscv,535,"Predict the next statement of this code snippet:
 <s> riscv_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , <NUM_LIT> , <NUM_LIT> , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; riscv_block_move_straight ( dest , src , bytes_per_iter ) ; riscv_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; riscv_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ;"
GCC,riscv,536,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT shifted_val ; shifted_val = ( value << shift ) | ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << shift ) - <NUM_LIT> ) ; alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = LSHIFTRT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } shifted_val = value << shift ; alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = LSHIFTRT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } } if ( ! TARGET_64BIT && ( value > INT32_MAX || value < INT32_MIN ) ) { unsigned HOST_WIDE_INT loval = sext_hwi ( value , <NUM_LIT> ) ; unsigned HOST_WIDE_INT hival = sext_hwi ( ( value - loval ) >> <NUM_LIT> , <NUM_LIT> ) ; struct riscv_integer_op alt_codes [ RISCV_MAX_INTEGER_OPS ] ;"
GCC,riscv,537,"Predict the next statement of this code snippet:
 <s> int leading_ones = clz_hwi ( ~ value ) ; int trailing_ones = ctz_hwi ( ~ value ) ; if ( leading_ones < <NUM_LIT> && ( ( <NUM_LIT> - leading_ones - trailing_ones ) < <NUM_LIT> ) ) { codes [ <NUM_LIT> ] . code = UNKNOWN ; codes [ <NUM_LIT> ] . value = ( ( ( unsigned HOST_WIDE_INT ) value >> trailing_ones ) | ( value << ( <NUM_LIT> - trailing_ones ) ) ) ; codes [ <NUM_LIT> ] . code = ROTATERT ; codes [ <NUM_LIT> ] . value = <NUM_LIT> - trailing_ones ; cost = <NUM_LIT> ; } else { int upper_trailing_ones = ctz_hwi ( ~ value >> <NUM_LIT> ) ; int lower_leading_ones = clz_hwi ( ~ value << <NUM_LIT> ) ; if ( upper_trailing_ones < <NUM_LIT> && lower_leading_ones < <NUM_LIT> && ( ( <NUM_LIT> - upper_trailing_ones - lower_leading_ones ) < <NUM_LIT> ) ) { codes [ <NUM_LIT> ] . code = UNKNOWN ; codes [ <NUM_LIT> ] . value = ( ( value << ( <NUM_LIT> - upper_trailing_ones ) ) | ( ( unsigned HOST_WIDE_INT ) value >> ( <NUM_LIT> + upper_trailing_ones ) ) ) ; codes [ <NUM_LIT> ] . code = ROTATERT ; codes [ <NUM_LIT> ] . value = <NUM_LIT> - upper_trailing_ones ; cost = <NUM_LIT> ; }"
GCC,riscv,538,"Predict the next statement of this code snippet:
 <s> subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) if ( GET_CODE ( * iter ) == CONST_POLY_INT ) return true ; if ( GET_CODE ( x ) == HIGH ) return true ; split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > <NUM_LIT> ) return true ; if ( flag_pic ) return true ; } if ( tls_referenced_p ( x ) ) return true ;"
GCC,riscv,539,"Predict the next statement of this code snippet:
 <s> return ( reload_completed && known_eq ( cfun -> machine -> frame . total_size , <NUM_LIT> ) && ! cfun -> machine -> interrupt_handler_p ) ;"
GCC,riscv,540,"Predict the next statement of this code snippet:
 <s> switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ;"
GCC,riscv,541,"Predict the next statement of this code snippet:
 <s> if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; info -> symbol_type = riscv_classify_symbolic_expression ( info -> offset ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_lo_sum_p ( info -> symbol_type , mode , info -> offset ) ) ; case CONST_INT : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ;"
GCC,riscv,542,"Predict the next statement of this code snippet:
 <s> if ( reg_class_subset_p ( rclass , GR_REGS ) ) return riscv_hard_regno_nregs ( GP_REG_FIRST , mode ) ;"
GCC,riscv,543,"Predict the next statement of this code snippet:
 <s> sbitmap components = sbitmap_alloc ( FIRST_PSEUDO_REGISTER ) ; bitmap_clear ( components ) ; function_abi_aggregator callee_abis ; rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( CALL_P ( insn ) ) callee_abis . note_callee_abi ( insn_callee_abi ( insn ) ) ; HARD_REG_SET extra_caller_saves = callee_abis . caller_save_regs ( * crtl -> abi ) ; for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) bitmap_set_bit ( components , regno ) ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) bitmap_set_bit ( components , regno ) ;"
GCC,riscv,544,"Predict the next statement of this code snippet:
 <s> for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) bitmap_set_bit ( components , regno ) ; return components ;"
GCC,riscv,545,"Predict the next statement of this code snippet:
 <s> if ( ! cfun -> machine -> naked_p ) { for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) || ( interrupt_save_prologue_temp && ( regno == RISCV_PROLOGUE_TEMP_REGNUM ) ) ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( crtl -> calls_eh_return ) for ( i = <NUM_LIT> ; ( regno = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( TARGET_HARD_FLOAT ) for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) ) frame -> fmask |= <NUM_LIT> << ( regno - FP_REG_FIRST ) , num_f_saved ++ ;"
GCC,riscv,546,"Predict the next statement of this code snippet:
 <s> if ( riscv_abi == ABI_ILP32E ) { for ( int r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) call_used_regs [ r ] = <NUM_LIT> ; } if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = <NUM_LIT> ; } if ( UNITS_PER_FP_ARG == <NUM_LIT> ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = <NUM_LIT> ; }"
GCC,riscv,547,"Predict the next statement of this code snippet:
 <s> for ( int r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) fixed_regs [ r ] = <NUM_LIT> ; } if ( riscv_abi == ABI_ILP32E ) { for ( int r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) call_used_regs [ r ] = <NUM_LIT> ; } if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = <NUM_LIT> ; } if ( UNITS_PER_FP_ARG == <NUM_LIT> ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = <NUM_LIT> ; }"
GCC,riscv,548,"Predict the next statement of this code snippet:
 <s> static poly_uint16 riscv_convert_vector_bits ( void ) { if ( TARGET_MIN_VLEN > <NUM_LIT> ) { riscv_bytes_per_vector_chunk = <NUM_LIT> ; } else {"
GCC,riscv,549,"Predict the next statement of this code snippet:
 <s> static void riscv_disqualify_components ( sbitmap , edge , sbitmap , bool ) {"
GCC,riscv,550,"Predict the next statement of this code snippet:
 <s> static void riscv_disqualify_components ( sbitmap , edge , sbitmap , bool ) {"
GCC,riscv,551,"Predict the next statement of this code snippet:
 <s> if ( startswith ( s -> named . name , <STR_LIT> ) ) { char * name = ( char * ) alloca ( strlen ( s -> named . name ) + <NUM_LIT> ) ; sprintf ( name , <STR_LIT> , s -> named . name + <NUM_LIT> ) ; return get_section ( name , s -> named . common . flags , NULL ) ; } if ( s == data_section ) return sdata_section ; } return s ;"
GCC,riscv,552,"Predict the next statement of this code snippet:
 <s> static section * riscv_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { section * s = default_elf_select_rtx_section ( mode , x , align ) ;"
GCC,riscv,553,"Predict the next statement of this code snippet:
 <s> static void riscv_emit_epilogue_components ( sbitmap components ) { riscv_process_components ( components , false ) ;"
GCC,riscv,554,"Predict the next statement of this code snippet:
 <s> rtx tmp0 , tmp1 , cmp_op0 = * op0 , cmp_op1 = * op1 ; enum rtx_code fp_code = * code ; * code = NE ; switch ( fp_code ) { case UNORDERED : * code = EQ ; case ORDERED : tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; case UNEQ : * code = EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == HFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quiethfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == HFmode ) \ emit_insn ( gen_f ## CMP ## _quiethfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; break ; case LTGT : tmp0 = riscv_force_binary ( word_mode , LT , cmp_op0 , cmp_op1 ) ; tmp1 = riscv_force_binary ( word_mode , GT , cmp_op0 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , IOR , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ;"
GCC,riscv,555,"Predict the next statement of this code snippet:
 <s> * code = EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == HFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quiethfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == HFmode ) \ emit_insn ( gen_f ## CMP ## _quiethfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ;"
GCC,riscv,556,"Predict the next statement of this code snippet:
 <s> if ( ! riscv_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; riscv_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == <NUM_LIT> ) { rtx inv_target = riscv_force_binary ( word_mode , inv_code , cmp0 , cmp1 ) ; riscv_emit_binary ( EQ , target , inv_target , const0_rtx ) ;"
GCC,riscv,557,"Predict the next statement of this code snippet:
 <s> static void riscv_emit_prologue_components ( sbitmap components ) { riscv_process_components ( components , true ) ;"
GCC,riscv,558,"Predict the next statement of this code snippet:
 <s> riscv_process_components ( components , true ) ;"
GCC,riscv,559,"Predict the next statement of this code snippet:
 <s> case EXCESS_PRECISION_TYPE_STANDARD : return ( ( TARGET_ZFH || TARGET_ZHINX ) ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ) ; case EXCESS_PRECISION_TYPE_IMPLICIT : case EXCESS_PRECISION_TYPE_FLOAT16 :"
GCC,riscv,560,"Predict the next statement of this code snippet:
 <s> case EXCESS_PRECISION_TYPE_FAST : case EXCESS_PRECISION_TYPE_STANDARD : return ( ( TARGET_ZFH || TARGET_ZHINX ) ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ) ; case EXCESS_PRECISION_TYPE_IMPLICIT : case EXCESS_PRECISION_TYPE_FLOAT16 : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 ;"
GCC,riscv,561,"Predict the next statement of this code snippet:
 <s> if ( TARGET_XTHEADCONDMOV && GET_MODE_CLASS ( mode ) == MODE_INT && reg_or_0_operand ( cons , mode ) && reg_or_0_operand ( alt , mode ) && GET_MODE ( op ) == mode && GET_MODE ( op0 ) == mode && GET_MODE ( op1 ) == mode && ( code == EQ || code == NE ) ) { riscv_expand_conditional_move_onesided ( dest , cons , alt , code , op0 , op1 ) ; return true ; } else if ( TARGET_SFB_ALU && mode == word_mode ) { riscv_emit_int_compare ( & code , & op0 , & op1 ) ; rtx cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) ;"
GCC,riscv,562,"Predict the next statement of this code snippet:
 <s> gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT ) ; gcc_assert ( reg_or_0_operand ( cons , mode ) ) ; gcc_assert ( reg_or_0_operand ( alt , mode ) ) ; riscv_emit_int_compare ( & code , & op0 , & op1 , true ) ; rtx cond = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; rtx tmp1 = gen_reg_rtx ( mode ) ; rtx tmp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( tmp1 , gen_rtx_IF_THEN_ELSE ( mode , cond , cons , const0_rtx ) ) ) ; cond = gen_rtx_fmt_ee ( ( code == EQ ) ? NE : EQ , mode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( tmp2 , gen_rtx_IF_THEN_ELSE ( mode , cond , alt , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IOR ( mode , tmp1 , tmp2 ) ) ) ;"
GCC,riscv,563,"Predict the next statement of this code snippet:
 <s> machine_mode mode = GET_MODE ( dest ) ; gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT ) ; gcc_assert ( reg_or_0_operand ( cons , mode ) ) ; gcc_assert ( reg_or_0_operand ( alt , mode ) ) ; riscv_emit_int_compare ( & code , & op0 , & op1 , true ) ; rtx cond = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ;"
GCC,riscv,564,"Predict the next statement of this code snippet:
 <s> rtx ra = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx insn ; bool need_barrier_p = known_ne ( get_frame_size ( ) + cfun -> machine -> frame . arg_pointer_offset , <NUM_LIT> ) ; if ( cfun -> machine -> naked_p ) { gcc_assert ( style == NORMAL_RETURN ) ; emit_jump_insn ( gen_return ( ) ) ; return ; } if ( ( style == NORMAL_RETURN ) && riscv_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } epilogue_cfa_sp_offset = <NUM_LIT> ; if ( cfun -> calls_alloca ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; poly_int64 adjust_offset = - frame -> hard_frame_pointer_offset ; rtx adjust = NULL_RTX ; if ( ! adjust_offset . is_constant ( ) ) { rtx tmp1 = RISCV_PROLOGUE_TEMP ( Pmode ) ; rtx tmp2 = RISCV_PROLOGUE_TEMP2 ( Pmode ) ; riscv_legitimize_poly_move ( Pmode , tmp1 , tmp2 , gen_int_mode ( adjust_offset , Pmode ) ) ; adjust = tmp1 ; } else { if ( ! SMALL_OPERAND ( adjust_offset . to_constant ( ) ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( adjust_offset . to_constant ( ) ) ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } else adjust = GEN_INT ( adjust_offset . to_constant ( ) ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_value = gen_rtx_PLUS ( Pmode , hard_frame_pointer_rtx , gen_int_mode ( - frame -> hard_frame_pointer_offset , Pmode ) ) ; rtx cfa_adjust_rtx = gen_rtx_SET ( stack_pointer_rtx , cfa_adjust_value ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { step2 = riscv_first_stack_step ( frame ) ; step1 -= step2 ; } if ( known_gt ( step1 , <NUM_LIT> ) ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; if ( ! step1 . is_constant ( ) ) { poly_int64 scalable_frame = step1 ; scalable_frame . coeffs [ <NUM_LIT> ] = step1 . coeffs [ <NUM_LIT> ] ; riscv_v_adjust_scalable_frame ( stack_pointer_rtx , scalable_frame , true ) ; step1 -= scalable_frame ; } if ( step1 . to_constant ( ) != <NUM_LIT> ) { rtx adjust = GEN_INT ( step1 . to_constant ( ) ) ; if ( ! SMALL_OPERAND ( step1 . to_constant ( ) ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;"
GCC,riscv,565,"Predict the next statement of this code snippet:
 <s> rtx insn ; bool need_barrier_p = known_ne ( get_frame_size ( ) + cfun -> machine -> frame . arg_pointer_offset , <NUM_LIT> ) ; if ( cfun -> machine -> naked_p ) { gcc_assert ( style == NORMAL_RETURN ) ; emit_jump_insn ( gen_return ( ) ) ; return ; } if ( ( style == NORMAL_RETURN ) && riscv_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } epilogue_cfa_sp_offset = <NUM_LIT> ; if ( cfun -> calls_alloca ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; poly_int64 adjust_offset = - frame -> hard_frame_pointer_offset ; rtx adjust = NULL_RTX ; if ( ! adjust_offset . is_constant ( ) ) { rtx tmp1 = RISCV_PROLOGUE_TEMP ( Pmode ) ; rtx tmp2 = RISCV_PROLOGUE_TEMP2 ( Pmode ) ; riscv_legitimize_poly_move ( Pmode , tmp1 , tmp2 , gen_int_mode ( adjust_offset , Pmode ) ) ; adjust = tmp1 ; } else { if ( ! SMALL_OPERAND ( adjust_offset . to_constant ( ) ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( adjust_offset . to_constant ( ) ) ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } else adjust = GEN_INT ( adjust_offset . to_constant ( ) ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_value = gen_rtx_PLUS ( Pmode , hard_frame_pointer_rtx , gen_int_mode ( - frame -> hard_frame_pointer_offset , Pmode ) ) ; rtx cfa_adjust_rtx = gen_rtx_SET ( stack_pointer_rtx , cfa_adjust_value ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { step2 = riscv_first_stack_step ( frame ) ; step1 -= step2 ; } if ( known_gt ( step1 , <NUM_LIT> ) ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; if ( ! step1 . is_constant ( ) ) {"
GCC,riscv,566,"Predict the next statement of this code snippet:
 <s> static void riscv_expand_mult_with_const_int ( machine_mode mode , rtx dest , rtx multiplicand , int multiplier ) { if ( multiplier == <NUM_LIT> ) { riscv_emit_move ( dest , GEN_INT ( <NUM_LIT> ) ) ; return ; } bool neg_p = multiplier < <NUM_LIT> ; int multiplier_abs = abs ( multiplier ) ; if ( multiplier_abs == <NUM_LIT> ) { if ( neg_p ) riscv_expand_op ( NEG , mode , dest , multiplicand , NULL_RTX ) ; else riscv_emit_move ( dest , multiplicand ) ; } else { if ( pow2p_hwi ( multiplier_abs ) ) { riscv_expand_op ( ASHIFT , mode , dest , multiplicand , gen_int_mode ( exact_log2 ( multiplier_abs ) , QImode ) ) ; if ( neg_p ) riscv_expand_op ( NEG , mode , dest , dest , NULL_RTX ) ; } else if ( pow2p_hwi ( multiplier_abs + <NUM_LIT> ) ) { riscv_expand_op ( ASHIFT , mode , dest , multiplicand , gen_int_mode ( exact_log2 ( multiplier_abs + <NUM_LIT> ) , QImode ) ) ; if ( neg_p ) riscv_expand_op ( MINUS , mode , dest , multiplicand , dest ) ; else riscv_expand_op ( MINUS , mode , dest , dest , multiplicand ) ; } else if ( pow2p_hwi ( multiplier - <NUM_LIT> ) ) { riscv_expand_op ( ASHIFT , mode , dest , multiplicand , gen_int_mode ( exact_log2 ( multiplier_abs - <NUM_LIT> ) , QImode ) ) ; riscv_expand_op ( PLUS , mode , dest , dest , multiplicand ) ; if ( neg_p ) riscv_expand_op ( NEG , mode , dest , dest , NULL_RTX ) ; } else { gcc_assert ( TARGET_MUL && <STR_LIT> <STR_LIT> ) ; riscv_emit_move ( dest , gen_int_mode ( multiplier , mode ) ) ; riscv_expand_op ( MULT , mode , dest , dest , multiplicand ) ; } }"
GCC,riscv,567,"Predict the next statement of this code snippet:
 <s> if ( GET_RTX_CLASS ( code ) == RTX_UNARY ) result = expand_simple_unop ( mode , code , op1 , NULL_RTX , false ) ; else result = expand_simple_binop ( mode , code , op1 , op2 , NULL_RTX , false , OPTAB_DIRECT ) ; riscv_emit_move ( op0 , result ) ; } else { rtx pat ; if ( GET_RTX_CLASS ( code ) == RTX_UNARY ) pat = gen_rtx_fmt_e ( code , mode , op1 ) ;"
GCC,riscv,568,"Predict the next statement of this code snippet:
 <s> riscv_emit_move ( op0 , result ) ; } else { rtx pat ; if ( GET_RTX_CLASS ( code ) == RTX_UNARY ) pat = gen_rtx_fmt_e ( code , mode , op1 ) ; else pat = gen_rtx_fmt_ee ( code , mode , op1 , op2 ) ; emit_insn ( gen_rtx_SET ( op0 , pat ) ) ; }"
GCC,riscv,569,"Predict the next statement of this code snippet:
 <s> rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( riscv_gen_gpr_save_insn ( frame ) ) ; frame -> mask = <NUM_LIT> ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = riscv_first_stack_step ( frame ) ; if ( size . is_constant ( ) ) step1 = MIN ( size . to_constant ( ) , step1 ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg , false , false ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( ( frame -> hard_frame_pointer_offset - size ) . to_constant ( ) ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; riscv_emit_stack_tie ( ) ; } if ( known_gt ( size , <NUM_LIT> ) ) { poly_int64 scalable_frame ( <NUM_LIT> , <NUM_LIT> ) ; if ( ! size . is_constant ( ) ) {"
GCC,riscv,570,"Predict the next statement of this code snippet:
 <s> riscv_emit_stack_tie ( ) ; } if ( known_gt ( size , <NUM_LIT> ) ) { poly_int64 scalable_frame ( <NUM_LIT> , <NUM_LIT> ) ; if ( ! size . is_constant ( ) ) { poly_int64 scalable_frame = size ; scalable_frame . coeffs [ <NUM_LIT> ] = size . coeffs [ <NUM_LIT> ] ; riscv_v_adjust_scalable_frame ( stack_pointer_rtx , scalable_frame , false ) ; size -= scalable_frame ; } HOST_WIDE_INT constant_frame = size . to_constant ( ) ; if ( constant_frame == <NUM_LIT> ) return ; if ( SMALL_OPERAND ( - constant_frame ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - constant_frame ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; } else { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - constant_frame ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , RISCV_PROLOGUE_TEMP ( Pmode ) ) ) ;"
GCC,riscv,571,"Predict the next statement of this code snippet:
 <s> if ( unsigned_condition ( code ) == code && ( GET_MODE ( * op0 ) == QImode && ! ( GET_CODE ( * op0 ) == SUBREG && SUBREG_PROMOTED_VAR_P ( * op0 ) && SUBREG_PROMOTED_SIGNED_P ( * op0 ) && ( CONST_INT_P ( * op1 ) || ( GET_CODE ( * op1 ) == SUBREG && SUBREG_PROMOTED_VAR_P ( * op1 ) && SUBREG_PROMOTED_SIGNED_P ( * op1 ) ) ) ) ) ) { * op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ; if ( CONST_INT_P ( * op1 ) ) * op1 = GEN_INT ( ( uint8_t ) INTVAL ( * op1 ) ) ; else * op1 = gen_rtx_ZERO_EXTEND ( word_mode , * op1 ) ; } else { * op0 = gen_rtx_SIGN_EXTEND ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = gen_rtx_SIGN_EXTEND ( word_mode , * op1 ) ;"
GCC,riscv,572,"Predict the next statement of this code snippet:
 <s> fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT> ) ) ; if ( ! riscv_mrelax ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( riscv_mcsr_check ) fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,riscv,573,"Predict the next statement of this code snippet:
 <s> if ( ! SMALL_OPERAND ( min_second_step ) && frame_total_constant_size % IMM_REACH < IMM_REACH / <NUM_LIT> && frame_total_constant_size % IMM_REACH >= min_first_step ) return frame_total_constant_size % IMM_REACH ; if ( TARGET_RVC ) { if ( IN_RANGE ( min_second_step , <NUM_LIT> , ( TARGET_64BIT ? SDSP_REACH : SWSP_REACH ) ) ) return MAX ( min_second_step , min_first_step ) ; else if ( ! SMALL_OPERAND ( min_second_step ) ) return min_first_step ; }"
GCC,riscv,574,"Predict the next statement of this code snippet:
 <s> else frame_total_constant_size = frame -> total_size . to_constant ( ) ; if ( SMALL_OPERAND ( frame_total_constant_size ) ) return frame_total_constant_size ; HOST_WIDE_INT min_first_step = RISCV_STACK_ALIGN ( ( frame -> total_size - frame -> frame_pointer_offset ) . to_constant ( ) ) ; HOST_WIDE_INT max_first_step = IMM_REACH / <NUM_LIT> - PREFERRED_STACK_BOUNDARY / <NUM_LIT> ; HOST_WIDE_INT min_second_step = frame_total_constant_size - max_first_step ; gcc_assert ( min_first_step <= max_first_step ) ; if ( ! SMALL_OPERAND ( min_second_step ) && frame_total_constant_size % IMM_REACH < IMM_REACH / <NUM_LIT> && frame_total_constant_size % IMM_REACH >= min_first_step ) return frame_total_constant_size % IMM_REACH ; if ( TARGET_RVC ) { if ( IN_RANGE ( min_second_step , <NUM_LIT> , ( TARGET_64BIT ? SDSP_REACH : SWSP_REACH ) ) ) return MAX ( min_second_step , min_first_step ) ; else if ( ! SMALL_OPERAND ( min_second_step ) ) return min_first_step ; }"
GCC,riscv,575,"Predict the next statement of this code snippet:
 <s> if ( ignore_zero_width_bit_field_p && DECL_BIT_FIELD ( f ) && ( DECL_SIZE ( f ) == NULL_TREE || integer_zerop ( DECL_SIZE ( f ) ) ) ) ; else { HOST_WIDE_INT pos = offset + int_byte_position ( f ) ; n = riscv_flatten_aggregate_field ( TREE_TYPE ( f ) , fields , n , pos , ignore_zero_width_bit_field_p ) ; } if ( n < <NUM_LIT> ) return - <NUM_LIT> ; } return n ; case ARRAY_TYPE : { HOST_WIDE_INT n_elts ; riscv_aggregate_field subfields [ <NUM_LIT> ] ; tree index = TYPE_DOMAIN ( type ) ; tree elt_size = TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) ; int n_subfields = riscv_flatten_aggregate_field ( TREE_TYPE ( type ) , subfields , <NUM_LIT> , offset , ignore_zero_width_bit_field_p ) ; if ( n_subfields <= <NUM_LIT> || ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || ! tree_fits_uhwi_p ( elt_size ) ) return - <NUM_LIT> ; n_elts = <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ; gcc_assert ( n_elts >= <NUM_LIT> ) ; for ( HOST_WIDE_INT i = <NUM_LIT> ; i < n_elts ; i ++ ) for ( int j = <NUM_LIT> ; j < n_subfields ; j ++ ) { if ( n >= <NUM_LIT> ) return - <NUM_LIT> ; fields [ n ] = subfields [ j ] ;"
GCC,riscv,576,"Predict the next statement of this code snippet:
 <s> bool load_p = ( fn == riscv_restore_reg ) ; rtx operands [ <NUM_LIT> ] ; th_mempair_prepare_save_restore_operands ( operands , load_p , word_mode , regno , offset , regno2 , offset2 ) ; if ( th_mempair_operands_p ( operands , load_p , word_mode ) ) { th_mempair_save_restore_regs ( operands , load_p , word_mode ) ; offset = offset2 ; regno = regno2 ; continue ; } } } riscv_save_restore_reg ( word_mode , regno , offset , fn ) ; } offset = ( cfun -> machine -> frame . fp_sp_offset - sp_offset ) . to_constant ( ) ;"
GCC,riscv,577,"Predict the next statement of this code snippet:
 <s> } } } riscv_save_restore_reg ( word_mode , regno , offset , fn ) ; } offset = ( cfun -> machine -> frame . fp_sp_offset - sp_offset ) . to_constant ( ) ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { bool handle_reg = ! cfun -> machine -> reg_is_wrapped_separately [ regno ] ; machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; if ( handle_reg ) riscv_save_restore_reg ( mode , regno , offset , fn ) ;"
GCC,riscv,578,"Predict the next statement of this code snippet:
 <s> gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno ) ; case MODE_COMPLEX_FLOAT : return riscv_pass_fpr_pair ( mode , fregno , GET_MODE_INNER ( mode ) , <NUM_LIT> , fregno + <NUM_LIT> , GET_MODE_INNER ( mode ) , GET_MODE_UNIT_SIZE ( mode ) ) ; default : gcc_unreachable ( ) ; } if ( riscv_pass_aggregate_in_fpr_and_gpr_p ( type , fields ) && info -> gpr_offset < MAX_ARGS_IN_REGISTERS && info -> fpr_offset < MAX_ARGS_IN_REGISTERS ) { info -> num_gprs = <NUM_LIT> ; info -> num_fprs = <NUM_LIT> ; if ( ! SCALAR_FLOAT_TYPE_P ( fields [ <NUM_LIT> ] . type ) ) std :: swap ( fregno , gregno ) ; return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , gregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ;"
GCC,riscv,579,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT offset ; sbitmap components = sbitmap_alloc ( FIRST_PSEUDO_REGISTER ) ; bitmap_clear ( components ) ; if ( riscv_use_save_libcall ( & cfun -> machine -> frame ) || cfun -> machine -> interrupt_handler_p || ! cfun -> machine -> frame . gp_sp_offset . is_constant ( ) ) return components ; offset = cfun -> machine -> frame . gp_sp_offset . to_constant ( ) ;"
GCC,riscv,580,"Predict the next statement of this code snippet:
 <s> } offset = cfun -> machine -> frame . fp_sp_offset . to_constant ( ) ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; if ( SMALL_OPERAND ( offset ) ) bitmap_set_bit ( components , regno ) ; offset -= GET_MODE_SIZE ( mode ) . to_constant ( ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; bitmap_clear_bit ( components , RETURN_ADDR_REGNUM ) ; return components ;"
GCC,riscv,581,"Predict the next statement of this code snippet:
 <s> } else if ( FP_REG_P ( regno ) ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; if ( ! FP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ; if ( GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_REG || ( ! call_used_or_fixed_reg_p ( regno ) && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_ARG ) ) return false ; } else if ( V_REG_P ( regno ) ) { if ( ! riscv_v_ext_vector_mode_p ( mode ) ) return false ; if ( ! V_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; int lmul = <NUM_LIT> ; if ( known_gt ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) ) lmul = exact_div ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) . to_constant ( ) ; if ( lmul != <NUM_LIT> ) return ( ( regno % lmul ) == <NUM_LIT> ) ; } else if ( regno == VL_REGNUM || regno == VTYPE_REGNUM ) return true ; else return false ; for ( unsigned i = <NUM_LIT> ; i < nregs ; i ++ ) if ( call_used_or_fixed_reg_p ( regno ) != call_used_or_fixed_reg_p ( regno + i ) ) return false ; if ( ! TARGET_64BIT && TARGET_ZDINX ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_UNIT_SIZE ( mode ) == GET_MODE_SIZE ( DFmode ) ) return ! ( regno & <NUM_LIT> ) ; }"
GCC,riscv,582,"Predict the next statement of this code snippet:
 <s> if ( known_gt ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) ) lmul = exact_div ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) . to_constant ( ) ; if ( lmul != <NUM_LIT> ) return ( ( regno % lmul ) == <NUM_LIT> ) ; } else if ( regno == VL_REGNUM || regno == VTYPE_REGNUM ) return true ; else return false ; for ( unsigned i = <NUM_LIT> ; i < nregs ; i ++ ) if ( call_used_or_fixed_reg_p ( regno ) != call_used_or_fixed_reg_p ( regno + i ) ) return false ; if ( ! TARGET_64BIT && TARGET_ZDINX ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_UNIT_SIZE ( mode ) == GET_MODE_SIZE ( DFmode ) ) return ! ( regno & <NUM_LIT> ) ; } return true ;"
GCC,riscv,583,"Predict the next statement of this code snippet:
 <s> if ( riscv_v_ext_vector_mode_p ( mode ) ) { if ( maybe_lt ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) ) return <NUM_LIT> ; return exact_div ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) . to_constant ( ) ; } if ( regno == VTYPE_REGNUM || regno == VL_REGNUM ) return <NUM_LIT> ; if ( V_REG_P ( regno ) ) return <NUM_LIT> ; if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) . to_constant ( ) + UNITS_PER_FP_REG - <NUM_LIT> ) / UNITS_PER_FP_REG ; return ( GET_MODE_SIZE ( mode ) . to_constant ( ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;"
GCC,riscv,584,"Predict the next statement of this code snippet:
 <s> poly_int64 src , dest ; riscv_compute_frame_info ( ) ; if ( to == HARD_FRAME_POINTER_REGNUM ) dest = cfun -> machine -> frame . hard_frame_pointer_offset ; else if ( to == STACK_POINTER_REGNUM ) dest = <NUM_LIT> ; else gcc_unreachable ( ) ; if ( from == FRAME_POINTER_REGNUM ) src = cfun -> machine -> frame . frame_pointer_offset ; else if ( from == ARG_POINTER_REGNUM ) src = cfun -> machine -> frame . arg_pointer_offset ; else gcc_unreachable ( ) ; return src - dest ;"
GCC,riscv,585,"Predict the next statement of this code snippet:
 <s> if ( from == FRAME_POINTER_REGNUM ) src = cfun -> machine -> frame . frame_pointer_offset ;"
GCC,riscv,586,"Predict the next statement of this code snippet:
 <s> set_optab_libfunc ( smul_optab , HFmode , NULL ) ; set_optab_libfunc ( neg_optab , HFmode , NULL ) ; set_optab_libfunc ( sub_optab , HFmode , NULL ) ; set_optab_libfunc ( eq_optab , HFmode , NULL ) ; set_optab_libfunc ( ne_optab , HFmode , NULL ) ; set_optab_libfunc ( lt_optab , HFmode , NULL ) ; set_optab_libfunc ( le_optab , HFmode , NULL ) ;"
GCC,riscv,587,"Predict the next statement of this code snippet:
 <s> if ( ! crtl -> calls_eh_return ) return false ; for ( i = <NUM_LIT> ; ( regnum = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) if ( regno == regnum ) { return true ; } return false ;"
GCC,riscv,588,"Predict the next statement of this code snippet:
 <s> return true ; } poly_int64 value = rtx_to_poly_int64 ( src ) ; if ( ! value . is_constant ( ) && ! TARGET_VECTOR ) { riscv_report_v_required ( ) ; return false ; } if ( satisfies_constraint_vp ( src ) ) return false ; if ( GET_MODE_SIZE ( mode ) . to_constant ( ) < GET_MODE_SIZE ( Pmode ) ) { rtx tmp = gen_reg_rtx ( Pmode ) ; riscv_legitimize_poly_move ( Pmode , gen_lowpart ( Pmode , dest ) , tmp , src ) ; } else { rtx tmp = gen_reg_rtx ( mode ) ; riscv_legitimize_poly_move ( mode , dest , tmp , src ) ; } return true ; } if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) . to_constant ( ) < UNITS_PER_WORD && can_create_pseudo_p ( ) && MEM_P ( src ) ) { rtx temp_reg ; int zero_extend_p ; temp_reg = gen_reg_rtx ( word_mode ) ; zero_extend_p = ( LOAD_EXTEND_OP ( mode ) == ZERO_EXTEND ) ; emit_insn ( gen_extend_insn ( temp_reg , src , word_mode , mode , zero_extend_p ) ) ; riscv_emit_move ( dest , gen_lowpart ( mode , temp_reg ) ) ; return true ; } if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { rtx reg ; if ( GET_CODE ( src ) == CONST_INT ) { machine_mode promoted_mode = mode ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) . to_constant ( ) < UNITS_PER_WORD ) promoted_mode = word_mode ; if ( splittable_const_int_operand ( src , mode ) ) { reg = gen_reg_rtx ( promoted_mode ) ; riscv_move_integer ( reg , reg , INTVAL ( src ) , mode , FALSE ) ; } else reg = force_reg ( promoted_mode , src ) ; if ( promoted_mode != mode ) reg = gen_lowpart ( mode , reg ) ; } else reg = force_reg ( mode , src ) ; riscv_emit_move ( dest , reg ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { riscv_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } if ( MEM_P ( dest ) && ! riscv_legitimate_address_p ( mode , XEXP ( dest , <NUM_LIT> ) , reload_completed ) ) { XEXP ( dest , <NUM_LIT> ) = riscv_force_address ( XEXP ( dest , <NUM_LIT> ) , mode ) ; } if ( MEM_P ( src ) && ! riscv_legitimate_address_p ( mode , XEXP ( src , <NUM_LIT> ) , reload_completed ) ) { XEXP ( src , <NUM_LIT> ) = riscv_force_address ( XEXP ( src , <NUM_LIT> ) , mode ) ;"
GCC,riscv,589,"Predict the next statement of this code snippet:
 <s> int zero_extend_p ; temp_reg = gen_reg_rtx ( word_mode ) ; zero_extend_p = ( LOAD_EXTEND_OP ( mode ) == ZERO_EXTEND ) ; emit_insn ( gen_extend_insn ( temp_reg , src , word_mode , mode , zero_extend_p ) ) ; riscv_emit_move ( dest , gen_lowpart ( mode , temp_reg ) ) ; return true ; } if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { rtx reg ; if ( GET_CODE ( src ) == CONST_INT ) { machine_mode promoted_mode = mode ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) . to_constant ( ) < UNITS_PER_WORD ) promoted_mode = word_mode ; if ( splittable_const_int_operand ( src , mode ) ) { reg = gen_reg_rtx ( promoted_mode ) ; riscv_move_integer ( reg , reg , INTVAL ( src ) , mode , FALSE ) ; } else reg = force_reg ( promoted_mode , src ) ; if ( promoted_mode != mode ) reg = gen_lowpart ( mode , reg ) ; } else reg = force_reg ( mode , src ) ;"
GCC,riscv,590,"Predict the next statement of this code snippet:
 <s> int div_factor = <NUM_LIT> ; emit_move_insn ( tmp , gen_int_mode ( BYTES_PER_RISCV_VECTOR , mode ) ) ; if ( BYTES_PER_RISCV_VECTOR . is_constant ( ) ) { gcc_assert ( value . is_constant ( ) ) ; riscv_emit_move ( dest , GEN_INT ( value . to_constant ( ) ) ) ; return ; } else if ( ( factor % vlenb ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else if ( ( factor % ( vlenb / <NUM_LIT> ) ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else if ( ( factor % ( vlenb / <NUM_LIT> ) ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else if ( ( factor % ( vlenb / <NUM_LIT> ) ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else gcc_unreachable ( ) ; if ( div_factor != <NUM_LIT> ) riscv_expand_op ( LSHIFTRT , mode , tmp , tmp , gen_int_mode ( exact_log2 ( div_factor ) , QImode ) ) ; riscv_expand_mult_with_const_int ( mode , dest , tmp , factor / ( vlenb / div_factor ) ) ; HOST_WIDE_INT constant = offset - factor ; if ( constant == <NUM_LIT> ) return ; else if ( SMALL_OPERAND ( constant ) ) riscv_expand_op ( PLUS , mode , dest , dest , gen_int_mode ( constant , mode ) ) ; else { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( constant ) , mode ) ; constant = CONST_LOW_PART ( constant ) ; riscv_emit_move ( tmp , high ) ; riscv_expand_op ( PLUS , mode , dest , tmp , dest ) ;"
GCC,riscv,591,"Predict the next statement of this code snippet:
 <s> else if ( ( factor % ( vlenb / <NUM_LIT> ) ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else gcc_unreachable ( ) ; if ( div_factor != <NUM_LIT> ) riscv_expand_op ( LSHIFTRT , mode , tmp , tmp , gen_int_mode ( exact_log2 ( div_factor ) , QImode ) ) ; riscv_expand_mult_with_const_int ( mode , dest , tmp , factor / ( vlenb / div_factor ) ) ; HOST_WIDE_INT constant = offset - factor ; if ( constant == <NUM_LIT> ) return ; else if ( SMALL_OPERAND ( constant ) ) riscv_expand_op ( PLUS , mode , dest , dest , gen_int_mode ( constant , mode ) ) ; else { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( constant ) , mode ) ; constant = CONST_LOW_PART ( constant ) ; riscv_emit_move ( tmp , high ) ; riscv_expand_op ( PLUS , mode , dest , tmp , dest ) ; riscv_expand_op ( PLUS , mode , dest , dest , gen_int_mode ( constant , mode ) ) ; }"
GCC,riscv,592,"Predict the next statement of this code snippet:
 <s> bool might_split_p ; rtx set ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( mem ) ; might_split_p = true ; if ( GET_MODE_BITSIZE ( mode ) . to_constant ( ) <= <NUM_LIT> ) might_split_p = false ; else if ( GET_MODE_BITSIZE ( mode ) . to_constant ( ) == <NUM_LIT> ) { set = single_set ( insn ) ; if ( set && ! riscv_split_64bit_move_p ( SET_DEST ( set ) , SET_SRC ( set ) ) ) might_split_p = false ; }"
GCC,riscv,593,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == <NUM_LIT> ) return <STR_LIT> ; if ( TYPE_NAME ( type ) != NULL ) { const char * res = <STR_LIT> ( type ) ;"
GCC,riscv,594,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == <NUM_LIT> ) return <STR_LIT> ; if ( TYPE_NAME ( type ) != NULL ) {"
GCC,riscv,595,"Predict the next statement of this code snippet:
 <s> for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; codes [ i ] . value = trunc_int_for_mode ( codes [ i ] . value , mode ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } }"
GCC,riscv,596,"Predict the next statement of this code snippet:
 <s> mode = GET_MODE ( dest ) ; num_ops = riscv_build_integer ( codes , value , orig_mode ) ; if ( can_create_pseudo && num_ops > <NUM_LIT> && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { codes [ <NUM_LIT> ] . value = trunc_int_for_mode ( codes [ <NUM_LIT> ] . value , mode ) ; x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ;"
GCC,riscv,597,"Predict the next statement of this code snippet:
 <s> if ( inc ) regno ++ ; while ( regno <= limit ) { if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { * offset = * offset - UNITS_PER_WORD ; return regno ; } regno ++ ; } return INVALID_REGNUM ;"
GCC,riscv,598,"Predict the next statement of this code snippet:
 <s> if ( dest_code == REG ) { if ( GP_REG_P ( REGNO ( dest ) ) ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( dest ) ) ) switch ( width ) { case <NUM_LIT> : if ( TARGET_ZFHMIN ) return <STR_LIT> ; return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : if ( TARGET_64BIT ) return <STR_LIT> ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return <STR_LIT> ; } } if ( dest_code == MEM ) switch ( width ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) switch ( width ) { case <NUM_LIT> : if ( TARGET_ZFH ) return <STR_LIT> ; return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( dest_code == MEM ) switch ( width ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == MEM ) switch ( width ) { case <NUM_LIT> :"
GCC,riscv,599,"Predict the next statement of this code snippet:
 <s> riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; if ( info . num_fprs ) return false ; }"
GCC,riscv,600,"Predict the next statement of this code snippet:
 <s> } else { if ( CONST_INT_P ( op ) ) asm_fprintf ( file , <STR_LIT> ) ; else asm_fprintf ( file , <STR_LIT> ) ; } break ; } case 'v' : { rtx elt ; if ( REG_P ( op ) ) asm_fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; else { if ( ! const_vec_duplicate_p ( op , & elt ) ) output_operand_lossage ( <STR_LIT> ) ; else if ( satisfies_constraint_Wc0 ( op ) ) asm_fprintf ( file , <STR_LIT> ) ; else if ( satisfies_constraint_vi ( op ) || satisfies_constraint_vj ( op ) ) asm_fprintf ( file , <STR_LIT> , INTVAL ( elt ) ) ; else output_operand_lossage ( <STR_LIT> ) ; } break ; } case 'V' : { rtx elt ; if ( ! const_vec_duplicate_p ( op , & elt ) ) output_operand_lossage ( <STR_LIT> ) ; else if ( satisfies_constraint_vj ( op ) ) asm_fprintf ( file , <STR_LIT> , - INTVAL ( elt ) ) ; else output_operand_lossage ( <STR_LIT> ) ; break ; } case 'm' : { if ( riscv_v_ext_vector_mode_p ( mode ) ) { poly_int64 size = GET_MODE_SIZE ( mode ) ; unsigned int lmul ; if ( known_lt ( size , BYTES_PER_RISCV_VECTOR ) ) lmul = <NUM_LIT> ; else lmul = exact_div ( size , BYTES_PER_RISCV_VECTOR ) . to_constant ( ) ; asm_fprintf ( file , <STR_LIT> , lmul ) ; } else if ( code == CONST_INT ) { unsigned int vlmul = UINTVAL ( op ) ; switch ( vlmul ) { case <STR_LIT> : asm_fprintf ( file , <STR_LIT> , <STR_LIT> ) ;"
GCC,riscv,601,"Predict the next statement of this code snippet:
 <s> offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset . to_constant ( ) ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ;"
GCC,riscv,602,"Predict the next statement of this code snippet:
 <s> if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp = * punsignedp ; PROMOTE_MODE ( as_a < scalar_mode > ( mode ) , unsignedp , type ) ; * punsignedp = unsignedp ; return mode ;"
GCC,riscv,603,"Predict the next statement of this code snippet:
 <s> PROMOTE_MODE ( as_a < scalar_mode > ( mode ) , unsignedp , type ) ; * punsignedp = unsignedp ; return mode ;"
GCC,riscv,604,"Predict the next statement of this code snippet:
 <s> poly_uint64 riscv_regmode_natural_size ( machine_mode mode ) { if ( ! riscv_vector_chunks . is_constant ( ) && riscv_v_ext_vector_mode_p ( mode ) ) return BYTES_PER_RISCV_VECTOR ;"
GCC,riscv,605,"Predict the next statement of this code snippet:
 <s> if ( ! riscv_vector_chunks . is_constant ( ) && riscv_v_ext_vector_mode_p ( mode ) ) return BYTES_PER_RISCV_VECTOR ;"
GCC,riscv,606,"Predict the next statement of this code snippet:
 <s> init_adjust_machine_modes ( ) ; init_derived_machine_modes ( ) ; reinit_regs ( ) ;"
GCC,riscv,607,"Predict the next statement of this code snippet:
 <s> init_derived_machine_modes ( ) ; reinit_regs ( ) ;"
GCC,riscv,608,"Predict the next statement of this code snippet:
 <s> inform ( input_location , <STR_LIT> <STR_LIT> <STR_LIT> ) ;"
GCC,riscv,609,"Predict the next statement of this code snippet:
 <s> else return default_scalar_mode_supported_p ( mode ) ;"
GCC,riscv,610,"Predict the next statement of this code snippet:
 <s> static bool riscv_scalar_mode_supported_p ( scalar_mode mode ) { if ( mode == HFmode ) return true ; else return default_scalar_mode_supported_p ( mode ) ;"
GCC,riscv,611,"Predict the next statement of this code snippet:
 <s> static bool riscv_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 ) {"
GCC,riscv,612,"Predict the next statement of this code snippet:
 <s> static bool riscv_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 ) { return ( ! riscv_v_ext_vector_mode_p ( mode ) && GET_MODE_SIZE ( mode ) . to_constant ( ) > UNITS_PER_WORD && ( class1 == FP_REGS ) != ( class2 == FP_REGS ) && ! TARGET_XTHEADFMV ) ;"
GCC,riscv,613,"Predict the next statement of this code snippet:
 <s> local_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) riscv_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == <NUM_LIT> ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ;"
GCC,riscv,614,"Predict the next statement of this code snippet:
 <s> static void riscv_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) riscv_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ;"
GCC,riscv,615,"Predict the next statement of this code snippet:
 <s> static void riscv_set_handled_components ( sbitmap components ) { for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( bitmap_bit_p ( components , regno ) ) cfun -> machine -> reg_is_wrapped_separately [ regno ] = true ;"
GCC,riscv,616,"Predict the next statement of this code snippet:
 <s> static void riscv_set_handled_components ( sbitmap components ) { for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( bitmap_bit_p ( components , regno ) ) cfun -> machine -> reg_is_wrapped_separately [ regno ] = true ;"
GCC,riscv,617,"Predict the next statement of this code snippet:
 <s> slot_address = riscv_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset . to_constant ( ) ) ;"
GCC,riscv,618,"Predict the next statement of this code snippet:
 <s> bool riscv_shamt_matches_mask_p ( int shamt , HOST_WIDE_INT mask ) { return shamt == ctz_hwi ( mask ) ;"
GCC,riscv,619,"Predict the next statement of this code snippet:
 <s> bool riscv_shamt_matches_mask_p ( int shamt , HOST_WIDE_INT mask ) {"
GCC,riscv,620,"Predict the next statement of this code snippet:
 <s> emit_insn ( gen_th_fmv_x_w ( low_dest , src ) ) ; emit_insn ( gen_th_fmv_x_hw ( high_dest , src ) ) ; return ; } } rtx low_dest = riscv_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; } else { riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; }"
GCC,riscv,621,"Predict the next statement of this code snippet:
 <s> emit_insn ( gen_th_fmv_hw_w_x ( dest , high_src , low_src ) ) ; return ; } if ( FP_REG_RTX_P ( src ) ) { rtx low_dest = riscv_subword ( dest , false ) ; rtx high_dest = riscv_subword ( dest , true ) ; emit_insn ( gen_th_fmv_x_w ( low_dest , src ) ) ; emit_insn ( gen_th_fmv_x_hw ( high_dest , src ) ) ; return ; } } rtx low_dest = riscv_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; } else {"
GCC,riscv,622,"Predict the next statement of this code snippet:
 <s> rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; align = ( SYMBOL_REF_DECL ( x ) ? DECL_ALIGN ( SYMBOL_REF_DECL ( x ) ) : <NUM_LIT> ) ; size = ( SYMBOL_REF_DECL ( x ) && DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ? tree_to_uhwi ( DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ) : <NUM_LIT> * BITS_PER_WORD ) ; } else { align = GET_MODE_ALIGNMENT ( mode ) ; size = GET_MODE_BITSIZE ( mode ) . to_constant ( ) ;"
GCC,riscv,623,"Predict the next statement of this code snippet:
 <s> int align , size ; if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; align = ( SYMBOL_REF_DECL ( x ) ? DECL_ALIGN ( SYMBOL_REF_DECL ( x ) ) : <NUM_LIT> ) ; size = ( SYMBOL_REF_DECL ( x ) && DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ? tree_to_uhwi ( DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ) : <NUM_LIT> * BITS_PER_WORD ) ;"
GCC,riscv,624,"Predict the next statement of this code snippet:
 <s> static bool riscv_valid_offset_p ( rtx x , machine_mode mode ) { if ( ! const_arith_operand ( x , Pmode ) ) return false ; if ( GET_MODE_SIZE ( mode ) . to_constant ( ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) . to_constant ( ) - UNITS_PER_WORD ) ) return false ; return true ;"
GCC,riscv,625,"Predict the next statement of this code snippet:
 <s> if ( GET_MODE_SIZE ( mode ) . to_constant ( ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) . to_constant ( ) - UNITS_PER_WORD ) ) return false ; return true ;"
GCC,riscv,626,"Predict the next statement of this code snippet:
 <s> widest_int min_size = constant_lower_bound ( wi :: to_poly_widest ( TYPE_SIZE ( type ) ) ) ;"
GCC,riscv,627,"Predict the next statement of this code snippet:
 <s> if ( GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_VECTOR_BOOL ) return <NUM_LIT> ; widest_int min_size = constant_lower_bound ( wi :: to_poly_widest ( TYPE_SIZE ( type ) ) ) ;"
GCC,riscv,628,"Predict the next statement of this code snippet:
 <s> if ( TARGET_VECTOR ) return riscv_v_ext_vector_mode_p ( mode ) ;"
GCC,riscv,629,"Predict the next statement of this code snippet:
 <s> poly_int64 riscv_v_adjust_bytesize ( machine_mode mode , int scale ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { poly_uint16 mode_size = GET_MODE_SIZE ( mode ) ; if ( maybe_eq ( mode_size , ( uint16_t ) - <NUM_LIT> ) ) mode_size = riscv_vector_chunks * scale ; if ( known_gt ( mode_size , BYTES_PER_RISCV_VECTOR ) ) mode_size = BYTES_PER_RISCV_VECTOR ; return mode_size ; }"
GCC,riscv,630,"Predict the next statement of this code snippet:
 <s> poly_int64 riscv_v_adjust_bytesize ( machine_mode mode , int scale ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { poly_uint16 mode_size = GET_MODE_SIZE ( mode ) ; if ( maybe_eq ( mode_size , ( uint16_t ) - <NUM_LIT> ) ) mode_size = riscv_vector_chunks * scale ; if ( known_gt ( mode_size , BYTES_PER_RISCV_VECTOR ) ) mode_size = BYTES_PER_RISCV_VECTOR ; return mode_size ;"
GCC,riscv,631,"Predict the next statement of this code snippet:
 <s> if ( riscv_v_ext_vector_mode_p ( mode ) ) return riscv_vector_chunks * scale ;"
GCC,riscv,632,"Predict the next statement of this code snippet:
 <s> if ( riscv_v_ext_vector_mode_p ( mode ) ) return riscv_vector_chunks * scale ;"
GCC,riscv,633,"Predict the next statement of this code snippet:
 <s> poly_int64 riscv_v_adjust_precision ( machine_mode mode , int scale ) {"
GCC,riscv,634,"Predict the next statement of this code snippet:
 <s> rtx insn , dwarf , adjust_frame_rtx ; riscv_legitimize_poly_move ( Pmode , adjust_size , tmp , gen_int_mode ( offset , Pmode ) ) ; if ( epilogue ) insn = gen_add3_insn ( target , target , adjust_size ) ; else insn = gen_sub3_insn ( target , target , adjust_size ) ; insn = emit_insn ( insn ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; adjust_frame_rtx = gen_rtx_SET ( target , plus_constant ( Pmode , target , epilogue ? offset : - offset ) ) ; dwarf = alloc_reg_note ( REG_FRAME_RELATED_EXPR , copy_rtx ( adjust_frame_rtx ) , NULL_RTX ) ;"
GCC,riscv,635,"Predict the next statement of this code snippet:
 <s> if ( epilogue ) insn = gen_add3_insn ( target , target , adjust_size ) ; else insn = gen_sub3_insn ( target , target , adjust_size ) ; insn = emit_insn ( insn ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; adjust_frame_rtx = gen_rtx_SET ( target , plus_constant ( Pmode , target , epilogue ? offset : - offset ) ) ; dwarf = alloc_reg_note ( REG_FRAME_RELATED_EXPR , copy_rtx ( adjust_frame_rtx ) , NULL_RTX ) ; REG_NOTES ( insn ) = dwarf ;"
GCC,riscv,636,"Predict the next statement of this code snippet:
 <s> bool riscv_v_ext_vector_mode_p ( machine_mode mode ) {"
GCC,riscv,637,"Predict the next statement of this code snippet:
 <s> switch ( mode ) { default :"
GCC,riscv,638,"Predict the next statement of this code snippet:
 <s> HARD_REG_SET riscv_zero_call_used_regs ( HARD_REG_SET need_zeroed_hardregs ) { HARD_REG_SET zeroed_hardregs ; CLEAR_HARD_REG_SET ( zeroed_hardregs ) ;"
GCC,riscv,639,"Predict the next statement of this code snippet:
 <s> return zeroed_hardregs | default_zero_call_used_regs ( need_zeroed_hardregs & ~ zeroed_hardregs ) ;"
GCC,riscv,640,"Predict the next statement of this code snippet:
 <s> if ( TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { vl_regno = regno ; break ; } } if ( vl_regno > GP_REG_LAST ) sorry ( <STR_LIT> , <STR_LIT> ) ; bool emitted_vlmax_vsetvl = false ; rtx vl = gen_rtx_REG ( Pmode , vl_regno ) ; for ( unsigned regno = V_REG_FIRST ; regno <= V_REG_LAST ; ++ regno ) { if ( TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { rtx target = regno_reg_rtx [ regno ] ; machine_mode mode = GET_MODE ( target ) ;"
GCC,riscv,641,"Predict the next statement of this code snippet:
 <s> HARD_REG_SET zeroed_hardregs ; CLEAR_HARD_REG_SET ( zeroed_hardregs ) ; unsigned vl_regno = INVALID_REGNUM ; for ( unsigned regno = GP_REG_FIRST + <NUM_LIT> ; regno <= GP_REG_LAST ; regno ++ ) { if ( TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { vl_regno = regno ; break ; } } if ( vl_regno > GP_REG_LAST ) sorry ( <STR_LIT> , <STR_LIT> ) ; bool emitted_vlmax_vsetvl = false ; rtx vl = gen_rtx_REG ( Pmode , vl_regno ) ; for ( unsigned regno = V_REG_FIRST ; regno <= V_REG_LAST ; ++ regno ) {"
GCC,riscv,642,"Predict the next statement of this code snippet:
 <s> static int riscv_address_cost ( rtx addr , enum machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) {"
GCC,riscv,643,"Predict the next statement of this code snippet:
 <s> if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;"
GCC,riscv,644,"Predict the next statement of this code snippet:
 <s> int n = <NUM_LIT> ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) return <NUM_LIT> ;"
GCC,riscv,645,"Predict the next statement of this code snippet:
 <s> high = riscv_force_temporary ( temp , high ) ; reg = riscv_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) ) ;"
GCC,riscv,646,"Predict the next statement of this code snippet:
 <s> static rtx riscv_adjust_libcall_cfi_epilogue ( ) { rtx dwarf = NULL_RTX ; rtx adjust_sp_rtx , reg ; int saved_size = cfun -> machine -> frame . save_libcall_adjustment ; adjust_sp_rtx = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( saved_size ) ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , adjust_sp_rtx , dwarf ) ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST - <NUM_LIT> ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { reg = gen_rtx_REG ( SImode , regno ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } return dwarf ;"
GCC,riscv,647,"Predict the next statement of this code snippet:
 <s> rtx dwarf = NULL_RTX ; rtx adjust_sp_rtx , reg ; int saved_size = cfun -> machine -> frame . save_libcall_adjustment ;"
GCC,riscv,648,"Predict the next statement of this code snippet:
 <s> rtx dwarf = NULL_RTX ; rtx adjust_sp_rtx , reg , mem , insn ; int saved_size = cfun -> machine -> frame . save_libcall_adjustment ; int offset ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST - <NUM_LIT> ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { if ( regno == RETURN_ADDR_REGNUM ) offset = saved_size - UNITS_PER_WORD ; else if ( regno == S0_REGNUM ) offset = saved_size - UNITS_PER_WORD * <NUM_LIT> ; else if ( regno == S1_REGNUM ) offset = saved_size - UNITS_PER_WORD * <NUM_LIT> ; else offset = saved_size - ( ( regno - S2_REGNUM + <NUM_LIT> ) * UNITS_PER_WORD ) ; reg = gen_rtx_REG ( SImode , regno ) ;"
GCC,riscv,649,"Predict the next statement of this code snippet:
 <s> riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , mode , type , named , false ) ;"
GCC,riscv,650,"Predict the next statement of this code snippet:
 <s> riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , mode , type , named , false ) ;"
GCC,riscv,651,"Predict the next statement of this code snippet:
 <s> if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = LSHIFTRT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } shifted_val = value << shift ; alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = LSHIFTRT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ;"
GCC,riscv,652,"Predict the next statement of this code snippet:
 <s> if ( cost > <NUM_LIT> && ( value & <NUM_LIT> ) == <NUM_LIT> ) { int shift = ctz_hwi ( value ) ; unsigned HOST_WIDE_INT x = value ; x = sext_hwi ( x >> shift , HOST_BITS_PER_WIDE_INT - shift ) ; if ( shift > IMM_BITS && ! SMALL_OPERAND ( x ) && LUI_OPERAND ( x << IMM_BITS ) ) shift -= IMM_BITS , x <<= IMM_BITS ; alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , x , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = ASHIFT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; }"
GCC,riscv,653,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( x ) == HIGH ) return true ; split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > <NUM_LIT> ) return true ; if ( flag_pic ) return true ; }"
GCC,riscv,654,"Predict the next statement of this code snippet:
 <s> case LE : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( INTVAL ( * cmp1 ) < plus_one ) { * code = LT ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; case LEU : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( plus_one != <NUM_LIT> ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; default : break ;"
GCC,riscv,655,"Predict the next statement of this code snippet:
 <s> if ( riscv_int_order_operand_ok_p ( * code , * cmp1 ) ) return true ; if ( CONST_INT_P ( * cmp1 ) ) switch ( * code ) { case LE : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( INTVAL ( * cmp1 ) < plus_one ) { * code = LT ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ;"
GCC,riscv,656,"Predict the next statement of this code snippet:
 <s> bool riscv_can_use_return_insn ( void ) { return reload_completed && cfun -> machine -> frame . total_size == <NUM_LIT> ;"
GCC,riscv,657,"Predict the next statement of this code snippet:
 <s> case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ;"
GCC,riscv,658,"Predict the next statement of this code snippet:
 <s> case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ;"
GCC,riscv,659,"Predict the next statement of this code snippet:
 <s> if ( reg_class_subset_p ( GR_REGS , rclass ) ) return riscv_hard_regno_nregs ( GP_REG_FIRST , mode ) ;"
GCC,riscv,660,"Predict the next statement of this code snippet:
 <s> memset ( frame , <NUM_LIT> , sizeof ( * frame ) ) ; for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( crtl -> calls_eh_return ) for ( i = <NUM_LIT> ; ( regno = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( TARGET_HARD_FLOAT ) for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) ) frame -> fmask |= <NUM_LIT> << ( regno - FP_REG_FIRST ) , num_f_saved ++ ; offset = crtl -> outgoing_args_size ; offset += RISCV_STACK_ALIGN ( get_frame_size ( ) ) ; frame -> frame_pointer_offset = offset ; if ( frame -> fmask ) offset += RISCV_STACK_ALIGN ( num_f_saved * UNITS_PER_FP_REG ) ; frame -> fp_sp_offset = offset - UNITS_PER_FP_REG ; if ( frame -> mask ) { unsigned x_save_size = RISCV_STACK_ALIGN ( num_x_saved * UNITS_PER_WORD ) ; unsigned num_save_restore = <NUM_LIT> + riscv_save_libcall_count ( frame -> mask ) ; if ( RISCV_STACK_ALIGN ( num_save_restore * UNITS_PER_WORD ) == x_save_size ) frame -> save_libcall_adjustment = x_save_size ; offset += x_save_size ; } frame -> gp_sp_offset = offset - UNITS_PER_WORD ; frame -> hard_frame_pointer_offset = offset ; offset += RISCV_STACK_ALIGN ( cfun -> machine -> varargs_size ) ; frame -> arg_pointer_offset = offset ;"
GCC,riscv,661,"Predict the next statement of this code snippet:
 <s> static void riscv_conditional_register_usage ( void ) { if ( ! TARGET_HARD_FLOAT ) {"
GCC,riscv,662,"Predict the next statement of this code snippet:
 <s> char * name = ( char * ) alloca ( strlen ( s -> named . name ) + <NUM_LIT> ) ; sprintf ( name , <STR_LIT> , s -> named . name + <NUM_LIT> ) ; return get_section ( name , s -> named . common . flags , NULL ) ; } if ( s == data_section ) return sdata_section ; } return s ;"
GCC,riscv,663,"Predict the next statement of this code snippet:
 <s> * code = EQ ; case ORDERED : tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; case UNEQ : case LTGT : * code = fp_code == LTGT ? GTU : EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; break ; default :"
GCC,riscv,664,"Predict the next statement of this code snippet:
 <s> } else if ( invert_ptr == <NUM_LIT> ) { rtx inv_target = riscv_force_binary ( GET_MODE ( target ) , inv_code , cmp0 , cmp1 ) ; riscv_emit_binary ( XOR , target , inv_target , const1_rtx ) ; } else { * invert_ptr = ! * invert_ptr ; riscv_emit_binary ( inv_code , target , cmp0 , cmp1 ) ; } }"
GCC,riscv,665,"Predict the next statement of this code snippet:
 <s> step1 -= step2 ; } if ( step1 > <NUM_LIT> ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( step1 ) ; if ( ! SMALL_OPERAND ( step1 ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( use_restore_libcall ) frame -> mask = <NUM_LIT> ; riscv_for_each_saved_reg ( frame -> total_size - step2 , riscv_restore_reg ) ; if ( use_restore_libcall ) { frame -> mask = mask ; gcc_assert ( step2 >= frame -> save_libcall_adjustment ) ; step2 -= frame -> save_libcall_adjustment ; } if ( need_barrier_p ) riscv_emit_stack_tie ( ) ;"
GCC,riscv,666,"Predict the next statement of this code snippet:
 <s> insn = emit_insn ( gen_gpr_save ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; }"
GCC,riscv,667,"Predict the next statement of this code snippet:
 <s> insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; riscv_emit_stack_tie ( ) ; } if ( size > <NUM_LIT> ) {"
GCC,riscv,668,"Predict the next statement of this code snippet:
 <s> if ( GET_MODE_SIZE ( word_mode ) > GET_MODE_SIZE ( GET_MODE ( * op0 ) ) ) { if ( unsigned_condition ( code ) == code && GET_MODE ( * op0 ) == QImode ) { * op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ; if ( CONST_INT_P ( * op1 ) ) * op1 = GEN_INT ( ( uint8_t ) INTVAL ( * op1 ) ) ; else * op1 = gen_rtx_ZERO_EXTEND ( word_mode , * op1 ) ;"
GCC,riscv,669,"Predict the next statement of this code snippet:
 <s> static void riscv_extend_comparands ( rtx_code code , rtx * op0 , rtx * op1 ) { if ( GET_MODE_SIZE ( word_mode ) > GET_MODE_SIZE ( GET_MODE ( * op0 ) ) ) { if ( unsigned_condition ( code ) == code && GET_MODE ( * op0 ) == QImode ) { * op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ; if ( CONST_INT_P ( * op1 ) ) * op1 = GEN_INT ( ( uint8_t ) INTVAL ( * op1 ) ) ; else * op1 = gen_rtx_ZERO_EXTEND ( word_mode , * op1 ) ; } else { * op0 = gen_rtx_SIGN_EXTEND ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = gen_rtx_SIGN_EXTEND ( word_mode , * op1 ) ;"
GCC,riscv,670,"Predict the next statement of this code snippet:
 <s> default_file_start ( ) ;"
GCC,riscv,671,"Predict the next statement of this code snippet:
 <s> static void riscv_file_start ( void ) { default_file_start ( ) ;"
GCC,riscv,672,"Predict the next statement of this code snippet:
 <s> if ( ! SMALL_OPERAND ( frame -> total_size - max_first_step ) && frame -> total_size % IMM_REACH < IMM_REACH / <NUM_LIT> && frame -> total_size % IMM_REACH >= min_first_step ) return frame -> total_size % IMM_REACH ; gcc_assert ( min_first_step <= max_first_step ) ;"
GCC,riscv,673,"Predict the next statement of this code snippet:
 <s> return riscv_flatten_aggregate_field ( type , fields , <NUM_LIT> , <NUM_LIT> ) ;"
GCC,riscv,674,"Predict the next statement of this code snippet:
 <s> static int riscv_flatten_aggregate_argument ( const_tree type , riscv_aggregate_field fields [ <NUM_LIT> ] ) { if ( ! type || TREE_CODE ( type ) != RECORD_TYPE ) return - <NUM_LIT> ; return riscv_flatten_aggregate_field ( type , fields , <NUM_LIT> , <NUM_LIT> ) ;"
GCC,riscv,675,"Predict the next statement of this code snippet:
 <s> n_elts = <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ; gcc_assert ( n_elts >= <NUM_LIT> ) ; for ( HOST_WIDE_INT i = <NUM_LIT> ; i < n_elts ; i ++ ) for ( int j = <NUM_LIT> ; j < n_subfields ; j ++ ) { if ( n >= <NUM_LIT> ) return - <NUM_LIT> ; fields [ n ] = subfields [ j ] ; fields [ n ++ ] . offset += i * tree_to_uhwi ( elt_size ) ; } return n ; } case COMPLEX_TYPE : { if ( n != <NUM_LIT> ) return - <NUM_LIT> ; HOST_WIDE_INT elt_size = GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( type ) ) ) ; if ( elt_size <= UNITS_PER_FP_ARG ) { fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset = offset ; fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset = offset + elt_size ; return <NUM_LIT> ; } return - <NUM_LIT> ;"
GCC,riscv,676,"Predict the next statement of this code snippet:
 <s> if ( n >= <NUM_LIT> ) return - <NUM_LIT> ; fields [ n ] = subfields [ j ] ; fields [ n ++ ] . offset += i * tree_to_uhwi ( elt_size ) ; } return n ; } case COMPLEX_TYPE : { if ( n != <NUM_LIT> ) return - <NUM_LIT> ; HOST_WIDE_INT elt_size = GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( type ) ) ) ; if ( elt_size <= UNITS_PER_FP_ARG ) { fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset = offset ; fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset = offset + elt_size ; return <NUM_LIT> ; } return - <NUM_LIT> ; } default : if ( n < <NUM_LIT> && ( ( SCALAR_FLOAT_TYPE_P ( type ) && GET_MODE_SIZE ( TYPE_MODE ( type ) ) <= UNITS_PER_FP_ARG ) || ( INTEGRAL_TYPE_P ( type ) && GET_MODE_SIZE ( TYPE_MODE ( type ) ) <= UNITS_PER_WORD ) ) ) {"
GCC,riscv,677,"Predict the next statement of this code snippet:
 <s> static rtx riscv_force_address ( rtx x , enum machine_mode mode ) { if ( ! riscv_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ;"
GCC,riscv,678,"Predict the next statement of this code snippet:
 <s> static rtx riscv_force_binary ( enum machine_mode mode , enum rtx_code code , rtx x , rtx y ) {"
GCC,riscv,679,"Predict the next statement of this code snippet:
 <s> static rtx riscv_force_temporary ( rtx dest , rtx value ) { if ( can_create_pseudo_p ( ) ) return force_reg ( Pmode , value ) ; else { riscv_emit_move ( dest , value ) ; return dest ; }"
GCC,riscv,680,"Predict the next statement of this code snippet:
 <s> if ( can_create_pseudo_p ( ) ) return force_reg ( Pmode , value ) ; else { riscv_emit_move ( dest , value ) ; return dest ; }"
GCC,riscv,681,"Predict the next statement of this code snippet:
 <s> offset = cfun -> machine -> frame . gp_sp_offset - sp_offset ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST - <NUM_LIT> ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { riscv_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { enum machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; riscv_save_restore_reg ( mode , regno , offset , fn ) ;"
GCC,riscv,682,"Predict the next statement of this code snippet:
 <s> return riscv_get_arg_info ( & info , cum , mode , type , named , false ) ;"
GCC,riscv,683,"Predict the next statement of this code snippet:
 <s> struct riscv_arg_info info ; if ( mode == VOIDmode ) return NULL ; return riscv_get_arg_info ( & info , cum , mode , type , named , false ) ;"
GCC,riscv,684,"Predict the next statement of this code snippet:
 <s> else alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ;"
GCC,riscv,685,"Predict the next statement of this code snippet:
 <s> static bool riscv_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_SAVE_RESTORE ) return riscv_leaf_function_p ( ) ; return true ;"
GCC,riscv,686,"Predict the next statement of this code snippet:
 <s> } memset ( & args , <NUM_LIT> , sizeof args ) ;"
GCC,riscv,687,"Predict the next statement of this code snippet:
 <s> rtx riscv_function_value ( const_tree type , const_tree func , enum machine_mode mode ) { struct riscv_arg_info info ; CUMULATIVE_ARGS args ; if ( type ) { int unsigned_p = TYPE_UNSIGNED ( type ) ; mode = TYPE_MODE ( type ) ; mode = promote_function_mode ( type , mode , & unsigned_p , func , <NUM_LIT> ) ;"
GCC,riscv,688,"Predict the next statement of this code snippet:
 <s> memset ( info , <NUM_LIT> , sizeof ( * info ) ) ; info -> gpr_offset = cum -> num_gprs ; info -> fpr_offset = cum -> num_fprs ; if ( named ) { riscv_aggregate_field fields [ <NUM_LIT> ] ; unsigned fregno = fpr_base + info -> fpr_offset ; unsigned gregno = gpr_base + info -> gpr_offset ; if ( ( info -> num_fprs = riscv_pass_aggregate_in_fpr_pair_p ( type , fields ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( info -> num_fprs ) { case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno ) ; case MODE_COMPLEX_FLOAT :"
GCC,riscv,689,"Predict the next statement of this code snippet:
 <s> memset ( info , <NUM_LIT> , sizeof ( * info ) ) ; info -> gpr_offset = cum -> num_gprs ; info -> fpr_offset = cum -> num_fprs ; if ( named ) { riscv_aggregate_field fields [ <NUM_LIT> ] ; unsigned fregno = fpr_base + info -> fpr_offset ; unsigned gregno = gpr_base + info -> gpr_offset ; if ( ( info -> num_fprs = riscv_pass_aggregate_in_fpr_pair_p ( type , fields ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( info -> num_fprs ) { case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno ) ;"
GCC,riscv,690,"Predict the next statement of this code snippet:
 <s> } else if ( FP_REG_P ( regno ) ) { if ( ! FP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ; if ( GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_REG || ( ! call_used_regs [ regno ] && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_ARG ) ) return false ;"
GCC,riscv,691,"Predict the next statement of this code snippet:
 <s> unsigned int nregs = riscv_hard_regno_nregs ( regno , mode ) ; if ( GP_REG_P ( regno ) ) { if ( ! GP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; } else if ( FP_REG_P ( regno ) ) { if ( ! FP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ;"
GCC,riscv,692,"Predict the next statement of this code snippet:
 <s> if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_REG - <NUM_LIT> ) / UNITS_PER_FP_REG ;"
GCC,riscv,693,"Predict the next statement of this code snippet:
 <s> static bool riscv_leaf_function_p ( void ) { if ( cfun -> machine -> is_leaf == <NUM_LIT> ) cfun -> machine -> is_leaf = leaf_function_p ( ) ? <NUM_LIT> : - <NUM_LIT> ; return cfun -> machine -> is_leaf > <NUM_LIT> ;"
GCC,riscv,694,"Predict the next statement of this code snippet:
 <s> static bool riscv_legitimate_address_p ( enum machine_mode mode , rtx x , bool strict_p ) { struct riscv_address_info addr ;"
GCC,riscv,695,"Predict the next statement of this code snippet:
 <s> struct riscv_address_info addr ;"
GCC,riscv,696,"Predict the next statement of this code snippet:
 <s> static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ; if ( riscv_split_symbol ( NULL , x , mode , & addr ) ) return riscv_force_address ( addr , mode ) ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) != <NUM_LIT> ) { rtx base = XEXP ( x , <NUM_LIT> ) ; HOST_WIDE_INT offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( ! riscv_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = riscv_add_offset ( NULL , base , offset ) ; return riscv_force_address ( addr , mode ) ; }"
GCC,riscv,697,"Predict the next statement of this code snippet:
 <s> rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { riscv_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) {"
GCC,riscv,698,"Predict the next statement of this code snippet:
 <s> riscv_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { riscv_legitimize_const_move ( mode , dest , src ) ;"
GCC,riscv,699,"Predict the next statement of this code snippet:
 <s> bool riscv_legitimize_move ( enum machine_mode mode , rtx dest , rtx src ) { if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { riscv_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) {"
GCC,riscv,700,"Predict the next statement of this code snippet:
 <s> mode = GET_MODE ( mem ) ; might_split_p = true ; if ( GET_MODE_BITSIZE ( mode ) <= <NUM_LIT> ) might_split_p = false ; else if ( GET_MODE_BITSIZE ( mode ) == <NUM_LIT> ) { set = single_set ( insn ) ; if ( set && ! riscv_split_64bit_move_p ( SET_DEST ( set ) , SET_SRC ( set ) ) ) might_split_p = false ;"
GCC,riscv,701,"Predict the next statement of this code snippet:
 <s> set = single_set ( insn ) ; if ( set && ! riscv_split_64bit_move_p ( SET_DEST ( set ) , SET_SRC ( set ) ) ) might_split_p = false ; } return riscv_address_insns ( XEXP ( mem , <NUM_LIT> ) , mode , might_split_p ) ;"
GCC,riscv,702,"Predict the next statement of this code snippet:
 <s> return ( tune_info -> memory_cost + memory_move_secondary_cost ( mode , rclass , in ) ) ;"
GCC,riscv,703,"Predict the next statement of this code snippet:
 <s> if ( can_create_pseudo_p ( ) && num_ops > <NUM_LIT> && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) x = riscv_emit_set ( temp , x ) ;"
GCC,riscv,704,"Predict the next statement of this code snippet:
 <s> x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ;"
GCC,riscv,705,"Predict the next statement of this code snippet:
 <s> SUBTARGET_OVERRIDE_OPTIONS ; flag_pcc_struct_return = <NUM_LIT> ; if ( flag_pic ) g_switch_value = <NUM_LIT> ; if ( TARGET_MUL && ( target_flags_explicit & MASK_DIV ) == <NUM_LIT> ) target_flags |= MASK_DIV ; else if ( ! TARGET_MUL && TARGET_DIV ) error ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT && ( target_flags_explicit & MASK_FDIV ) == <NUM_LIT> ) target_flags |= MASK_FDIV ; cpu = riscv_parse_cpu ( riscv_tune_string ? riscv_tune_string : RISCV_TUNE_STRING_DEFAULT ) ; tune_info = optimize_size ? & optimize_size_tune_info : cpu -> tune_info ; if ( riscv_branch_cost == <NUM_LIT> ) riscv_branch_cost = tune_info -> branch_cost ; init_machine_status = & riscv_init_machine_status ; if ( flag_pic ) riscv_cmodel = CM_PIC ; if ( ( target_flags_explicit & MASK_EXPLICIT_RELOCS ) == <NUM_LIT> ) if ( riscv_cmodel == CM_MEDLOW ) target_flags |= MASK_EXPLICIT_RELOCS ; if ( UNITS_PER_FP_ARG > ( TARGET_HARD_FLOAT ? UNITS_PER_FP_REG : <NUM_LIT> ) ) error ( <STR_LIT> , UNITS_PER_FP_ARG > <NUM_LIT> ? 'Q' : ( UNITS_PER_FP_ARG > <NUM_LIT> ? 'D' : 'F' ) ) ; if ( BITS_PER_WORD != POINTER_SIZE ) error ( <STR_LIT> , POINTER_SIZE ) ;"
GCC,riscv,706,"Predict the next statement of this code snippet:
 <s> RISCV_TUNE_STRING_DEFAULT ) ; tune_info = optimize_size ? & optimize_size_tune_info : cpu -> tune_info ; if ( riscv_branch_cost == <NUM_LIT> ) riscv_branch_cost = tune_info -> branch_cost ; init_machine_status = & riscv_init_machine_status ; if ( flag_pic ) riscv_cmodel = CM_PIC ; if ( ( target_flags_explicit & MASK_EXPLICIT_RELOCS ) == <NUM_LIT> ) if ( riscv_cmodel == CM_MEDLOW ) target_flags |= MASK_EXPLICIT_RELOCS ; if ( UNITS_PER_FP_ARG > ( TARGET_HARD_FLOAT ? UNITS_PER_FP_REG : <NUM_LIT> ) ) error ( <STR_LIT> , UNITS_PER_FP_ARG > <NUM_LIT> ? 'Q' : ( UNITS_PER_FP_ARG > <NUM_LIT> ? 'D' : 'F' ) ) ; if ( BITS_PER_WORD != POINTER_SIZE ) error ( <STR_LIT> , POINTER_SIZE ) ;"
GCC,riscv,707,"Predict the next statement of this code snippet:
 <s> reload_completed = <NUM_LIT> ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = gen_rtx_MEM ( FUNCTION_MODE , XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ) ; temp1 = gen_rtx_REG ( Pmode , RISCV_PROLOGUE_TEMP_REGNUM ) ; temp2 = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != <NUM_LIT> ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { riscv_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; }"
GCC,riscv,708,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_cpu_info_table ) ; i ++ ) if ( strcmp ( riscv_cpu_info_table [ i ] . name , cpu_string ) == <NUM_LIT> ) return riscv_cpu_info_table + i ; error ( <STR_LIT> , cpu_string ) ; return riscv_cpu_info_table ;"
GCC,riscv,709,"Predict the next statement of this code snippet:
 <s> static const struct riscv_cpu_info * riscv_parse_cpu ( const char * cpu_string ) { for ( unsigned i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_cpu_info_table ) ; i ++ ) if ( strcmp ( riscv_cpu_info_table [ i ] . name , cpu_string ) == <NUM_LIT> ) return riscv_cpu_info_table + i ;"
GCC,riscv,710,"Predict the next statement of this code snippet:
 <s> unsigned num_int = <NUM_LIT> , num_float = <NUM_LIT> ; int n = riscv_flatten_aggregate_argument ( type , fields ) ; for ( int i = <NUM_LIT> ; i < n ; i ++ ) { num_float += SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ;"
GCC,riscv,711,"Predict the next statement of this code snippet:
 <s> int n = riscv_flatten_aggregate_argument ( type , fields ) ; for ( int i = <NUM_LIT> ; i < n ; i ++ ) if ( ! SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ) return <NUM_LIT> ; return n > <NUM_LIT> ? n : <NUM_LIT> ;"
GCC,riscv,712,"Predict the next statement of this code snippet:
 <s> struct riscv_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) { riscv_get_arg_info ( & info , cum , mode , type , named , false ) ;"
GCC,riscv,713,"Predict the next statement of this code snippet:
 <s> struct riscv_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) {"
GCC,riscv,714,"Predict the next statement of this code snippet:
 <s> return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode1 , regno1 ) , GEN_INT ( offset1 ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode2 , regno2 ) , GEN_INT ( offset2 ) ) ) ) ;"
GCC,riscv,715,"Predict the next statement of this code snippet:
 <s> static rtx riscv_pass_fpr_pair ( enum machine_mode mode , unsigned regno1 , enum machine_mode mode1 , HOST_WIDE_INT offset1 , unsigned regno2 , enum machine_mode mode2 , HOST_WIDE_INT offset2 ) {"
GCC,riscv,716,"Predict the next statement of this code snippet:
 <s> static rtx riscv_pass_fpr_single ( enum machine_mode type_mode , unsigned regno , enum machine_mode value_mode ) {"
GCC,riscv,717,"Predict the next statement of this code snippet:
 <s> static rtx riscv_pass_fpr_single ( enum machine_mode type_mode , unsigned regno , enum machine_mode value_mode ) { rtx x = gen_rtx_REG ( value_mode , regno ) ; if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode , x , const0_rtx ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( <NUM_LIT> , x ) ) ; } return x ;"
GCC,riscv,718,"Predict the next statement of this code snippet:
 <s> case REG : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; break ; case MEM : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; else output_address ( mode , XEXP ( op , <NUM_LIT> ) ) ; break ; default : if ( letter == 'z' && op == CONST0_RTX ( GET_MODE ( op ) ) ) fputs ( reg_names [ GP_REG_FIRST ] , file ) ; else if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ;"
GCC,riscv,719,"Predict the next statement of this code snippet:
 <s> switch ( code ) { case REG : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; break ; case MEM : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; else output_address ( mode , XEXP ( op , <NUM_LIT> ) ) ; break ; default : if ( letter == 'z' && op == CONST0_RTX ( GET_MODE ( op ) ) ) fputs ( reg_names [ GP_REG_FIRST ] , file ) ; else if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ;"
GCC,riscv,720,"Predict the next statement of this code snippet:
 <s> reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; case SYMBOL_PCREL : reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; case SYMBOL_TLS_LE : reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; default : gcc_unreachable ( ) ;"
GCC,riscv,721,"Predict the next statement of this code snippet:
 <s> if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; }"
GCC,riscv,722,"Predict the next statement of this code snippet:
 <s> regno = reg_renumber [ regno ] ; }"
GCC,riscv,723,"Predict the next statement of this code snippet:
 <s> static void riscv_restore_reg ( rtx reg , rtx mem ) { rtx insn = riscv_emit_move ( reg , mem ) ; rtx dwarf = NULL_RTX ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; REG_NOTES ( insn ) = dwarf ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;"
GCC,riscv,724,"Predict the next statement of this code snippet:
 <s> memset ( & args , <NUM_LIT> , sizeof args ) ;"
GCC,riscv,725,"Predict the next statement of this code snippet:
 <s> bool might_clobber = crtl -> saves_all_registers || df_regs_ever_live_p ( regno ) ; if ( call_saved && might_clobber ) return true ;"
GCC,riscv,726,"Predict the next statement of this code snippet:
 <s> bool call_saved = ! global_regs [ regno ] && ! call_used_regs [ regno ] ; bool might_clobber = crtl -> saves_all_registers || df_regs_ever_live_p ( regno ) ; if ( call_saved && might_clobber ) return true ;"
GCC,riscv,727,"Predict the next statement of this code snippet:
 <s> static void riscv_save_restore_reg ( enum machine_mode mode , int regno , HOST_WIDE_INT offset , riscv_save_restore_fn fn ) { rtx mem ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ;"
GCC,riscv,728,"Predict the next statement of this code snippet:
 <s> static void riscv_setup_incoming_varargs ( cumulative_args_t cum , enum machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; riscv_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , <NUM_LIT> ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ;"
GCC,riscv,729,"Predict the next statement of this code snippet:
 <s> { static unsigned seqno ; char buf [ <NUM_LIT> ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; * low_out = gen_rtx_LO_SUM ( Pmode , temp , label ) ; seqno ++ ; } break ; default : gcc_unreachable ( ) ; }"
GCC,riscv,730,"Predict the next statement of this code snippet:
 <s> rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; * low_out = gen_rtx_LO_SUM ( Pmode , temp , label ) ; seqno ++ ; } break ;"
GCC,riscv,731,"Predict the next statement of this code snippet:
 <s> if ( MEM_P ( op ) ) return adjust_address ( op , word_mode , byte ) ; if ( REG_P ( op ) ) gcc_assert ( ! FP_REG_RTX_P ( op ) ) ;"
GCC,riscv,732,"Predict the next statement of this code snippet:
 <s> if ( REG_P ( op ) ) gcc_assert ( ! FP_REG_RTX_P ( op ) ) ; return simplify_gen_subreg ( word_mode , op , mode , byte ) ;"
GCC,riscv,733,"Predict the next statement of this code snippet:
 <s> static rtx riscv_unspec_offset_high ( rtx temp , rtx addr , enum riscv_symbol_type symbol_type ) {"
GCC,riscv,734,"Predict the next statement of this code snippet:
 <s> if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ;"
GCC,riscv,735,"Predict the next statement of this code snippet:
 <s> static bool riscv_valid_lo_sum_p ( enum riscv_symbol_type sym_type , enum machine_mode mode ) { if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ;"
GCC,riscv,736,"Predict the next statement of this code snippet:
 <s> int n = <NUM_LIT> ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) return <NUM_LIT> ; if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;"
GCC,riscv,737,"Predict the next statement of this code snippet:
 <s> struct riscv_arg_info arg ; riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , mode , type , named , false ) ; return arg . stack_p ? arg . num_gprs * UNITS_PER_WORD : <NUM_LIT> ;"
GCC,riscv,738,"Predict the next statement of this code snippet:
 <s> struct riscv_arg_info arg ;"
GCC,riscv,739,"Predict the next statement of this code snippet:
 <s> static void riscv_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; enum machine_mode mode ; rtx * regs ; bits = MAX ( BITS_PER_UNIT , MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ) ; mode = mode_for_size ( bits , MODE_INT , <NUM_LIT> ) . require ( ) ;"
GCC,riscv,740,"Predict the next statement of this code snippet:
 <s> switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : info -> type = ADDRESS_LO_SUM ;"
GCC,riscv,741,"Predict the next statement of this code snippet:
 <s> info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; info -> symbol_type = riscv_classify_symbolic_expression ( info -> offset ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_lo_sum_p ( info -> symbol_type , mode ) ) ; case CONST_INT : info -> type = ADDRESS_CONST_INT ; return SMALL_OPERAND ( INTVAL ( x ) ) ; default : return false ;"
GCC,riscv,742,"Predict the next statement of this code snippet:
 <s> if ( ! cfun -> machine -> naked_p ) { for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( crtl -> calls_eh_return ) for ( i = <NUM_LIT> ; ( regno = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( TARGET_HARD_FLOAT ) for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) ) frame -> fmask |= <NUM_LIT> << ( regno - FP_REG_FIRST ) , num_f_saved ++ ; } offset = RISCV_STACK_ALIGN ( crtl -> outgoing_args_size ) ; offset += RISCV_STACK_ALIGN ( get_frame_size ( ) ) ; frame -> frame_pointer_offset = offset ; if ( frame -> fmask ) offset += RISCV_STACK_ALIGN ( num_f_saved * UNITS_PER_FP_REG ) ; frame -> fp_sp_offset = offset - UNITS_PER_FP_REG ; if ( frame -> mask ) { unsigned x_save_size = RISCV_STACK_ALIGN ( num_x_saved * UNITS_PER_WORD ) ; unsigned num_save_restore = <NUM_LIT> + riscv_save_libcall_count ( frame -> mask ) ; if ( RISCV_STACK_ALIGN ( num_save_restore * UNITS_PER_WORD ) == x_save_size ) frame -> save_libcall_adjustment = x_save_size ; offset += x_save_size ; } frame -> gp_sp_offset = offset - UNITS_PER_WORD ; frame -> hard_frame_pointer_offset = offset ; offset += RISCV_STACK_ALIGN ( cfun -> machine -> varargs_size ) ; offset += RISCV_STACK_ALIGN ( crtl -> args . pretend_args_size ) ;"
GCC,riscv,743,"Predict the next statement of this code snippet:
 <s> } if ( UNITS_PER_FP_ARG == <NUM_LIT> ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = <NUM_LIT> ; }"
GCC,riscv,744,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return align ;"
GCC,riscv,745,"Predict the next statement of this code snippet:
 <s> riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( use_restore_libcall ) frame -> mask = <NUM_LIT> ; riscv_for_each_saved_reg ( frame -> total_size - step2 , riscv_restore_reg ) ; if ( use_restore_libcall ) { frame -> mask = mask ; gcc_assert ( step2 >= frame -> save_libcall_adjustment ) ; step2 -= frame -> save_libcall_adjustment ; } if ( need_barrier_p ) riscv_emit_stack_tie ( ) ; if ( step2 > <NUM_LIT> ) { insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( step2 ) ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( use_restore_libcall ) { rtx dwarf = riscv_adjust_libcall_cfi_epilogue ( ) ; insn = emit_insn ( gen_gpr_restore ( GEN_INT ( riscv_save_libcall_count ( mask ) ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ;"
GCC,riscv,746,"Predict the next statement of this code snippet:
 <s> if ( riscv_use_save_libcall ( frame ) ) { rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; frame -> mask = <NUM_LIT> ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( gen_gpr_save ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; riscv_emit_stack_tie ( ) ; } if ( size > <NUM_LIT> ) { if ( SMALL_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; } else { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , RISCV_PROLOGUE_TEMP ( Pmode ) ) ) ;"
GCC,riscv,747,"Predict the next statement of this code snippet:
 <s> fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT> ) ) ;"
GCC,riscv,748,"Predict the next statement of this code snippet:
 <s> static void riscv_file_start ( void ) { default_file_start ( ) ;"
GCC,riscv,749,"Predict the next statement of this code snippet:
 <s> offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ;"
GCC,riscv,750,"Predict the next statement of this code snippet:
 <s> return riscv_get_arg_info ( & info , cum , mode , type , named , false ) ;"
GCC,riscv,751,"Predict the next statement of this code snippet:
 <s> struct riscv_arg_info info ; riscv_get_arg_info ( & info , cum , mode , type , named , false ) ;"
GCC,riscv,752,"Predict the next statement of this code snippet:
 <s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct riscv_arg_info info ; riscv_get_arg_info ( & info , cum , mode , type , named , false ) ;"
GCC,riscv,753,"Predict the next statement of this code snippet:
 <s> if ( TARGET_SAVE_RESTORE ) return false ; if ( cfun -> machine -> naked_p ) return false ;"
GCC,riscv,754,"Predict the next statement of this code snippet:
 <s> static bool riscv_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_SAVE_RESTORE ) return false ; if ( cfun -> machine -> naked_p ) return false ; return true ;"
GCC,riscv,755,"Predict the next statement of this code snippet:
 <s> info -> num_gprs = <NUM_LIT> ; info -> num_fprs = <NUM_LIT> ; if ( ! SCALAR_FLOAT_TYPE_P ( fields [ <NUM_LIT> ] . type ) ) std :: swap ( fregno , gregno ) ; return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , gregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; } } num_bytes = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; num_words = ( num_bytes + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( ! named && num_bytes != <NUM_LIT> && alignment > BITS_PER_WORD ) info -> gpr_offset += info -> gpr_offset & <NUM_LIT> ; info -> num_fprs = <NUM_LIT> ; info -> num_gprs = MIN ( num_words , MAX_ARGS_IN_REGISTERS - info -> gpr_offset ) ; info -> stack_p = ( num_words - info -> num_gprs ) != <NUM_LIT> ;"
GCC,riscv,756,"Predict the next statement of this code snippet:
 <s> if ( GP_REG_P ( regno ) ) { if ( ! GP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; } else if ( FP_REG_P ( regno ) ) { if ( ! FP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ; if ( GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_REG || ( ! call_used_regs [ regno ] && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_ARG ) ) return false ; }"
GCC,riscv,757,"Predict the next statement of this code snippet:
 <s> static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ;"
GCC,riscv,758,"Predict the next statement of this code snippet:
 <s> return ; } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) { base = riscv_force_temporary ( dest , base ) ;"
GCC,riscv,759,"Predict the next statement of this code snippet:
 <s> } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) { base = riscv_force_temporary ( dest , base ) ; riscv_emit_move ( dest , riscv_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; riscv_split_symbol ( dest , XEXP ( src , <NUM_LIT> ) , mode , & XEXP ( src , <NUM_LIT> ) ) ; riscv_emit_move ( dest , src ) ;"
GCC,riscv,760,"Predict the next statement of this code snippet:
 <s> riscv_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } if ( MEM_P ( dest ) && ! riscv_legitimate_address_p ( mode , XEXP ( dest , <NUM_LIT> ) , reload_completed ) ) { XEXP ( dest , <NUM_LIT> ) = riscv_force_address ( XEXP ( dest , <NUM_LIT> ) , mode ) ; }"
GCC,riscv,761,"Predict the next statement of this code snippet:
 <s> if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { riscv_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } if ( MEM_P ( dest ) && ! riscv_legitimate_address_p ( mode , XEXP ( dest , <NUM_LIT> ) , reload_completed ) ) { XEXP ( dest , <NUM_LIT> ) = riscv_force_address ( XEXP ( dest , <NUM_LIT> ) , mode ) ; } if ( MEM_P ( src ) && ! riscv_legitimate_address_p ( mode , XEXP ( src , <NUM_LIT> ) , reload_completed ) ) { XEXP ( src , <NUM_LIT> ) = riscv_force_address ( XEXP ( src , <NUM_LIT> ) , mode ) ; } return false ;"
GCC,riscv,762,"Predict the next statement of this code snippet:
 <s> if ( can_create_pseudo_p ( ) && num_ops > <NUM_LIT> && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) x = riscv_emit_set ( temp , x ) ;"
GCC,riscv,763,"Predict the next statement of this code snippet:
 <s> for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ;"
GCC,riscv,764,"Predict the next statement of this code snippet:
 <s> flag_pcc_struct_return = <NUM_LIT> ; if ( flag_pic ) g_switch_value = <NUM_LIT> ; if ( TARGET_MUL && ( target_flags_explicit & MASK_DIV ) == <NUM_LIT> ) target_flags |= MASK_DIV ; else if ( ! TARGET_MUL && TARGET_DIV ) error ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT && ( target_flags_explicit & MASK_FDIV ) == <NUM_LIT> ) target_flags |= MASK_FDIV ; cpu = riscv_parse_cpu ( riscv_tune_string ? riscv_tune_string : RISCV_TUNE_STRING_DEFAULT ) ; tune_info = optimize_size ? & optimize_size_tune_info : cpu -> tune_info ; riscv_slow_unaligned_access_p = ( cpu -> tune_info -> slow_unaligned_access || TARGET_STRICT_ALIGN ) ; if ( ( target_flags_explicit & MASK_STRICT_ALIGN ) == <NUM_LIT> && cpu -> tune_info -> slow_unaligned_access ) target_flags |= MASK_STRICT_ALIGN ; if ( riscv_branch_cost == <NUM_LIT> ) riscv_branch_cost = tune_info -> branch_cost ; init_machine_status = & riscv_init_machine_status ; if ( flag_pic ) riscv_cmodel = CM_PIC ; if ( ( target_flags_explicit & MASK_EXPLICIT_RELOCS ) == <NUM_LIT> ) if ( riscv_cmodel == CM_MEDLOW ) target_flags |= MASK_EXPLICIT_RELOCS ; if ( UNITS_PER_FP_ARG > ( TARGET_HARD_FLOAT ? UNITS_PER_FP_REG : <NUM_LIT> ) ) error ( <STR_LIT> , UNITS_PER_FP_ARG > <NUM_LIT> ? 'Q' : ( UNITS_PER_FP_ARG > <NUM_LIT> ? 'D' : 'F' ) ) ; if ( BITS_PER_WORD != POINTER_SIZE ) error ( <STR_LIT> , POINTER_SIZE ) ; riscv_stack_boundary = ABI_STACK_BOUNDARY ; if ( riscv_preferred_stack_boundary_arg ) { int min = ctz_hwi ( STACK_BOUNDARY / <NUM_LIT> ) ; int max = <NUM_LIT> ;"
GCC,riscv,765,"Predict the next statement of this code snippet:
 <s> if ( GP_REG_P ( REGNO ( dest ) ) ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return <STR_LIT> ; if ( TARGET_64BIT ) return <STR_LIT> ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return <STR_LIT> ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) {"
GCC,riscv,766,"Predict the next statement of this code snippet:
 <s> enum rtx_code dest_code , src_code ; machine_mode mode ; bool dbl_p ; dest_code = GET_CODE ( dest ) ; src_code = GET_CODE ( src ) ; mode = GET_MODE ( dest ) ; dbl_p = ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ; if ( dbl_p && riscv_split_64bit_move_p ( dest , src ) ) return <STR_LIT> ; if ( dest_code == REG && GP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) return dbl_p ? <STR_LIT> : <STR_LIT> ; if ( src_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( src_code == CONST_INT ) return <STR_LIT> ; if ( src_code == HIGH ) return <STR_LIT> ; if ( symbolic_operand ( src , VOIDmode ) ) switch ( riscv_classify_symbolic_expression ( src ) ) { case SYMBOL_GOT_DISP : return <STR_LIT> ; case SYMBOL_ABSOLUTE : return <STR_LIT> ; case SYMBOL_PCREL : return <STR_LIT> ; default : gcc_unreachable ( ) ; } } if ( ( src_code == REG && GP_REG_P ( REGNO ( src ) ) ) || ( src == CONST0_RTX ( mode ) ) ) { if ( dest_code == REG ) { if ( GP_REG_P ( REGNO ( dest ) ) ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return <STR_LIT> ; if ( TARGET_64BIT ) return <STR_LIT> ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return <STR_LIT> ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;"
GCC,riscv,767,"Predict the next statement of this code snippet:
 <s> if ( cum != NULL ) { riscv_get_arg_info ( & info , cum , mode , type , named , false ) ; if ( info . num_fprs ) return false ; } return ! IN_RANGE ( size , <NUM_LIT> , <NUM_LIT> * UNITS_PER_WORD ) ;"
GCC,riscv,768,"Predict the next statement of this code snippet:
 <s> x = gen_rtx_EXPR_LIST ( VOIDmode , x , const0_rtx ) ;"
GCC,riscv,769,"Predict the next statement of this code snippet:
 <s> gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == <NUM_LIT> ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ;"
GCC,riscv,770,"Predict the next statement of this code snippet:
 <s> if ( decl == NULL_TREE || current_function_decl == NULL_TREE || current_function_decl == error_mark_node || ! cfun -> machine ) return ;"
GCC,riscv,771,"Predict the next statement of this code snippet:
 <s> if ( decl == NULL_TREE || current_function_decl == NULL_TREE || current_function_decl == error_mark_node || ! cfun -> machine ) return ;"
GCC,riscv,772,"Predict the next statement of this code snippet:
 <s> riscv_move_integer ( hi , hi , hival ) ; riscv_move_integer ( lo , lo , loval ) ;"
GCC,riscv,773,"Predict the next statement of this code snippet:
 <s> riscv_move_integer ( lo , lo , loval ) ; hi = gen_rtx_fmt_ee ( ASHIFT , mode , hi , GEN_INT ( <NUM_LIT> ) ) ; hi = force_reg ( mode , hi ) ;"
GCC,riscv,774,"Predict the next statement of this code snippet:
 <s> bool riscv_split_symbol ( rtx temp , rtx addr , machine_mode mode , rtx * low_out ) { enum riscv_symbol_type symbol_type ; if ( ( GET_CODE ( addr ) == HIGH && mode == MAX_MACHINE_MODE ) || ! riscv_symbolic_constant_p ( addr , & symbol_type ) || riscv_symbol_insns ( symbol_type ) == <NUM_LIT> || ! riscv_split_symbol_type ( symbol_type ) ) return false ; if ( low_out ) switch ( symbol_type ) { case SYMBOL_ABSOLUTE : { rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = riscv_force_temporary ( temp , high ) ; * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; } break ; case SYMBOL_PCREL : { static unsigned seqno ; char buf [ <NUM_LIT> ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ;"
GCC,riscv,775,"Predict the next statement of this code snippet:
 <s> if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ( ! TARGET_STRICT_ALIGN || GET_MODE_BITSIZE ( mode ) > GET_MODE_ALIGNMENT ( mode ) ) ) return false ; return true ;"
GCC,riscv,776,"Predict the next statement of this code snippet:
 <s> } if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( addr . type == ADDRESS_LO_SUM ) n += riscv_symbol_insns ( addr . symbol_type ) - <NUM_LIT> ;"
GCC,riscv,777,"Predict the next statement of this code snippet:
 <s> bool riscv_epilogue_uses ( unsigned int regno ) { if ( regno == RETURN_ADDR_REGNUM ) return true ;"
GCC,riscv,778,"Predict the next statement of this code snippet:
 <s> static bool riscv_save_reg_p ( unsigned int regno ) { bool call_saved = ! global_regs [ regno ] && ! call_used_regs [ regno ] ; bool might_clobber = crtl -> saves_all_registers || df_regs_ever_live_p ( regno ) ;"
GCC,riscv,779,"Predict the next statement of this code snippet:
 <s> ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( ! nonzero_address_p ( addr ) ) SYMBOL_REF_WEAK ( label ) = <NUM_LIT> ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; * low_out = gen_rtx_LO_SUM ( Pmode , temp , label ) ; seqno ++ ; } break ; default :"
GCC,riscv,780,"Predict the next statement of this code snippet:
 <s> if ( TARGET_RVC && ! speed && riscv_mshorten_memrefs && mode == SImode && ! riscv_compressed_lw_address_p ( addr ) ) return riscv_address_insns ( addr , mode , false ) + <NUM_LIT> ;"
GCC,riscv,781,"Predict the next statement of this code snippet:
 <s> int riscv_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct riscv_address_info addr = { } ; int n = <NUM_LIT> ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) { return <NUM_LIT> ; } if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;"
GCC,riscv,782,"Predict the next statement of this code snippet:
 <s> offset = CONST_LOW_PART ( offset ) ; high = riscv_force_temporary ( temp , high , FALSE ) ;"
GCC,riscv,783,"Predict the next statement of this code snippet:
 <s> high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ; high = riscv_force_temporary ( temp , high , FALSE ) ; reg = riscv_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) , FALSE ) ; }"
GCC,riscv,784,"Predict the next statement of this code snippet:
 <s> * loop_reg = copy_addr_to_reg ( XEXP ( mem , <NUM_LIT> ) ) ;"
GCC,riscv,785,"Predict the next statement of this code snippet:
 <s> for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { reg = gen_rtx_REG ( SImode , regno ) ;"
GCC,riscv,786,"Predict the next statement of this code snippet:
 <s> static rtx riscv_adjust_libcall_cfi_epilogue ( ) { rtx dwarf = NULL_RTX ; rtx adjust_sp_rtx , reg ; int saved_size = cfun -> machine -> frame . save_libcall_adjustment ; adjust_sp_rtx = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( saved_size ) ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , adjust_sp_rtx , dwarf ) ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { reg = gen_rtx_REG ( SImode , regno ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ;"
GCC,riscv,787,"Predict the next statement of this code snippet:
 <s> int saved_size = cfun -> machine -> frame . save_libcall_adjustment ; int offset ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { if ( regno == RETURN_ADDR_REGNUM ) offset = saved_size - UNITS_PER_WORD ; else if ( regno == S0_REGNUM ) offset = saved_size - UNITS_PER_WORD * <NUM_LIT> ; else if ( regno == S1_REGNUM ) offset = saved_size - UNITS_PER_WORD * <NUM_LIT> ; else offset = saved_size - ( ( regno - S2_REGNUM + <NUM_LIT> ) * UNITS_PER_WORD ) ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; insn = gen_rtx_SET ( mem , reg ) ; dwarf = alloc_reg_note ( REG_CFA_OFFSET , insn , dwarf ) ; } adjust_sp_rtx = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - saved_size ) ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , adjust_sp_rtx , dwarf ) ; return dwarf ;"
GCC,riscv,788,"Predict the next statement of this code snippet:
 <s> for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { if ( regno == RETURN_ADDR_REGNUM ) offset = saved_size - UNITS_PER_WORD ; else if ( regno == S0_REGNUM ) offset = saved_size - UNITS_PER_WORD * <NUM_LIT> ; else if ( regno == S1_REGNUM ) offset = saved_size - UNITS_PER_WORD * <NUM_LIT> ; else offset = saved_size - ( ( regno - S2_REGNUM + <NUM_LIT> ) * UNITS_PER_WORD ) ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; insn = gen_rtx_SET ( mem , reg ) ; dwarf = alloc_reg_note ( REG_CFA_OFFSET , insn , dwarf ) ; } adjust_sp_rtx = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - saved_size ) ) ;"
GCC,riscv,789,"Predict the next statement of this code snippet:
 <s> return ! riscv_naked_function_p ( current_function_decl ) ;"
GCC,riscv,790,"Predict the next statement of this code snippet:
 <s> static bool riscv_allocate_stack_slots_for_args ( ) { return ! riscv_naked_function_p ( current_function_decl ) ;"
GCC,riscv,791,"Predict the next statement of this code snippet:
 <s> riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , generic_arg . mode , generic_arg . type , generic_arg . named , false ) ; return arg . stack_p ? arg . num_gprs * UNITS_PER_WORD : <NUM_LIT> ;"
GCC,riscv,792,"Predict the next statement of this code snippet:
 <s> static unsigned HOST_WIDE_INT riscv_asan_shadow_offset ( void ) { return TARGET_64BIT ? ( HOST_WIDE_INT_1 << <NUM_LIT> ) : <NUM_LIT> ;"
GCC,riscv,793,"Predict the next statement of this code snippet:
 <s> static unsigned HOST_WIDE_INT riscv_asan_shadow_offset ( void ) {"
GCC,riscv,794,"Predict the next statement of this code snippet:
 <s> static int riscv_binary_cost ( rtx x , int single_insns , int double_insns ) { if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * <NUM_LIT> ) return COSTS_N_INSNS ( double_insns ) ;"
GCC,riscv,795,"Predict the next statement of this code snippet:
 <s> leftover = length % bytes_per_iter ; length -= leftover ; riscv_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; riscv_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , <NUM_LIT> , <NUM_LIT> , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; riscv_block_move_straight ( dest , src , bytes_per_iter ) ; riscv_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ;"
GCC,riscv,796,"Predict the next statement of this code snippet:
 <s> static void riscv_block_move_straight ( rtx dest , rtx src , unsigned HOST_WIDE_INT length ) { unsigned HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; enum machine_mode mode ; rtx * regs ; bits = MAX ( BITS_PER_UNIT , MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ) ; mode = mode_for_size ( bits , MODE_INT , <NUM_LIT> ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ;"
GCC,riscv,797,"Predict the next statement of this code snippet:
 <s> for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) riscv_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ;"
GCC,riscv,798,"Predict the next statement of this code snippet:
 <s> } shifted_val = value << shift ; alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = LSHIFTRT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; }"
GCC,riscv,799,"Predict the next statement of this code snippet:
 <s> codes [ <NUM_LIT> ] . value = value ; return <NUM_LIT> ; } if ( TARGET_ZBS && SINGLE_BIT_MASK_OPERAND ( value ) ) { codes [ <NUM_LIT> ] . code = UNKNOWN ; codes [ <NUM_LIT> ] . value = value ; return <NUM_LIT> ; } if ( low_part != <NUM_LIT> && ( mode != HImode || value - low_part <= ( ( <NUM_LIT> << ( GET_MODE_BITSIZE ( HImode ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) ) { alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , value - low_part , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = PLUS ; alt_codes [ alt_cost - <NUM_LIT> ] . value = low_part ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } } if ( cost > <NUM_LIT> && ( low_part < <NUM_LIT> || mode == HImode ) ) { alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , value ^ low_part , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = XOR ;"
GCC,riscv,800,"Predict the next statement of this code snippet:
 <s> if ( ! riscv_tls_symbol ) riscv_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; func = gen_rtx_MEM ( FUNCTION_MODE , riscv_tls_symbol ) ; start_sequence ( ) ; emit_insn ( riscv_got_load_tls_gd ( a0 , sym ) ) ; insn = emit_call_insn ( gen_call_value ( result , func , const0_rtx , NULL ) ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ;"
GCC,riscv,801,"Predict the next statement of this code snippet:
 <s> emit_insn ( riscv_got_load_tls_gd ( a0 , sym ) ) ; insn = emit_call_insn ( gen_call_value ( result , func , const0_rtx , NULL ) ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ;"
GCC,riscv,802,"Predict the next statement of this code snippet:
 <s> static bool riscv_cannot_copy_insn_p ( rtx_insn * insn ) { return recog_memoized ( insn ) >= <NUM_LIT> && get_attr_cannot_copy ( insn ) ;"
GCC,riscv,803,"Predict the next statement of this code snippet:
 <s> split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > <NUM_LIT> ) return true ; if ( flag_pic ) return true ; }"
GCC,riscv,804,"Predict the next statement of this code snippet:
 <s> return true ; } break ; case LEU : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( plus_one != <NUM_LIT> ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ;"
GCC,riscv,805,"Predict the next statement of this code snippet:
 <s> } break ; case LEU : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( plus_one != <NUM_LIT> ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ;"
GCC,riscv,806,"Predict the next statement of this code snippet:
 <s> static bool riscv_can_change_mode_class ( machine_mode , machine_mode , reg_class_t rclass ) {"
GCC,riscv,807,"Predict the next statement of this code snippet:
 <s> static bool riscv_can_change_mode_class ( machine_mode , machine_mode , reg_class_t rclass ) { return ! reg_classes_intersect_p ( FP_REGS , rclass ) ;"
GCC,riscv,808,"Predict the next statement of this code snippet:
 <s> static bool riscv_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM ) ;"
GCC,riscv,809,"Predict the next statement of this code snippet:
 <s> bool riscv_can_use_return_insn ( void ) {"
GCC,riscv,810,"Predict the next statement of this code snippet:
 <s> static enum riscv_symbol_type riscv_classify_symbol ( const_rtx x ) {"
GCC,riscv,811,"Predict the next statement of this code snippet:
 <s> if ( UNSPEC_ADDRESS_P ( x ) ) return UNSPEC_ADDRESS_TYPE ( x ) ;"
GCC,riscv,812,"Predict the next statement of this code snippet:
 <s> split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) return UNSPEC_ADDRESS_TYPE ( x ) ; return riscv_classify_symbol ( x ) ;"
GCC,riscv,813,"Predict the next statement of this code snippet:
 <s> static unsigned char riscv_class_max_nregs ( reg_class_t rclass , machine_mode mode ) {"
GCC,riscv,814,"Predict the next statement of this code snippet:
 <s> struct riscv_address_info addr ; bool result = riscv_classify_address ( & addr , x , GET_MODE ( x ) , reload_completed ) ; if ( ! result || addr . type != ADDRESS_REG || ( reload_completed && ! riscv_compressed_reg_p ( REGNO ( addr . reg ) ) && addr . reg != stack_pointer_rtx ) || ! riscv_compressed_lw_offset_p ( addr . offset ) ) return false ; return result ;"
GCC,riscv,815,"Predict the next statement of this code snippet:
 <s> static bool riscv_compressed_lw_offset_p ( rtx x ) { return ( CONST_INT_P ( x ) && ( INTVAL ( x ) & <NUM_LIT> ) == <NUM_LIT> && IN_RANGE ( INTVAL ( x ) , <NUM_LIT> , CSW_MAX_OFFSET ) ) ;"
GCC,riscv,816,"Predict the next statement of this code snippet:
 <s> return ( CONST_INT_P ( x ) && ( INTVAL ( x ) & <NUM_LIT> ) == <NUM_LIT> && IN_RANGE ( INTVAL ( x ) , <NUM_LIT> , CSW_MAX_OFFSET ) ) ;"
GCC,riscv,817,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT offset ; bool interrupt_save_prologue_temp = false ; unsigned int regno , i , num_x_saved = <NUM_LIT> , num_f_saved = <NUM_LIT> ; frame = & cfun -> machine -> frame ; if ( cfun -> machine -> interrupt_handler_p ) { HOST_WIDE_INT step1 = riscv_first_stack_step ( frame ) ; if ( ! SMALL_OPERAND ( frame -> total_size - step1 ) ) interrupt_save_prologue_temp = true ; } memset ( frame , <NUM_LIT> , sizeof ( * frame ) ) ; if ( ! cfun -> machine -> naked_p ) { for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) || ( interrupt_save_prologue_temp && ( regno == RISCV_PROLOGUE_TEMP_REGNUM ) ) ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( crtl -> calls_eh_return ) for ( i = <NUM_LIT> ; ( regno = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( TARGET_HARD_FLOAT ) for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) ) frame -> fmask |= <NUM_LIT> << ( regno - FP_REG_FIRST ) , num_f_saved ++ ; } offset = RISCV_STACK_ALIGN ( crtl -> outgoing_args_size ) ; offset += RISCV_STACK_ALIGN ( get_frame_size ( ) ) ; frame -> frame_pointer_offset = offset ; if ( frame -> fmask ) offset += RISCV_STACK_ALIGN ( num_f_saved * UNITS_PER_FP_REG ) ; frame -> fp_sp_offset = offset - UNITS_PER_FP_REG ; if ( frame -> mask ) { unsigned x_save_size = RISCV_STACK_ALIGN ( num_x_saved * UNITS_PER_WORD ) ; unsigned num_save_restore = <NUM_LIT> + riscv_save_libcall_count ( frame -> mask ) ; if ( RISCV_STACK_ALIGN ( num_save_restore * UNITS_PER_WORD ) == x_save_size ) { if ( TARGET_RVE ) x_save_size = <NUM_LIT> * UNITS_PER_WORD ; frame -> save_libcall_adjustment = x_save_size ; } offset += x_save_size ; } frame -> gp_sp_offset = offset - UNITS_PER_WORD ; frame -> hard_frame_pointer_offset = offset ; offset += RISCV_STACK_ALIGN ( cfun -> machine -> varargs_size ) ; offset += RISCV_STACK_ALIGN ( crtl -> args . pretend_args_size ) ;"
GCC,riscv,818,"Predict the next statement of this code snippet:
 <s> } if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = <NUM_LIT> ; } if ( UNITS_PER_FP_ARG == <NUM_LIT> ) {"
GCC,riscv,819,"Predict the next statement of this code snippet:
 <s> case CONST_DOUBLE : case CONST_VECTOR : return x == CONST0_RTX ( GET_MODE ( x ) ) ? <NUM_LIT> : <NUM_LIT> ; case CONST : if ( riscv_symbolic_constant_p ( x , & symbol_type ) ) return riscv_symbol_insns ( symbol_type ) ; split_const ( x , & x , & offset ) ;"
GCC,riscv,820,"Predict the next statement of this code snippet:
 <s> if ( startswith ( s -> named . name , <STR_LIT> ) ) { char * name = ( char * ) alloca ( strlen ( s -> named . name ) + <NUM_LIT> ) ; sprintf ( name , <STR_LIT> , s -> named . name + <NUM_LIT> ) ; return get_section ( name , s -> named . common . flags , NULL ) ; } if ( s == data_section ) return sdata_section ;"
GCC,riscv,821,"Predict the next statement of this code snippet:
 <s> static section * riscv_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { section * s = default_elf_select_rtx_section ( mode , x , align ) ; if ( riscv_size_ok_for_small_data_p ( GET_MODE_SIZE ( mode ) ) ) { if ( startswith ( s -> named . name , <STR_LIT> ) ) { char * name = ( char * ) alloca ( strlen ( s -> named . name ) + <NUM_LIT> ) ;"
GCC,riscv,822,"Predict the next statement of this code snippet:
 <s> fprintf ( asm_out_file , <STR_LIT> , TARGET_STRICT_ALIGN ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,riscv,823,"Predict the next statement of this code snippet:
 <s> case UNORDERED : * code = EQ ; case ORDERED : tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; case UNEQ : * code = EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; break ; case LTGT : tmp0 = riscv_force_binary ( word_mode , LT , cmp_op0 , cmp_op1 ) ; tmp1 = riscv_force_binary ( word_mode , GT , cmp_op0 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , IOR , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; default :"
GCC,riscv,824,"Predict the next statement of this code snippet:
 <s> static void riscv_emit_int_order_test ( enum rtx_code code , bool * invert_ptr , rtx target , rtx cmp0 , rtx cmp1 ) { machine_mode mode ; mode = GET_MODE ( cmp0 ) ; if ( riscv_canonicalize_int_order_test ( & code , & cmp1 , mode ) ) riscv_emit_binary ( code , target , cmp0 , cmp1 ) ; else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! riscv_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; riscv_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == <NUM_LIT> ) {"
GCC,riscv,825,"Predict the next statement of this code snippet:
 <s> rtx riscv_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ;"
GCC,riscv,826,"Predict the next statement of this code snippet:
 <s> rtx riscv_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ;"
GCC,riscv,827,"Predict the next statement of this code snippet:
 <s> static rtx riscv_emit_set ( rtx target , rtx src ) {"
GCC,riscv,828,"Predict the next statement of this code snippet:
 <s> static void riscv_emit_stack_tie ( void ) { if ( Pmode == SImode ) emit_insn ( gen_stack_tiesi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; else emit_insn ( gen_stack_tiedi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ;"
GCC,riscv,829,"Predict the next statement of this code snippet:
 <s> if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( epilogue_completed && cfun -> machine -> interrupt_handler_p ) {"
GCC,riscv,830,"Predict the next statement of this code snippet:
 <s> if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( epilogue_completed && cfun -> machine -> interrupt_handler_p ) { if ( df_regs_ever_live_p ( regno ) || ( ! crtl -> is_leaf && call_used_or_fixed_reg_p ( regno ) ) ) return true ;"
GCC,riscv,831,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = min_iter_words ; i < min_iter_words * <NUM_LIT> - <NUM_LIT> ; i ++ ) { unsigned cur_cost = iter_words + words % iter_words ; unsigned new_cost = i + words % i ; if ( new_cost <= cur_cost ) iter_words = i ; } riscv_block_move_loop ( dest , src , bytes , iter_words * UNITS_PER_WORD ) ; return true ; } } return false ;"
GCC,riscv,832,"Predict the next statement of this code snippet:
 <s> void riscv_expand_conditional_branch ( rtx label , rtx_code code , rtx op0 , rtx op1 ) { if ( FLOAT_MODE_P ( GET_MODE ( op1 ) ) ) riscv_emit_float_compare ( & code , & op0 , & op1 ) ; else riscv_emit_int_compare ( & code , & op0 , & op1 ) ; rtx condition = gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ;"
GCC,riscv,833,"Predict the next statement of this code snippet:
 <s> riscv_emit_int_compare ( & code , & op0 , & op1 ) ;"
GCC,riscv,834,"Predict the next statement of this code snippet:
 <s> } if ( ( style == NORMAL_RETURN ) && riscv_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } epilogue_cfa_sp_offset = <NUM_LIT> ; if ( cfun -> calls_alloca ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( - frame -> hard_frame_pointer_offset ) ; if ( ! SMALL_OPERAND ( INTVAL ( adjust ) ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_value = gen_rtx_PLUS ( Pmode , hard_frame_pointer_rtx , GEN_INT ( - frame -> hard_frame_pointer_offset ) ) ; rtx cfa_adjust_rtx = gen_rtx_SET ( stack_pointer_rtx , cfa_adjust_value ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { step2 = riscv_first_stack_step ( frame ) ; step1 -= step2 ; } if ( step1 > <NUM_LIT> ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( step1 ) ; if ( ! SMALL_OPERAND ( step1 ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } else if ( frame_pointer_needed ) { epilogue_cfa_sp_offset = step2 ; } if ( use_restore_libcall ) frame -> mask = <NUM_LIT> ; riscv_for_each_saved_reg ( frame -> total_size - step2 , riscv_restore_reg , true , style == EXCEPTION_RETURN ) ; if ( use_restore_libcall ) { frame -> mask = mask ; gcc_assert ( step2 >= frame -> save_libcall_adjustment ) ; step2 -= frame -> save_libcall_adjustment ; } if ( need_barrier_p ) riscv_emit_stack_tie ( ) ; if ( step2 > <NUM_LIT> ) {"
GCC,riscv,835,"Predict the next statement of this code snippet:
 <s> void riscv_expand_float_scc ( rtx target , enum rtx_code code , rtx op0 , rtx op1 ) { riscv_emit_float_compare ( & code , & op0 , & op1 ) ;"
GCC,riscv,836,"Predict the next statement of this code snippet:
 <s> riscv_emit_float_compare ( & code , & op0 , & op1 ) ; rtx cmp = riscv_force_binary ( word_mode , code , op0 , op1 ) ; riscv_emit_set ( target , lowpart_subreg ( SImode , cmp , word_mode ) ) ;"
GCC,riscv,837,"Predict the next statement of this code snippet:
 <s> op0 = force_reg ( word_mode , op0 ) ; if ( code == EQ || code == NE ) { rtx zie = riscv_zero_if_equal ( op0 , op1 ) ; riscv_emit_binary ( code , target , zie , const0_rtx ) ; } else riscv_emit_int_order_test ( code , <NUM_LIT> , target , op0 , op1 ) ;"
GCC,riscv,838,"Predict the next statement of this code snippet:
 <s> if ( code == EQ || code == NE ) { rtx zie = riscv_zero_if_equal ( op0 , op1 ) ;"
GCC,riscv,839,"Predict the next statement of this code snippet:
 <s> if ( cfun -> machine -> naked_p ) return ; if ( riscv_use_save_libcall ( frame ) ) { rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( riscv_gen_gpr_save_insn ( frame ) ) ; frame -> mask = <NUM_LIT> ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg , false , false ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; riscv_emit_stack_tie ( ) ; } if ( size > <NUM_LIT> ) { if ( SMALL_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; } else { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , RISCV_PROLOGUE_TEMP ( Pmode ) ) ) ; insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ; insn = gen_rtx_SET ( stack_pointer_rtx , insn ) ;"
GCC,riscv,840,"Predict the next statement of this code snippet:
 <s> if ( cfun -> machine -> naked_p ) return ; if ( riscv_use_save_libcall ( frame ) ) { rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( riscv_gen_gpr_save_insn ( frame ) ) ; frame -> mask = <NUM_LIT> ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ;"
GCC,riscv,841,"Predict the next statement of this code snippet:
 <s> if ( GET_MODE_SIZE ( word_mode ) > GET_MODE_SIZE ( GET_MODE ( * op0 ) ) ) { if ( unsigned_condition ( code ) == code && ( GET_MODE ( * op0 ) == QImode && ! ( GET_CODE ( * op0 ) == SUBREG && SUBREG_PROMOTED_VAR_P ( * op0 ) && SUBREG_PROMOTED_SIGNED_P ( * op0 ) && ( CONST_INT_P ( * op1 ) || ( GET_CODE ( * op1 ) == SUBREG && SUBREG_PROMOTED_VAR_P ( * op1 ) && SUBREG_PROMOTED_SIGNED_P ( * op1 ) ) ) ) ) ) { * op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ; if ( CONST_INT_P ( * op1 ) ) * op1 = GEN_INT ( ( uint8_t ) INTVAL ( * op1 ) ) ; else * op1 = gen_rtx_ZERO_EXTEND ( word_mode , * op1 ) ; } else { * op0 = gen_rtx_SIGN_EXTEND ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = gen_rtx_SIGN_EXTEND ( word_mode , * op1 ) ; } }"
GCC,riscv,842,"Predict the next statement of this code snippet:
 <s> static void riscv_extend_comparands ( rtx_code code , rtx * op0 , rtx * op1 ) { if ( GET_MODE_SIZE ( word_mode ) > GET_MODE_SIZE ( GET_MODE ( * op0 ) ) ) { if ( unsigned_condition ( code ) == code && ( GET_MODE ( * op0 ) == QImode && ! ( GET_CODE ( * op0 ) == SUBREG && SUBREG_PROMOTED_VAR_P ( * op0 ) && SUBREG_PROMOTED_SIGNED_P ( * op0 ) && ( CONST_INT_P ( * op1 ) || ( GET_CODE ( * op1 ) == SUBREG && SUBREG_PROMOTED_VAR_P ( * op1 ) && SUBREG_PROMOTED_SIGNED_P ( * op1 ) ) ) ) ) ) { * op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ; if ( CONST_INT_P ( * op1 ) ) * op1 = GEN_INT ( ( uint8_t ) INTVAL ( * op1 ) ) ; else * op1 = gen_rtx_ZERO_EXTEND ( word_mode , * op1 ) ;"
GCC,riscv,843,"Predict the next statement of this code snippet:
 <s> if ( unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE ( op ) == SImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_ZBB ) { if ( ! unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( GET_MODE ( op ) == HImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; } if ( ! unsigned_p && GET_MODE ( op ) == SImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; return COSTS_N_INSNS ( <NUM_LIT> ) ;"
GCC,riscv,844,"Predict the next statement of this code snippet:
 <s> if ( MEM_P ( op ) ) return <NUM_LIT> ; if ( unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE ( op ) == SImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_ZBB ) { if ( ! unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ;"
GCC,riscv,845,"Predict the next statement of this code snippet:
 <s> default_file_start ( ) ; fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT> ) ) ; if ( ! riscv_mrelax ) fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,riscv,846,"Predict the next statement of this code snippet:
 <s> gcc_assert ( min_first_step <= max_first_step ) ; if ( ! SMALL_OPERAND ( min_second_step ) && frame -> total_size % IMM_REACH < IMM_REACH / <NUM_LIT> && frame -> total_size % IMM_REACH >= min_first_step ) return frame -> total_size % IMM_REACH ; if ( TARGET_RVC ) { if ( IN_RANGE ( min_second_step , <NUM_LIT> , ( TARGET_64BIT ? SDSP_REACH : SWSP_REACH ) ) ) return MAX ( min_second_step , min_first_step ) ; else if ( ! SMALL_OPERAND ( min_second_step ) ) return min_first_step ; } return max_first_step ;"
GCC,riscv,847,"Predict the next statement of this code snippet:
 <s> if ( ! type || TREE_CODE ( type ) != RECORD_TYPE ) return - <NUM_LIT> ;"
GCC,riscv,848,"Predict the next statement of this code snippet:
 <s> static int riscv_flatten_aggregate_argument ( const_tree type , riscv_aggregate_field fields [ <NUM_LIT> ] , bool ignore_zero_width_bit_field_p ) { if ( ! type || TREE_CODE ( type ) != RECORD_TYPE ) return - <NUM_LIT> ;"
GCC,riscv,849,"Predict the next statement of this code snippet:
 <s> n = riscv_flatten_aggregate_field ( TREE_TYPE ( f ) , fields , n , pos , ignore_zero_width_bit_field_p ) ; } if ( n < <NUM_LIT> ) return - <NUM_LIT> ; } return n ; case ARRAY_TYPE : { HOST_WIDE_INT n_elts ; riscv_aggregate_field subfields [ <NUM_LIT> ] ; tree index = TYPE_DOMAIN ( type ) ; tree elt_size = TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) ; int n_subfields = riscv_flatten_aggregate_field ( TREE_TYPE ( type ) , subfields , <NUM_LIT> , offset , ignore_zero_width_bit_field_p ) ; if ( n_subfields <= <NUM_LIT> || ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || ! tree_fits_uhwi_p ( elt_size ) ) return - <NUM_LIT> ; n_elts = <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ; gcc_assert ( n_elts >= <NUM_LIT> ) ; for ( HOST_WIDE_INT i = <NUM_LIT> ; i < n_elts ; i ++ ) for ( int j = <NUM_LIT> ; j < n_subfields ; j ++ ) { if ( n >= <NUM_LIT> ) return - <NUM_LIT> ; fields [ n ] = subfields [ j ] ; fields [ n ++ ] . offset += i * tree_to_uhwi ( elt_size ) ; } return n ; } case COMPLEX_TYPE : { if ( n != <NUM_LIT> ) return - <NUM_LIT> ; HOST_WIDE_INT elt_size = GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( type ) ) ) ; if ( elt_size <= UNITS_PER_FP_ARG ) { fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset = offset ; fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ;"
GCC,riscv,850,"Predict the next statement of this code snippet:
 <s> static rtx riscv_force_address ( rtx x , machine_mode mode ) { if ( ! riscv_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ; return x ;"
GCC,riscv,851,"Predict the next statement of this code snippet:
 <s> static rtx riscv_force_binary ( machine_mode mode , enum rtx_code code , rtx x , rtx y ) {"
GCC,riscv,852,"Predict the next statement of this code snippet:
 <s> return riscv_emit_binary ( code , gen_reg_rtx ( mode ) , x , y ) ;"
GCC,riscv,853,"Predict the next statement of this code snippet:
 <s> for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { bool handle_reg = TRUE ; if ( epilogue && ! maybe_eh_return && crtl -> calls_eh_return ) { unsigned int i , regnum ; for ( i = <NUM_LIT> ; ( regnum = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) if ( regno == regnum ) { handle_reg = FALSE ; break ; } } if ( handle_reg ) riscv_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ;"
GCC,riscv,854,"Predict the next statement of this code snippet:
 <s> rtx set = gen_rtx_SET ( mem , reg ) ;"
GCC,riscv,855,"Predict the next statement of this code snippet:
 <s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct riscv_arg_info info ; if ( arg . end_marker_p ( ) ) return NULL ; return riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ;"
GCC,riscv,856,"Predict the next statement of this code snippet:
 <s> struct riscv_arg_info info ; if ( arg . end_marker_p ( ) ) return NULL ;"
GCC,riscv,857,"Predict the next statement of this code snippet:
 <s> struct riscv_arg_info info ; riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ;"
GCC,riscv,858,"Predict the next statement of this code snippet:
 <s> riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ;"
GCC,riscv,859,"Predict the next statement of this code snippet:
 <s> else alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ;"
GCC,riscv,860,"Predict the next statement of this code snippet:
 <s> if ( cfun -> machine -> naked_p ) return false ; if ( cfun -> machine -> interrupt_handler_p ) return false ;"
GCC,riscv,861,"Predict the next statement of this code snippet:
 <s> mode = TYPE_MODE ( type ) ; mode = promote_function_mode ( type , mode , & unsigned_p , func , <NUM_LIT> ) ; } memset ( & args , <NUM_LIT> , sizeof args ) ;"
GCC,riscv,862,"Predict the next statement of this code snippet:
 <s> case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno ) ; case MODE_COMPLEX_FLOAT :"
GCC,riscv,863,"Predict the next statement of this code snippet:
 <s> unsigned fpr_base = return_p ? FP_RETURN : FP_ARG_FIRST ; unsigned gpr_base = return_p ? GP_RETURN : GP_ARG_FIRST ; unsigned alignment = riscv_function_arg_boundary ( mode , type ) ; memset ( info , <NUM_LIT> , sizeof ( * info ) ) ; info -> gpr_offset = cum -> num_gprs ; info -> fpr_offset = cum -> num_fprs ; if ( named ) { riscv_aggregate_field fields [ <NUM_LIT> ] ; unsigned fregno = fpr_base + info -> fpr_offset ; unsigned gregno = gpr_base + info -> gpr_offset ; if ( ( info -> num_fprs = riscv_pass_aggregate_in_fpr_pair_p ( type , fields ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( info -> num_fprs ) { case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT :"
GCC,riscv,864,"Predict the next statement of this code snippet:
 <s> if ( ( TREE_CODE ( decl ) != FUNCTION_DECL ) || ( ! riscv_interrupt_type_p ( TREE_TYPE ( decl ) ) ) ) return UNKNOWN_MODE ; tree attr_args = TREE_VALUE ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) ; if ( attr_args && TREE_CODE ( TREE_VALUE ( attr_args ) ) != VOID_TYPE ) { const char * string = TREE_STRING_POINTER ( TREE_VALUE ( attr_args ) ) ; if ( ! strcmp ( string , <STR_LIT> ) ) return USER_MODE ; else if ( ! strcmp ( string , <STR_LIT> ) ) return SUPERVISOR_MODE ;"
GCC,riscv,865,"Predict the next statement of this code snippet:
 <s> static enum riscv_privilege_levels riscv_get_interrupt_type ( tree decl ) { gcc_assert ( decl != NULL_TREE ) ; if ( ( TREE_CODE ( decl ) != FUNCTION_DECL ) || ( ! riscv_interrupt_type_p ( TREE_TYPE ( decl ) ) ) ) return UNKNOWN_MODE ; tree attr_args = TREE_VALUE ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) ; if ( attr_args && TREE_CODE ( TREE_VALUE ( attr_args ) ) != VOID_TYPE ) { const char * string = TREE_STRING_POINTER ( TREE_VALUE ( attr_args ) ) ; if ( ! strcmp ( string , <STR_LIT> ) ) return USER_MODE ; else if ( ! strcmp ( string , <STR_LIT> ) ) return SUPERVISOR_MODE ; else return MACHINE_MODE ;"
GCC,riscv,866,"Predict the next statement of this code snippet:
 <s> if ( Pmode == DImode ) return gen_got_load_tls_gddi ( dest , sym ) ;"
GCC,riscv,867,"Predict the next statement of this code snippet:
 <s> static rtx riscv_got_load_tls_gd ( rtx dest , rtx sym ) { if ( Pmode == DImode ) return gen_got_load_tls_gddi ( dest , sym ) ;"
GCC,riscv,868,"Predict the next statement of this code snippet:
 <s> static rtx riscv_got_load_tls_ie ( rtx dest , rtx sym ) { if ( Pmode == DImode ) return gen_got_load_tls_iedi ( dest , sym ) ;"
GCC,riscv,869,"Predict the next statement of this code snippet:
 <s> if ( Pmode == DImode ) return gen_got_load_tls_iedi ( dest , sym ) ;"
GCC,riscv,870,"Predict the next statement of this code snippet:
 <s> bool riscv_gpr_save_operation_p ( rtx op ) { unsigned len = XVECLEN ( op , <NUM_LIT> ) ; if ( len > ARRAY_SIZE ( gpr_save_reg_order ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < len ; i ++ ) { rtx elt = XVECEXP ( op , <NUM_LIT> , i ) ; if ( i == <NUM_LIT> ) {"
GCC,riscv,871,"Predict the next statement of this code snippet:
 <s> if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_REG - <NUM_LIT> ) / UNITS_PER_FP_REG ;"
GCC,riscv,872,"Predict the next statement of this code snippet:
 <s> static unsigned int riscv_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_REG - <NUM_LIT> ) / UNITS_PER_FP_REG ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;"
GCC,riscv,873,"Predict the next statement of this code snippet:
 <s> case LT : case LTU : return SMALL_OPERAND ( x ) ; case LE : return SMALL_OPERAND ( x + <NUM_LIT> ) ; case LEU : return SMALL_OPERAND ( x + <NUM_LIT> ) && x + <NUM_LIT> != <NUM_LIT> ; case GE : case GEU : return x == <NUM_LIT> ; default :"
GCC,riscv,874,"Predict the next statement of this code snippet:
 <s> if ( to == HARD_FRAME_POINTER_REGNUM ) dest = cfun -> machine -> frame . hard_frame_pointer_offset ; else if ( to == STACK_POINTER_REGNUM ) dest = <NUM_LIT> ; else gcc_unreachable ( ) ; if ( from == FRAME_POINTER_REGNUM ) src = cfun -> machine -> frame . frame_pointer_offset ; else if ( from == ARG_POINTER_REGNUM ) src = cfun -> machine -> frame . arg_pointer_offset ;"
GCC,riscv,875,"Predict the next statement of this code snippet:
 <s> static struct machine_function * riscv_init_machine_status ( void ) {"
GCC,riscv,876,"Predict the next statement of this code snippet:
 <s> static int riscv_integer_cost ( HOST_WIDE_INT val ) { struct riscv_integer_op codes [ RISCV_MAX_INTEGER_OPS ] ; return MIN ( riscv_build_integer ( codes , val , VOIDmode ) , riscv_split_integer_cost ( val ) ) ;"
GCC,riscv,877,"Predict the next statement of this code snippet:
 <s> struct riscv_integer_op codes [ RISCV_MAX_INTEGER_OPS ] ; return MIN ( riscv_build_integer ( codes , val , VOIDmode ) , riscv_split_integer_cost ( val ) ) ;"
GCC,riscv,878,"Predict the next statement of this code snippet:
 <s> static bool riscv_interrupt_type_p ( tree type ) {"
GCC,riscv,879,"Predict the next statement of this code snippet:
 <s> return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL ;"
GCC,riscv,880,"Predict the next statement of this code snippet:
 <s> return cmp1 == const1_rtx ; case LT : case LTU : return arith_operand ( cmp1 , VOIDmode ) ; case LE : return sle_operand ( cmp1 , VOIDmode ) ; case LEU : return sleu_operand ( cmp1 , VOIDmode ) ; default : gcc_unreachable ( ) ;"
GCC,riscv,881,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( x ) == VAR_DECL && DECL_SECTION_NAME ( x ) ) { const char * sec = DECL_SECTION_NAME ( x ) ; return strcmp ( sec , <STR_LIT> ) == <NUM_LIT> || strcmp ( sec , <STR_LIT> ) == <NUM_LIT> ; }"
GCC,riscv,882,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( x ) == VAR_DECL && DECL_SECTION_NAME ( x ) ) { const char * sec = DECL_SECTION_NAME ( x ) ; return strcmp ( sec , <STR_LIT> ) == <NUM_LIT> || strcmp ( sec , <STR_LIT> ) == <NUM_LIT> ; } return riscv_size_ok_for_small_data_p ( int_size_in_bytes ( TREE_TYPE ( x ) ) ) ;"
GCC,riscv,883,"Predict the next statement of this code snippet:
 <s> static int riscv_issue_rate ( void ) {"
GCC,riscv,884,"Predict the next statement of this code snippet:
 <s> return riscv_classify_address ( & addr , x , mode , strict_p ) ;"
GCC,riscv,885,"Predict the next statement of this code snippet:
 <s> static bool riscv_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p ) {"
GCC,riscv,886,"Predict the next statement of this code snippet:
 <s> static bool riscv_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return riscv_const_insns ( x ) > <NUM_LIT> ;"
GCC,riscv,887,"Predict the next statement of this code snippet:
 <s> static bool riscv_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) {"
GCC,riscv,888,"Predict the next statement of this code snippet:
 <s> static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ; if ( riscv_split_symbol ( NULL , x , mode , & addr , FALSE ) ) return riscv_force_address ( addr , mode ) ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) != <NUM_LIT> ) { rtx base = XEXP ( x , <NUM_LIT> ) ; HOST_WIDE_INT offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( ! riscv_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; if ( optimize_function_for_size_p ( cfun ) && ( strcmp ( current_pass -> name , <STR_LIT> ) == <NUM_LIT> ) && mode == SImode ) addr = riscv_shorten_lw_offset ( base , offset ) ; else addr = riscv_add_offset ( NULL , base , offset ) ;"
GCC,riscv,889,"Predict the next statement of this code snippet:
 <s> riscv_emit_move ( reg , addr ) ; return reg ; } return addr ;"
GCC,riscv,890,"Predict the next statement of this code snippet:
 <s> if ( ! call_insn_operand ( addr , VOIDmode ) ) {"
GCC,riscv,891,"Predict the next statement of this code snippet:
 <s> riscv_move_integer ( dest , dest , INTVAL ( src ) , mode , FALSE ) ; return ; } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src , FALSE ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) { base = riscv_force_temporary ( dest , base , FALSE ) ; riscv_emit_move ( dest , riscv_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; }"
GCC,riscv,892,"Predict the next statement of this code snippet:
 <s> tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( riscv_got_load_tls_ie ( tmp , loc ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC :"
GCC,riscv,893,"Predict the next statement of this code snippet:
 <s> if ( ! flag_pic ) model = TLS_MODEL_LOCAL_EXEC ; switch ( model ) { case TLS_MODEL_LOCAL_DYNAMIC : case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( riscv_call_tls_get_addr ( loc , tmp ) , dest , tmp , loc ) ; break ; case TLS_MODEL_INITIAL_EXEC : tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( riscv_got_load_tls_ie ( tmp , loc ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp = riscv_unspec_offset_high ( NULL , loc , SYMBOL_TLS_LE ) ;"
GCC,riscv,894,"Predict the next statement of this code snippet:
 <s> rtx set ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( mem ) ; might_split_p = true ; if ( GET_MODE_BITSIZE ( mode ) <= <NUM_LIT> ) might_split_p = false ; else if ( GET_MODE_BITSIZE ( mode ) == <NUM_LIT> ) { set = single_set ( insn ) ; if ( set && ! riscv_split_64bit_move_p ( SET_DEST ( set ) , SET_SRC ( set ) ) ) might_split_p = false ;"
GCC,riscv,895,"Predict the next statement of this code snippet:
 <s> case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE : return true ; case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : case MEMMODEL_RELAXED : return false ;"
GCC,riscv,896,"Predict the next statement of this code snippet:
 <s> case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE : return true ; case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : case MEMMODEL_RELAXED : return false ; default : gcc_unreachable ( ) ;"
GCC,riscv,897,"Predict the next statement of this code snippet:
 <s> case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE : case MEMMODEL_RELAXED : return false ; default : gcc_unreachable ( ) ;"
GCC,riscv,898,"Predict the next statement of this code snippet:
 <s> static bool riscv_memmodel_needs_release_fence ( enum memmodel model ) { switch ( model ) { case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : return true ; case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE :"
GCC,riscv,899,"Predict the next statement of this code snippet:
 <s> static int riscv_memory_move_cost ( machine_mode mode , reg_class_t rclass , bool in ) { return ( tune_param -> memory_cost + memory_move_secondary_cost ( mode , rclass , in ) ) ;"
GCC,riscv,900,"Predict the next statement of this code snippet:
 <s> static tree riscv_merge_decl_attributes ( tree olddecl , tree newdecl ) { tree combined_attrs ; enum riscv_privilege_levels old_interrupt_type = riscv_get_interrupt_type ( olddecl ) ; enum riscv_privilege_levels new_interrupt_type = riscv_get_interrupt_type ( newdecl ) ; if ( ( old_interrupt_type != UNKNOWN_MODE ) && ( new_interrupt_type != UNKNOWN_MODE ) && ( old_interrupt_type != new_interrupt_type ) ) error ( <STR_LIT> , <STR_LIT> ) ; combined_attrs = merge_attributes ( DECL_ATTRIBUTES ( olddecl ) , DECL_ATTRIBUTES ( newdecl ) ) ; return combined_attrs ;"
GCC,riscv,901,"Predict the next statement of this code snippet:
 <s> enum riscv_privilege_levels new_interrupt_type = riscv_get_interrupt_type ( newdecl ) ; if ( ( old_interrupt_type != UNKNOWN_MODE ) && ( new_interrupt_type != UNKNOWN_MODE ) && ( old_interrupt_type != new_interrupt_type ) ) error ( <STR_LIT> , <STR_LIT> ) ; combined_attrs = merge_attributes ( DECL_ATTRIBUTES ( olddecl ) , DECL_ATTRIBUTES ( newdecl ) ) ; return combined_attrs ;"
GCC,riscv,902,"Predict the next statement of this code snippet:
 <s> return ( mode1 == mode2 || ! ( GET_MODE_CLASS ( mode1 ) == MODE_FLOAT && GET_MODE_CLASS ( mode2 ) == MODE_FLOAT ) ) ;"
GCC,riscv,903,"Predict the next statement of this code snippet:
 <s> static bool riscv_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) {"
GCC,riscv,904,"Predict the next statement of this code snippet:
 <s> if ( can_create_pseudo && num_ops > <NUM_LIT> && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo ) x = riscv_emit_set ( temp , x ) ;"
GCC,riscv,905,"Predict the next statement of this code snippet:
 <s> return NULL_TREE != lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func_decl ) ) ;"
GCC,riscv,906,"Predict the next statement of this code snippet:
 <s> bool riscv_new_address_profitable_p ( rtx memref , rtx_insn * insn , rtx new_addr ) { addr_space_t as = MEM_ADDR_SPACE ( memref ) ; bool speed = optimize_bb_for_speed_p ( BLOCK_FOR_INSN ( insn ) ) ; int old_cost = address_cost ( XEXP ( memref , <NUM_LIT> ) , GET_MODE ( memref ) , as , speed ) ; int new_cost = address_cost ( new_addr , GET_MODE ( memref ) , as , speed ) ;"
GCC,riscv,907,"Predict the next statement of this code snippet:
 <s> bool speed = optimize_bb_for_speed_p ( BLOCK_FOR_INSN ( insn ) ) ;"
GCC,riscv,908,"Predict the next statement of this code snippet:
 <s> int max = <NUM_LIT> ; if ( ! IN_RANGE ( riscv_preferred_stack_boundary_arg , min , max ) ) error ( <STR_LIT> , riscv_preferred_stack_boundary_arg , min , max ) ; riscv_stack_boundary = <NUM_LIT> << riscv_preferred_stack_boundary_arg ; } if ( riscv_emit_attribute_p < <NUM_LIT> ) riscv_emit_attribute_p = TARGET_RISCV_ATTRIBUTE ; riscv_emit_attribute_p = <NUM_LIT> ; if ( riscv_emit_attribute_p ) error ( <STR_LIT> <STR_LIT> ) ; if ( riscv_stack_protector_guard == SSP_GLOBAL && OPTION_SET_P ( riscv_stack_protector_guard_offset_str ) ) { error ( <STR_LIT> <STR_LIT> , riscv_stack_protector_guard_offset_str ) ; } if ( riscv_stack_protector_guard == SSP_TLS && ! ( OPTION_SET_P ( riscv_stack_protector_guard_offset_str ) && OPTION_SET_P ( riscv_stack_protector_guard_reg_str ) ) ) { error ( <STR_LIT> <STR_LIT> <STR_LIT> ) ; } if ( OPTION_SET_P ( riscv_stack_protector_guard_reg_str ) ) { const char * str = riscv_stack_protector_guard_reg_str ; int reg = decode_reg_name ( str ) ;"
GCC,riscv,909,"Predict the next statement of this code snippet:
 <s> unsigned n = riscv_save_libcall_count ( mask ) ;"
GCC,riscv,910,"Predict the next statement of this code snippet:
 <s> ssize_t bytes = snprintf ( s , sizeof ( s ) , <STR_LIT> , n ) ; gcc_assert ( ( size_t ) bytes < sizeof ( s ) ) ;"
GCC,riscv,911,"Predict the next statement of this code snippet:
 <s> emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = gen_rtx_MEM ( FUNCTION_MODE , XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ) ; temp1 = gen_rtx_REG ( Pmode , RISCV_PROLOGUE_TEMP_REGNUM ) ; temp2 = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != <NUM_LIT> ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) {"
GCC,riscv,912,"Predict the next statement of this code snippet:
 <s> } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != <NUM_LIT> ) { rtx addr ; riscv_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = riscv_add_offset ( temp2 , temp1 , vcall_offset ) ; riscv_emit_move ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp1 ) ) ; } insn = emit_call_insn ( gen_sibcall ( fnaddr , const0_rtx , NULL , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ;"
GCC,riscv,913,"Predict the next statement of this code snippet:
 <s> if ( src_code == CONST_INT ) { if ( SMALL_OPERAND ( INTVAL ( src ) ) || LUI_OPERAND ( INTVAL ( src ) ) ) return <STR_LIT> ; if ( TARGET_ZBS && SINGLE_BIT_MASK_OPERAND ( INTVAL ( src ) ) ) return <STR_LIT> ; abort ( ) ; } if ( src_code == HIGH ) return <STR_LIT> ; if ( symbolic_operand ( src , VOIDmode ) ) switch ( riscv_classify_symbolic_expression ( src ) ) { case SYMBOL_GOT_DISP : return <STR_LIT> ; case SYMBOL_ABSOLUTE : return <STR_LIT> ; case SYMBOL_PCREL : return <STR_LIT> ; default : gcc_unreachable ( ) ; } } if ( ( src_code == REG && GP_REG_P ( REGNO ( src ) ) ) || ( src == CONST0_RTX ( mode ) ) ) { if ( dest_code == REG ) { if ( GP_REG_P ( REGNO ( dest ) ) ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return <STR_LIT> ; if ( TARGET_64BIT ) return <STR_LIT> ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return <STR_LIT> ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) {"
GCC,riscv,914,"Predict the next statement of this code snippet:
 <s> const char * riscv_output_return ( ) { if ( cfun -> machine -> naked_p ) return <STR_LIT> ;"
GCC,riscv,915,"Predict the next statement of this code snippet:
 <s> const char * riscv_output_return ( ) {"
GCC,riscv,916,"Predict the next statement of this code snippet:
 <s> static const struct riscv_tune_info * riscv_parse_tune ( const char * tune_string ) { const riscv_cpu_info * cpu = riscv_find_cpu ( tune_string ) ; if ( cpu ) tune_string = cpu -> tune ;"
GCC,riscv,917,"Predict the next statement of this code snippet:
 <s> static int warned = <NUM_LIT> ; unsigned num_int_old = <NUM_LIT> , num_float_old = <NUM_LIT> ; int n_old = riscv_flatten_aggregate_argument ( type , fields , false ) ; for ( int i = <NUM_LIT> ; i < n_old ; i ++ ) { num_float_old += SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ; num_int_old += INTEGRAL_TYPE_P ( fields [ i ] . type ) ; } unsigned num_int_new = <NUM_LIT> , num_float_new = <NUM_LIT> ; int n_new = riscv_flatten_aggregate_argument ( type , fields , true ) ; for ( int i = <NUM_LIT> ; i < n_new ; i ++ ) { num_float_new += SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ; num_int_new += INTEGRAL_TYPE_P ( fields [ i ] . type ) ;"
GCC,riscv,918,"Predict the next statement of this code snippet:
 <s> int n_new = riscv_flatten_aggregate_argument ( type , fields , true ) ; for ( int i = <NUM_LIT> ; i < n_new ; i ++ ) if ( ! SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ) { n_new = - <NUM_LIT> ; break ; } if ( ( n_old != n_new ) && ( warned == <NUM_LIT> ) ) { warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ; warned = <NUM_LIT> ; }"
GCC,riscv,919,"Predict the next statement of this code snippet:
 <s> struct riscv_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) { riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; if ( info . num_fprs ) return false ;"
GCC,riscv,920,"Predict the next statement of this code snippet:
 <s> riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; if ( info . num_fprs ) return false ;"
GCC,riscv,921,"Predict the next statement of this code snippet:
 <s> static rtx riscv_pass_fpr_pair ( machine_mode mode , unsigned regno1 , machine_mode mode1 , HOST_WIDE_INT offset1 , unsigned regno2 , machine_mode mode2 , HOST_WIDE_INT offset2 ) { return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode1 , regno1 ) , GEN_INT ( offset1 ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode2 , regno2 ) , GEN_INT ( offset2 ) ) ) ) ;"
GCC,riscv,922,"Predict the next statement of this code snippet:
 <s> x = gen_rtx_EXPR_LIST ( VOIDmode , x , GEN_INT ( offset ) ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( <NUM_LIT> , x ) ) ; } return x ;"
GCC,riscv,923,"Predict the next statement of this code snippet:
 <s> if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode , x , GEN_INT ( offset ) ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( <NUM_LIT> , x ) ) ;"
GCC,riscv,924,"Predict the next statement of this code snippet:
 <s> static unsigned riscv_pass_mode_in_fpr_p ( machine_mode mode ) { if ( GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_FP_ARG ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return <NUM_LIT> ; if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) return <NUM_LIT> ; }"
GCC,riscv,925,"Predict the next statement of this code snippet:
 <s> if ( riscv_memmodel_needs_amo_acquire ( ( enum memmodel ) INTVAL ( op ) ) ) fputs ( <STR_LIT> , file ) ; break ; case 'F' : if ( riscv_memmodel_needs_release_fence ( ( enum memmodel ) INTVAL ( op ) ) ) fputs ( <STR_LIT> , file ) ; break ; case 'i' : if ( code != REG ) fputs ( <STR_LIT> , file ) ; break ; case 'S' : { rtx newop = GEN_INT ( ctz_hwi ( INTVAL ( op ) ) ) ; output_addr_const ( file , newop ) ; break ; } case 'T' : { rtx newop = GEN_INT ( ctz_hwi ( ~ INTVAL ( op ) ) ) ;"
GCC,riscv,926,"Predict the next statement of this code snippet:
 <s> case REG : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; break ; case MEM : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; else output_address ( mode , XEXP ( op , <NUM_LIT> ) ) ; break ; default : if ( letter == 'z' && op == CONST0_RTX ( GET_MODE ( op ) ) ) fputs ( reg_names [ GP_REG_FIRST ] , file ) ;"
GCC,riscv,927,"Predict the next statement of this code snippet:
 <s> reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; default : output_operand_lossage ( <STR_LIT> , hi_reloc ? 'h' : 'R' ) ; return ; } fprintf ( file , <STR_LIT> , reloc ) ; output_addr_const ( file , riscv_strip_unspec_address ( op ) ) ;"
GCC,riscv,928,"Predict the next statement of this code snippet:
 <s> if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp = * punsignedp ; PROMOTE_MODE ( mode , unsignedp , type ) ; * punsignedp = unsignedp ;"
GCC,riscv,929,"Predict the next statement of this code snippet:
 <s> return riscv_secondary_memory_needed ( mode , from , to ) ? <NUM_LIT> : <NUM_LIT> ;"
GCC,riscv,930,"Predict the next statement of this code snippet:
 <s> return riscv_secondary_memory_needed ( mode , from , to ) ? <NUM_LIT> : <NUM_LIT> ;"
GCC,riscv,931,"Predict the next statement of this code snippet:
 <s> if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; }"
GCC,riscv,932,"Predict the next statement of this code snippet:
 <s> if ( TARGET_SAVE_RESTORE ) riscv_remove_unneeded_save_restore_calls ( ) ;"
GCC,riscv,933,"Predict the next statement of this code snippet:
 <s> static void riscv_reorg ( void ) {"
GCC,riscv,934,"Predict the next statement of this code snippet:
 <s> dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; if ( epilogue_cfa_sp_offset && REGNO ( reg ) == HARD_FRAME_POINTER_REGNUM ) { rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( epilogue_cfa_sp_offset ) ) ;"
GCC,riscv,935,"Predict the next statement of this code snippet:
 <s> if ( count != <NUM_LIT> ) return const0_rtx ;"
GCC,riscv,936,"Predict the next statement of this code snippet:
 <s> rtx riscv_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) {"
GCC,riscv,937,"Predict the next statement of this code snippet:
 <s> memset ( & args , <NUM_LIT> , sizeof args ) ; function_arg_info arg ( const_cast < tree > ( type ) , true ) ;"
GCC,riscv,938,"Predict the next statement of this code snippet:
 <s> static bool riscv_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS args ; cumulative_args_t cum = pack_cumulative_args ( & args ) ; memset ( & args , <NUM_LIT> , sizeof args ) ; function_arg_info arg ( const_cast < tree > ( type ) , true ) ; return riscv_pass_by_reference ( cum , arg ) ;"
GCC,riscv,939,"Predict the next statement of this code snippet:
 <s> static unsigned riscv_save_libcall_count ( unsigned mask ) {"
GCC,riscv,940,"Predict the next statement of this code snippet:
 <s> riscv_emit_move ( mem , reg ) ; riscv_set_frame_expr ( riscv_frame_set ( mem , reg ) ) ;"
GCC,riscv,941,"Predict the next statement of this code snippet:
 <s> mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; fn ( gen_rtx_REG ( mode , regno ) , mem ) ;"
GCC,riscv,942,"Predict the next statement of this code snippet:
 <s> mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ;"
GCC,riscv,943,"Predict the next statement of this code snippet:
 <s> return ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ( class1 == FP_REGS ) != ( class2 == FP_REGS ) ) ;"
GCC,riscv,944,"Predict the next statement of this code snippet:
 <s> switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_SRODATA : return get_named_section ( decl , <STR_LIT> , reloc ) ; default : return default_elf_select_section ( decl , reloc , align ) ;"
GCC,riscv,945,"Predict the next statement of this code snippet:
 <s> static section * riscv_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_SRODATA : return get_named_section ( decl , <STR_LIT> , reloc ) ; default : return default_elf_select_section ( decl , reloc , align ) ; }"
GCC,riscv,946,"Predict the next statement of this code snippet:
 <s> gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ;"
GCC,riscv,947,"Predict the next statement of this code snippet:
 <s> rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == <NUM_LIT> ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ;"
GCC,riscv,948,"Predict the next statement of this code snippet:
 <s> static void riscv_set_current_function ( tree decl ) { if ( decl == NULL_TREE || current_function_decl == NULL_TREE || current_function_decl == error_mark_node || ! cfun -> machine || cfun -> machine -> attributes_checked_p ) return ; cfun -> machine -> naked_p = riscv_naked_function_p ( decl ) ; cfun -> machine -> interrupt_handler_p = riscv_interrupt_type_p ( TREE_TYPE ( decl ) ) ; if ( cfun -> machine -> naked_p && cfun -> machine -> interrupt_handler_p ) error ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( cfun -> machine -> interrupt_handler_p ) { tree ret = TREE_TYPE ( TREE_TYPE ( decl ) ) ; tree args = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( TREE_CODE ( ret ) != VOID_TYPE ) error ( <STR_LIT> , <STR_LIT> ) ; if ( args && TREE_CODE ( TREE_VALUE ( args ) ) != VOID_TYPE ) error ( <STR_LIT> , <STR_LIT> ) ; cfun -> machine -> interrupt_mode = riscv_get_interrupt_type ( decl ) ; gcc_assert ( cfun -> machine -> interrupt_mode != UNKNOWN_MODE ) ;"
GCC,riscv,949,"Predict the next statement of this code snippet:
 <s> slot_address = riscv_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset ) ; riscv_emit_move ( gen_frame_mem ( GET_MODE ( address ) , slot_address ) , address ) ;"
GCC,riscv,950,"Predict the next statement of this code snippet:
 <s> offset &= CSW_MAX_OFFSET ; if ( ! SMALL_OPERAND ( INTVAL ( high ) ) ) high = force_reg ( Pmode , high ) ; base = force_reg ( Pmode , gen_rtx_PLUS ( Pmode , high , base ) ) ; addr = plus_constant ( Pmode , base , offset ) ; return addr ;"
GCC,riscv,951,"Predict the next statement of this code snippet:
 <s> static bool riscv_size_ok_for_small_data_p ( int size ) { return g_switch_value && IN_RANGE ( size , <NUM_LIT> , g_switch_value ) ;"
GCC,riscv,952,"Predict the next statement of this code snippet:
 <s> static bool riscv_slow_unaligned_access ( machine_mode , unsigned int ) {"
GCC,riscv,953,"Predict the next statement of this code snippet:
 <s> if ( TARGET_64BIT ) return false ; if ( TARGET_DOUBLE_FLOAT && ( ( FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) || ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) || ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) || ( FP_REG_RTX_P ( dest ) && src == CONST0_RTX ( GET_MODE ( src ) ) ) ) ) return false ;"
GCC,riscv,954,"Predict the next statement of this code snippet:
 <s> low = riscv_const_insns ( riscv_subword ( x , false ) ) ; high = riscv_const_insns ( riscv_subword ( x , true ) ) ; gcc_assert ( low > <NUM_LIT> && high > <NUM_LIT> ) ;"
GCC,riscv,955,"Predict the next statement of this code snippet:
 <s> void riscv_split_doubleword_move ( rtx dest , rtx src ) { rtx low_dest ; low_dest = riscv_subword ( dest , false ) ;"
GCC,riscv,956,"Predict the next statement of this code snippet:
 <s> low_dest = riscv_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; } else { riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ;"
GCC,riscv,957,"Predict the next statement of this code snippet:
 <s> unsigned HOST_WIDE_INT hival = sext_hwi ( ( val - loval ) >> <NUM_LIT> , <NUM_LIT> ) ; rtx hi = gen_reg_rtx ( mode ) , lo = gen_reg_rtx ( mode ) ; riscv_move_integer ( hi , hi , hival , mode , FALSE ) ; riscv_move_integer ( lo , lo , loval , mode , FALSE ) ; hi = gen_rtx_fmt_ee ( ASHIFT , mode , hi , GEN_INT ( <NUM_LIT> ) ) ; hi = force_reg ( mode , hi ) ;"
GCC,riscv,958,"Predict the next statement of this code snippet:
 <s> hi = gen_rtx_fmt_ee ( ASHIFT , mode , hi , GEN_INT ( <NUM_LIT> ) ) ; hi = force_reg ( mode , hi ) ; return gen_rtx_fmt_ee ( PLUS , mode , hi , lo ) ;"
GCC,riscv,959,"Predict the next statement of this code snippet:
 <s> unsigned HOST_WIDE_INT loval = sext_hwi ( val , <NUM_LIT> ) ; unsigned HOST_WIDE_INT hival = sext_hwi ( ( val - loval ) >> <NUM_LIT> , <NUM_LIT> ) ; struct riscv_integer_op codes [ RISCV_MAX_INTEGER_OPS ] ; cost = <NUM_LIT> + riscv_build_integer ( codes , loval , VOIDmode ) ; if ( loval != hival ) cost += riscv_build_integer ( codes , hival , VOIDmode ) ;"
GCC,riscv,960,"Predict the next statement of this code snippet:
 <s> cost = <NUM_LIT> + riscv_build_integer ( codes , loval , VOIDmode ) ; if ( loval != hival ) cost += riscv_build_integer ( codes , hival , VOIDmode ) ;"
GCC,riscv,961,"Predict the next statement of this code snippet:
 <s> { rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = riscv_force_temporary ( temp , high , in_splitter ) ; * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; } break ; case SYMBOL_PCREL : { static unsigned seqno ; char buf [ <NUM_LIT> ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( ! nonzero_address_p ( addr ) ) SYMBOL_REF_WEAK ( label ) = <NUM_LIT> ;"
GCC,riscv,962,"Predict the next statement of this code snippet:
 <s> case SYMBOL_PCREL : { static unsigned seqno ; char buf [ <NUM_LIT> ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( ! nonzero_address_p ( addr ) ) SYMBOL_REF_WEAK ( label ) = <NUM_LIT> ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ;"
GCC,riscv,963,"Predict the next statement of this code snippet:
 <s> bool riscv_split_symbol_type ( enum riscv_symbol_type symbol_type ) { if ( symbol_type == SYMBOL_TLS_LE ) return true ; if ( ! TARGET_EXPLICIT_RELOCS ) return false ;"
GCC,riscv,964,"Predict the next statement of this code snippet:
 <s> if ( MEM_P ( SET_DEST ( in_set ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) == PARALLEL ) { for ( i = <NUM_LIT> ; i < XVECLEN ( out_pat , <NUM_LIT> ) ; i ++ ) { out_exp = XVECEXP ( out_pat , <NUM_LIT> , i ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } } } } else { in_pat = PATTERN ( in_insn ) ; if ( GET_CODE ( in_pat ) != PARALLEL ) return false ; for ( i = <NUM_LIT> ; i < XVECLEN ( in_pat , <NUM_LIT> ) ; i ++ ) { in_exp = XVECEXP ( in_pat , <NUM_LIT> , i ) ; if ( ( GET_CODE ( in_exp ) == CLOBBER ) || ( GET_CODE ( in_exp ) == USE ) ) continue ; else if ( GET_CODE ( in_exp ) != SET ) return false ; if ( MEM_P ( SET_DEST ( in_exp ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) != PARALLEL ) return false ; for ( j = <NUM_LIT> ; j < XVECLEN ( out_pat , <NUM_LIT> ) ; j ++ ) { out_exp = XVECEXP ( out_pat , <NUM_LIT> , j ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } }"
GCC,riscv,965,"Predict the next statement of this code snippet:
 <s> if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ;"
GCC,riscv,966,"Predict the next statement of this code snippet:
 <s> unsigned int byte = ( high_p != BYTES_BIG_ENDIAN ) ? UNITS_PER_WORD : <NUM_LIT> ; machine_mode mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = TARGET_64BIT ? TImode : DImode ; if ( MEM_P ( op ) ) return adjust_address ( op , word_mode , byte ) ; if ( REG_P ( op ) ) gcc_assert ( ! FP_REG_RTX_P ( op ) ) ; return simplify_gen_subreg ( word_mode , op , mode , byte ) ;"
GCC,riscv,967,"Predict the next statement of this code snippet:
 <s> unsigned int byte = ( high_p != BYTES_BIG_ENDIAN ) ? UNITS_PER_WORD : <NUM_LIT> ; machine_mode mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = TARGET_64BIT ? TImode : DImode ; if ( MEM_P ( op ) ) return adjust_address ( op , word_mode , byte ) ;"
GCC,riscv,968,"Predict the next statement of this code snippet:
 <s> static rtx riscv_swap_instruction ( rtx inst ) {"
GCC,riscv,969,"Predict the next statement of this code snippet:
 <s> static rtx riscv_swap_instruction ( rtx inst ) { gcc_assert ( GET_MODE ( inst ) == SImode ) ;"
GCC,riscv,970,"Predict the next statement of this code snippet:
 <s> else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_ABSOLUTE : case SYMBOL_PCREL : case SYMBOL_TLS_LE : return sext_hwi ( INTVAL ( offset ) , <NUM_LIT> ) == INTVAL ( offset ) ; default : return false ;"
GCC,riscv,971,"Predict the next statement of this code snippet:
 <s> if ( SYMBOL_REF_P ( x ) ) return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; else return false ;"
GCC,riscv,972,"Predict the next statement of this code snippet:
 <s> if ( Pmode == DImode ) return gen_tls_add_tp_ledi ( dest , base , tp , sym ) ;"
GCC,riscv,973,"Predict the next statement of this code snippet:
 <s> if ( Pmode == DImode ) return gen_tls_add_tp_ledi ( dest , base , tp , sym ) ;"
GCC,riscv,974,"Predict the next statement of this code snippet:
 <s> hi_chain = riscv_force_binary ( SImode , AND , hi_chain , uimm_mask ) ; lui_hi_chain_code = OPCODE_LUI | ( STATIC_CHAIN_REGNUM << SHIFT_RD ) ; rtx lui_hi_chain = riscv_force_binary ( SImode , IOR , hi_chain , gen_int_mode ( lui_hi_chain_code , SImode ) ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ; riscv_emit_move ( mem , riscv_swap_instruction ( lui_hi_chain ) ) ; rtx hi_func = riscv_force_binary ( SImode , PLUS , target_function , fixup_value ) ; hi_func = riscv_force_binary ( SImode , AND , hi_func , uimm_mask ) ; lui_hi_func_code = OPCODE_LUI | ( RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD ) ; rtx lui_hi_func = riscv_force_binary ( SImode , IOR , hi_func , gen_int_mode ( lui_hi_func_code , SImode ) ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> * GET_MODE_SIZE ( SImode ) ) ; riscv_emit_move ( mem , riscv_swap_instruction ( lui_hi_func ) ) ; rtx lo_chain = riscv_force_binary ( SImode , AND , chain_value , imm12_mask ) ; lo_chain = riscv_force_binary ( SImode , ASHIFT , lo_chain , GEN_INT ( <NUM_LIT> ) ) ; lo_chain_code = OPCODE_ADDI | ( STATIC_CHAIN_REGNUM << SHIFT_RD ) | ( STATIC_CHAIN_REGNUM << SHIFT_RS1 ) ; rtx addi_lo_chain = riscv_force_binary ( SImode , IOR , lo_chain , force_reg ( SImode , GEN_INT ( lo_chain_code ) ) ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> * GET_MODE_SIZE ( SImode ) ) ; riscv_emit_move ( mem , riscv_swap_instruction ( addi_lo_chain ) ) ; rtx lo_func = riscv_force_binary ( SImode , AND , target_function , imm12_mask ) ; lo_func = riscv_force_binary ( SImode , ASHIFT , lo_func , GEN_INT ( <NUM_LIT> ) ) ; lo_func_code = OPCODE_JALR | ( RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1 ) ; rtx jr_lo_func = riscv_force_binary ( SImode , IOR , lo_func , force_reg ( SImode , GEN_INT ( lo_func_code ) ) ) ;"
GCC,riscv,975,"Predict the next statement of this code snippet:
 <s> static void riscv_unique_section ( tree decl , int reloc ) { const char * prefix = NULL ; bool one_only = DECL_ONE_ONLY ( decl ) && ! HAVE_COMDAT_GROUP ; switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_SRODATA :"
GCC,riscv,976,"Predict the next statement of this code snippet:
 <s> break ; default : break ; } if ( prefix ) { const char * name , * linkonce ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; linkonce = one_only ? <STR_LIT> : <STR_LIT> ; string = ACONCAT ( ( linkonce , prefix , <STR_LIT> , name , NULL ) ) ;"
GCC,riscv,977,"Predict the next statement of this code snippet:
 <s> rtx riscv_unspec_address ( rtx address , enum riscv_symbol_type symbol_type ) { rtx base , offset ;"
GCC,riscv,978,"Predict the next statement of this code snippet:
 <s> if ( offset != const0_rtx ) base = gen_rtx_PLUS ( Pmode , base , offset ) ;"
GCC,riscv,979,"Predict the next statement of this code snippet:
 <s> static rtx riscv_unspec_address_offset ( rtx base , rtx offset , enum riscv_symbol_type symbol_type ) {"
GCC,riscv,980,"Predict the next statement of this code snippet:
 <s> static rtx riscv_unspec_offset_high ( rtx temp , rtx addr , enum riscv_symbol_type symbol_type ) {"
GCC,riscv,981,"Predict the next statement of this code snippet:
 <s> static bool riscv_use_save_libcall ( const struct riscv_frame_info * frame ) { if ( ! TARGET_SAVE_RESTORE || crtl -> calls_eh_return || frame_pointer_needed || cfun -> machine -> interrupt_handler_p ) return false ; return frame -> save_libcall_adjustment != <NUM_LIT> ;"
GCC,riscv,982,"Predict the next statement of this code snippet:
 <s> static bool riscv_valid_base_register_p ( rtx x , machine_mode mode , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && riscv_regno_mode_ok_for_base_p ( REGNO ( x ) , mode , strict_p ) ) ;"
GCC,riscv,983,"Predict the next statement of this code snippet:
 <s> if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ;"
GCC,riscv,984,"Predict the next statement of this code snippet:
 <s> static bool riscv_valid_lo_sum_p ( enum riscv_symbol_type sym_type , machine_mode mode , rtx x ) { int align , size ; if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ;"
GCC,riscv,985,"Predict the next statement of this code snippet:
 <s> if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; align = ( SYMBOL_REF_DECL ( x ) ? DECL_ALIGN ( SYMBOL_REF_DECL ( x ) ) : <NUM_LIT> ) ; size = ( SYMBOL_REF_DECL ( x ) && DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ? tree_to_uhwi ( DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ) : <NUM_LIT> * BITS_PER_WORD ) ; } else {"
GCC,riscv,986,"Predict the next statement of this code snippet:
 <s> if ( ! const_arith_operand ( x , Pmode ) ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ) ) return false ;"
GCC,riscv,987,"Predict the next statement of this code snippet:
 <s> static void riscv_va_start ( tree valist , rtx nextarg ) { nextarg = plus_constant ( Pmode , nextarg , - cfun -> machine -> varargs_size ) ; std_expand_builtin_va_start ( valist , nextarg ) ;"
GCC,riscv,988,"Predict the next statement of this code snippet:
 <s> static bool riscv_warn_func_return ( tree decl ) { return ! riscv_naked_function_p ( decl ) ;"
GCC,riscv,989,"Predict the next statement of this code snippet:
 <s> if ( cmp1 == const0_rtx ) return cmp0 ; return expand_binop ( GET_MODE ( cmp0 ) , sub_optab , cmp0 , cmp1 , <NUM_LIT> , <NUM_LIT> , OPTAB_DIRECT ) ;"
GCC,riscv,990,"Predict the next statement of this code snippet:
 <s> if ( cmp1 == const0_rtx ) return cmp0 ;"
GCC,riscv,991,"Predict the next statement of this code snippet:
 <s> break ; case RVV_VXSAT : __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv ) : : <STR_LIT> ) ; break ; case RVV_VXRM :"
GCC,riscv,992,"Predict the next statement of this code snippet:
 <s> __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv ) : : <STR_LIT> ) ; break ; case RVV_VXRM : __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv ) : : <STR_LIT> ) ; break ; case RVV_VCSR : __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv ) : : <STR_LIT> ) ; break ;"
GCC,riscv,993,"Predict the next statement of this code snippet:
 <s> vwrite_csr ( enum RVV_CSR csr , unsigned long value ) { switch ( csr ) { case RVV_VSTART : __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( value ) : <STR_LIT> ) ; break ; case RVV_VXSAT :"
GCC,riscv,994,"Predict the next statement of this code snippet:
 <s> static bool extract_base_offset_in_addr ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( REG_P ( addr ) ) { * base = addr ; * offset = const0_rtx ; return true ; } if ( GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) {"
GCC,riscv,995,"Predict the next statement of this code snippet:
 <s> * offset_ptr = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; } else { * base_ptr = x ;"
GCC,riscv,996,"Predict the next statement of this code snippet:
 <s> if ( known_eq ( UINTVAL ( offset1 ) + size , UINTVAL ( offset2 ) ) ) { * reversed = false ; return true ; } if ( known_eq ( UINTVAL ( offset2 ) + size , UINTVAL ( offset1 ) ) ) { * reversed = true ; return true ; }"
GCC,riscv,997,"Predict the next statement of this code snippet:
 <s> split_plus ( XEXP ( mem , <NUM_LIT> ) , & base , & offset ) ; if ( ! REG_P ( base ) ) return true ; if ( REG_P ( base ) ) { if ( REGNO ( base ) == REGNO ( reg1 ) || REGNO ( base ) == REGNO ( reg2 ) ) return true ; } return false ;"
GCC,riscv,998,"Predict the next statement of this code snippet:
 <s> if ( riscv_slow_unaligned_access_p && known_lt ( MEM_ALIGN ( mem_1 ) , GET_MODE_SIZE ( mode ) * BITS_PER_UNIT ) ) return false ; bool reversed = false ; if ( ! th_mempair_check_consecutive_mems ( mode , & mem_1 , & mem_2 , & reversed ) ) return false ; if ( ( ! reversed && ! th_mempair_operand_p ( mem_1 , mode ) ) || ( reversed && ! th_mempair_operand_p ( mem_2 , mode ) ) ) return false ; gcc_assert ( known_eq ( GET_MODE_SIZE ( GET_MODE ( mem_1 ) ) , GET_MODE_SIZE ( GET_MODE ( mem_2 ) ) ) ) ; return true ;"
GCC,riscv,999,"Predict the next statement of this code snippet:
 <s> auto mode_sz = GET_MODE_SIZE ( mode ) ; if ( ! known_eq ( mem_sz , mode_sz ) ) return false ; machine_mode mem_mode = GET_MODE ( mem ) ; unsigned shamt = ( mem_mode == DImode ) ? <NUM_LIT> : <NUM_LIT> ; rtx base ; HOST_WIDE_INT offset ; split_plus ( XEXP ( mem , <NUM_LIT> ) , & base , & offset ) ;"
GCC,riscv,1000,"Predict the next statement of this code snippet:
 <s> void th_mempair_order_operands ( rtx operands [ <NUM_LIT> ] , bool load_p , machine_mode mode ) { int mem_op = load_p ? <NUM_LIT> : <NUM_LIT> ;"
GCC,riscv,1001,"Predict the next statement of this code snippet:
 <s> void th_mempair_order_operands ( rtx operands [ <NUM_LIT> ] , bool load_p , machine_mode mode ) { int mem_op = load_p ? <NUM_LIT> : <NUM_LIT> ; bool reversed = false ; if ( ! th_mempair_check_consecutive_mems ( mode , operands + mem_op , operands + mem_op + <NUM_LIT> , & reversed ) ) gcc_unreachable ( ) ; if ( reversed ) { std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; }"
GCC,riscv,1002,"Predict the next statement of this code snippet:
 <s> auto size1 = MEM_SIZE ( mem1 ) ; auto size2 = MEM_SIZE ( mem2 ) ; gcc_assert ( known_eq ( size1 , size2 ) ) ; gcc_assert ( known_eq ( offset1 + size1 , offset2 ) ) ; HOST_WIDE_INT imm2 = offset1 >> shamt ; gcc_assert ( imm2 >= <NUM_LIT> && imm2 < <NUM_LIT> ) ; gcc_assert ( ( imm2 << shamt ) == offset1 ) ; gcc_assert ( REG_P ( reg1 ) ) ; gcc_assert ( REG_P ( reg2 ) ) ; gcc_assert ( REG_P ( base1 ) ) ; if ( load_p ) { gcc_assert ( REGNO ( reg1 ) != REGNO ( reg2 ) ) ; gcc_assert ( REGNO ( reg1 ) != REGNO ( base1 ) ) ; gcc_assert ( REGNO ( reg2 ) != REGNO ( base1 ) ) ; } output_operands [ <NUM_LIT> ] = copy_rtx ( reg1 ) ; output_operands [ <NUM_LIT> ] = copy_rtx ( reg2 ) ; output_operands [ <NUM_LIT> ] = copy_rtx ( base1 ) ;"
GCC,riscv,1003,"Predict the next statement of this code snippet:
 <s> mem2 = copy_rtx ( operands [ <NUM_LIT> ] ) ; if ( mode == SImode ) format = <STR_LIT> ; else format = <STR_LIT> ; } split_plus ( XEXP ( mem1 , <NUM_LIT> ) , & base1 , & offset1 ) ; split_plus ( XEXP ( mem2 , <NUM_LIT> ) , & base2 , & offset2 ) ; gcc_assert ( rtx_equal_p ( base1 , base2 ) ) ; auto size1 = MEM_SIZE ( mem1 ) ; auto size2 = MEM_SIZE ( mem2 ) ; gcc_assert ( known_eq ( size1 , size2 ) ) ; gcc_assert ( known_eq ( offset1 + size1 , offset2 ) ) ; HOST_WIDE_INT imm2 = offset1 >> shamt ; gcc_assert ( imm2 >= <NUM_LIT> && imm2 < <NUM_LIT> ) ; gcc_assert ( ( imm2 << shamt ) == offset1 ) ; gcc_assert ( REG_P ( reg1 ) ) ; gcc_assert ( REG_P ( reg2 ) ) ; gcc_assert ( REG_P ( base1 ) ) ; if ( load_p ) { gcc_assert ( REGNO ( reg1 ) != REGNO ( reg2 ) ) ; gcc_assert ( REGNO ( reg1 ) != REGNO ( base1 ) ) ; gcc_assert ( REGNO ( reg2 ) != REGNO ( base1 ) ) ; } output_operands [ <NUM_LIT> ] = copy_rtx ( reg1 ) ;"
GCC,riscv,1004,"Predict the next statement of this code snippet:
 <s> mem2 = gen_frame_mem ( mode , mem2 ) ; operands [ reg_op ] = gen_rtx_REG ( mode , regno ) ; operands [ mem_op ] = mem1 ; operands [ <NUM_LIT> + reg_op ] = gen_rtx_REG ( mode , regno2 ) ; operands [ <NUM_LIT> + mem_op ] = mem2 ;"
GCC,riscv,1005,"Predict the next statement of this code snippet:
 <s> int reg_op = load_p ? <NUM_LIT> : <NUM_LIT> ; int mem_op = load_p ? <NUM_LIT> : <NUM_LIT> ; rtx mem1 = plus_constant ( mode , stack_pointer_rtx , offset ) ; mem1 = gen_frame_mem ( mode , mem1 ) ; rtx mem2 = plus_constant ( mode , stack_pointer_rtx , offset2 ) ; mem2 = gen_frame_mem ( mode , mem2 ) ; operands [ reg_op ] = gen_rtx_REG ( mode , regno ) ; operands [ mem_op ] = mem1 ;"
GCC,riscv,1006,"Predict the next statement of this code snippet:
 <s> rtx set2 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; rtx insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set1 , set2 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE , operands [ <NUM_LIT> ] ) ; add_reg_note ( insn , REG_CFA_RESTORE , operands [ <NUM_LIT> ] ) ;"
GCC,riscv,1007,"Predict the next statement of this code snippet:
 <s> rtx set2 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; rtx insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set1 , set2 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;"
GCC,riscv,1008,"Predict the next statement of this code snippet:
 <s> void th_mempair_save_restore_regs ( rtx operands [ <NUM_LIT> ] , bool load_p , machine_mode mode ) {"
GCC,arc,0,"Predict the next statement of this code snippet:
 <s> builtin_define ( <STR_LIT> ) ; def_or_undef_macro ( pfile , NAME , CONDITION ) ; builtin_define_with_int_value ( <STR_LIT> , arc_tp_regno ) ;"
GCC,arc,1,"Predict the next statement of this code snippet:
 <s> builtin_assert ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; def_or_undef_macro ( pfile , NAME , CONDITION ) ; builtin_define_with_int_value ( <STR_LIT> , arc_tp_regno ) ; builtin_define ( TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ;"
GCC,arc,2,"Predict the next statement of this code snippet:
 <s> builtin_assert ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; def_or_undef_macro ( pfile , NAME , CONDITION ) ; builtin_define_with_int_value ( <STR_LIT> , arc_tp_regno ) ; builtin_define_with_int_value ( <STR_LIT> , arc_lpcwidth ) ; builtin_define ( TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ;"
GCC,arc,3,"Predict the next statement of this code snippet:
 <s> builtin_assert ( <STR_LIT> ) ; builtin_assert ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; def_or_undef_macro ( pfile , NAME , CONDITION ) ; builtin_define_with_int_value ( <STR_LIT> , arc_tp_regno ) ;"
GCC,arc,4,"Predict the next statement of this code snippet:
 <s> builtin_define_with_int_value ( <STR_LIT> , arc_tp_regno ) ; builtin_define_with_int_value ( <STR_LIT> , arc_lpcwidth ) ; builtin_define ( TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ; if ( TARGET_BIG_ENDIAN ) builtin_define ( <STR_LIT> ) ;"
GCC,arc,5,"Predict the next statement of this code snippet:
 <s> builtin_define ( <STR_LIT> ) ; def_or_undef_macro ( pfile , NAME , CONDITION ) ; builtin_define_with_int_value ( <STR_LIT> , arc_tp_regno ) ; builtin_define_with_int_value ( <STR_LIT> , arc_lpcwidth ) ; builtin_define ( TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ; if ( TARGET_BIG_ENDIAN ) builtin_define ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } else {"
GCC,arc,6,"Predict the next statement of this code snippet:
 <s> if ( def_p ) cpp_define ( pfile , name ) ;"
GCC,arc,7,"Predict the next statement of this code snippet:
 <s> static void def_or_undef_macro ( cpp_reader * pfile , const char * name , bool def_p ) { if ( def_p ) cpp_define ( pfile , name ) ;"
GCC,arc,8,"Predict the next statement of this code snippet:
 <s> case PRE_INC : case PRE_DEC : case POST_INC : case POST_DEC : case PRE_MODIFY : case POST_MODIFY : return ! speed ; case LABEL_REF : case SYMBOL_REF : case CONST : if ( TARGET_NPS_CMEM && cmem_address ( addr , SImode ) ) return <NUM_LIT> ; return COSTS_N_INSNS ( <NUM_LIT> ) ; case PLUS : { rtx plus0 = XEXP ( addr , <NUM_LIT> ) ; rtx plus1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) != MULT || ! CONST_INT_P ( XEXP ( plus0 , <NUM_LIT> ) ) || ( INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> && INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> ) ) ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return ( ! RTX_OK_FOR_OFFSET_P ( SImode , plus1 ) ? COSTS_N_INSNS ( <NUM_LIT> ) : speed ? <NUM_LIT> : ( arc_check_short_reg_p ( plus0 ) && satisfies_constraint_O ( plus1 ) ) ? <NUM_LIT> : <NUM_LIT> ) ; case REG : return ( speed < <NUM_LIT> ? <NUM_LIT> : ( arc_check_short_reg_p ( plus0 ) && arc_check_short_reg_p ( plus1 ) ) ? <NUM_LIT> : <NUM_LIT> ) ; case CONST : case SYMBOL_REF : case LABEL_REF : return COSTS_N_INSNS ( <NUM_LIT> ) ; default : break ;"
GCC,arc,9,"Predict the next statement of this code snippet:
 <s> case LABEL_REF : case SYMBOL_REF : case CONST : if ( TARGET_NPS_CMEM && cmem_address ( addr , SImode ) ) return <NUM_LIT> ; return COSTS_N_INSNS ( <NUM_LIT> ) ; case PLUS : { rtx plus0 = XEXP ( addr , <NUM_LIT> ) ; rtx plus1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) != MULT || ! CONST_INT_P ( XEXP ( plus0 , <NUM_LIT> ) ) || ( INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> && INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> ) ) ) break ;"
GCC,arc,10,"Predict the next statement of this code snippet:
 <s> if ( TARGET_HS && ( arc_tune == ARC_TUNE_ARCHS4X_REL31A ) ) switch ( get_attr_type ( pred ) ) { case TYPE_STORE : switch ( get_attr_type ( succ ) ) { case TYPE_BRCC : case TYPE_BRCC_NO_DELAY_SLOT : case TYPE_LOOP_END : return <NUM_LIT> ; default : break ; } break ;"
GCC,arc,11,"Predict the next statement of this code snippet:
 <s> if ( IN_RANGE ( REGNO ( op ) ^ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return true ;"
GCC,arc,12,"Predict the next statement of this code snippet:
 <s> if ( ! REG_P ( op ) ) return false ; if ( IN_RANGE ( REGNO ( op ) ^ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return true ; return false ;"
GCC,arc,13,"Predict the next statement of this code snippet:
 <s> if ( ARC_NAKED_P ( fn_type ) ) return ; size = arc_compute_frame_size ( ) ; size_to_deallocate = size ; first_offset = size - ( frame -> pretend_size + frame -> reg_size + frame -> extra_size ) ; if ( ! can_trust_sp_p ) gcc_assert ( arc_frame_pointer_needed ( ) ) ; if ( size ) emit_insn ( gen_blockage ( ) ) ; if ( ARC_INTERRUPT_P ( fn_type ) ) { size_to_deallocate -= arc_restore_callee_saves ( <NUM_LIT> , false , restore_fp , first_offset , size_to_deallocate ) ; restore_fp = false ; first_offset = <NUM_LIT> ; } if ( arc_must_save_register ( R58_REG , cfun , true ) ) { rtx insn ; rtx reg0 = gen_rtx_REG ( SImode , R0_REG ) ; rtx reg1 = gen_rtx_REG ( SImode , R1_REG ) ; size_to_deallocate -= pop_reg ( reg0 ) ; size_to_deallocate -= pop_reg ( reg1 ) ; insn = emit_insn ( gen_mulu64 ( reg0 , const1_rtx ) ) ; add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , R58_REG ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_arc600_stall ( ) ) ; insn = emit_insn ( gen_rtx_UNSPEC_VOLATILE ( VOIDmode , gen_rtvec ( <NUM_LIT> , reg1 , GEN_INT ( AUX_MULHI ) ) , VUNSPEC_ARC_SR ) ) ; add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , R59_REG ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( arc_must_save_register ( TARGET_BIG_ENDIAN ? R41_REG : R40_REG , cfun , TARGET_DPFP ) ) { rtx reg0 = gen_rtx_REG ( SImode , R0_REG ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { size_to_deallocate -= pop_reg ( reg0 ) ; emit_insn ( gen_rtx_UNSPEC_VOLATILE ( VOIDmode , gen_rtvec ( <NUM_LIT> , reg0 , GEN_INT ( AUX_DPFP_START + i ) ) , VUNSPEC_ARC_SR ) ) ; } } if ( arc_lpcwidth != <NUM_LIT> && arc_must_save_register ( LP_COUNT , cfun , true ) ) { rtx reg0 = gen_rtx_REG ( SImode , R0_REG ) ; size_to_deallocate -= pop_reg ( reg0 ) ; emit_move_insn ( gen_rtx_REG ( SImode , LP_COUNT ) , reg0 ) ;"
GCC,arc,14,"Predict the next statement of this code snippet:
 <s> int match = operands_match_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; int match2 = operands_match_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; int intval = ( REG_P ( operands [ <NUM_LIT> ] ) ? <NUM_LIT> : CONST_INT_P ( operands [ <NUM_LIT> ] ) ? INTVAL ( operands [ <NUM_LIT> ] ) : <NUM_LIT> ) ;"
GCC,arc,15,"Predict the next statement of this code snippet:
 <s> int regno , indx , off , nregs ; rtx insn , reg , mem ; int frame_allocated = <NUM_LIT> ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( <NUM_LIT> << regno ) ) ; ) regno ++ ; end_reg = regno - <NUM_LIT> ; nregs = end_reg - start_reg + <NUM_LIT> ; nregs += save_blink ? <NUM_LIT> : <NUM_LIT> ; nregs += save_fp ? <NUM_LIT> : <NUM_LIT> ; if ( offset ) frame_stack_add ( offset ) ; insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + ( save_fp ? <NUM_LIT> : <NUM_LIT> ) + <NUM_LIT> ) ) ; indx = <NUM_LIT> ; reg = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - nregs * UNITS_PER_WORD ) ) ; RTX_FRAME_RELATED_P ( reg ) = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; save_blink = false ; } for ( regno = start_reg ; regno <= end_reg ; regno ++ , indx ++ , off -= UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; }"
GCC,arc,16,"Predict the next statement of this code snippet:
 <s> RTX_FRAME_RELATED_P ( reg ) = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; save_blink = false ; } for ( regno = start_reg ; regno <= end_reg ; regno ++ , indx ++ , off -= UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; } if ( save_fp ) { mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , hard_frame_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; save_fp = false ;"
GCC,arc,17,"Predict the next statement of this code snippet:
 <s> case ARC_TUNE_ARCHS4X : case ARC_TUNE_ARCHS4XD : return <NUM_LIT> ; default : break ;"
GCC,arc,18,"Predict the next statement of this code snippet:
 <s> next_cum = * get_cumulative_args ( args_so_far ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) arc_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; first_anon_arg = next_cum ; if ( FUNCTION_ARG_REGNO_P ( first_anon_arg ) ) { int first_reg_offset = first_anon_arg ; if ( ! no_rtl ) { rtx regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( <NUM_LIT> ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , MAX_ARC_PARM_REGS - first_reg_offset ) ; } * pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ;"
GCC,arc,19,"Predict the next statement of this code snippet:
 <s> } xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; xop [ <NUM_LIT> ] = GEN_INT ( trunc_int_for_mode ( intval0 , SImode ) ) ; xop [ <NUM_LIT> ] = GEN_INT ( trunc_int_for_mode ( intval1 , SImode ) ) ; emit_move_insn ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; emit_move_insn ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; return ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( MEM_P ( operands [ i ] ) && auto_inc_p ( XEXP ( operands [ i ] , <NUM_LIT> ) ) ) { rtx addr = XEXP ( operands [ i ] , <NUM_LIT> ) ; rtx r , o ; enum rtx_code code ; gcc_assert ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , addr ) ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : o = GEN_INT ( - <NUM_LIT> ) ; goto pre_modify ; case PRE_INC : o = GEN_INT ( <NUM_LIT> ) ; goto pre_modify ; case PRE_MODIFY : o = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; pre_modify : code = PRE_MODIFY ; break ; case POST_DEC : o = GEN_INT ( - <NUM_LIT> ) ; goto post_modify ; case POST_INC : o = GEN_INT ( <NUM_LIT> ) ; goto post_modify ; case POST_MODIFY : o = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; post_modify : code = POST_MODIFY ; swap = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } r = XEXP ( addr , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , gen_rtx_fmt_ee ( code , Pmode , r , gen_rtx_PLUS ( Pmode , r , o ) ) , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , plus_constant ( Pmode , r , <NUM_LIT> ) , <NUM_LIT> ) ; } else { xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ; xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ; } } if ( reg_overlap_mentioned_p ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ) { swap = <NUM_LIT> ;"
GCC,arc,20,"Predict the next statement of this code snippet:
 <s> intval0 = INTVAL ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ) << <NUM_LIT> ; intval0 |= INTVAL ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ) & <NUM_LIT> ; } xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; xop [ <NUM_LIT> ] = GEN_INT ( trunc_int_for_mode ( intval0 , SImode ) ) ; xop [ <NUM_LIT> ] = GEN_INT ( trunc_int_for_mode ( intval1 , SImode ) ) ; emit_move_insn ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; emit_move_insn ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; return ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( MEM_P ( operands [ i ] ) && auto_inc_p ( XEXP ( operands [ i ] , <NUM_LIT> ) ) ) { rtx addr = XEXP ( operands [ i ] , <NUM_LIT> ) ; rtx r , o ; enum rtx_code code ; gcc_assert ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , addr ) ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : o = GEN_INT ( - <NUM_LIT> ) ; goto pre_modify ; case PRE_INC : o = GEN_INT ( <NUM_LIT> ) ; goto pre_modify ; case PRE_MODIFY : o = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; pre_modify : code = PRE_MODIFY ; break ; case POST_DEC : o = GEN_INT ( - <NUM_LIT> ) ; goto post_modify ; case POST_INC : o = GEN_INT ( <NUM_LIT> ) ; goto post_modify ; case POST_MODIFY : o = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; post_modify : code = POST_MODIFY ; swap = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } r = XEXP ( addr , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , gen_rtx_fmt_ee ( code , Pmode , r , gen_rtx_PLUS ( Pmode , r , o ) ) , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , plus_constant ( Pmode , r , <NUM_LIT> ) , <NUM_LIT> ) ; } else { xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ;"
GCC,arc,21,"Predict the next statement of this code snippet:
 <s> operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ;"
GCC,arc,22,"Predict the next statement of this code snippet:
 <s> operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; }"
GCC,arc,23,"Predict the next statement of this code snippet:
 <s> operands [ <NUM_LIT> ] = gen_rtx_NEG ( SImode , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } else if ( val >= <NUM_LIT> && val < <NUM_LIT> ) { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_MINUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; }"
GCC,arc,24,"Predict the next statement of this code snippet:
 <s> int val = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( arc_check_short_reg_p ( operands [ <NUM_LIT> ] ) && arc_check_short_reg_p ( operands [ <NUM_LIT> ] ) ) { if ( val >= - <NUM_LIT> && val <= <NUM_LIT> ) { operands [ <NUM_LIT> ] = gen_rtx_NEG ( SImode , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } else if ( val >= <NUM_LIT> && val < <NUM_LIT> ) { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_MINUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } } operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_MINUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ;"
GCC,arc,25,"Predict the next statement of this code snippet:
 <s> static void workaround_arc_anomaly ( void ) { rtx_insn * insn , * succ0 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { succ0 = next_real_insn ( insn ) ; if ( arc_hazard ( insn , succ0 ) || arc_check_release31a ( insn , succ0 ) ) emit_insn_before ( gen_nopv ( ) , succ0 ) ; } if ( ! TARGET_ARC700 ) return ;"
GCC,arc,26,"Predict the next statement of this code snippet:
 <s> if ( arc_hazard ( insn , succ0 ) || arc_check_release31a ( insn , succ0 ) ) emit_insn_before ( gen_nopv ( ) , succ0 ) ; } if ( ! TARGET_ARC700 ) return ;"
GCC,arc,27,"Predict the next statement of this code snippet:
 <s> int arc_ccfsm_branch_deleted_p ( ) { if ( arc_ccfsm_state == <NUM_LIT> || arc_ccfsm_state == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;"
GCC,arc,28,"Predict the next statement of this code snippet:
 <s> int arc_ccfsm_branch_deleted_p ( ) { if ( arc_ccfsm_state == <NUM_LIT> || arc_ccfsm_state == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;"
GCC,arc,29,"Predict the next statement of this code snippet:
 <s> void arc_ccfsm_record_branch_deleted ( ) { arc_ccfsm_state += <NUM_LIT> ;"
GCC,arc,30,"Predict the next statement of this code snippet:
 <s> void arc_ccfsm_record_branch_deleted ( ) { arc_ccfsm_state += <NUM_LIT> ; current_insn_set_cc_p = last_insn_set_cc_p ;"
GCC,arc,31,"Predict the next statement of this code snippet:
 <s> if ( arc_compute_function_type ( current_function_decl ) != ARC_FUNCTION_NORMAL ) return <NUM_LIT> ; if ( ! current_frame_info . initialized ) ( void ) arc_compute_frame_size ( get_frame_size ( ) ) ;"
GCC,arc,32,"Predict the next statement of this code snippet:
 <s> if ( arc_compute_function_type ( current_function_decl ) != ARC_FUNCTION_NORMAL ) return <NUM_LIT> ; if ( ! current_frame_info . initialized ) ( void ) arc_compute_frame_size ( get_frame_size ( ) ) ; if ( current_frame_info . total_size == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;"
GCC,arc,33,"Predict the next statement of this code snippet:
 <s> void arc_finalize_pic ( ) {"
GCC,arc,34,"Predict the next statement of this code snippet:
 <s> void arc_finalize_pic ( ) {"
GCC,arc,35,"Predict the next statement of this code snippet:
 <s> arc_cpu_string = <STR_LIT> ; arc_cpu_type = <NUM_LIT> ; arc_mangle_cpu = NULL ; } arc_text_section = tmp = xmalloc ( strlen ( arc_text_string ) + sizeof ( ARC_SECTION_FORMAT ) + <NUM_LIT> ) ; sprintf ( tmp , ARC_SECTION_FORMAT , arc_text_string ) ; arc_data_section = tmp = xmalloc ( strlen ( arc_data_string ) + sizeof ( ARC_SECTION_FORMAT ) + <NUM_LIT> ) ; sprintf ( tmp , ARC_SECTION_FORMAT , arc_data_string ) ; arc_rodata_section = tmp = xmalloc ( strlen ( arc_rodata_string ) + sizeof ( ARC_SECTION_FORMAT ) + <NUM_LIT> ) ; sprintf ( tmp , ARC_SECTION_FORMAT , arc_rodata_string ) ; arc_init_reg_tables ( ) ; memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ; arc_punct_chars [ '*' ] = <NUM_LIT> ; arc_punct_chars [ '?' ] = <NUM_LIT> ; arc_punct_chars [ '!' ] = <NUM_LIT> ; arc_punct_chars [ '~' ] = <NUM_LIT> ;"
GCC,arc,36,"Predict the next statement of this code snippet:
 <s> case REG : return <NUM_LIT> ; case LABEL_REF : case SYMBOL_REF : case CONST : return <NUM_LIT> ; case PLUS : { register rtx plus0 = XEXP ( addr , <NUM_LIT> ) ; register rtx plus1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( plus0 ) != REG ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return SMALL_INT ( plus1 ) ? <NUM_LIT> : <NUM_LIT> ; case CONST : case SYMBOL_REF : case LABEL_REF : return <NUM_LIT> ; default : break ;"
GCC,arc,37,"Predict the next statement of this code snippet:
 <s> case PLUS : { register rtx plus0 = XEXP ( addr , <NUM_LIT> ) ; register rtx plus1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( plus0 ) != REG ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return SMALL_INT ( plus1 ) ? <NUM_LIT> : <NUM_LIT> ; case CONST : case SYMBOL_REF : case LABEL_REF : return <NUM_LIT> ; default : break ; } break ; } default : break ; } return <NUM_LIT> ;"
GCC,arc,38,"Predict the next statement of this code snippet:
 <s> if ( size == UNITS_PER_WORD && aligned_p && ( ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) ) || GET_CODE ( x ) == LABEL_REF ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( <STR_LIT> , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ;"
GCC,arc,39,"Predict the next statement of this code snippet:
 <s> fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( <STR_LIT> , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ;"
GCC,arc,40,"Predict the next statement of this code snippet:
 <s> void arc_ccfsm_at_label ( const char * prefix , int num ) { if ( arc_ccfsm_state == <NUM_LIT> && arc_ccfsm_target_label == num && ! strcmp ( prefix , <STR_LIT> ) ) { arc_ccfsm_state = <NUM_LIT> ; arc_ccfsm_target_insn = NULL_RTX ; }"
GCC,arc,41,"Predict the next statement of this code snippet:
 <s> if ( arc_ccfsm_state == <NUM_LIT> || arc_ccfsm_state == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;"
GCC,arc,42,"Predict the next statement of this code snippet:
 <s> if ( arc_ccfsm_state == <NUM_LIT> || arc_ccfsm_state == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;"
GCC,arc,43,"Predict the next statement of this code snippet:
 <s> arc_ccfsm_state += <NUM_LIT> ;"
GCC,arc,44,"Predict the next statement of this code snippet:
 <s> unsigned int arc_compute_frame_size ( int size ) { int regno ; unsigned int total_size , var_size , args_size , pretend_size , extra_size ; unsigned int reg_size , reg_offset ; unsigned int gmask ; enum arc_function_type fn_type ; int interrupt_p ; var_size = size ; args_size = current_function_outgoing_args_size ; pretend_size = current_function_pretend_args_size ; extra_size = FIRST_PARM_OFFSET ( <NUM_LIT> ) ; total_size = extra_size + pretend_size + args_size + var_size ; reg_offset = FIRST_PARM_OFFSET ( <NUM_LIT> ) + current_function_outgoing_args_size ; reg_size = <NUM_LIT> ; gmask = <NUM_LIT> ; fn_type = arc_compute_function_type ( current_function_decl ) ; interrupt_p = ARC_INTERRUPT_P ( fn_type ) ; for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( MUST_SAVE_REGISTER ( regno , interrupt_p ) ) { reg_size += UNITS_PER_WORD ; gmask |= <NUM_LIT> << regno ; } } total_size += reg_size ; if ( total_size == extra_size && ! MUST_SAVE_RETURN_ADDR ) total_size = extra_size = <NUM_LIT> ; total_size = ARC_STACK_ALIGN ( total_size ) ; current_frame_info . total_size = total_size ; current_frame_info . extra_size = extra_size ; current_frame_info . pretend_size = pretend_size ; current_frame_info . var_size = var_size ; current_frame_info . args_size = args_size ; current_frame_info . reg_size = reg_size ; current_frame_info . reg_offset = reg_offset ;"
GCC,arc,45,"Predict the next statement of this code snippet:
 <s> return fn_type ; } if ( decl == last_fn && fn_type != ARC_FUNCTION_UNKNOWN ) return fn_type ; fn_type = ARC_FUNCTION_NORMAL ; for ( a = DECL_ATTRIBUTES ( current_function_decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) , args = TREE_VALUE ( a ) ; if ( name == get_identifier ( <STR_LIT> ) && list_length ( args ) == <NUM_LIT> && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST ) {"
GCC,arc,46,"Predict the next statement of this code snippet:
 <s> if ( ! current_frame_info . initialized ) ( void ) arc_compute_frame_size ( get_frame_size ( ) ) ; if ( current_frame_info . total_size == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;"
GCC,arc,47,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT low , high ; gcc_assert ( GET_CODE ( value ) == CONST_DOUBLE ) ; low = CONST_DOUBLE_LOW ( value ) ; high = CONST_DOUBLE_HIGH ( value ) ; if ( low & <NUM_LIT> ) { return ( ( ( unsigned HOST_WIDE_INT ) low <= <NUM_LIT> && high == <NUM_LIT> ) || ( ( ( low & - ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) == - ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) && high == - <NUM_LIT> ) ) ; }"
GCC,arc,48,"Predict the next statement of this code snippet:
 <s> if ( get_attr_length ( trial ) == <NUM_LIT> && current_frame_info . gmask == <NUM_LIT> && ! reg_mentioned_p ( stack_pointer_rtx , PATTERN ( trial ) ) && ! reg_mentioned_p ( frame_pointer_rtx , PATTERN ( trial ) ) ) return <NUM_LIT> ;"
GCC,arc,49,"Predict the next statement of this code snippet:
 <s> fprintf ( FILE , <STR_LIT> , XSTR ( SYMREF , <NUM_LIT> ) , XSTR ( SYMREF , <NUM_LIT> ) , arc_mangle_suffix ) ;"
GCC,arc,50,"Predict the next statement of this code snippet:
 <s> default_file_start ( ) ;"
GCC,arc,51,"Predict the next statement of this code snippet:
 <s> static void arc_file_start ( void ) { default_file_start ( ) ; fprintf ( asm_out_file , <STR_LIT> , arc_cpu_string ) ;"
GCC,arc,52,"Predict the next statement of this code snippet:
 <s> int insns_skipped = <NUM_LIT> , fail = FALSE , succeed = FALSE ; int then_not_else = TRUE ; int next_must_be_target_label_p ; rtx this_insn = start_insn , label = <NUM_LIT> ; if ( reverse ) { if ( ! seeking_return ) label = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; } else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) { label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; then_not_else = FALSE ; } else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == RETURN ) seeking_return = <NUM_LIT> ; else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == RETURN ) { seeking_return = <NUM_LIT> ; then_not_else = FALSE ; } else gcc_unreachable ( ) ; for ( insns_skipped = <NUM_LIT> , next_must_be_target_label_p = FALSE ; ! fail && ! succeed && insns_skipped < MAX_INSNS_SKIPPED ; insns_skipped ++ ) { rtx scanbody ; this_insn = next_nonnote_insn ( this_insn ) ; if ( ! this_insn ) break ; if ( next_must_be_target_label_p ) { if ( GET_CODE ( this_insn ) == BARRIER ) continue ; if ( GET_CODE ( this_insn ) == CODE_LABEL && this_insn == label ) { arc_ccfsm_state = <NUM_LIT> ; succeed = TRUE ; } else fail = TRUE ; break ; } scanbody = PATTERN ( this_insn ) ; switch ( GET_CODE ( this_insn ) ) { case CODE_LABEL : if ( this_insn == label ) { arc_ccfsm_state = <NUM_LIT> ; succeed = TRUE ; } else fail = TRUE ; break ; case BARRIER : next_must_be_target_label_p = TRUE ; break ; case CALL_INSN : if ( get_attr_cond ( this_insn ) == COND_CANUSE ) next_must_be_target_label_p = TRUE ; else fail = TRUE ; break ;"
GCC,arc,53,"Predict the next statement of this code snippet:
 <s> case OPT_mcpu_ : return strcmp ( arg , <STR_LIT> ) == <NUM_LIT> || ARC_EXTENSION_CPU ( arg ) ;"
GCC,arc,54,"Predict the next statement of this code snippet:
 <s> memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ; arc_punct_chars [ '*' ] = <NUM_LIT> ; arc_punct_chars [ '?' ] = <NUM_LIT> ; arc_punct_chars [ '!' ] = <NUM_LIT> ;"
GCC,arc,55,"Predict the next statement of this code snippet:
 <s> void arc_initialize_trampoline ( rtx tramp ATTRIBUTE_UNUSED , rtx fnaddr ATTRIBUTE_UNUSED , rtx cxt ATTRIBUTE_UNUSED ) {"
GCC,arc,56,"Predict the next statement of this code snippet:
 <s> void arc_initialize_trampoline ( rtx tramp ATTRIBUTE_UNUSED , rtx fnaddr ATTRIBUTE_UNUSED , rtx cxt ATTRIBUTE_UNUSED ) {"
GCC,arc,57,"Predict the next statement of this code snippet:
 <s> else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) O_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( i ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) OF_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_CC : arc_mode_class [ i ] = <NUM_LIT> << ( int ) C_MODE ; break ; default :"
GCC,arc,58,"Predict the next statement of this code snippet:
 <s> case MODE_COMPLEX_INT : if ( GET_MODE_SIZE ( i ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) S_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) O_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( i ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) OF_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_CC : arc_mode_class [ i ] = <NUM_LIT> << ( int ) C_MODE ; break ; default : arc_mode_class [ i ] = <NUM_LIT> ;"
GCC,arc,59,"Predict the next statement of this code snippet:
 <s> static void arc_internal_label ( FILE * stream , const char * prefix , unsigned long labelno ) {"
GCC,arc,60,"Predict the next statement of this code snippet:
 <s> final_scan_insn ( XEXP ( epilogue_delay , <NUM_LIT> ) , file , <NUM_LIT> , <NUM_LIT> , NULL ) ; } } { static const int regs [ <NUM_LIT> ] = { <NUM_LIT> , RETURN_ADDR_REGNUM , ILINK1_REGNUM , ILINK2_REGNUM } ; if ( ARC_INTERRUPT_P ( fn_type ) ) fprintf ( file , <STR_LIT> , reg_names [ regs [ fn_type ] ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ regs [ fn_type ] ] ) ; } if ( ARC_INTERRUPT_P ( fn_type ) ) fprintf ( file , <STR_LIT> , sp_str , sp_str ) ; else if ( epilogue_delay != NULL_RTX ) { gcc_assert ( ! frame_pointer_needed || fp_restored_p ) ; gcc_assert ( restored >= size ) ; final_scan_insn ( XEXP ( epilogue_delay , <NUM_LIT> ) , file , <NUM_LIT> , <NUM_LIT> , NULL ) ; } else if ( frame_pointer_needed && ! fp_restored_p ) { gcc_assert ( SMALL_INT ( frame_size ) ) ; fprintf ( file , <STR_LIT> , fp_str , sp_str , frame_size ) ; } else if ( restored < size ) { gcc_assert ( SMALL_INT ( size - restored ) ) ;"
GCC,arc,61,"Predict the next statement of this code snippet:
 <s> fprintf ( file , <STR_LIT> , ASM_COMMENT_START , ASM_COMMENT_START , current_frame_info . var_size , current_frame_info . reg_size / <NUM_LIT> , current_frame_info . args_size , current_frame_info . extra_size ) ; size = ARC_STACK_ALIGN ( size ) ; size = ( ! current_frame_info . initialized ? arc_compute_frame_size ( size ) : current_frame_info . total_size ) ; gcc_assert ( size || ! gmask ) ; if ( current_frame_info . pretend_size != <NUM_LIT> ) fprintf ( file , <STR_LIT> , sp_str , sp_str , current_frame_info . pretend_size ) ; if ( MUST_SAVE_RETURN_ADDR ) fprintf ( file , <STR_LIT> , reg_names [ RETURN_ADDR_REGNUM ] , sp_str , UNITS_PER_WORD ) ; if ( frame_pointer_needed ) { fprintf ( file , <STR_LIT> , fp_str , sp_str ) ;"
GCC,arc,62,"Predict the next statement of this code snippet:
 <s> fputs ( reg_names [ REGNO ( addr ) ] , file ) ; break ; case SYMBOL_REF : if ( <NUM_LIT> && SYMBOL_REF_FUNCTION_P ( addr ) ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , addr ) ; fprintf ( file , <STR_LIT> ) ; } else output_addr_const ( file , addr ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT ) offset = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) , base = XEXP ( addr , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT ) offset = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) , base = XEXP ( addr , <NUM_LIT> ) ; else base = XEXP ( addr , <NUM_LIT> ) , index = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( base ) == REG ) ; fputs ( reg_names [ REGNO ( base ) ] , file ) ;"
GCC,arc,63,"Predict the next statement of this code snippet:
 <s> if ( AGGREGATE_TYPE_P ( type ) ) return true ; else { HOST_WIDE_INT size = int_size_in_bytes ( type ) ;"
GCC,arc,64,"Predict the next statement of this code snippet:
 <s> if ( AGGREGATE_TYPE_P ( type ) ) return true ; else {"
GCC,arc,65,"Predict the next statement of this code snippet:
 <s> * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case CONST_DOUBLE : { rtx high , low ; split_double ( x , & high , & low ) ; * total = COSTS_N_INSNS ( ! SMALL_INT ( INTVAL ( high ) ) + ! SMALL_INT ( INTVAL ( low ) ) ) ; return true ; } case ASHIFT : case ASHIFTRT :"
GCC,arc,66,"Predict the next statement of this code snippet:
 <s> for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( ( gmask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) { fprintf ( file , <STR_LIT> , op , reg_names [ regno ] , base_reg , offset ) ;"
GCC,arc,67,"Predict the next statement of this code snippet:
 <s> if ( ( gmask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) { fprintf ( file , <STR_LIT> , op , reg_names [ regno ] , base_reg , offset ) ;"
GCC,arc,68,"Predict the next statement of this code snippet:
 <s> return CCZNmode ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : return CCZNCmode ; default : break ; } } return CCmode ;"
GCC,arc,69,"Predict the next statement of this code snippet:
 <s> int first_anon_arg ; gcc_assert ( mode != BLKmode ) ; first_anon_arg = * cum + ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; if ( first_anon_arg < MAX_ARC_PARM_REGS && ! no_rtl ) { int first_reg_offset = first_anon_arg ; int size = MAX_ARC_PARM_REGS - first_reg_offset ;"
GCC,arc,70,"Predict the next statement of this code snippet:
 <s> void arc_va_start ( tree valist , rtx nextarg ) { if ( current_function_args_info < <NUM_LIT> && ( current_function_args_info & <NUM_LIT> ) ) nextarg = plus_constant ( nextarg , UNITS_PER_WORD ) ;"
GCC,arc,71,"Predict the next statement of this code snippet:
 <s> return ( symbolic_operand ( op , mode ) || ( GET_CODE ( op ) == CONST_INT && LEGITIMATE_CONSTANT_P ( op ) ) || ( GET_CODE ( op ) == REG ) ) ;"
GCC,arc,72,"Predict the next statement of this code snippet:
 <s> int call_operand ( rtx op , enum machine_mode mode ) {"
GCC,arc,73,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( op ) != MEM ) return <NUM_LIT> ; op = XEXP ( op , <NUM_LIT> ) ; return call_address_operand ( op , mode ) ;"
GCC,arc,74,"Predict the next statement of this code snippet:
 <s> return ( GET_CODE ( op ) == CONST_INT && ( INTVAL ( op ) >= ( - <NUM_LIT> - <NUM_LIT> ) && INTVAL ( op ) <= <NUM_LIT> ) ) ;"
GCC,arc,75,"Predict the next statement of this code snippet:
 <s> return ( GET_CODE ( op ) == CONST_INT && ( INTVAL ( op ) >= <NUM_LIT> && INTVAL ( op ) <= <NUM_LIT> ) ) ;"
GCC,arc,76,"Predict the next statement of this code snippet:
 <s> int const_uint32_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) {"
GCC,arc,77,"Predict the next statement of this code snippet:
 <s> rtx cc_reg ; cc_reg = gen_rtx_REG ( mode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ;"
GCC,arc,78,"Predict the next statement of this code snippet:
 <s> static int get_arc_condition_code ( rtx comparison ) { switch ( GET_CODE ( comparison ) ) { case EQ : return <NUM_LIT> ; case NE : return <NUM_LIT> ; case GT : return <NUM_LIT> ; case LE : return <NUM_LIT> ; case GE : return <NUM_LIT> ; case LT : return <NUM_LIT> ;"
GCC,arc,79,"Predict the next statement of this code snippet:
 <s> case LEU : return <NUM_LIT> ; case LTU : return <NUM_LIT> ; case GEU : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } return ( <NUM_LIT> ) ;"
GCC,arc,80,"Predict the next statement of this code snippet:
 <s> op = XEXP ( op , <NUM_LIT> ) ;"
GCC,arc,81,"Predict the next statement of this code snippet:
 <s> return <NUM_LIT> ; case CONST_INT : return <NUM_LIT> ; case CONST_DOUBLE : return <NUM_LIT> ; case REG : return <NUM_LIT> ; case PLUS : if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT && ! SMALL_INT ( INTVAL ( XEXP ( op , <NUM_LIT> ) ) ) ) return <NUM_LIT> ; return <NUM_LIT> ;"
GCC,arc,82,"Predict the next statement of this code snippet:
 <s> int long_immediate_loadstore_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) != MEM ) return <NUM_LIT> ; op = XEXP ( op , <NUM_LIT> ) ; switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : case CONST : return <NUM_LIT> ; case CONST_INT : return <NUM_LIT> ;"
GCC,arc,83,"Predict the next statement of this code snippet:
 <s> int long_immediate_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : case CONST : return <NUM_LIT> ; case CONST_INT : return ! SMALL_INT ( INTVAL ( op ) ) ; case CONST_DOUBLE :"
GCC,arc,84,"Predict the next statement of this code snippet:
 <s> else return register_operand ( op , mode ) ; case MEM : return address_operand ( XEXP ( op , <NUM_LIT> ) , mode ) ; default : return <NUM_LIT> ;"
GCC,arc,85,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( SUBREG_REG ( op ) ) == MEM ) return move_double_src_operand ( SUBREG_REG ( op ) , mode ) ; else return register_operand ( op , mode ) ; case MEM : if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PRE_DEC || GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PRE_INC ) return <NUM_LIT> ; return address_operand ( XEXP ( op , <NUM_LIT> ) , mode ) ;"
GCC,arc,86,"Predict the next statement of this code snippet:
 <s> case LABEL_REF : case CONST : return <NUM_LIT> ; case CONST_INT : return ( LARGE_INT ( INTVAL ( op ) ) ) ; case CONST_DOUBLE : if ( mode == SImode ) return arc_double_limm_p ( op ) ; if ( mode == SFmode ) return GET_MODE ( op ) == SFmode ; return <NUM_LIT> ; case REG : return register_operand ( op , mode ) ; case SUBREG : if ( GET_CODE ( SUBREG_REG ( op ) ) == MEM ) return address_operand ( XEXP ( SUBREG_REG ( op ) , <NUM_LIT> ) , mode ) ; else return register_operand ( op , mode ) ; case MEM : return address_operand ( XEXP ( op , <NUM_LIT> ) , mode ) ; default : return <NUM_LIT> ;"
GCC,arc,87,"Predict the next statement of this code snippet:
 <s> case LABEL_REF : case CONST : return <NUM_LIT> ; case CONST_INT : return ( LARGE_INT ( INTVAL ( op ) ) ) ; case CONST_DOUBLE : if ( mode == SImode ) return arc_double_limm_p ( op ) ; if ( mode == SFmode ) return GET_MODE ( op ) == SFmode ; return <NUM_LIT> ; case REG : return register_operand ( op , mode ) ; case SUBREG : if ( GET_CODE ( SUBREG_REG ( op ) ) == MEM ) return address_operand ( XEXP ( SUBREG_REG ( op ) , <NUM_LIT> ) , mode ) ; else return register_operand ( op , mode ) ; case MEM : return address_operand ( XEXP ( op , <NUM_LIT> ) , mode ) ; default : return <NUM_LIT> ; }"
GCC,arc,88,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( op ) == MEM && MEM_VOLATILE_P ( op ) ) return <NUM_LIT> ; return nonimmediate_operand ( op , mode ) ;"
GCC,arc,89,"Predict the next statement of this code snippet:
 <s> int nonvol_nonimm_operand ( rtx op , enum machine_mode mode ) {"
GCC,arc,90,"Predict the next statement of this code snippet:
 <s> output_asm_insn ( <STR_LIT> , operands ) ; } else output_asm_insn ( <STR_LIT> , operands ) ; goto shiftloop ; } else { int n = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( n < <NUM_LIT> ) n = <NUM_LIT> ; else if ( n > GET_MODE_BITSIZE ( mode ) ) n = GET_MODE_BITSIZE ( mode ) ; if ( n <= <NUM_LIT> ) { while ( -- n >= <NUM_LIT> ) output_asm_insn ( shift_one , operands ) ; } else if ( n == BITS_PER_WORD - <NUM_LIT> ) { switch ( code ) { case ASHIFT : output_asm_insn ( <STR_LIT> , operands ) ; break ; case ASHIFTRT : output_asm_insn ( <STR_LIT> , operands ) ; break ; case LSHIFTRT : output_asm_insn ( <STR_LIT> , operands ) ; break ; default : break ; } } else { char buf [ <NUM_LIT> ] ; if ( optimize ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; shiftloop : if ( optimize ) { if ( flag_pic ) sprintf ( buf , <STR_LIT> , ASM_COMMENT_START ) ; else sprintf ( buf , <STR_LIT> , ASM_COMMENT_START ) ; output_asm_insn ( buf , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( flag_pic ) fprintf ( asm_out_file , <STR_LIT> , ASM_COMMENT_START ) ; else fprintf ( asm_out_file , <STR_LIT> , ASM_COMMENT_START ) ; output_asm_insn ( shift_one , operands ) ; fprintf ( asm_out_file , <STR_LIT> , ASM_COMMENT_START ) ; } else { fprintf ( asm_out_file , <STR_LIT> , ASM_COMMENT_START ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( shift_one , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; fprintf ( asm_out_file , <STR_LIT> , ASM_COMMENT_START ) ; }"
GCC,arc,91,"Predict the next statement of this code snippet:
 <s> if ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == CCZNmode ) return ( code == EQ || code == NE ) ; if ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == CCZNCmode ) return ( code == EQ || code == NE || code == LTU || code == GEU || code == GTU || code == LEU ) ;"
GCC,arc,92,"Predict the next statement of this code snippet:
 <s> static void record_cc_ref ( rtx insn ) { last_insn_set_cc_p = current_insn_set_cc_p ; switch ( get_attr_cond ( insn ) ) { case COND_SET : case COND_SET_ZN :"
GCC,arc,93,"Predict the next statement of this code snippet:
 <s> static void record_cc_ref ( rtx insn ) { last_insn_set_cc_p = current_insn_set_cc_p ; switch ( get_attr_cond ( insn ) ) { case COND_SET : case COND_SET_ZN : case COND_SET_ZNC : if ( get_attr_length ( insn ) == <NUM_LIT> ) current_insn_set_cc_p = <NUM_LIT> ; else current_insn_set_cc_p = <NUM_LIT> ;"
GCC,arc,94,"Predict the next statement of this code snippet:
 <s> int short_immediate_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) != CONST_INT ) return <NUM_LIT> ;"
GCC,arc,95,"Predict the next statement of this code snippet:
 <s> op = XEXP ( op , <NUM_LIT> ) ;"
GCC,arc,96,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( op ) != PLUS || GET_MODE ( op ) != Pmode || ! register_operand ( XEXP ( op , <NUM_LIT> ) , Pmode ) || ! ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT && SMALL_INT ( INTVAL ( XEXP ( op , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; return <NUM_LIT> ;"
GCC,arc,97,"Predict the next statement of this code snippet:
 <s> int symbolic_memory_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( GET_CODE ( op ) != MEM ) return <NUM_LIT> ; op = XEXP ( op , <NUM_LIT> ) ;"
GCC,arc,98,"Predict the next statement of this code snippet:
 <s> op = XEXP ( op , <NUM_LIT> ) ;"
GCC,arc,99,"Predict the next statement of this code snippet:
 <s> case LABEL_REF : case CONST : return <NUM_LIT> ; default : return <NUM_LIT> ; }"
GCC,arc,100,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( PATTERN ( succ ) ) == SEQUENCE ) succ = as_a < rtx_sequence * > ( PATTERN ( succ ) ) -> insn ( <NUM_LIT> ) ; if ( recog_memoized ( pred ) == CODE_FOR_mulsi_600 || recog_memoized ( pred ) == CODE_FOR_umul_600 || recog_memoized ( pred ) == CODE_FOR_mac_600 || recog_memoized ( pred ) == CODE_FOR_mul64_600 || recog_memoized ( pred ) == CODE_FOR_mac64_600 || recog_memoized ( pred ) == CODE_FOR_umul64_600 || recog_memoized ( pred ) == CODE_FOR_umac64_600 ) return <NUM_LIT> ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( pred ) , NONCONST ) { const_rtx x = * iter ; switch ( GET_CODE ( x ) ) { case SET : case POST_INC : case POST_DEC : case PRE_INC : case PRE_DEC : break ; default : continue ;"
GCC,arc,101,"Predict the next statement of this code snippet:
 <s> case PLUS : { register rtx plus0 = XEXP ( addr , <NUM_LIT> ) ; register rtx plus1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) != MULT || ! CONST_INT_P ( XEXP ( plus0 , <NUM_LIT> ) ) || ( INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> && INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> ) ) ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return ( ! RTX_OK_FOR_OFFSET_P ( SImode , plus1 ) ? COSTS_N_INSNS ( <NUM_LIT> ) : speed ? <NUM_LIT> : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_O ( plus1 ) ) ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,102,"Predict the next statement of this code snippet:
 <s> rtx_insn * prev = prev_nonnote_insn ( insn ) ; return ( ( LABEL_P ( prev ) || ( TARGET_ARC600 && ( JUMP_P ( prev ) || CALL_P ( prev ) || ( NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == SEQUENCE ) ) ) ) ? len + <NUM_LIT> : len ) ; } if ( TARGET_PAD_RETURN && JUMP_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && get_attr_type ( insn ) == TYPE_RETURN ) { rtx_insn * prev = prev_active_insn ( insn ) ; if ( ! prev || ! ( prev = prev_active_insn ( prev ) ) || ( ( NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == SEQUENCE ) ? CALL_ATTR ( as_a < rtx_sequence * > ( PATTERN ( prev ) ) -> insn ( <NUM_LIT> ) , NON_SIBCALL ) : CALL_ATTR ( prev , NON_SIBCALL ) ) ) return len + <NUM_LIT> ; } if ( TARGET_ARC600 ) { rtx_insn * succ = next_real_insn ( insn ) ; if ( succ && INSN_P ( succ ) ) len += arc600_corereg_hazard ( insn , succ ) ; }"
GCC,arc,103,"Predict the next statement of this code snippet:
 <s> if ( recog_memoized ( insn ) == CODE_FOR_doloop_end_i ) { rtx_insn * prev = prev_nonnote_insn ( insn ) ; return ( ( LABEL_P ( prev ) || ( TARGET_ARC600 && ( JUMP_P ( prev ) || CALL_P ( prev ) || ( NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == SEQUENCE ) ) ) ) ? len + <NUM_LIT> : len ) ; } if ( TARGET_PAD_RETURN && JUMP_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && get_attr_type ( insn ) == TYPE_RETURN ) {"
GCC,arc,104,"Predict the next statement of this code snippet:
 <s> static int arc_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes = ( mode == BLKmode ? int_size_in_bytes ( type ) : ( int ) GET_MODE_SIZE ( mode ) ) ;"
GCC,arc,105,"Predict the next statement of this code snippet:
 <s> int words = ( bytes + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; int arg_num = * cum ; int ret ; arg_num = ROUND_ADVANCE_CUM ( arg_num , mode , type ) ;"
GCC,arc,106,"Predict the next statement of this code snippet:
 <s> int in_small_data = arc_in_small_data_p ( decl ) ; if ( in_small_data ) switch_to_section ( get_named_section ( NULL , <STR_LIT> , <NUM_LIT> ) ) ; else switch_to_section ( bss_section ) ; if ( globalize_p ) ( * targetm . asm_out . globalize_label ) ( stream , name ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( ( align ) / BITS_PER_UNIT ) ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , <STR_LIT> ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name , size ) ; ASM_OUTPUT_LABEL ( stream , name ) ; if ( size != <NUM_LIT> ) ASM_OUTPUT_SKIP ( stream , size ) ;"
GCC,arc,107,"Predict the next statement of this code snippet:
 <s> int in_small_data = arc_in_small_data_p ( decl ) ; if ( in_small_data ) switch_to_section ( get_named_section ( NULL , <STR_LIT> , <NUM_LIT> ) ) ; else switch_to_section ( bss_section ) ; if ( globalize_p ) ( * targetm . asm_out . globalize_label ) ( stream , name ) ;"
GCC,arc,108,"Predict the next statement of this code snippet:
 <s> if ( NONJUMP_INSN_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) : JUMP_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == ADDR_VEC || GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC ) : ! CALL_P ( insn ) ) return - <NUM_LIT> ;"
GCC,arc,109,"Predict the next statement of this code snippet:
 <s> union { const rtx_insn * c ; rtx_insn * r ; } u ; u . c = follower ; if ( CROSSING_JUMP_P ( followee ) ) switch ( get_attr_type ( u . r ) ) { case TYPE_BRCC : case TYPE_BRCC_NO_DELAY_SLOT : return false ; default : return true ; } return true ;"
GCC,arc,110,"Predict the next statement of this code snippet:
 <s> static bool arc_can_use_doloop_p ( const widest_int & iterations , const widest_int & , unsigned int loop_depth , bool entered_at_top ) { if ( loop_depth > <NUM_LIT> ) return false ;"
GCC,arc,111,"Predict the next statement of this code snippet:
 <s> if ( TARGET_ARC700 && ! entered_at_top && wi :: gtu_p ( iterations , <NUM_LIT> ) && wi :: leu_p ( iterations , flag_pic ? <NUM_LIT> : <NUM_LIT> ) ) return false ;"
GCC,arc,112,"Predict the next statement of this code snippet:
 <s> else { rtx src = SET_SRC ( PATTERN ( insn ) ) ; arc_ccfsm_record_condition ( XEXP ( src , <NUM_LIT> ) , XEXP ( src , <NUM_LIT> ) == pc_rtx , insn , state ) ; } }"
GCC,arc,113,"Predict the next statement of this code snippet:
 <s> int interrupt_p ; struct arc_frame_info * frame_info = & cfun -> machine -> frame_info ; size = ARC_STACK_ALIGN ( size ) ; var_size = size ; args_size = crtl -> outgoing_args_size ; reg_size = <NUM_LIT> ; gmask = <NUM_LIT> ; fn_type = arc_compute_function_type ( cfun ) ; interrupt_p = ARC_INTERRUPT_P ( fn_type ) ; for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( MUST_SAVE_REGISTER ( regno , interrupt_p ) ) { reg_size += UNITS_PER_WORD ; gmask |= <NUM_LIT> << regno ; } } frame_info -> save_return_addr = ( ! crtl -> is_leaf || df_regs_ever_live_p ( RETURN_ADDR_REGNUM ) ) ; if ( optimize_size && ! TARGET_NO_MILLICODE_THUNK_SET ) { if ( arc_compute_millicode_save_restore_regs ( gmask , frame_info ) ) frame_info -> save_return_addr = true ; } extra_size = <NUM_LIT> ; if ( MUST_SAVE_RETURN_ADDR ) extra_size = <NUM_LIT> ; if ( frame_pointer_needed ) extra_size += <NUM_LIT> ; pretend_size = crtl -> args . pretend_args_size ; { unsigned int extra_plus_reg_size ; unsigned int extra_plus_reg_size_aligned ; extra_plus_reg_size = extra_size + reg_size ; extra_plus_reg_size_aligned = ARC_STACK_ALIGN ( extra_plus_reg_size ) ; reg_size = extra_plus_reg_size_aligned - extra_size ; } total_size = var_size + args_size + extra_size + pretend_size + reg_size ; total_size = ARC_STACK_ALIGN ( total_size ) ; reg_offset = ( total_size - ( pretend_size + reg_size + extra_size ) + ( frame_pointer_needed ? <NUM_LIT> : <NUM_LIT> ) ) ; frame_info -> total_size = total_size ; frame_info -> extra_size = extra_size ; frame_info -> pretend_size = pretend_size ; frame_info -> var_size = var_size ; frame_info -> args_size = args_size ; frame_info -> reg_size = reg_size ; frame_info -> reg_offset = reg_offset ;"
GCC,arc,114,"Predict the next statement of this code snippet:
 <s> fn_type = ARC_FUNCTION_NORMAL ; for ( a = DECL_ATTRIBUTES ( decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) , args = TREE_VALUE ( a ) ; if ( name == get_identifier ( <STR_LIT> ) && list_length ( args ) == <NUM_LIT> && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST ) { tree value = TREE_VALUE ( args ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type = ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type = ARC_FUNCTION_ILINK2 ; else gcc_unreachable ( ) ; break ; } }"
GCC,arc,115,"Predict the next statement of this code snippet:
 <s> fn_type = ARC_FUNCTION_NORMAL ; for ( a = DECL_ATTRIBUTES ( decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) , args = TREE_VALUE ( a ) ; if ( name == get_identifier ( <STR_LIT> ) && list_length ( args ) == <NUM_LIT> && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST ) { tree value = TREE_VALUE ( args ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type = ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type = ARC_FUNCTION_ILINK2 ; else gcc_unreachable ( ) ; break ; } } return fun -> machine -> fn_type = fn_type ;"
GCC,arc,116,"Predict the next statement of this code snippet:
 <s> for ( regno = start_reg ; regno <= end_reg && ( gmask & ( <NUM_LIT> << regno ) ) ; ) regno ++ ; end_reg = regno - <NUM_LIT> ; if ( regno - start_reg >= <NUM_LIT> - ( crtl -> is_leaf == <NUM_LIT> ) ) { frame -> millicode_start_reg = <NUM_LIT> ; frame -> millicode_end_reg = regno - <NUM_LIT> ; return <NUM_LIT> ;"
GCC,arc,117,"Predict the next statement of this code snippet:
 <s> static bool arc_decl_anon_ns_mem_p ( const_tree decl ) { while ( <NUM_LIT> ) { if ( decl == NULL_TREE || decl == error_mark_node ) return false ;"
GCC,arc,118,"Predict the next statement of this code snippet:
 <s> int arc_decl_pretend_args ( tree decl ) {"
GCC,arc,119,"Predict the next statement of this code snippet:
 <s> if ( x ) { if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ; } return orig_x ;"
GCC,arc,120,"Predict the next statement of this code snippet:
 <s> } else if ( GET_CODE ( x ) == PLUS && ( ( REG_P ( gp = XEXP ( x , <NUM_LIT> ) ) && REGNO ( gp ) == PIC_OFFSET_TABLE_REGNUM ) || ( GET_CODE ( gp ) == CONST && GET_CODE ( u = XEXP ( gp , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOT && GET_CODE ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF && ! strcmp ( XSTR ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , <STR_LIT> ) ) ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST && GET_CODE ( u = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOTOFF ) return XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ; else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && ( ( REG_P ( gp = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && REGNO ( gp ) == PIC_OFFSET_TABLE_REGNUM ) || ( GET_CODE ( gp ) == CONST && GET_CODE ( u = XEXP ( gp , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOT && GET_CODE ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF && ! strcmp ( XSTR ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , <STR_LIT> ) ) ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST && GET_CODE ( u = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOTOFF ) return gen_rtx_PLUS ( GET_MODE ( x ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ) ;"
GCC,arc,121,"Predict the next statement of this code snippet:
 <s> static void arc_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { rtx symbol = XEXP ( rtl , <NUM_LIT> ) ; int flags = SYMBOL_REF_FLAGS ( symbol ) ; tree attr = ( TREE_TYPE ( decl ) != error_mark_node ? TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) : NULL_TREE ) ; tree long_call_attr = lookup_attribute ( <STR_LIT> , attr ) ; tree medium_call_attr = lookup_attribute ( <STR_LIT> , attr ) ; tree short_call_attr = lookup_attribute ( <STR_LIT> , attr ) ; if ( long_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_LONG_CALL ; else if ( medium_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_MEDIUM_CALL ; else if ( short_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_SHORT_CALL ;"
GCC,arc,122,"Predict the next statement of this code snippet:
 <s> if ( reload_completed ) { if ( ARC_INTERRUPT_P ( cfun -> machine -> fn_type ) ) { if ( ! fixed_regs [ regno ] ) return true ;"
GCC,arc,123,"Predict the next statement of this code snippet:
 <s> if ( sibthunk_p ) goto epilogue_done ; } if ( ( ! SMALL_INT ( first_offset ) && cfun -> machine -> frame_info . gmask && ( ( TARGET_ARC700 && ! optimize_size ) ? first_offset <= <NUM_LIT> : satisfies_constraint_C2a ( GEN_INT ( first_offset ) ) ) ) || ( MUST_SAVE_RETURN_ADDR && ! SMALL_INT ( ( cfun -> machine -> frame_info . reg_size + first_offset ) >> <NUM_LIT> ) && cfun -> machine -> frame_info . gmask ) ) { frame_stack_add ( first_offset ) ; first_offset = <NUM_LIT> ; } if ( MUST_SAVE_RETURN_ADDR ) { rtx ra = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; int ra_offs = cfun -> machine -> frame_info . reg_size + first_offset ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , ra_offs ) ; if ( ! SMALL_INT ( ra_offs >> <NUM_LIT> ) && ! cfun -> machine -> frame_info . gmask && ( ( TARGET_ARC700 && ! optimize_size ) ? ra_offs <= <NUM_LIT> : satisfies_constraint_C2a ( GEN_INT ( ra_offs ) ) ) ) { size_to_deallocate -= ra_offs - first_offset ; first_offset = <NUM_LIT> ; frame_stack_add ( ra_offs ) ; ra_offs = <NUM_LIT> ; addr = stack_pointer_rtx ; } if ( ra_offs && ! cfun -> machine -> frame_info . gmask && ( SMALL_INT ( ra_offs ) || ! SMALL_INT ( ra_offs >> <NUM_LIT> ) ) ) { addr = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , addr ) ; first_offset = <NUM_LIT> ; size_to_deallocate -= cfun -> machine -> frame_info . reg_size ; } else if ( ! ra_offs && size_to_deallocate == UNITS_PER_WORD ) { addr = gen_rtx_POST_INC ( Pmode , addr ) ; size_to_deallocate = <NUM_LIT> ; }"
GCC,arc,124,"Predict the next statement of this code snippet:
 <s> unsigned n_pieces ; int piece = align ; rtx store [ <NUM_LIT> ] ; rtx tmpx [ <NUM_LIT> ] ; int i ; if ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) ) return false ; size = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( align >= <NUM_LIT> ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> + ( size & <NUM_LIT> ) ; else if ( align == <NUM_LIT> ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> ; else n_pieces = size ; if ( n_pieces >= ( unsigned int ) ( optimize_size ? <NUM_LIT> : <NUM_LIT> ) ) return false ; if ( piece > <NUM_LIT> ) piece = <NUM_LIT> ; dst_addr = force_offsettable ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , size , <NUM_LIT> ) ; src_addr = force_offsettable ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , size , <NUM_LIT> ) ; store [ <NUM_LIT> ] = store [ <NUM_LIT> ] = NULL_RTX ; tmpx [ <NUM_LIT> ] = tmpx [ <NUM_LIT> ] = NULL_RTX ; for ( i = <NUM_LIT> ; size > <NUM_LIT> ; i ^= <NUM_LIT> , size -= piece ) { rtx tmp ; machine_mode mode ; if ( piece > size ) piece = size & - size ; mode = smallest_mode_for_size ( piece * BITS_PER_UNIT , MODE_INT ) ; if ( <NUM_LIT> && tmpx [ i ] && GET_MODE ( tmpx [ i ] ) == mode ) tmp = tmpx [ i ] ; else tmpx [ i ] = tmp = gen_reg_rtx ( mode ) ; dst_addr = force_offsettable ( dst_addr , piece , <NUM_LIT> ) ; src_addr = force_offsettable ( src_addr , piece , <NUM_LIT> ) ; if ( store [ i ] ) emit_insn ( store [ i ] ) ; emit_move_insn ( tmp , change_address ( src , mode , src_addr ) ) ; store [ i ] = gen_move_insn ( change_address ( dst , mode , dst_addr ) , tmp ) ; dst_addr = plus_constant ( Pmode , dst_addr , piece ) ; src_addr = plus_constant ( Pmode , src_addr , piece ) ; } if ( store [ i ] ) emit_insn ( store [ i ] ) ; if ( store [ i ^ <NUM_LIT> ] ) emit_insn ( store [ i ^ <NUM_LIT> ] ) ;"
GCC,arc,125,"Predict the next statement of this code snippet:
 <s> rtx dst = operands [ <NUM_LIT> ] ; rtx src = operands [ <NUM_LIT> ] ; rtx dst_addr , src_addr ; HOST_WIDE_INT size ; int align = INTVAL ( operands [ <NUM_LIT> ] ) ; unsigned n_pieces ; int piece = align ; rtx store [ <NUM_LIT> ] ; rtx tmpx [ <NUM_LIT> ] ; int i ; if ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) ) return false ; size = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( align >= <NUM_LIT> ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> + ( size & <NUM_LIT> ) ; else if ( align == <NUM_LIT> ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> ; else n_pieces = size ; if ( n_pieces >= ( unsigned int ) ( optimize_size ? <NUM_LIT> : <NUM_LIT> ) ) return false ;"
GCC,arc,126,"Predict the next statement of this code snippet:
 <s> unsigned int gmask = cfun -> machine -> frame_info . gmask ; unsigned int frame_size_to_allocate ; int first_offset = <NUM_LIT> ; size = ARC_STACK_ALIGN ( size ) ; size = ( ! cfun -> machine -> frame_info . initialized ? arc_compute_frame_size ( size ) : cfun -> machine -> frame_info . total_size ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; frame_size_to_allocate = size ; gcc_assert ( ! ( size == <NUM_LIT> && gmask ) ) ; if ( cfun -> machine -> frame_info . pretend_size != <NUM_LIT> ) { gcc_assert ( cfun -> machine -> frame_info . pretend_size <= <NUM_LIT> ) ; frame_stack_add ( - ( HOST_WIDE_INT ) cfun -> machine -> frame_info . pretend_size ) ; frame_size_to_allocate -= cfun -> machine -> frame_info . pretend_size ; } if ( MUST_SAVE_RETURN_ADDR ) { rtx ra = gen_rtx_REG ( SImode , RETURN_ADDR_REGNUM ) ; rtx mem = gen_frame_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ; frame_move_inc ( mem , ra , stack_pointer_rtx , <NUM_LIT> ) ; frame_size_to_allocate -= UNITS_PER_WORD ; } if ( cfun -> machine -> frame_info . reg_size ) { first_offset = - cfun -> machine -> frame_info . reg_size ; arc_save_restore ( stack_pointer_rtx , gmask , <NUM_LIT> , & first_offset ) ; frame_size_to_allocate -= cfun -> machine -> frame_info . reg_size ; } if ( frame_pointer_needed ) {"
GCC,arc,127,"Predict the next statement of this code snippet:
 <s> pat = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , pat ) , ARC_UNSPEC_GOT ) ; pat = gen_rtx_CONST ( Pmode , pat ) ;"
GCC,arc,128,"Predict the next statement of this code snippet:
 <s> if ( PREV_INSN ( insn ) && PREV_INSN ( NEXT_INSN ( insn ) ) == insn && arc_hazard ( prev_real_insn ( insn ) , insn ) ) { current_output_insn = emit_insn_before ( gen_nop ( ) , NEXT_INSN ( PREV_INSN ( insn ) ) ) ; final_scan_insn ( current_output_insn , asm_out_file , optimize , <NUM_LIT> , NULL ) ;"
GCC,arc,129,"Predict the next statement of this code snippet:
 <s> extract_constrain_insn_cached ( insn ) ; if ( ! cfun -> machine -> prescan_initialized ) { memset ( & arc_ccfsm_current , <NUM_LIT> , sizeof arc_ccfsm_current ) ; cfun -> machine -> prescan_initialized = <NUM_LIT> ; } arc_ccfsm_advance ( insn , & arc_ccfsm_current ) ; cfun -> machine -> size_reason = <NUM_LIT> ;"
GCC,arc,130,"Predict the next statement of this code snippet:
 <s> static bool arc_frame_pointer_required ( void ) {"
GCC,arc,131,"Predict the next statement of this code snippet:
 <s> const char * debstr ATTRIBUTE_UNUSED ; arg_num = ROUND_ADVANCE_CUM ( arg_num , mode , type ) ; if ( mode == VOIDmode ) { ret = const0_rtx ; debstr = <STR_LIT> ; } else if ( GPR_REST_ARG_REGS ( arg_num ) > <NUM_LIT> ) { ret = gen_rtx_REG ( mode , arg_num ) ; debstr = reg_names [ arg_num ] ; } else { ret = NULL_RTX ; debstr = <STR_LIT> ; }"
GCC,arc,132,"Predict the next statement of this code snippet:
 <s> ret = const0_rtx ; debstr = <STR_LIT> ; } else if ( GPR_REST_ARG_REGS ( arg_num ) > <NUM_LIT> ) { ret = gen_rtx_REG ( mode , arg_num ) ; debstr = reg_names [ arg_num ] ; } else { ret = NULL_RTX ; debstr = <STR_LIT> ;"
GCC,arc,133,"Predict the next statement of this code snippet:
 <s> int words = ( bytes + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; int i ; if ( words ) * cum = ROUND_ADVANCE_CUM ( * cum , mode , type ) ; for ( i = <NUM_LIT> ; i < words ; i ++ ) * cum = ARC_NEXT_ARG_REG ( * cum ) ;"
GCC,arc,134,"Predict the next statement of this code snippet:
 <s> static void arc_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes = ( mode == BLKmode ? int_size_in_bytes ( type ) : ( int ) GET_MODE_SIZE ( mode ) ) ; int words = ( bytes + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; int i ;"
GCC,arc,135,"Predict the next statement of this code snippet:
 <s> if ( ARC_INTERRUPT_P ( arc_compute_function_type ( cfun ) ) ) return false ; return true ;"
GCC,arc,136,"Predict the next statement of this code snippet:
 <s> static bool arc_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { if ( ARC_INTERRUPT_P ( arc_compute_function_type ( cfun ) ) ) return false ; return true ;"
GCC,arc,137,"Predict the next statement of this code snippet:
 <s> return cfun -> machine -> unalign ;"
GCC,arc,138,"Predict the next statement of this code snippet:
 <s> } else if ( strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) && strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ;"
GCC,arc,139,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( value ) != STRING_CST ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } else if ( strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) && strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ;"
GCC,arc,140,"Predict the next statement of this code snippet:
 <s> if ( ! TARGET_ARC600 ) return <NUM_LIT> ; if ( ! pred || ! INSN_P ( pred ) || ! succ || ! INSN_P ( succ ) ) return <NUM_LIT> ; if ( recog_memoized ( succ ) == CODE_FOR_doloop_end_i && ( JUMP_P ( pred ) || CALL_P ( pred ) || GET_CODE ( PATTERN ( pred ) ) == SEQUENCE ) ) return <NUM_LIT> ; return arc600_corereg_hazard ( pred , succ ) ;"
GCC,arc,141,"Predict the next statement of this code snippet:
 <s> const char * name = LABEL_NAME ( insn ) ; PUT_CODE ( insn , NOTE ) ; NOTE_KIND ( insn ) = NOTE_INSN_DELETED_LABEL ; NOTE_DELETED_LABEL_NAME ( insn ) = name ; } merge_bb = <NUM_LIT> ; continue ; } case <NUM_LIT> : case <NUM_LIT> : if ( ! NONDEBUG_INSN_P ( insn ) ) break ; rtx_insn * prev , * pprev ; rtx * patp , pat , cond ; bool annulled ; annulled = false ; prev = PREV_INSN ( insn ) ; pprev = PREV_INSN ( prev ) ; if ( pprev && NEXT_INSN ( NEXT_INSN ( pprev ) ) == NEXT_INSN ( insn ) && JUMP_P ( prev ) && get_attr_cond ( prev ) == COND_USE ) { if ( ! INSN_ANNULLED_BRANCH_P ( prev ) ) break ; annulled = true ; } patp = & PATTERN ( insn ) ; pat = * patp ; cond = arc_get_ccfsm_cond ( statep , INSN_FROM_TARGET_P ( insn ) ) ; if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { pat = conditionalize_nonjump ( pat , cond , insn , annulled ) ; } else if ( simplejump_p ( insn ) ) { patp = & SET_SRC ( pat ) ; pat = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , * patp , pc_rtx ) ; } else if ( JUMP_P ( insn ) && ANY_RETURN_P ( PATTERN ( insn ) ) ) { pat = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , pat , pc_rtx ) ; pat = gen_rtx_SET ( VOIDmode , pc_rtx , pat ) ; } else gcc_unreachable ( ) ; validate_change ( insn , patp , pat , <NUM_LIT> ) ; if ( ! apply_change_group ( ) ) gcc_unreachable ( ) ; if ( JUMP_P ( insn ) ) { rtx_insn * next = next_nonnote_insn ( insn ) ; if ( GET_CODE ( next ) == BARRIER ) delete_insn ( next ) ; if ( statep -> state == <NUM_LIT> ) continue ; } break ;"
GCC,arc,142,"Predict the next statement of this code snippet:
 <s> break ; } default : arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } if ( TARGET_MUL64_SET && TARGET_ARC700 ) error ( <STR_LIT> ) ; if ( TARGET_NOMPY_SET && ! TARGET_ARC700 ) error ( <STR_LIT> ) ; if ( TARGET_MULMAC_32BY16_SET && ! ( TARGET_ARC600 || TARGET_ARC601 ) ) error ( <STR_LIT> ) ; if ( ! TARGET_DPFP && TARGET_DPFP_DISABLE_LRSR ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET && TARGET_DPFP_COMPACT_SET ) || ( TARGET_SPFP_FAST_SET && TARGET_SPFP_COMPACT_SET ) ) error ( <STR_LIT> ) ; if ( TARGET_SPFP_FAST_SET && ( TARGET_ARC600 || TARGET_ARC601 ) ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP || TARGET_SPFP ) && ! ( TARGET_ARC600 || TARGET_ARC601 || TARGET_ARC700 ) ) error ( <STR_LIT> ) ; if ( flag_pic && ! TARGET_ARC700 ) { warning ( DK_WARNING , <STR_LIT> , arc_cpu_string ) ; flag_pic = <NUM_LIT> ; } arc_init_reg_tables ( ) ; memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ; arc_punct_chars [ '*' ] = <NUM_LIT> ; arc_punct_chars [ '?' ] = <NUM_LIT> ; arc_punct_chars [ '!' ] = <NUM_LIT> ; arc_punct_chars [ '^' ] = <NUM_LIT> ; arc_punct_chars [ '&' ] = <NUM_LIT> ; if ( optimize > <NUM_LIT> && ! TARGET_NO_COND_EXEC ) { opt_pass * pass_arc_ifcvt_4 = make_pass_arc_ifcvt ( g ) ; struct register_pass_info arc_ifcvt4_info = { pass_arc_ifcvt_4 , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_AFTER } ; struct register_pass_info arc_ifcvt5_info = { pass_arc_ifcvt_4 -> clone ( ) , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_BEFORE } ; register_pass ( & arc_ifcvt4_info ) ; register_pass ( & arc_ifcvt5_info ) ; } if ( flag_delayed_branch ) {"
GCC,arc,143,"Predict the next statement of this code snippet:
 <s> static void arc_initialize_trampoline ( rtx tramp , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; emit_store_direct ( tramp , <NUM_LIT> , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ; emit_store_direct ( tramp , <NUM_LIT> , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ; emit_store_direct ( tramp , <NUM_LIT> , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ; emit_move_insn ( adjust_address ( tramp , SImode , <NUM_LIT> ) , fnaddr ) ; emit_move_insn ( adjust_address ( tramp , SImode , <NUM_LIT> ) , cxt ) ; emit_insn ( gen_flush_icache ( adjust_address ( tramp , SImode , <NUM_LIT> ) ) ) ;"
GCC,arc,144,"Predict the next statement of this code snippet:
 <s> if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return ( cfun -> machine -> frame_info . total_size - cfun -> machine -> frame_info . pretend_size ) ; } if ( ( from == FRAME_POINTER_REGNUM ) && ( to == STACK_POINTER_REGNUM ) ) { return ( cfun -> machine -> frame_info . total_size - ( cfun -> machine -> frame_info . pretend_size + cfun -> machine -> frame_info . extra_size + cfun -> machine -> frame_info . reg_size ) ) ; }"
GCC,arc,145,"Predict the next statement of this code snippet:
 <s> } if ( ( from == FRAME_POINTER_REGNUM ) && ( to == STACK_POINTER_REGNUM ) ) {"
GCC,arc,146,"Predict the next statement of this code snippet:
 <s> def_mbuiltin ( TARGET_MUL64_SET , <STR_LIT> , void_ftype_int_int , ARC_BUILTIN_MUL64 ) ; def_mbuiltin ( TARGET_MUL64_SET , <STR_LIT> , void_ftype_usint_usint , ARC_BUILTIN_MULU64 ) ; def_mbuiltin ( <NUM_LIT> , <STR_LIT> , void_ftype_void , ARC_BUILTIN_RTIE ) ; def_mbuiltin ( TARGET_ARC700 , <STR_LIT> , void_ftype_void , ARC_BUILTIN_SYNC ) ; def_mbuiltin ( ( TARGET_EA_SET ) , <STR_LIT> , int_ftype_int_int , ARC_BUILTIN_DIVAW ) ; def_mbuiltin ( <NUM_LIT> , <STR_LIT> , void_ftype_void , ARC_BUILTIN_BRK ) ; def_mbuiltin ( <NUM_LIT> , <STR_LIT> , void_ftype_usint , ARC_BUILTIN_FLAG ) ; def_mbuiltin ( <NUM_LIT> , <STR_LIT> , void_ftype_usint , ARC_BUILTIN_SLEEP ) ; def_mbuiltin ( <NUM_LIT> , <STR_LIT> , void_ftype_void , ARC_BUILTIN_SWI ) ; def_mbuiltin ( <NUM_LIT> , <STR_LIT> , usint_ftype_usint , ARC_BUILTIN_CORE_READ ) ; def_mbuiltin ( <NUM_LIT> , <STR_LIT> , void_ftype_usint_usint , ARC_BUILTIN_CORE_WRITE ) ;"
GCC,arc,147,"Predict the next statement of this code snippet:
 <s> machine -> fn_type = ARC_FUNCTION_UNKNOWN ; machine -> force_short_suffix = - <NUM_LIT> ;"
GCC,arc,148,"Predict the next statement of this code snippet:
 <s> static struct machine_function * arc_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> fn_type = ARC_FUNCTION_UNKNOWN ; machine -> force_short_suffix = - <NUM_LIT> ;"
GCC,arc,149,"Predict the next statement of this code snippet:
 <s> case MODE_PARTIAL_INT : case MODE_COMPLEX_INT : if ( GET_MODE_SIZE ( m ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) S_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) O_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( m ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) DF_MODE ;"
GCC,arc,150,"Predict the next statement of this code snippet:
 <s> int i ; for ( i = <NUM_LIT> ; i < NUM_MACHINE_MODES ; i ++ ) { machine_mode m = ( machine_mode ) i ; switch ( GET_MODE_CLASS ( m ) ) { case MODE_INT : case MODE_PARTIAL_INT : case MODE_COMPLEX_INT : if ( GET_MODE_SIZE ( m ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) S_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) O_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ;"
GCC,arc,151,"Predict the next statement of this code snippet:
 <s> static void arc_insn_length_parameters ( insn_length_parameters_t * ilp ) { ilp -> align_unit_log = <NUM_LIT> ; ilp -> align_base_log = <NUM_LIT> ; ilp -> max_variants = <NUM_LIT> ; ilp -> get_variants = arc_get_insn_variants ;"
GCC,arc,152,"Predict the next statement of this code snippet:
 <s> name = DECL_SECTION_NAME ( decl ) ; if ( strcmp ( name , <STR_LIT> ) != <NUM_LIT> && strcmp ( name , <STR_LIT> ) != <NUM_LIT> ) return false ; if ( ! DECL_EXTERNAL ( decl ) ) return true ; } else if ( <NUM_LIT> ) { if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && ( ! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) return false ; if ( default_binds_local_p_1 ( decl , <NUM_LIT> ) || arc_decl_anon_ns_mem_p ( decl ) ) return false ;"
GCC,arc,153,"Predict the next statement of this code snippet:
 <s> if ( prev && NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == PARALLEL && recog_memoized ( prev ) == CODE_FOR_doloop_begin_i ) return loop_align ; } if ( align_labels_log < <NUM_LIT> ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( INSN_P ( next ) && recog_memoized ( next ) >= <NUM_LIT> ) return <NUM_LIT> ; }"
GCC,arc,154,"Predict the next statement of this code snippet:
 <s> rtx_insn * prev = prev_nonnote_insn ( label ) ; if ( prev && NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == PARALLEL && recog_memoized ( prev ) == CODE_FOR_doloop_begin_i ) return loop_align ; } if ( align_labels_log < <NUM_LIT> ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( INSN_P ( next ) && recog_memoized ( next ) >= <NUM_LIT> ) return <NUM_LIT> ; } return align_labels_log ;"
GCC,arc,155,"Predict the next statement of this code snippet:
 <s> if ( RTX_OK_FOR_BASE_P ( x , strict ) ) return true ; if ( LEGITIMATE_OFFSET_ADDRESS_P ( mode , x , TARGET_INDEXED_LOADS , strict ) ) return true ; if ( LEGITIMATE_SCALED_ADDRESS_P ( mode , x , strict ) ) return true ; if ( LEGITIMATE_SMALL_DATA_ADDRESS_P ( x ) ) return true ; if ( GET_CODE ( x ) == CONST_INT && LARGE_INT ( INTVAL ( x ) ) ) return true ; if ( ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == CONST ) ) { if ( ! flag_pic || arc_legitimate_pic_addr_p ( x ) ) return true ; } if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == POST_INC ) && RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; if ( ( GET_CODE ( x ) == PRE_MODIFY || GET_CODE ( x ) == POST_MODIFY ) && GET_CODE ( XEXP ( ( x ) , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( ( x ) , <NUM_LIT> ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && LEGITIMATE_OFFSET_ADDRESS_P ( QImode , XEXP ( x , <NUM_LIT> ) , TARGET_AUTO_MODIFY_REG , strict ) ) return true ;"
GCC,arc,156,"Predict the next statement of this code snippet:
 <s> case ARC_UNSPEC_PLT : case ARC_UNSPEC_GOTOFF : case ARC_UNSPEC_GOT : case UNSPEC_PROF : return true ; default : gcc_unreachable ( ) ; } if ( arc_raw_symbolic_reference_mentioned_p ( x , false ) ) return false ; break ; case LABEL_REF : case SYMBOL_REF :"
GCC,arc,157,"Predict the next statement of this code snippet:
 <s> }"
GCC,arc,158,"Predict the next statement of this code snippet:
 <s> } return ( GET_CODE ( addr ) == UNSPEC && XVECLEN ( addr , <NUM_LIT> ) == <NUM_LIT> && XINT ( addr , <NUM_LIT> ) == ARC_UNSPEC_GOT && GET_CODE ( XVECEXP ( addr , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF ) ;"
GCC,arc,159,"Predict the next statement of this code snippet:
 <s> return ! arc_raw_symbolic_reference_mentioned_p ( x , true ) ;"
GCC,arc,160,"Predict the next statement of this code snippet:
 <s> if ( flag_pic && SYMBOLIC_CONST ( x ) ) ( x ) = arc_legitimize_pic_address ( x , <NUM_LIT> ) ; addr = x ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == SYMBOL_REF && ! SYMBOL_REF_FUNCTION_P ( XEXP ( addr , <NUM_LIT> ) ) ) || ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) ) ) ) { HOST_WIDE_INT offs , upper ; int size = GET_MODE_SIZE ( mode ) ; offs = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ; upper = ( offs + <NUM_LIT> * size ) & ~ <NUM_LIT> * size ; inner = plus_constant ( Pmode , XEXP ( addr , <NUM_LIT> ) , upper ) ;"
GCC,arc,161,"Predict the next statement of this code snippet:
 <s> if ( oldx == orig ) oldx = NULL ; if ( GET_CODE ( addr ) == LABEL_REF ) ; else if ( GET_CODE ( addr ) == SYMBOL_REF && ( CONSTANT_POOL_ADDRESS_P ( addr ) || SYMBOL_REF_LOCAL_P ( addr ) ) ) { crtl -> uses_pic_offset_table = <NUM_LIT> ; pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr ) , ARC_UNSPEC_GOTOFF ) ; pat = gen_rtx_CONST ( Pmode , pat ) ; pat = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , pat ) ; if ( oldx == NULL ) oldx = gen_reg_rtx ( Pmode ) ; if ( oldx != <NUM_LIT> ) { emit_move_insn ( oldx , pat ) ; pat = oldx ; } } else if ( GET_CODE ( addr ) == SYMBOL_REF ) { pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr ) , ARC_UNSPEC_GOT ) ; pat = gen_rtx_CONST ( Pmode , pat ) ; pat = gen_const_mem ( Pmode , pat ) ; if ( oldx == <NUM_LIT> ) oldx = gen_reg_rtx ( Pmode ) ; emit_move_insn ( oldx , pat ) ; pat = oldx ; } else { if ( GET_CODE ( addr ) == CONST ) { addr = XEXP ( addr , <NUM_LIT> ) ;"
GCC,arc,162,"Predict the next statement of this code snippet:
 <s> if ( oldx == <NUM_LIT> ) oldx = gen_reg_rtx ( Pmode ) ; emit_move_insn ( oldx , pat ) ; pat = oldx ; } else { if ( GET_CODE ( addr ) == CONST ) { addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == UNSPEC ) { } else gcc_assert ( GET_CODE ( addr ) == PLUS ) ; } if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , <NUM_LIT> ) , op1 = XEXP ( addr , <NUM_LIT> ) ; if ( ( GET_CODE ( op0 ) == LABEL_REF || ( GET_CODE ( op0 ) == SYMBOL_REF && ( CONSTANT_POOL_ADDRESS_P ( op0 ) || SYMBOL_REF_LOCAL_P ( op0 ) ) ) ) && GET_CODE ( op1 ) == CONST_INT ) { crtl -> uses_pic_offset_table = <NUM_LIT> ; pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , op0 ) , ARC_UNSPEC_GOTOFF ) ; pat = gen_rtx_PLUS ( Pmode , pat , op1 ) ; pat = gen_rtx_CONST ( Pmode , pat ) ; pat = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , pat ) ; if ( oldx != <NUM_LIT> ) { emit_move_insn ( oldx , pat ) ; pat = oldx ; } } else { base = arc_legitimize_pic_address ( XEXP ( addr , <NUM_LIT> ) , oldx ) ; pat = arc_legitimize_pic_address ( XEXP ( addr , <NUM_LIT> ) , base == oldx ? NULL_RTX : oldx ) ; if ( GET_CODE ( pat ) == CONST_INT ) pat = plus_constant ( Pmode , base , INTVAL ( pat ) ) ; else { if ( GET_CODE ( pat ) == PLUS && CONSTANT_P ( XEXP ( pat , <NUM_LIT> ) ) ) { base = gen_rtx_PLUS ( Pmode , base , XEXP ( pat , <NUM_LIT> ) ) ; pat = XEXP ( pat , <NUM_LIT> ) ; } pat = gen_rtx_PLUS ( Pmode , base , pat ) ; } }"
GCC,arc,163,"Predict the next statement of this code snippet:
 <s> rtx reg , sum , sum2 ; if ( scale > <NUM_LIT> ) scale = <NUM_LIT> ; if ( ( scale - <NUM_LIT> ) & offset ) scale = <NUM_LIT> ; shift = scale >> <NUM_LIT> ; offset_base = ( offset + ( <NUM_LIT> << shift ) ) & ( - <NUM_LIT> << shift ) ; if ( GET_MODE_SIZE ( mode ) + offset - offset_base <= ( <NUM_LIT> << shift ) ) { int regno ; reg = XEXP ( x , <NUM_LIT> ) ; regno = REGNO ( reg ) ; sum2 = sum = plus_constant ( Pmode , reg , offset_base ) ; if ( reg_equiv_constant ( regno ) ) { sum2 = plus_constant ( Pmode , reg_equiv_constant ( regno ) , offset_base ) ; if ( GET_CODE ( sum2 ) == PLUS ) sum2 = gen_rtx_CONST ( Pmode , sum2 ) ; } * p = gen_rtx_PLUS ( Pmode , sum , GEN_INT ( offset - offset_base ) ) ; push_reload ( sum2 , NULL_RTX , & XEXP ( * p , <NUM_LIT> ) , NULL , BASE_REG_CLASS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , type ) ; return true ; }"
GCC,arc,164,"Predict the next statement of this code snippet:
 <s> shift = scale >> <NUM_LIT> ; offset_base = ( offset + ( <NUM_LIT> << shift ) ) & ( - <NUM_LIT> << shift ) ; if ( GET_MODE_SIZE ( mode ) + offset - offset_base <= ( <NUM_LIT> << shift ) ) { int regno ; reg = XEXP ( x , <NUM_LIT> ) ; regno = REGNO ( reg ) ; sum2 = sum = plus_constant ( Pmode , reg , offset_base ) ; if ( reg_equiv_constant ( regno ) ) { sum2 = plus_constant ( Pmode , reg_equiv_constant ( regno ) , offset_base ) ; if ( GET_CODE ( sum2 ) == PLUS ) sum2 = gen_rtx_CONST ( Pmode , sum2 ) ; } * p = gen_rtx_PLUS ( Pmode , sum , GEN_INT ( offset - offset_base ) ) ; push_reload ( sum2 , NULL_RTX , & XEXP ( * p , <NUM_LIT> ) , NULL , BASE_REG_CLASS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , type ) ; return true ;"
GCC,arc,165,"Predict the next statement of this code snippet:
 <s> static bool arc_lra_p ( void ) { return ! TARGET_NO_LRA ;"
GCC,arc,166,"Predict the next statement of this code snippet:
 <s> static bool arc_lra_p ( void ) {"
GCC,arc,167,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( addr ) == PLUS && ( GET_CODE ( XEXP ( ( addr ) , <NUM_LIT> ) ) == MULT || ( CONST_INT_P ( XEXP ( ( addr ) , <NUM_LIT> ) ) && ! SMALL_INT ( INTVAL ( XEXP ( ( addr ) , <NUM_LIT> ) ) ) ) ) ) return true ; return false ;"
GCC,arc,168,"Predict the next statement of this code snippet:
 <s> static rtx_insn * arc_next_active_insn ( rtx_insn * insn , struct arc_ccfsm * statep ) { rtx pat ; do { if ( statep ) arc_ccfsm_post_advance ( insn , statep ) ; insn = NEXT_INSN ( insn ) ; if ( ! insn || BARRIER_P ( insn ) ) return NULL ; if ( statep ) arc_ccfsm_advance ( insn , statep ) ; } while ( NOTE_P ( insn ) || ( cfun -> machine -> arc_reorg_started && LABEL_P ( insn ) && ! label_to_alignment ( insn ) ) || ( NONJUMP_INSN_P ( insn ) && ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) ) ) ; if ( ! LABEL_P ( insn ) ) { gcc_assert ( INSN_P ( insn ) ) ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == ADDR_VEC || GET_CODE ( pat ) == ADDR_DIFF_VEC ) return NULL ; if ( GET_CODE ( pat ) == SEQUENCE ) return as_a < rtx_insn * > ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; } return insn ;"
GCC,arc,169,"Predict the next statement of this code snippet:
 <s> do { if ( statep ) arc_ccfsm_post_advance ( insn , statep ) ; insn = NEXT_INSN ( insn ) ; if ( ! insn || BARRIER_P ( insn ) ) return NULL ; if ( statep ) arc_ccfsm_advance ( insn , statep ) ; } while ( NOTE_P ( insn ) || ( cfun -> machine -> arc_reorg_started && LABEL_P ( insn ) && ! label_to_alignment ( insn ) ) || ( NONJUMP_INSN_P ( insn ) && ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) ) ) ; if ( ! LABEL_P ( insn ) ) { gcc_assert ( INSN_P ( insn ) ) ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == ADDR_VEC || GET_CODE ( pat ) == ADDR_DIFF_VEC ) return NULL ; if ( GET_CODE ( pat ) == SEQUENCE ) return as_a < rtx_insn * > ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; }"
GCC,arc,170,"Predict the next statement of this code snippet:
 <s> int intval = ( REG_P ( operands [ <NUM_LIT> ] ) ? <NUM_LIT> : CONST_INT_P ( operands [ <NUM_LIT> ] ) ? INTVAL ( operands [ <NUM_LIT> ] ) : <NUM_LIT> ) ; int neg_intval = - intval ; int short_0 = satisfies_constraint_Rcq ( operands [ <NUM_LIT> ] ) ; int short_p = ( ! cond_p && short_0 && satisfies_constraint_Rcq ( operands [ <NUM_LIT> ] ) ) ; int ret = <NUM_LIT> ;"
GCC,arc,171,"Predict the next statement of this code snippet:
 <s> if ( TARGET_LONG_CALLS_SET || ( TARGET_MEDIUM_CALLS && arc_ccfsm_cond_exec_p ( ) ) ) { if ( flag_pic ) sprintf ( buf , <STR_LIT> , fname ) ; else sprintf ( buf , <STR_LIT> , fname ) ;"
GCC,arc,172,"Predict the next statement of this code snippet:
 <s> if ( flag_pic ) sprintf ( buf , <STR_LIT> , fname ) ; else sprintf ( buf , <STR_LIT> , fname ) ; }"
GCC,arc,173,"Predict the next statement of this code snippet:
 <s> while ( mi_delta != <NUM_LIT> ) { if ( ( mi_delta & ( <NUM_LIT> << shift ) ) == <NUM_LIT> ) shift += <NUM_LIT> ; else { asm_fprintf ( file , <STR_LIT> , mi_op , reg_names [ this_regno ] , reg_names [ this_regno ] , mi_delta & ( <NUM_LIT> << shift ) ) ; mi_delta &= ~ ( <NUM_LIT> << shift ) ; shift += <NUM_LIT> ; } } if ( vcall_offset != <NUM_LIT> ) { asm_fprintf ( file , <STR_LIT> , ARC_TEMP_SCRATCH_REG , reg_names [ this_regno ] ) ; asm_fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , ARC_TEMP_SCRATCH_REG , ARC_TEMP_SCRATCH_REG , vcall_offset ) ; asm_fprintf ( file , <STR_LIT> , ARC_TEMP_SCRATCH_REG , ARC_TEMP_SCRATCH_REG ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ this_regno ] , reg_names [ this_regno ] , ARC_TEMP_SCRATCH_REG ) ; }"
GCC,arc,174,"Predict the next statement of this code snippet:
 <s> } else output_operand_lossage ( <STR_LIT> ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else gcc_unreachable ( ) ; break ; case MINUS : x = simplify_subtraction ( x ) ; if ( GET_CODE ( x ) != MINUS ) goto restart ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( x , <NUM_LIT> ) ) < <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; } else arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case ZERO_EXTEND : case SIGN_EXTEND : arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case UNSPEC : gcc_assert ( XVECLEN ( x , <NUM_LIT> ) == <NUM_LIT> ) ; if ( XINT ( x , <NUM_LIT> ) == ARC_UNSPEC_GOT ) fputs ( <STR_LIT> , file ) ; arc_output_pic_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , code ) ; switch ( XINT ( x , <NUM_LIT> ) ) { case ARC_UNSPEC_GOT : fputs ( <STR_LIT> , file ) ; break ; case ARC_UNSPEC_GOTOFF : fputs ( <STR_LIT> , file ) ; break ; case ARC_UNSPEC_PLT : fputs ( <STR_LIT> , file ) ;"
GCC,arc,175,"Predict the next statement of this code snippet:
 <s> case PC : if ( flag_pic ) putc ( '.' , file ) ; else gcc_unreachable ( ) ; break ; case SYMBOL_REF : output_addr_const ( file , x ) ; if ( code == 'P' && ! SYMBOL_REF_LOCAL_P ( x ) ) fputs ( <STR_LIT> , file ) ; break ; case LABEL_REF : ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , CODE_LABEL_NUMBER ( XEXP ( x , <NUM_LIT> ) ) ) ; assemble_name ( file , buf ) ; break ; case CODE_LABEL : ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , CODE_LABEL_NUMBER ( x ) ) ; assemble_name ( file , buf ) ; break ; case CONST_INT : fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( x ) ) ; break ; case CONST : arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode ) { if ( CONST_DOUBLE_HIGH ( x ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DOUBLE_HEX , CONST_DOUBLE_HIGH ( x ) , CONST_DOUBLE_LOW ( x ) ) ; else if ( CONST_DOUBLE_LOW ( x ) < <NUM_LIT> ) fprintf ( file , HOST_WIDE_INT_PRINT_HEX , CONST_DOUBLE_LOW ( x ) ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , CONST_DOUBLE_LOW ( x ) ) ; } else output_operand_lossage ( <STR_LIT> ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else gcc_unreachable ( ) ; break ; case MINUS : x = simplify_subtraction ( x ) ; if ( GET_CODE ( x ) != MINUS ) goto restart ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( x , <NUM_LIT> ) ) < <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; } else arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case ZERO_EXTEND : case SIGN_EXTEND : arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ;"
GCC,arc,176,"Predict the next statement of this code snippet:
 <s> if ( flag_pic ) target_flags |= MASK_NO_SDATA_SET ; if ( flag_no_common == <NUM_LIT> ) flag_no_common = ! TARGET_NO_SDATA_SET ; \ if ( TARGET_MIXED_CODE ) TARGET_Q_CLASS = <NUM_LIT> ; if ( ! TARGET_Q_CLASS ) TARGET_COMPACT_CASESI = <NUM_LIT> ; if ( TARGET_COMPACT_CASESI ) TARGET_CASE_VECTOR_PC_RELATIVE = <NUM_LIT> ; arc_init ( ) ;"
GCC,arc,177,"Predict the next statement of this code snippet:
 <s> want_long = <NUM_LIT> ; } if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( insn ) && ( get_attr_cond ( insn ) != COND_USE || ! reg_set_p ( gen_rtx_REG ( CCmode , CC_REG ) , XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ) ) { prev = as_a < rtx_insn * > ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ; gcc_assert ( ! prev_real_insn ( insn ) || ! arc_hazard ( prev_real_insn ( insn ) , prev ) ) ; cfun -> machine -> force_short_suffix = ! want_long ; rtx save_pred = current_insn_predicate ; final_scan_insn ( prev , asm_out_file , optimize , <NUM_LIT> , NULL ) ; cfun -> machine -> force_short_suffix = - <NUM_LIT> ; prev -> set_deleted ( ) ; current_output_insn = insn ; current_insn_predicate = save_pred ; }"
GCC,arc,178,"Predict the next statement of this code snippet:
 <s> enum reg_class arc_preferred_reload_class ( rtx , enum reg_class cl ) {"
GCC,arc,179,"Predict the next statement of this code snippet:
 <s> arc_print_operand_address ( file , base ) ; if ( CONSTANT_P ( base ) && CONST_INT_P ( index ) ) fputc ( '+' , file ) ; else fputc ( ',' , file ) ; gcc_assert ( OBJECT_P ( index ) ) ; arc_print_operand_address ( file , index ) ; break ; case CONST : { rtx c = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == SYMBOL_REF ) ; gcc_assert ( GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == CONST_INT ) ; output_address ( XEXP ( addr , <NUM_LIT> ) ) ; break ;"
GCC,arc,180,"Predict the next statement of this code snippet:
 <s> rtx destHigh = simplify_gen_subreg ( SImode , dest , DFmode , <NUM_LIT> ) ; rtx destLow = simplify_gen_subreg ( SImode , dest , DFmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( VOIDmode , destHigh , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , src ) , VUNSPEC_LR_HIGH ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , destLow , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , src ) , VUNSPEC_LR ) ) ) ; } } else if ( state == destDx ) { rtx srcHigh = simplify_gen_subreg ( SImode , src , DFmode , <NUM_LIT> ) ; rtx srcLow = simplify_gen_subreg ( SImode , src , DFmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , dest , srcHigh , srcLow ) , VUNSPEC_DEXCL_NORES ) ) ; } else gcc_unreachable ( ) ;"
GCC,arc,181,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( op ) == SYMBOL_REF ) { tree decl = SYMBOL_REF_DECL ( op ) ; return ! skip_local || ! decl || ! default_binds_local_p ( decl ) ; } fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( op , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( arc_raw_symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) , skip_local ) ) return true ;"
GCC,arc,182,"Predict the next statement of this code snippet:
 <s> register const char * fmt ; register int i ; if ( GET_CODE ( op ) == UNSPEC ) return false ; if ( GET_CODE ( op ) == SYMBOL_REF ) { tree decl = SYMBOL_REF_DECL ( op ) ; return ! skip_local || ! decl || ! default_binds_local_p ( decl ) ; } fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( op , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( arc_raw_symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) , skip_local ) ) return true ; } else if ( fmt [ i ] == 'e' && arc_raw_symbolic_reference_mentioned_p ( XEXP ( op , i ) , skip_local ) ) return true ;"
GCC,arc,183,"Predict the next statement of this code snippet:
 <s> else if ( to_class == LPCOUNT_REG ) return <NUM_LIT> ; else if ( to_class == WRITABLE_CORE_REGS ) return <NUM_LIT> ; } if ( TARGET_ARC700 && ( from_class == LPCOUNT_REG || from_class == ALL_CORE_REGS || from_class == WRITABLE_CORE_REGS ) ) return <NUM_LIT> ;"
GCC,arc,184,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - <NUM_LIT> || size > <NUM_LIT> ) ; }"
GCC,arc,185,"Predict the next statement of this code snippet:
 <s> struct arc_frame_info * afi = & cfun -> machine -> frame_info ;"
GCC,arc,186,"Predict the next statement of this code snippet:
 <s> int arc_return_slot_offset ( ) { struct arc_frame_info * afi = & cfun -> machine -> frame_info ; return ( afi -> save_return_addr ? afi -> total_size - afi -> pretend_size - afi -> extra_size : - <NUM_LIT> ) ;"
GCC,arc,187,"Predict the next statement of this code snippet:
 <s> if ( loc != & op ) { if ( GET_CODE ( op ) == MEM && & XEXP ( op , <NUM_LIT> ) == loc ) ; else if ( GET_CODE ( op ) == MEM && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == MULT ) * loc = force_reg ( Pmode , * loc ) ;"
GCC,arc,188,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) x = XEXP ( x , <NUM_LIT> ) ; } return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_SMALL_P ( x ) ) ;"
GCC,arc,189,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( x ) == PLUS ) {"
GCC,arc,190,"Predict the next statement of this code snippet:
 <s> * total = COSTS_N_INSNS ( INTVAL ( XEXP ( ( x ) , <NUM_LIT> ) ) ) ; if ( * total < <NUM_LIT> ) * total = <NUM_LIT> ; } return false ; case DIV : case UDIV : if ( speed ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case MULT : if ( ( TARGET_DPFP && GET_MODE ( x ) == DFmode ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( speed ) * total = arc_multcost ; else if ( TARGET_MUL64_SET || ( TARGET_ARC700 && ! TARGET_NOMPY_SET ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && _2_4_8_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) { * total += ( rtx_cost ( XEXP ( x , <NUM_LIT> ) , PLUS , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , PLUS , <NUM_LIT> , speed ) ) ; return true ; } return false ; case MINUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && _2_4_8_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) { * total += ( rtx_cost ( XEXP ( x , <NUM_LIT> ) , PLUS , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , PLUS , <NUM_LIT> , speed ) ) ; return true ; } return false ; case COMPARE : { rtx op0 = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == ZERO_EXTRACT && op1 == const0_rtx && XEXP ( op0 , <NUM_LIT> ) == const1_rtx ) { * total = ( rtx_cost ( XEXP ( op0 , <NUM_LIT> ) , SET , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( op0 , <NUM_LIT> ) , SET , <NUM_LIT> , speed ) ) ;"
GCC,arc,191,"Predict the next statement of this code snippet:
 <s> rtx sibthunk_insn = NULL_RTX ; if ( gmask ) { if ( epilogue_p == <NUM_LIT> || frame -> millicode_end_reg > <NUM_LIT> ) { int start_call = frame -> millicode_start_reg ; int end_call = frame -> millicode_end_reg ; int n_regs = end_call - start_call + <NUM_LIT> ; int i = <NUM_LIT> , r , off = <NUM_LIT> ; rtx insn ; rtx ret_addr = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; if ( * first_offset ) { gcc_assert ( epilogue_p || abs ( * first_offset ) <= <NUM_LIT> ) ; frame_add ( base_reg , * first_offset ) ; * first_offset = <NUM_LIT> ; } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( ( epilogue_p == <NUM_LIT> ) + n_regs + <NUM_LIT> ) ) ; if ( epilogue_p == <NUM_LIT> ) i += <NUM_LIT> ; else XVECEXP ( insn , <NUM_LIT> , n_regs ) = gen_rtx_CLOBBER ( VOIDmode , ret_addr ) ; for ( r = start_call ; r <= end_call ; r ++ , off += UNITS_PER_WORD , i ++ ) { rtx reg = gen_rtx_REG ( SImode , r ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base_reg , off ) ) ; if ( epilogue_p ) XVECEXP ( insn , <NUM_LIT> , i ) = gen_rtx_SET ( VOIDmode , reg , mem ) ; else XVECEXP ( insn , <NUM_LIT> , i ) = gen_rtx_SET ( VOIDmode , mem , reg ) ; gmask = gmask & ~ ( <NUM_LIT> << r ) ; } if ( epilogue_p == <NUM_LIT> ) sibthunk_insn = insn ; else frame_insn ( insn ) ; offset += off ; } for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( ( gmask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx addr , mem ; if ( * first_offset ) { gcc_assert ( ! offset ) ; addr = plus_constant ( Pmode , base_reg , * first_offset ) ; addr = gen_rtx_PRE_MODIFY ( Pmode , base_reg , addr ) ; * first_offset = <NUM_LIT> ; } else {"
GCC,arc,192,"Predict the next statement of this code snippet:
 <s> if ( * first_offset ) { gcc_assert ( epilogue_p || abs ( * first_offset ) <= <NUM_LIT> ) ; frame_add ( base_reg , * first_offset ) ; * first_offset = <NUM_LIT> ; } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( ( epilogue_p == <NUM_LIT> ) + n_regs + <NUM_LIT> ) ) ; if ( epilogue_p == <NUM_LIT> ) i += <NUM_LIT> ; else XVECEXP ( insn , <NUM_LIT> , n_regs ) = gen_rtx_CLOBBER ( VOIDmode , ret_addr ) ; for ( r = start_call ; r <= end_call ; r ++ , off += UNITS_PER_WORD , i ++ ) { rtx reg = gen_rtx_REG ( SImode , r ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base_reg , off ) ) ; if ( epilogue_p ) XVECEXP ( insn , <NUM_LIT> , i ) = gen_rtx_SET ( VOIDmode , reg , mem ) ; else XVECEXP ( insn , <NUM_LIT> , i ) = gen_rtx_SET ( VOIDmode , mem , reg ) ; gmask = gmask & ~ ( <NUM_LIT> << r ) ; } if ( epilogue_p == <NUM_LIT> ) sibthunk_insn = insn ; else frame_insn ( insn ) ; offset += off ; } for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( ( gmask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx addr , mem ; if ( * first_offset ) { gcc_assert ( ! offset ) ; addr = plus_constant ( Pmode , base_reg , * first_offset ) ; addr = gen_rtx_PRE_MODIFY ( Pmode , base_reg , addr ) ; * first_offset = <NUM_LIT> ; } else {"
GCC,arc,193,"Predict the next statement of this code snippet:
 <s> machine_mode mode = GET_MODE ( x ) ; rtx x1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && y == const0_rtx && ( op == EQ || op == NE || ( ( op == LT || op == GE ) && GET_MODE_SIZE ( GET_MODE ( x ) ) <= <NUM_LIT> ) ) ) return CC_ZNmode ; if ( mode == SImode && GET_CODE ( y ) == NEG && ( op == EQ || op == NE ) ) return CC_ZNmode ; if ( mode == SImode && ( op == EQ || op == NE ) && CONST_INT_P ( y ) && ( ( INTVAL ( y ) - <NUM_LIT> ) & INTVAL ( y ) ) == <NUM_LIT> && INTVAL ( y ) ) return CC_Zmode ; if ( mode == SImode && ( op == EQ || op == NE ) && CONST_INT_P ( y ) && GET_CODE ( x ) == AND && CONST_INT_P ( ( x1 = XEXP ( x , <NUM_LIT> ) ) ) && ( ( INTVAL ( x1 ) + <NUM_LIT> ) & INTVAL ( x1 ) ) == <NUM_LIT> && ( ~ INTVAL ( x1 ) | INTVAL ( y ) ) < <NUM_LIT> && ( ~ INTVAL ( x1 ) | INTVAL ( y ) ) > - <NUM_LIT> ) return CC_Zmode ; if ( GET_MODE ( x ) == SImode && ( op == LTU || op == GEU ) && GET_CODE ( x ) == PLUS && ( rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , y ) || rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , y ) ) ) return CC_Cmode ; if ( TARGET_ARGONAUT_SET && ( ( mode == SFmode && TARGET_SPFP ) || ( mode == DFmode && TARGET_DPFP ) ) ) switch ( op ) {"
GCC,arc,194,"Predict the next statement of this code snippet:
 <s> next_cum = * get_cumulative_args ( args_so_far ) ; arc_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , <NUM_LIT> ) ; first_anon_arg = next_cum ; if ( first_anon_arg < MAX_ARC_PARM_REGS ) { int first_reg_offset = first_anon_arg ;"
GCC,arc,195,"Predict the next statement of this code snippet:
 <s> if ( ! no_rtl ) { rtx regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( <NUM_LIT> ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , MAX_ARC_PARM_REGS - first_reg_offset ) ; } * pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ; }"
GCC,arc,196,"Predict the next statement of this code snippet:
 <s> void arc_set_default_type_attributes ( tree type ATTRIBUTE_UNUSED ) { gcc_unreachable ( ) ;"
GCC,arc,197,"Predict the next statement of this code snippet:
 <s> case POST_MODIFY : o = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; post_modify : code = POST_MODIFY ; swap = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } r = XEXP ( addr , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , gen_rtx_fmt_ee ( code , Pmode , r , gen_rtx_PLUS ( Pmode , r , o ) ) , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , plus_constant ( Pmode , r , <NUM_LIT> ) , <NUM_LIT> ) ; } else { xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ; xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ; } } if ( reg_overlap_mentioned_p ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ) { swap = <NUM_LIT> ; gcc_assert ( ! reg_overlap_mentioned_p ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ) ; } operands [ <NUM_LIT> + swap ] = xop [ <NUM_LIT> ] ; operands [ <NUM_LIT> + swap ] = xop [ <NUM_LIT> ] ; operands [ <NUM_LIT> - swap ] = xop [ <NUM_LIT> ] ; operands [ <NUM_LIT> - swap ] = xop [ <NUM_LIT> ] ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ;"
GCC,arc,198,"Predict the next statement of this code snippet:
 <s> enum rtx_code code ; gcc_assert ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , addr ) ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : o = GEN_INT ( - <NUM_LIT> ) ; goto pre_modify ; case PRE_INC : o = GEN_INT ( <NUM_LIT> ) ; goto pre_modify ; case PRE_MODIFY : o = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; pre_modify : code = PRE_MODIFY ; break ; case POST_DEC : o = GEN_INT ( - <NUM_LIT> ) ; goto post_modify ; case POST_INC : o = GEN_INT ( <NUM_LIT> ) ; goto post_modify ; case POST_MODIFY : o = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; post_modify : code = POST_MODIFY ; swap = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } r = XEXP ( addr , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , gen_rtx_fmt_ee ( code , Pmode , r , gen_rtx_PLUS ( Pmode , r , o ) ) , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , plus_constant ( Pmode , r , <NUM_LIT> ) , <NUM_LIT> ) ; } else { xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ; xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ; } } if ( reg_overlap_mentioned_p ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ) { swap = <NUM_LIT> ; gcc_assert ( ! reg_overlap_mentioned_p ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ) ; } operands [ <NUM_LIT> + swap ] = xop [ <NUM_LIT> ] ; operands [ <NUM_LIT> + swap ] = xop [ <NUM_LIT> ] ; operands [ <NUM_LIT> - swap ] = xop [ <NUM_LIT> ] ; operands [ <NUM_LIT> - swap ] = xop [ <NUM_LIT> ] ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; val = get_insns ( ) ; end_sequence ( ) ; return val ;"
GCC,arc,199,"Predict the next statement of this code snippet:
 <s> return plus_constant ( Pmode , addr , <NUM_LIT> ) ;"
GCC,arc,200,"Predict the next statement of this code snippet:
 <s> static rtx arc_trampoline_adjust_address ( rtx addr ) {"
GCC,arc,201,"Predict the next statement of this code snippet:
 <s> default_promote_function_mode_always_promote arc_use_by_pieces_infrastructure_p static int arc_sched_adjust_priority ( rtx_insn * insn , int priority ) { rtx set = single_set ( insn ) ; if ( set && GET_MODE ( SET_SRC ( set ) ) == DFmode && GET_CODE ( SET_SRC ( set ) ) == REG ) { return priority + <NUM_LIT> ; } return priority ;"
GCC,arc,202,"Predict the next statement of this code snippet:
 <s> enum attr_iscompact iscompact ; struct machine_function * machine ; if ( check_attr > <NUM_LIT> ) { iscompact = get_attr_iscompact ( insn ) ;"
GCC,arc,203,"Predict the next statement of this code snippet:
 <s> int branch_dest ( rtx branch ) { rtx pat = PATTERN ( branch ) ;"
GCC,arc,204,"Predict the next statement of this code snippet:
 <s> int dest_uid ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , XEXP ( dest , <NUM_LIT> ) == pc_rtx ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,205,"Predict the next statement of this code snippet:
 <s> bool check_if_valid_regno_const ( rtx * operands , int opno ) { switch ( GET_CODE ( operands [ opno ] ) ) {"
GCC,arc,206,"Predict the next statement of this code snippet:
 <s> switch ( GET_CODE ( operands [ opno ] ) ) { case SYMBOL_REF : case CONST : case CONST_INT :"
GCC,arc,207,"Predict the next statement of this code snippet:
 <s> case CONST : case CONST_INT : if ( UNSIGNED_INT6 ( INTVAL ( operands [ opno ] ) ) ) return true ; default :"
GCC,arc,208,"Predict the next statement of this code snippet:
 <s> rtx addr ; int size ; if ( GET_CODE ( op ) != MEM ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ;"
GCC,arc,209,"Predict the next statement of this code snippet:
 <s> size = GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD ) return false ; addr = XEXP ( op , <NUM_LIT> ) ; return LEGITIMATE_SMALL_DATA_ADDRESS_P ( addr ) ;"
GCC,arc,210,"Predict the next statement of this code snippet:
 <s> if ( COMMUTATIVE_P ( src ) ) { rtx src0 = XEXP ( src , <NUM_LIT> ) ; rtx src1 = XEXP ( src , <NUM_LIT> ) ; rtx dst = SET_DEST ( pat ) ; if ( rtx_equal_p ( src1 , dst ) && ! rtx_equal_p ( src0 , dst ) && REG_P ( src0 ) ) pat = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( GET_CODE ( src ) , GET_MODE ( src ) , src1 , src0 ) ) ; } } if ( RTX_FRAME_RELATED_P ( insn ) ) {"
GCC,arc,211,"Predict the next statement of this code snippet:
 <s> void emit_pic_move ( rtx * operands , machine_mode ) { rtx temp = reload_in_progress ? operands [ <NUM_LIT> ] : gen_reg_rtx ( Pmode ) ;"
GCC,arc,212,"Predict the next statement of this code snippet:
 <s> rtx temp = reload_in_progress ? operands [ <NUM_LIT> ] : gen_reg_rtx ( Pmode ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = force_reg ( Pmode , operands [ <NUM_LIT> ] ) ;"
GCC,arc,213,"Predict the next statement of this code snippet:
 <s> static void emit_store_direct ( rtx block , int offset , int value ) {"
GCC,arc,214,"Predict the next statement of this code snippet:
 <s> } if ( ! REG_P ( base ) || ( REGNO ( base ) != STACK_POINTER_REGNUM && REGNO_PTR_FRAME_P ( REGNO ( addr ) ) ) || ! CONST_INT_P ( offs ) || ! SMALL_INT ( INTVAL ( offs ) ) || ! SMALL_INT ( INTVAL ( offs ) + size ) ) { if ( reuse ) emit_insn ( gen_add2_insn ( addr , offs ) ) ; else addr = copy_to_mode_reg ( Pmode , addr ) ;"
GCC,arc,215,"Predict the next statement of this code snippet:
 <s> FOR_EACH_SUBRTX ( iter , array , op , ALL ) {"
GCC,arc,216,"Predict the next statement of this code snippet:
 <s> if ( ! register_operand ( x , SImode ) ) { if ( register_operand ( y , SImode ) ) { tmp = x ; x = y ; y = tmp ; code = swap_condition ( code ) ; } else x = copy_to_mode_reg ( SImode , x ) ; } if ( GET_CODE ( y ) == SYMBOL_REF && flag_pic ) y = copy_to_mode_reg ( SImode , y ) ; } else { x = force_reg ( cmode , x ) ; y = force_reg ( cmode , y ) ; } mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( mode , CC_REG ) ; if ( TARGET_ARGONAUT_SET && ( ( cmode == SFmode && TARGET_SPFP ) || ( cmode == DFmode && TARGET_DPFP ) ) ) { switch ( code ) { case NE : case EQ : case LT : case UNGE : case LE : case UNGT : case UNEQ : case LTGT : case ORDERED : case UNORDERED : break ; case GT : case UNLE : case GE : case UNLT : code = swap_condition ( code ) ; tmp = x ; x = y ; y = tmp ; break ; default : gcc_unreachable ( ) ; } if ( cmode == SFmode ) { emit_insn ( gen_cmpsfpx_raw ( x , y ) ) ; } else { emit_insn ( gen_cmpdfpx_raw ( x , y ) ) ; } if ( mode != CC_FPXmode ) emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , gen_rtx_REG ( CC_FPXmode , <NUM_LIT> ) , const0_rtx ) ) ) ; } else if ( GET_MODE_CLASS ( cmode ) == MODE_FLOAT && TARGET_OPTFPE ) { rtx op0 = gen_rtx_REG ( cmode , <NUM_LIT> ) ; rtx op1 = gen_rtx_REG ( cmode , GET_MODE_SIZE ( cmode ) / UNITS_PER_WORD ) ; switch ( code ) { case NE : case EQ : case GT : case UNLE : case GE : case UNLT : case UNEQ : case LTGT : case ORDERED : case UNORDERED : break ; case LT : case UNGE : case LE : case UNGT : code = swap_condition ( code ) ; tmp = x ; x = y ;"
GCC,arc,217,"Predict the next statement of this code snippet:
 <s> rtx gen_mlo ( void ) { return gen_rtx_REG ( SImode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,218,"Predict the next statement of this code snippet:
 <s> default : gcc_unreachable ( ) ; } case CC_FP_GTmode : if ( TARGET_ARGONAUT_SET && TARGET_SPFP ) switch ( GET_CODE ( comparison ) ) { case GT : return ARC_CC_N ; case UNLE : return ARC_CC_P ; default : gcc_unreachable ( ) ; } else switch ( GET_CODE ( comparison ) ) { case GT : return ARC_CC_HI ; case UNLE : return ARC_CC_LS ; default : gcc_unreachable ( ) ; } case CC_FP_GEmode : switch ( GET_CODE ( comparison ) ) { case GE : return ARC_CC_HS ; case UNLT : return ARC_CC_LO ; default : gcc_unreachable ( ) ; } case CC_FP_UNEQmode : switch ( GET_CODE ( comparison ) ) { case UNEQ : return ARC_CC_EQ ; case LTGT : return ARC_CC_NE ; default : gcc_unreachable ( ) ; } case CC_FP_ORDmode : switch ( GET_CODE ( comparison ) ) { case UNORDERED : return ARC_CC_C ; case ORDERED : return ARC_CC_NC ; default : gcc_unreachable ( ) ; } case CC_FPXmode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; case UNORDERED : return ARC_CC_C ; case ORDERED : return ARC_CC_NC ; case LTGT : return ARC_CC_HI ; case UNEQ : return ARC_CC_LS ; default : gcc_unreachable ( ) ; } default : gcc_unreachable ( ) ;"
GCC,arc,219,"Predict the next statement of this code snippet:
 <s> if ( arc_verify_short ( insn , cfun -> machine -> unalign , <NUM_LIT> ) ) { fprintf ( file , <STR_LIT> ) ; cfun -> machine -> unalign ^= <NUM_LIT> ;"
GCC,arc,220,"Predict the next statement of this code snippet:
 <s> pass_arc_ifcvt ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_arc_ifcvt , ctxt ) {"
GCC,arc,221,"Predict the next statement of this code snippet:
 <s> pass_arc_ifcvt ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_arc_ifcvt , ctxt ) {"
GCC,arc,222,"Predict the next statement of this code snippet:
 <s> else if ( mode == SImode && flag_pic && SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) { emit_pic_move ( operands , SImode ) ; } else if ( GET_CODE ( operands [ <NUM_LIT> ] ) != MEM && ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ <NUM_LIT> ] , Pmode ) ) { operands [ <NUM_LIT> ] = arc_rewrite_small_data ( operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( mode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , operands [ <NUM_LIT> ] ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; } } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ <NUM_LIT> ] , mode , pat ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } } } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ;"
GCC,arc,223,"Predict the next statement of this code snippet:
 <s> if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ <NUM_LIT> ] , mode , pat ) ;"
GCC,arc,224,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( x ) == PLUS && rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , pic_offset_table_rtx ) ) iter . skip_subrtxes ( ) ; else if ( arc_rewrite_small_data_p ( x ) ) return true ;"
GCC,arc,225,"Predict the next statement of this code snippet:
 <s> FOR_EACH_SUBRTX ( iter , array , op , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == PLUS && rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , pic_offset_table_rtx ) ) iter . skip_subrtxes ( ) ; else if ( arc_rewrite_small_data_p ( x ) ) return true ; } return false ;"
GCC,arc,226,"Predict the next statement of this code snippet:
 <s> const_rtx u0 = ( const_rtx ) x ; const_rtx u1 = ( const_rtx ) y ; const_rtx s01 = XVECEXP ( u0 , <NUM_LIT> , <NUM_LIT> ) ; const_rtx s11 = XVECEXP ( u1 , <NUM_LIT> , <NUM_LIT> ) ; return ( ! strcmp ( XSTR ( XVECEXP ( u0 , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , XSTR ( XVECEXP ( u1 , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) && rtx_equal_p ( s01 , s11 ) ) ;"
GCC,arc,227,"Predict the next statement of this code snippet:
 <s> return ( ! strcmp ( XSTR ( XVECEXP ( u0 , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , XSTR ( XVECEXP ( u1 , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) && rtx_equal_p ( s01 , s11 ) ) ;"
GCC,arc,228,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( x ) == COND_EXEC ) x = COND_EXEC_CODE ( x ) ; if ( GET_CODE ( x ) == SET || GET_CODE ( x ) == CLOBBER ) { rtx dest = SET_DEST ( x ) ; while ( ( GET_CODE ( dest ) == SUBREG && ( ! REG_P ( SUBREG_REG ( dest ) ) || REGNO ( SUBREG_REG ( dest ) ) >= FIRST_PSEUDO_REGISTER ) ) || GET_CODE ( dest ) == ZERO_EXTRACT || GET_CODE ( dest ) == STRICT_LOW_PART ) dest = XEXP ( dest , <NUM_LIT> ) ; if ( GET_CODE ( dest ) == PARALLEL ) { for ( i = XVECLEN ( dest , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( XEXP ( XVECEXP ( dest , <NUM_LIT> , i ) , <NUM_LIT> ) != <NUM_LIT> ) ( * fun ) ( XEXP ( XVECEXP ( dest , <NUM_LIT> , i ) , <NUM_LIT> ) , x , data ) ; } else ( * fun ) ( dest , x , data ) ; } else if ( GET_CODE ( x ) == PARALLEL ) for ( i = XVECLEN ( x , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) walk_stores ( XVECEXP ( x , <NUM_LIT> , i ) , fun , data ) ;"
GCC,arc,229,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( x ) == SET || GET_CODE ( x ) == CLOBBER ) { rtx dest = SET_DEST ( x ) ; while ( ( GET_CODE ( dest ) == SUBREG && ( ! REG_P ( SUBREG_REG ( dest ) ) || REGNO ( SUBREG_REG ( dest ) ) >= FIRST_PSEUDO_REGISTER ) ) || GET_CODE ( dest ) == ZERO_EXTRACT || GET_CODE ( dest ) == STRICT_LOW_PART ) dest = XEXP ( dest , <NUM_LIT> ) ; if ( GET_CODE ( dest ) == PARALLEL ) {"
GCC,arc,230,"Predict the next statement of this code snippet:
 <s> output_asm_insn ( <STR_LIT> <STR_LIT> , & XVECEXP ( src , <NUM_LIT> , <NUM_LIT> ) ) ; } slot = ( rtx * ) htab_find_slot ( htab , src , INSERT ) ; if ( * slot == HTAB_EMPTY_ENTRY ) { static int count_nr ; char buf [ <NUM_LIT> ] ; rtx count ; * slot = src ; sprintf ( buf , <STR_LIT> , count_nr ++ ) ; count = gen_rtx_SYMBOL_REF ( Pmode , xstrdup ( buf ) ) ;"
GCC,arc,231,"Predict the next statement of this code snippet:
 <s> slot = ( rtx * ) htab_find_slot ( htab , src , INSERT ) ; if ( * slot == HTAB_EMPTY_ENTRY ) { static int count_nr ; char buf [ <NUM_LIT> ] ; rtx count ; * slot = src ; sprintf ( buf , <STR_LIT> , count_nr ++ ) ; count = gen_rtx_SYMBOL_REF ( Pmode , xstrdup ( buf ) ) ; XVECEXP ( src , <NUM_LIT> , <NUM_LIT> ) = count ; output_asm_insn ( <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , & XVECEXP ( src , <NUM_LIT> , <NUM_LIT> ) ) ; * srcp = count ; } else * srcp = XVECEXP ( * slot , <NUM_LIT> , <NUM_LIT> ) ;"
GCC,arc,232,"Predict the next statement of this code snippet:
 <s> for ( a = DECL_ATTRIBUTES ( decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) , args = TREE_VALUE ( a ) ; if ( name == get_identifier ( <STR_LIT> ) && list_length ( args ) == <NUM_LIT> && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST ) {"
GCC,arc,233,"Predict the next statement of this code snippet:
 <s> enum arc_function_type arc_compute_function_type ( struct function * fun ) { tree decl = fun -> decl ; tree a ; enum arc_function_type fn_type = fun -> machine -> fn_type ; if ( fn_type != ARC_FUNCTION_UNKNOWN ) return fn_type ; fn_type = ARC_FUNCTION_NORMAL ; for ( a = DECL_ATTRIBUTES ( decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) , args = TREE_VALUE ( a ) ; if ( name == get_identifier ( <STR_LIT> ) && list_length ( args ) == <NUM_LIT> && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST ) { tree value = TREE_VALUE ( args ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) || ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type = ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type = ARC_FUNCTION_ILINK2 ; else gcc_unreachable ( ) ; break ; } } return fun -> machine -> fn_type = fn_type ;"
GCC,arc,234,"Predict the next statement of this code snippet:
 <s> XVECEXP ( p , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_REG ( SImode , regno ) ;"
GCC,arc,235,"Predict the next statement of this code snippet:
 <s> rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op1 ) ) { if ( optimize ) warning ( <NUM_LIT> , <STR_LIT> ) ; } else { HOST_WIDE_INT alignTest = INTVAL ( op1 ) ; if ( alignTest <= <NUM_LIT> || alignTest != ( alignTest & - alignTest ) ) { error ( <STR_LIT> ) ; return NULL_RTX ;"
GCC,arc,236,"Predict the next statement of this code snippet:
 <s> } if ( millicode_p ) { int sibthunk_p = ( ! sibcall_p && fn_type == ARC_FUNCTION_NORMAL && ! cfun -> machine -> frame_info . pretend_size ) ; gcc_assert ( ! ( cfun -> machine -> frame_info . gmask & ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) ) ) ; arc_save_restore ( stack_pointer_rtx , cfun -> machine -> frame_info . gmask , <NUM_LIT> + sibthunk_p , & first_offset ) ; if ( sibthunk_p ) return ; } if ( ( ! SMALL_INT ( first_offset ) && cfun -> machine -> frame_info . gmask && ( ( TARGET_ARC700 && ! optimize_size ) ? first_offset <= <NUM_LIT> : satisfies_constraint_C2a ( GEN_INT ( first_offset ) ) ) ) || ( MUST_SAVE_RETURN_ADDR && ! SMALL_INT ( ( cfun -> machine -> frame_info . reg_size + first_offset ) >> <NUM_LIT> ) && cfun -> machine -> frame_info . gmask ) ) { frame_stack_add ( first_offset ) ; first_offset = <NUM_LIT> ; } if ( MUST_SAVE_RETURN_ADDR ) { rtx ra = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; int ra_offs = cfun -> machine -> frame_info . reg_size + first_offset ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , ra_offs ) ; HOST_WIDE_INT cfa_adjust = <NUM_LIT> ; if ( ! SMALL_INT ( ra_offs >> <NUM_LIT> ) && ! cfun -> machine -> frame_info . gmask && ( ( TARGET_ARC700 && ! optimize_size ) ? ra_offs <= <NUM_LIT> : satisfies_constraint_C2a ( GEN_INT ( ra_offs ) ) ) ) { size_to_deallocate -= ra_offs - first_offset ; first_offset = <NUM_LIT> ; frame_stack_add ( ra_offs ) ; ra_offs = <NUM_LIT> ; addr = stack_pointer_rtx ; } if ( ra_offs && ! cfun -> machine -> frame_info . gmask && ( SMALL_INT ( ra_offs ) || ! SMALL_INT ( ra_offs >> <NUM_LIT> ) ) ) { addr = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , addr ) ; cfa_adjust = ra_offs ; first_offset = <NUM_LIT> ; size_to_deallocate -= cfun -> machine -> frame_info . reg_size ; } else if ( ! ra_offs && size_to_deallocate == UNITS_PER_WORD ) {"
GCC,arc,237,"Predict the next statement of this code snippet:
 <s> rtx ra = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; int ra_offs = cfun -> machine -> frame_info . reg_size + first_offset ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , ra_offs ) ; HOST_WIDE_INT cfa_adjust = <NUM_LIT> ; if ( ! SMALL_INT ( ra_offs >> <NUM_LIT> ) && ! cfun -> machine -> frame_info . gmask && ( ( TARGET_ARC700 && ! optimize_size ) ? ra_offs <= <NUM_LIT> : satisfies_constraint_C2a ( GEN_INT ( ra_offs ) ) ) ) { size_to_deallocate -= ra_offs - first_offset ; first_offset = <NUM_LIT> ; frame_stack_add ( ra_offs ) ; ra_offs = <NUM_LIT> ; addr = stack_pointer_rtx ; } if ( ra_offs && ! cfun -> machine -> frame_info . gmask && ( SMALL_INT ( ra_offs ) || ! SMALL_INT ( ra_offs >> <NUM_LIT> ) ) ) { addr = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , addr ) ; cfa_adjust = ra_offs ; first_offset = <NUM_LIT> ; size_to_deallocate -= cfun -> machine -> frame_info . reg_size ; } else if ( ! ra_offs && size_to_deallocate == UNITS_PER_WORD ) { addr = gen_rtx_POST_INC ( Pmode , addr ) ; cfa_adjust = GET_MODE_SIZE ( Pmode ) ; size_to_deallocate = <NUM_LIT> ; } insn = frame_move_inc ( ra , gen_frame_mem ( Pmode , addr ) , stack_pointer_rtx , addr ) ; if ( cfa_adjust ) { enum reg_note note = REG_CFA_ADJUST_CFA ; add_reg_note ( insn , note , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( SImode , stack_pointer_rtx , cfa_adjust ) ) ) ; } add_reg_note ( insn , REG_CFA_RESTORE , ra ) ; } if ( ! millicode_p ) { if ( cfun -> machine -> frame_info . reg_size ) arc_save_restore ( stack_pointer_rtx , cfun -> machine -> frame_info . gmask & ~ ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) , <NUM_LIT> , & first_offset ) ; } size_to_deallocate += first_offset ; restored = size - size_to_deallocate ; if ( size > restored ) frame_stack_add ( size - restored ) ;"
GCC,arc,238,"Predict the next statement of this code snippet:
 <s> while ( piece > size ) piece >>= <NUM_LIT> ; mode = smallest_mode_for_size ( piece * BITS_PER_UNIT , MODE_INT ) ; if ( <NUM_LIT> && tmpx [ i ] && GET_MODE ( tmpx [ i ] ) == mode ) tmp = tmpx [ i ] ; else tmpx [ i ] = tmp = gen_reg_rtx ( mode ) ; dst_addr = force_offsettable ( dst_addr , piece , <NUM_LIT> ) ; src_addr = force_offsettable ( src_addr , piece , <NUM_LIT> ) ; if ( store [ i ] ) emit_insn ( store [ i ] ) ; emit_move_insn ( tmp , change_address ( src , mode , src_addr ) ) ; store [ i ] = gen_move_insn ( change_address ( dst , mode , dst_addr ) , tmp ) ; dst_addr = plus_constant ( Pmode , dst_addr , piece ) ;"
GCC,arc,239,"Predict the next statement of this code snippet:
 <s> if ( crtl -> uses_pic_offset_table == <NUM_LIT> ) return ; gcc_assert ( flag_pic != <NUM_LIT> ) ; pat = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , pat ) , ARC_UNSPEC_GOT ) ; pat = gen_rtx_CONST ( Pmode , pat ) ;"
GCC,arc,240,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( value ) != STRING_CST ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; }"
GCC,arc,241,"Predict the next statement of this code snippet:
 <s> * no_add_attrs = true ; } else if ( strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) && strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) && ! TARGET_V2 ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } else if ( TARGET_V2 && strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ;"
GCC,arc,242,"Predict the next statement of this code snippet:
 <s> int arc_hazard ( rtx_insn * pred , rtx_insn * succ ) { if ( ! pred || ! INSN_P ( pred ) || ! succ || ! INSN_P ( succ ) ) return <NUM_LIT> ; if ( arc_loop_hazard ( pred , succ ) ) return <NUM_LIT> ; if ( TARGET_ARC600 ) return arc600_corereg_hazard ( pred , succ ) ; return <NUM_LIT> ;"
GCC,arc,243,"Predict the next statement of this code snippet:
 <s> merge_blocks ( merge_bb , succ_bb ) ; } else { PUT_CODE ( insn , NOTE ) ; NOTE_KIND ( insn ) = NOTE_INSN_DELETED ; } continue ; } case <NUM_LIT> : if ( LABEL_P ( insn ) && statep -> target_label == CODE_LABEL_NUMBER ( insn ) ) { arc_ccfsm_post_advance ( insn , statep ) ; basic_block succ_bb = BLOCK_FOR_INSN ( insn ) ; if ( merge_bb && succ_bb ) merge_blocks ( merge_bb , succ_bb ) ; else if ( -- LABEL_NUSES ( insn ) == <NUM_LIT> ) { const char * name = LABEL_NAME ( insn ) ; PUT_CODE ( insn , NOTE ) ; NOTE_KIND ( insn ) = NOTE_INSN_DELETED_LABEL ; NOTE_DELETED_LABEL_NAME ( insn ) = name ; } merge_bb = <NUM_LIT> ; continue ; } case <NUM_LIT> : case <NUM_LIT> : if ( ! NONDEBUG_INSN_P ( insn ) ) break ; rtx_insn * prev , * pprev ; rtx * patp , pat , cond ; bool annulled ; annulled = false ; prev = PREV_INSN ( insn ) ; pprev = PREV_INSN ( prev ) ; if ( pprev && NEXT_INSN ( NEXT_INSN ( pprev ) ) == NEXT_INSN ( insn ) && JUMP_P ( prev ) && get_attr_cond ( prev ) == COND_USE ) { if ( ! INSN_ANNULLED_BRANCH_P ( prev ) ) break ; annulled = true ; } patp = & PATTERN ( insn ) ; pat = * patp ; cond = arc_get_ccfsm_cond ( statep , INSN_FROM_TARGET_P ( insn ) ) ; if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { pat = conditionalize_nonjump ( pat , cond , insn , annulled ) ; } else if ( simplejump_p ( insn ) ) { patp = & SET_SRC ( pat ) ; pat = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , * patp , pc_rtx ) ; } else if ( JUMP_P ( insn ) && ANY_RETURN_P ( PATTERN ( insn ) ) ) { pat = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , pat , pc_rtx ) ; pat = gen_rtx_SET ( pc_rtx , pat ) ; } else gcc_unreachable ( ) ; validate_change ( insn , patp , pat , <NUM_LIT> ) ; if ( ! apply_change_group ( ) ) gcc_unreachable ( ) ; if ( JUMP_P ( insn ) ) { rtx_insn * next = next_nonnote_insn ( insn ) ; if ( GET_CODE ( next ) == BARRIER ) delete_insn ( next ) ; if ( statep -> state == <NUM_LIT> ) continue ; } break ; default :"
GCC,arc,244,"Predict the next statement of this code snippet:
 <s> NOTE_KIND ( insn ) = NOTE_INSN_DELETED_LABEL ; NOTE_DELETED_LABEL_NAME ( insn ) = name ; } merge_bb = <NUM_LIT> ; continue ; } case <NUM_LIT> : case <NUM_LIT> : if ( ! NONDEBUG_INSN_P ( insn ) ) break ; rtx_insn * prev , * pprev ; rtx * patp , pat , cond ; bool annulled ; annulled = false ; prev = PREV_INSN ( insn ) ; pprev = PREV_INSN ( prev ) ; if ( pprev && NEXT_INSN ( NEXT_INSN ( pprev ) ) == NEXT_INSN ( insn ) && JUMP_P ( prev ) && get_attr_cond ( prev ) == COND_USE ) { if ( ! INSN_ANNULLED_BRANCH_P ( prev ) ) break ; annulled = true ; } patp = & PATTERN ( insn ) ; pat = * patp ; cond = arc_get_ccfsm_cond ( statep , INSN_FROM_TARGET_P ( insn ) ) ; if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { pat = conditionalize_nonjump ( pat , cond , insn , annulled ) ; } else if ( simplejump_p ( insn ) ) { patp = & SET_SRC ( pat ) ; pat = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , * patp , pc_rtx ) ; } else if ( JUMP_P ( insn ) && ANY_RETURN_P ( PATTERN ( insn ) ) ) { pat = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , pat , pc_rtx ) ; pat = gen_rtx_SET ( pc_rtx , pat ) ; } else gcc_unreachable ( ) ; validate_change ( insn , patp , pat , <NUM_LIT> ) ; if ( ! apply_change_group ( ) ) gcc_unreachable ( ) ; if ( JUMP_P ( insn ) ) { rtx_insn * next = next_nonnote_insn ( insn ) ; if ( GET_CODE ( next ) == BARRIER ) delete_insn ( next ) ; if ( statep -> state == <NUM_LIT> ) continue ; } break ; default : gcc_unreachable ( ) ; } arc_ccfsm_post_advance ( insn , statep ) ; } return <NUM_LIT> ;"
GCC,arc,245,"Predict the next statement of this code snippet:
 <s> case PROCESSOR_ARC601 : arc_cpu_string = <STR_LIT> ; tune_dflt = TUNE_ARC600 ; break ; case PROCESSOR_ARC700 : arc_cpu_string = <STR_LIT> ; tune_dflt = TUNE_ARC700_4_2_STD ; break ; case PROCESSOR_ARCEM : arc_cpu_string = <STR_LIT> ; break ; case PROCESSOR_ARCHS : arc_cpu_string = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( arc_tune == TUNE_NONE ) arc_tune = tune_dflt ; if ( arc_multcost < <NUM_LIT> ) switch ( arc_tune ) { case TUNE_ARC700_4_2_STD : arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_NOMPY_SET ) arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case TUNE_ARC700_4_2_XMAC : arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_NOMPY_SET ) arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case TUNE_ARC600 : if ( TARGET_MUL64_SET ) { arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } default : arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } if ( TARGET_MUL64_SET && ( ! TARGET_ARC600_FAMILY ) ) error ( <STR_LIT> ) ; if ( TARGET_NOMPY_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( TARGET_MULMAC_32BY16_SET && ( ! TARGET_ARC600_FAMILY ) ) error ( <STR_LIT> ) ; if ( ! TARGET_DPFP && TARGET_DPFP_DISABLE_LRSR ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET && TARGET_DPFP_COMPACT_SET ) || ( TARGET_SPFP_FAST_SET && TARGET_SPFP_COMPACT_SET ) ) error ( <STR_LIT> ) ; if ( TARGET_SPFP_FAST_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP || TARGET_SPFP ) && ( ! TARGET_ARCOMPACT_FAMILY && ! TARGET_EM ) ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP || TARGET_SPFP ) && TARGET_HARD_FLOAT && TARGET_HS ) error ( <STR_LIT> ) ; if ( TARGET_HS && ( ( arc_mpy_option > <NUM_LIT> && arc_mpy_option < <NUM_LIT> ) || ( arc_mpy_option == <NUM_LIT> ) ) ) error ( <STR_LIT> ) ; if ( flag_pic && TARGET_ARC600_FAMILY ) { warning ( DK_WARNING , <STR_LIT> , arc_cpu_string ) ; flag_pic = <NUM_LIT> ; } if ( TARGET_ATOMIC && ! ( TARGET_ARC700 || TARGET_HS ) ) error ( <STR_LIT> ) ; if ( TARGET_LL64 && ! TARGET_HS ) error ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT ) { if ( TARGET_EM && ( arc_fpu_build & ~ ( FPU_SP | FPU_SF | FPU_SC | FPU_SD | FPX_DP ) ) ) error ( <STR_LIT> ) ; if ( TARGET_HS && ( arc_fpu_build & FPX_DP ) ) error ( <STR_LIT> <STR_LIT> ) ; if ( ! TARGET_HS && ! TARGET_EM ) error ( <STR_LIT> ) ; } arc_init_reg_tables ( ) ; memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ;"
GCC,arc,246,"Predict the next statement of this code snippet:
 <s> else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) OF_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_VECTOR_INT : arc_mode_class [ i ] = ( <NUM_LIT> << ( int ) V_MODE ) ; break ; case MODE_CC : default : if ( i == ( int ) CCmode || i == ( int ) CC_ZNmode || i == ( int ) CC_Zmode || i == ( int ) CC_Cmode || i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode || i == CC_FPUmode || i == CC_FPU_UNEQmode ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) C_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; } }"
GCC,arc,247,"Predict the next statement of this code snippet:
 <s> else return false ; if ( ( GET_CODE ( PATTERN ( jump ) ) == PARALLEL ) && ( XVECEXP ( PATTERN ( jump ) , <NUM_LIT> , <NUM_LIT> ) == ret_rtx ) ) return false ; label_rtx = JUMP_LABEL ( jump ) ; if ( ! label_rtx ) return false ; if ( ANY_RETURN_P ( label_rtx ) ) return false ; label = safe_as_a < rtx_insn * > ( label_rtx ) ; succ_bb = BLOCK_FOR_INSN ( label ) ; if ( ! succ_bb ) { gcc_assert ( NEXT_INSN ( label ) ) ; if ( NOTE_INSN_BASIC_BLOCK_P ( NEXT_INSN ( label ) ) ) succ_bb = NOTE_BASIC_BLOCK ( NEXT_INSN ( label ) ) ; else succ_bb = BLOCK_FOR_INSN ( NEXT_INSN ( label ) ) ;"
GCC,arc,248,"Predict the next statement of this code snippet:
 <s> if ( arc_size_opt_level == <NUM_LIT> ) optimize_size = <NUM_LIT> ; if ( flag_pic ) target_flags |= MASK_NO_SDATA_SET ;"
GCC,arc,249,"Predict the next statement of this code snippet:
 <s> case SYMBOL_REF : output_addr_const ( file , addr ) ; if ( SYMBOL_REF_SMALL_P ( addr ) ) fprintf ( file , <STR_LIT> ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == MULT ) index = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , base = XEXP ( addr , <NUM_LIT> ) ; else if ( CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) index = XEXP ( addr , <NUM_LIT> ) , base = XEXP ( addr , <NUM_LIT> ) ; else base = XEXP ( addr , <NUM_LIT> ) , index = XEXP ( addr , <NUM_LIT> ) ;"
GCC,arc,250,"Predict the next statement of this code snippet:
 <s> output_addr_const ( file , addr ) ; if ( SYMBOL_REF_SMALL_P ( addr ) ) fprintf ( file , <STR_LIT> ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == MULT ) index = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , base = XEXP ( addr , <NUM_LIT> ) ; else if ( CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) index = XEXP ( addr , <NUM_LIT> ) , base = XEXP ( addr , <NUM_LIT> ) ;"
GCC,arc,251,"Predict the next statement of this code snippet:
 <s> gcc_assert ( state == none ) ; state = destDx ; } if ( state == none ) return false ; if ( state == srcDx ) { if ( TARGET_DPFP_DISABLE_LRSR ) { rtx set = gen_rtx_SET ( dest , src ) ; rtx use1 = gen_rtx_USE ( VOIDmode , const1_rtx ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , use1 ) ) ) ; } else { rtx destHigh = simplify_gen_subreg ( SImode , dest , DFmode , <NUM_LIT> ) ; rtx destLow = simplify_gen_subreg ( SImode , dest , DFmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( destHigh , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , src ) , VUNSPEC_ARC_LR_HIGH ) ) ) ; emit_insn ( gen_rtx_SET ( destLow , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , src ) , VUNSPEC_ARC_LR ) ) ) ; } } else if ( state == destDx ) { rtx srcHigh = simplify_gen_subreg ( SImode , src , DFmode , <NUM_LIT> ) ;"
GCC,arc,252,"Predict the next statement of this code snippet:
 <s> if ( refers_to_regno_p ( <NUM_LIT> , <NUM_LIT> , src , <NUM_LIT> ) ) state = srcDx ; if ( refers_to_regno_p ( <NUM_LIT> , <NUM_LIT> , dest , <NUM_LIT> ) ) { gcc_assert ( state == none ) ; state = destDx ; } if ( state == none ) return false ; if ( state == srcDx ) { if ( TARGET_DPFP_DISABLE_LRSR ) { rtx set = gen_rtx_SET ( dest , src ) ; rtx use1 = gen_rtx_USE ( VOIDmode , const1_rtx ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , use1 ) ) ) ; }"
GCC,arc,253,"Predict the next statement of this code snippet:
 <s> struct arc_frame_info * frame = & cfun -> machine -> frame_info ; rtx sibthunk_insn = NULL_RTX ; if ( gmask ) { if ( epilogue_p == <NUM_LIT> || frame -> millicode_end_reg > <NUM_LIT> ) { int start_call = frame -> millicode_start_reg ; int end_call = frame -> millicode_end_reg ; int n_regs = end_call - start_call + <NUM_LIT> ; int i = <NUM_LIT> , r , off = <NUM_LIT> ; rtx insn ; rtx ret_addr = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; if ( * first_offset ) { gcc_assert ( epilogue_p || abs ( * first_offset ) <= <NUM_LIT> ) ; frame_add ( base_reg , * first_offset ) ; * first_offset = <NUM_LIT> ; } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( ( epilogue_p == <NUM_LIT> ) + n_regs + <NUM_LIT> ) ) ; if ( epilogue_p == <NUM_LIT> ) i += <NUM_LIT> ; else XVECEXP ( insn , <NUM_LIT> , n_regs ) = gen_rtx_CLOBBER ( VOIDmode , ret_addr ) ; for ( r = start_call ; r <= end_call ; r ++ , off += UNITS_PER_WORD , i ++ ) { rtx reg = gen_rtx_REG ( SImode , r ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base_reg , off ) ) ; if ( epilogue_p ) XVECEXP ( insn , <NUM_LIT> , i ) = gen_rtx_SET ( reg , mem ) ; else XVECEXP ( insn , <NUM_LIT> , i ) = gen_rtx_SET ( mem , reg ) ; gmask = gmask & ~ ( <NUM_LIT> << r ) ; } if ( epilogue_p == <NUM_LIT> ) sibthunk_insn = insn ; else { insn = frame_insn ( insn ) ; if ( epilogue_p ) for ( r = start_call ; r <= end_call ; r ++ ) { rtx reg = gen_rtx_REG ( SImode , r ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ;"
GCC,arc,254,"Predict the next statement of this code snippet:
 <s> CUMULATIVE_ARGS next_cum ; next_cum = * get_cumulative_args ( args_so_far ) ; arc_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , true ) ; first_anon_arg = next_cum ; if ( FUNCTION_ARG_REGNO_P ( first_anon_arg ) ) { int first_reg_offset = first_anon_arg ; if ( ! no_rtl ) { rtx regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( <NUM_LIT> ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , MAX_ARC_PARM_REGS - first_reg_offset ) ; } * pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ;"
GCC,arc,255,"Predict the next statement of this code snippet:
 <s> insn = emit_jump_insn ( insn ) ;"
GCC,arc,256,"Predict the next statement of this code snippet:
 <s> static void emit_unlikely_jump ( rtx insn ) {"
GCC,arc,257,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( y ) == SYMBOL_REF && flag_pic ) y = copy_to_mode_reg ( SImode , y ) ; } else { x = force_reg ( cmode , x ) ; y = force_reg ( cmode , y ) ; } mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( mode , CC_REG ) ; if ( TARGET_ARGONAUT_SET && ( ( cmode == SFmode && TARGET_SPFP ) || ( cmode == DFmode && TARGET_DPFP ) ) ) { switch ( code ) { case NE : case EQ : case LT : case UNGE : case LE : case UNGT : case UNEQ : case LTGT : case ORDERED : case UNORDERED : break ; case GT : case UNLE : case GE : case UNLT : code = swap_condition ( code ) ; tmp = x ; x = y ; y = tmp ; break ; default : gcc_unreachable ( ) ; } if ( cmode == SFmode ) { emit_insn ( gen_cmpsfpx_raw ( x , y ) ) ; } else { emit_insn ( gen_cmpdfpx_raw ( x , y ) ) ; } if ( mode != CC_FPXmode ) emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( mode , gen_rtx_REG ( CC_FPXmode , <NUM_LIT> ) , const0_rtx ) ) ) ; } else if ( TARGET_HARD_FLOAT && ( ( cmode == SFmode && TARGET_FP_SP_BASE ) || ( cmode == DFmode && TARGET_FP_DP_BASE ) ) ) emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; else if ( GET_MODE_CLASS ( cmode ) == MODE_FLOAT && TARGET_OPTFPE ) { rtx op0 = gen_rtx_REG ( cmode , <NUM_LIT> ) ; rtx op1 = gen_rtx_REG ( cmode , GET_MODE_SIZE ( cmode ) / UNITS_PER_WORD ) ; bool swap = false ; switch ( code ) { case NE : case EQ : case GT : case UNLE : case GE : case UNLT : case UNEQ : case LTGT : case ORDERED : case UNORDERED : break ; case LT : case UNGE : case LE : case UNGT : code = swap_condition ( code ) ; swap = true ; break ; default : gcc_unreachable ( ) ;"
GCC,arc,258,"Predict the next statement of this code snippet:
 <s> operands [ <NUM_LIT> ] = gen_rtx_fmt_e ( code , omode , arc_rewrite_small_data ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , operands [ <NUM_LIT> ] ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; }"
GCC,arc,259,"Predict the next statement of this code snippet:
 <s> emit_pic_move ( operands , SImode ) ; } else if ( GET_CODE ( operands [ <NUM_LIT> ] ) != MEM && ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ <NUM_LIT> ] , Pmode ) ) { operands [ <NUM_LIT> ] = arc_rewrite_small_data ( operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , operands [ <NUM_LIT> ] ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; } } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) {"
GCC,arc,260,"Predict the next statement of this code snippet:
 <s> if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ;"
GCC,arc,261,"Predict the next statement of this code snippet:
 <s> for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { succ0 = next_real_insn ( insn ) ; if ( arc_hazard ( insn , succ0 ) ) { emit_insn_before ( gen_nopv ( ) , succ0 ) ;"
GCC,arc,262,"Predict the next statement of this code snippet:
 <s> if ( arc_hazard ( insn , succ0 ) ) { emit_insn_before ( gen_nopv ( ) , succ0 ) ;"
GCC,arc,263,"Predict the next statement of this code snippet:
 <s> case SYMBOL_REF : case CONST : if ( TARGET_NPS_CMEM && cmem_address ( addr , SImode ) ) return <NUM_LIT> ; return COSTS_N_INSNS ( <NUM_LIT> ) ; case PLUS : { register rtx plus0 = XEXP ( addr , <NUM_LIT> ) ; register rtx plus1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) != MULT || ! CONST_INT_P ( XEXP ( plus0 , <NUM_LIT> ) ) || ( INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> && INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> ) ) ) break ;"
GCC,arc,264,"Predict the next statement of this code snippet:
 <s> else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) { label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; then_not_else = FALSE ; } else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == SIMPLE_RETURN ) seeking_return = <NUM_LIT> ; else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == SIMPLE_RETURN ) { seeking_return = <NUM_LIT> ; then_not_else = FALSE ; } else gcc_unreachable ( ) ; if ( NEXT_INSN ( PREV_INSN ( insn ) ) != insn && state -> state == <NUM_LIT> && ! INSN_ANNULLED_BRANCH_P ( insn ) ) { this_insn = NEXT_INSN ( this_insn ) ; gcc_assert ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( start_insn ) ) ) == NEXT_INSN ( this_insn ) ) ; } for ( insns_skipped = <NUM_LIT> , next_must_be_target_label_p = FALSE ; ! fail && ! succeed && insns_skipped < MAX_INSNS_SKIPPED ; insns_skipped ++ ) { rtx scanbody ; this_insn = next_nonnote_insn ( this_insn ) ; if ( ! this_insn ) break ; if ( next_must_be_target_label_p ) { if ( GET_CODE ( this_insn ) == BARRIER ) continue ; if ( GET_CODE ( this_insn ) == CODE_LABEL && this_insn == label ) { state -> state = <NUM_LIT> ; succeed = TRUE ; } else fail = TRUE ; break ; } switch ( GET_CODE ( this_insn ) ) { case CODE_LABEL : if ( this_insn == label ) { state -> state = <NUM_LIT> ; succeed = TRUE ; } else fail = TRUE ; break ; case BARRIER : next_must_be_target_label_p = TRUE ; break ; case CALL_INSN : if ( get_attr_cond ( this_insn ) == COND_CANUSE ) next_must_be_target_label_p = TRUE ; else fail = TRUE ; break ; case JUMP_INSN : scanbody = PATTERN ( this_insn ) ; if ( GET_CODE ( scanbody ) == SET && GET_CODE ( SET_DEST ( scanbody ) ) == PC ) { if ( GET_CODE ( SET_SRC ( scanbody ) ) == LABEL_REF && XEXP ( SET_SRC ( scanbody ) , <NUM_LIT> ) == label && ! reverse ) { state -> state = <NUM_LIT> ; succeed = TRUE ; } else if ( GET_CODE ( SET_SRC ( scanbody ) ) == IF_THEN_ELSE ) fail = TRUE ;"
GCC,arc,265,"Predict the next statement of this code snippet:
 <s> else if ( GET_CODE ( x ) == PLUS && ( ( REG_P ( gp = XEXP ( x , <NUM_LIT> ) ) && REGNO ( gp ) == PIC_OFFSET_TABLE_REGNUM ) || ( GET_CODE ( gp ) == CONST && GET_CODE ( u = XEXP ( gp , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOT && GET_CODE ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF && ! strcmp ( XSTR ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , <STR_LIT> ) ) ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST && GET_CODE ( u = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOTOFF ) return XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ; else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && ( ( REG_P ( gp = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && REGNO ( gp ) == PIC_OFFSET_TABLE_REGNUM ) || ( GET_CODE ( gp ) == CONST && GET_CODE ( u = XEXP ( gp , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOT && GET_CODE ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF && ! strcmp ( XSTR ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , <STR_LIT> ) ) ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST && GET_CODE ( u = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOTOFF ) return gen_rtx_PLUS ( GET_MODE ( x ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ) ;"
GCC,arc,266,"Predict the next statement of this code snippet:
 <s> RTL_PURE_CALL_P ( call_insn ) = <NUM_LIT> ; add_function_usage_to ( call_insn , call_fusage ) ; rtx_insn * insns = get_insns ( ) ; end_sequence ( ) ; rtx dest = gen_reg_rtx ( Pmode ) ;"
GCC,arc,267,"Predict the next statement of this code snippet:
 <s> pat = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; pat = arc_unspec_offset ( pat , ARC_UNSPEC_GOT ) ; pat = gen_rtx_SET ( baseptr_rtx , pat ) ; emit_insn ( pat ) ;"
GCC,arc,268,"Predict the next statement of this code snippet:
 <s> pat = arc_unspec_offset ( pat , ARC_UNSPEC_GOT ) ; pat = gen_rtx_SET ( baseptr_rtx , pat ) ;"
GCC,arc,269,"Predict the next statement of this code snippet:
 <s> static rtx arc_get_tp ( void ) { if ( arc_tp_regno != - <NUM_LIT> ) return gen_rtx_REG ( Pmode , arc_tp_regno ) ; rtx reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_load_tp_soft ( ) ) ; emit_move_insn ( reg , gen_rtx_REG ( Pmode , R0_REG ) ) ; return reg ;"
GCC,arc,270,"Predict the next statement of this code snippet:
 <s> rtx reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_load_tp_soft ( ) ) ; emit_move_insn ( reg , gen_rtx_REG ( Pmode , R0_REG ) ) ; return reg ;"
GCC,arc,271,"Predict the next statement of this code snippet:
 <s> if ( ! TARGET_DPFP && TARGET_DPFP_DISABLE_LRSR ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET && TARGET_DPFP_COMPACT_SET ) || ( TARGET_SPFP_FAST_SET && TARGET_SPFP_COMPACT_SET ) ) error ( <STR_LIT> ) ; if ( TARGET_SPFP_FAST_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET || TARGET_SPFP ) && TARGET_HARD_FLOAT ) error ( <STR_LIT> ) ; if ( flag_pic && TARGET_ARC600_FAMILY ) { warning ( DK_WARNING , <STR_LIT> , arc_cpu_string ) ; flag_pic = <NUM_LIT> ; } arc_init_reg_tables ( ) ; memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ; arc_punct_chars [ '*' ] = <NUM_LIT> ; arc_punct_chars [ '?' ] = <NUM_LIT> ; arc_punct_chars [ '!' ] = <NUM_LIT> ; arc_punct_chars [ '^' ] = <NUM_LIT> ; arc_punct_chars [ '&' ] = <NUM_LIT> ; arc_punct_chars [ '+' ] = <NUM_LIT> ; arc_punct_chars [ '_' ] = <NUM_LIT> ; if ( optimize > <NUM_LIT> && ! TARGET_NO_COND_EXEC ) { opt_pass * pass_arc_ifcvt_4 = make_pass_arc_ifcvt ( g ) ; struct register_pass_info arc_ifcvt4_info = { pass_arc_ifcvt_4 , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_AFTER } ; struct register_pass_info arc_ifcvt5_info = { pass_arc_ifcvt_4 -> clone ( ) , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_BEFORE } ;"
GCC,arc,272,"Predict the next statement of this code snippet:
 <s> arc_init_reg_tables ( ) ; memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ; arc_punct_chars [ '*' ] = <NUM_LIT> ; arc_punct_chars [ '?' ] = <NUM_LIT> ; arc_punct_chars [ '!' ] = <NUM_LIT> ; arc_punct_chars [ '^' ] = <NUM_LIT> ; arc_punct_chars [ '&' ] = <NUM_LIT> ; arc_punct_chars [ '+' ] = <NUM_LIT> ; arc_punct_chars [ '_' ] = <NUM_LIT> ; if ( optimize > <NUM_LIT> && ! TARGET_NO_COND_EXEC ) { opt_pass * pass_arc_ifcvt_4 = make_pass_arc_ifcvt ( g ) ; struct register_pass_info arc_ifcvt4_info = { pass_arc_ifcvt_4 , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_AFTER } ; struct register_pass_info arc_ifcvt5_info = { pass_arc_ifcvt_4 -> clone ( ) , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_BEFORE } ; register_pass ( & arc_ifcvt4_info ) ;"
GCC,arc,273,"Predict the next statement of this code snippet:
 <s> case MODE_COMPLEX_INT : if ( GET_MODE_SIZE ( m ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) S_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) O_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( m ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) OF_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_VECTOR_INT : if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = ( <NUM_LIT> << ( int ) S_MODE ) ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = ( <NUM_LIT> << ( int ) D_MODE ) ;"
GCC,arc,274,"Predict the next statement of this code snippet:
 <s> if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = ( <NUM_LIT> << ( int ) S_MODE ) ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = ( <NUM_LIT> << ( int ) D_MODE ) ; else arc_mode_class [ i ] = ( <NUM_LIT> << ( int ) V_MODE ) ; break ; case MODE_CC : default : if ( i == ( int ) CCmode || i == ( int ) CC_ZNmode || i == ( int ) CC_Zmode || i == ( int ) CC_Cmode || i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode || i == CC_FPUmode || i == CC_FPU_UNEQmode ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) C_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; } }"
GCC,arc,275,"Predict the next statement of this code snippet:
 <s> int arc_label_align ( rtx_insn * label ) { int loop_align = LOOP_ALIGN ( LABEL ) ; if ( loop_align > align_labels_log ) { rtx_insn * prev = prev_nonnote_insn ( label ) ; if ( prev && NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == PARALLEL && recog_memoized ( prev ) == CODE_FOR_doloop_begin_i ) return loop_align ; } if ( align_labels_log < <NUM_LIT> ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ) ;"
GCC,arc,276,"Predict the next statement of this code snippet:
 <s> if ( LEGITIMATE_SMALL_DATA_ADDRESS_P ( x ) ) return true ; if ( GET_CODE ( x ) == CONST_INT && LARGE_INT ( INTVAL ( x ) ) ) return true ; if ( ! flag_pic && optimize_size && ! reload_completed && ( GET_CODE ( x ) == CONST ) && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) && ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> && ! SYMBOL_REF_FUNCTION_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( CONST_INT_P ( addend ) ) ; HOST_WIDE_INT offset = INTVAL ( addend ) ; return ! ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; } if ( ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && CONSTANT_P ( x ) ) {"
GCC,arc,277,"Predict the next statement of this code snippet:
 <s> if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == POST_INC ) && RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; if ( ( GET_CODE ( x ) == PRE_MODIFY || GET_CODE ( x ) == POST_MODIFY ) && GET_CODE ( XEXP ( ( x ) , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( ( x ) , <NUM_LIT> ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && LEGITIMATE_OFFSET_ADDRESS_P ( QImode , XEXP ( x , <NUM_LIT> ) , TARGET_AUTO_MODIFY_REG , strict ) ) return true ; return false ;"
GCC,arc,278,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( ! flag_pic && mode != Pmode ) return true ; switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == PLUS ) { if ( flag_pic ? GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT : ! arc_legitimate_constant_p ( mode , XEXP ( x , <NUM_LIT> ) ) ) return false ;"
GCC,arc,279,"Predict the next statement of this code snippet:
 <s> switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == PLUS ) { if ( flag_pic ? GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT : ! arc_legitimate_constant_p ( mode , XEXP ( x , <NUM_LIT> ) ) ) return false ; x = XEXP ( x , <NUM_LIT> ) ; } if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , <NUM_LIT> ) ) { case ARC_UNSPEC_PLT : case ARC_UNSPEC_GOTOFF : case ARC_UNSPEC_GOTOFFPC :"
GCC,arc,280,"Predict the next statement of this code snippet:
 <s> bool arc_legitimate_pc_offset_p ( rtx addr ) { if ( GET_CODE ( addr ) != CONST ) return false ;"
GCC,arc,281,"Predict the next statement of this code snippet:
 <s> bool arc_legitimate_pc_offset_p ( rtx addr ) { if ( GET_CODE ( addr ) != CONST ) return false ; return arc_needs_pcl_p ( addr ) ;"
GCC,arc,282,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( addr ) != UNSPEC || XVECLEN ( addr , <NUM_LIT> ) != <NUM_LIT> ) return false ;"
GCC,arc,283,"Predict the next statement of this code snippet:
 <s> static rtx arc_legitimize_address ( rtx orig_x , rtx oldx , machine_mode mode ) { if ( GET_CODE ( orig_x ) == SYMBOL_REF ) { enum tls_model model = SYMBOL_REF_TLS_MODEL ( orig_x ) ; if ( model != <NUM_LIT> ) return arc_legitimize_tls_address ( orig_x , model ) ; } rtx new_x = arc_legitimize_address_0 ( orig_x , oldx , mode ) ;"
GCC,arc,284,"Predict the next statement of this code snippet:
 <s> static rtx arc_legitimize_address ( rtx orig_x , rtx oldx , machine_mode mode ) { if ( GET_CODE ( orig_x ) == SYMBOL_REF ) { enum tls_model model = SYMBOL_REF_TLS_MODEL ( orig_x ) ; if ( model != <NUM_LIT> ) return arc_legitimize_tls_address ( orig_x , model ) ;"
GCC,arc,285,"Predict the next statement of this code snippet:
 <s> emit_insn ( gen_rtx_SET ( oldx , gen_rtx_MINUS ( SImode , op0 , oldx ) ) ) ; return oldx ; } else if ( GET_CODE ( addr ) != PLUS ) { rtx tmp = XEXP ( addr , <NUM_LIT> ) ; enum rtx_code code = GET_CODE ( addr ) ; gcc_assert ( UNARY_P ( addr ) ) ; gcc_assert ( GET_CODE ( tmp ) == UNSPEC ) ; gcc_assert ( oldx ) ; emit_move_insn ( oldx , gen_rtx_CONST ( SImode , arc_legitimize_pic_address ( tmp , NULL_RTX ) ) ) ; emit_insn ( gen_rtx_SET ( oldx , gen_rtx_fmt_ee ( code , SImode , oldx , const0_rtx ) ) ) ; return oldx ; } else { gcc_assert ( GET_CODE ( addr ) == PLUS ) ; if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == UNSPEC ) return orig ; } } if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , <NUM_LIT> ) , op1 = XEXP ( addr , <NUM_LIT> ) ; base = arc_legitimize_pic_address ( op0 , oldx ) ; pat = arc_legitimize_pic_address ( op1 , base == oldx ? NULL_RTX : oldx ) ; if ( base == op0 && pat == op1 ) return orig ; if ( GET_CODE ( pat ) == CONST_INT ) pat = plus_constant ( Pmode , base , INTVAL ( pat ) ) ;"
GCC,arc,286,"Predict the next statement of this code snippet:
 <s> base_name = DTPOFF_ZERO_SYM ; if ( decl && bss_initializer_p ( decl ) ) base_name = <STR_LIT> ; base = gen_rtx_SYMBOL_REF ( Pmode , base_name ) ; if ( strcmp ( base_name , DTPOFF_ZERO_SYM ) == <NUM_LIT> ) { if ( ! flag_pic ) goto local_exec ; v = gen_rtvec ( <NUM_LIT> , addr ) ; } else v = gen_rtvec ( <NUM_LIT> , addr , base ) ;"
GCC,arc,287,"Predict the next statement of this code snippet:
 <s> if ( recog_memoized ( succ ) != CODE_FOR_doloop_end_i ) return false ; if ( TARGET_ARC600 || TARGET_HS ) if ( JUMP_P ( pred ) || CALL_P ( pred ) || arc_asm_insn_p ( PATTERN ( pred ) ) || GET_CODE ( PATTERN ( pred ) ) == SEQUENCE ) return true ; if ( JUMP_P ( pred ) ) jump = pred ; else if ( GET_CODE ( PATTERN ( pred ) ) == SEQUENCE && JUMP_P ( XVECEXP ( PATTERN ( pred ) , <NUM_LIT> , <NUM_LIT> ) ) ) jump = as_a < rtx_insn * > ( XVECEXP ( PATTERN ( pred ) , <NUM_LIT> , <NUM_LIT> ) ) ; else return false ; if ( ( GET_CODE ( PATTERN ( jump ) ) == PARALLEL ) && ( XVECEXP ( PATTERN ( jump ) , <NUM_LIT> , <NUM_LIT> ) == ret_rtx ) ) return false ; label_rtx = JUMP_LABEL ( jump ) ; if ( ! label_rtx ) return false ; if ( ANY_RETURN_P ( label_rtx ) ) return false ; label = safe_as_a < rtx_insn * > ( label_rtx ) ; succ_bb = BLOCK_FOR_INSN ( label ) ; if ( ! succ_bb ) { gcc_assert ( NEXT_INSN ( label ) ) ; if ( NOTE_INSN_BASIC_BLOCK_P ( NEXT_INSN ( label ) ) ) succ_bb = NOTE_BASIC_BLOCK ( NEXT_INSN ( label ) ) ;"
GCC,arc,288,"Predict the next statement of this code snippet:
 <s> register int i , j ; if ( ( GET_CODE ( x ) == UNSPEC ) && ( XVECLEN ( x , <NUM_LIT> ) == <NUM_LIT> ) && ( GET_CODE ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF ) ) switch ( XINT ( x , <NUM_LIT> ) ) { case ARC_UNSPEC_GOT : case ARC_UNSPEC_GOTOFFPC : case UNSPEC_TLS_GD :"
GCC,arc,289,"Predict the next statement of this code snippet:
 <s> register int i , j ; if ( ( GET_CODE ( x ) == UNSPEC ) && ( XVECLEN ( x , <NUM_LIT> ) == <NUM_LIT> ) && ( GET_CODE ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF ) ) switch ( XINT ( x , <NUM_LIT> ) ) { case ARC_UNSPEC_GOT : case ARC_UNSPEC_GOTOFFPC : case UNSPEC_TLS_GD : case UNSPEC_TLS_IE : return true ; default : break ; } fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( arc_needs_pcl_p ( XEXP ( x , i ) ) ) return true ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( arc_needs_pcl_p ( XVECEXP ( x , i , j ) ) ) return true ; }"
GCC,arc,290,"Predict the next statement of this code snippet:
 <s> int match = operands_match_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; int match2 = operands_match_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; int intval = ( REG_P ( operands [ <NUM_LIT> ] ) ? <NUM_LIT> : CONST_INT_P ( operands [ <NUM_LIT> ] ) ? INTVAL ( operands [ <NUM_LIT> ] ) : <NUM_LIT> ) ;"
GCC,arc,291,"Predict the next statement of this code snippet:
 <s> gcc_assert ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) ) ; switch ( commutative_op ) { case AND : if ( satisfies_constraint_C1p ( operands [ <NUM_LIT> ] ) ) pat = <STR_LIT> ; else if ( satisfies_constraint_C2p ( operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = GEN_INT ( ( ~ INTVAL ( operands [ <NUM_LIT> ] ) ) ) ; pat = <STR_LIT> ; }"
GCC,arc,292,"Predict the next statement of this code snippet:
 <s> arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else gcc_unreachable ( ) ; break ; case MINUS : x = simplify_subtraction ( x ) ; if ( GET_CODE ( x ) != MINUS ) goto restart ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( x , <NUM_LIT> ) ) < <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; } else arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case ZERO_EXTEND : case SIGN_EXTEND : arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case UNSPEC : const char * suffix ; bool pcrel ; pcrel = false ; rtx base ; base = NULL ; gcc_assert ( XVECLEN ( x , <NUM_LIT> ) >= <NUM_LIT> ) ; switch ( XINT ( x , <NUM_LIT> ) ) { case ARC_UNSPEC_GOT : suffix = <STR_LIT> , pcrel = true ; break ; case ARC_UNSPEC_GOTOFF : suffix = <STR_LIT> ; break ; case ARC_UNSPEC_GOTOFFPC : suffix = <STR_LIT> , pcrel = true ; break ; case ARC_UNSPEC_PLT : suffix = <STR_LIT> ; break ; case UNSPEC_TLS_GD : suffix = <STR_LIT> , pcrel = true ; break ; case UNSPEC_TLS_IE : suffix = <STR_LIT> , pcrel = true ; break ; case UNSPEC_TLS_OFF : if ( XVECLEN ( x , <NUM_LIT> ) == <NUM_LIT> ) base = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; if ( SYMBOL_REF_TLS_MODEL ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == TLS_MODEL_LOCAL_EXEC || ( ! flag_pic && ! base ) ) suffix = <STR_LIT> ; else suffix = <STR_LIT> ; break ;"
GCC,arc,293,"Predict the next statement of this code snippet:
 <s> return TARGET_PLUS_QMACW ? V4HImode : V2HImode ; case SImode : return V2SImode ; default : return word_mode ; }"
GCC,arc,294,"Predict the next statement of this code snippet:
 <s> if ( ( GET_CODE ( c ) == UNSPEC && ( XINT ( c , <NUM_LIT> ) == UNSPEC_TLS_OFF || XINT ( c , <NUM_LIT> ) == UNSPEC_TLS_IE ) ) || ( GET_CODE ( c ) == PLUS && GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == UNSPEC && ( XINT ( XEXP ( c , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS_OFF || XINT ( XEXP ( c , <NUM_LIT> ) , <NUM_LIT> ) == ARC_UNSPEC_GOTOFFPC ) ) ) { arc_output_pic_addr_const ( file , c , <NUM_LIT> ) ; break ; } gcc_assert ( GET_CODE ( c ) == PLUS ) ; gcc_assert ( GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == SYMBOL_REF ) ; gcc_assert ( GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == CONST_INT ) ;"
GCC,arc,295,"Predict the next statement of this code snippet:
 <s> arc_print_operand_address ( file , base ) ; if ( CONSTANT_P ( base ) && CONST_INT_P ( index ) ) fputc ( '+' , file ) ; else fputc ( ',' , file ) ; gcc_assert ( OBJECT_P ( index ) ) ; arc_print_operand_address ( file , index ) ; break ; case CONST : { rtx c = XEXP ( addr , <NUM_LIT> ) ; if ( ( GET_CODE ( c ) == UNSPEC && ( XINT ( c , <NUM_LIT> ) == UNSPEC_TLS_OFF || XINT ( c , <NUM_LIT> ) == UNSPEC_TLS_IE ) ) || ( GET_CODE ( c ) == PLUS && GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == UNSPEC && ( XINT ( XEXP ( c , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS_OFF || XINT ( XEXP ( c , <NUM_LIT> ) , <NUM_LIT> ) == ARC_UNSPEC_GOTOFFPC ) ) ) { arc_output_pic_addr_const ( file , c , <NUM_LIT> ) ; break ;"
GCC,arc,296,"Predict the next statement of this code snippet:
 <s> else { rtx destHigh = simplify_gen_subreg ( SImode , dest , DFmode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ; rtx destLow = simplify_gen_subreg ( SImode , dest , DFmode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( destHigh , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , src ) , VUNSPEC_ARC_LR_HIGH ) ) ) ; emit_insn ( gen_rtx_SET ( destLow , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , src ) , VUNSPEC_ARC_LR ) ) ) ; } } else if ( state == destDx ) { rtx srcHigh = simplify_gen_subreg ( SImode , src , DFmode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,297,"Predict the next statement of this code snippet:
 <s> if ( TARGET_ARC700 && ( from_class == LPCOUNT_REG || from_class == ALL_CORE_REGS || from_class == WRITABLE_CORE_REGS ) ) return <NUM_LIT> ;"
GCC,arc,298,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_SMALL_P ( x ) ) { gcc_assert ( SYMBOL_REF_TLS_MODEL ( x ) == <NUM_LIT> ) ; return true ; } return false ;"
GCC,arc,299,"Predict the next statement of this code snippet:
 <s> static bool arc_rewrite_small_data_p ( const_rtx x ) { if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) x = XEXP ( x , <NUM_LIT> ) ; } if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_SMALL_P ( x ) ) { gcc_assert ( SYMBOL_REF_TLS_MODEL ( x ) == <NUM_LIT> ) ; return true ; } return false ;"
GCC,arc,300,"Predict the next statement of this code snippet:
 <s> case SYMBOL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case CONST_DOUBLE : { rtx first , second ; if ( TARGET_DPFP ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } split_double ( x , & first , & second ) ; * total = COSTS_N_INSNS ( ! SMALL_INT ( INTVAL ( first ) ) + ! SMALL_INT ( INTVAL ( second ) ) ) ; return true ; } case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( TARGET_BARREL_SHIFTER ) { if ( CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { * total += ( COSTS_N_INSNS ( <NUM_LIT> ) + rtx_cost ( XEXP ( x , <NUM_LIT> ) , mode , ( enum rtx_code ) code , <NUM_LIT> , speed ) ) ; return true ; } * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else { * total = COSTS_N_INSNS ( INTVAL ( XEXP ( ( x ) , <NUM_LIT> ) ) ) ; if ( * total < <NUM_LIT> ) * total = <NUM_LIT> ; } return false ; case DIV : case UDIV : if ( speed ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case MULT : if ( ( TARGET_DPFP && GET_MODE ( x ) == DFmode ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( speed ) * total = arc_multcost ; else if ( TARGET_MUL64_SET || TARGET_ARC700_MPY ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && _2_4_8_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) { * total += ( rtx_cost ( XEXP ( x , <NUM_LIT> ) , mode , PLUS , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , mode , PLUS , <NUM_LIT> , speed ) ) ; return true ; } return false ; case MINUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && _2_4_8_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) {"
GCC,arc,301,"Predict the next statement of this code snippet:
 <s> rtx in_set , out_set ; rtx out_addr , in_addr ; if ( ! producer ) return false ; if ( ! consumer ) return false ; out_set = single_set ( producer ) ; if ( out_set ) { out_addr = SET_DEST ( out_set ) ; if ( ! out_addr ) return false ; if ( GET_CODE ( out_addr ) == ZERO_EXTEND || GET_CODE ( out_addr ) == SIGN_EXTEND ) out_addr = XEXP ( out_addr , <NUM_LIT> ) ; if ( ! MEM_P ( out_addr ) ) return false ; in_set = single_set ( consumer ) ; if ( in_set ) { in_addr = SET_SRC ( in_set ) ; if ( ! in_addr ) return false ; if ( GET_CODE ( in_addr ) == ZERO_EXTEND || GET_CODE ( in_addr ) == SIGN_EXTEND ) in_addr = XEXP ( in_addr , <NUM_LIT> ) ; if ( ! MEM_P ( in_addr ) ) return false ; in_addr = XEXP ( in_addr , <NUM_LIT> ) ; out_addr = XEXP ( out_addr , <NUM_LIT> ) ; return exp_equiv_p ( in_addr , out_addr , <NUM_LIT> , true ) ; }"
GCC,arc,302,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( out_addr ) == ZERO_EXTEND || GET_CODE ( out_addr ) == SIGN_EXTEND ) out_addr = XEXP ( out_addr , <NUM_LIT> ) ; if ( ! MEM_P ( out_addr ) ) return false ; in_set = single_set ( consumer ) ; if ( in_set ) { in_addr = SET_SRC ( in_set ) ; if ( ! in_addr ) return false ; if ( GET_CODE ( in_addr ) == ZERO_EXTEND || GET_CODE ( in_addr ) == SIGN_EXTEND ) in_addr = XEXP ( in_addr , <NUM_LIT> ) ; if ( ! MEM_P ( in_addr ) ) return false ; in_addr = XEXP ( in_addr , <NUM_LIT> ) ; out_addr = XEXP ( out_addr , <NUM_LIT> ) ; return exp_equiv_p ( in_addr , out_addr , <NUM_LIT> , true ) ; } } return false ;"
GCC,arc,303,"Predict the next statement of this code snippet:
 <s> case V2HImode : return TARGET_PLUS_DMPY ; case V4HImode : case V2SImode : return TARGET_PLUS_QMACW ; case V4SImode : case V8HImode : return TARGET_SIMD_SET ; default : return false ;"
GCC,arc,304,"Predict the next statement of this code snippet:
 <s> static void emit_unlikely_jump ( rtx insn ) {"
GCC,arc,305,"Predict the next statement of this code snippet:
 <s> rtx_insn * jump = emit_jump_insn ( insn ) ;"
GCC,arc,306,"Predict the next statement of this code snippet:
 <s> if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) {"
GCC,arc,307,"Predict the next statement of this code snippet:
 <s> static void prepare_pic_move ( rtx * operands , machine_mode ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) && flag_pic ) operands [ <NUM_LIT> ] = force_reg ( Pmode , operands [ <NUM_LIT> ] ) ; else { rtx temp = ( reload_in_progress ? operands [ <NUM_LIT> ] : flag_pic ? gen_reg_rtx ( Pmode ) : NULL_RTX ) ;"
GCC,arc,308,"Predict the next statement of this code snippet:
 <s> emit_insn_after ( gen_nopv ( ) , insn ) ; emit_insn_after ( gen_nopv ( ) , insn ) ; continue ; } succ1 = next_real_insn ( succ0 ) ; if ( succ0 && ! JUMP_P ( succ0 ) && ! CALL_P ( succ0 ) && arc_store_addr_hazard_p ( insn , succ1 ) ) emit_insn_after ( gen_nopv ( ) , insn ) ; } }"
GCC,arc,309,"Predict the next statement of this code snippet:
 <s> static void arc_autovectorize_vector_sizes ( vector_sizes * sizes ) { if ( TARGET_PLUS_QMACW ) { sizes -> quick_push ( <NUM_LIT> ) ; sizes -> quick_push ( <NUM_LIT> ) ; }"
GCC,arc,310,"Predict the next statement of this code snippet:
 <s> sizes -> quick_push ( <NUM_LIT> ) ; sizes -> quick_push ( <NUM_LIT> ) ;"
GCC,arc,311,"Predict the next statement of this code snippet:
 <s> static rtx arc_builtin_setjmp_frame_value ( void ) { return gen_raw_REG ( Pmode , FRAME_POINTER_REGNUM ) ;"
GCC,arc,312,"Predict the next statement of this code snippet:
 <s> static rtx arc_builtin_setjmp_frame_value ( void ) {"
GCC,arc,313,"Predict the next statement of this code snippet:
 <s> return ( ( to == FRAME_POINTER_REGNUM ) || ! arc_frame_pointer_needed ( ) ) ;"
GCC,arc,314,"Predict the next statement of this code snippet:
 <s> static bool arc_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( ( to == FRAME_POINTER_REGNUM ) || ! arc_frame_pointer_needed ( ) ) ;"
GCC,arc,315,"Predict the next statement of this code snippet:
 <s> int size ; if ( cfun -> machine -> frame_info . initialized ) return cfun -> machine -> frame_info . total_size ; frame_info = & cfun -> machine -> frame_info ; size = ARC_STACK_ALIGN ( get_frame_size ( ) ) ; var_size = size ; args_size = crtl -> outgoing_args_size ; reg_size = <NUM_LIT> ; gmask = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( arc_must_save_register ( regno , cfun ) ) { reg_size += UNITS_PER_WORD ; gmask |= <NUM_LIT> << regno ; } } if ( crtl -> calls_eh_return ) for ( regno = <NUM_LIT> ; EH_RETURN_DATA_REGNO ( regno ) != INVALID_REGNUM ; regno ++ ) { reg_size += UNITS_PER_WORD ; gmask |= <NUM_LIT> << regno ; } frame_info -> save_return_addr = ( ! crtl -> is_leaf || df_regs_ever_live_p ( RETURN_ADDR_REGNUM ) || crtl -> calls_eh_return ) ; if ( optimize_size && ! TARGET_NO_MILLICODE_THUNK_SET && ! crtl -> calls_eh_return ) { if ( arc_compute_millicode_save_restore_regs ( gmask , frame_info ) ) frame_info -> save_return_addr = true ; } extra_size = <NUM_LIT> ; if ( arc_must_save_return_addr ( cfun ) ) extra_size = <NUM_LIT> ; if ( arc_frame_pointer_needed ( ) ) extra_size += <NUM_LIT> ; pretend_size = crtl -> args . pretend_args_size ; { unsigned int extra_plus_reg_size ; unsigned int extra_plus_reg_size_aligned ; extra_plus_reg_size = extra_size + reg_size ; extra_plus_reg_size_aligned = ARC_STACK_ALIGN ( extra_plus_reg_size ) ; reg_size = extra_plus_reg_size_aligned - extra_size ; } total_size = var_size + args_size + extra_size + pretend_size + reg_size ; gcc_assert ( total_size == ARC_STACK_ALIGN ( total_size ) ) ; reg_offset = ( total_size - ( pretend_size + reg_size + extra_size ) + ( arc_frame_pointer_needed ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; frame_info -> total_size = total_size ; frame_info -> extra_size = extra_size ; frame_info -> pretend_size = pretend_size ; frame_info -> var_size = var_size ; frame_info -> args_size = args_size ; frame_info -> reg_size = reg_size ; frame_info -> reg_offset = reg_offset ;"
GCC,arc,316,"Predict the next statement of this code snippet:
 <s> value = TREE_VALUE ( args ) ; gcc_assert ( TREE_CODE ( value ) == STRING_CST ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) || ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type |= ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type |= ARC_FUNCTION_ILINK2 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type |= ARC_FUNCTION_FIRQ ; else gcc_unreachable ( ) ; } return fun -> machine -> fn_type = fn_type ;"
GCC,arc,317,"Predict the next statement of this code snippet:
 <s> rtx mem ; int offset ; struct arc_frame_info * afi ; arc_compute_frame_size ( ) ; afi = & cfun -> machine -> frame_info ;"
GCC,arc,318,"Predict the next statement of this code snippet:
 <s> if ( reload_completed ) { if ( ARC_INTERRUPT_P ( cfun -> machine -> fn_type ) ) {"
GCC,arc,319,"Predict the next statement of this code snippet:
 <s> if ( ! fixed_regs [ regno ] ) return true ; return ( ( regno == arc_return_address_register ( fn_type ) ) || ( regno == RETURN_ADDR_REGNUM ) ) ; } else return regno == RETURN_ADDR_REGNUM ;"
GCC,arc,320,"Predict the next statement of this code snippet:
 <s> if ( ! can_trust_sp_p ) gcc_assert ( arc_frame_pointer_needed ( ) ) ; if ( frame_size ) { if ( arc_frame_pointer_needed ( ) ) frame_move ( stack_pointer_rtx , frame_pointer_rtx ) ; else first_offset = frame_size ; size_to_deallocate -= frame_size ; } else if ( ! can_trust_sp_p ) frame_stack_add ( - frame_size ) ; if ( arc_frame_pointer_needed ( ) && ! ARC_AUTOFP_IRQ_P ( fn_type ) ) { rtx addr = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; insn = frame_move_inc ( frame_pointer_rtx , gen_frame_mem ( Pmode , addr ) , stack_pointer_rtx , <NUM_LIT> ) ; add_reg_note ( insn , REG_CFA_RESTORE , frame_pointer_rtx ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( SImode , stack_pointer_rtx , <NUM_LIT> ) ) ; size_to_deallocate -= UNITS_PER_WORD ; } if ( millicode_p ) { int sibthunk_p = ( ! sibcall_p && fn_type == ARC_FUNCTION_NORMAL && ! cfun -> machine -> frame_info . pretend_size ) ; gcc_assert ( ! ( cfun -> machine -> frame_info . gmask & ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) ) ) ; arc_save_restore ( stack_pointer_rtx , cfun -> machine -> frame_info . gmask , <NUM_LIT> + sibthunk_p , & first_offset ) ; if ( sibthunk_p ) return ; } if ( ( ! SMALL_INT ( first_offset ) && cfun -> machine -> frame_info . gmask && ( ( TARGET_ARC700 && ! optimize_size ) ? first_offset <= <NUM_LIT> : satisfies_constraint_C2a ( GEN_INT ( first_offset ) ) ) ) || ( arc_must_save_return_addr ( cfun ) && ! SMALL_INT ( ( cfun -> machine -> frame_info . reg_size + first_offset ) >> <NUM_LIT> ) && cfun -> machine -> frame_info . gmask ) ) { frame_stack_add ( first_offset ) ; first_offset = <NUM_LIT> ; } if ( arc_must_save_return_addr ( cfun ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) ) { rtx ra = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; int ra_offs = cfun -> machine -> frame_info . reg_size + first_offset ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , ra_offs ) ; HOST_WIDE_INT cfa_adjust = <NUM_LIT> ; if ( ! SMALL_INT ( ra_offs >> <NUM_LIT> ) && ! cfun -> machine -> frame_info . gmask && ( ( TARGET_ARC700 && ! optimize_size ) ? ra_offs <= <NUM_LIT> : satisfies_constraint_C2a ( GEN_INT ( ra_offs ) ) ) ) { size_to_deallocate -= ra_offs - first_offset ; first_offset = <NUM_LIT> ; frame_stack_add ( ra_offs ) ; ra_offs = <NUM_LIT> ;"
GCC,arc,321,"Predict the next statement of this code snippet:
 <s> rtx src = operands [ <NUM_LIT> ] ; rtx dst_addr , src_addr ; HOST_WIDE_INT size ; int align = INTVAL ( operands [ <NUM_LIT> ] ) ; unsigned n_pieces ; int piece = align ; rtx store [ <NUM_LIT> ] ; rtx tmpx [ <NUM_LIT> ] ; int i ; if ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) ) return false ; size = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( align >= <NUM_LIT> ) { if ( TARGET_LL64 ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> + ( ( size >> <NUM_LIT> ) & <NUM_LIT> ) + ( size & <NUM_LIT> ) ; else n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> + ( size & <NUM_LIT> ) ; } else if ( align == <NUM_LIT> ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> ; else n_pieces = size ; if ( n_pieces >= ( unsigned int ) ( optimize_size ? <NUM_LIT> : <NUM_LIT> ) ) return false ; if ( TARGET_LL64 && ( piece >= <NUM_LIT> ) && ( size >= <NUM_LIT> ) ) piece = <NUM_LIT> ; else if ( piece > <NUM_LIT> ) piece = <NUM_LIT> ; dst_addr = force_offsettable ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , size , <NUM_LIT> ) ;"
GCC,arc,322,"Predict the next statement of this code snippet:
 <s> store [ <NUM_LIT> ] = store [ <NUM_LIT> ] = NULL_RTX ; tmpx [ <NUM_LIT> ] = tmpx [ <NUM_LIT> ] = NULL_RTX ; for ( i = <NUM_LIT> ; size > <NUM_LIT> ; i ^= <NUM_LIT> , size -= piece ) { rtx tmp ; machine_mode mode ; while ( piece > size ) piece >>= <NUM_LIT> ; mode = smallest_int_mode_for_size ( piece * BITS_PER_UNIT ) ; if ( <NUM_LIT> && tmpx [ i ] && GET_MODE ( tmpx [ i ] ) == mode ) tmp = tmpx [ i ] ; else tmpx [ i ] = tmp = gen_reg_rtx ( mode ) ; dst_addr = force_offsettable ( dst_addr , piece , <NUM_LIT> ) ; src_addr = force_offsettable ( src_addr , piece , <NUM_LIT> ) ; if ( store [ i ] ) emit_insn ( store [ i ] ) ; emit_move_insn ( tmp , change_address ( src , mode , src_addr ) ) ; store [ i ] = gen_move_insn ( change_address ( dst , mode , dst_addr ) , tmp ) ;"
GCC,arc,323,"Predict the next statement of this code snippet:
 <s> asm_fprintf ( asm_out_file , <STR_LIT> , ATTRIBUTE_PCS ) ; asm_fprintf ( asm_out_file , <STR_LIT> , TARGET_RF16 ? <NUM_LIT> : <NUM_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> , flag_pic ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,324,"Predict the next statement of this code snippet:
 <s> asm_fprintf ( asm_out_file , <STR_LIT> , ATTRIBUTE_PCS ) ; asm_fprintf ( asm_out_file , <STR_LIT> , TARGET_RF16 ? <NUM_LIT> : <NUM_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> , flag_pic ? <NUM_LIT> : <NUM_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> , ( arc_tp_regno != - <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> , TARGET_NO_SDATA_SET ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,325,"Predict the next statement of this code snippet:
 <s> if ( ! cfun -> machine -> prescan_initialized ) { memset ( & arc_ccfsm_current , <NUM_LIT> , sizeof arc_ccfsm_current ) ; cfun -> machine -> prescan_initialized = <NUM_LIT> ;"
GCC,arc,326,"Predict the next statement of this code snippet:
 <s> } if ( TREE_CODE ( * node ) == VAR_DECL ) { tree fntype = TREE_TYPE ( * node ) ; if ( fntype && TREE_CODE ( fntype ) == POINTER_TYPE ) { tree attrs = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( fntype ) ) ; TYPE_ATTRIBUTES ( fntype ) = attrs ; } } }"
GCC,arc,327,"Predict the next statement of this code snippet:
 <s> tree arg = TREE_VALUE ( args ) ; if ( TREE_CODE ( arg ) != INTEGER_CST ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; } } if ( TREE_CODE ( * node ) == VAR_DECL ) { tree fntype = TREE_TYPE ( * node ) ; if ( fntype && TREE_CODE ( fntype ) == POINTER_TYPE ) { tree attrs = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( fntype ) ) ; TYPE_ATTRIBUTES ( fntype ) = attrs ; } } }"
GCC,arc,328,"Predict the next statement of this code snippet:
 <s> if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) { return ( cfun -> machine -> frame_info . extra_size + cfun -> machine -> frame_info . reg_size ) ; } if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return ( cfun -> machine -> frame_info . total_size - cfun -> machine -> frame_info . pretend_size ) ; }"
GCC,arc,329,"Predict the next statement of this code snippet:
 <s> if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return ( cfun -> machine -> frame_info . total_size - cfun -> machine -> frame_info . pretend_size ) ; }"
GCC,arc,330,"Predict the next statement of this code snippet:
 <s> struct mem_attrs * refattrs ; if ( ! MEM_P ( pat ) ) return false ; refattrs = MEM_ATTRS ( pat ) ; if ( ! refattrs || ! refattrs -> expr ) return false ; ttype = TREE_TYPE ( refattrs -> expr ) ; if ( ! ttype ) return false ; attrs = TYPE_ATTRIBUTES ( ttype ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ;"
GCC,arc,331,"Predict the next statement of this code snippet:
 <s> if ( INSN_P ( next ) && recog_memoized ( next ) >= <NUM_LIT> ) return <NUM_LIT> ; }"
GCC,arc,332,"Predict the next statement of this code snippet:
 <s> if ( align_labels_log < <NUM_LIT> ) {"
GCC,arc,333,"Predict the next statement of this code snippet:
 <s> } if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == POST_INC ) && RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; if ( ( GET_CODE ( x ) == PRE_MODIFY || GET_CODE ( x ) == POST_MODIFY ) && GET_CODE ( XEXP ( ( x ) , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( ( x ) , <NUM_LIT> ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && legitimate_offset_address_p ( QImode , XEXP ( x , <NUM_LIT> ) , TARGET_AUTO_MODIFY_REG , strict ) ) return true ;"
GCC,arc,334,"Predict the next statement of this code snippet:
 <s> gcc_assert ( CONST_INT_P ( addend ) ) ; HOST_WIDE_INT offset = INTVAL ( addend ) ; return ! ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; } if ( ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && CONSTANT_P ( x ) ) { return arc_legitimate_constant_p ( mode , x ) ; } if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == POST_INC ) && RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; if ( ( GET_CODE ( x ) == PRE_MODIFY || GET_CODE ( x ) == POST_MODIFY ) && GET_CODE ( XEXP ( ( x ) , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( ( x ) , <NUM_LIT> ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && legitimate_offset_address_p ( QImode , XEXP ( x , <NUM_LIT> ) , TARGET_AUTO_MODIFY_REG , strict ) ) return true ; return false ;"
GCC,arc,335,"Predict the next statement of this code snippet:
 <s> break ; case <NUM_LIT> : firq_auto_save_p &= ( ( regno < <NUM_LIT> ) || ( ( regno > <NUM_LIT> ) && ( regno < <NUM_LIT> ) ) || ( ( regno > <NUM_LIT> ) && ( regno < <NUM_LIT> ) ) || ( ( regno > <NUM_LIT> ) && ( regno < <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : firq_auto_save_p &= ( regno != <NUM_LIT> ) && ( regno < <NUM_LIT> ) ; break ; default : firq_auto_save_p = false ;"
GCC,arc,336,"Predict the next statement of this code snippet:
 <s> int shift = <NUM_LIT> ; int this_regno = aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ? <NUM_LIT> : <NUM_LIT> ; rtx fnaddr ; if ( mi_delta < <NUM_LIT> ) mi_delta = - mi_delta ; while ( mi_delta != <NUM_LIT> ) { if ( ( mi_delta & ( <NUM_LIT> << shift ) ) == <NUM_LIT> ) shift += <NUM_LIT> ; else { asm_fprintf ( file , <STR_LIT> , mi_op , reg_names [ this_regno ] , reg_names [ this_regno ] , mi_delta & ( <NUM_LIT> << shift ) ) ; mi_delta &= ~ ( <NUM_LIT> << shift ) ; shift += <NUM_LIT> ; } } if ( vcall_offset != <NUM_LIT> ) { asm_fprintf ( file , <STR_LIT> , ARC_TEMP_SCRATCH_REG , reg_names [ this_regno ] ) ; asm_fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , ARC_TEMP_SCRATCH_REG , ARC_TEMP_SCRATCH_REG , vcall_offset ) ; asm_fprintf ( file , <STR_LIT> , ARC_TEMP_SCRATCH_REG , ARC_TEMP_SCRATCH_REG ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ this_regno ] , reg_names [ this_regno ] , ARC_TEMP_SCRATCH_REG ) ; } fnaddr = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( arc_is_longcall_p ( fnaddr ) ) { if ( flag_pic ) { asm_fprintf ( file , <STR_LIT> , ARC_TEMP_SCRATCH_REG ) ; assemble_name ( file , XSTR ( fnaddr , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , file ) ; asm_fprintf ( file , <STR_LIT> , ARC_TEMP_SCRATCH_REG ) ; } else { fputs ( <STR_LIT> , file ) ; assemble_name ( file , XSTR ( fnaddr , <NUM_LIT> ) ) ; } }"
GCC,arc,337,"Predict the next statement of this code snippet:
 <s> int arc_register_move_cost ( machine_mode , enum reg_class from_class , enum reg_class to_class ) { if ( TARGET_ARC600 ) { if ( to_class == MPY_WRITABLE_CORE_REGS ) return <NUM_LIT> ;"
GCC,arc,338,"Predict the next statement of this code snippet:
 <s> else { rtx op , cc_clob_rtx , op0 , op1 , brcc_insn , note ; rtx cmp0 , cmp1 ; op = XEXP ( pc_target , <NUM_LIT> ) ; op0 = cmp0 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; op1 = cmp1 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == ZERO_EXTRACT && XEXP ( op0 , <NUM_LIT> ) == const1_rtx && ( GET_CODE ( op ) == EQ || GET_CODE ( op ) == NE ) ) { op0 = XEXP ( cmp0 , <NUM_LIT> ) ; op1 = XEXP ( cmp0 , <NUM_LIT> ) ; } else if ( ! register_operand ( op0 , VOIDmode ) || ! general_operand ( op1 , VOIDmode ) ) continue ; else if ( TARGET_SPFP && GET_MODE ( op0 ) == SFmode && GET_MODE ( op1 ) == SFmode ) continue ; if ( reg_set_between_p ( op0 , link_insn , insn ) ) continue ; if ( reg_set_between_p ( op1 , link_insn , insn ) ) continue ; if ( ( reg_set_between_p ( SET_DEST ( pat ) , link_insn , insn ) ) || ( reg_used_between_p ( SET_DEST ( pat ) , link_insn , insn ) ) ) continue ; if ( ! find_regno_note ( insn , REG_DEAD , CC_REG ) ) continue ; op = gen_rtx_fmt_ee ( GET_CODE ( op ) , GET_MODE ( op ) , cmp0 , cmp1 ) ; if ( ! brcc_nolimm_operator ( op , VOIDmode ) && ! long_immediate_operand ( op1 , VOIDmode ) && ( TARGET_ARC700 || next_active_insn ( link_insn ) != insn ) ) continue ; if ( op0 != cmp0 ) cc_clob_rtx = gen_rtx_REG ( CC_ZNmode , CC_REG ) ; else if ( ( offset >= - <NUM_LIT> && offset < <NUM_LIT> ) && rtx_equal_p ( op1 , const0_rtx ) && compact_register_operand ( op0 , VOIDmode ) && ( GET_CODE ( op ) == EQ || GET_CODE ( op ) == NE ) ) cc_clob_rtx = gen_rtx_REG ( CC_Zmode , CC_REG ) ; else cc_clob_rtx = gen_rtx_REG ( CCmode , CC_REG ) ; brcc_insn = gen_rtx_IF_THEN_ELSE ( VOIDmode , op , label , pc_rtx ) ; brcc_insn = gen_rtx_SET ( pc_rtx , brcc_insn ) ; cc_clob_rtx = gen_rtx_CLOBBER ( VOIDmode , cc_clob_rtx ) ; brcc_insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , brcc_insn , cc_clob_rtx ) ) ; brcc_insn = emit_jump_insn_before ( brcc_insn , insn ) ; JUMP_LABEL ( brcc_insn ) = JUMP_LABEL ( insn ) ; note = find_reg_note ( insn , REG_BR_PROB , <NUM_LIT> ) ; if ( note ) { XEXP ( note , <NUM_LIT> ) = REG_NOTES ( brcc_insn ) ; REG_NOTES ( brcc_insn ) = note ;"
GCC,arc,339,"Predict the next statement of this code snippet:
 <s> if ( ( ( fn_type & ARC_FUNCTION_ILINK1 ) | ARC_FUNCTION_FIRQ ) != <NUM_LIT> ) regno = ILINK1_REGNUM ; else if ( ( fn_type & ARC_FUNCTION_ILINK2 ) != <NUM_LIT> ) regno = ILINK2_REGNUM ; else gcc_unreachable ( ) ;"
GCC,arc,340,"Predict the next statement of this code snippet:
 <s> rtx arc_rewrite_small_data ( rtx op ) { op = arc_rewrite_small_data_1 ( op ) ; if ( MEM_P ( op ) && ! LEGITIMATE_SMALL_DATA_ADDRESS_P ( XEXP ( op , <NUM_LIT> ) ) ) { rtx addr = XEXP ( op , <NUM_LIT> ) ; rtx tmp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tmp , addr ) ; op = replace_equiv_address_nv ( op , tmp ) ; } return op ;"
GCC,arc,341,"Predict the next statement of this code snippet:
 <s> iter . skip_subrtxes ( ) ; } else if ( GET_CODE ( * loc ) == PLUS && rtx_equal_p ( XEXP ( * loc , <NUM_LIT> ) , rgp ) ) iter . skip_subrtxes ( ) ; }"
GCC,arc,342,"Predict the next statement of this code snippet:
 <s> rtx addr = NULL_RTX ; x = SUBREG_REG ( x ) ; if ( REG_P ( x ) ) { int regno = REGNO ( x ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = reg_renumber [ regno ] ; if ( regno != - <NUM_LIT> ) return NO_REGS ; if ( reg_equiv_mem ( REGNO ( x ) ) ) { rtx mem = reg_equiv_mem ( REGNO ( x ) ) ; addr = find_replacement ( & XEXP ( mem , <NUM_LIT> ) ) ; } } else { gcc_assert ( MEM_P ( x ) ) ; addr = XEXP ( x , <NUM_LIT> ) ; addr = simplify_rtx ( addr ) ; } if ( addr && GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( ! RTX_OK_FOR_OFFSET_P ( mode , XEXP ( addr , <NUM_LIT> ) ) ) ) { switch ( mode ) { case E_QImode : sri -> icode = in_p ? CODE_FOR_reload_qi_load : CODE_FOR_reload_qi_store ;"
GCC,arc,343,"Predict the next statement of this code snippet:
 <s> machine = cfun -> machine ; if ( machine -> force_short_suffix >= <NUM_LIT> ) return machine -> force_short_suffix ; return ( get_attr_length ( insn ) & <NUM_LIT> ) != <NUM_LIT> ;"
GCC,arc,344,"Predict the next statement of this code snippet:
 <s> static int arc_verify_short ( rtx_insn * insn , int , int check_attr ) { enum attr_iscompact iscompact ; struct machine_function * machine ; if ( check_attr > <NUM_LIT> ) { iscompact = get_attr_iscompact ( insn ) ; if ( iscompact == ISCOMPACT_FALSE ) return <NUM_LIT> ; }"
GCC,arc,345,"Predict the next statement of this code snippet:
 <s> size = GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD ) return false ; addr = XEXP ( op , <NUM_LIT> ) ; if ( ! LEGITIMATE_SMALL_DATA_ADDRESS_P ( addr ) ) return false ; if ( ! short_p || size == <NUM_LIT> ) return true ; if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == SYMBOL_REF ) decl = SYMBOL_REF_DECL ( XEXP ( addr , <NUM_LIT> ) ) ; else if ( GET_CODE ( XEXP ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) decl = SYMBOL_REF_DECL ( XEXP ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( decl ) align = DECL_ALIGN ( decl ) ; align = align / BITS_PER_UNIT ; switch ( mode ) { case E_HImode : mask = <NUM_LIT> ; break ; default : mask = <NUM_LIT> ;"
GCC,arc,346,"Predict the next statement of this code snippet:
 <s> FOR_EACH_SUBRTX ( iter , array , op , ALL ) { const_rtx x = * iter ;"
GCC,arc,347,"Predict the next statement of this code snippet:
 <s> } case E_CC_Cmode : switch ( GET_CODE ( comparison ) ) { case LTU : return ARC_CC_C ; case GEU : return ARC_CC_NC ; default : gcc_unreachable ( ) ; } case E_CC_FP_GTmode : if ( TARGET_ARGONAUT_SET && TARGET_SPFP ) switch ( GET_CODE ( comparison ) ) { case GT : return ARC_CC_N ; case UNLE : return ARC_CC_P ; default : gcc_unreachable ( ) ; } else switch ( GET_CODE ( comparison ) ) { case GT : return ARC_CC_HI ; case UNLE : return ARC_CC_LS ; default : gcc_unreachable ( ) ; } case E_CC_FP_GEmode : switch ( GET_CODE ( comparison ) ) { case GE : return ARC_CC_HS ; case UNLT : return ARC_CC_LO ; default : gcc_unreachable ( ) ; } case E_CC_FP_UNEQmode : switch ( GET_CODE ( comparison ) ) { case UNEQ : return ARC_CC_EQ ; case LTGT : return ARC_CC_NE ; default : gcc_unreachable ( ) ; } case E_CC_FP_ORDmode : switch ( GET_CODE ( comparison ) ) { case UNORDERED : return ARC_CC_C ; case ORDERED : return ARC_CC_NC ; default : gcc_unreachable ( ) ; } case E_CC_FPXmode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; case UNORDERED : return ARC_CC_C ;"
GCC,arc,348,"Predict the next statement of this code snippet:
 <s> return ; } if ( ! ( last & <NUM_LIT> ) ) { warning ( <NUM_LIT> , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash = '-' ; if ( first > last ) { warning ( <NUM_LIT> , <STR_LIT> , str , dash + <NUM_LIT> ) ; return ; } while ( comma ) { * comma = ',' ; str = comma + <NUM_LIT> ; comma = strchr ( str , ',' ) ; if ( comma ) * comma = '\0' ; xreg = decode_reg_name ( str ) ; switch ( xreg ) { case <NUM_LIT> : blink = <NUM_LIT> ; break ; case <NUM_LIT> : lpcount = <NUM_LIT> ; break ; default : warning ( <NUM_LIT> , <STR_LIT> , str ) ; return ; }"
GCC,arc,349,"Predict the next statement of this code snippet:
 <s> } if ( ! strcmp ( dash + <NUM_LIT> , <STR_LIT> ) ) last = <NUM_LIT> ; else last = decode_reg_name ( dash + <NUM_LIT> ) ; if ( last < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } if ( ! ( last & <NUM_LIT> ) ) { warning ( <NUM_LIT> , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash = '-' ; if ( first > last ) { warning ( <NUM_LIT> , <STR_LIT> , str , dash + <NUM_LIT> ) ; return ; } while ( comma ) { * comma = ',' ; str = comma + <NUM_LIT> ; comma = strchr ( str , ',' ) ; if ( comma ) * comma = '\0' ; xreg = decode_reg_name ( str ) ; switch ( xreg ) { case <NUM_LIT> :"
GCC,arc,350,"Predict the next statement of this code snippet:
 <s> static void parse_mrgf_banked_regs_option ( const char * arg ) { long int val ; char * end_ptr ; errno = <NUM_LIT> ; val = strtol ( arg , & end_ptr , <NUM_LIT> ) ; if ( errno != <NUM_LIT> || * arg == '\0' || * end_ptr != '\0' || ( val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> ) ) { error ( <STR_LIT> <STR_LIT> , arg ) ;"
GCC,arc,351,"Predict the next statement of this code snippet:
 <s> val = strtol ( arg , & end_ptr , <NUM_LIT> ) ; if ( errno != <NUM_LIT> || * arg == '\0' || * end_ptr != '\0' || ( val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> ) ) { error ( <STR_LIT> <STR_LIT> , arg ) ;"
GCC,arc,352,"Predict the next statement of this code snippet:
 <s> tmp = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; } operands [ <NUM_LIT> ] = force_reg ( SImode , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_UNSPEC_VOLATILE ( VOIDmode , gen_rtvec ( <NUM_LIT> , operands [ <NUM_LIT> ] , tmp ) , VUNSPEC_ARC_SR ) ) ; return true ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) && arc_is_aux_reg_p ( operands [ <NUM_LIT> ] ) ) { if ( arc_get_aux_arg ( operands [ <NUM_LIT> ] , & auxr ) ) { tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp , GEN_INT ( auxr ) ) ; } else { tmp = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( tmp ) == SYMBOL_REF ) ; } gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( <NUM_LIT> , tmp ) , VUNSPEC_ARC_LR ) ) ) ; return true ; } } if ( ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ <NUM_LIT> ] , Pmode ) ) operands [ <NUM_LIT> ] = arc_rewrite_small_data ( operands [ <NUM_LIT> ] ) ; if ( mode == SImode && SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) { prepare_pic_move ( operands , SImode ) ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) != MEM && ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ <NUM_LIT> ] , Pmode ) ) { operands [ <NUM_LIT> ] = arc_rewrite_small_data ( operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , operands [ <NUM_LIT> ] ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ <NUM_LIT> ] , mode , pat ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } } } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! cse_not_expected ) {"
GCC,arc,353,"Predict the next statement of this code snippet:
 <s> if ( ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ <NUM_LIT> ] , Pmode ) ) operands [ <NUM_LIT> ] = arc_rewrite_small_data ( operands [ <NUM_LIT> ] ) ; if ( mode == SImode && SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) { prepare_pic_move ( operands , SImode ) ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) != MEM && ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ <NUM_LIT> ] , Pmode ) ) { operands [ <NUM_LIT> ] = arc_rewrite_small_data ( operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , operands [ <NUM_LIT> ] ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ <NUM_LIT> ] , mode , pat ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; }"
GCC,arc,354,"Predict the next statement of this code snippet:
 <s> const_rtx x = * iter ;"
GCC,arc,355,"Predict the next statement of this code snippet:
 <s> static rtx arc_builtin_setjmp_frame_value ( void ) {"
GCC,arc,356,"Predict the next statement of this code snippet:
 <s> if ( cfun -> machine -> frame_info . initialized ) return cfun -> machine -> frame_info . total_size ; frame_info = & cfun -> machine -> frame_info ; size = ARC_STACK_ALIGN ( get_frame_size ( ) ) ; var_size = size ; args_size = crtl -> outgoing_args_size ; reg_size = <NUM_LIT> ; gmask = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( arc_must_save_register ( regno , cfun ) ) { reg_size += UNITS_PER_WORD ; gmask |= <NUM_LIT> << regno ; } } if ( crtl -> calls_eh_return ) for ( regno = <NUM_LIT> ; EH_RETURN_DATA_REGNO ( regno ) != INVALID_REGNUM ; regno ++ ) { reg_size += UNITS_PER_WORD ; gmask |= <NUM_LIT> << regno ; } frame_info -> save_return_addr = ( ! crtl -> is_leaf || df_regs_ever_live_p ( RETURN_ADDR_REGNUM ) || crtl -> calls_eh_return ) ; if ( TARGET_MILLICODE_THUNK_SET && ! crtl -> calls_eh_return ) { if ( arc_compute_millicode_save_restore_regs ( gmask , frame_info ) ) frame_info -> save_return_addr = true ; } extra_size = <NUM_LIT> ; if ( arc_must_save_return_addr ( cfun ) ) extra_size = <NUM_LIT> ;"
GCC,arc,357,"Predict the next statement of this code snippet:
 <s> gmask |= <NUM_LIT> << regno ; } frame_info -> save_return_addr = ( ! crtl -> is_leaf || df_regs_ever_live_p ( RETURN_ADDR_REGNUM ) || crtl -> calls_eh_return ) ; if ( TARGET_MILLICODE_THUNK_SET && ! crtl -> calls_eh_return ) { if ( arc_compute_millicode_save_restore_regs ( gmask , frame_info ) ) frame_info -> save_return_addr = true ; } extra_size = <NUM_LIT> ; if ( arc_must_save_return_addr ( cfun ) ) extra_size = <NUM_LIT> ; if ( arc_frame_pointer_needed ( ) ) extra_size += <NUM_LIT> ; pretend_size = crtl -> args . pretend_args_size ; extra_plus_reg_size = extra_size + reg_size ; extra_plus_reg_size_aligned = ARC_STACK_ALIGN ( extra_plus_reg_size ) ; reg_size = extra_plus_reg_size_aligned - extra_size ; total_size = var_size + args_size + extra_size + pretend_size + reg_size ; gcc_assert ( total_size == ARC_STACK_ALIGN ( total_size ) ) ; frame_info -> total_size = total_size ; frame_info -> extra_size = extra_size ; frame_info -> pretend_size = pretend_size ;"
GCC,arc,358,"Predict the next statement of this code snippet:
 <s> for ( i = R16_REG ; i <= R25_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; } if ( TARGET_HS ) for ( regno = R1_REG ; regno < R32_REG ; regno += <NUM_LIT> ) arc_hard_regno_modes [ regno ] = S_MODES ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( i < ILINK1_REG ) { if ( ( TARGET_Q_CLASS || TARGET_RRQ_CLASS ) && ( ( i <= R3_REG ) || ( ( i >= R12_REG ) && ( i <= R15_REG ) ) ) ) arc_regno_reg_class [ i ] = ARCOMPACT16_REGS ; else arc_regno_reg_class [ i ] = GENERAL_REGS ; } else if ( i < LP_COUNT ) arc_regno_reg_class [ i ] = GENERAL_REGS ; else arc_regno_reg_class [ i ] = NO_REGS ; arc_regno_reg_class [ CC_REG ] = NO_REGS ; arc_regno_reg_class [ FRAME_POINTER_REGNUM ] = GENERAL_REGS ; arc_regno_reg_class [ ARG_POINTER_REGNUM ] = GENERAL_REGS ; if ( TARGET_DPFP ) for ( i = R40_REG ; i < R44_REG ; ++ i ) { arc_regno_reg_class [ i ] = DOUBLE_REGS ; if ( ! TARGET_ARGONAUT_SET ) CLEAR_HARD_REG_BIT ( reg_class_contents [ GENERAL_REGS ] , i ) ; } else { arc_regno_reg_class [ R40_REG ] = ALL_REGS ; arc_regno_reg_class [ R41_REG ] = ALL_REGS ; arc_regno_reg_class [ R42_REG ] = ALL_REGS ; arc_regno_reg_class [ R43_REG ] = ALL_REGS ; fixed_regs [ R40_REG ] = <NUM_LIT> ; fixed_regs [ R41_REG ] = <NUM_LIT> ; fixed_regs [ R42_REG ] = <NUM_LIT> ; fixed_regs [ R43_REG ] = <NUM_LIT> ; arc_hard_regno_modes [ R40_REG ] = <NUM_LIT> ; arc_hard_regno_modes [ R42_REG ] = <NUM_LIT> ; } if ( TARGET_SIMD_SET ) { gcc_assert ( ARC_FIRST_SIMD_VR_REG == <NUM_LIT> ) ; gcc_assert ( ARC_LAST_SIMD_VR_REG == <NUM_LIT> ) ; for ( i = ARC_FIRST_SIMD_VR_REG ; i <= ARC_LAST_SIMD_VR_REG ; i ++ ) arc_regno_reg_class [ i ] = SIMD_VR_REGS ; gcc_assert ( ARC_FIRST_SIMD_DMA_CONFIG_REG == <NUM_LIT> ) ; gcc_assert ( ARC_FIRST_SIMD_DMA_CONFIG_IN_REG == <NUM_LIT> ) ; gcc_assert ( ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG == <NUM_LIT> ) ; gcc_assert ( ARC_LAST_SIMD_DMA_CONFIG_REG == <NUM_LIT> ) ; for ( i = ARC_FIRST_SIMD_DMA_CONFIG_REG ; i <= ARC_LAST_SIMD_DMA_CONFIG_REG ; i ++ ) arc_regno_reg_class [ i ] = SIMD_DMA_CONFIG_REGS ; } arc_regno_reg_class [ PCL_REG ] = NO_REGS ;"
GCC,arc,359,"Predict the next statement of this code snippet:
 <s> static bool arc_enter_leave_p ( unsigned int gmask ) { int regno ; unsigned int rmask = <NUM_LIT> ; if ( ! gmask ) return false ; for ( regno = ENTER_LEAVE_START_REG ; regno <= ENTER_LEAVE_END_REG && ( gmask & ( <NUM_LIT> << regno ) ) ; regno ++ ) rmask |= <NUM_LIT> << regno ; if ( rmask ^ gmask ) return false ; return true ;"
GCC,arc,360,"Predict the next statement of this code snippet:
 <s> if ( ! gmask ) return false ; for ( regno = ENTER_LEAVE_START_REG ; regno <= ENTER_LEAVE_END_REG && ( gmask & ( <NUM_LIT> << regno ) ) ; regno ++ ) rmask |= <NUM_LIT> << regno ; if ( rmask ^ gmask ) return false ;"
GCC,arc,361,"Predict the next statement of this code snippet:
 <s> int can_trust_sp_p = ! cfun -> calls_alloca ; int first_offset ; bool restore_fp = arc_frame_pointer_needed ( ) && ! ARC_AUTOFP_IRQ_P ( fn_type ) ; bool restore_blink = arc_must_save_return_addr ( cfun ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) ; unsigned int gmask = cfun -> machine -> frame_info . gmask ; bool return_p = ! sibcall_p && fn_type == ARC_FUNCTION_NORMAL && ! cfun -> machine -> frame_info . pretend_size ; struct arc_frame_info * frame = & cfun -> machine -> frame_info ; if ( ARC_NAKED_P ( fn_type ) ) return ; size = arc_compute_frame_size ( ) ; size_to_deallocate = size ; first_offset = size - ( frame -> pretend_size + frame -> reg_size + frame -> extra_size ) ; if ( ! can_trust_sp_p ) gcc_assert ( arc_frame_pointer_needed ( ) ) ; if ( size ) emit_insn ( gen_blockage ( ) ) ; if ( TARGET_CODE_DENSITY && TARGET_CODE_DENSITY_FRAME && ! ARC_AUTOFP_IRQ_P ( fn_type ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) && ! ARC_INTERRUPT_P ( fn_type ) && arc_enter_leave_p ( gmask ) ) { size_to_deallocate -= arc_restore_callee_leave ( gmask , restore_blink , restore_fp , return_p , first_offset ) ; if ( return_p ) { gcc_assert ( size_to_deallocate == <NUM_LIT> ) ; return ; } } else if ( frame -> millicode_end_reg > <NUM_LIT> ) { size_to_deallocate -= arc_restore_callee_milli ( gmask , restore_blink , restore_fp , return_p , first_offset ) ; if ( return_p ) { gcc_assert ( size_to_deallocate == <NUM_LIT> ) ; return ; }"
GCC,arc,362,"Predict the next statement of this code snippet:
 <s> if ( TARGET_CODE_DENSITY && TARGET_CODE_DENSITY_FRAME && ! ARC_AUTOFP_IRQ_P ( fn_type ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) && ! ARC_INTERRUPT_P ( fn_type ) && arc_enter_leave_p ( gmask ) ) { size_to_deallocate -= arc_restore_callee_leave ( gmask , restore_blink , restore_fp , return_p , first_offset ) ; if ( return_p ) { gcc_assert ( size_to_deallocate == <NUM_LIT> ) ; return ; } } else if ( frame -> millicode_end_reg > <NUM_LIT> ) { size_to_deallocate -= arc_restore_callee_milli ( gmask , restore_blink , restore_fp , return_p , first_offset ) ; if ( return_p ) { gcc_assert ( size_to_deallocate == <NUM_LIT> ) ; return ; }"
GCC,arc,363,"Predict the next statement of this code snippet:
 <s> frame_size_to_allocate = size ; gcc_assert ( ! ( size == <NUM_LIT> && gmask ) ) ; if ( frame -> pretend_size != <NUM_LIT> ) first_offset = - frame -> pretend_size ; if ( ARC_AUTO_IRQ_P ( fn_type ) && ! ARC_FAST_INTERRUPT_P ( fn_type ) ) { frame_stack_add ( first_offset ) ; first_offset = <NUM_LIT> ; arc_dwarf_emit_irq_save_regs ( ) ; } save_blink = arc_must_save_return_addr ( cfun ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) ; save_fp = arc_frame_pointer_needed ( ) && ! ARC_AUTOFP_IRQ_P ( fn_type ) ; if ( TARGET_CODE_DENSITY && TARGET_CODE_DENSITY_FRAME && ! ARC_AUTOFP_IRQ_P ( fn_type ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) && ! ARC_INTERRUPT_P ( fn_type ) && arc_enter_leave_p ( gmask ) ) frame_size_to_allocate -= arc_save_callee_enter ( gmask , save_blink , save_fp , first_offset ) ; else if ( frame -> millicode_end_reg > <NUM_LIT> ) frame_size_to_allocate -= arc_save_callee_milli ( gmask , save_blink , save_fp , first_offset , frame -> reg_size ) ; else frame_size_to_allocate -= arc_save_callee_saves ( gmask , save_blink , save_fp , first_offset ) ; if ( frame_size_to_allocate > <NUM_LIT> ) frame_stack_add ( ( HOST_WIDE_INT ) <NUM_LIT> - frame_size_to_allocate ) ;"
GCC,arc,364,"Predict the next statement of this code snippet:
 <s> arc_punct_chars [ '&' ] = <NUM_LIT> ; arc_punct_chars [ '+' ] = <NUM_LIT> ; arc_punct_chars [ '_' ] = <NUM_LIT> ; if ( optimize > <NUM_LIT> && ! TARGET_NO_COND_EXEC ) { opt_pass * pass_arc_ifcvt_4 = make_pass_arc_ifcvt ( g ) ; struct register_pass_info arc_ifcvt4_info = { pass_arc_ifcvt_4 , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_AFTER } ; struct register_pass_info arc_ifcvt5_info = { pass_arc_ifcvt_4 -> clone ( ) , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_BEFORE } ; register_pass ( & arc_ifcvt4_info ) ; register_pass ( & arc_ifcvt5_info ) ; } if ( flag_delayed_branch ) { opt_pass * pass_arc_predicate_delay_insns = make_pass_arc_predicate_delay_insns ( g ) ;"
GCC,arc,365,"Predict the next statement of this code snippet:
 <s> arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_NOMPY_SET ) arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case ARC_TUNE_ARC700_4_2_XMAC : arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_NOMPY_SET ) arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case ARC_TUNE_ARC600 : if ( TARGET_MUL64_SET ) { arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } default : arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } if ( TARGET_NOMPY_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ! TARGET_DPFP && TARGET_DPFP_DISABLE_LRSR ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET && TARGET_DPFP_COMPACT_SET ) || ( TARGET_SPFP_FAST_SET && TARGET_SPFP_COMPACT_SET ) ) error ( <STR_LIT> ) ; if ( TARGET_SPFP_FAST_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET || TARGET_SPFP ) && TARGET_HARD_FLOAT ) error ( <STR_LIT> ) ; if ( flag_pic && TARGET_ARC600_FAMILY ) { warning ( <NUM_LIT> , <STR_LIT> , arc_cpu_string ) ; flag_pic = <NUM_LIT> ; } arc_init_reg_tables ( ) ; memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ; arc_punct_chars [ '*' ] = <NUM_LIT> ; arc_punct_chars [ '?' ] = <NUM_LIT> ; arc_punct_chars [ '!' ] = <NUM_LIT> ; arc_punct_chars [ '^' ] = <NUM_LIT> ; arc_punct_chars [ '&' ] = <NUM_LIT> ; arc_punct_chars [ '+' ] = <NUM_LIT> ; arc_punct_chars [ '_' ] = <NUM_LIT> ;"
GCC,arc,366,"Predict the next statement of this code snippet:
 <s> attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; } if ( TREE_CODE ( addr ) == COMPONENT_REF ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ;"
GCC,arc,367,"Predict the next statement of this code snippet:
 <s> if ( ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && CONSTANT_P ( x ) ) { return arc_legitimate_constant_p ( mode , x ) ; } if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == POST_INC ) && RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; if ( ( GET_CODE ( x ) == PRE_MODIFY || GET_CODE ( x ) == POST_MODIFY ) && GET_CODE ( XEXP ( ( x ) , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( ( x ) , <NUM_LIT> ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && legitimate_offset_address_p ( QImode , XEXP ( x , <NUM_LIT> ) , TARGET_AUTO_MODIFY_REG , strict ) ) return true ;"
GCC,arc,368,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT offset = INTVAL ( addend ) ; return ! ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; } if ( ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && CONSTANT_P ( x ) ) { return arc_legitimate_constant_p ( mode , x ) ; } if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == POST_INC ) && RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ;"
GCC,arc,369,"Predict the next statement of this code snippet:
 <s> bool firq_auto_save_p = ARC_FAST_INTERRUPT_P ( fn_type ) ; switch ( rgf_banked_register_count ) { case <NUM_LIT> : firq_auto_save_p &= ( regno < <NUM_LIT> ) ; break ; case <NUM_LIT> : firq_auto_save_p &= ( ( regno < <NUM_LIT> ) || ( ( regno > <NUM_LIT> ) && ( regno < <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> :"
GCC,arc,370,"Predict the next statement of this code snippet:
 <s> reg = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset + nregs * UNITS_PER_WORD ) ) ; RTX_FRAME_RELATED_P ( reg ) = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( restore_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( reg , mem ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; } for ( regno = start_reg ; regno <= end_reg ; regno ++ , indx ++ , off -= UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( reg , mem ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; } if ( restore_fp ) { mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( hard_frame_pointer_rtx , mem ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; } gcc_assert ( off == <NUM_LIT> ) ; if ( return_p ) { insn = emit_jump_insn ( insn ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else insn = frame_insn ( insn ) ; add_reg_note ( insn , REG_INC , stack_pointer_rtx ) ; if ( restore_fp ) { add_reg_note ( insn , REG_CFA_RESTORE , hard_frame_pointer_rtx ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , offset + nregs * UNITS_PER_WORD ) ) ; } else { add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , nregs * UNITS_PER_WORD ) ) ) ;"
GCC,arc,371,"Predict the next statement of this code snippet:
 <s> regno <= end_reg ; regno ++ , indx ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( reg , mem ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; } for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( ( gmask & ( <NUM_LIT> << regno ) ) == <NUM_LIT> ) continue ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; rtx tmp = frame_move_inc ( reg , mem , stack_pointer_rtx , <NUM_LIT> ) ; add_reg_note ( tmp , REG_CFA_RESTORE , reg ) ; off += UNITS_PER_WORD ; } if ( return_p ) { reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; frame_insn ( gen_rtx_SET ( reg , GEN_INT ( off ) ) ) ; frame_allocated += off ; insn = emit_jump_insn ( insn ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else insn = frame_insn ( insn ) ; for ( regno = start_reg ; regno <= end_reg ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } if ( restore_blink && ! return_p ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; insn = frame_insn ( gen_rtx_SET ( reg , mem ) ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ;"
GCC,arc,372,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT offs = cfun -> machine -> frame_info . reg_size ; bool early_blink_restore ; if ( arc_frame_pointer_needed ( ) && offset ) { frame_move ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; frame_deallocated += offset ; offset = <NUM_LIT> ; } if ( restore_fp ) { gcc_assert ( offset == <NUM_LIT> ) ; frame_deallocated += frame_restore_reg ( hard_frame_pointer_rtx , <NUM_LIT> ) ; } if ( offset ) { frame_stack_add ( offset ) ; frame_deallocated += offset ; offset = <NUM_LIT> ; } early_blink_restore = restore_blink && ! optimize_size && offs ; if ( early_blink_restore ) { rtx addr = plus_constant ( Pmode , stack_pointer_rtx , offs ) ; reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx insn = frame_move_inc ( reg , gen_frame_mem ( Pmode , addr ) , stack_pointer_rtx , NULL_RTX ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; restore_blink = false ; } if ( gmask ) for ( int i = <NUM_LIT> ; i <= GMASK_LEN ; i ++ ) { machine_mode restore_mode = SImode ; if ( TARGET_LL64 && ( ( i % <NUM_LIT> ) == <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << ( i + <NUM_LIT> ) ) ) != <NUM_LIT> ) ) restore_mode = DImode ; else if ( ( gmask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) continue ; reg = gen_rtx_REG ( restore_mode , i ) ; offs = <NUM_LIT> ; switch ( restore_mode ) { case E_DImode : if ( ( GMASK_LEN - __builtin_clz ( gmask ) ) == ( i + <NUM_LIT> ) && early_blink_restore ) offs = <NUM_LIT> ; break ; case E_SImode : if ( ( GMASK_LEN - __builtin_clz ( gmask ) ) == i && early_blink_restore ) offs = <NUM_LIT> ; break ; default : offs = <NUM_LIT> ; } frame_deallocated += frame_restore_reg ( reg , offs ) ;"
GCC,arc,373,"Predict the next statement of this code snippet:
 <s> gcc_assert ( offset == <NUM_LIT> ) ; frame_deallocated += frame_restore_reg ( hard_frame_pointer_rtx , <NUM_LIT> ) ; } if ( offset ) { frame_stack_add ( offset ) ; frame_deallocated += offset ; offset = <NUM_LIT> ; } early_blink_restore = restore_blink && ! optimize_size && offs ; if ( early_blink_restore ) { rtx addr = plus_constant ( Pmode , stack_pointer_rtx , offs ) ; reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx insn = frame_move_inc ( reg , gen_frame_mem ( Pmode , addr ) , stack_pointer_rtx , NULL_RTX ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; restore_blink = false ; } if ( gmask ) for ( int i = <NUM_LIT> ; i <= GMASK_LEN ; i ++ ) { machine_mode restore_mode = SImode ; if ( TARGET_LL64 && ( ( i % <NUM_LIT> ) == <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << ( i + <NUM_LIT> ) ) ) != <NUM_LIT> ) ) restore_mode = DImode ; else if ( ( gmask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) continue ; reg = gen_rtx_REG ( restore_mode , i ) ;"
GCC,arc,374,"Predict the next statement of this code snippet:
 <s> if ( ( fn_type & ( ARC_FUNCTION_ILINK1 | ARC_FUNCTION_FIRQ ) ) != <NUM_LIT> ) regno = ILINK1_REG ; else if ( ( fn_type & ARC_FUNCTION_ILINK2 ) != <NUM_LIT> ) regno = ILINK2_REG ; else gcc_unreachable ( ) ; } else if ( ARC_NORMAL_P ( fn_type ) || ARC_NAKED_P ( fn_type ) ) regno = RETURN_ADDR_REGNUM ;"
GCC,arc,375,"Predict the next statement of this code snippet:
 <s> else gcc_unreachable ( ) ; } else if ( ARC_NORMAL_P ( fn_type ) || ARC_NAKED_P ( fn_type ) ) regno = RETURN_ADDR_REGNUM ;"
GCC,arc,376,"Predict the next statement of this code snippet:
 <s> int start_reg = ENTER_LEAVE_START_REG ; int end_reg = ENTER_LEAVE_END_REG ; int regno , indx , off , nregs ; rtx insn , reg , mem ; int frame_allocated = <NUM_LIT> ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( <NUM_LIT> << regno ) ) ; ) regno ++ ; end_reg = regno - <NUM_LIT> ; nregs = end_reg - start_reg + <NUM_LIT> ; nregs += save_blink ? <NUM_LIT> : <NUM_LIT> ; nregs += save_fp ? <NUM_LIT> : <NUM_LIT> ; if ( offset ) frame_stack_add ( offset ) ; insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + ( save_fp ? <NUM_LIT> : <NUM_LIT> ) + <NUM_LIT> ) ) ; indx = <NUM_LIT> ; reg = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - nregs * UNITS_PER_WORD ) ) ; RTX_FRAME_RELATED_P ( reg ) = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ;"
GCC,arc,377,"Predict the next statement of this code snippet:
 <s> int end_reg = <NUM_LIT> ; int regno , indx , off , nregs ; rtx insn , reg , mem ; int frame_allocated = <NUM_LIT> ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( <NUM_LIT> << regno ) ) ; ) regno ++ ; end_reg = regno - <NUM_LIT> ; nregs = end_reg - start_reg + <NUM_LIT> ; gcc_assert ( end_reg > <NUM_LIT> ) ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = <NUM_LIT> ; } if ( reg_size || offset ) { frame_stack_add ( offset - reg_size ) ; frame_allocated += nregs * UNITS_PER_WORD - offset ; offset = <NUM_LIT> ; } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + <NUM_LIT> ) ) ; indx = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , nregs ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ; for ( regno = start_reg , indx = <NUM_LIT> , off = <NUM_LIT> ; regno <= end_reg ; regno ++ , indx ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ;"
GCC,arc,378,"Predict the next statement of this code snippet:
 <s> RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; } insn = frame_insn ( insn ) ; for ( regno = start_reg , off = <NUM_LIT> ; regno <= end_reg ; regno ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } if ( arc_must_save_return_addr ( cfun ) ) { emit_insn ( gen_rtx_SET ( gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_MEM ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , reg_size ) ) ) ) ; } for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) {"
GCC,arc,379,"Predict the next statement of this code snippet:
 <s> if ( gmask ) for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { machine_mode save_mode = SImode ; if ( TARGET_LL64 && ( ( i - <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ) ) { save_mode = DImode ; -- i ; } else if ( ( gmask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) continue ; reg = gen_rtx_REG ( save_mode , i ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = <NUM_LIT> ; } if ( save_fp ) {"
GCC,arc,380,"Predict the next statement of this code snippet:
 <s> machine_mode save_mode = SImode ; if ( TARGET_LL64 && ( ( i - <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ) ) { save_mode = DImode ; -- i ; }"
GCC,arc,381,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( op ) != MEM ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; size = GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD ) return false ; addr = XEXP ( op , <NUM_LIT> ) ; if ( ! legitimate_small_data_address_p ( addr ) ) return false ; if ( ! short_p || size == <NUM_LIT> ) return true ; align = get_symbol_alignment ( addr ) ; switch ( mode ) { case E_HImode : mask = <NUM_LIT> ; break ; default :"
GCC,arc,382,"Predict the next statement of this code snippet:
 <s> case <NUM_LIT> : if ( INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != <NUM_LIT> ) return false ; default : return false ; } if ( RTX_OK_FOR_BASE_P ( XEXP ( op , <NUM_LIT> ) , ( strict ) ) ) return true ; if ( flag_pic ) { if ( CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) return true ; return false ; } if ( legitimate_small_data_address_p ( op ) ) return false ; if ( CONSTANT_P ( XEXP ( op , <NUM_LIT> ) ) ) return true ; return false ;"
GCC,arc,383,"Predict the next statement of this code snippet:
 <s> switch ( GET_CODE ( x ) ) { case CONST : return legitimate_small_data_address_p ( XEXP ( x , <NUM_LIT> ) ) ; case SYMBOL_REF : return SYMBOL_REF_SMALL_P ( x ) ; case PLUS : { bool p0 = ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SYMBOL_REF ) && SYMBOL_REF_SMALL_P ( XEXP ( x , <NUM_LIT> ) ) ; bool p1 = CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) <= g_switch_value ) ; return p0 && p1 ; } default :"
GCC,arc,384,"Predict the next statement of this code snippet:
 <s> static bool legitimate_small_data_address_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : return legitimate_small_data_address_p ( XEXP ( x , <NUM_LIT> ) ) ; case SYMBOL_REF : return SYMBOL_REF_SMALL_P ( x ) ; case PLUS : { bool p0 = ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SYMBOL_REF ) && SYMBOL_REF_SMALL_P ( XEXP ( x , <NUM_LIT> ) ) ; bool p1 = CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) <= g_switch_value ) ; return p0 && p1 ; } default : return false ; }"
GCC,arc,385,"Predict the next statement of this code snippet:
 <s> } if ( MEM_P ( operands [ <NUM_LIT> ] ) && arc_is_aux_reg_p ( operands [ <NUM_LIT> ] ) ) { if ( arc_get_aux_arg ( operands [ <NUM_LIT> ] , & auxr ) ) { tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp , GEN_INT ( auxr ) ) ; } else { tmp = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( tmp ) == SYMBOL_REF ) ; } gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( <NUM_LIT> , tmp ) , VUNSPEC_ARC_LR ) ) ) ; return true ; } } if ( mode == SImode && SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) { prepare_pic_move ( operands , SImode ) ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ <NUM_LIT> ] , mode , pat ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } } } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ;"
GCC,arc,386,"Predict the next statement of this code snippet:
 <s> return GEN_FCN ( icode ) ( arg [ <NUM_LIT> ] ) ; case <NUM_LIT> : return GEN_FCN ( icode ) ( arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] ) ; case <NUM_LIT> :"
GCC,arc,387,"Predict the next statement of this code snippet:
 <s> return GEN_FCN ( icode ) ( arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] ) ; case <NUM_LIT> : return GEN_FCN ( icode ) ( arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] ) ; case <NUM_LIT> : return GEN_FCN ( icode ) ( arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] ) ; case <NUM_LIT> : return GEN_FCN ( icode ) ( arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] ) ; default : gcc_unreachable ( ) ;"
GCC,arc,388,"Predict the next statement of this code snippet:
 <s> static int arc600_corereg_hazard ( rtx_insn * pred , rtx_insn * succ ) { if ( ! TARGET_ARC600 ) return <NUM_LIT> ; if ( GET_CODE ( PATTERN ( pred ) ) == SEQUENCE ) pred = as_a < rtx_sequence * > ( PATTERN ( pred ) ) -> insn ( <NUM_LIT> ) ; if ( GET_CODE ( PATTERN ( succ ) ) == SEQUENCE ) succ = as_a < rtx_sequence * > ( PATTERN ( succ ) ) -> insn ( <NUM_LIT> ) ; if ( recog_memoized ( pred ) == CODE_FOR_mulsi_600 || recog_memoized ( pred ) == CODE_FOR_umul_600 || recog_memoized ( pred ) == CODE_FOR_mac_600 || recog_memoized ( pred ) == CODE_FOR_mul64_600 || recog_memoized ( pred ) == CODE_FOR_mac64_600 || recog_memoized ( pred ) == CODE_FOR_umul64_600 || recog_memoized ( pred ) == CODE_FOR_umac64_600 ) return <NUM_LIT> ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( pred ) , NONCONST ) { const_rtx x = * iter ; switch ( GET_CODE ( x ) ) { case SET : case POST_INC : case POST_DEC : case PRE_INC : case PRE_DEC : break ; default : continue ; } rtx dest = XEXP ( x , <NUM_LIT> ) ; if ( REG_P ( dest ) && REGNO ( dest ) >= <NUM_LIT> && REGNO ( dest ) < <NUM_LIT> && ( refers_to_regno_p ( REGNO ( dest ) , REGNO ( dest ) + ( GET_MODE_SIZE ( GET_MODE ( dest ) ) + <NUM_LIT> ) / <NUM_LIT> , PATTERN ( succ ) , <NUM_LIT> ) ) ) return <NUM_LIT> ;"
GCC,arc,389,"Predict the next statement of this code snippet:
 <s> insn = NEXT_INSN ( insn ) ; if ( insn == <NUM_LIT> || ( active_insn_p ( insn ) && NONDEBUG_INSN_P ( insn ) && ! NOTE_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != UNSPEC_VOLATILE && GET_CODE ( PATTERN ( insn ) ) != PARALLEL ) ) break ; }"
GCC,arc,390,"Predict the next statement of this code snippet:
 <s> rtx plus1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) != MULT || ! CONST_INT_P ( XEXP ( plus0 , <NUM_LIT> ) ) || ( INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> && INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> ) ) ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return ( ! RTX_OK_FOR_OFFSET_P ( SImode , plus1 ) ? COSTS_N_INSNS ( <NUM_LIT> ) : speed ? <NUM_LIT> : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_O ( plus1 ) ) ? <NUM_LIT> : <NUM_LIT> ) ; case REG : return ( speed < <NUM_LIT> ? <NUM_LIT> : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_Rcq ( plus1 ) ) ? <NUM_LIT> : <NUM_LIT> ) ; case CONST : case SYMBOL_REF : case LABEL_REF : return COSTS_N_INSNS ( <NUM_LIT> ) ; default : break ; } break ;"
GCC,arc,391,"Predict the next statement of this code snippet:
 <s> arc_jli_section * sec = arc_jli_sections , * new_section ; tree decl = SYMBOL_REF_DECL ( pat ) ; if ( ! pat ) return ; if ( decl ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return ; } name = XSTR ( pat , <NUM_LIT> ) ; while ( sec != NULL ) { if ( strcmp ( name , sec -> name ) == <NUM_LIT> ) return ; sec = sec -> next ; } new_section = ( arc_jli_section * ) xmalloc ( sizeof ( arc_jli_section ) ) ;"
GCC,arc,392,"Predict the next statement of this code snippet:
 <s> if ( strcmp ( name , sec -> name ) == <NUM_LIT> ) return ; sec = sec -> next ; } new_section = ( arc_jli_section * ) xmalloc ( sizeof ( arc_jli_section ) ) ; gcc_assert ( new_section != NULL ) ; new_section -> name = name ;"
GCC,arc,393,"Predict the next statement of this code snippet:
 <s> void arc_adjust_reg_alloc_order ( void ) { const int arc_default_alloc_order [ ] = REG_ALLOC_ORDER ; memcpy ( reg_alloc_order , arc_default_alloc_order , sizeof ( reg_alloc_order ) ) ;"
GCC,arc,394,"Predict the next statement of this code snippet:
 <s> void arc_adjust_reg_alloc_order ( void ) {"
GCC,arc,395,"Predict the next statement of this code snippet:
 <s> static bool arc_allocate_stack_slots_for_args ( void ) {"
GCC,arc,396,"Predict the next statement of this code snippet:
 <s> return ! ARC_NAKED_P ( fn_type ) ;"
GCC,arc,397,"Predict the next statement of this code snippet:
 <s> int bytes = arg . promoted_size_in_bytes ( ) ; int words = ( bytes + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; int arg_num = * cum ; int ret ; arg_num = ROUND_ADVANCE_CUM ( arg_num , arg . mode , arg . type ) ; ret = GPR_REST_ARG_REGS ( arg_num ) ; ret = ( ret >= words ? <NUM_LIT> : ret * UNITS_PER_WORD ) ;"
GCC,arc,398,"Predict the next statement of this code snippet:
 <s> return <NUM_LIT> ; case SET : return arc_asm_insn_p ( SET_SRC ( x ) ) ; case PARALLEL : j = <NUM_LIT> ; for ( i = XVECLEN ( x , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) j += arc_asm_insn_p ( XVECEXP ( x , <NUM_LIT> , i ) ) ; if ( j > <NUM_LIT> ) return <NUM_LIT> ; break ;"
GCC,arc,399,"Predict the next statement of this code snippet:
 <s> for ( i = XVECLEN ( x , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) j += arc_asm_insn_p ( XVECEXP ( x , <NUM_LIT> , i ) ) ; if ( j > <NUM_LIT> ) return <NUM_LIT> ; break ;"
GCC,arc,400,"Predict the next statement of this code snippet:
 <s> if ( globalize_p ) ( * targetm . asm_out . globalize_label ) ( stream , name ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( ( align ) / BITS_PER_UNIT ) ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , <STR_LIT> ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name , size ) ; ASM_OUTPUT_LABEL ( stream , name ) ; if ( size != <NUM_LIT> ) ASM_OUTPUT_SKIP ( stream , size ) ;"
GCC,arc,401,"Predict the next statement of this code snippet:
 <s> static void arc_asm_trampoline_template ( FILE * f ) { asm_fprintf ( f , <STR_LIT> , ARC_TEMP_SCRATCH_REG ) ; asm_fprintf ( f , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] ) ; asm_fprintf ( f , <STR_LIT> , ARC_TEMP_SCRATCH_REG ) ; assemble_aligned_integer ( UNITS_PER_WORD , const0_rtx ) ;"
GCC,arc,402,"Predict the next statement of this code snippet:
 <s> asm_fprintf ( f , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] ) ; asm_fprintf ( f , <STR_LIT> , ARC_TEMP_SCRATCH_REG ) ; assemble_aligned_integer ( UNITS_PER_WORD , const0_rtx ) ; assemble_aligned_integer ( UNITS_PER_WORD , const0_rtx ) ;"
GCC,arc,403,"Predict the next statement of this code snippet:
 <s> static int arc_attr_type ( rtx_insn * insn ) { if ( NONJUMP_INSN_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) : JUMP_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == ADDR_VEC || GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC ) : ! CALL_P ( insn ) ) return - <NUM_LIT> ; return get_attr_type ( insn ) ;"
GCC,arc,404,"Predict the next statement of this code snippet:
 <s> static int arc_attr_type ( rtx_insn * insn ) { if ( NONJUMP_INSN_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) : JUMP_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == ADDR_VEC || GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC ) : ! CALL_P ( insn ) ) return - <NUM_LIT> ; return get_attr_type ( insn ) ;"
GCC,arc,405,"Predict the next statement of this code snippet:
 <s> static unsigned int arc_autovectorize_vector_modes ( vector_modes * modes , bool ) { if ( TARGET_PLUS_QMACW ) { modes -> quick_push ( V4HImode ) ; modes -> quick_push ( V2HImode ) ; }"
GCC,arc,406,"Predict the next statement of this code snippet:
 <s> return ! optimize_size && arc_reorg_in_progress ;"
GCC,arc,407,"Predict the next statement of this code snippet:
 <s> if ( ! arc_tls_symbol ) arc_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; emit_move_insn ( arg , ti ) ; fn = gen_rtx_MEM ( SImode , arc_tls_symbol ) ; insn = emit_call_insn ( gen_call_value ( ret , fn , const0_rtx ) ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , ret ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , arg ) ; return ret ;"
GCC,arc,408,"Predict the next statement of this code snippet:
 <s> emit_move_insn ( arg , ti ) ; fn = gen_rtx_MEM ( SImode , arc_tls_symbol ) ; insn = emit_call_insn ( gen_call_value ( ret , fn , const0_rtx ) ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , ret ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , arg ) ;"
GCC,arc,409,"Predict the next statement of this code snippet:
 <s> return ! arc_legitimate_constant_p ( mode , x ) ;"
GCC,arc,410,"Predict the next statement of this code snippet:
 <s> static bool arc_cannot_substitute_mem_equiv_p ( rtx ) {"
GCC,arc,411,"Predict the next statement of this code snippet:
 <s> return ( ( to == HARD_FRAME_POINTER_REGNUM ) || ( to == STACK_POINTER_REGNUM ) ) ;"
GCC,arc,412,"Predict the next statement of this code snippet:
 <s> return ( ( to == HARD_FRAME_POINTER_REGNUM ) || ( to == STACK_POINTER_REGNUM ) ) ;"
GCC,arc,413,"Predict the next statement of this code snippet:
 <s> if ( CROSSING_JUMP_P ( followee ) ) switch ( get_attr_type ( u . r ) ) { case TYPE_BRANCH : if ( get_attr_length ( u . r ) != <NUM_LIT> ) break ; case TYPE_BRCC : case TYPE_BRCC_NO_DELAY_SLOT :"
GCC,arc,414,"Predict the next statement of this code snippet:
 <s> if ( loop_depth > <NUM_LIT> || ! entered_at_top ) return false ; if ( arc_lpcwidth != <NUM_LIT> && ( wi :: gtu_p ( iterations_max , ( ( <NUM_LIT> << arc_lpcwidth ) - <NUM_LIT> ) ) || wi :: eq_p ( iterations_max , <NUM_LIT> ) ) ) return false ;"
GCC,arc,415,"Predict the next statement of this code snippet:
 <s> bool arc_can_use_return_insn ( void ) {"
GCC,arc,416,"Predict the next statement of this code snippet:
 <s> int reverse = <NUM_LIT> ; int seeking_return = <NUM_LIT> ; rtx_insn * start_insn = insn ; enum attr_type jump_insn_type ; if ( optimize < <NUM_LIT> || TARGET_NO_COND_EXEC ) return ; if ( ! INSN_P ( insn ) ) return ; body = PATTERN ( insn ) ; if ( state -> state == <NUM_LIT> ) { if ( insn == state -> target_insn ) { state -> target_insn = NULL ; state -> state = <NUM_LIT> ; } return ; } if ( state -> state == <NUM_LIT> ) { if ( simplejump_p ( insn ) ) { start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == BARRIER ) { start_insn = next_nonnote_insn ( start_insn ) ; } if ( GET_CODE ( start_insn ) == CODE_LABEL && CODE_LABEL_NUMBER ( start_insn ) == state -> target_label && LABEL_NUSES ( start_insn ) == <NUM_LIT> ) reverse = TRUE ; else return ; } else if ( GET_CODE ( body ) == SIMPLE_RETURN ) { start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == BARRIER ) start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == CODE_LABEL && CODE_LABEL_NUMBER ( start_insn ) == state -> target_label && LABEL_NUSES ( start_insn ) == <NUM_LIT> ) { reverse = TRUE ; seeking_return = <NUM_LIT> ; } else return ; } else return ; } if ( GET_CODE ( insn ) != JUMP_INSN || GET_CODE ( PATTERN ( insn ) ) == ADDR_VEC || GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC ) return ; jump_insn_type = get_attr_type ( insn ) ; if ( jump_insn_type == TYPE_BRCC || jump_insn_type == TYPE_BRCC_NO_DELAY_SLOT || jump_insn_type == TYPE_LOOP_END || ( jump_insn_type == TYPE_CALL && ! get_attr_predicable ( insn ) ) ) return ; if ( GET_CODE ( body ) == PARALLEL && XVECLEN ( body , <NUM_LIT> ) > <NUM_LIT> ) body = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( reverse || ( GET_CODE ( body ) == SET && GET_CODE ( SET_DEST ( body ) ) == PC && GET_CODE ( SET_SRC ( body ) ) == IF_THEN_ELSE ) ) { int insns_skipped = <NUM_LIT> , fail = FALSE , succeed = FALSE ; int then_not_else = TRUE ; int next_must_be_target_label_p ; rtx_insn * this_insn = start_insn ;"
GCC,arc,417,"Predict the next statement of this code snippet:
 <s> static void arc_ccfsm_at_label ( const char * prefix , int num , struct arc_ccfsm * state ) {"
GCC,arc,418,"Predict the next statement of this code snippet:
 <s> bool arc_ccfsm_branch_deleted_p ( void ) { return ARC_CCFSM_BRANCH_DELETED_P ( & arc_ccfsm_current ) ;"
GCC,arc,419,"Predict the next statement of this code snippet:
 <s> bool arc_ccfsm_branch_deleted_p ( void ) { return ARC_CCFSM_BRANCH_DELETED_P ( & arc_ccfsm_current ) ;"
GCC,arc,420,"Predict the next statement of this code snippet:
 <s> bool arc_ccfsm_cond_exec_p ( void ) {"
GCC,arc,421,"Predict the next statement of this code snippet:
 <s> enum attr_type type ; if ( LABEL_P ( insn ) ) arc_ccfsm_at_label ( <STR_LIT> , CODE_LABEL_NUMBER ( insn ) , state ) ;"
GCC,arc,422,"Predict the next statement of this code snippet:
 <s> if ( ARC_CCFSM_BRANCH_DELETED_P ( state ) ) ARC_CCFSM_RECORD_BRANCH_DELETED ( state ) ; else { rtx src = SET_SRC ( PATTERN ( insn ) ) ; arc_ccfsm_record_condition ( XEXP ( src , <NUM_LIT> ) , XEXP ( src , <NUM_LIT> ) == pc_rtx , insn , state ) ; } }"
GCC,arc,423,"Predict the next statement of this code snippet:
 <s> ARC_CCFSM_RECORD_BRANCH_DELETED ( & arc_ccfsm_current ) ;"
GCC,arc,424,"Predict the next statement of this code snippet:
 <s> if ( ! as_a < rtx_insn * > ( insn ) -> deleted ( ) && INSN_ANNULLED_BRANCH_P ( jump ) && ( TARGET_AT_DBR_CONDEXEC || INSN_FROM_TARGET_P ( insn ) ) ) { state -> cond = cond ; state -> cc = get_arc_condition_code ( cond ) ; if ( ! reverse ) arc_ccfsm_current . cc = ARC_INVERSE_CONDITION_CODE ( state -> cc ) ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) gcc_assert ( ( INSN_FROM_TARGET_P ( insn ) ? ARC_INVERSE_CONDITION_CODE ( state -> cc ) : state -> cc ) == get_arc_condition_code ( XEXP ( pat , <NUM_LIT> ) ) ) ; else state -> state = <NUM_LIT> ;"
GCC,arc,425,"Predict the next statement of this code snippet:
 <s> if ( ! reverse ) arc_ccfsm_current . cc = ARC_INVERSE_CONDITION_CODE ( state -> cc ) ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) gcc_assert ( ( INSN_FROM_TARGET_P ( insn ) ? ARC_INVERSE_CONDITION_CODE ( state -> cc ) : state -> cc ) == get_arc_condition_code ( XEXP ( pat , <NUM_LIT> ) ) ) ; else state -> state = <NUM_LIT> ; }"
GCC,arc,426,"Predict the next statement of this code snippet:
 <s> bool arc_check_ior_const ( HOST_WIDE_INT ival ) { unsigned int mask = ( unsigned int ) ( ival & <NUM_LIT> ) ; if ( UNSIGNED_INT6 ( ival ) || IS_POWEROF2_P ( mask ) ) return false ; if ( __builtin_popcount ( mask ) <= <NUM_LIT> ) return true ;"
GCC,arc,427,"Predict the next statement of this code snippet:
 <s> if ( load_p == <NUM_LIT> ) { if ( len < <NUM_LIT> || len > <NUM_LIT> ) return <NUM_LIT> ; load_p = <NUM_LIT> ; } else { rtx elt = XVECEXP ( op , <NUM_LIT> , -- len ) ; if ( GET_CODE ( elt ) != CLOBBER || ! REG_P ( XEXP ( elt , <NUM_LIT> ) ) || REGNO ( XEXP ( elt , <NUM_LIT> ) ) != RETURN_ADDR_REGNUM || len < <NUM_LIT> || len > <NUM_LIT> ) return <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < len ; i ++ ) { rtx elt = XVECEXP ( op , <NUM_LIT> , i + offset ) ; rtx reg , mem , addr ; if ( GET_CODE ( elt ) != SET ) return <NUM_LIT> ; mem = XEXP ( elt , load_p ) ; reg = XEXP ( elt , <NUM_LIT> - load_p ) ; if ( ! REG_P ( reg ) || REGNO ( reg ) != <NUM_LIT> + i || ! MEM_P ( mem ) ) return <NUM_LIT> ;"
GCC,arc,428,"Predict the next statement of this code snippet:
 <s> ival = ival & <NUM_LIT> ; if ( SIGNED_INT12 ( ival ) ) return false ; if ( ( ival & ~ <NUM_LIT> ) == <NUM_LIT> ) return true ; if ( IS_POWEROF2_P ( ival + <NUM_LIT> ) ) return true ; if ( ! TARGET_BARREL_SHIFTER ) return false ; if ( ( ( ival >> ( __builtin_ffs ( ival ) - <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return true ; if ( ( ival & ~ <NUM_LIT> ) == <NUM_LIT> ) return true ;"
GCC,arc,429,"Predict the next statement of this code snippet:
 <s> if ( ( ival & ~ <NUM_LIT> ) == <NUM_LIT> ) return true ; if ( ( ival & ~ <NUM_LIT> ) == <NUM_LIT> ) return true ; if ( ( ival & ~ <NUM_LIT> ) == <NUM_LIT> ) return true ;"
GCC,arc,430,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT len = XVECLEN ( op , <NUM_LIT> ) ; unsigned int regno , i , start ; unsigned int memp = push_p ? <NUM_LIT> : <NUM_LIT> ; rtx elt ; if ( len <= <NUM_LIT> ) return false ; start = <NUM_LIT> ; elt = XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ; if ( ! push_p && GET_CODE ( elt ) == RETURN ) start = <NUM_LIT> ; for ( i = start , regno = ENTER_LEAVE_START_REG ; i < len ; i ++ , regno ++ ) { rtx elt = XVECEXP ( op , <NUM_LIT> , i ) ; rtx reg , mem , addr ; if ( GET_CODE ( elt ) != SET ) return false ; mem = XEXP ( elt , memp ) ; reg = XEXP ( elt , <NUM_LIT> - memp ) ; if ( ! REG_P ( reg ) || ! MEM_P ( mem ) ) return false ; if ( REGNO ( reg ) == RETURN_ADDR_REGNUM && i == start ) regno = <NUM_LIT> ; else if ( REGNO ( reg ) == HARD_FRAME_POINTER_REGNUM ) ++ i ; else if ( REGNO ( reg ) != regno ) return false ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( stack_pointer_rtx , XEXP ( addr , <NUM_LIT> ) ) || ! CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) return false ;"
GCC,arc,431,"Predict the next statement of this code snippet:
 <s> void arc_clear_unalign ( void ) {"
GCC,arc,432,"Predict the next statement of this code snippet:
 <s> void arc_clear_unalign ( void ) {"
GCC,arc,433,"Predict the next statement of this code snippet:
 <s> reg_size += UNITS_PER_WORD ; gmask |= <NUM_LIT> << regno ; } frame_info -> save_return_addr = ( ! crtl -> is_leaf || df_regs_ever_live_p ( RETURN_ADDR_REGNUM ) || crtl -> calls_eh_return ) ; if ( TARGET_MILLICODE_THUNK_SET && ! ARC_INTERRUPT_P ( fn_type ) && ! crtl -> calls_eh_return ) { if ( arc_compute_millicode_save_restore_regs ( gmask , frame_info ) ) frame_info -> save_return_addr = true ; } if ( arc_lpcwidth != <NUM_LIT> && arc_must_save_register ( LP_COUNT , cfun , true ) ) reg_size += UNITS_PER_WORD * <NUM_LIT> ; if ( arc_must_save_register ( TARGET_BIG_ENDIAN ? R41_REG : R40_REG , cfun , TARGET_DPFP ) ) reg_size += UNITS_PER_WORD * <NUM_LIT> ; if ( arc_must_save_register ( TARGET_BIG_ENDIAN ? R43_REG : R42_REG , cfun , TARGET_DPFP ) ) reg_size += UNITS_PER_WORD * <NUM_LIT> ; if ( arc_must_save_register ( R58_REG , cfun , true ) ) reg_size += UNITS_PER_WORD * <NUM_LIT> ; extra_size = <NUM_LIT> ; if ( arc_must_save_return_addr ( cfun ) ) extra_size = <NUM_LIT> ; if ( arc_frame_pointer_needed ( ) && ! ARC_AUTOFP_IRQ_P ( fn_type ) ) extra_size += <NUM_LIT> ; pretend_size = crtl -> args . pretend_args_size ; extra_plus_reg_size = extra_size + reg_size ;"
GCC,arc,434,"Predict the next statement of this code snippet:
 <s> tree value , args = TREE_VALUE ( attr ) ; gcc_assert ( list_length ( args ) == <NUM_LIT> ) ; value = TREE_VALUE ( args ) ; gcc_assert ( TREE_CODE ( value ) == STRING_CST ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) || ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type |= ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type |= ARC_FUNCTION_ILINK2 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type |= ARC_FUNCTION_FIRQ ; else gcc_unreachable ( ) ;"
GCC,arc,435,"Predict the next statement of this code snippet:
 <s> tree value , args = TREE_VALUE ( attr ) ; gcc_assert ( list_length ( args ) == <NUM_LIT> ) ; value = TREE_VALUE ( args ) ; gcc_assert ( TREE_CODE ( value ) == STRING_CST ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) || ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type |= ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type |= ARC_FUNCTION_ILINK2 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type |= ARC_FUNCTION_FIRQ ; else gcc_unreachable ( ) ; }"
GCC,arc,436,"Predict the next statement of this code snippet:
 <s> int regno ; int start_reg = <NUM_LIT> , end_reg = <NUM_LIT> ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( <NUM_LIT> << regno ) ) ; ) regno ++ ; end_reg = regno - <NUM_LIT> ; if ( regno - start_reg >= <NUM_LIT> - ( crtl -> is_leaf == <NUM_LIT> ) ) { frame -> millicode_start_reg = <NUM_LIT> ;"
GCC,arc,437,"Predict the next statement of this code snippet:
 <s> for ( regno = start_reg ; regno <= end_reg && ( gmask & ( <NUM_LIT> << regno ) ) ; ) regno ++ ; end_reg = regno - <NUM_LIT> ; if ( regno - start_reg >= <NUM_LIT> - ( crtl -> is_leaf == <NUM_LIT> ) ) { frame -> millicode_start_reg = <NUM_LIT> ; frame -> millicode_end_reg = regno - <NUM_LIT> ; return <NUM_LIT> ; }"
GCC,arc,438,"Predict the next statement of this code snippet:
 <s> m2 = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; s1 = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; s2 = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; if ( l1 | l2 | m1 | m2 | s1 | s2 ) {"
GCC,arc,439,"Predict the next statement of this code snippet:
 <s> arc_regno_reg_class [ R30_REG ] = GENERAL_REGS ; } } if ( TARGET_MUL64_SET ) { fix_start = R57_REG ; fix_end = R59_REG ; strcpy ( rname57 , <STR_LIT> ) ; strcpy ( rname58 , <STR_LIT> ) ; strcpy ( rname59 , <STR_LIT> ) ; } if ( arc_tp_regno != - <NUM_LIT> ) fixed_regs [ arc_tp_regno ] = call_used_regs [ arc_tp_regno ] = <NUM_LIT> ; if ( TARGET_MULMAC_32BY16_SET ) { fix_start = MUL32x16_REG ; fix_end = fix_end > R57_REG ? fix_end : R57_REG ; strcpy ( rname56 , TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ; strcpy ( rname57 , TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ; } for ( regno = fix_start ; regno <= fix_end ; regno ++ ) { if ( ! fixed_regs [ regno ] ) warning ( <NUM_LIT> , <STR_LIT> , regno ) ; fixed_regs [ regno ] = call_used_regs [ regno ] = <NUM_LIT> ; } if ( TARGET_RF16 ) { for ( i = R4_REG ; i <= R9_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; for ( i = R16_REG ; i <= R25_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; } if ( TARGET_HS ) for ( regno = R1_REG ; regno < R32_REG ; regno += <NUM_LIT> ) arc_hard_regno_modes [ regno ] = S_MODES ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( i < ILINK1_REG ) { if ( ( i <= R3_REG ) || ( ( i >= R12_REG ) && ( i <= R15_REG ) ) ) arc_regno_reg_class [ i ] = ARCOMPACT16_REGS ; else arc_regno_reg_class [ i ] = GENERAL_REGS ; } else if ( i < LP_COUNT ) arc_regno_reg_class [ i ] = GENERAL_REGS ; else arc_regno_reg_class [ i ] = NO_REGS ; arc_regno_reg_class [ CC_REG ] = NO_REGS ; arc_regno_reg_class [ FRAME_POINTER_REGNUM ] = GENERAL_REGS ; arc_regno_reg_class [ ARG_POINTER_REGNUM ] = GENERAL_REGS ; if ( TARGET_DPFP ) for ( i = R40_REG ; i < R44_REG ; ++ i ) { arc_regno_reg_class [ i ] = DOUBLE_REGS ; if ( ! TARGET_ARGONAUT_SET ) CLEAR_HARD_REG_BIT ( reg_class_contents [ GENERAL_REGS ] , i ) ; } else { arc_regno_reg_class [ R40_REG ] = ALL_REGS ; arc_regno_reg_class [ R41_REG ] = ALL_REGS ; arc_regno_reg_class [ R42_REG ] = ALL_REGS ; arc_regno_reg_class [ R43_REG ] = ALL_REGS ; fixed_regs [ R40_REG ] = <NUM_LIT> ; fixed_regs [ R41_REG ] = <NUM_LIT> ; fixed_regs [ R42_REG ] = <NUM_LIT> ; fixed_regs [ R43_REG ] = <NUM_LIT> ; arc_hard_regno_modes [ R40_REG ] = <NUM_LIT> ; arc_hard_regno_modes [ R42_REG ] = <NUM_LIT> ; } if ( TARGET_SIMD_SET ) { gcc_assert ( ARC_FIRST_SIMD_VR_REG == <NUM_LIT> ) ; gcc_assert ( ARC_LAST_SIMD_VR_REG == <NUM_LIT> ) ; for ( i = ARC_FIRST_SIMD_VR_REG ; i <= ARC_LAST_SIMD_VR_REG ; i ++ ) arc_regno_reg_class [ i ] = SIMD_VR_REGS ;"
GCC,arc,440,"Predict the next statement of this code snippet:
 <s> if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; x = arc_delegitimize_address_0 ( x ) ; if ( ! x ) return orig_x ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ;"
GCC,arc,441,"Predict the next statement of this code snippet:
 <s> if ( ! x ) return orig_x ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ;"
GCC,arc,442,"Predict the next statement of this code snippet:
 <s> rtx t1 = arc_delegitimize_address_0 ( XEXP ( op , <NUM_LIT> ) ) ; rtx t2 = XEXP ( op , <NUM_LIT> ) ; if ( t1 && t2 ) return gen_rtx_PLUS ( GET_MODE ( op ) , t1 , t2 ) ; break ; } default : break ; }"
GCC,arc,443,"Predict the next statement of this code snippet:
 <s> case ARC_UNSPEC_GOTOFFPC : return XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ; default : break ; } break ; case PLUS : { rtx t1 = arc_delegitimize_address_0 ( XEXP ( op , <NUM_LIT> ) ) ; rtx t2 = XEXP ( op , <NUM_LIT> ) ; if ( t1 && t2 ) return gen_rtx_PLUS ( GET_MODE ( op ) , t1 , t2 ) ; break ; }"
GCC,arc,444,"Predict the next statement of this code snippet:
 <s> if ( TARGET_DPFP ) return true ; low = CONST_DOUBLE_LOW ( value ) ; high = CONST_DOUBLE_HIGH ( value ) ; if ( low & <NUM_LIT> ) { return ( ( ( unsigned HOST_WIDE_INT ) low <= <NUM_LIT> && high == <NUM_LIT> ) || ( ( ( low & - ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) == - ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) && high == - <NUM_LIT> ) ) ; }"
GCC,arc,445,"Predict the next statement of this code snippet:
 <s> offset = UNITS_PER_WORD * ( irq_ctrl_saved . irq_save_last_reg + <NUM_LIT> + irq_ctrl_saved . irq_save_blink + irq_ctrl_saved . irq_save_lpcount ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * offset ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , j ++ ) = tmp ; offset -= UNITS_PER_WORD ; if ( irq_ctrl_saved . irq_save_lpcount ) { reg = gen_rtx_REG ( SImode , <NUM_LIT> ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; tmp = gen_frame_mem ( SImode , tmp ) ;"
GCC,arc,446,"Predict the next statement of this code snippet:
 <s> static rtx arc_dwarf_register_span ( rtx rtl ) { machine_mode mode = GET_MODE ( rtl ) ; unsigned regno ; rtx p ; if ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) return NULL_RTX ; p = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ;"
GCC,arc,447,"Predict the next statement of this code snippet:
 <s> machine_mode mode = GET_MODE ( rtl ) ; unsigned regno ; rtx p ; if ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) return NULL_RTX ; p = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; regno = REGNO ( rtl ) ; XVECEXP ( p , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_REG ( SImode , regno ) ;"
GCC,arc,448,"Predict the next statement of this code snippet:
 <s> afi = & cfun -> machine -> frame_info ; gcc_assert ( crtl -> calls_eh_return ) ; gcc_assert ( afi -> save_return_addr ) ; gcc_assert ( afi -> extra_size >= <NUM_LIT> ) ; offset = afi -> reg_size + afi -> extra_size - <NUM_LIT> ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , hard_frame_pointer_rtx , offset ) ) ; MEM_VOLATILE_P ( mem ) = true ;"
GCC,arc,449,"Predict the next statement of this code snippet:
 <s> rtx mem ; int offset ; struct arc_frame_info * afi ; arc_compute_frame_size ( ) ; afi = & cfun -> machine -> frame_info ; gcc_assert ( crtl -> calls_eh_return ) ; gcc_assert ( afi -> save_return_addr ) ;"
GCC,arc,450,"Predict the next statement of this code snippet:
 <s> static void arc_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { rtx symbol = XEXP ( rtl , <NUM_LIT> ) ; int flags = SYMBOL_REF_FLAGS ( symbol ) ; tree attr = ( TREE_TYPE ( decl ) != error_mark_node ? TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) : NULL_TREE ) ; tree long_call_attr = lookup_attribute ( <STR_LIT> , attr ) ; tree medium_call_attr = lookup_attribute ( <STR_LIT> , attr ) ; tree short_call_attr = lookup_attribute ( <STR_LIT> , attr ) ; if ( long_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_LONG_CALL ; else if ( medium_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_MEDIUM_CALL ; else if ( short_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_SHORT_CALL ; SYMBOL_REF_FLAGS ( symbol ) = flags ; } else if ( TREE_CODE ( decl ) == VAR_DECL ) { rtx symbol = XEXP ( rtl , <NUM_LIT> ) ; tree attr = ( TREE_TYPE ( decl ) != error_mark_node ? DECL_ATTRIBUTES ( decl ) : NULL_TREE ) ; tree sec_attr = lookup_attribute ( <STR_LIT> , attr ) ; if ( sec_attr ) { const char * sec_name = TREE_STRING_POINTER ( TREE_VALUE ( TREE_VALUE ( sec_attr ) ) ) ;"
GCC,arc,451,"Predict the next statement of this code snippet:
 <s> int regno ; unsigned int rmask = <NUM_LIT> ; if ( ! gmask ) return false ; for ( regno = ENTER_LEAVE_START_REG ;"
GCC,arc,452,"Predict the next statement of this code snippet:
 <s> static bool arc_enter_leave_p ( uint64_t gmask ) { int regno ; unsigned int rmask = <NUM_LIT> ; if ( ! gmask ) return false ; for ( regno = ENTER_LEAVE_START_REG ;"
GCC,arc,453,"Predict the next statement of this code snippet:
 <s> if ( regno == arc_tp_regno ) return true ; if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( regno == arc_return_address_register ( fn_type ) ) return true ; if ( epilogue_completed && ARC_INTERRUPT_P ( fn_type ) ) { if ( df_regs_ever_live_p ( regno ) || call_used_or_fixed_reg_p ( regno ) ) return true ; }"
GCC,arc,454,"Predict the next statement of this code snippet:
 <s> emit_label ( label ) ; label = gen_rtx_LABEL_REF ( VOIDmode , label ) ; if ( before == NULL_RTX ) before = gen_reg_rtx ( mode ) ; if ( after == NULL_RTX ) after = gen_reg_rtx ( mode ) ; emit_insn ( gen_arc_load_exclusivesi ( before , mem ) ) ; switch ( code ) { case NOT : x = gen_rtx_AND ( mode , before , val ) ; emit_insn ( gen_rtx_SET ( after , x ) ) ; x = gen_rtx_NOT ( mode , after ) ; emit_insn ( gen_rtx_SET ( after , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( val ) ) { val = GEN_INT ( - INTVAL ( val ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , mode , before , val ) ; emit_insn ( gen_rtx_SET ( after , x ) ) ; break ; } emit_insn ( gen_arc_store_exclusivesi ( mem , after ) ) ; cond = gen_rtx_REG ( CC_Zmode , CC_REG ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , label , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ;"
GCC,arc,455,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT alignTest = INTVAL ( op1 ) ; if ( alignTest <= <NUM_LIT> || alignTest != ( alignTest & - alignTest ) ) { error ( <STR_LIT> ) ; return NULL_RTX ; } if ( CONST_INT_P ( op0 ) ) { HOST_WIDE_INT pnt = INTVAL ( op0 ) ; if ( ( pnt & ( alignTest - <NUM_LIT> ) ) == <NUM_LIT> ) return const1_rtx ; } else {"
GCC,arc,456,"Predict the next statement of this code snippet:
 <s> if ( GET_MODE ( mem ) == QImode ) mask = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; else mask = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( mask , gen_rtx_ASHIFT ( SImode , mask , off ) ) ) ; emit_insn ( gen_rtx_SET ( val , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , val ) ) ) ; oldval = gen_lowpart ( SImode , oldval ) ; emit_insn ( gen_rtx_SET ( oldv , gen_rtx_ASHIFT ( SImode , oldval , off ) ) ) ; newval = gen_lowpart_common ( SImode , newval ) ; emit_insn ( gen_rtx_SET ( newv , gen_rtx_ASHIFT ( SImode , newval , off ) ) ) ; emit_insn ( gen_rtx_SET ( oldv , gen_rtx_AND ( SImode , oldv , mask ) ) ) ; emit_insn ( gen_rtx_SET ( newv , gen_rtx_AND ( SImode , newv , mask ) ) ) ; if ( ! is_weak ) { end_label = gen_label_rtx ( ) ; loop_label = gen_label_rtx ( ) ; emit_label ( loop_label ) ; } emit_insn ( gen_rtx_SET ( oldvalue , gen_rtx_IOR ( SImode , oldv , val ) ) ) ; emit_insn ( gen_rtx_SET ( newvalue , gen_rtx_IOR ( SImode , newv , val ) ) ) ; emit_insn ( gen_atomic_compare_and_swapsi_1 ( res , memsi , oldvalue , newvalue , weak , mod_s , mod_f ) ) ;"
GCC,arc,457,"Predict the next statement of this code snippet:
 <s> emit_insn ( gen_rtx_SET ( off , gen_rtx_AND ( SImode , addr1 , GEN_INT ( <NUM_LIT> ) ) ) ) ; if ( TARGET_BIG_ENDIAN ) emit_insn ( gen_rtx_SET ( off , gen_rtx_MINUS ( SImode , ( GET_MODE ( mem ) == QImode ) ? GEN_INT ( <NUM_LIT> ) : GEN_INT ( <NUM_LIT> ) , off ) ) ) ; memsi = gen_rtx_MEM ( SImode , addr ) ; set_mem_alias_set ( memsi , ALIAS_SET_MEMORY_BARRIER ) ; MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; val = copy_to_reg ( memsi ) ; emit_insn ( gen_rtx_SET ( off , gen_rtx_ASHIFT ( SImode , off , GEN_INT ( <NUM_LIT> ) ) ) ) ; if ( GET_MODE ( mem ) == QImode ) mask = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; else mask = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( mask , gen_rtx_ASHIFT ( SImode , mask , off ) ) ) ; emit_insn ( gen_rtx_SET ( val , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , val ) ) ) ; oldval = gen_lowpart ( SImode , oldval ) ; emit_insn ( gen_rtx_SET ( oldv , gen_rtx_ASHIFT ( SImode , oldval , off ) ) ) ; newval = gen_lowpart_common ( SImode , newval ) ; emit_insn ( gen_rtx_SET ( newv , gen_rtx_ASHIFT ( SImode , newval , off ) ) ) ; emit_insn ( gen_rtx_SET ( oldv , gen_rtx_AND ( SImode , oldv , mask ) ) ) ; emit_insn ( gen_rtx_SET ( newv , gen_rtx_AND ( SImode , newv , mask ) ) ) ;"
GCC,arc,458,"Predict the next statement of this code snippet:
 <s> fprintf ( asm_out_file , <STR_LIT> <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; sec = sec -> next ; }"
GCC,arc,459,"Predict the next statement of this code snippet:
 <s> asm_fprintf ( asm_out_file , <STR_LIT> , TARGET_OPTFPE ? <NUM_LIT> : <NUM_LIT> ) ; if ( TARGET_V2 ) asm_fprintf ( asm_out_file , <STR_LIT> , ( arc_tune < ARC_TUNE_CORE_3 ) ? <NUM_LIT> :"
GCC,arc,460,"Predict the next statement of this code snippet:
 <s> asm_fprintf ( asm_out_file , <STR_LIT> , ( arc_tp_regno != - <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> , TARGET_NO_SDATA_SET ? <NUM_LIT> : <NUM_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> , TARGET_OPTFPE ? <NUM_LIT> : <NUM_LIT> ) ; if ( TARGET_V2 ) asm_fprintf ( asm_out_file , <STR_LIT> , ( arc_tune < ARC_TUNE_CORE_3 ) ? <NUM_LIT> :"
GCC,arc,461,"Predict the next statement of this code snippet:
 <s> if ( TARGET_DUMPISIZE ) fprintf ( asm_out_file , <STR_LIT> , INSN_ADDRESSES ( INSN_UID ( insn ) ) ) ; if ( ! cfun -> machine -> prescan_initialized ) {"
GCC,arc,462,"Predict the next statement of this code snippet:
 <s> if ( TARGET_DUMPISIZE ) fprintf ( asm_out_file , <STR_LIT> , INSN_ADDRESSES ( INSN_UID ( insn ) ) ) ; if ( ! cfun -> machine -> prescan_initialized ) { memset ( & arc_ccfsm_current , <NUM_LIT> , sizeof arc_ccfsm_current ) ; cfun -> machine -> prescan_initialized = <NUM_LIT> ;"
GCC,arc,463,"Predict the next statement of this code snippet:
 <s> static bool arc_frame_pointer_needed ( void ) {"
GCC,arc,464,"Predict the next statement of this code snippet:
 <s> rtx ret ; const char * debstr ATTRIBUTE_UNUSED ; arg_num = ROUND_ADVANCE_CUM ( arg_num , arg . mode , arg . type ) ; if ( arg . end_marker_p ( ) ) { ret = const0_rtx ;"
GCC,arc,465,"Predict the next statement of this code snippet:
 <s> if ( words ) * cum = ROUND_ADVANCE_CUM ( * cum , arg . mode , arg . type ) ;"
GCC,arc,466,"Predict the next statement of this code snippet:
 <s> if ( decl ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return false ;"
GCC,arc,467,"Predict the next statement of this code snippet:
 <s> if ( decl ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return false ;"
GCC,arc,468,"Predict the next statement of this code snippet:
 <s> int unsignedp ATTRIBUTE_UNUSED ; unsignedp = TYPE_UNSIGNED ( valtype ) ; if ( INTEGRAL_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == OFFSET_TYPE ) PROMOTE_MODE ( mode , unsignedp , valtype ) ; return gen_rtx_REG ( mode , <NUM_LIT> ) ;"
GCC,arc,469,"Predict the next statement of this code snippet:
 <s> unsignedp = TYPE_UNSIGNED ( valtype ) ; if ( INTEGRAL_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == OFFSET_TYPE ) PROMOTE_MODE ( mode , unsignedp , valtype ) ;"
GCC,arc,470,"Predict the next statement of this code snippet:
 <s> gcc_assert ( ARC_INVERSE_CONDITION_CODE ( raw_cc ) == statep -> cc ) ; machine_mode ccm = GET_MODE ( XEXP ( cond , <NUM_LIT> ) ) ; enum rtx_code code = reverse_condition ( GET_CODE ( cond ) ) ; if ( code == UNKNOWN || ccm == CC_FP_GTmode || ccm == CC_FP_GEmode ) code = reverse_condition_maybe_unordered ( GET_CODE ( cond ) ) ; return gen_rtx_fmt_ee ( code , GET_MODE ( cond ) , copy_rtx ( XEXP ( cond , <NUM_LIT> ) ) , copy_rtx ( XEXP ( cond , <NUM_LIT> ) ) ) ;"
GCC,arc,471,"Predict the next statement of this code snippet:
 <s> machine_mode ccm = GET_MODE ( XEXP ( cond , <NUM_LIT> ) ) ; enum rtx_code code = reverse_condition ( GET_CODE ( cond ) ) ;"
GCC,arc,472,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( arg ) != INTEGER_CST ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; } } if ( TREE_CODE ( * node ) == VAR_DECL ) { tree fntype = TREE_TYPE ( * node ) ; if ( fntype && TREE_CODE ( fntype ) == POINTER_TYPE ) { tree attrs = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( fntype ) ) ; TYPE_ATTRIBUTES ( fntype ) = attrs ; } } }"
GCC,arc,473,"Predict the next statement of this code snippet:
 <s> } else if ( args ) { if ( TREE_CODE ( TREE_VALUE ( args ) ) == NON_LVALUE_EXPR ) TREE_VALUE ( args ) = TREE_OPERAND ( TREE_VALUE ( args ) , <NUM_LIT> ) ; tree arg = TREE_VALUE ( args ) ; if ( TREE_CODE ( arg ) != INTEGER_CST ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; } } if ( TREE_CODE ( * node ) == VAR_DECL ) { tree fntype = TREE_TYPE ( * node ) ; if ( fntype && TREE_CODE ( fntype ) == POINTER_TYPE ) { tree attrs = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( fntype ) ) ; TYPE_ATTRIBUTES ( fntype ) = attrs ; }"
GCC,arc,474,"Predict the next statement of this code snippet:
 <s> static tree arc_handle_fndecl_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) != FUNCTION_DECL ) {"
GCC,arc,475,"Predict the next statement of this code snippet:
 <s> static tree arc_handle_fndecl_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) {"
GCC,arc,476,"Predict the next statement of this code snippet:
 <s> * no_add_attrs = true ; } else if ( ! TARGET_V2 && strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) && strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ;"
GCC,arc,477,"Predict the next statement of this code snippet:
 <s> if ( DECL_P ( * node ) && TREE_CODE ( * node ) != TYPE_DECL ) { error ( <STR_LIT> , name ) ;"
GCC,arc,478,"Predict the next statement of this code snippet:
 <s> static bool arc_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) {"
GCC,arc,479,"Predict the next statement of this code snippet:
 <s> if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> && regno >= ARC_FIRST_SIMD_VR_REG && regno <= ARC_LAST_SIMD_VR_REG ) return <NUM_LIT> ;"
GCC,arc,480,"Predict the next statement of this code snippet:
 <s> int arc_hazard ( rtx_insn * pred , rtx_insn * succ ) { if ( ! pred || ! INSN_P ( pred ) || ! succ || ! INSN_P ( succ ) ) return <NUM_LIT> ; if ( TARGET_ARC600 ) return arc600_corereg_hazard ( pred , succ ) ; return <NUM_LIT> ;"
GCC,arc,481,"Predict the next statement of this code snippet:
 <s> gcc_assert ( ! IN_RANGE ( statep -> state , <NUM_LIT> , <NUM_LIT> ) ) ; rtx_insn * seq = NEXT_INSN ( PREV_INSN ( insn ) ) ; if ( GET_CODE ( PATTERN ( seq ) ) == SEQUENCE ) { rtx slot = XVECEXP ( PATTERN ( seq ) , <NUM_LIT> , <NUM_LIT> ) ; rtx pat = PATTERN ( slot ) ; if ( INSN_ANNULLED_BRANCH_P ( insn ) ) { rtx cond = arc_get_ccfsm_cond ( statep , INSN_FROM_TARGET_P ( slot ) ) ; pat = gen_rtx_COND_EXEC ( VOIDmode , cond , pat ) ; } if ( ! validate_change ( seq , & PATTERN ( seq ) , pat , <NUM_LIT> ) ) gcc_unreachable ( ) ; PUT_CODE ( slot , NOTE ) ; NOTE_KIND ( slot ) = NOTE_INSN_DELETED ; } else { set_insn_deleted ( insn ) ; } continue ; } case <NUM_LIT> : if ( LABEL_P ( insn ) && statep -> target_label == CODE_LABEL_NUMBER ( insn ) ) { arc_ccfsm_post_advance ( insn , statep ) ; if ( -- LABEL_NUSES ( insn ) == <NUM_LIT> ) delete_insn ( insn ) ; continue ; } case <NUM_LIT> : case <NUM_LIT> : if ( ! NONDEBUG_INSN_P ( insn ) ) break ; rtx_insn * prev , * pprev ; rtx * patp , pat , cond ; bool annulled ; annulled = false ; prev = PREV_INSN ( insn ) ; pprev = PREV_INSN ( prev ) ; if ( pprev && NEXT_INSN ( NEXT_INSN ( pprev ) ) == NEXT_INSN ( insn ) && JUMP_P ( prev ) && get_attr_cond ( prev ) == COND_USE ) { if ( ! INSN_ANNULLED_BRANCH_P ( prev ) ) break ; annulled = true ; } patp = & PATTERN ( insn ) ; pat = * patp ; cond = arc_get_ccfsm_cond ( statep , INSN_FROM_TARGET_P ( insn ) ) ; if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { pat = conditionalize_nonjump ( pat , cond , insn , annulled ) ; } else if ( simplejump_p ( insn ) ) { patp = & SET_SRC ( pat ) ; pat = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , * patp , pc_rtx ) ; } else if ( JUMP_P ( insn ) && ANY_RETURN_P ( PATTERN ( insn ) ) ) { pat = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , pat , pc_rtx ) ; pat = gen_rtx_SET ( pc_rtx , pat ) ; } else gcc_unreachable ( ) ; validate_change ( insn , patp , pat , <NUM_LIT> ) ; if ( ! apply_change_group ( ) ) gcc_unreachable ( ) ; if ( JUMP_P ( insn ) ) {"
GCC,arc,482,"Predict the next statement of this code snippet:
 <s> if ( TARGET_NOMPY_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ! TARGET_DPFP && TARGET_DPFP_DISABLE_LRSR ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET && TARGET_DPFP_COMPACT_SET ) || ( TARGET_SPFP_FAST_SET && TARGET_SPFP_COMPACT_SET ) ) error ( <STR_LIT> ) ; if ( TARGET_SPFP_FAST_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET || TARGET_SPFP ) && TARGET_HARD_FLOAT ) error ( <STR_LIT> ) ; if ( flag_pic && TARGET_ARC600_FAMILY ) { warning ( <NUM_LIT> , <STR_LIT> , arc_cpu_string ) ; flag_pic = <NUM_LIT> ; } arc_init_reg_tables ( ) ; memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ; arc_punct_chars [ '*' ] = <NUM_LIT> ; arc_punct_chars [ '?' ] = <NUM_LIT> ; arc_punct_chars [ '!' ] = <NUM_LIT> ; arc_punct_chars [ '^' ] = <NUM_LIT> ; arc_punct_chars [ '&' ] = <NUM_LIT> ;"
GCC,arc,483,"Predict the next statement of this code snippet:
 <s> arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_NOMPY_SET ) arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case ARC_TUNE_ARC600 : if ( TARGET_MUL64_SET ) { arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } default : arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } if ( TARGET_NOMPY_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ! TARGET_DPFP && TARGET_DPFP_DISABLE_LRSR ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET && TARGET_DPFP_COMPACT_SET ) || ( TARGET_SPFP_FAST_SET && TARGET_SPFP_COMPACT_SET ) ) error ( <STR_LIT> ) ; if ( TARGET_SPFP_FAST_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET || TARGET_SPFP ) && TARGET_HARD_FLOAT ) error ( <STR_LIT> ) ;"
GCC,arc,484,"Predict the next statement of this code snippet:
 <s> rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; emit_block_move ( tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ;"
GCC,arc,485,"Predict the next statement of this code snippet:
 <s> if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return ( cfun -> machine -> frame_info . total_size - cfun -> machine -> frame_info . pretend_size ) ; } if ( ( from == FRAME_POINTER_REGNUM ) && ( to == STACK_POINTER_REGNUM ) ) { return ( cfun -> machine -> frame_info . total_size - ( cfun -> machine -> frame_info . pretend_size + cfun -> machine -> frame_info . extra_size + cfun -> machine -> frame_info . reg_size ) ) ; } if ( ( from == FRAME_POINTER_REGNUM ) && ( to == HARD_FRAME_POINTER_REGNUM ) ) return <NUM_LIT> ;"
GCC,arc,486,"Predict the next statement of this code snippet:
 <s> init_machine_status = arc_init_machine_status ;"
GCC,arc,487,"Predict the next statement of this code snippet:
 <s> static struct machine_function * arc_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> fn_type = ARC_FUNCTION_UNKNOWN ; return machine ;"
GCC,arc,488,"Predict the next statement of this code snippet:
 <s> for ( i = <NUM_LIT> ; i < NUM_MACHINE_MODES ; i ++ ) { machine_mode m = ( machine_mode ) i ; switch ( GET_MODE_CLASS ( m ) ) { case MODE_INT : case MODE_PARTIAL_INT : case MODE_COMPLEX_INT : if ( GET_MODE_SIZE ( m ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) S_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) O_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( m ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) OF_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_VECTOR_INT : if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = ( <NUM_LIT> << ( int ) S_MODE ) ; else if ( GET_MODE_SIZE ( m ) == <NUM_LIT> ) arc_mode_class [ i ] = ( <NUM_LIT> << ( int ) D_MODE ) ; else arc_mode_class [ i ] = ( <NUM_LIT> << ( int ) V_MODE ) ; break ; case MODE_CC : default : if ( i == ( int ) CCmode || i == ( int ) CC_ZNmode || i == ( int ) CC_Zmode || i == ( int ) CC_Cmode || i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode || i == CC_FPUmode || i == CC_FPUEmode || i == CC_FPU_UNEQmode ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) C_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; } }"
GCC,arc,489,"Predict the next statement of this code snippet:
 <s> static int arc_insn_cost ( rtx_insn * insn , bool speed ) { int cost ; if ( recog_memoized ( insn ) < <NUM_LIT> ) return <NUM_LIT> ; if ( ! speed ) return get_attr_length ( insn ) ; cost = get_attr_cost ( insn ) ; if ( cost > <NUM_LIT> ) return cost ; enum attr_type type = get_attr_type ( insn ) ;"
GCC,arc,490,"Predict the next statement of this code snippet:
 <s> static void arc_internal_label ( FILE * stream , const char * prefix , unsigned long labelno ) { if ( cfun ) arc_ccfsm_at_label ( prefix , labelno , & arc_ccfsm_current ) ;"
GCC,arc,491,"Predict the next statement of this code snippet:
 <s> if ( cfun ) arc_ccfsm_at_label ( prefix , labelno , & arc_ccfsm_current ) ; default_internal_label ( stream , prefix , labelno ) ;"
GCC,arc,492,"Predict the next statement of this code snippet:
 <s> static const char * arc_invalid_within_doloop ( const rtx_insn * insn ) { if ( CALL_P ( insn ) ) return <STR_LIT> ; return NULL ;"
GCC,arc,493,"Predict the next statement of this code snippet:
 <s> static bool arc_in_small_data_p ( const_tree decl ) { HOST_WIDE_INT size ; tree attr ; if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TARGET_NO_SDATA_SET ) return false ; if ( DECL_WEAK ( decl ) ) return false ; if ( TREE_READONLY ( decl ) ) return false ; if ( ! TARGET_VOLATILE_CACHE_SET && TREE_THIS_VOLATILE ( decl ) ) return false ; attr = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attr ) ) return false ; attr = DECL_ATTRIBUTES ( decl ) ; if ( lookup_attribute ( <STR_LIT> , attr ) ) return false ;"
GCC,arc,494,"Predict the next statement of this code snippet:
 <s> if ( TREE_READONLY ( decl ) ) return false ; if ( ! TARGET_VOLATILE_CACHE_SET && TREE_THIS_VOLATILE ( decl ) ) return false ; attr = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attr ) ) return false ; attr = DECL_ATTRIBUTES ( decl ) ; if ( lookup_attribute ( <STR_LIT> , attr ) ) return false ; if ( DECL_SECTION_NAME ( decl ) != <NUM_LIT> ) {"
GCC,arc,495,"Predict the next statement of this code snippet:
 <s> else if ( TREE_CODE ( addr ) == MEM_REF ) attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ; else return false ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; return false ;"
GCC,arc,496,"Predict the next statement of this code snippet:
 <s> if ( ! addr ) return false ; if ( TREE_CODE ( addr ) == VAR_DECL ) attrs = DECL_ATTRIBUTES ( addr ) ; else if ( TREE_CODE ( addr ) == MEM_REF ) attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ; else return false ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; return false ;"
GCC,arc,497,"Predict the next statement of this code snippet:
 <s> if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; return TARGET_JLI_ALWAYS ;"
GCC,arc,498,"Predict the next statement of this code snippet:
 <s> if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; return TARGET_JLI_ALWAYS ;"
GCC,arc,499,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( sym_ref ) != SYMBOL_REF ) return false ; return ( SYMBOL_REF_LONG_CALL_P ( sym_ref ) || ( TARGET_LONG_CALLS_SET && ! SYMBOL_REF_SHORT_CALL_P ( sym_ref ) && ! SYMBOL_REF_MEDIUM_CALL_P ( sym_ref ) ) ) ;"
GCC,arc,500,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( sym_ref ) != SYMBOL_REF ) return false ;"
GCC,arc,501,"Predict the next statement of this code snippet:
 <s> attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ;"
GCC,arc,502,"Predict the next statement of this code snippet:
 <s> if ( ! decl ) return false ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ;"
GCC,arc,503,"Predict the next statement of this code snippet:
 <s> bool arc_is_shortcall_p ( rtx sym_ref ) { if ( GET_CODE ( sym_ref ) != SYMBOL_REF ) return false ; return ( SYMBOL_REF_SHORT_CALL_P ( sym_ref ) || ( ! TARGET_LONG_CALLS_SET && ! TARGET_MEDIUM_CALLS && ! SYMBOL_REF_LONG_CALL_P ( sym_ref ) && ! SYMBOL_REF_MEDIUM_CALL_P ( sym_ref ) ) ) ;"
GCC,arc,504,"Predict the next statement of this code snippet:
 <s> tree addr ; if ( ! MEM_P ( pat ) ) return false ; addr = MEM_EXPR ( pat ) ; if ( ! addr ) return false ; if ( TREE_CODE ( addr ) == MEM_REF || TREE_CODE ( addr ) == VAR_DECL ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( addr ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; } if ( TREE_CODE ( addr ) == MEM_REF ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ;"
GCC,arc,505,"Predict the next statement of this code snippet:
 <s> if ( TREE_CODE ( addr ) == COMPONENT_REF ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( addr ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ;"
GCC,arc,506,"Predict the next statement of this code snippet:
 <s> if ( align_labels . levels [ <NUM_LIT> ] . log < <NUM_LIT> ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( INSN_P ( next ) && recog_memoized ( next ) >= <NUM_LIT> ) return <NUM_LIT> ; }"
GCC,arc,507,"Predict the next statement of this code snippet:
 <s> int arc_label_align ( rtx_insn * label ) { if ( align_labels . levels [ <NUM_LIT> ] . log < <NUM_LIT> ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( INSN_P ( next ) && recog_memoized ( next ) >= <NUM_LIT> ) return <NUM_LIT> ; } return align_labels . levels [ <NUM_LIT> ] . log ;"
GCC,arc,508,"Predict the next statement of this code snippet:
 <s> static bool arc_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { if ( RTX_OK_FOR_BASE_P ( x , strict ) ) return true ; if ( legitimate_offset_address_p ( mode , x , TARGET_INDEXED_LOADS , strict ) ) return true ; if ( legitimate_scaled_address_p ( mode , x , strict ) ) return true ; if ( legitimate_small_data_address_p ( x , mode ) ) return true ; if ( GET_CODE ( x ) == CONST_INT && LARGE_INT ( INTVAL ( x ) ) ) return true ; if ( ! flag_pic && optimize_size && ! reload_completed && ( GET_CODE ( x ) == CONST ) && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) && ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> && ! SYMBOL_REF_FUNCTION_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) {"
GCC,arc,509,"Predict the next statement of this code snippet:
 <s> case CONST_DOUBLE : return true ; case NEG : return arc_legitimate_constant_p ( mode , XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : { bool t1 = arc_legitimate_constant_p ( mode , XEXP ( x , <NUM_LIT> ) ) ; bool t2 = arc_legitimate_constant_p ( mode , XEXP ( x , <NUM_LIT> ) ) ; return ( t1 && t2 ) ; } case CONST_VECTOR : switch ( mode ) { case E_V2HImode : return TARGET_PLUS_DMPY ;"
GCC,arc,510,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) != CONST_INT ) return false ; addr = XEXP ( addr , <NUM_LIT> ) ; } if ( GET_CODE ( addr ) != UNSPEC || XVECLEN ( addr , <NUM_LIT> ) != <NUM_LIT> ) return false ; if ( XINT ( addr , <NUM_LIT> ) != ARC_UNSPEC_GOT && XINT ( addr , <NUM_LIT> ) != ARC_UNSPEC_GOTOFF && XINT ( addr , <NUM_LIT> ) != ARC_UNSPEC_GOTOFFPC && XINT ( addr , <NUM_LIT> ) != UNSPEC_TLS_GD && XINT ( addr , <NUM_LIT> ) != UNSPEC_TLS_IE ) return false ;"
GCC,arc,511,"Predict the next statement of this code snippet:
 <s> static rtx arc_legitimize_address ( rtx orig_x , rtx oldx , machine_mode mode ) {"
GCC,arc,512,"Predict the next statement of this code snippet:
 <s> static rtx arc_legitimize_address ( rtx orig_x , rtx oldx , machine_mode mode ) { rtx new_x = arc_legitimize_address_0 ( orig_x , oldx , mode ) ; if ( new_x ) return new_x ;"
GCC,arc,513,"Predict the next statement of this code snippet:
 <s> int size = GET_MODE_SIZE ( mode ) ; offs = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ; upper = ( offs + <NUM_LIT> * size ) & ~ <NUM_LIT> * size ; inner = plus_constant ( Pmode , XEXP ( addr , <NUM_LIT> ) , upper ) ; if ( GET_CODE ( x ) == CONST ) inner = gen_rtx_CONST ( Pmode , inner ) ; addr = plus_constant ( Pmode , force_reg ( Pmode , inner ) , offs - upper ) ; x = addr ; }"
GCC,arc,514,"Predict the next statement of this code snippet:
 <s> addr = x ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == SYMBOL_REF && ! SYMBOL_REF_FUNCTION_P ( XEXP ( addr , <NUM_LIT> ) ) ) || ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) ) ) ) {"
GCC,arc,515,"Predict the next statement of this code snippet:
 <s> case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( addr ) ) return addr ; if ( ! arc_symbol_binds_local_p ( addr ) ) return gen_const_mem ( Pmode , arc_unspec_offset ( addr , ARC_UNSPEC_GOT ) ) ; case LABEL_REF : return arc_unspec_offset ( addr , ARC_UNSPEC_GOTOFFPC ) ; default : break ; } return addr ;"
GCC,arc,516,"Predict the next statement of this code snippet:
 <s> offset_base = ( ( offset + ( <NUM_LIT> << shift ) ) & ( ( HOST_WIDE_INT ) ( ( unsigned HOST_WIDE_INT ) - <NUM_LIT> << shift ) ) ) ; if ( GET_MODE_SIZE ( mode ) + offset - offset_base <= ( <NUM_LIT> << shift ) ) { int regno ; reg = XEXP ( x , <NUM_LIT> ) ; regno = REGNO ( reg ) ; sum2 = sum = plus_constant ( Pmode , reg , offset_base ) ; if ( reg_equiv_constant ( regno ) ) { sum2 = plus_constant ( Pmode , reg_equiv_constant ( regno ) , offset_base ) ; if ( GET_CODE ( sum2 ) == PLUS ) sum2 = gen_rtx_CONST ( Pmode , sum2 ) ; } * p = gen_rtx_PLUS ( Pmode , sum , GEN_INT ( offset - offset_base ) ) ; push_reload ( sum2 , NULL_RTX , & XEXP ( * p , <NUM_LIT> ) , NULL , BASE_REG_CLASS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , type ) ; return true ; } } else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && REG_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , type ) ; return true ; }"
GCC,arc,517,"Predict the next statement of this code snippet:
 <s> if ( ! flag_pic && model == TLS_MODEL_LOCAL_DYNAMIC ) model = TLS_MODEL_LOCAL_EXEC ; gcc_assert ( arc_tp_regno != - <NUM_LIT> ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tmp , arc_unspec_offset ( addr , UNSPEC_TLS_GD ) ) ; return arc_call_tls_get_addr ( tmp ) ; case TLS_MODEL_LOCAL_DYNAMIC : rtx base ; tree decl ; const char * base_name ; decl = SYMBOL_REF_DECL ( addr ) ; base_name = DTPOFF_ZERO_SYM ; if ( decl && bss_initializer_p ( decl ) ) base_name = <STR_LIT> ; base = gen_rtx_SYMBOL_REF ( Pmode , base_name ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tmp , arc_unspec_offset ( base , UNSPEC_TLS_GD ) ) ;"
GCC,arc,518,"Predict the next statement of this code snippet:
 <s> return gen_rtx_PLUS ( Pmode , force_reg ( Pmode , base ) , arc_unspec_offset ( addr , UNSPEC_TLS_OFF ) ) ; case TLS_MODEL_INITIAL_EXEC : addr = arc_unspec_offset ( addr , UNSPEC_TLS_IE ) ; addr = copy_to_mode_reg ( Pmode , gen_const_mem ( Pmode , addr ) ) ; return gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , arc_tp_regno ) , addr ) ; case TLS_MODEL_LOCAL_EXEC : addr = arc_unspec_offset ( addr , UNSPEC_TLS_OFF ) ;"
GCC,arc,519,"Predict the next statement of this code snippet:
 <s> bool arc_lra_p ( void ) {"
GCC,arc,520,"Predict the next statement of this code snippet:
 <s> return arc_lra_flag ;"
GCC,arc,521,"Predict the next statement of this code snippet:
 <s> static int arc_memory_move_cost ( machine_mode mode , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { if ( ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) || ( ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD * <NUM_LIT> ) && TARGET_LL64 ) ) return <NUM_LIT> ;"
GCC,arc,522,"Predict the next statement of this code snippet:
 <s> return ( GET_MODE_CLASS ( mode1 ) == MODE_INT && GET_MODE_CLASS ( mode2 ) == MODE_INT && GET_MODE_SIZE ( mode1 ) <= UNITS_PER_WORD && GET_MODE_SIZE ( mode2 ) <= UNITS_PER_WORD ) ;"
GCC,arc,523,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( ( addr ) , <NUM_LIT> ) ) == MULT ) return true ; return false ;"
GCC,arc,524,"Predict the next statement of this code snippet:
 <s> static bool arc_must_save_return_addr ( struct function * func ) { if ( func -> machine -> frame_info . save_return_addr ) return true ; return false ;"
GCC,arc,525,"Predict the next statement of this code snippet:
 <s> bool arc_need_delay ( rtx_insn * insn ) { rtx_insn * next ; if ( ! flag_delayed_branch ) return false ;"
GCC,arc,526,"Predict the next statement of this code snippet:
 <s> return true ;"
GCC,arc,527,"Predict the next statement of this code snippet:
 <s> return true ;"
GCC,arc,528,"Predict the next statement of this code snippet:
 <s> int match = operands_match_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; int match2 = operands_match_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; int intval = ( REG_P ( operands [ <NUM_LIT> ] ) ? <NUM_LIT> : CONST_INT_P ( operands [ <NUM_LIT> ] ) ? INTVAL ( operands [ <NUM_LIT> ] ) : <NUM_LIT> ) ; int neg_intval = - intval ; int short_0 = satisfies_constraint_Rcq ( operands [ <NUM_LIT> ] ) ; int short_p = ( ! cond_p && short_0 && satisfies_constraint_Rcq ( operands [ <NUM_LIT> ] ) ) ; int ret = <NUM_LIT> ;"
GCC,arc,529,"Predict the next statement of this code snippet:
 <s> int match2 = operands_match_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; int intval = ( REG_P ( operands [ <NUM_LIT> ] ) ? <NUM_LIT> : CONST_INT_P ( operands [ <NUM_LIT> ] ) ? INTVAL ( operands [ <NUM_LIT> ] ) : <NUM_LIT> ) ; int neg_intval = - intval ;"
GCC,arc,530,"Predict the next statement of this code snippet:
 <s> unsigned len = strlen ( fname ) ; static char buf [ <NUM_LIT> ] ; gcc_assert ( len < sizeof buf - <NUM_LIT> ) ; if ( TARGET_LONG_CALLS_SET || ( TARGET_MEDIUM_CALLS && arc_ccfsm_cond_exec_p ( ) ) ) { if ( flag_pic ) sprintf ( buf , <STR_LIT> , fname ) ; else sprintf ( buf , <STR_LIT> , fname ) ;"
GCC,arc,531,"Predict the next statement of this code snippet:
 <s> const char * arc_output_libcall ( const char * fname ) { unsigned len = strlen ( fname ) ; static char buf [ <NUM_LIT> ] ; gcc_assert ( len < sizeof buf - <NUM_LIT> ) ; if ( TARGET_LONG_CALLS_SET || ( TARGET_MEDIUM_CALLS && arc_ccfsm_cond_exec_p ( ) ) ) { if ( flag_pic ) sprintf ( buf , <STR_LIT> , fname ) ; else sprintf ( buf , <STR_LIT> , fname ) ; } else sprintf ( buf , <STR_LIT> , fname ) ;"
GCC,arc,532,"Predict the next statement of this code snippet:
 <s> asm_fprintf ( file , <STR_LIT> , ARC_TEMP_SCRATCH_REG , ARC_TEMP_SCRATCH_REG ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ this_regno ] , reg_names [ this_regno ] , ARC_TEMP_SCRATCH_REG ) ; } fnaddr = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( arc_is_longcall_p ( fnaddr ) ) { if ( flag_pic ) { asm_fprintf ( file , <STR_LIT> , ARC_TEMP_SCRATCH_REG ) ; assemble_name ( file , XSTR ( fnaddr , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , file ) ; asm_fprintf ( file , <STR_LIT> , ARC_TEMP_SCRATCH_REG ) ; } else { fputs ( <STR_LIT> , file ) ; assemble_name ( file , XSTR ( fnaddr , <NUM_LIT> ) ) ;"
GCC,arc,533,"Predict the next statement of this code snippet:
 <s> if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else gcc_unreachable ( ) ; break ; case MINUS : x = simplify_subtraction ( x ) ; if ( GET_CODE ( x ) != MINUS ) goto restart ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( x , <NUM_LIT> ) ) < <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; } else arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case ZERO_EXTEND : case SIGN_EXTEND : arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case UNSPEC : const char * suffix ; bool pcrel ; pcrel = false ; rtx base ; base = NULL ; gcc_assert ( XVECLEN ( x , <NUM_LIT> ) >= <NUM_LIT> ) ; switch ( XINT ( x , <NUM_LIT> ) ) { case ARC_UNSPEC_GOT : suffix = <STR_LIT> , pcrel = true ; break ; case ARC_UNSPEC_GOTOFF : suffix = <STR_LIT> ; break ; case ARC_UNSPEC_GOTOFFPC : suffix = <STR_LIT> , pcrel = true ; break ; case ARC_UNSPEC_PLT : suffix = <STR_LIT> ; break ; case UNSPEC_TLS_GD : suffix = <STR_LIT> , pcrel = true ; break ; case UNSPEC_TLS_IE : suffix = <STR_LIT> , pcrel = true ; break ; case UNSPEC_TLS_OFF : if ( XVECLEN ( x , <NUM_LIT> ) == <NUM_LIT> ) base = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; if ( SYMBOL_REF_TLS_MODEL ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == TLS_MODEL_LOCAL_EXEC || ( ! flag_pic && ! base ) ) suffix = <STR_LIT> ; else suffix = <STR_LIT> ; break ; default : suffix = <STR_LIT> ; output_operand_lossage ( <STR_LIT> , XINT ( x , <NUM_LIT> ) ) ;"
GCC,arc,534,"Predict the next statement of this code snippet:
 <s> static bool arc_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) {"
GCC,arc,535,"Predict the next statement of this code snippet:
 <s> static void arc_post_atomic_barrier ( enum memmodel model ) {"
GCC,arc,536,"Predict the next statement of this code snippet:
 <s> static void arc_post_atomic_barrier ( enum memmodel model ) { if ( need_atomic_barrier_p ( model , false ) ) emit_insn ( gen_memory_barrier ( ) ) ;"
GCC,arc,537,"Predict the next statement of this code snippet:
 <s> jump = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; dlay = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( ! JUMP_P ( jump ) || ! INSN_ANNULLED_BRANCH_P ( jump ) ) continue ; if ( ! TARGET_AT_DBR_CONDEXEC && ! INSN_FROM_TARGET_P ( dlay ) ) continue ; gcc_assert ( GET_CODE ( PATTERN ( jump ) ) == SET ) ; gcc_assert ( SET_DEST ( PATTERN ( jump ) ) == pc_rtx ) ; src = SET_SRC ( PATTERN ( jump ) ) ; gcc_assert ( GET_CODE ( src ) == IF_THEN_ELSE ) ; cond = XEXP ( src , <NUM_LIT> ) ; if ( XEXP ( src , <NUM_LIT> ) == pc_rtx ) reverse = <NUM_LIT> ; else if ( XEXP ( src , <NUM_LIT> ) == pc_rtx ) reverse = <NUM_LIT> ; else gcc_unreachable ( ) ; if ( reverse != ! INSN_FROM_TARGET_P ( dlay ) ) { machine_mode ccm = GET_MODE ( XEXP ( cond , <NUM_LIT> ) ) ;"
GCC,arc,538,"Predict the next statement of this code snippet:
 <s> enum reg_class arc_preferred_reload_class ( rtx , enum reg_class cl ) {"
GCC,arc,539,"Predict the next statement of this code snippet:
 <s> static machine_mode arc_preferred_simd_mode ( scalar_mode mode ) {"
GCC,arc,540,"Predict the next statement of this code snippet:
 <s> static void arc_pre_atomic_barrier ( enum memmodel model ) { if ( need_atomic_barrier_p ( model , true ) ) emit_insn ( gen_memory_barrier ( ) ) ;"
GCC,arc,541,"Predict the next statement of this code snippet:
 <s> if ( need_atomic_barrier_p ( model , true ) ) emit_insn ( gen_memory_barrier ( ) ) ;"
GCC,arc,542,"Predict the next statement of this code snippet:
 <s> if ( output_sdata ) fputs ( <STR_LIT> , file ) ; output_sdata = <NUM_LIT> ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == MULT ) index = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , base = XEXP ( addr , <NUM_LIT> ) ; else if ( CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) index = XEXP ( addr , <NUM_LIT> ) , base = XEXP ( addr , <NUM_LIT> ) ; else base = XEXP ( addr , <NUM_LIT> ) , index = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( OBJECT_P ( base ) ) ; arc_print_operand_address ( file , base ) ; if ( CONSTANT_P ( base ) && CONST_INT_P ( index ) ) fputc ( '+' , file ) ; else fputc ( ',' , file ) ; gcc_assert ( OBJECT_P ( index ) ) ; arc_print_operand_address ( file , index ) ; break ;"
GCC,arc,543,"Predict the next statement of this code snippet:
 <s> if ( refers_to_regno_p ( <NUM_LIT> , <NUM_LIT> , dest , <NUM_LIT> ) ) { gcc_assert ( REG_P ( src ) ) ; gcc_assert ( state == none ) ; state = destDx ; } if ( state == none ) return false ; if ( state == srcDx ) { if ( TARGET_DPFP_DISABLE_LRSR ) { rtx set = gen_rtx_SET ( dest , src ) ; rtx use1 = gen_rtx_USE ( VOIDmode , const1_rtx ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , use1 ) ) ) ; } else { rtx destHigh = simplify_gen_subreg ( SImode , dest , DFmode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ; rtx destLow = simplify_gen_subreg ( SImode , dest , DFmode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( destHigh , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , src ) , VUNSPEC_ARC_LR_HIGH ) ) ) ; emit_insn ( gen_rtx_SET ( destLow , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , src ) , VUNSPEC_ARC_LR ) ) ) ;"
GCC,arc,544,"Predict the next statement of this code snippet:
 <s> if ( SYMBOL_REF_TLS_MODEL ( op ) ) return true ; if ( ! flag_pic ) return false ; tree decl = SYMBOL_REF_DECL ( op ) ; return ! skip_local || ! decl || ! default_binds_local_p ( decl ) ; } fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( arc_raw_symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) , skip_local ) ) return true ; } else if ( fmt [ i ] == 'e' && arc_raw_symbolic_reference_mentioned_p ( XEXP ( op , i ) , skip_local ) ) return true ;"
GCC,arc,545,"Predict the next statement of this code snippet:
 <s> return ( ( ( ( r & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ) & <NUM_LIT> ) == r ; default : gcc_unreachable ( ) ;"
GCC,arc,546,"Predict the next statement of this code snippet:
 <s> if ( REG_P ( x ) && refers_to_regno_p ( regno , x ) ) return x ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( ( tem = regno_use_in ( regno , XEXP ( x , i ) ) ) ) return tem ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( ( tem = regno_use_in ( regno , XVECEXP ( x , i , j ) ) ) ) return tem ; } return NULL_RTX ;"
GCC,arc,547,"Predict the next statement of this code snippet:
 <s> int i , j ; rtx tem ; if ( REG_P ( x ) && refers_to_regno_p ( regno , x ) ) return x ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( ( tem = regno_use_in ( regno , XEXP ( x , i ) ) ) ) return tem ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( ( tem = regno_use_in ( regno , XVECEXP ( x , i , j ) ) ) ) return tem ; }"
GCC,arc,548,"Predict the next statement of this code snippet:
 <s> if ( ! link_insn ) continue ; else { rtx op , cc_clob_rtx , op0 , op1 , brcc_insn , note ; rtx cmp0 , cmp1 ; if ( find_reg_note ( link_insn , REG_SAVE_NOTE , GEN_INT ( <NUM_LIT> ) ) ) continue ; op = XEXP ( pc_target , <NUM_LIT> ) ; op0 = cmp0 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; op1 = cmp1 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == ZERO_EXTRACT && XEXP ( op0 , <NUM_LIT> ) == const1_rtx && ( GET_CODE ( op ) == EQ || GET_CODE ( op ) == NE ) ) { op0 = XEXP ( cmp0 , <NUM_LIT> ) ; op1 = XEXP ( cmp0 , <NUM_LIT> ) ; } else if ( ! register_operand ( op0 , VOIDmode ) || ! general_operand ( op1 , VOIDmode ) ) continue ; else if ( TARGET_SPFP && GET_MODE ( op0 ) == SFmode && GET_MODE ( op1 ) == SFmode ) continue ; if ( reg_set_between_p ( op0 , link_insn , insn ) ) continue ; if ( reg_set_between_p ( op1 , link_insn , insn ) ) continue ; if ( ( reg_set_between_p ( SET_DEST ( pat ) , link_insn , insn ) ) || ( reg_used_between_p ( SET_DEST ( pat ) , link_insn , insn ) ) ) continue ; if ( ! find_regno_note ( insn , REG_DEAD , CC_REG ) ) continue ; op = gen_rtx_fmt_ee ( GET_CODE ( op ) , GET_MODE ( op ) , cmp0 , cmp1 ) ; if ( ! brcc_nolimm_operator ( op , VOIDmode ) && ! long_immediate_operand ( op1 , VOIDmode ) && ( TARGET_ARC700 || ( TARGET_V2 && optimize_size ) || next_active_insn ( link_insn ) != insn ) ) continue ; if ( op0 != cmp0 ) cc_clob_rtx = gen_rtx_REG ( CC_ZNmode , CC_REG ) ; else if ( ( offset >= - <NUM_LIT> && offset < <NUM_LIT> ) && rtx_equal_p ( op1 , const0_rtx ) && compact_register_operand ( op0 , VOIDmode ) && ( GET_CODE ( op ) == EQ || GET_CODE ( op ) == NE ) ) cc_clob_rtx = gen_rtx_REG ( CC_Zmode , CC_REG ) ;"
GCC,arc,549,"Predict the next statement of this code snippet:
 <s> static void arc_reorg_loops ( void ) {"
GCC,arc,550,"Predict the next statement of this code snippet:
 <s> reorg_loops ( true , & arc_doloop_hooks ) ;"
GCC,arc,551,"Predict the next statement of this code snippet:
 <s> gcc_assert ( end_reg > <NUM_LIT> ) ; if ( arc_frame_pointer_needed ( ) && offset ) { frame_move ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; frame_allocated = offset ; offset = <NUM_LIT> ; } if ( restore_fp ) frame_allocated += frame_restore_reg ( hard_frame_pointer_rtx , <NUM_LIT> ) ; if ( offset ) { frame_stack_add ( offset ) ; frame_allocated += offset ; offset = <NUM_LIT> ; } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( ( return_p ? <NUM_LIT> : <NUM_LIT> ) + nregs + <NUM_LIT> ) ) ; indx = <NUM_LIT> ; if ( return_p ) { reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; XVECEXP ( insn , <NUM_LIT> , indx ++ ) = ret_rtx ; XVECEXP ( insn , <NUM_LIT> , indx ++ ) = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , reg ) ) ; frame_allocated += UNITS_PER_WORD ; } else { XVECEXP ( insn , <NUM_LIT> , nregs ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ; } for ( regno = start_reg , off = <NUM_LIT> ; regno <= end_reg ; regno ++ , indx ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ;"
GCC,arc,552,"Predict the next statement of this code snippet:
 <s> if ( early_blink_restore ) { rtx addr = plus_constant ( Pmode , stack_pointer_rtx , offs ) ; reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx insn = frame_move_inc ( reg , gen_frame_mem ( Pmode , addr ) , stack_pointer_rtx , NULL_RTX ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; restore_blink = false ; } if ( gmask ) for ( i = <NUM_LIT> ; i <= GMASK_LEN ; i ++ ) { machine_mode restore_mode = SImode ; if ( TARGET_LL64 && ( ( i % <NUM_LIT> ) == <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << ( i + <NUM_LIT> ) ) ) != <NUM_LIT> ) ) restore_mode = DImode ; else if ( ( gmask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) continue ; reg = gen_rtx_REG ( restore_mode , i ) ; offs = <NUM_LIT> ; switch ( restore_mode ) { case E_DImode : if ( ( GMASK_LEN - __builtin_clzll ( gmask ) ) == ( i + <NUM_LIT> ) && early_blink_restore ) offs = <NUM_LIT> ; break ; case E_SImode : if ( ( GMASK_LEN - __builtin_clzll ( gmask ) ) == i && early_blink_restore ) offs = <NUM_LIT> ; break ;"
GCC,arc,553,"Predict the next statement of this code snippet:
 <s> else if ( ( fn_type & ARC_FUNCTION_ILINK2 ) != <NUM_LIT> ) regno = ILINK2_REG ; else gcc_unreachable ( ) ; } else if ( ARC_NORMAL_P ( fn_type ) || ARC_NAKED_P ( fn_type ) ) regno = RETURN_ADDR_REGNUM ; gcc_assert ( regno != <NUM_LIT> ) ;"
GCC,arc,554,"Predict the next statement of this code snippet:
 <s> if ( count != <NUM_LIT> ) return const0_rtx ;"
GCC,arc,555,"Predict the next statement of this code snippet:
 <s> rtx arc_return_addr_rtx ( int count , ATTRIBUTE_UNUSED rtx frame ) {"
GCC,arc,556,"Predict the next statement of this code snippet:
 <s> else { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - <NUM_LIT> || size > ( TARGET_V2 ? <NUM_LIT> : <NUM_LIT> ) ) ; }"
GCC,arc,557,"Predict the next statement of this code snippet:
 <s> insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + ( save_fp ? <NUM_LIT> : <NUM_LIT> ) + <NUM_LIT> ) ) ; indx = <NUM_LIT> ; reg = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - nregs * UNITS_PER_WORD ) ) ; RTX_FRAME_RELATED_P ( reg ) = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; save_blink = false ; } for ( regno = start_reg ; regno <= end_reg ; regno ++ , indx ++ , off -= UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; } if ( save_fp ) { mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , hard_frame_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( hard_frame_pointer_rtx , stack_pointer_rtx ) ;"
GCC,arc,558,"Predict the next statement of this code snippet:
 <s> if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = <NUM_LIT> ; } if ( reg_size || offset ) { frame_stack_add ( offset - reg_size ) ; frame_allocated += nregs * UNITS_PER_WORD - offset ; offset = <NUM_LIT> ; } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + <NUM_LIT> ) ) ; indx = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , nregs ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ; for ( regno = start_reg , indx = <NUM_LIT> , off = <NUM_LIT> ; regno <= end_reg ; regno ++ , indx ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; } insn = frame_insn ( insn ) ; for ( regno = start_reg , off = <NUM_LIT> ; regno <= end_reg ; regno ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } if ( arc_must_save_return_addr ( cfun ) ) { emit_insn ( gen_rtx_SET ( gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_MEM ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , reg_size ) ) ) ) ; } for ( regno = <NUM_LIT> ; regno <= GMASK_LEN ; regno ++ ) {"
GCC,arc,559,"Predict the next statement of this code snippet:
 <s> int frame_allocated = <NUM_LIT> ; int i ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = <NUM_LIT> ; } if ( gmask ) for ( i = GMASK_LEN ; i >= <NUM_LIT> ; i -- ) { machine_mode save_mode = SImode ; if ( TARGET_LL64 && ( ( i - <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ) ) { save_mode = DImode ; -- i ; } else if ( ( gmask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) continue ;"
GCC,arc,560,"Predict the next statement of this code snippet:
 <s> if ( gmask ) for ( i = GMASK_LEN ; i >= <NUM_LIT> ; i -- ) { machine_mode save_mode = SImode ;"
GCC,arc,561,"Predict the next statement of this code snippet:
 <s> bool arc_scheduling_not_expected ( void ) { return cfun -> machine -> arc_reorg_started ;"
GCC,arc,562,"Predict the next statement of this code snippet:
 <s> rtx set = single_set ( insn ) ; if ( set && GET_MODE ( SET_SRC ( set ) ) == DFmode && GET_CODE ( SET_SRC ( set ) ) == REG ) { return priority + <NUM_LIT> ; }"
GCC,arc,563,"Predict the next statement of this code snippet:
 <s> if ( set && GET_MODE ( SET_SRC ( set ) ) == DFmode && GET_CODE ( SET_SRC ( set ) ) == REG ) { return priority + <NUM_LIT> ; }"
GCC,arc,564,"Predict the next statement of this code snippet:
 <s> case TUNE_ARCHS4XD : return <NUM_LIT> ; default : break ; }"
GCC,arc,565,"Predict the next statement of this code snippet:
 <s> addr = find_replacement ( & XEXP ( mem , <NUM_LIT> ) ) ; } } else { gcc_assert ( MEM_P ( x ) ) ; addr = XEXP ( x , <NUM_LIT> ) ; addr = simplify_rtx ( addr ) ; } if ( addr && GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( ! RTX_OK_FOR_OFFSET_P ( mode , XEXP ( addr , <NUM_LIT> ) ) ) ) { switch ( mode ) { case E_QImode : sri -> icode = in_p ? CODE_FOR_reload_qi_load : CODE_FOR_reload_qi_store ; break ; case E_HImode : sri -> icode = in_p ? CODE_FOR_reload_hi_load : CODE_FOR_reload_hi_store ; break ;"
GCC,arc,566,"Predict the next statement of this code snippet:
 <s> void arc_secondary_reload_conv ( rtx reg , rtx mem , rtx scratch , bool store_p ) { rtx addr ; gcc_assert ( GET_CODE ( mem ) == MEM ) ; addr = XEXP ( mem , <NUM_LIT> ) ;"
GCC,arc,567,"Predict the next statement of this code snippet:
 <s> gcc_assert ( GET_CODE ( mem ) == MEM ) ; addr = XEXP ( mem , <NUM_LIT> ) ; emit_move_insn ( scratch , addr ) ; mem = replace_equiv_address_nv ( mem , scratch ) ; if ( store_p ) emit_insn ( gen_rtx_SET ( mem , reg ) ) ;"
GCC,arc,568,"Predict the next statement of this code snippet:
 <s> machine_mode arc_select_cc_mode ( enum rtx_code op , rtx x , rtx y ) { machine_mode mode = GET_MODE ( x ) ; rtx x1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && y == const0_rtx && ( op == EQ || op == NE || ( ( op == LT || op == GE ) && GET_MODE_SIZE ( GET_MODE ( x ) ) <= <NUM_LIT> ) ) ) return CC_ZNmode ; if ( mode == SImode && GET_CODE ( y ) == NEG && ( op == EQ || op == NE ) ) return CC_ZNmode ; if ( mode == SImode && ( op == EQ || op == NE ) && CONST_INT_P ( y ) && ( ( INTVAL ( y ) - <NUM_LIT> ) & INTVAL ( y ) ) == <NUM_LIT> && INTVAL ( y ) ) return CC_Zmode ; if ( mode == SImode && ( op == EQ || op == NE ) && CONST_INT_P ( y ) && GET_CODE ( x ) == AND && CONST_INT_P ( ( x1 = XEXP ( x , <NUM_LIT> ) ) ) && ( ( INTVAL ( x1 ) + <NUM_LIT> ) & INTVAL ( x1 ) ) == <NUM_LIT> && ( ~ INTVAL ( x1 ) | INTVAL ( y ) ) < <NUM_LIT> && ( ~ INTVAL ( x1 ) | INTVAL ( y ) ) > - <NUM_LIT> ) return CC_Zmode ; if ( GET_MODE ( x ) == SImode && ( op == LTU || op == GEU ) && GET_CODE ( x ) == PLUS && ( rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , y ) || rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , y ) ) ) return CC_Cmode ; if ( TARGET_ARGONAUT_SET && ( ( mode == SFmode && TARGET_SPFP ) || ( mode == DFmode && TARGET_DPFP ) ) ) switch ( op ) { case EQ : case NE : case UNEQ : case LTGT : case ORDERED : case UNORDERED : return CC_FPXmode ; case LT : case UNGE : case GT : case UNLE : return CC_FP_GTmode ; case LE : case UNGT : case GE : case UNLT : return CC_FP_GEmode ; default : gcc_unreachable ( ) ; } else if ( TARGET_HARD_FLOAT && ( ( mode == SFmode && TARGET_FP_SP_BASE ) || ( mode == DFmode && TARGET_FP_DP_BASE ) ) ) switch ( op ) { case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : return CC_FPUmode ; case LT : case LE : case GT : case GE : return CC_FPUEmode ; case LTGT : case UNEQ : return CC_FPU_UNEQmode ; default : gcc_unreachable ( ) ; } else if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && TARGET_OPTFPE ) { switch ( op ) { case EQ : case NE : return CC_Zmode ; case LT : case UNGE :"
GCC,arc,569,"Predict the next statement of this code snippet:
 <s> bool arc_sets_cc_p ( rtx_insn * insn ) { if ( NONJUMP_INSN_P ( insn ) ) if ( rtx_sequence * seq = dyn_cast < rtx_sequence * > ( PATTERN ( insn ) ) ) insn = seq -> insn ( seq -> len ( ) - <NUM_LIT> ) ; return arc_attr_type ( insn ) == TYPE_COMPARE ;"
GCC,arc,570,"Predict the next statement of this code snippet:
 <s> if ( FUNCTION_ARG_REGNO_P ( first_anon_arg ) ) { int first_reg_offset = first_anon_arg ; if ( ! no_rtl ) { rtx regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( <NUM_LIT> ) ) ) ;"
GCC,arc,571,"Predict the next statement of this code snippet:
 <s> switch ( get_arc_condition_code ( comparison ) ) { case ARC_CC_EQ : case ARC_CC_NE : return offset >= - <NUM_LIT> && offset <= <NUM_LIT> ;"
GCC,arc,572,"Predict the next statement of this code snippet:
 <s> int is_short = arc_verify_short ( insn , cfun -> machine -> unalign , - <NUM_LIT> ) ;"
GCC,arc,573,"Predict the next statement of this code snippet:
 <s> const char * arc_short_long ( rtx_insn * insn , const char * s_tmpl , const char * l_tmpl ) {"
GCC,arc,574,"Predict the next statement of this code snippet:
 <s> static reg_class_t arc_spill_class ( reg_class_t , machine_mode ) {"
GCC,arc,575,"Predict the next statement of this code snippet:
 <s> return GENERAL_REGS ;"
GCC,arc,576,"Predict the next statement of this code snippet:
 <s> label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; emit_insn ( gen_arc_load_exclusivesi ( rval , mem ) ) ; mode = SELECT_CC_MODE ( NE , rval , oldval ) ; cond = gen_rtx_REG ( mode , CC_REG ) ; emit_insn ( gen_rtx_SET ( cond , gen_rtx_COMPARE ( mode , rval , oldval ) ) ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; emit_insn ( gen_arc_store_exclusivesi ( mem , newval ) ) ; if ( ! is_weak ) { cond = gen_rtx_REG ( CC_Zmode , CC_REG ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } if ( mod_f != MEMMODEL_RELAXED ) emit_label ( label2 ) ; arc_post_atomic_barrier ( mod_s ) ; if ( mod_f == MEMMODEL_RELAXED ) emit_label ( label2 ) ;"
GCC,arc,577,"Predict the next statement of this code snippet:
 <s> case <NUM_LIT> : maskx = <NUM_LIT> << ( __builtin_ffs ( mask ) - <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_IOR ( SImode , op1 , GEN_INT ( maskx ) ) ) ) ; mask &= ~ maskx ; op1 = operands [ <NUM_LIT> ] ; case <NUM_LIT> : maskx = <NUM_LIT> << ( __builtin_ffs ( mask ) - <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_IOR ( SImode , op1 , GEN_INT ( maskx ) ) ) ) ; break ; case <NUM_LIT> :"
GCC,arc,578,"Predict the next statement of this code snippet:
 <s> if ( GET_MODE ( operands [ <NUM_LIT> ] ) == V2SImode ) { intval0 = INTVAL ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ) ; intval1 = INTVAL ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ) ; } else { intval1 = INTVAL ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ) << <NUM_LIT> ; intval1 |= INTVAL ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ) & <NUM_LIT> ; intval0 = INTVAL ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ) << <NUM_LIT> ; intval0 |= INTVAL ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ) & <NUM_LIT> ; } xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; xop [ <NUM_LIT> ] = GEN_INT ( trunc_int_for_mode ( intval0 , SImode ) ) ; xop [ <NUM_LIT> ] = GEN_INT ( trunc_int_for_mode ( intval1 , SImode ) ) ; emit_move_insn ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; emit_move_insn ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; return ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {"
GCC,arc,579,"Predict the next statement of this code snippet:
 <s> HOST_WIDE_INT shift = __builtin_ffs ( ival ) ; shimm = ( ival >> ( shift - <NUM_LIT> ) ) & <NUM_LIT> ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , GEN_INT ( shimm ) ) ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_ASHIFT ( mode , operands [ <NUM_LIT> ] , GEN_INT ( shift - <NUM_LIT> ) ) ) ) ; return true ; } if ( ( ival & ~ <NUM_LIT> ) == <NUM_LIT> ) { shimm = ( ival * <NUM_LIT> + <NUM_LIT> ) & <NUM_LIT> ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_ROTATERT ( mode , GEN_INT ( shimm ) , const1_rtx ) ) ) ; return true ; } if ( IS_POWEROF2_P ( ival + <NUM_LIT> ) ) {"
GCC,arc,580,"Predict the next statement of this code snippet:
 <s> rtx out_addr , in_addr ; if ( ! producer ) return false ; if ( ! consumer ) return false ; out_set = single_set ( producer ) ; if ( out_set ) { out_addr = SET_DEST ( out_set ) ; if ( ! out_addr ) return false ; if ( GET_CODE ( out_addr ) == ZERO_EXTEND || GET_CODE ( out_addr ) == SIGN_EXTEND ) out_addr = XEXP ( out_addr , <NUM_LIT> ) ;"
GCC,arc,581,"Predict the next statement of this code snippet:
 <s> if ( out_set ) { out_addr = SET_DEST ( out_set ) ; if ( ! out_addr ) return false ; if ( GET_CODE ( out_addr ) == ZERO_EXTEND || GET_CODE ( out_addr ) == SIGN_EXTEND ) out_addr = XEXP ( out_addr , <NUM_LIT> ) ; if ( ! MEM_P ( out_addr ) ) return false ; in_set = single_set ( consumer ) ; if ( in_set ) { in_addr = SET_SRC ( in_set ) ; if ( ! in_addr ) return false ; if ( GET_CODE ( in_addr ) == ZERO_EXTEND || GET_CODE ( in_addr ) == SIGN_EXTEND ) in_addr = XEXP ( in_addr , <NUM_LIT> ) ; if ( ! MEM_P ( in_addr ) ) return false ; in_addr = XEXP ( in_addr , <NUM_LIT> ) ; out_addr = XEXP ( out_addr , <NUM_LIT> ) ; return exp_equiv_p ( in_addr , out_addr , <NUM_LIT> , true ) ;"
GCC,arc,582,"Predict the next statement of this code snippet:
 <s> bool arc_store_addr_hazard_p ( rtx_insn * producer , rtx_insn * consumer ) { if ( TARGET_ARC700 && ( arc_tune != ARC_TUNE_ARC7XX ) ) return true ;"
GCC,arc,583,"Predict the next statement of this code snippet:
 <s> static bool arc_symbol_binds_local_p ( const_rtx x ) {"
GCC,arc,584,"Predict the next statement of this code snippet:
 <s> next = next_nonnote_insn ( label ) ;"
GCC,arc,585,"Predict the next statement of this code snippet:
 <s> gcc_assert ( GET_CODE ( label ) == CODE_LABEL || ( GET_CODE ( label ) == NOTE && NOTE_KIND ( label ) == NOTE_INSN_DELETED_LABEL ) ) ;"
GCC,arc,586,"Predict the next statement of this code snippet:
 <s> void arc_toggle_unalign ( void ) {"
GCC,arc,587,"Predict the next statement of this code snippet:
 <s> void arc_toggle_unalign ( void ) {"
GCC,arc,588,"Predict the next statement of this code snippet:
 <s> char * lo0 = lo ; for ( ; * up ; up ++ , lo ++ ) * lo = TOLOWER ( * up ) ; * lo = '\0' ; return lo0 ;"
GCC,arc,589,"Predict the next statement of this code snippet:
 <s> int arc_unalign_branch_p ( rtx branch ) { rtx note ; if ( ! TARGET_UNALIGN_BRANCH ) return <NUM_LIT> ; if ( get_attr_delay_slot_filled ( branch ) == DELAY_SLOT_FILLED_YES && ! NEXT_INSN ( branch ) -> deleted ( ) ) return <NUM_LIT> ; note = find_reg_note ( branch , REG_BR_PROB , <NUM_LIT> ) ;"
GCC,arc,590,"Predict the next statement of this code snippet:
 <s> int arc_unalign_branch_p ( rtx branch ) { rtx note ; if ( ! TARGET_UNALIGN_BRANCH ) return <NUM_LIT> ; if ( get_attr_delay_slot_filled ( branch ) == DELAY_SLOT_FILLED_YES && ! NEXT_INSN ( branch ) -> deleted ( ) ) return <NUM_LIT> ; note = find_reg_note ( branch , REG_BR_PROB , <NUM_LIT> ) ;"
GCC,arc,591,"Predict the next statement of this code snippet:
 <s> static rtx arc_unspec_offset ( rtx loc , int unspec ) { return gen_rtx_CONST ( Pmode , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , loc ) , unspec ) ) ;"
GCC,arc,592,"Predict the next statement of this code snippet:
 <s> if ( flag_pic ) return false ; if ( SYMBOL_REF_SMALL_P ( symbol ) ) return false ; return default_use_anchors_for_symbol_p ( symbol ) ;"
GCC,arc,593,"Predict the next statement of this code snippet:
 <s> if ( op == MOVE_BY_PIECES ) return false ;"
GCC,arc,594,"Predict the next statement of this code snippet:
 <s> if ( op == MOVE_BY_PIECES ) return false ; return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ;"
GCC,arc,595,"Predict the next statement of this code snippet:
 <s> case E_V2SImode : return TARGET_PLUS_QMACW ; case E_V4SImode : case E_V8HImode : return TARGET_SIMD_SET ; default : return false ;"
GCC,arc,596,"Predict the next statement of this code snippet:
 <s> static bool arc_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case E_V2HImode : return TARGET_PLUS_DMPY ; case E_V4HImode : case E_V2SImode : return TARGET_PLUS_QMACW ; case E_V4SImode :"
GCC,arc,597,"Predict the next statement of this code snippet:
 <s> static int arc_verify_short ( rtx_insn * insn , int , int check_attr ) { enum attr_iscompact iscompact ; if ( check_attr > <NUM_LIT> ) { iscompact = get_attr_iscompact ( insn ) ; if ( iscompact == ISCOMPACT_FALSE ) return <NUM_LIT> ; } return ( get_attr_length ( insn ) & <NUM_LIT> ) != <NUM_LIT> ;"
GCC,arc,598,"Predict the next statement of this code snippet:
 <s> static bool arc_warn_func_return ( tree decl ) {"
GCC,arc,599,"Predict the next statement of this code snippet:
 <s> int arc_write_ext_corereg ( rtx insn ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) { const_rtx x = * iter ; switch ( GET_CODE ( x ) ) {"
GCC,arc,600,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , XEXP ( dest , <NUM_LIT> ) == pc_rtx ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,601,"Predict the next statement of this code snippet:
 <s> rtx dest = ( GET_CODE ( pat ) == PARALLEL ? SET_SRC ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) : SET_SRC ( pat ) ) ; int dest_uid ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , XEXP ( dest , <NUM_LIT> ) == pc_rtx ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,602,"Predict the next statement of this code snippet:
 <s> case CONST : case CONST_INT : return true ; default : error ( <STR_LIT> <STR_LIT> ) ; break ; }"
GCC,arc,603,"Predict the next statement of this code snippet:
 <s> return new pass_arc_ifcvt ( m_ctxt ) ;"
GCC,arc,604,"Predict the next statement of this code snippet:
 <s> addr = XEXP ( op , <NUM_LIT> ) ; if ( ! legitimate_small_data_address_p ( addr , mode ) ) return false ; if ( ! short_p || size == <NUM_LIT> ) return true ; align = get_symbol_alignment ( addr ) ; switch ( mode ) {"
GCC,arc,605,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( pat ) == SET ) { rtx src = SET_SRC ( pat ) ; if ( COMMUTATIVE_P ( src ) ) { rtx src0 = XEXP ( src , <NUM_LIT> ) ; rtx src1 = XEXP ( src , <NUM_LIT> ) ; rtx dst = SET_DEST ( pat ) ; if ( rtx_equal_p ( src1 , dst ) && ! rtx_equal_p ( src0 , dst ) && REG_P ( src0 ) ) pat = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( GET_CODE ( src ) , GET_MODE ( src ) , src1 , src0 ) ) ; } } if ( RTX_FRAME_RELATED_P ( insn ) ) { gcc_assert ( annulled ) ; rtx note = alloc_reg_note ( REG_FRAME_RELATED_EXPR , pat , REG_NOTES ( insn ) ) ; validate_change ( insn , & REG_NOTES ( insn ) , note , <NUM_LIT> ) ;"
GCC,arc,606,"Predict the next statement of this code snippet:
 <s> return simplify_gen_subreg ( SImode , in , DImode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,607,"Predict the next statement of this code snippet:
 <s> rtx disi_highpart ( rtx in ) {"
GCC,arc,608,"Predict the next statement of this code snippet:
 <s> void emit_shift ( enum rtx_code code , rtx op0 , rtx op1 , rtx op2 ) {"
GCC,arc,609,"Predict the next statement of this code snippet:
 <s> void emit_shift ( enum rtx_code code , rtx op0 , rtx op1 , rtx op2 ) { rtx shift = gen_rtx_fmt_ee ( code , SImode , op1 , op2 ) ; rtx pat = ( ( shift4_operator ( shift , SImode ) ? gen_shift_si3 : gen_shift_si3_loop ) ( op0 , op1 , op2 , shift ) ) ;"
GCC,arc,610,"Predict the next statement of this code snippet:
 <s> add_reg_br_prob_note ( jump , profile_probability :: very_unlikely ( ) ) ;"
GCC,arc,611,"Predict the next statement of this code snippet:
 <s> add_reg_br_prob_note ( jump , profile_probability :: very_unlikely ( ) ) ;"
GCC,arc,612,"Predict the next statement of this code snippet:
 <s> return arc_predicate_delay_insns ( ) ;"
GCC,arc,613,"Predict the next statement of this code snippet:
 <s> virtual unsigned int execute ( function * ) { return arc_predicate_delay_insns ( ) ;"
GCC,arc,614,"Predict the next statement of this code snippet:
 <s> const_rtx dest = XEXP ( x , <NUM_LIT> ) ;"
GCC,arc,615,"Predict the next statement of this code snippet:
 <s> if ( ( reg = decode_reg_name_and_count ( opt -> arg , & nregs ) ) >= <NUM_LIT> ) for ( j = reg ; j < reg + nregs ; j ++ ) SET_HARD_REG_BIT ( overrideregs , j ) ; break ;"
GCC,arc,616,"Predict the next statement of this code snippet:
 <s> gcc_assert ( ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; if ( ! offset ) return NULL_RTX ;"
GCC,arc,617,"Predict the next statement of this code snippet:
 <s> gcc_assert ( ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; if ( ! offset ) return NULL_RTX ; return frame_move ( reg , plus_constant ( Pmode , reg , offset ) ) ;"
GCC,arc,618,"Predict the next statement of this code snippet:
 <s> x = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( x ) = <NUM_LIT> ; return x ;"
GCC,arc,619,"Predict the next statement of this code snippet:
 <s> RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ;"
GCC,arc,620,"Predict the next statement of this code snippet:
 <s> if ( ! addr || GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) add_reg_note ( insn , REG_INC , reg ) ; return insn ;"
GCC,arc,621,"Predict the next statement of this code snippet:
 <s> } else addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; insn = frame_move_inc ( reg , addr , stack_pointer_rtx , <NUM_LIT> ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; if ( reg == hard_frame_pointer_rtx ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( GET_MODE ( reg ) ) + offset ) ) ;"
GCC,arc,622,"Predict the next statement of this code snippet:
 <s> rtx tmp = plus_constant ( Pmode , stack_pointer_rtx , offset + GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ; addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ) ; } else addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; insn = frame_move_inc ( reg , addr , stack_pointer_rtx , <NUM_LIT> ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; if ( reg == hard_frame_pointer_rtx ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( GET_MODE ( reg ) ) + offset ) ) ; else add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( GET_MODE ( reg ) ) + offset ) ) ) ;"
GCC,arc,623,"Predict the next statement of this code snippet:
 <s> rtx tmp = plus_constant ( Pmode , stack_pointer_rtx , offset - GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ; addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ) ; } else addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ;"
GCC,arc,624,"Predict the next statement of this code snippet:
 <s> static int frame_save_reg ( rtx reg , HOST_WIDE_INT offset ) { rtx addr ; if ( offset ) { rtx tmp = plus_constant ( Pmode , stack_pointer_rtx , offset - GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ; addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ) ; } else addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ;"
GCC,arc,625,"Predict the next statement of this code snippet:
 <s> return frame_add ( stack_pointer_rtx , offset ) ;"
GCC,arc,626,"Predict the next statement of this code snippet:
 <s> static rtx frame_stack_add ( HOST_WIDE_INT offset ) {"
GCC,arc,627,"Predict the next statement of this code snippet:
 <s> virtual bool gate ( function * ) { return flag_delayed_branch ;"
GCC,arc,628,"Predict the next statement of this code snippet:
 <s> virtual bool gate ( function * ) {"
GCC,arc,629,"Predict the next statement of this code snippet:
 <s> rtx gen_acc1 ( void ) {"
GCC,arc,630,"Predict the next statement of this code snippet:
 <s> return gen_rtx_REG ( SImode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,631,"Predict the next statement of this code snippet:
 <s> rtx gen_acc2 ( void ) { return gen_rtx_REG ( SImode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,632,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( operands [ i ] ) == SUBREG ) { tmp = SUBREG_REG ( operands [ i ] ) ; gcc_assert ( GET_MODE ( operands [ i ] ) == GET_MODE ( tmp ) ) ; operands [ i ] = tmp ; } } if ( load && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( base ) ) return false ; if ( load && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) ) return false ; if ( offsets [ <NUM_LIT> ] > offsets [ <NUM_LIT> ] ) { gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; }"
GCC,arc,633,"Predict the next statement of this code snippet:
 <s> rtx cur_base , cur_offset , tmp ; rtx base = NULL_RTX ; for ( i = <NUM_LIT> ; i < nops ; i ++ ) { if ( ! mem_ok_for_ldd_std ( operands [ nops + i ] , & cur_base , & cur_offset ) ) return false ; if ( i == <NUM_LIT> ) base = cur_base ; else if ( REGNO ( base ) != REGNO ( cur_base ) ) return false ; offsets [ i ] = INTVAL ( cur_offset ) ; if ( GET_CODE ( operands [ i ] ) == SUBREG ) { tmp = SUBREG_REG ( operands [ i ] ) ; gcc_assert ( GET_MODE ( operands [ i ] ) == GET_MODE ( tmp ) ) ; operands [ i ] = tmp ; } } if ( load && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( base ) ) return false ;"
GCC,arc,634,"Predict the next statement of this code snippet:
 <s> case GEU : return ARC_CC_HS ; default : gcc_unreachable ( ) ; } case E_CC_ZNmode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; case GE : return ARC_CC_P ; case LT : return ARC_CC_N ; case GT : return ARC_CC_PNZ ; default : gcc_unreachable ( ) ; } case E_CC_Zmode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; default : gcc_unreachable ( ) ; } case E_CC_Cmode : switch ( GET_CODE ( comparison ) ) { case LTU : return ARC_CC_C ; case GEU : return ARC_CC_NC ; default : gcc_unreachable ( ) ; } case E_CC_FP_GTmode : if ( TARGET_ARGONAUT_SET && TARGET_SPFP ) switch ( GET_CODE ( comparison ) ) { case GT : return ARC_CC_N ; case UNLE : return ARC_CC_P ; default : gcc_unreachable ( ) ; } else switch ( GET_CODE ( comparison ) ) { case GT : return ARC_CC_HI ; case UNLE : return ARC_CC_LS ; default : gcc_unreachable ( ) ; } case E_CC_FP_GEmode : switch ( GET_CODE ( comparison ) ) { case GE : return ARC_CC_HS ; case UNLT : return ARC_CC_LO ; default : gcc_unreachable ( ) ; } case E_CC_FP_UNEQmode : switch ( GET_CODE ( comparison ) ) { case UNEQ : return ARC_CC_EQ ; case LTGT : return ARC_CC_NE ; default : gcc_unreachable ( ) ;"
GCC,arc,635,"Predict the next statement of this code snippet:
 <s> case CONST : return get_symbol_alignment ( XEXP ( x , <NUM_LIT> ) ) ; case PLUS : gcc_assert ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) ; return get_symbol_alignment ( XEXP ( x , <NUM_LIT> ) ) ; default : return <NUM_LIT> ; } if ( decl ) align = DECL_ALIGN ( decl ) ;"
GCC,arc,636,"Predict the next statement of this code snippet:
 <s> switch ( GET_CODE ( x ) ) { case SYMBOL_REF : decl = SYMBOL_REF_DECL ( x ) ; break ; case CONST : return get_symbol_alignment ( XEXP ( x , <NUM_LIT> ) ) ; case PLUS :"
GCC,arc,637,"Predict the next statement of this code snippet:
 <s> else { emit_insn_before ( gen_addsi3 ( loop -> iter_reg , loop -> iter_reg , constm1_rtx ) , loop -> loop_end ) ; test = gen_rtx_NE ( VOIDmode , loop -> iter_reg , const0_rtx ) ; insn = emit_jump_insn_before ( gen_cbranchsi4 ( test , loop -> iter_reg , const0_rtx , loop -> start_label ) , loop -> loop_end ) ; } JUMP_LABEL ( insn ) = loop -> start_label ;"
GCC,arc,638,"Predict the next statement of this code snippet:
 <s> last_insn = emit_insn_after ( gen_nopv ( ) , last_insn ) ; } add_reg_note ( last_insn , REG_SAVE_NOTE , GEN_INT ( <NUM_LIT> ) ) ; loop -> last_insn = last_insn ; iter_reg = loop -> iter_reg ; gcc_assert ( REG_P ( iter_reg ) ) ; entry_edge = NULL ; FOR_EACH_VEC_SAFE_ELT ( loop -> incoming , i , entry_edge ) if ( entry_edge -> flags & EDGE_FALLTHRU ) break ; if ( entry_edge == NULL ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , loop -> loop_no ) ; return false ; } end_label = gen_label_rtx ( ) ; loop -> end_label = end_label ; entry_bb = entry_edge -> src ; start_sequence ( ) ; if ( need_fix ) { emit_insn ( gen_rtx_SET ( lp_reg , iter_reg ) ) ; SET_HARD_REG_BIT ( loop -> regs_set_in_loop , LP_COUNT ) ; iter_reg = lp_reg ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , loop -> loop_no ) ; } } insn = emit_insn ( gen_arc_lp ( loop -> start_label , loop -> end_label ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; entry_after = BB_END ( entry_bb ) ; if ( ! single_succ_p ( entry_bb ) || vec_safe_length ( loop -> incoming ) > <NUM_LIT> || ! entry_after ) { basic_block new_bb ; edge e ; edge_iterator ei ; emit_insn_before ( seq , BB_HEAD ( loop -> head ) ) ; seq = emit_label_before ( gen_label_rtx ( ) , seq ) ; new_bb = create_basic_block ( seq , insn , entry_bb ) ; FOR_EACH_EDGE ( e , ei , loop -> incoming ) { if ( ! ( e -> flags & EDGE_FALLTHRU ) ) redirect_edge_and_branch_force ( e , new_bb ) ; else redirect_edge_succ ( e , new_bb ) ; } make_edge ( new_bb , loop -> head , <NUM_LIT> ) ; } else { while ( DEBUG_INSN_P ( entry_after ) || ( NOTE_P ( entry_after ) && NOTE_KIND ( entry_after ) != NOTE_INSN_BASIC_BLOCK && NOTE_KIND ( entry_after ) != NOTE_INSN_CALL_ARG_LOCATION ) ) entry_after = NEXT_INSN ( entry_after ) ; entry_after = next_nonnote_insn_bb ( entry_after ) ;"
GCC,arc,639,"Predict the next statement of this code snippet:
 <s> rtx reg ; if ( ! JUMP_P ( insn ) || recog_memoized ( insn ) != CODE_FOR_loop_end ) return NULL_RTX ; reg = SET_DEST ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; if ( ! REG_P ( reg ) ) return NULL_RTX ;"
GCC,arc,640,"Predict the next statement of this code snippet:
 <s> if ( ! JUMP_P ( insn ) || recog_memoized ( insn ) != CODE_FOR_loop_end ) return NULL_RTX ; reg = SET_DEST ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ;"
GCC,arc,641,"Predict the next statement of this code snippet:
 <s> i = strlen ( cstr ) ; str = ( char * ) alloca ( i + <NUM_LIT> ) ; memcpy ( str , cstr , i + <NUM_LIT> ) ; blink = - <NUM_LIT> ; lpcount = - <NUM_LIT> ; dash = strchr ( str , '-' ) ; if ( ! dash ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> ) ; return ; } * dash = '\0' ; comma = strchr ( dash + <NUM_LIT> , ',' ) ; if ( comma ) * comma = '\0' ; first = decode_reg_name ( str ) ; if ( first != <NUM_LIT> ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> ) ; return ; } if ( ! strcmp ( dash + <NUM_LIT> , <STR_LIT> ) ) last = <NUM_LIT> ; else last = decode_reg_name ( dash + <NUM_LIT> ) ; if ( last < <NUM_LIT> ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } if ( ! ( last & <NUM_LIT> ) ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash = '-' ; if ( first > last ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> , str , dash + <NUM_LIT> ) ; return ; } while ( comma ) { * comma = ',' ; str = comma + <NUM_LIT> ; comma = strchr ( str , ',' ) ; if ( comma ) * comma = '\0' ; xreg = decode_reg_name ( str ) ; switch ( xreg ) { case <NUM_LIT> : blink = <NUM_LIT> ; break ;"
GCC,arc,642,"Predict the next statement of this code snippet:
 <s> if ( ! strcmp ( dash + <NUM_LIT> , <STR_LIT> ) ) last = <NUM_LIT> ; else last = decode_reg_name ( dash + <NUM_LIT> ) ; if ( last < <NUM_LIT> ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } if ( ! ( last & <NUM_LIT> ) ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash = '-' ; if ( first > last ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> , str , dash + <NUM_LIT> ) ; return ; } while ( comma ) { * comma = ',' ; str = comma + <NUM_LIT> ; comma = strchr ( str , ',' ) ; if ( comma ) * comma = '\0' ; xreg = decode_reg_name ( str ) ; switch ( xreg ) { case <NUM_LIT> : blink = <NUM_LIT> ; break ; case <NUM_LIT> : lpcount = <NUM_LIT> ; break ; default : warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> , str ) ;"
GCC,arc,643,"Predict the next statement of this code snippet:
 <s> rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! CALL_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) pat = COND_EXEC_CODE ( pat ) ;"
GCC,arc,644,"Predict the next statement of this code snippet:
 <s> if ( ! CALL_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) pat = COND_EXEC_CODE ( pat ) ; pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( pat ) == SET ) pat = SET_SRC ( pat ) ; pat = XEXP ( XEXP ( pat , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( pat ) == SYMBOL_REF && arc_is_jli_call_p ( pat ) ) arc_add_jli_section ( pat ) ; }"
GCC,arc,645,"Predict the next statement of this code snippet:
 <s> if ( GET_CODE ( x ) != PLUS ) return false ; if ( ! RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , ( strict ) ) ) return false ; if ( ( ( index && RTX_OK_FOR_INDEX_P ( XEXP ( x , <NUM_LIT> ) , ( strict ) ) && GET_MODE_SIZE ( ( mode ) ) <= <NUM_LIT> ) || RTX_OK_FOR_OFFSET_P ( mode , XEXP ( x , <NUM_LIT> ) ) ) ) return true ; if ( ! flag_pic && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SYMBOL_REF ) && ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) && ( ! SYMBOL_REF_SMALL_P ( XEXP ( x , <NUM_LIT> ) ) ) ) return true ;"
GCC,arc,646,"Predict the next statement of this code snippet:
 <s> if ( INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != <NUM_LIT> ) return false ; break ; case <NUM_LIT> : if ( ! TARGET_LL64 ) return false ; case <NUM_LIT> : if ( INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != <NUM_LIT> ) return false ; default : return false ; } if ( RTX_OK_FOR_BASE_P ( XEXP ( op , <NUM_LIT> ) , ( strict ) ) ) return true ;"
GCC,arc,647,"Predict the next statement of this code snippet:
 <s> rtl_opt_pass * make_pass_arc_ifcvt ( gcc :: context * ctxt ) {"
GCC,arc,648,"Predict the next statement of this code snippet:
 <s> rtl_opt_pass * make_pass_arc_predicate_delay_insns ( gcc :: context * ctxt ) { return new pass_arc_predicate_delay_insns ( ctxt ) ;"
GCC,arc,649,"Predict the next statement of this code snippet:
 <s> gcc_assert ( MEM_P ( mem ) ) ; * offset = const0_rtx ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( ! arc_legitimate_address_p ( DImode , addr , reload_in_progress || reload_completed ) ) return false ; if ( REG_P ( addr ) ) {"
GCC,arc,650,"Predict the next statement of this code snippet:
 <s> if ( insn == <NUM_LIT> || ! NOTE_P ( insn ) ) break ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) return NULL ; }"
GCC,arc,651,"Predict the next statement of this code snippet:
 <s> insn = NEXT_INSN ( insn ) ; if ( insn == <NUM_LIT> || ! NOTE_P ( insn ) ) break ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) return NULL ; }"
GCC,arc,652,"Predict the next statement of this code snippet:
 <s> static bool operands_ok_ldd_std ( rtx rt , rtx rt2 , HOST_WIDE_INT offset ) { unsigned int t , t2 ; if ( ! reload_completed ) return true ; if ( ! ( SMALL_INT_RANGE ( offset , ( GET_MODE_SIZE ( DImode ) - <NUM_LIT> ) & ( ~ <NUM_LIT> ) , ( offset & ( GET_MODE_SIZE ( DImode ) - <NUM_LIT> ) & <NUM_LIT> ? <NUM_LIT> : - ( - GET_MODE_SIZE ( DImode ) | ( ~ <NUM_LIT> ) ) >> <NUM_LIT> ) ) ) ) return false ;"
GCC,arc,653,"Predict the next statement of this code snippet:
 <s> if ( ! ( SMALL_INT_RANGE ( offset , ( GET_MODE_SIZE ( DImode ) - <NUM_LIT> ) & ( ~ <NUM_LIT> ) , ( offset & ( GET_MODE_SIZE ( DImode ) - <NUM_LIT> ) & <NUM_LIT> ? <NUM_LIT> : - ( - GET_MODE_SIZE ( DImode ) | ( ~ <NUM_LIT> ) ) >> <NUM_LIT> ) ) ) ) return false ; t = REGNO ( rt ) ;"
GCC,arc,654,"Predict the next statement of this code snippet:
 <s> case LSHIFTRT : output_asm_insn ( <STR_LIT> , operands ) ; break ; default : break ; } } else if ( n == BITS_PER_WORD - <NUM_LIT> && dest_reg_operand ( operands [ <NUM_LIT> ] , SImode ) ) { switch ( code ) { case ASHIFT : output_asm_insn ( <STR_LIT> , operands ) ; break ; case ASHIFTRT : output_asm_insn ( <STR_LIT> <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> <STR_LIT> , operands ) ; break ; case LSHIFTRT : output_asm_insn ( <STR_LIT> <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> <STR_LIT> , operands ) ; break ; default : break ; } } else if ( n == BITS_PER_WORD - <NUM_LIT> && code == ASHIFT ) output_asm_insn ( <STR_LIT> , operands ) ; else { operands [ <NUM_LIT> ] = GEN_INT ( n ) ; output_asm_insn ( <STR_LIT> , operands ) ; shiftloop :"
GCC,arc,655,"Predict the next statement of this code snippet:
 <s> if ( ! insn ) return ; if ( arc_verify_short ( insn , cfun -> machine -> unalign , <NUM_LIT> ) ) {"
GCC,arc,656,"Predict the next statement of this code snippet:
 <s> static void output_short_suffix ( FILE * file ) { rtx_insn * insn = current_output_insn ; if ( ! insn ) return ; if ( arc_verify_short ( insn , cfun -> machine -> unalign , <NUM_LIT> ) ) {"
GCC,arc,657,"Predict the next statement of this code snippet:
 <s> add_reg_note ( prev0 , REG_SAVE_NOTE , GEN_INT ( <NUM_LIT> ) ) ; emit_insn_before ( gen_nopv ( ) , insn ) ; continue ; } offset = get_attr_length ( prev0 ) ; if ( get_attr_length ( prev0 ) == <NUM_LIT> && get_attr_iscompact ( prev0 ) != ISCOMPACT_TRUE ) { wantlong = true ; offset += <NUM_LIT> ; } rtx_insn * prev = prev_active_insn ( prev0 ) ; if ( prev ) offset += get_attr_length ( prev ) ; prev = prev_active_insn ( prev ) ; if ( prev ) offset += get_attr_length ( prev ) ; switch ( offset ) { case <NUM_LIT> :"
GCC,arc,658,"Predict the next statement of this code snippet:
 <s> static void parse_mrgf_banked_regs_option ( const char * arg ) { long int val ; char * end_ptr ; errno = <NUM_LIT> ; val = strtol ( arg , & end_ptr , <NUM_LIT> ) ; if ( errno != <NUM_LIT> || * arg == '\0' || * end_ptr != '\0' || ( val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> ) ) {"
GCC,arc,659,"Predict the next statement of this code snippet:
 <s> pass_arc_ifcvt ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_arc_ifcvt , ctxt ) {"
GCC,arc,660,"Predict the next statement of this code snippet:
 <s> pass_arc_ifcvt ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_arc_ifcvt , ctxt ) {"
GCC,arc,661,"Predict the next statement of this code snippet:
 <s> pass_arc_predicate_delay_insns ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_arc_predicate_delay_insns , ctxt ) {"
GCC,arc,662,"Predict the next statement of this code snippet:
 <s> pass_arc_predicate_delay_insns ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_arc_predicate_delay_insns , ctxt ) {"
GCC,arc,663,"Predict the next statement of this code snippet:
 <s> rtx stkslot = gen_rtx_MEM ( GET_MODE ( reg ) , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; rtx insn = emit_move_insn ( reg , stkslot ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ;"
GCC,arc,664,"Predict the next statement of this code snippet:
 <s> if ( MEM_P ( operands [ <NUM_LIT> ] ) ) tmp = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_UNSPEC_VOLATILE ( mode , gen_rtvec ( <NUM_LIT> , operands [ <NUM_LIT> ] ) , VUNSPEC_ARC_LDDI ) ) ) ; if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = tmp ; return false ; } return true ; } } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == SYMBOL_REF ) { enum tls_model model = SYMBOL_REF_TLS_MODEL ( operands [ <NUM_LIT> ] ) ; if ( MEM_P ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; else if ( model ) operands [ <NUM_LIT> ] = arc_legitimize_tls_address ( operands [ <NUM_LIT> ] , model ) ; } operands [ <NUM_LIT> ] = arc_legitimize_pic_address ( operands [ <NUM_LIT> ] ) ; if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx tmp0 = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx tmp1 = change_address ( operands [ <NUM_LIT> ] , mode , tmp0 ) ; MEM_COPY_ATTRIBUTES ( tmp1 , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = tmp1 ; } if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && ! arc_legitimate_constant_p ( mode , operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = force_reg ( mode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; else if ( MEM_P ( operands [ <NUM_LIT> ] ) && ( ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && ! satisfies_constraint_Cm3 ( operands [ <NUM_LIT> ] ) ) || MEM_P ( operands [ <NUM_LIT> ] ) ) ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ;"
GCC,arc,665,"Predict the next statement of this code snippet:
 <s> int val = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( val > <NUM_LIT> && val <= <NUM_LIT> && satisfies_constraint_Rcq ( operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ;"
GCC,arc,666,"Predict the next statement of this code snippet:
 <s> operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ;"
GCC,arc,667,"Predict the next statement of this code snippet:
 <s> if ( val >= - <NUM_LIT> && val <= <NUM_LIT> ) { operands [ <NUM_LIT> ] = gen_rtx_NEG ( SImode , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } else if ( val >= <NUM_LIT> && val < <NUM_LIT> ) { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_MINUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ;"
GCC,arc,668,"Predict the next statement of this code snippet:
 <s> for ( j = XVECLEN ( op , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return true ; }"
GCC,arc,669,"Predict the next statement of this code snippet:
 <s> } switch ( arc_selected_cpu -> arch_info -> arch_id ) { case BASE_ARCH_em : if ( arc_selected_cpu -> flags & FL_CD ) name = <STR_LIT> ; else name = <STR_LIT> ; if ( arc_selected_cpu -> flags & FL_FPUDA ) name = concat ( <STR_LIT> , name , NULL ) ; if ( arc_selected_cpu -> flags & FL_SPFP ) name = concat ( <STR_LIT> , name , NULL ) ; if ( arc_selected_cpu -> flags & FL_DPFP ) name = concat ( <STR_LIT> , name , NULL ) ; return concat ( <STR_LIT> , name , NULL ) ; case BASE_ARCH_hs : return <STR_LIT> ; case BASE_ARCH_700 : if ( arc_selected_cpu -> processor == PROCESSOR_nps400 ) return <STR_LIT> ; else return <STR_LIT> ; case BASE_ARCH_6xx : if ( arc_selected_cpu -> flags & FL_MUL64 ) return <STR_LIT> ; if ( arc_selected_cpu -> flags & FL_MUL32x16 ) return <STR_LIT> ;"
GCC,arc,670,"Predict the next statement of this code snippet:
 <s> func_ptr * p ; for ( p = __CTOR_END__ - <NUM_LIT> ; * p != ( func_ptr ) - <NUM_LIT> ; p -- ) ( * p ) ( ) ;"
GCC,arc,671,"Predict the next statement of this code snippet:
 <s> static void __do_global_ctors ( void ) { func_ptr * p ; for ( p = __CTOR_END__ - <NUM_LIT> ; * p != ( func_ptr ) - <NUM_LIT> ; p -- ) ( * p ) ( ) ;"
GCC,arc,672,"Predict the next statement of this code snippet:
 <s> for ( p = __DTOR_LIST__ + <NUM_LIT> ; * p ; p ++ ) ( * p ) ( ) ;"
GCC,arc,673,"Predict the next statement of this code snippet:
 <s> for ( p = __DTOR_LIST__ + <NUM_LIT> ; * p ; p ++ ) ( * p ) ( ) ;"
GCC,arc,674,"Predict the next statement of this code snippet:
 <s> static void __do_global_ctors ( ) { func_ptr * p ; for ( p = __CTOR_END__ - <NUM_LIT> ; * p != ( func_ptr ) - <NUM_LIT> ; p -- ) ( * p ) ( ) ;"
GCC,arc,675,"Predict the next statement of this code snippet:
 <s> func_ptr * p ;"
GCC,arc,676,"Predict the next statement of this code snippet:
 <s> func_ptr * p ;"
LLVM,ARC,0,"Predict the next statement of this code snippet:
 <s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;"
LLVM,ARC,1,"Predict the next statement of this code snippet:
 <s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;"
LLVM,ARC,2,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ;"
LLVM,ARC,3,"Predict the next statement of this code snippet:
 <s> return static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ;"
LLVM,ARC,4,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer & <ISA_LIT>AsmPrinter :: getTargetStreamer ( ) {"
LLVM,ARC,5,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MF . ensureAlignment ( Align ( <NUM_LIT> ) ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ;"
LLVM,ARC,6,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( & OutContext , * this ) {"
LLVM,ARC,7,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( & OutContext , * this ) {"
LLVM,ARC,8,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ;"
LLVM,ARC,9,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,ARC,10,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override {"
LLVM,ARC,11,"Predict the next statement of this code snippet:
 <s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;"
LLVM,ARC,12,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MF . ensureAlignment ( Align ( <NUM_LIT> ) ) ; AsmPrinter :: runOnMachineFunction ( MF ) ;"
LLVM,ARC,13,"Predict the next statement of this code snippet:
 <s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; unsigned CC = getCCForBRcc ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( CC != - <NUM_LIT> ) { BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( getBRccForPseudo ( MI ) ) ) . addMBB ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( getCCForBRcc ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ;"
LLVM,ARC,14,"Predict the next statement of this code snippet:
 <s> if ( CC != - <NUM_LIT> ) { BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( getBRccForPseudo ( MI ) ) ) . addMBB ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( getCCForBRcc ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; MI -> eraseFromParent ( ) ; } else {"
LLVM,ARC,15,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>BranchFinalize :: replaceWithCmpBcc ( MachineInstr * MI ) const { DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( getCmpForPseudo ( MI ) ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MI -> eraseFromParent ( ) ;"
LLVM,ARC,16,"Predict the next statement of this code snippet:
 <s> DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( getCmpForPseudo ( MI ) ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;"
LLVM,ARC,17,"Predict the next statement of this code snippet:
 <s> BlockToPCMap . insert ( std :: make_pair ( & MBB , PC ) ) ; for ( auto & MI : MBB ) { unsigned Size = TII -> getInstSizeInBytes ( MI ) ; if ( Size > <NUM_LIT> || Size == <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; } else { MaxSize += Size ; } if ( MI . isBranch ( ) ) {"
LLVM,ARC,18,"Predict the next statement of this code snippet:
 <s> unsigned MaxSize = <NUM_LIT> ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; std :: map < MachineBasicBlock * , unsigned > BlockToPCMap ; std :: vector < std :: pair < MachineInstr * , unsigned >> BranchToPCList ; unsigned PC = <NUM_LIT> ; for ( auto & MBB : MF ) { BlockToPCMap . insert ( std :: make_pair ( & MBB , PC ) ) ; for ( auto & MI : MBB ) { unsigned Size = TII -> getInstSizeInBytes ( MI ) ; if ( Size > <NUM_LIT> || Size == <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; } else { MaxSize += Size ; } if ( MI . isBranch ( ) ) { Branches . push_back ( & MI ) ;"
LLVM,ARC,19,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>BranchFinalize ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>BranchFinalizePass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,ARC,20,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>BranchFinalizePass ( ) { return new <ISA_LIT>BranchFinalize ( ) ;"
LLVM,ARC,21,"Predict the next statement of this code snippet:
 <s> static unsigned getBRccForPseudo ( MachineInstr * MI ) { assert ( isBRccPseudo ( MI ) && <STR_LIT> ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return <STR_LIT> ;"
LLVM,ARC,22,"Predict the next statement of this code snippet:
 <s> return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; default :"
LLVM,ARC,23,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,ARC,24,"Predict the next statement of this code snippet:
 <s> if ( CC != - <NUM_LIT> ) {"
LLVM,ARC,25,"Predict the next statement of this code snippet:
 <s> BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( getBRccForPseudo ( MI ) ) ) . addMBB ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( getCCForBRcc ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; MI -> eraseFromParent ( ) ; } else {"
LLVM,ARC,26,"Predict the next statement of this code snippet:
 <s> BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( getCmpForPseudo ( MI ) ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;"
LLVM,ARC,27,"Predict the next statement of this code snippet:
 <s> BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;"
LLVM,ARC,28,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; std :: vector < MachineInstr * > Branches ; bool Changed = false ; unsigned MaxSize = <NUM_LIT> ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; std :: map < MachineBasicBlock * , unsigned > BlockToPCMap ; std :: vector < std :: pair < MachineInstr * , unsigned >> BranchToPCList ; unsigned PC = <NUM_LIT> ; for ( auto & MBB : MF ) { BlockToPCMap . insert ( std :: make_pair ( & MBB , PC ) ) ; for ( auto & MI : MBB ) { unsigned Size = TII -> getInstSizeInBytes ( MI ) ; if ( Size > <NUM_LIT> || Size == <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; } else { MaxSize += Size ;"
LLVM,ARC,29,"Predict the next statement of this code snippet:
 <s> for ( auto & MI : MBB ) { unsigned Size = TII -> getInstSizeInBytes ( MI ) ; if ( Size > <NUM_LIT> || Size == <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; } else { MaxSize += Size ; } if ( MI . isBranch ( ) ) { Branches . push_back ( & MI ) ; BranchToPCList . emplace_back ( & MI , PC ) ; }"
LLVM,ARC,30,"Predict the next statement of this code snippet:
 <s> static_assert ( B > <NUM_LIT> , <STR_LIT> ) ; DecodeSymbolicOperandOff ( Inst , Address , SignExtend32 < B > ( InsnS ) , Decoder ) ; return MCDisassembler :: Success ;"
LLVM,ARC,31,"Predict the next statement of this code snippet:
 <s> const unsigned max = ( <NUM_LIT> << B ) - <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( InsnS < max ? static_cast < int > ( InsnS ) : - <NUM_LIT> ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,32,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( InsnS < max ? static_cast < int > ( InsnS ) : - <NUM_LIT> ) ) ;"
LLVM,ARC,33,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGBR32ShortRegister ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) RegNo += <NUM_LIT> ; return DecodeGPR32RegisterClass ( Inst , RegNo , Address , Decoder ) ;"
LLVM,ARC,34,"Predict the next statement of this code snippet:
 <s> } unsigned Reg = GPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,ARC,35,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MCDisassembler :: Fail ;"
LLVM,ARC,36,"Predict the next statement of this code snippet:
 <s> return MCDisassembler :: Fail ; } DstA = decodeAField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstA , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ;"
LLVM,ARC,37,"Predict the next statement of this code snippet:
 <s> unsigned DstA , SrcB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; DstA = decodeAField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstA , Address , Decoder ) ; SrcB = decodeBField ( Insn ) ;"
LLVM,ARC,38,"Predict the next statement of this code snippet:
 <s> unsigned S9 = Insn & <NUM_LIT> ; unsigned R = ( Insn & ( <NUM_LIT> & ~ <NUM_LIT> ) ) >> <NUM_LIT> ; DecodeGPR32RegisterClass ( Inst , R , Address , Dec ) ;"
LLVM,ARC,39,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeMEMrs9 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Dec ) { unsigned S9 = Insn & <NUM_LIT> ; unsigned R = ( Insn & ( <NUM_LIT> & ~ <NUM_LIT> ) ) >> <NUM_LIT> ; DecodeGPR32RegisterClass ( Inst , R , Address , Dec ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( S9 ) ) ) ;"
LLVM,ARC,40,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeMoveHRegInstruction ( MCInst & Inst , uint64_t Insn , uint64_t Address , const void * Decoder ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; using Field = decltype ( Insn ) ; Field h = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Field g = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; auto DecodeRegisterOrImm = [ & Inst , Address , Decoder ] ( Field RegNum , Field Value ) { if ( <NUM_LIT> == RegNum ) { Inst . addOperand ( MCOperand :: createImm ( Value ) ) ; return MCDisassembler :: Success ; }"
LLVM,ARC,41,"Predict the next statement of this code snippet:
 <s> Field h = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Field g = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; auto DecodeRegisterOrImm = [ & Inst , Address , Decoder ] ( Field RegNum , Field Value ) { if ( <NUM_LIT> == RegNum ) { Inst . addOperand ( MCOperand :: createImm ( Value ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,42,"Predict the next statement of this code snippet:
 <s> static_assert ( B > <NUM_LIT> , <STR_LIT> ) ;"
LLVM,ARC,43,"Predict the next statement of this code snippet:
 <s> SrcC = decodeCField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , SrcC , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ;"
LLVM,ARC,44,"Predict the next statement of this code snippet:
 <s> static bool DecodeSymbolicOperand ( MCInst & Inst , uint64_t Address , uint64_t Value , const void * Decoder ) { static const uint64_t atLeast = <NUM_LIT> ; auto Disassembler = static_cast < const MCDisassembler * > ( Decoder ) ; return ( nullptr != Disassembler && Disassembler -> tryAddingSymbolicOperand ( Inst , Value , Address , true , <NUM_LIT> , atLeast ) ) ;"
LLVM,ARC,45,"Predict the next statement of this code snippet:
 <s> return ( nullptr != Disassembler && Disassembler -> tryAddingSymbolicOperand ( Inst , Value , Address , true , <NUM_LIT> , atLeast ) ) ;"
LLVM,ARC,46,"Predict the next statement of this code snippet:
 <s> static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t Offset , const void * Decoder ) {"
LLVM,ARC,47,"Predict the next statement of this code snippet:
 <s> static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t Offset , const void * Decoder ) {"
LLVM,ARC,48,"Predict the next statement of this code snippet:
 <s> if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) { return Fail ; } return decodeInstruction ( DecoderTable32 , Instr , Insn32 , Address , this , STI ) ; } else { if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn48 ; if ( ! readInstruction48 ( Bytes , Address , Size , Insn48 ) ) return Fail ; Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ; if ( Success == Result ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Result ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } uint32_t Insn16 ; if ( ! readInstruction16 ( Bytes , Address , Size , Insn16 ) ) return Fail ;"
LLVM,ARC,49,"Predict the next statement of this code snippet:
 <s> Size = <NUM_LIT> ; return Fail ; } uint8_t DecodeByte = ( Bytes [ <NUM_LIT> ] & <NUM_LIT> ) >> <NUM_LIT> ; if ( DecodeByte < <NUM_LIT> ) { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return Fail ; } if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn64 ; if ( ! readInstruction64 ( Bytes , Address , Size , Insn64 ) ) return Fail ; Result = decodeInstruction ( DecoderTable64 , Instr , Insn64 , Address , this , STI ) ; if ( Success == Result ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Result ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } uint32_t Insn32 ; if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) { return Fail ; } return decodeInstruction ( DecoderTable32 , Instr , Insn32 , Address , this , STI ) ; } else { if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn48 ; if ( ! readInstruction48 ( Bytes , Address , Size , Insn48 ) ) return Fail ; Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ; if ( Success == Result ) {"
LLVM,ARC,50,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Disassembler ( ) {"
LLVM,ARC,51,"Predict the next statement of this code snippet:
 <s> unsigned DstB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; DstB = decodeBField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstB , Address , Decoder ) ; using Field = decltype ( Insn ) ; Field U6Field = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( U6Field ) ) ; Field CCField = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( CCField ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,52,"Predict the next statement of this code snippet:
 <s> Field U6Field = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( U6Field ) ) ;"
LLVM,ARC,53,"Predict the next statement of this code snippet:
 <s> Field H = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Field G = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; auto DecodeRegisterOrImm = [ & Inst , Address , Decoder ] ( Field RegNum , Field Value ) { if ( <NUM_LIT> == RegNum ) {"
LLVM,ARC,54,"Predict the next statement of this code snippet:
 <s> unsigned DstB = decodeBField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstB , Address , Decoder ) ; using Field = decltype ( Insn ) ; Field Lower = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Field Upper = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Field Sign = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ? - <NUM_LIT> : <NUM_LIT> ; Field Result = Sign * ( ( Upper << <NUM_LIT> ) + Lower ) ; Inst . addOperand ( MCOperand :: createImm ( Result ) ) ;"
LLVM,ARC,55,"Predict the next statement of this code snippet:
 <s> Field U6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,ARC,56,"Predict the next statement of this code snippet:
 <s> Field U6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( U6 ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,57,"Predict the next statement of this code snippet:
 <s> return ( nullptr != Disassembler && Disassembler -> tryAddingSymbolicOperand ( Inst , Value , Address , true , <NUM_LIT> , AtLeast ) ) ;"
LLVM,ARC,58,"Predict the next statement of this code snippet:
 <s> static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t Offset , const void * Decoder ) {"
LLVM,ARC,59,"Predict the next statement of this code snippet:
 <s> static const uint64_t AtLeast = <NUM_LIT> ;"
LLVM,ARC,60,"Predict the next statement of this code snippet:
 <s> unsigned DstB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; DstB = decodeBField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstB , Address , Decoder ) ; using Field = decltype ( Insn ) ;"
LLVM,ARC,61,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( S ) ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,62,"Predict the next statement of this code snippet:
 <s> static MCDisassembler :: DecodeStatus DecodeBranchTargetS21 ( MCInst & Inst , unsigned S , uint64_t Address , const void * Decoder ) {"
LLVM,ARC,63,"Predict the next statement of this code snippet:
 <s> static MCDisassembler :: DecodeStatus DecodeBranchTargetS25 ( MCInst & Inst , unsigned S , uint64_t Address , const void * Decoder ) {"
LLVM,ARC,64,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( S ) ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,65,"Predict the next statement of this code snippet:
 <s> return MCDisassembler :: Fail ; } unsigned Reg = GPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,ARC,66,"Predict the next statement of this code snippet:
 <s> static MCDisassembler :: DecodeStatus DecodeLdLImmInstruction ( MCInst & Inst , uint64_t Insn , uint64_t Address , const void * Decoder ) { unsigned DstA , SrcB , LImm ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SrcB = decodeBField ( Insn ) ; if ( SrcB != <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MCDisassembler :: Fail ; } DstA = decodeAField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstA , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;"
LLVM,ARC,67,"Predict the next statement of this code snippet:
 <s> unsigned R = ( Insn & ( <NUM_LIT> & ~ <NUM_LIT> ) ) >> <NUM_LIT> ; DecodeGPR32RegisterClass ( Inst , R , Address , Dec ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( S9 ) ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,68,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( <NUM_LIT> & InsnS12 ) ) ) ;"
LLVM,ARC,69,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( <NUM_LIT> & InsnS12 ) ) ) ;"
LLVM,ARC,70,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( <NUM_LIT> & InsnS9 ) ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,71,"Predict the next statement of this code snippet:
 <s> static MCDisassembler :: DecodeStatus DecodeS9Operand ( MCInst & Inst , unsigned InsnS9 , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( <NUM_LIT> & InsnS9 ) ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,72,"Predict the next statement of this code snippet:
 <s> if ( DstB != <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MCDisassembler :: Fail ; } SrcC = decodeCField ( Insn ) ;"
LLVM,ARC,73,"Predict the next statement of this code snippet:
 <s> LImm = ( Insn >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,74,"Predict the next statement of this code snippet:
 <s> MCDisassembler :: DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { MCDisassembler :: DecodeStatus Result ; if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return Fail ; } uint8_t DecodeByte = ( Bytes [ <NUM_LIT> ] & <NUM_LIT> ) >> <NUM_LIT> ; if ( DecodeByte < <NUM_LIT> ) { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return Fail ; } if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn64 ;"
LLVM,ARC,75,"Predict the next statement of this code snippet:
 <s> if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return Fail ; } if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn64 ; if ( ! readInstruction64 ( Bytes , Address , Size , Insn64 ) ) return Fail ; Result = decodeInstruction ( DecoderTable64 , Instr , Insn64 , Address , this , STI ) ; if ( Result == MCDisassembler :: Success ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MCDisassembler :: Success ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; } uint32_t Insn32 ; if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) {"
LLVM,ARC,76,"Predict the next statement of this code snippet:
 <s> DstA = decodeAField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstA , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ;"
LLVM,ARC,77,"Predict the next statement of this code snippet:
 <s> SrcB = decodeBField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , SrcB , Address , Decoder ) ; if ( decodeCField ( Insn ) != <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MCDisassembler :: Fail ;"
LLVM,ARC,78,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeMoveHRegInstruction ( MCInst & Inst , uint64_t Insn , uint64_t Address , const void * Decoder ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; using Field = decltype ( Insn ) ;"
LLVM,ARC,79,"Predict the next statement of this code snippet:
 <s> return MCDisassembler :: Fail ; } SrcC = decodeCField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , SrcC , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ;"
LLVM,ARC,80,"Predict the next statement of this code snippet:
 <s> if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return Fail ; } uint8_t DecodeByte = ( Bytes [ <NUM_LIT> ] & <NUM_LIT> ) >> <NUM_LIT> ; if ( DecodeByte < <NUM_LIT> ) { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return Fail ; } if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn64 ; if ( ! readInstruction64 ( Bytes , Address , Size , Insn64 ) ) return Fail ; Result = decodeInstruction ( DecoderTable64 , Instr , Insn64 , Address , this , STI ) ; if ( Success == Result ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Result ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; } uint32_t Insn32 ; if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) { return Fail ; } return decodeInstruction ( DecoderTable32 , Instr , Insn32 , Address , this , STI ) ; } else { if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn48 ; if ( ! readInstruction48 ( Bytes , Address , Size , Insn48 ) ) return Fail ; Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ; if ( Success == Result ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Result ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ;"
LLVM,ARC,81,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) {"
LLVM,ARC,82,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) {"
LLVM,ARC,83,"Predict the next statement of this code snippet:
 <s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCInstrInfo ( ) ) ;"
LLVM,ARC,84,"Predict the next statement of this code snippet:
 <s> static unsigned decodeAField ( unsigned Insn ) { return fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,ARC,85,"Predict the next statement of this code snippet:
 <s> static unsigned decodeAField ( unsigned Insn ) {"
LLVM,ARC,86,"Predict the next statement of this code snippet:
 <s> static unsigned decodeBField ( unsigned Insn ) {"
LLVM,ARC,87,"Predict the next statement of this code snippet:
 <s> DecodeSymbolicOperandOff ( Inst , Address , SignExtend32 < B > ( InsnS ) , Decoder ) ;"
LLVM,ARC,88,"Predict the next statement of this code snippet:
 <s> DstB = decodeBField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstB , Address , Decoder ) ; using Field = decltype ( Insn ) ; Field U6Field = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( U6Field ) ) ; Field CCField = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( CCField ) ) ; return MCDisassembler :: Success ;"
LLVM,ARC,89,"Predict the next statement of this code snippet:
 <s> static_assert ( B > <NUM_LIT> , <STR_LIT> ) ; const unsigned max = ( <NUM_LIT> << B ) - <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( InsnS < max ? static_cast < int > ( InsnS ) : - <NUM_LIT> ) ) ;"
LLVM,ARC,90,"Predict the next statement of this code snippet:
 <s> const unsigned max = ( <NUM_LIT> << B ) - <NUM_LIT> ;"
LLVM,ARC,91,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGBR32ShortRegister ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) RegNo += <NUM_LIT> ;"
LLVM,ARC,92,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGBR32ShortRegister ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) {"
LLVM,ARC,93,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MCDisassembler :: Fail ;"
LLVM,ARC,94,"Predict the next statement of this code snippet:
 <s> return MCDisassembler :: Fail ; } unsigned Reg = GPR32DecoderTable [ RegNo ] ;"
LLVM,ARC,95,"Predict the next statement of this code snippet:
 <s> if ( decodeCField ( Insn ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( ( uint32_t ) ( Insn >> <NUM_LIT> ) ) ) ;"
LLVM,ARC,96,"Predict the next statement of this code snippet:
 <s> unsigned R = ( Insn & ( <NUM_LIT> & ~ <NUM_LIT> ) ) >> <NUM_LIT> ; DecodeGPR32RegisterClass ( Inst , R , Address , Dec ) ;"
LLVM,ARC,97,"Predict the next statement of this code snippet:
 <s> Field G = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; auto DecodeRegisterOrImm = [ & Inst , Address , Decoder ] ( Field RegNum , Field Value ) { if ( <NUM_LIT> == RegNum ) { Inst . addOperand ( MCOperand :: createImm ( Value ) ) ; return MCDisassembler :: Success ; } return DecodeGPR32RegisterClass ( Inst , RegNum , Address , Decoder ) ;"
LLVM,ARC,98,"Predict the next statement of this code snippet:
 <s> static_assert ( B > <NUM_LIT> , <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < B > ( maskTrailingOnes < decltype ( InsnS ) > ( B ) & InsnS ) ) ) ;"
LLVM,ARC,99,"Predict the next statement of this code snippet:
 <s> unsigned DstB = decodeBField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstB , Address , Decoder ) ; using Field = decltype ( Insn ) ; Field Lower = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Field Upper = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,ARC,100,"Predict the next statement of this code snippet:
 <s> using Field = decltype ( Insn ) ; Field U6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( U6 ) ) ;"
LLVM,ARC,101,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeSOPwithRU6 ( MCInst & Inst , uint64_t Insn , uint64_t Address , const MCDisassembler * Decoder ) {"
LLVM,ARC,102,"Predict the next statement of this code snippet:
 <s> } SrcC = decodeCField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , SrcC , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;"
LLVM,ARC,103,"Predict the next statement of this code snippet:
 <s> static bool DecodeSymbolicOperand ( MCInst & Inst , uint64_t Address , uint64_t Value , const MCDisassembler * Decoder ) { static const uint64_t AtLeast = <NUM_LIT> ; return ( nullptr != Decoder && Decoder -> tryAddingSymbolicOperand ( Inst , Value , Address , true , <NUM_LIT> , AtLeast ) ) ;"
LLVM,ARC,104,"Predict the next statement of this code snippet:
 <s> uint64_t NextAddress = Address + Offset ;"
LLVM,ARC,105,"Predict the next statement of this code snippet:
 <s> uint64_t NextAddress = Address + Offset ; if ( ! DecodeSymbolicOperand ( Inst , Address , NextAddress , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ;"
LLVM,ARC,106,"Predict the next statement of this code snippet:
 <s> if ( Success == Result ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Result ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } uint32_t Insn32 ; if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) { return Fail ; } return decodeInstruction ( DecoderTable32 , Instr , Insn32 , Address , this , STI ) ; } else { if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn48 ;"
LLVM,ARC,107,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ;"
LLVM,ARC,108,"Predict the next statement of this code snippet:
 <s> static bool readInstruction32 ( ArrayRef < uint8_t > Bytes , uint64_t Address , uint64_t & Size , uint32_t & Insn ) { Size = <NUM_LIT> ;"
LLVM,ARC,109,"Predict the next statement of this code snippet:
 <s> Size = <NUM_LIT> ;"
LLVM,ARC,110,"Predict the next statement of this code snippet:
 <s> static bool readInstruction48 ( ArrayRef < uint8_t > Bytes , uint64_t Address , uint64_t & Size , uint64_t & Insn ) { Size = <NUM_LIT> ; Insn = ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return true ;"
LLVM,ARC,111,"Predict the next statement of this code snippet:
 <s> Register Rb = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Ra ) . add ( Src ) ;"
LLVM,ARC,112,"Predict the next statement of this code snippet:
 <s> BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addReg ( R ) ;"
LLVM,ARC,113,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>ExpandPseudos :: expandCTTZ ( MachineFunction & MF , MachineBasicBlock :: iterator MII ) { MachineInstr & MI = * MII ; const MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ;"
LLVM,ARC,114,"Predict the next statement of this code snippet:
 <s> Register AddOpc = isUInt < <NUM_LIT> > ( SI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( AddOpc ) , AddrReg ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( SI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( getMappedOp ( SI . getOpcode ( ) ) ) ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( AddrReg ) . addImm ( <NUM_LIT> ) ; SI . eraseFromParent ( ) ;"
LLVM,ARC,115,"Predict the next statement of this code snippet:
 <s> Register AddrReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; Register AddOpc = isUInt < <NUM_LIT> > ( SI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( AddOpc ) , AddrReg ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( SI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( getMappedOp ( SI . getOpcode ( ) ) ) ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( AddrReg ) . addImm ( <NUM_LIT> ) ;"
LLVM,ARC,116,"Predict the next statement of this code snippet:
 <s> while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expandStore ( MF , MBBI ) ; Expanded = true ; break ; case <STR_LIT> : expandCTLZ ( MF , MBBI ) ;"
LLVM,ARC,117,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ExpandPseudos ( ) : MachineFunctionPass ( ID ) {"
LLVM,ARC,118,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ExpandPseudos ( ) : MachineFunctionPass ( ID ) {"
LLVM,ARC,119,"Predict the next statement of this code snippet:
 <s> unsigned AddrReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned AddOpc = isUInt < <NUM_LIT> > ( SI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( AddOpc ) , AddrReg ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( SI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( getMappedOp ( SI . getOpcode ( ) ) ) ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( AddrReg ) . addImm ( <NUM_LIT> ) ; SI . eraseFromParent ( ) ;"
LLVM,ARC,120,"Predict the next statement of this code snippet:
 <s> BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( getMappedOp ( SI . getOpcode ( ) ) ) ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( AddrReg ) . addImm ( <NUM_LIT> ) ; SI . eraseFromParent ( ) ;"
LLVM,ARC,121,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,ARC,122,"Predict the next statement of this code snippet:
 <s> switch ( PseudoOp ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,ARC,123,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,ARC,124,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <STR_LIT> ;"
LLVM,ARC,125,"Predict the next statement of this code snippet:
 <s> while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,ARC,126,"Predict the next statement of this code snippet:
 <s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . set ( <STR_LIT> ) ;"
LLVM,ARC,127,"Predict the next statement of this code snippet:
 <s> if ( Amt > AFI -> MaxCallStackReq && Old . getOpcode ( ) == <STR_LIT> ) AFI -> MaxCallStackReq = Amt ; } else { if ( Amt != <NUM_LIT> ) { assert ( ( Old . getOpcode ( ) == <STR_LIT> || Old . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool IsAdd = ( Old . getOpcode ( ) == <STR_LIT> ) ; emitRegUpdate ( MBB , I , dl , <STR_LIT> , Amt , IsAdd , TII ) ; }"
LLVM,ARC,128,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( load_funclet_name [ Last - <STR_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * ( StackSlotsUsedByFunclet ) ) ; } if ( SavedBlink ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } if ( MF . getFunction ( ) . isVarArg ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ;"
LLVM,ARC,129,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint64_t StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; bool SavedBlink = false ; unsigned AmountAboveFunclet = <NUM_LIT> ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize ) ; AmountAboveFunclet += <NUM_LIT> ; } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; unsigned StackSlotsUsedByFunclet = <NUM_LIT> ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { StackSlotsUsedByFunclet = Last - <STR_LIT> ; AmountAboveFunclet += <NUM_LIT> * ( StackSlotsUsedByFunclet + <NUM_LIT> ) ; SavedBlink = true ; } if ( MFI . hasCalls ( ) && ! SavedBlink ) { AmountAboveFunclet += <NUM_LIT> ; SavedBlink = true ; } if ( StackSize - AmountAboveFunclet ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize - AmountAboveFunclet ) ; } if ( StackSlotsUsedByFunclet ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( load_funclet_name [ Last - <STR_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * ( StackSlotsUsedByFunclet ) ) ; } if ( SavedBlink ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) ;"
LLVM,ARC,130,"Predict the next statement of this code snippet:
 <s> unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int CurOffset = - <NUM_LIT> ; if ( hasFP ( MF ) ) { CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( <STR_LIT> , true ) , CurOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; CurOffset -= <NUM_LIT> ; } if ( MFI . hasCalls ( ) ) { CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( <STR_LIT> , true ) , CurOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } for ( const auto & Entry : CSI ) { unsigned Reg = Entry . getReg ( ) ; int FI = Entry . getFrameIdx ( ) ; if ( ( hasFP ( MF ) && Reg == <STR_LIT> ) || ( MFI . hasCalls ( ) && Reg == <STR_LIT> ) ) continue ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , MFI . getObjectOffset ( FI ) ) ) ;"
LLVM,ARC,131,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ;"
LLVM,ARC,132,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getParent ( ) -> getName ( ) << <STR_LIT> ) ;"
LLVM,ARC,133,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getParent ( ) -> getName ( ) << <STR_LIT> ) ; unsigned Last = determineLastCalleeSave ( CSI ) ;"
LLVM,ARC,134,"Predict the next statement of this code snippet:
 <s> unsigned Last = <NUM_LIT> ; for ( auto Reg : CSI ) { assert ( Reg . getReg ( ) >= <STR_LIT> && Reg . getReg ( ) <= <STR_LIT> && <STR_LIT> ) ; if ( Reg . getReg ( ) > Last ) Last = Reg . getReg ( ) ; } return Last ;"
LLVM,ARC,135,"Predict the next statement of this code snippet:
 <s> assert ( Reg . getReg ( ) >= <STR_LIT> && Reg . getReg ( ) <= <STR_LIT> && <STR_LIT> ) ; if ( Reg . getReg ( ) > Last ) Last = Reg . getReg ( ) ; }"
LLVM,ARC,136,"Predict the next statement of this code snippet:
 <s> AmountAboveFunclet += <NUM_LIT> ; } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; unsigned StackSlotsUsedByFunclet = <NUM_LIT> ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { StackSlotsUsedByFunclet = Last - <STR_LIT> ; AmountAboveFunclet += <NUM_LIT> * ( StackSlotsUsedByFunclet + <NUM_LIT> ) ; SavedBlink = true ; } if ( MFI . hasCalls ( ) && ! SavedBlink ) { AmountAboveFunclet += <NUM_LIT> ; SavedBlink = true ; } if ( unsigned MoveAmount = StackSize - AmountAboveFunclet ) { unsigned Opc = <STR_LIT> ; if ( isUInt < <NUM_LIT> > ( MoveAmount ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( MoveAmount ) ) Opc = <STR_LIT> ; BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize - AmountAboveFunclet ) ; } if ( StackSlotsUsedByFunclet ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( load_funclet_name [ Last - <STR_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; unsigned Opc = <STR_LIT> ;"
LLVM,ARC,137,"Predict the next statement of this code snippet:
 <s> unsigned VarArgsBytes = MFI . getObjectSize ( AFI -> getVarArgsFrameIndex ( ) ) ; unsigned Opc = <STR_LIT> ; if ( isUInt < <NUM_LIT> > ( VarArgsBytes ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( VarArgsBytes ) ) Opc = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII -> get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( VarArgsBytes ) ; } if ( hasFP ( MF ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; AlreadyAdjusted += <NUM_LIT> ; } if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; StackSlotsUsedByFunclet = Last - <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * StackSlotsUsedByFunclet ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( store_funclet_name [ Last - <STR_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; AlreadyAdjusted += <NUM_LIT> * ( StackSlotsUsedByFunclet + <NUM_LIT> ) ; SavedBlink = true ; } if ( MFI . hasCalls ( ) && ! SavedBlink ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) ; AlreadyAdjusted += <NUM_LIT> ; } if ( AFI -> MaxCallStackReq > <NUM_LIT> ) MFI . setStackSize ( MFI . getStackSize ( ) + AFI -> MaxCallStackReq ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( MFI . getStackSize ( ) - AlreadyAdjusted ) << <STR_LIT> ) ; generateStackAdjustment ( MBB , MBBI , * ST . getInstrInfo ( ) , dl , - ( MFI . getStackSize ( ) - AlreadyAdjusted ) , <STR_LIT> ) ; if ( hasFP ( MF ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;"
LLVM,ARC,138,"Predict the next statement of this code snippet:
 <s> else Opc = IsAdd ? <STR_LIT> : <STR_LIT> ;"
LLVM,ARC,139,"Predict the next statement of this code snippet:
 <s> unsigned AdjOp ; if ( ! Amount ) return ; bool Positive ; unsigned AbsAmount ; if ( Amount < <NUM_LIT> ) { AbsAmount = - Amount ; Positive = false ; } else { AbsAmount = Amount ; Positive = true ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Amount << <STR_LIT> << AbsAmount << <STR_LIT> ) ; assert ( ( AbsAmount % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; if ( isUInt < <NUM_LIT> > ( AbsAmount ) ) AdjOp = Positive ? <STR_LIT> : <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( AbsAmount ) ) AdjOp = Positive ? <STR_LIT> : <STR_LIT> ; else AdjOp = Positive ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( AdjOp ) , StackPtr ) . addReg ( StackPtr ) . addImm ( AbsAmount ) ;"
LLVM,ARC,140,"Predict the next statement of this code snippet:
 <s> static void generateStackAdjustment ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const <ISA_LIT>InstrInfo & TII , DebugLoc dl , int Amount , int StackPtr ) { unsigned AdjOp ; if ( ! Amount ) return ; bool Positive ; unsigned AbsAmount ; if ( Amount < <NUM_LIT> ) { AbsAmount = - Amount ; Positive = false ; } else { AbsAmount = Amount ; Positive = true ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Amount << <STR_LIT> << AbsAmount << <STR_LIT> ) ;"
LLVM,ARC,141,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getParent ( ) -> getName ( ) << <STR_LIT> ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { return true ; }"
LLVM,ARC,142,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * StackSlotsUsedByFunclet ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( store_funclet_name [ Last - <STR_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; AlreadyAdjusted += <NUM_LIT> * ( StackSlotsUsedByFunclet + <NUM_LIT> ) ; SavedBlink = true ; } if ( MFI . hasCalls ( ) && ! SavedBlink ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) ; AlreadyAdjusted += <NUM_LIT> ; } if ( AFI -> MaxCallStackReq > <NUM_LIT> ) MFI . setStackSize ( MFI . getStackSize ( ) + AFI -> MaxCallStackReq ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( MFI . getStackSize ( ) - AlreadyAdjusted ) << <STR_LIT> ) ; generateStackAdjustment ( MBB , MBBI , * ST . getInstrInfo ( ) , dl , - ( MFI . getStackSize ( ) - AlreadyAdjusted ) , <STR_LIT> ) ; if ( hasFP ( MF ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( isUInt < <NUM_LIT> > ( MFI . getStackSize ( ) ) ? <STR_LIT> : <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( MFI . getStackSize ( ) ) ; } unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int CurOffset = - <NUM_LIT> ; if ( hasFP ( MF ) ) { CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( <STR_LIT> , true ) , CurOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; CurOffset -= <NUM_LIT> ; } if ( MFI . hasCalls ( ) ) { CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( <STR_LIT> , true ) , CurOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } for ( const auto & Entry : CSI ) { unsigned Reg = Entry . getReg ( ) ;"
LLVM,ARC,143,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * RC = & <STR_LIT> ; if ( MFI . hasStackObjects ( ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegScavFI << <STR_LIT> ) ; }"
LLVM,ARC,144,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MFI . getStackSize ( ) << <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( MFI . hasStackObjects ( ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegScavFI << <STR_LIT> ) ; }"
LLVM,ARC,145,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getParent ( ) -> getName ( ) << <STR_LIT> ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) {"
LLVM,ARC,146,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & st ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) , ST ( st ) {"
LLVM,ARC,147,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & st ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) , ST ( st ) {"
LLVM,ARC,148,"Predict the next statement of this code snippet:
 <s> } if ( MFI . hasCalls ( ) || ( UseSaveRestoreFunclet && Last > <STR_LIT> ) ) { int StackObj = MFI . CreateFixedSpillStackObject ( <NUM_LIT> , CurOffset , true ) ; DEBUG ( dbgs ( ) << <STR_LIT> << StackObj << <STR_LIT> << CurOffset << <STR_LIT> ) ; ( void ) StackObj ; CurOffset -= <NUM_LIT> ; } for ( unsigned Which = Last ; Which > <STR_LIT> ; Which -- ) { auto RegI = getSavedReg ( CSI , Which ) ; if ( RegI == CSI . end ( ) || RegI -> getFrameIdx ( ) == <NUM_LIT> ) { int FI = MFI . CreateFixedSpillStackObject ( <NUM_LIT> , CurOffset , true ) ; if ( RegI != CSI . end ( ) ) RegI -> setFrameIdx ( FI ) ; } else MFI . setObjectOffset ( RegI -> getFrameIdx ( ) , CurOffset ) ; CurOffset -= <NUM_LIT> ; } for ( auto & I : CSI ) { if ( I . getReg ( ) > <STR_LIT> ) continue ; if ( I . getFrameIdx ( ) == <NUM_LIT> ) { I . setFrameIdx ( MFI . CreateFixedSpillStackObject ( <NUM_LIT> , CurOffset , true ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << I . getFrameIdx ( ) << <STR_LIT> << CurOffset << <STR_LIT> ) ; } else { MFI . setObjectOffset ( I . getFrameIdx ( ) , CurOffset ) ; DEBUG ( dbgs ( ) << <STR_LIT> << I . getFrameIdx ( ) << <STR_LIT> << CurOffset << <STR_LIT> ) ; } CurOffset -= <NUM_LIT> ; }"
LLVM,ARC,149,"Predict the next statement of this code snippet:
 <s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . set ( <STR_LIT> ) ;"
LLVM,ARC,150,"Predict the next statement of this code snippet:
 <s> } else { if ( Amt != <NUM_LIT> ) { assert ( ( Old . getOpcode ( ) == <STR_LIT> || Old . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool IsAdd = ( Old . getOpcode ( ) == <STR_LIT> ) ; emitRegUpdate ( MBB , I , dl , <STR_LIT> , Amt , IsAdd , TII ) ; } } return MBB . erase ( I ) ;"
LLVM,ARC,151,"Predict the next statement of this code snippet:
 <s> if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize ) ; AmountAboveFunclet += <NUM_LIT> ; } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; unsigned StackSlotsUsedByFunclet = <NUM_LIT> ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { StackSlotsUsedByFunclet = Last - <STR_LIT> ; AmountAboveFunclet += <NUM_LIT> * ( StackSlotsUsedByFunclet + <NUM_LIT> ) ; SavedBlink = true ; } if ( MFI . hasCalls ( ) && ! SavedBlink ) { AmountAboveFunclet += <NUM_LIT> ; SavedBlink = true ; } if ( StackSize - AmountAboveFunclet ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize - AmountAboveFunclet ) ; } if ( StackSlotsUsedByFunclet ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( load_funclet_name [ Last - <STR_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * ( StackSlotsUsedByFunclet ) ) ; } if ( SavedBlink ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) ; } if ( hasFP ( MF ) ) {"
LLVM,ARC,152,"Predict the next statement of this code snippet:
 <s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; unsigned StackSlotsUsedByFunclet = <NUM_LIT> ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { StackSlotsUsedByFunclet = Last - <STR_LIT> ; AmountAboveFunclet += <NUM_LIT> * ( StackSlotsUsedByFunclet + <NUM_LIT> ) ; SavedBlink = true ; } if ( MFI . hasCalls ( ) && ! SavedBlink ) { AmountAboveFunclet += <NUM_LIT> ; SavedBlink = true ; } if ( StackSize - AmountAboveFunclet ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize - AmountAboveFunclet ) ; } if ( StackSlotsUsedByFunclet ) {"
LLVM,ARC,153,"Predict the next statement of this code snippet:
 <s> DEBUG ( dbgs ( ) << <STR_LIT> << Amount << <STR_LIT> << AbsAmount << <STR_LIT> ) ; assert ( ( AbsAmount % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; if ( isUInt < <NUM_LIT> > ( AbsAmount ) ) AdjOp = Positive ? <STR_LIT> : <STR_LIT> ;"
LLVM,ARC,154,"Predict the next statement of this code snippet:
 <s> static void generateStackAdjustment ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const <ISA_LIT>InstrInfo & TII , DebugLoc dl , int Amount , int StackPtr ) { unsigned AdjOp ; if ( ! Amount ) return ; bool Positive ; unsigned AbsAmount ; if ( Amount < <NUM_LIT> ) { AbsAmount = - Amount ; Positive = false ; } else {"
LLVM,ARC,155,"Predict the next statement of this code snippet:
 <s> DEBUG ( dbgs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MFI . getStackSize ( ) << <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( MFI . hasStackObjects ( ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlignment ( * RC ) , false ) ;"
LLVM,ARC,156,"Predict the next statement of this code snippet:
 <s> DEBUG ( dbgs ( ) << <STR_LIT> << MFI . getStackSize ( ) << <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( MFI . hasStackObjects ( ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlignment ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << RegScavFI << <STR_LIT> ) ;"
LLVM,ARC,157,"Predict the next statement of this code snippet:
 <s> DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getParent ( ) -> getFunction ( ) -> getName ( ) << <STR_LIT> ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { return true ; }"
LLVM,ARC,158,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getParent ( ) -> getFunction ( ) -> getName ( ) << <STR_LIT> ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { return true ; }"
LLVM,ARC,159,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MF . getFrameInfo ( ) . isFrameAddressTaken ( ) || RegInfo -> hasStackRealignment ( MF ) ;"
LLVM,ARC,160,"Predict the next statement of this code snippet:
 <s> bool HasFP = MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MF . getFrameInfo ( ) . isFrameAddressTaken ( ) || RegInfo -> hasStackRealignment ( MF ) ; return HasFP ;"
LLVM,ARC,161,"Predict the next statement of this code snippet:
 <s> ScalarAlloc = - ScalarAlloc ; } generateStackAdjustment ( MBB , MBBI , * ST . getInstrInfo ( ) , DebugLoc ( ) , ScalarAlloc , <STR_LIT> ) ;"
LLVM,ARC,162,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: adjustStackToMatchRecords ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , bool Allocate ) const { MachineFunction & MF = * MBB . getParent ( ) ; int ScalarAlloc = MF . getFrameInfo ( ) . getStackSize ( ) ;"
LLVM,ARC,163,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & st ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , ST ( st ) {"
LLVM,ARC,164,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & st ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , ST ( st ) {"
LLVM,ARC,165,"Predict the next statement of this code snippet:
 <s> auto RegI = getSavedReg ( CSI , Which ) ; if ( RegI == CSI . end ( ) || RegI -> getFrameIdx ( ) == <NUM_LIT> ) { int FI = MFI . CreateFixedSpillStackObject ( <NUM_LIT> , CurOffset , true ) ; if ( RegI != CSI . end ( ) ) RegI -> setFrameIdx ( FI ) ; } else MFI . setObjectOffset ( RegI -> getFrameIdx ( ) , CurOffset ) ; CurOffset -= <NUM_LIT> ; } for ( auto & I : CSI ) { if ( I . getReg ( ) > <STR_LIT> ) continue ; if ( I . getFrameIdx ( ) == <NUM_LIT> ) {"
LLVM,ARC,166,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;"
LLVM,ARC,167,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . set ( <STR_LIT> ) ;"
LLVM,ARC,168,"Predict the next statement of this code snippet:
 <s> assert ( Reg . getReg ( ) >= <STR_LIT> && Reg . getReg ( ) <= <STR_LIT> && <STR_LIT> ) ; if ( Reg . getReg ( ) > Last ) Last = Reg . getReg ( ) ;"
LLVM,ARC,169,"Predict the next statement of this code snippet:
 <s> if ( Reg . getReg ( ) > Last ) Last = Reg . getReg ( ) ; } return Last ;"
LLVM,ARC,170,"Predict the next statement of this code snippet:
 <s> auto * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! hasFP ( MF ) ) { if ( Amt > AFI -> MaxCallStackReq && Old . getOpcode ( ) == <STR_LIT> ) AFI -> MaxCallStackReq = Amt ; } else { if ( Amt != <NUM_LIT> ) { assert ( ( Old . getOpcode ( ) == <STR_LIT> || Old . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool IsAdd = ( Old . getOpcode ( ) == <STR_LIT> ) ; emitRegUpdate ( MBB , I , dl , <STR_LIT> , Amt , IsAdd , TII ) ; }"
LLVM,ARC,171,"Predict the next statement of this code snippet:
 <s> static void emitRegUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned Reg , int NumBytes , bool IsAdd , const <ISA_LIT>InstrInfo * TII ) { unsigned Opc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII -> get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( NumBytes ) ;"
LLVM,ARC,172,"Predict the next statement of this code snippet:
 <s> AbsAmount = Amount ; Positive = true ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Amount << <STR_LIT> << AbsAmount << <STR_LIT> ) ; assert ( ( AbsAmount % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ;"
LLVM,ARC,173,"Predict the next statement of this code snippet:
 <s> static std :: vector < CalleeSavedInfo > :: iterator getSavedReg ( std :: vector < CalleeSavedInfo > & V , unsigned reg ) {"
LLVM,ARC,174,"Predict the next statement of this code snippet:
 <s> for ( auto I = V . begin ( ) , E = V . end ( ) ; I != E ; ++ I ) { if ( reg == I -> getReg ( ) ) return I ; }"
LLVM,ARC,175,"Predict the next statement of this code snippet:
 <s> bool HasFP = MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MF . getFrameInfo ( ) . isFrameAddressTaken ( ) || RegInfo -> needsStackRealignment ( MF ) ; return HasFP ;"
LLVM,ARC,176,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MF . getFrameInfo ( ) . isFrameAddressTaken ( ) || RegInfo -> needsStackRealignment ( MF ) ; return HasFP ;"
LLVM,ARC,177,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MFI . getStackSize ( ) << <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( MFI . hasStackObjects ( ) ) {"
LLVM,ARC,178,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getParent ( ) -> getName ( ) << <STR_LIT> ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { return true ;"
LLVM,ARC,179,"Predict the next statement of this code snippet:
 <s> void printOperand ( const MCInst * MI , uint64_t , unsigned OpNum , raw_ostream & O ) { printOperand ( MI , OpNum , O ) ;"
LLVM,ARC,180,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << cc << <STR_LIT> ) ; return <STR_LIT> ;"
LLVM,ARC,181,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,ARC,182,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,ARC,183,"Predict the next statement of this code snippet:
 <s> O << <ISA_LIT>CondCodeToString ( ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ) ;"
LLVM,ARC,184,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ;"
LLVM,ARC,185,"Predict the next statement of this code snippet:
 <s> printU6ShiftedBy ( <NUM_LIT> , MI , OpNum , O ) ;"
LLVM,ARC,186,"Predict the next statement of this code snippet:
 <s> unsigned Value2 = Value >> ShiftBy ; if ( Value2 > <NUM_LIT> || ( Value2 << ShiftBy != Value ) ) { errs ( ) << <STR_LIT> << <STR_LIT> << MI -> getOpcode ( ) << <STR_LIT> << Value ; if ( ShiftBy ) errs ( ) << <STR_LIT> << ( <NUM_LIT> << ShiftBy ) << <STR_LIT> ; assert ( false && <STR_LIT> ) ; } } printOperand ( MI , OpNum , O ) ;"
LLVM,ARC,187,"Predict the next statement of this code snippet:
 <s> errs ( ) << <STR_LIT> << <STR_LIT> << MI -> getOpcode ( ) << <STR_LIT> << Value ; if ( ShiftBy ) errs ( ) << <STR_LIT> << ( <NUM_LIT> << ShiftBy ) << <STR_LIT> ; assert ( false && <STR_LIT> ) ; } }"
LLVM,ARC,188,"Predict the next statement of this code snippet:
 <s> static const char * <ISA_LIT>BRCondCodeToString ( <STR_LIT> BRCC ) { switch ( BRCC ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,ARC,189,"Predict the next statement of this code snippet:
 <s> int Offset = <NUM_LIT> ; const MCSymbolRefExpr * SRE ; if ( const auto * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { SRE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; const auto * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ;"
LLVM,ARC,190,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return BadConditionCode ( BRCC ) ;"
LLVM,ARC,191,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,ARC,192,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,ARC,193,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {"
LLVM,ARC,194,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {"
LLVM,ARC,195,"Predict the next statement of this code snippet:
 <s> DEBUG ( dbgs ( ) << <STR_LIT> << cc << <STR_LIT> ) ;"
LLVM,ARC,196,"Predict the next statement of this code snippet:
 <s> static const char * BadConditionCode ( T cc ) { DEBUG ( dbgs ( ) << <STR_LIT> << cc << <STR_LIT> ) ; return <STR_LIT> ;"
LLVM,ARC,197,"Predict the next statement of this code snippet:
 <s> const MCOperand & Op = MI -> getOperand ( OpNum ) ;"
LLVM,ARC,198,"Predict the next statement of this code snippet:
 <s> assert ( Op . isImm ( ) && <STR_LIT> ) ;"
LLVM,ARC,199,"Predict the next statement of this code snippet:
 <s> const auto * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else { SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; } assert ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_None ) ; OS << '@' ; SRE -> getSymbol ( ) . print ( OS , MAI ) ; if ( Offset ) {"
LLVM,ARC,200,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ;"
LLVM,ARC,201,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ;"
LLVM,ARC,202,"Predict the next statement of this code snippet:
 <s> const MCOperand & base = MI -> getOperand ( OpNum ) ; const MCOperand & offset = MI -> getOperand ( OpNum + <NUM_LIT> ) ; assert ( base . isReg ( ) && <STR_LIT> ) ; assert ( offset . isImm ( ) && <STR_LIT> ) ; printRegName ( O , base . getReg ( ) ) ;"
LLVM,ARC,203,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isReg ( ) ) { printRegName ( O , Op . getReg ( ) ) ; return ; } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ; } assert ( Op . isExpr ( ) && <STR_LIT> ) ; printExpr ( Op . getExpr ( ) , & MAI , O ) ;"
LLVM,ARC,204,"Predict the next statement of this code snippet:
 <s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isReg ( ) ) { printRegName ( O , Op . getReg ( ) ) ; return ; } if ( Op . isImm ( ) ) {"
LLVM,ARC,205,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {"
LLVM,ARC,206,"Predict the next statement of this code snippet:
 <s> assert ( Op . isImm ( ) && <STR_LIT> ) ;"
LLVM,ARC,207,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const {"
LLVM,ARC,208,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const {"
LLVM,ARC,209,"Predict the next statement of this code snippet:
 <s> while ( isPredicated ( * I ) || I -> isTerminator ( ) || I -> isDebugValue ( ) ) { bool CantAnalyze = false ; while ( I -> isDebugValue ( ) || ! I -> isTerminator ( ) ) { if ( I == MBB . begin ( ) ) return false ; -- I ; } if ( isJumpOpcode ( I -> getOpcode ( ) ) ) { CantAnalyze = true ; } else if ( isUncondBranchOpcode ( I -> getOpcode ( ) ) ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; } else if ( isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( ! Cond . empty ( ) ) return true ; assert ( ! FBB && <STR_LIT> ) ; FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } else if ( I -> isReturn ( ) ) { CantAnalyze = ! isPredicated ( * I ) ; } else { return true ; } if ( ! isPredicated ( * I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isJumpOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) {"
LLVM,ARC,210,"Predict the next statement of this code snippet:
 <s> unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , Align ) ; assert ( MMO && <STR_LIT> ) ;"
LLVM,ARC,211,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , Align ) ; assert ( MMO && <STR_LIT> ) ; assert ( TRI -> getSpillSize ( * RC ) == <NUM_LIT> && <STR_LIT> ) ; assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ;"
LLVM,ARC,212,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc dl = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , Align ) ; assert ( MMO && <STR_LIT> ) ; assert ( TRI -> getSpillSize ( * RC ) == <NUM_LIT> && <STR_LIT> ) ; assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ;"
LLVM,ARC,213,"Predict the next statement of this code snippet:
 <s> assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ;"
LLVM,ARC,214,"Predict the next statement of this code snippet:
 <s> DebugLoc dl = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , Align ) ;"
LLVM,ARC,215,"Predict the next statement of this code snippet:
 <s> DebugLoc dl = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , Align ) ; assert ( MMO && <STR_LIT> ) ; assert ( TRI -> getSpillSize ( * RC ) == <NUM_LIT> && <STR_LIT> ) ; assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ;"
LLVM,ARC,216,"Predict the next statement of this code snippet:
 <s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , Align ) ; assert ( MMO && <STR_LIT> ) ; assert ( TRI -> getSpillSize ( * RC ) == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,ARC,217,"Predict the next statement of this code snippet:
 <s> DebugLoc dl = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , Align ) ; assert ( MMO && <STR_LIT> ) ; assert ( TRI -> getSpillSize ( * RC ) == <NUM_LIT> && <STR_LIT> ) ; assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( SrcReg , TRI ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; BuildMI ( MBB , I , dl , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;"
LLVM,ARC,218,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & dl , MCRegister DestReg , MCRegister SrcReg , bool KillSrc ) const { assert ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> ) ; assert ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> ) ; BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,ARC,219,"Predict the next statement of this code snippet:
 <s> OffsetPos ++ ; } if ( ! MI . getOperand ( BasePos ) . isReg ( ) || ! MI . getOperand ( OffsetPos ) . isImm ( ) ) return false ;"
LLVM,ARC,220,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: getBaseAndOffsetPosition ( const MachineInstr & MI , unsigned & BasePos , unsigned & OffsetPos ) const { if ( ! MI . mayLoad ( ) && ! MI . mayStore ( ) ) return false ; BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ;"
LLVM,ARC,221,"Predict the next statement of this code snippet:
 <s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;"
LLVM,ARC,222,"Predict the next statement of this code snippet:
 <s> const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ;"
LLVM,ARC,223,"Predict the next statement of this code snippet:
 <s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } int BccOpc = Cond [ <NUM_LIT> ] . isImm ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,ARC,224,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: isPostIncrement ( const MachineInstr & MI ) const { const MCInstrDesc & MID = MI . getDesc ( ) ;"
LLVM,ARC,225,"Predict the next statement of this code snippet:
 <s> const uint64_t F = MID . TSFlags ;"
LLVM,ARC,226,"Predict the next statement of this code snippet:
 <s> const MCInstrDesc & MID = MI . getDesc ( ) ; const uint64_t F = MID . TSFlags ; return ( ( F >> TSF_AddrModeOff ) & TSF_AddModeMask ) == PreInc ;"
LLVM,ARC,227,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ST ) {"
LLVM,ARC,228,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ST ) {"
LLVM,ARC,229,"Predict the next statement of this code snippet:
 <s> assert ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> ) ; assert ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,ARC,230,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , MCRegister DestReg , MCRegister SrcReg , bool KillSrc ) const { assert ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> ) ; assert ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,ARC,231,"Predict the next statement of this code snippet:
 <s> return <NUM_LIT> ; } int BccOpc = Cond [ <NUM_LIT> ] . isImm ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( BccOpc ) ) ; MIB . addMBB ( TBB ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { MIB . add ( Cond [ i ] ) ; } if ( ! FBB ) {"
LLVM,ARC,232,"Predict the next statement of this code snippet:
 <s> if ( isInt < <NUM_LIT> > ( Value ) ) { return BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Value ) . getInstr ( ) ; }"
LLVM,ARC,233,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ;"
LLVM,ARC,234,"Predict the next statement of this code snippet:
 <s> assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchCondition ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false ;"
LLVM,ARC,235,"Predict the next statement of this code snippet:
 <s> assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( SrcReg , TRI ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ;"
LLVM,ARC,236,"Predict the next statement of this code snippet:
 <s> assert ( MMO && <STR_LIT> ) ; assert ( TRI -> getSpillSize ( * RC ) == <NUM_LIT> && <STR_LIT> ) ; assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ;"
LLVM,ARC,237,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ; assert ( MMO && <STR_LIT> ) ; assert ( TRI -> getSpillSize ( * RC ) == <NUM_LIT> && <STR_LIT> ) ; assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( SrcReg , TRI ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; BuildMI ( MBB , I , dl , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;"
LLVM,ARC,238,"Predict the next statement of this code snippet:
 <s> DebugLoc dl = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;"
LLVM,ARC,239,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , ST ( ST ) , RI ( ST ) {"
LLVM,ARC,240,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , ST ( ST ) , RI ( ST ) {"
LLVM,ARC,241,"Predict the next statement of this code snippet:
 <s> } else if ( isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( ! Cond . empty ( ) ) return true ; assert ( ! FBB && <STR_LIT> ) ; FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } else if ( I -> isReturn ( ) ) { CantAnalyze = ! isPredicated ( * I ) ; } else { return true ; } if ( ! isPredicated ( * I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isJumpOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) { Cond . clear ( ) ; FBB = nullptr ; if ( AllowModify ) { MachineBasicBlock :: iterator DI = std :: next ( I ) ; while ( DI != MBB . end ( ) ) { MachineInstr & InstToDelete = * DI ;"
LLVM,ARC,242,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: anchor ( ) {"
LLVM,ARC,243,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: anchor ( ) {"
LLVM,ARC,244,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {"
LLVM,ARC,245,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {"
LLVM,ARC,246,"Predict the next statement of this code snippet:
 <s> assert ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> ) ; assert ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> ) ;"
LLVM,ARC,247,"Predict the next statement of this code snippet:
 <s> assert ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> ) ; assert ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> ) ;"
LLVM,ARC,248,"Predict the next statement of this code snippet:
 <s> return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ;"
LLVM,ARC,249,"Predict the next statement of this code snippet:
 <s> const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ;"
LLVM,ARC,250,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,ARC,251,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {"
LLVM,ARC,252,"Predict the next statement of this code snippet:
 <s> return RI ;"
LLVM,ARC,253,"Predict the next statement of this code snippet:
 <s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } int BccOpc = Cond [ <NUM_LIT> ] . isImm ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( & MBB , dl , get ( BccOpc ) ) ; MIB . addMBB ( TBB ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { MIB . add ( Cond [ i ] ) ; } if ( ! FBB ) { return <NUM_LIT> ;"
LLVM,ARC,254,"Predict the next statement of this code snippet:
 <s> static bool isCondBranchOpcode ( int Opc ) {"
LLVM,ARC,255,"Predict the next statement of this code snippet:
 <s> static bool isJumpOpcode ( int Opc ) {"
LLVM,ARC,256,"Predict the next statement of this code snippet:
 <s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;"
LLVM,ARC,257,"Predict the next statement of this code snippet:
 <s> static bool isLoad ( int Opcode ) {"
LLVM,ARC,258,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { int Opcode = MI . getOpcode ( ) ;"
LLVM,ARC,259,"Predict the next statement of this code snippet:
 <s> static bool isStore ( int Opcode ) { return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;"
LLVM,ARC,260,"Predict the next statement of this code snippet:
 <s> static bool isUncondBranchOpcode ( int Opc ) { return Opc == <STR_LIT> ;"
LLVM,ARC,261,"Predict the next statement of this code snippet:
 <s> return Opc == <STR_LIT> ;"
LLVM,ARC,262,"Predict the next statement of this code snippet:
 <s> static bool isZeroImm ( const MachineOperand & Op ) { return Op . isImm ( ) && Op . getImm ( ) == <NUM_LIT> ;"
LLVM,ARC,263,"Predict the next statement of this code snippet:
 <s> return Op . isImm ( ) && Op . getImm ( ) == <NUM_LIT> ;"
LLVM,ARC,264,"Predict the next statement of this code snippet:
 <s> return BuildMI ( MBB , MI , dl , get ( <STR_LIT> ) , Reg ) . addImm ( Value ) . getInstr ( ) ; } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,ARC,265,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator <ISA_LIT>InstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Reg , uint64_t Value ) const { DebugLoc dl = MBB . findDebugLoc ( MI ) ;"
LLVM,ARC,266,"Predict the next statement of this code snippet:
 <s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , Align ) ; assert ( MMO && <STR_LIT> ) ; assert ( TRI -> getSpillSize ( * RC ) == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,ARC,267,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ;"
LLVM,ARC,268,"Predict the next statement of this code snippet:
 <s> DebugLoc dl = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , Align ) ; assert ( MMO && <STR_LIT> ) ; assert ( TRI -> getSpillSize ( * RC ) == <NUM_LIT> && <STR_LIT> ) ; assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( SrcReg , TRI ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; BuildMI ( MBB , I , dl , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;"
LLVM,ARC,269,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) {"
LLVM,ARC,270,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) {"
LLVM,ARC,271,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;"
LLVM,ARC,272,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;"
LLVM,ARC,273,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,ARC,274,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,ARC,275,"Predict the next statement of this code snippet:
 <s> if ( Addr . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; Base = Addr . getOperand ( <NUM_LIT> ) ;"
LLVM,ARC,276,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrModeFar ( SDValue Addr , SDValue & Base , SDValue & Offset ) { if ( SelectAddrModeS9 ( Addr , Base , Offset ) ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { return false ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { int32_t RHSC = RHS -> getSExtValue ( ) ; if ( Addr . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( RHSC , SDLoc ( Addr ) , <STR_LIT> ) ; return true ;"
LLVM,ARC,277,"Predict the next statement of this code snippet:
 <s> if ( Addr . getOpcode ( ) == <STR_LIT> ) {"
LLVM,ARC,278,"Predict the next statement of this code snippet:
 <s> Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; }"
LLVM,ARC,279,"Predict the next statement of this code snippet:
 <s> return false ; } if ( Addr . getOpcode ( ) != <STR_LIT> && Addr . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( Addr ) ) { if ( Addr . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Addr ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } else { Base = Addr ; } Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { int32_t RHSC = RHS -> getSExtValue ( ) ; if ( Addr . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ;"
LLVM,ARC,280,"Predict the next statement of this code snippet:
 <s> } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { int32_t RHSC = RHS -> getSExtValue ( ) ; if ( Addr . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ! isInt < <NUM_LIT> > ( RHSC ) ) return false ; Base = Addr . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } Offset = CurDAG -> getTargetConstant ( RHSC , SDLoc ( Addr ) , <STR_LIT> ) ;"
LLVM,ARC,281,"Predict the next statement of this code snippet:
 <s> Pred = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( N ) , <STR_LIT> ) ;"
LLVM,ARC,282,"Predict the next statement of this code snippet:
 <s> Pred = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( N ) , <STR_LIT> ) ; Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return true ;"
LLVM,ARC,283,"Predict the next statement of this code snippet:
 <s> return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = nullptr ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ;"
LLVM,ARC,284,"Predict the next statement of this code snippet:
 <s> ConstantSDNode * CN = nullptr ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } }"
LLVM,ARC,285,"Predict the next statement of this code snippet:
 <s> DEBUG ( errs ( ) << <STR_LIT> << ( unsigned ) RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgIn = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; CFRegNode . push_back ( ArgIn . getValue ( ArgIn -> getNumValues ( ) - <NUM_LIT> ) ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) ; assert ( ( ObjSize <= StackSlotSize ) && <STR_LIT> ) ; int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgIn = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } const ArgDataPair ADP = { ArgIn , Ins [ i ] . Flags } ; ArgData . push_back ( ADP ) ; } if ( IsVarArg ) { static const MCPhysReg ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FirstVAReg = CCInfo . getFirstUnallocated ( ArgRegs ) ; if ( FirstVAReg < array_lengthof ( ArgRegs ) ) { int Offset = <NUM_LIT> ; int VarFI = MFI . CreateFixedObject ( ( array_lengthof ( ArgRegs ) - FirstVAReg ) * <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ; AFI -> setVarArgsFrameIndex ( VarFI ) ; SDValue FIN = DAG . getFrameIndex ( VarFI , <STR_LIT> ) ; for ( unsigned i = FirstVAReg ; i < array_lengthof ( ArgRegs ) ; i ++ ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ;"
LLVM,ARC,286,"Predict the next statement of this code snippet:
 <s> assert ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> && <STR_LIT> ) ; Register FrameReg = ARI . getFrameRegister ( MF ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ;"
LLVM,ARC,287,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo & ARI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; assert ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> && <STR_LIT> ) ; Register FrameReg = ARI . getFrameRegister ( MF ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ;"
LLVM,ARC,288,"Predict the next statement of this code snippet:
 <s> assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) ; assert ( ( ObjSize <= StackSlotSize ) && <STR_LIT> ) ; int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgIn = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } const ArgDataPair ADP = { ArgIn , Ins [ i ] . Flags } ; ArgData . push_back ( ADP ) ; } if ( IsVarArg ) { static const MCPhysReg ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FirstVAReg = CCInfo . getFirstUnallocated ( ArgRegs ) ; if ( FirstVAReg < array_lengthof ( ArgRegs ) ) { int Offset = <NUM_LIT> ; int VarFI = MFI . CreateFixedObject ( ( array_lengthof ( ArgRegs ) - FirstVAReg ) * <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ; AFI -> setVarArgsFrameIndex ( VarFI ) ; SDValue FIN = DAG . getFrameIndex ( VarFI , <STR_LIT> ) ; for ( unsigned i = FirstVAReg ; i < array_lengthof ( ArgRegs ) ; i ++ ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; CFRegNode . push_back ( Val . getValue ( Val -> getNumValues ( ) - <NUM_LIT> ) ) ; SDValue VAObj = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FIN , DAG . getConstant ( Offset , dl , <STR_LIT> ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , VAObj , MachinePointerInfo ( ) ) ; MemOps . push_back ( Store ) ; Offset += <NUM_LIT> ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } if ( ! CFRegNode . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CFRegNode ) ; for ( const auto & ArgDI : ArgData ) { if ( ArgDI . Flags . isByVal ( ) && ArgDI . Flags . getByValSize ( ) ) {"
LLVM,ARC,289,"Predict the next statement of this code snippet:
 <s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> :"
LLVM,ARC,290,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( & DAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << N -> use_size ( ) << <STR_LIT> ) ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue V = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , V ) ; Results . push_back ( Op ) ; Results . push_back ( V . getValue ( <NUM_LIT> ) ) ; } break ; default : break ; }"
LLVM,ARC,291,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,ARC,292,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;"
LLVM,ARC,293,"Predict the next statement of this code snippet:
 <s> setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,ARC,294,"Predict the next statement of this code snippet:
 <s> computeRegisterProperties ( Subtarget . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: Source ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,ARC,295,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ;"
LLVM,ARC,296,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return nullptr ;"
LLVM,ARC,297,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,ARC,298,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,ARC,299,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const {"
LLVM,ARC,300,"Predict the next statement of this code snippet:
 <s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> arcCC = ISDCCto<ISA_LIT>CC ( CC ) ; assert ( LHS . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , LHS , RHS , DAG . getConstant ( arcCC , dl , <STR_LIT> ) ) ;"
LLVM,ARC,301,"Predict the next statement of this code snippet:
 <s> SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , SOffset ) ; SDValue Store = DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) ) ; MemOpChains . push_back ( Store ) ; IsTailCall = false ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue Glue ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; } bool IsDirect = true ; if ( auto * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( auto * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; else IsDirect = false ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ;"
LLVM,ARC,302,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : return LowerCallArguments ( Chain , CallConv , IsVarArg , Ins , dl , DAG , InVals ) ; }"
LLVM,ARC,303,"Predict the next statement of this code snippet:
 <s> MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; assert ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned FrameReg = ARI . getFrameRegister ( MF ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ;"
LLVM,ARC,304,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo & ARI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ;"
LLVM,ARC,305,"Predict the next statement of this code snippet:
 <s> const GlobalValue * GV = GN -> getGlobal ( ) ; SDLoc dl ( GN ) ; int64_t Offset = GN -> getOffset ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , Offset ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ;"
LLVM,ARC,306,"Predict the next statement of this code snippet:
 <s> int64_t Offset = GN -> getOffset ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , Offset ) ;"
LLVM,ARC,307,"Predict the next statement of this code snippet:
 <s> auto * N = cast < JumpTableSDNode > ( Op ) ; SDValue GA = DAG . getTargetJumpTable ( N -> getIndex ( ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , GA ) ;"
LLVM,ARC,308,"Predict the next statement of this code snippet:
 <s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> :"
LLVM,ARC,309,"Predict the next statement of this code snippet:
 <s> CCValAssign & VA = RVLocs [ i ] ; if ( VA . isRegLoc ( ) ) continue ; assert ( VA . isMemLoc ( ) ) ; if ( IsVarArg ) { report_fatal_error ( <STR_LIT> ) ; } int Offset = VA . getLocMemOffset ( ) ; unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , OutVals [ i ] , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; }"
LLVM,ARC,310,"Predict the next statement of this code snippet:
 <s> unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , OutVals [ i ] , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( ! VA . isRegLoc ( ) ) continue ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;"
LLVM,ARC,311,"Predict the next statement of this code snippet:
 <s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ;"
LLVM,ARC,312,"Predict the next statement of this code snippet:
 <s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned Width = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) ; if ( Width == <NUM_LIT> || Width == <NUM_LIT> ) return Op ; if ( Width >= <NUM_LIT> ) { return { } ; } SDValue LS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , DAG . getConstant ( <NUM_LIT> - Width , dl , <STR_LIT> ) ) ; SDValue SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LS , DAG . getConstant ( <NUM_LIT> - Width , dl , <STR_LIT> ) ) ;"
LLVM,ARC,313,"Predict the next statement of this code snippet:
 <s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned Width = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) ; if ( Width == <NUM_LIT> || Width == <NUM_LIT> ) return Op ; if ( Width >= <NUM_LIT> ) { return { } ;"
LLVM,ARC,314,"Predict the next statement of this code snippet:
 <s> SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ;"
LLVM,ARC,315,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const {"
LLVM,ARC,316,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return false ;"
LLVM,ARC,317,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { return { } ;"
LLVM,ARC,318,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const {"
LLVM,ARC,319,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) { MF . setAlignment ( <NUM_LIT> ) ;"
LLVM,ARC,320,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) {"
LLVM,ARC,321,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) {"
LLVM,ARC,322,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) { MF . setAlignment ( Align ( <NUM_LIT> ) ) ;"
LLVM,ARC,323,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FunctionInfo :: anchor ( ) {"
LLVM,ARC,324,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FunctionInfo :: anchor ( ) {"
LLVM,ARC,325,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgFrameBytes ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) {"
LLVM,ARC,326,"Predict the next statement of this code snippet:
 <s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex ;"
LLVM,ARC,327,"Predict the next statement of this code snippet:
 <s> void setReturnStackOffset ( unsigned value ) { assert ( ! ReturnStackOffsetSet && <STR_LIT> ) ; ReturnStackOffset = value ;"
LLVM,ARC,328,"Predict the next statement of this code snippet:
 <s> ReturnStackOffset = value ;"
LLVM,ARC,329,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>FunctionInfo ( ) {"
LLVM,ARC,330,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>FunctionInfo ( ) {"
LLVM,ARC,331,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {"
LLVM,ARC,332,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {"
LLVM,ARC,333,"Predict the next statement of this code snippet:
 <s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ;"
LLVM,ARC,334,"Predict the next statement of this code snippet:
 <s> AllowAtInName = true ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; ExceptionsType = ExceptionHandling :: DwarfCFI ;"
LLVM,ARC,335,"Predict the next statement of this code snippet:
 <s> for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ; }"
LLVM,ARC,336,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext * C , AsmPrinter & AsmPrinter ) : Ctx ( C ) , Printer ( AsmPrinter ) {"
LLVM,ARC,337,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext * C , AsmPrinter & AsmPrinter ) : Ctx ( C ) , Printer ( AsmPrinter ) {"
LLVM,ARC,338,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const {"
LLVM,ARC,339,"Predict the next statement of this code snippet:
 <s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ;"
LLVM,ARC,340,"Predict the next statement of this code snippet:
 <s> if ( MO . isImplicit ( ) ) break ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + Offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy , Offset ) ; case MachineOperand :: MO_RegisterMask :"
LLVM,ARC,341,"Predict the next statement of this code snippet:
 <s> switch ( MOTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + Offset ) ;"
LLVM,ARC,342,"Predict the next statement of this code snippet:
 <s> case MachineOperand :: MO_GlobalAddress : Symbol = Printer . getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } assert ( Symbol && <STR_LIT> ) ;"
LLVM,ARC,343,"Predict the next statement of this code snippet:
 <s> MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;"
LLVM,ARC,344,"Predict the next statement of this code snippet:
 <s> Target & The<ISA_LIT>Target = getThe<ISA_LIT>Target ( ) ; RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;"
LLVM,ARC,345,"Predict the next statement of this code snippet:
 <s> auto * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;"
LLVM,ARC,346,"Predict the next statement of this code snippet:
 <s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ;"
LLVM,ARC,347,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {"
LLVM,ARC,348,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {"
LLVM,ARC,349,"Predict the next statement of this code snippet:
 <s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;"
LLVM,ARC,350,"Predict the next statement of this code snippet:
 <s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;"
LLVM,ARC,351,"Predict the next statement of this code snippet:
 <s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;"
LLVM,ARC,352,"Predict the next statement of this code snippet:
 <s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {"
LLVM,ARC,353,"Predict the next statement of this code snippet:
 <s> auto * X = new MCInstrInfo ( ) ;"
LLVM,ARC,354,"Predict the next statement of this code snippet:
 <s> auto * X = new MCRegisterInfo ( ) ;"
LLVM,ARC,355,"Predict the next statement of this code snippet:
 <s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;"
LLVM,ARC,356,"Predict the next statement of this code snippet:
 <s> static MCTargetStreamer * createTargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetStreamer ( S ) ;"
LLVM,ARC,357,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;"
LLVM,ARC,358,"Predict the next statement of this code snippet:
 <s> RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;"
LLVM,ARC,359,"Predict the next statement of this code snippet:
 <s> if ( IsStore ) { Src = Ldst . getOperand ( BasePos - <NUM_LIT> ) ; Ldst . RemoveOperand ( BasePos - <NUM_LIT> ) ; } Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false ) ) ;"
LLVM,ARC,360,"Predict the next statement of this code snippet:
 <s> Register BaseReg = Ldst . getOperand ( BasePos ) . getReg ( ) ; Ldst . RemoveOperand ( OffPos ) ; Ldst . RemoveOperand ( BasePos ) ; if ( IsStore ) { Src = Ldst . getOperand ( BasePos - <NUM_LIT> ) ; Ldst . RemoveOperand ( BasePos - <NUM_LIT> ) ; } Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false ) ) ;"
LLVM,ARC,361,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ; dbgs ( ) << <STR_LIT> << * First << <STR_LIT> << * Last << <STR_LIT> ; ) ; MachineInstr * Result = Ldst . getNextNode ( ) ; if ( MoveTo == & Add ) {"
LLVM,ARC,362,"Predict the next statement of this code snippet:
 <s> Register B = Base . getReg ( ) ; if ( Register :: isStackSlot ( B ) || ! Register :: isVirtualRegister ( B ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ;"
LLVM,ARC,363,"Predict the next statement of this code snippet:
 <s> return nullptr ; } } SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterLdst ; SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterAdd ; for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( BaseReg ) ) { if ( & MI == Ldst || & MI == Add ) continue ; if ( & MI != Add && MDT -> dominates ( Ldst , & MI ) ) UsesAfterLdst . push_back ( & MI ) ; else if ( ! MDT -> dominates ( & MI , Ldst ) ) return nullptr ; if ( MDT -> dominates ( Add , & MI ) ) UsesAfterAdd . push_back ( & MI ) ; } MachineInstr * Result = nullptr ; if ( First == Add ) { if ( noUseOfAddBeforeLoadOrStore ( First , Last ) ) { Result = Last ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else if ( canHoistLoadStoreTo ( Ldst , Add ) ) { Result = First ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } else {"
LLVM,ARC,364,"Predict the next statement of this code snippet:
 <s> MachineInstr * First = Add ; MachineInstr * Last = Ldst ; if ( MDT -> dominates ( Ldst , Add ) ) std :: swap ( First , Last ) ; else if ( ! MDT -> dominates ( Add , Ldst ) ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * First << * Last ) ; unsigned BasePos , OffPos ; if ( ! AII -> getBaseAndOffsetPosition ( * Ldst , BasePos , OffPos ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register BaseReg = Ldst -> getOperand ( BasePos ) . getReg ( ) ; if ( Ldst -> mayStore ( ) && Ldst -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register StReg = Ldst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Add -> getOperand ( <NUM_LIT> ) . getReg ( ) == StReg || BaseReg == StReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } } SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterLdst ; SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterAdd ; for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( BaseReg ) ) { if ( & MI == Ldst || & MI == Add ) continue ; if ( & MI != Add && MDT -> dominates ( Ldst , & MI ) ) UsesAfterLdst . push_back ( & MI ) ; else if ( ! MDT -> dominates ( & MI , Ldst ) ) return nullptr ; if ( MDT -> dominates ( Add , & MI ) ) UsesAfterAdd . push_back ( & MI ) ; } MachineInstr * Result = nullptr ; if ( First == Add ) {"
LLVM,ARC,365,"Predict the next statement of this code snippet:
 <s> Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false ) ) ; Ldst . addOperand ( NewOffset ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Ldst ) ;"
LLVM,ARC,366,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock * MBB = User -> getOperand ( BBOperandIdx ) . getMBB ( ) ; if ( MBB -> empty ( ) ) { const MachineBasicBlock * InstBB = MI -> getParent ( ) ; assert ( InstBB != MBB && <STR_LIT> ) ; if ( ! MDT -> dominates ( InstBB , MBB ) ) return false ; continue ; }"
LLVM,ARC,367,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>OptAddrMode :: noUseOfAddBeforeLoadOrStore ( const MachineInstr * Add , const MachineInstr * Ldst ) { Register R = Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return dominatesAllUsesOf ( Ldst , R , MDT , MRI ) ;"
LLVM,ARC,368,"Predict the next statement of this code snippet:
 <s> AII = AST -> getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; for ( auto & MBB : MF ) Changed |= processBasicBlock ( MBB ) ; if ( DUMP_AFTER ( ) ) MF . dump ( ) ; if ( VIEW_AFTER ( ) ) MF . viewCFG ( ) ;"
LLVM,ARC,369,"Predict the next statement of this code snippet:
 <s> for ( auto & MBB : MF ) Changed |= processBasicBlock ( MBB ) ; if ( DUMP_AFTER ( ) ) MF . dump ( ) ; if ( VIEW_AFTER ( ) ) MF . viewCFG ( ) ;"
LLVM,ARC,370,"Predict the next statement of this code snippet:
 <s> } MachineOperand & Base = Ldst . getOperand ( BasePos ) ; MachineOperand & Offset = Ldst . getOperand ( OffsetPos ) ; assert ( Base . isReg ( ) && <STR_LIT> ) ; if ( ! Offset . isImm ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register B = Base . getReg ( ) ; if ( Register :: isStackSlot ( B ) || ! Register :: isVirtualRegister ( B ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ; dbgs ( ) << <STR_LIT> << * First << <STR_LIT> << * Last << <STR_LIT> ;"
LLVM,ARC,371,"Predict the next statement of this code snippet:
 <s> assert ( Base . isReg ( ) && <STR_LIT> ) ; if ( ! Offset . isImm ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register B = Base . getReg ( ) ; if ( Register :: isStackSlot ( B ) || ! Register :: isVirtualRegister ( B ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ; dbgs ( ) << <STR_LIT> << * First << <STR_LIT> << * Last << <STR_LIT> ; ) ; MachineInstr * Result = Ldst . getNextNode ( ) ; if ( MoveTo == & Add ) { Ldst . removeFromParent ( ) ; Add . getParent ( ) -> insertAfter ( Add . getIterator ( ) , & Ldst ) ; } if ( Result == & Add ) Result = Result -> getNextNode ( ) ; fixPastUses ( Uses , B , Incr ) ;"
LLVM,ARC,372,"Predict the next statement of this code snippet:
 <s> unsigned ValReg = IsLoad ? Ldst -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ; for ( ; MI != ME && MI != End ; ++ MI ) { if ( MI -> isDebugValue ( ) ) continue ; if ( MI -> mayStore ( ) || MI -> isCall ( ) || MI -> isInlineAsm ( ) || MI -> hasUnmodeledSideEffects ( ) ) return false ; if ( IsStore && MI -> mayLoad ( ) ) return false ; if ( ValReg && MI -> readsVirtualRegister ( ValReg ) ) return false ; }"
LLVM,ARC,373,"Predict the next statement of this code snippet:
 <s> Sign = - <NUM_LIT> ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; Amount = Sign * MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ;"
LLVM,ARC,374,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>OptAddrMode ( ) : MachineFunctionPass ( ID ) {"
LLVM,ARC,375,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>OptAddrMode ( ) : MachineFunctionPass ( ID ) {"
LLVM,ARC,376,"Predict the next statement of this code snippet:
 <s> int64_t Dummy ; if ( isAddConstantOp ( * MI , Dummy ) ) { if ( isValidIncrementOffset ( Dummy + NewOffset ) ) continue ; return false ; } if ( isLoadStoreThatCanHandleDisplacement ( AII , * MI , - NewOffset ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << - NewOffset << <STR_LIT> << * MI ) ; return false ;"
LLVM,ARC,377,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: const_iterator MI ( To ) , ME ( Ldst ) , End ( Ldst -> getParent ( ) -> end ( ) ) ; bool IsStore = Ldst -> mayStore ( ) ; for ( ; MI != ME && MI != End ; ++ MI ) { if ( MI -> isDebugValue ( ) ) continue ; if ( MI -> mayStore ( ) || MI -> isCall ( ) || MI -> isInlineAsm ( ) || MI -> hasUnmodeledSideEffects ( ) ) return false ; if ( IsStore && MI -> mayLoad ( ) ) return false ; } for ( auto & O : Ldst -> explicit_operands ( ) ) { if ( ! O . isReg ( ) || ! O . isUse ( ) ) continue ; MachineInstr * OpDef = MRI -> getVRegDef ( O . getReg ( ) ) ; if ( ! OpDef || ! MDT -> dominates ( OpDef , To ) ) return false ; }"
LLVM,ARC,378,"Predict the next statement of this code snippet:
 <s> if ( & MI != Add && MDT -> dominates ( Ldst , & MI ) ) UsesAfterLdst . push_back ( & MI ) ; else if ( ! MDT -> dominates ( & MI , Ldst ) ) return nullptr ; if ( MDT -> dominates ( Add , & MI ) ) UsesAfterAdd . push_back ( & MI ) ; } MachineInstr * Result = nullptr ; if ( First == Add ) { if ( noUseOfAddBeforeLoadOrStore ( First , Last ) ) { Result = Last ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else if ( canHoistLoadStoreTo ( Ldst , Add ) ) { Result = First ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } else { Result = First ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;"
LLVM,ARC,379,"Predict the next statement of this code snippet:
 <s> unsigned BasePos , OffPos ; if ( ! AII -> getBaseAndOffsetPosition ( * Ldst , BasePos , OffPos ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } unsigned BaseReg = Ldst -> getOperand ( BasePos ) . getReg ( ) ; if ( Ldst -> mayStore ( ) && Ldst -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned StReg = Ldst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Add -> getOperand ( <NUM_LIT> ) . getReg ( ) == StReg || BaseReg == StReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } } SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterLdst ; SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterAdd ; for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( BaseReg ) ) { if ( & MI == Ldst || & MI == Add ) continue ; if ( & MI != Add && MDT -> dominates ( Ldst , & MI ) ) UsesAfterLdst . push_back ( & MI ) ; else if ( ! MDT -> dominates ( & MI , Ldst ) ) return nullptr ;"
LLVM,ARC,380,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: const_iterator MI ( Ldst ) , ME ( To ) , End ( Ldst -> getParent ( ) -> end ( ) ) ; bool IsStore = Ldst -> mayStore ( ) ; bool IsLoad = Ldst -> mayLoad ( ) ; Register ValReg = IsLoad ? Ldst -> getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; for ( ; MI != ME && MI != End ; ++ MI ) { if ( MI -> isDebugValue ( ) ) continue ; if ( MI -> mayStore ( ) || MI -> isCall ( ) || MI -> isInlineAsm ( ) || MI -> hasUnmodeledSideEffects ( ) ) return false ;"
LLVM,ARC,381,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>OptAddrMode :: changeToAddrMode ( MachineInstr & Ldst , unsigned NewOpcode , unsigned NewBase , MachineOperand & NewOffset ) { bool IsStore = Ldst . mayStore ( ) ; unsigned BasePos , OffPos ; MachineOperand Src = MachineOperand :: CreateImm ( <NUM_LIT> ) ; AII -> getBaseAndOffsetPosition ( Ldst , BasePos , OffPos ) ; unsigned BaseReg = Ldst . getOperand ( BasePos ) . getReg ( ) ; Ldst . RemoveOperand ( OffPos ) ; Ldst . RemoveOperand ( BasePos ) ; if ( IsStore ) { Src = Ldst . getOperand ( BasePos - <NUM_LIT> ) ; Ldst . RemoveOperand ( BasePos - <NUM_LIT> ) ; } Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false ) ) ; Ldst . addOperand ( NewOffset ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Ldst ) ;"
LLVM,ARC,382,"Predict the next statement of this code snippet:
 <s> Ldst . RemoveOperand ( OffPos ) ; Ldst . RemoveOperand ( BasePos ) ; if ( IsStore ) { Src = Ldst . getOperand ( BasePos - <NUM_LIT> ) ; Ldst . RemoveOperand ( BasePos - <NUM_LIT> ) ; } Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ;"
LLVM,ARC,383,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>OptAddrMode ( ) { return new <ISA_LIT>OptAddrMode ( ) ;"
LLVM,ARC,384,"Predict the next statement of this code snippet:
 <s> const MachineBasicBlock * InstBB = MI -> getParent ( ) ; assert ( InstBB != MBB && <STR_LIT> ) ; if ( ! MDT -> dominates ( InstBB , MBB ) ) return false ; continue ; } User = & * MBB -> rbegin ( ) ; } if ( ! MDT -> dominates ( MI , User ) ) return false ;"
LLVM,ARC,385,"Predict the next statement of this code snippet:
 <s> OffPos = <NUM_LIT> ; } else if ( AII -> getBaseAndOffsetPosition ( * MI , BasePos , OffPos ) ) { MachineOperand & MO = MI -> getOperand ( OffPos ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; NewOffset += MO . getImm ( ) ; assert ( isValidLoadStoreOffset ( NewOffset ) && <STR_LIT> ) ;"
LLVM,ARC,386,"Predict the next statement of this code snippet:
 <s> assert ( isValidIncrementOffset ( NewOffset ) && <STR_LIT> ) ; BasePos = <NUM_LIT> ; OffPos = <NUM_LIT> ; } else if ( AII -> getBaseAndOffsetPosition ( * MI , BasePos , OffPos ) ) { MachineOperand & MO = MI -> getOperand ( OffPos ) ;"
LLVM,ARC,387,"Predict the next statement of this code snippet:
 <s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;"
LLVM,ARC,388,"Predict the next statement of this code snippet:
 <s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;"
LLVM,ARC,389,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return OPTADDRMODE_DESC ;"
LLVM,ARC,390,"Predict the next statement of this code snippet:
 <s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : Sign = - <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ;"
LLVM,ARC,391,"Predict the next statement of this code snippet:
 <s> if ( ! MO . isImm ( ) ) return false ; int64_t Offset = MO . getImm ( ) + Disp ;"
LLVM,ARC,392,"Predict the next statement of this code snippet:
 <s> return isUInt < <NUM_LIT> > ( Off ) ;"
LLVM,ARC,393,"Predict the next statement of this code snippet:
 <s> return isUInt < <NUM_LIT> > ( Off ) ;"
LLVM,ARC,394,"Predict the next statement of this code snippet:
 <s> static bool isValidLoadStoreOffset ( int64_t Off ) { return isInt < <NUM_LIT> > ( Off ) ;"
LLVM,ARC,395,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>OptAddrMode :: noUseOfAddBeforeLoadOrStore ( const MachineInstr * Add , const MachineInstr * Ldst ) {"
LLVM,ARC,396,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>OptAddrMode :: noUseOfAddBeforeLoadOrStore ( const MachineInstr * Add , const MachineInstr * Ldst ) { unsigned R = Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return dominatesAllUsesOf ( Ldst , R , MDT , MRI ) ;"
LLVM,ARC,397,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>OptAddrMode :: processBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; for ( auto MI = MBB . begin ( ) , ME = MBB . end ( ) ; MI != ME ; ++ MI ) { if ( MI -> isDebugValue ( ) ) continue ; if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) continue ; if ( <STR_LIT> ( MI -> getOpcode ( ) ) < <NUM_LIT> ) continue ; MachineInstr * Res = tryToCombine ( * MI ) ; if ( Res ) { Changed = true ; MI = std :: prev ( Res -> getIterator ( ) ) ; } }"
LLVM,ARC,398,"Predict the next statement of this code snippet:
 <s> if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) continue ; if ( <STR_LIT> ( MI -> getOpcode ( ) ) < <NUM_LIT> ) continue ; MachineInstr * Res = tryToCombine ( * MI ) ; if ( Res ) { Changed = true ; MI = std :: prev ( Res -> getIterator ( ) ) ; }"
LLVM,ARC,399,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>OptAddrMode :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; AST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AII = AST -> getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ;"
LLVM,ARC,400,"Predict the next statement of this code snippet:
 <s> MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; for ( auto & MBB : MF ) Changed |= processBasicBlock ( MBB ) ; return Changed ;"
LLVM,ARC,401,"Predict the next statement of this code snippet:
 <s> return MF . needsFrameMoves ( ) ;"
LLVM,ARC,402,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; int ObjSize = MF . getFrameInfo ( ) . getObjectSize ( FrameIndex ) ; int StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int LocalFrameSize = MF . getFrameInfo ( ) . getLocalFrameSize ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << MI << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ObjSize << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << StackSize << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << LocalFrameSize << <STR_LIT> ) ; ( void ) LocalFrameSize ; if ( MI . isDebugValue ( ) ) { unsigned FrameReg = getFrameRegister ( MF ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; if ( ! TFI -> hasFP ( MF ) ) { Offset = StackSize + Offset ; if ( FrameIndex >= <NUM_LIT> ) assert ( ( Offset >= <NUM_LIT> && Offset < StackSize ) && <STR_LIT> ) ; } else { if ( FrameIndex >= <NUM_LIT> ) {"
LLVM,ARC,403,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,ARC,404,"Predict the next statement of this code snippet:
 <s> MachineOperand & FrameOp = MI . getOperand ( FIOperandNum ) ; int FrameIndex = FrameOp . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; int ObjSize = MF . getFrameInfo ( ) . getObjectSize ( FrameIndex ) ; int StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int LocalFrameSize = MF . getFrameInfo ( ) . getLocalFrameSize ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << MI << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ObjSize << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << StackSize << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << LocalFrameSize << <STR_LIT> ) ; ( void ) LocalFrameSize ; if ( MI . isDebugValue ( ) ) { unsigned FrameReg = getFrameRegister ( MF ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; if ( ! TFI -> hasFP ( MF ) ) { Offset = StackSize + Offset ; if ( FrameIndex >= <NUM_LIT> ) assert ( ( Offset >= <NUM_LIT> && Offset < StackSize ) && <STR_LIT> ) ; } else { if ( FrameIndex >= <NUM_LIT> ) { assert ( ( Offset < <NUM_LIT> && - Offset <= StackSize ) && <STR_LIT> ) ; } }"
LLVM,ARC,405,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {"
LLVM,ARC,406,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;"
LLVM,ARC,407,"Predict the next statement of this code snippet:
 <s> } if ( MI . getOpcode ( ) != <STR_LIT> && ( Offset >= <NUM_LIT> || Offset < - <NUM_LIT> ) ) { BaseReg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! BaseReg ) { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; BaseReg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( BaseReg && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( BaseReg , TRI ) << <STR_LIT> << printReg ( FrameReg , TRI ) << <STR_LIT> << Offset << <STR_LIT> ) ; ( void ) TRI ; RS -> setRegUsed ( BaseReg ) ; } unsigned AddOpc = isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( AddOpc ) ) . addReg ( BaseReg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; KillState = RegState :: Kill ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> :"
LLVM,ARC,408,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , ST ( ST ) {"
LLVM,ARC,409,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , ST ( ST ) {"
LLVM,ARC,410,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineOperand & FrameOp = MI . getOperand ( FIOperandNum ) ; int FrameIndex = FrameOp . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; int ObjSize = MF . getFrameInfo ( ) . getObjectSize ( FrameIndex ) ; int StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int LocalFrameSize = MF . getFrameInfo ( ) . getLocalFrameSize ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << MI << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ObjSize << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << StackSize << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << LocalFrameSize << <STR_LIT> ) ; ( void ) LocalFrameSize ; if ( MI . isDebugValue ( ) ) { Register FrameReg = getFrameRegister ( MF ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; if ( ! TFI -> hasFP ( MF ) ) { Offset = StackSize + Offset ; if ( FrameIndex >= <NUM_LIT> ) assert ( ( Offset >= <NUM_LIT> && Offset < StackSize ) && <STR_LIT> ) ; } else { if ( FrameIndex >= <NUM_LIT> ) { assert ( ( Offset < <NUM_LIT> && - Offset <= StackSize ) && <STR_LIT> ) ; } } replaceFrameIndex ( II , TII , Reg , getFrameRegister ( MF ) , Offset , StackSize , ObjSize , RS , SPAdj ) ;"
LLVM,ARC,411,"Predict the next statement of this code snippet:
 <s> BaseReg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! BaseReg ) { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; BaseReg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( BaseReg && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( BaseReg , TRI ) << <STR_LIT> << printReg ( FrameReg , TRI ) << <STR_LIT> << Offset << <STR_LIT> ) ; ( void ) TRI ; RS -> setRegUsed ( BaseReg ) ; } unsigned AddOpc = isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , DL , TII . get ( AddOpc ) ) . addReg ( BaseReg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; KillState = RegState :: Kill ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII . get ( MI . getOpcode ( ) ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII . get ( isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; break ; default :"
LLVM,ARC,412,"Predict the next statement of this code snippet:
 <s> if ( MI . getOpcode ( ) != <STR_LIT> && ( Offset >= <NUM_LIT> || Offset < - <NUM_LIT> ) ) { BaseReg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! BaseReg ) { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; BaseReg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( BaseReg && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( BaseReg , TRI ) << <STR_LIT> << PrintReg ( FrameReg , TRI ) << <STR_LIT> << Offset << <STR_LIT> ) ; ( void ) TRI ; RS -> setRegUsed ( BaseReg ) ; } unsigned AddOpc = isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( AddOpc ) ) . addReg ( BaseReg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; KillState = RegState :: Kill ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ;"
LLVM,ARC,413,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {"
LLVM,ARC,414,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {"
LLVM,ARC,415,"Predict the next statement of this code snippet:
 <s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; if ( ! TFI -> hasFP ( MF ) ) { Offset = StackSize + Offset ; if ( FrameIndex >= <NUM_LIT> ) assert ( ( Offset >= <NUM_LIT> && Offset < StackSize ) && <STR_LIT> ) ; } else { if ( FrameIndex >= <NUM_LIT> ) { assert ( ( Offset < <NUM_LIT> && - Offset <= StackSize ) && <STR_LIT> ) ; }"
LLVM,ARC,416,"Predict the next statement of this code snippet:
 <s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {"
LLVM,ARC,417,"Predict the next statement of this code snippet:
 <s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {"
LLVM,ARC,418,"Predict the next statement of this code snippet:
 <s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_<ISA_LIT>_RegMask ;"
LLVM,ARC,419,"Predict the next statement of this code snippet:
 <s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_<ISA_LIT>_RegMask ;"
LLVM,ARC,420,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;"
LLVM,ARC,421,"Predict the next statement of this code snippet:
 <s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;"
LLVM,ARC,422,"Predict the next statement of this code snippet:
 <s> return MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) . needsUnwindTableEntry ( ) ;"
LLVM,ARC,423,"Predict the next statement of this code snippet:
 <s> ( void ) TRI ; RS -> setRegUsed ( BaseReg ) ; } unsigned AddOpc = isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( AddOpc ) ) . addReg ( BaseReg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; KillState = RegState :: Kill ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;"
LLVM,ARC,424,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ;"
LLVM,ARC,425,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ;"
LLVM,ARC,426,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const {"
LLVM,ARC,427,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return true ;"
LLVM,ARC,428,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , InstrInfo ( * this ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {"
LLVM,ARC,429,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , InstrInfo ( * this ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {"
LLVM,ARC,430,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {"
LLVM,ARC,431,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {"
LLVM,ARC,432,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>Subtarget :: anchor ( ) {"
LLVM,ARC,433,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>Subtarget :: anchor ( ) {"
LLVM,ARC,434,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {"
LLVM,ARC,435,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {"
LLVM,ARC,436,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override {"
LLVM,ARC,437,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override {"
LLVM,ARC,438,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ;"
LLVM,ARC,439,"Predict the next statement of this code snippet:
 <s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;"
LLVM,ARC,440,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {"
LLVM,ARC,441,"Predict the next statement of this code snippet:
 <s> return & TLInfo ;"
LLVM,ARC,442,"Predict the next statement of this code snippet:
 <s> bool hasNorm ( ) const { return Xnorm ;"
LLVM,ARC,443,"Predict the next statement of this code snippet:
 <s> RegisterTarget < Triple :: arc > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ) ;"
LLVM,ARC,444,"Predict the next statement of this code snippet:
 <s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;"
LLVM,ARC,445,"Predict the next statement of this code snippet:
 <s> return RM . getValueOr ( Reloc :: Static ) ;"
LLVM,ARC,446,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) {"
LLVM,ARC,447,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getRelocModel ( RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {"
LLVM,ARC,448,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getRelocModel ( RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;"
LLVM,ARC,449,"Predict the next statement of this code snippet:
 <s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM ) {"
LLVM,ARC,450,"Predict the next statement of this code snippet:
 <s> if ( CM ) return * CM ;"
LLVM,ARC,451,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Target ( ) {"
LLVM,ARC,452,"Predict the next statement of this code snippet:
 <s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;"
LLVM,ARC,453,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {"
LLVM,ARC,454,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) {"
LLVM,ARC,455,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) {"
LLVM,ARC,456,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {"
LLVM,ARC,457,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {"
LLVM,ARC,458,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;"
LLVM,ARC,459,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>PassConfig ( * this , PM ) ;"
LLVM,ARC,460,"Predict the next statement of this code snippet:
 <s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM ) ;"
LLVM,ARC,461,"Predict the next statement of this code snippet:
 <s> TargetLoweringObjectFile * getObjFileLowering ( ) const override {"
LLVM,ARC,462,"Predict the next statement of this code snippet:
 <s> static Reloc :: Model getRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return * RM ;"
LLVM,ARC,463,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override {"
LLVM,ARC,464,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override {"
LLVM,ARC,465,"Predict the next statement of this code snippet:
 <s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;"
LLVM,ARC,466,"Predict the next statement of this code snippet:
 <s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;"
LLVM,ARC,467,"Predict the next statement of this code snippet:
 <s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;"
LLVM,ARC,468,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TTIImpl ( <ISA_LIT>TTIImpl && Arg ) : BaseT ( std :: move ( static_cast < BaseT & > ( Arg ) ) ) , ST ( std :: move ( Arg . ST ) ) , TLI ( std :: move ( Arg . TLI ) ) {"
LLVM,ARC,469,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TTIImpl ( <ISA_LIT>TTIImpl && Arg ) : BaseT ( std :: move ( static_cast < BaseT & > ( Arg ) ) ) , ST ( std :: move ( Arg . ST ) ) , TLI ( std :: move ( Arg . TLI ) ) {"
LLVM,ARC,470,"Predict the next statement of this code snippet:
 <s> return ST ;"
LLVM,ARC,471,"Predict the next statement of this code snippet:
 <s> return TLI ;"
LLVM,RISCV,0,"Predict the next statement of this code snippet:
 <s> static inline bool isImmHF ( uint64_t Val ) { return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;"
LLVM,RISCV,1,"Predict the next statement of this code snippet:
 <s> static inline bool isImmHF ( uint64_t Val ) { return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;"
LLVM,RISCV,2,"Predict the next statement of this code snippet:
 <s> return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;"
LLVM,RISCV,3,"Predict the next statement of this code snippet:
 <s> static inline bool isImmHL ( uint64_t Val ) {"
LLVM,RISCV,4,"Predict the next statement of this code snippet:
 <s> static inline bool isImmLF ( uint64_t Val ) { return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;"
LLVM,RISCV,5,"Predict the next statement of this code snippet:
 <s> static inline bool isImmLH ( uint64_t Val ) { return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;"
LLVM,RISCV,6,"Predict the next statement of this code snippet:
 <s> return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;"
LLVM,RISCV,7,"Predict the next statement of this code snippet:
 <s> return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;"
LLVM,RISCV,8,"Predict the next statement of this code snippet:
 <s> static inline bool isImmLL ( uint64_t Val ) { return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;"
LLVM,RISCV,9,"Predict the next statement of this code snippet:
 <s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override {"
LLVM,RISCV,10,"Predict the next statement of this code snippet:
 <s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>"
LLVM,RISCV,11,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,RISCV,12,"Predict the next statement of this code snippet:
 <s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ;"
LLVM,RISCV,13,"Predict the next statement of this code snippet:
 <s> bool requiresDiffExpressionRelocations ( ) const override {"
LLVM,RISCV,14,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmBackend ( const MCSubtargetInfo & STI , uint8_t OSABI , bool Is64Bit ) : MCAsmBackend ( <STR_LIT> ) , STI ( STI ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) {"
LLVM,RISCV,15,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmBackend ( const MCSubtargetInfo & STI , uint8_t OSABI , bool Is64Bit ) : MCAsmBackend ( <STR_LIT> ) , STI ( STI ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) {"
LLVM,RISCV,16,"Predict the next statement of this code snippet:
 <s> ForceRelocs = true ;"
LLVM,RISCV,17,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>AsmBackend ( ) override {"
LLVM,RISCV,18,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>AsmBackend ( ) override {"
LLVM,RISCV,19,"Predict the next statement of this code snippet:
 <s> return Value ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;"
LLVM,RISCV,20,"Predict the next statement of this code snippet:
 <s> case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : return Value ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : {"
LLVM,RISCV,21,"Predict the next statement of this code snippet:
 <s> MCContext & Ctx = Asm . getContext ( ) ; MCFixupKind Kind = Fixup . getKind ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; if ( ! Value ) return ;"
LLVM,RISCV,22,"Predict the next statement of this code snippet:
 <s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , Is64Bit ) ;"
LLVM,RISCV,23,"Predict the next statement of this code snippet:
 <s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>AsmBackend ( OSABI , TT . isArch64Bit ( ) ) ;"
LLVM,RISCV,24,"Predict the next statement of this code snippet:
 <s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override {"
LLVM,RISCV,25,"Predict the next statement of this code snippet:
 <s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>"
LLVM,RISCV,26,"Predict the next statement of this code snippet:
 <s> bool mayNeedRelaxation ( const MCInst & Inst ) const override {"
LLVM,RISCV,27,"Predict the next statement of this code snippet:
 <s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override {"
LLVM,RISCV,28,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmBackend ( uint8_t OSABI , bool Is64Bit ) : MCAsmBackend ( ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) {"
LLVM,RISCV,29,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmBackend ( uint8_t OSABI , bool Is64Bit ) : MCAsmBackend ( ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) {"
LLVM,RISCV,30,"Predict the next statement of this code snippet:
 <s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> write32 ( <NUM_LIT> ) ;"
LLVM,RISCV,31,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const {"
LLVM,RISCV,32,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : return Value ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ;"
LLVM,RISCV,33,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCContext & Ctx = Asm . getContext ( ) ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ;"
LLVM,RISCV,34,"Predict the next statement of this code snippet:
 <s> const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> }"
LLVM,RISCV,35,"Predict the next statement of this code snippet:
 <s> <STR_LIT> getTargetABI ( ) const { return TargetABI ;"
LLVM,RISCV,36,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { return getRelaxedOpcode ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ;"
LLVM,RISCV,37,"Predict the next statement of this code snippet:
 <s> return willForceRelocations ( ) ;"
LLVM,RISCV,38,"Predict the next statement of this code snippet:
 <s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { return STI . getFeatureBits ( ) [ <STR_LIT> ] ;"
LLVM,RISCV,39,"Predict the next statement of this code snippet:
 <s> return STI . getFeatureBits ( ) [ <STR_LIT> ] ;"
LLVM,RISCV,40,"Predict the next statement of this code snippet:
 <s> bool willForceRelocations ( ) const {"
LLVM,RISCV,41,"Predict the next statement of this code snippet:
 <s> bool willForceRelocations ( ) const {"
LLVM,RISCV,42,"Predict the next statement of this code snippet:
 <s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; static_assert ( ( array_lengthof ( Infos ) ) == <STR_LIT> , <STR_LIT> ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;"
LLVM,RISCV,43,"Predict the next statement of this code snippet:
 <s> const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; static_assert ( ( array_lengthof ( Infos ) ) == <STR_LIT> , <STR_LIT> ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;"
LLVM,RISCV,44,"Predict the next statement of this code snippet:
 <s> unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;"
LLVM,RISCV,45,"Predict the next statement of this code snippet:
 <s> assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; }"
LLVM,RISCV,46,"Predict the next statement of this code snippet:
 <s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;"
LLVM,RISCV,47,"Predict the next statement of this code snippet:
 <s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) {"
LLVM,RISCV,48,"Predict the next statement of this code snippet:
 <s> const MCFixup * AUIPCFixup ; const MCFragment * AUIPCDF ; MCValue AUIPCTarget ; switch ( Fixup . getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : AUIPCFixup = & Fixup ; AUIPCDF = DF ; AUIPCTarget = Target ; break ; case <STR_LIT> : case <STR_LIT> : { AUIPCFixup = cast < <ISA_LIT>MCExpr > ( Fixup . getValue ( ) ) -> getPCRelHiFixup ( & AUIPCDF ) ; if ( ! AUIPCFixup ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return true ; } const MCExpr * AUIPCExpr = AUIPCFixup -> getValue ( ) ; if ( ! AUIPCExpr -> evaluateAsRelocatable ( AUIPCTarget , & Layout , AUIPCFixup ) ) return true ; break ; } } if ( ! AUIPCTarget . getSymA ( ) || AUIPCTarget . getSymB ( ) ) return false ; const MCSymbolRefExpr * A = AUIPCTarget . getSymA ( ) ; const MCSymbol & SA = A -> getSymbol ( ) ; if ( A -> getKind ( ) != MCSymbolRefExpr :: VK_None || SA . isUndefined ( ) ) return false ; auto * Writer = Asm . getWriterPtr ( ) ; if ( ! Writer ) return false ; bool IsResolved = Writer -> isSymbolRefDifferenceFullyResolvedImpl ( Asm , SA , * AUIPCDF , false , true ) ; if ( ! IsResolved ) return false ; Value = Layout . getSymbolOffset ( SA ) + AUIPCTarget . getConstant ( ) ;"
LLVM,RISCV,49,"Predict the next statement of this code snippet:
 <s> if ( ! Resolved && ! WasForced ) return true ; int64_t Offset = int64_t ( Value ) ; switch ( Fixup . getTargetKind ( ) ) { default : return false ; case <STR_LIT> : return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ; case <STR_LIT> :"
LLVM,RISCV,50,"Predict the next statement of this code snippet:
 <s> if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_NONE ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_32 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_64 ) . Default ( - <NUM_LIT> ) ;"
LLVM,RISCV,51,"Predict the next statement of this code snippet:
 <s> const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> }"
LLVM,RISCV,52,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: relaxDwarfCFA ( MCDwarfCallFrameFragment & DF , MCAsmLayout & Layout , bool & WasRelaxed ) const { const MCExpr & AddrDelta = DF . getAddrDelta ( ) ; SmallVectorImpl < char > & Data = DF . getContents ( ) ; SmallVectorImpl < MCFixup > & Fixups = DF . getFixups ( ) ; size_t OldSize = Data . size ( ) ; int64_t Value ; bool IsAbsolute = AddrDelta . evaluateKnownAbsolute ( Value , Layout ) ; assert ( IsAbsolute && <STR_LIT> ) ; ( void ) IsAbsolute ; Data . clear ( ) ; Fixups . clear ( ) ; raw_svector_ostream OS ( Data ) ; assert ( Layout . getAssembler ( ) . getContext ( ) . getAsmInfo ( ) -> getMinInstAlignment ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Value == <NUM_LIT> ) { WasRelaxed = OldSize != Data . size ( ) ; return true ; } auto AddFixups = [ & Fixups , & AddrDelta ] ( unsigned Offset , std :: pair < unsigned , unsigned > Fixup ) { const MCBinaryExpr & MBE = cast < MCBinaryExpr > ( AddrDelta ) ; Fixups . push_back ( MCFixup :: create ( Offset , MBE . getLHS ( ) , static_cast < MCFixupKind > ( std :: get < <NUM_LIT> > ( Fixup ) ) ) ) ;"
LLVM,RISCV,53,"Predict the next statement of this code snippet:
 <s> assert ( IsAbsolute && <STR_LIT> ) ; ( void ) IsAbsolute ; Data . clear ( ) ; Fixups . clear ( ) ; raw_svector_ostream OS ( Data ) ; assert ( Layout . getAssembler ( ) . getContext ( ) . getAsmInfo ( ) -> getMinInstAlignment ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Value == <NUM_LIT> ) { WasRelaxed = OldSize != Data . size ( ) ; return true ; } auto AddFixups = [ & Fixups , & AddrDelta ] ( unsigned Offset , std :: pair < unsigned , unsigned > Fixup ) { const MCBinaryExpr & MBE = cast < MCBinaryExpr > ( AddrDelta ) ; Fixups . push_back ( MCFixup :: create ( Offset , MBE . getLHS ( ) , static_cast < MCFixupKind > ( std :: get < <NUM_LIT> > ( Fixup ) ) ) ) ; Fixups . push_back ( MCFixup :: create ( Offset , MBE . getRHS ( ) , static_cast < MCFixupKind > ( std :: get < <NUM_LIT> > ( Fixup ) ) ) ) ; } ; if ( isUIntN ( <NUM_LIT> , Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc ) ; AddFixups ( <NUM_LIT> , { <STR_LIT> , <STR_LIT> } ) ; } else if ( isUInt < <NUM_LIT> > ( Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc1 ) ; <STR_LIT> :: write < uint8_t > ( OS , <NUM_LIT> , <STR_LIT> ) ; AddFixups ( <NUM_LIT> , { <STR_LIT> , <STR_LIT> } ) ; } else if ( isUInt < <NUM_LIT> > ( Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc2 ) ; <STR_LIT> :: write < uint16_t > ( OS , <NUM_LIT> , <STR_LIT> ) ; AddFixups ( <NUM_LIT> , { <STR_LIT> , <STR_LIT> } ) ; } else if ( isUInt < <NUM_LIT> > ( Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc4 ) ; <STR_LIT> :: write < uint32_t > ( OS , <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,54,"Predict the next statement of this code snippet:
 <s> switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; }"
LLVM,RISCV,55,"Predict the next statement of this code snippet:
 <s> Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> :"
LLVM,RISCV,56,"Predict the next statement of this code snippet:
 <s> if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return true ; switch ( Fixup . getTargetKind ( ) ) { default : break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : if ( Target . isAbsolute ( ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return STI . getFeatureBits ( ) [ <STR_LIT> ] || ForceRelocs ;"
LLVM,RISCV,57,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( const MCAlignFragment & AF , unsigned & Size ) { if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) return false ; bool HasStdExtC = STI . getFeatureBits ( ) [ <STR_LIT> ] ;"
LLVM,RISCV,58,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: shouldInsertFixupForCodeAlign ( MCAssembler & Asm , const MCAsmLayout & Layout , MCAlignFragment & AF ) { if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) return false ; unsigned Count ; if ( ! shouldInsertExtraNopBytesForCodeAlign ( AF , Count ) || ( Count == <NUM_LIT> ) ) return false ; MCContext & Ctx = Asm . getContext ( ) ;"
LLVM,RISCV,59,"Predict the next statement of this code snippet:
 <s> MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; MCFixup Fixup = MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , SMLoc ( ) ) ;"
LLVM,RISCV,60,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { bool HasStdExtC = STI -> getFeatureBits ( ) [ <STR_LIT> ] ; unsigned MinNopLen = HasStdExtC ? <NUM_LIT> : <NUM_LIT> ; if ( ( Count % MinNopLen ) != <NUM_LIT> ) return false ; for ( ; Count >= <NUM_LIT> ; Count -= <NUM_LIT> ) OS . write ( <STR_LIT> , <NUM_LIT> ) ; if ( Count && HasStdExtC ) OS . write ( <STR_LIT> , <NUM_LIT> ) ; return true ;"
LLVM,RISCV,61,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { bool HasStdExtC = STI -> getFeatureBits ( ) [ <STR_LIT> ] ;"
LLVM,RISCV,62,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { bool HasStdExtC = STI . getFeatureBits ( ) [ <STR_LIT> ] ;"
LLVM,RISCV,63,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : { unsigned Bit8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;"
LLVM,RISCV,64,"Predict the next statement of this code snippet:
 <s> return Value ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ;"
LLVM,RISCV,65,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : const MCFixup * T = cast < <ISA_LIT>MCExpr > ( Fixup . getValue ( ) ) -> getPCRelHiFixup ( ) ; if ( ! T ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } switch ( ( unsigned ) T -> getKind ( ) ) { default :"
LLVM,RISCV,66,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( const MCAlignFragment & AF , unsigned & Size ) { if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) return false ; bool HasStdExtC = STI . getFeatureBits ( ) [ <STR_LIT> ] ; unsigned MinNopLen = HasStdExtC ? <NUM_LIT> : <NUM_LIT> ; Size = AF . getAlignment ( ) - MinNopLen ; return true ;"
LLVM,RISCV,67,"Predict the next statement of this code snippet:
 <s> unsigned MinNopLen = HasStdExtC ? <NUM_LIT> : <NUM_LIT> ; Size = AF . getAlignment ( ) - MinNopLen ;"
LLVM,RISCV,68,"Predict the next statement of this code snippet:
 <s> MCFixup Fixup = MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , SMLoc ( ) ) ; uint64_t FixedValue = <NUM_LIT> ; MCValue NopBytes = MCValue :: get ( Count ) ;"
LLVM,RISCV,69,"Predict the next statement of this code snippet:
 <s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override {"
LLVM,RISCV,70,"Predict the next statement of this code snippet:
 <s> return STI . getFeatureBits ( ) [ <STR_LIT> ] || ForceRelocs ;"
LLVM,RISCV,71,"Predict the next statement of this code snippet:
 <s> case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case FK_Data_6b : return Value ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;"
LLVM,RISCV,72,"Predict the next statement of this code snippet:
 <s> return false ; case <STR_LIT> : return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ;"
LLVM,RISCV,73,"Predict the next statement of this code snippet:
 <s> const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ;"
LLVM,RISCV,74,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return IsCapMode ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,75,"Predict the next statement of this code snippet:
 <s> Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( IsCapMode ? <STR_LIT> : <STR_LIT> ) ; Res . addOperand ( MCOperand :: createReg ( IsCapMode ? <STR_LIT> : <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ;"
LLVM,RISCV,76,"Predict the next statement of this code snippet:
 <s> if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return true ; switch ( Fixup . getTargetKind ( ) ) { default : break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : if ( Target . isAbsolute ( ) ) return false ; break ;"
LLVM,RISCV,77,"Predict the next statement of this code snippet:
 <s> Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : { unsigned Bit8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7_6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4_3 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;"
LLVM,RISCV,78,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ;"
LLVM,RISCV,79,"Predict the next statement of this code snippet:
 <s> default : break ; case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : const MCFixup * T = cast < <ISA_LIT>MCExpr > ( Fixup . getValue ( ) ) -> getPCRelHiFixup ( ) ; if ( ! T ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } switch ( ( unsigned ) T -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : ShouldForce = true ; break ; case <STR_LIT> : ShouldForce = T -> getValue ( ) -> findAssociatedFragment ( ) != Fixup . getValue ( ) -> findAssociatedFragment ( ) ; break ; } break ; }"
LLVM,RISCV,80,"Predict the next statement of this code snippet:
 <s> case FK_Data_8 : case FK_Data_6b : return Value ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> :"
LLVM,RISCV,81,"Predict the next statement of this code snippet:
 <s> default : break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : if ( Target . isAbsolute ( ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }"
LLVM,RISCV,82,"Predict the next statement of this code snippet:
 <s> MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( Info . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) {"
LLVM,RISCV,83,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCContext & Ctx = Asm . getContext ( ) ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ;"
LLVM,RISCV,84,"Predict the next statement of this code snippet:
 <s> std :: unique_ptr < MCObjectWriter > <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , Is64Bit ) ;"
LLVM,RISCV,85,"Predict the next statement of this code snippet:
 <s> if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;"
LLVM,RISCV,86,"Predict the next statement of this code snippet:
 <s> Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : { unsigned Bit8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7_6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4_3 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit2_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit8 << <NUM_LIT> ) | ( Bit4_3 << <NUM_LIT> ) | ( Bit7_6 << <NUM_LIT> ) | ( Bit2_1 << <NUM_LIT> ) | ( Bit5 << <NUM_LIT> ) ; return Value ; }"
LLVM,RISCV,87,"Predict the next statement of this code snippet:
 <s> assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != FullSize ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;"
LLVM,RISCV,88,"Predict the next statement of this code snippet:
 <s> assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != FullSize ; ++ i ) {"
LLVM,RISCV,89,"Predict the next statement of this code snippet:
 <s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;"
LLVM,RISCV,90,"Predict the next statement of this code snippet:
 <s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;"
LLVM,RISCV,91,"Predict the next statement of this code snippet:
 <s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;"
LLVM,RISCV,92,"Predict the next statement of this code snippet:
 <s> switch ( Kind ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ;"
LLVM,RISCV,93,"Predict the next statement of this code snippet:
 <s> case FK_Data_6b : return Value ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ;"
LLVM,RISCV,94,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case FK_Data_6b : return Value ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; }"
LLVM,RISCV,95,"Predict the next statement of this code snippet:
 <s> if ( Type != - <NUM_LIT> ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return None ;"
LLVM,RISCV,96,"Predict the next statement of this code snippet:
 <s> Optional < MCFixupKind > <ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const {"
LLVM,RISCV,97,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmBackend ( const MCSubtargetInfo & STI , uint8_t OSABI , bool Is64Bit , const MCTargetOptions & Options ) : MCAsmBackend ( <STR_LIT> ) , STI ( STI ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) , TargetOptions ( Options ) { <STR_LIT> ( STI . getTargetTriple ( ) , STI . getFeatureBits ( ) ) ;"
LLVM,RISCV,98,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmBackend ( const MCSubtargetInfo & STI , uint8_t OSABI , bool Is64Bit , const MCTargetOptions & Options ) : MCAsmBackend ( <STR_LIT> ) , STI ( STI ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) , TargetOptions ( Options ) { <STR_LIT> ( STI . getTargetTriple ( ) , STI . getFeatureBits ( ) ) ;"
LLVM,RISCV,99,"Predict the next statement of this code snippet:
 <s> const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; static_assert ( ( array_lengthof ( Infos ) ) == <STR_LIT> , <STR_LIT> ) ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;"
LLVM,RISCV,100,"Predict the next statement of this code snippet:
 <s> int64_t Offset = int64_t ( Value ) ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case <STR_LIT> : return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ; case <STR_LIT> :"
LLVM,RISCV,101,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmBackend ( const MCSubtargetInfo & STI , uint8_t OSABI , bool Is64Bit ) : MCAsmBackend ( ) , STI ( STI ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) {"
LLVM,RISCV,102,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmBackend ( const MCSubtargetInfo & STI , uint8_t OSABI , bool Is64Bit ) : MCAsmBackend ( ) , STI ( STI ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) {"
LLVM,RISCV,103,"Predict the next statement of this code snippet:
 <s> uint64_t Nop32Count = Count / <NUM_LIT> ; for ( uint64_t i = Nop32Count ; i != <NUM_LIT> ; -- i ) OW -> write32 ( <NUM_LIT> ) ; if ( HasStdExtC ) { uint64_t Nop16Count = ( Count - Nop32Count * <NUM_LIT> ) / <NUM_LIT> ;"
LLVM,RISCV,104,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const { return ;"
LLVM,RISCV,105,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( const MCAlignFragment & AF , unsigned & Size ) { const MCSubtargetInfo * STI = AF . getSubtargetInfo ( ) ; if ( ! STI -> getFeatureBits ( ) [ <STR_LIT> ] ) return false ; bool HasStdExtC = STI -> getFeatureBits ( ) [ <STR_LIT> ] ; unsigned MinNopLen = HasStdExtC ? <NUM_LIT> : <NUM_LIT> ; if ( AF . getAlignment ( ) <= MinNopLen ) { return false ;"
LLVM,RISCV,106,"Predict the next statement of this code snippet:
 <s> const MCSubtargetInfo * STI = AF . getSubtargetInfo ( ) ; if ( ! STI -> getFeatureBits ( ) [ <STR_LIT> ] ) return false ; unsigned Count ; if ( ! shouldInsertExtraNopBytesForCodeAlign ( AF , Count ) || ( Count == <NUM_LIT> ) ) return false ; MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; MCFixup Fixup = MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , SMLoc ( ) ) ; uint64_t FixedValue = <NUM_LIT> ; MCValue NopBytes = MCValue :: get ( Count ) ;"
LLVM,RISCV,107,"Predict the next statement of this code snippet:
 <s> MCFixup Fixup = MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , SMLoc ( ) ) ; uint64_t FixedValue = <NUM_LIT> ; MCValue NopBytes = MCValue :: get ( Count ) ; Asm . getWriter ( ) . recordRelocation ( Asm , Layout , & AF , Fixup , NopBytes , FixedValue ) ;"
LLVM,RISCV,108,"Predict the next statement of this code snippet:
 <s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; static_assert ( ( array_lengthof ( Infos ) ) == <STR_LIT> , <STR_LIT> ) ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;"
LLVM,RISCV,109,"Predict the next statement of this code snippet:
 <s> Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } switch ( T -> getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ShouldForce = true ; break ; case <STR_LIT> : ShouldForce = T -> getValue ( ) -> findAssociatedFragment ( ) != Fixup . getValue ( ) -> findAssociatedFragment ( ) ; break ;"
LLVM,RISCV,110,"Predict the next statement of this code snippet:
 <s> unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : {"
LLVM,RISCV,111,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const { return ;"
LLVM,RISCV,112,"Predict the next statement of this code snippet:
 <s> uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : { unsigned Bit8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7_6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4_3 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit2_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit8 << <NUM_LIT> ) | ( Bit4_3 << <NUM_LIT> ) | ( Bit7_6 << <NUM_LIT> ) | ( Bit2_1 << <NUM_LIT> ) | ( Bit5 << <NUM_LIT> ) ; return Value ;"
LLVM,RISCV,113,"Predict the next statement of this code snippet:
 <s> case FK_Data_8 : return Value ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;"
LLVM,RISCV,114,"Predict the next statement of this code snippet:
 <s> unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = alignTo ( Info . TargetSize + Info . TargetOffset , <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;"
LLVM,RISCV,115,"Predict the next statement of this code snippet:
 <s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const { return create<ISA_LIT>ELFObjectWriter ( OSABI , Is64Bit ) ;"
LLVM,RISCV,116,"Predict the next statement of this code snippet:
 <s> const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;"
LLVM,RISCV,117,"Predict the next statement of this code snippet:
 <s> const Triple & TT = STI . getTargetTriple ( ) ;"
LLVM,RISCV,118,"Predict the next statement of this code snippet:
 <s> if ( ! Resolved && ! WasForced ) return true ; int64_t Offset = int64_t ( Value ) ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case <STR_LIT> : return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ; case <STR_LIT> :"
LLVM,RISCV,119,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>AsmBackend :: getRelaxedOpcode ( unsigned Op ) const { switch ( Op ) { default : return Op ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,120,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>AsmBackend :: getRelaxedOpcode ( unsigned Op ) const { switch ( Op ) { default : return Op ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; }"
LLVM,RISCV,121,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return getRelaxedOpcode ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ;"
LLVM,RISCV,122,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ;"
LLVM,RISCV,123,"Predict the next statement of this code snippet:
 <s> bool ShouldForce = false ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : const MCFixup * T = cast < <ISA_LIT>MCExpr > ( Fixup . getValue ( ) ) -> getPCRelHiFixup ( ) ; if ( ! T ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } switch ( ( unsigned ) T -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : ShouldForce = T -> getValue ( ) -> findAssociatedFragment ( ) != Fixup . getValue ( ) -> findAssociatedFragment ( ) ;"
LLVM,RISCV,124,"Predict the next statement of this code snippet:
 <s> switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : const MCFixup * T = cast < <ISA_LIT>MCExpr > ( Fixup . getValue ( ) ) -> getPCRelHiFixup ( ) ; if ( ! T ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } switch ( ( unsigned ) T -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ;"
LLVM,RISCV,125,"Predict the next statement of this code snippet:
 <s> bool HasStdExtC = STI . getFeatureBits ( ) [ <STR_LIT> ] ; unsigned MinNopLen = HasStdExtC ? <NUM_LIT> : <NUM_LIT> ; if ( ( Count % MinNopLen ) != <NUM_LIT> ) return false ;"
LLVM,RISCV,126,"Predict the next statement of this code snippet:
 <s> if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;"
LLVM,RISCV,127,"Predict the next statement of this code snippet:
 <s> if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;"
LLVM,RISCV,128,"Predict the next statement of this code snippet:
 <s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,129,"Predict the next statement of this code snippet:
 <s> addExpr ( Inst , getImm ( ) ) ;"
LLVM,RISCV,130,"Predict the next statement of this code snippet:
 <s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,131,"Predict the next statement of this code snippet:
 <s> auto Op = make_unique < <ISA_LIT>Operand > ( KindImm , StartLoc , EndLoc ) ;"
LLVM,RISCV,132,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createImm ( const MCExpr * Expr , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = make_unique < <ISA_LIT>Operand > ( KindImm , StartLoc , EndLoc ) ; Op -> Imm = Expr ;"
LLVM,RISCV,133,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createMem ( RegisterKind RegKind , unsigned Base , const MCExpr * Disp , unsigned Index , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = make_unique < <ISA_LIT>Operand > ( KindMem , StartLoc , EndLoc ) ; Op -> Mem . RegKind = RegKind ; Op -> Mem . Base = Base ; Op -> Mem . Index = Index ; Op -> Mem . Disp = Disp ; return Op ;"
LLVM,RISCV,134,"Predict the next statement of this code snippet:
 <s> Op -> Mem . RegKind = RegKind ; Op -> Mem . Base = Base ; Op -> Mem . Index = Index ;"
LLVM,RISCV,135,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( RegisterKind Kind , unsigned Num , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = make_unique < <ISA_LIT>Operand > ( KindReg , StartLoc , EndLoc ) ; Op -> Reg . Kind = Kind ; Op -> Reg . Num = Num ;"
LLVM,RISCV,136,"Predict the next statement of this code snippet:
 <s> auto Op = make_unique < <ISA_LIT>Operand > ( KindToken , Loc , Loc ) ; Op -> Token . Data = Str . data ( ) ;"
LLVM,RISCV,137,"Predict the next statement of this code snippet:
 <s> const MCExpr * getImm ( ) const { assert ( Kind == KindImm && <STR_LIT> ) ; return Imm ;"
LLVM,RISCV,138,"Predict the next statement of this code snippet:
 <s> unsigned getReg ( ) const override { assert ( Kind == KindReg && <STR_LIT> ) ;"
LLVM,RISCV,139,"Predict the next statement of this code snippet:
 <s> return StringRef ( Token . Data , Token . Length ) ;"
LLVM,RISCV,140,"Predict the next statement of this code snippet:
 <s> return StringRef ( Token . Data , Token . Length ) ;"
LLVM,RISCV,141,"Predict the next statement of this code snippet:
 <s> int64_t Value = CE -> getValue ( ) ; return Value >= MinValue && Value <= MaxValue ;"
LLVM,RISCV,142,"Predict the next statement of this code snippet:
 <s> return isReg ( ER64Reg ) ;"
LLVM,RISCV,143,"Predict the next statement of this code snippet:
 <s> bool isFP128 ( ) const { return isReg ( FP128Reg ) ;"
LLVM,RISCV,144,"Predict the next statement of this code snippet:
 <s> bool isFP32 ( ) const { return isReg ( FP32Reg ) ;"
LLVM,RISCV,145,"Predict the next statement of this code snippet:
 <s> return isReg ( FP32Reg ) ;"
LLVM,RISCV,146,"Predict the next statement of this code snippet:
 <s> return isReg ( FP64Reg ) ;"
LLVM,RISCV,147,"Predict the next statement of this code snippet:
 <s> return isReg ( GR64Reg ) ;"
LLVM,RISCV,148,"Predict the next statement of this code snippet:
 <s> bool isMem ( RegisterKind RegKind , bool HasIndex ) const { return ( Kind == KindMem && Mem . RegKind == RegKind && ( HasIndex || ! Mem . Index ) ) ;"
LLVM,RISCV,149,"Predict the next statement of this code snippet:
 <s> bool isMemDisp20 ( RegisterKind RegKind , bool HasIndex ) const { return isMem ( RegKind , HasIndex ) && inRange ( Mem . Disp , - <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,150,"Predict the next statement of this code snippet:
 <s> return isReg ( PairFP128Reg ) ;"
LLVM,RISCV,151,"Predict the next statement of this code snippet:
 <s> bool isPairFP128 ( ) const {"
LLVM,RISCV,152,"Predict the next statement of this code snippet:
 <s> bool isPairFP64 ( ) const {"
LLVM,RISCV,153,"Predict the next statement of this code snippet:
 <s> bool isPCR64Reg ( ) const { return isReg ( PCR64Reg ) ;"
LLVM,RISCV,154,"Predict the next statement of this code snippet:
 <s> bool isPCR64Reg ( ) const { return isReg ( PCR64Reg ) ;"
LLVM,RISCV,155,"Predict the next statement of this code snippet:
 <s> return isReg ( PCReg ) ;"
LLVM,RISCV,156,"Predict the next statement of this code snippet:
 <s> return isReg ( PCRReg ) ;"
LLVM,RISCV,157,"Predict the next statement of this code snippet:
 <s> return Kind == KindReg && Reg . Kind == RegKind ;"
LLVM,RISCV,158,"Predict the next statement of this code snippet:
 <s> return isImm ( - <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,159,"Predict the next statement of this code snippet:
 <s> return isImm ( - <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,160,"Predict the next statement of this code snippet:
 <s> bool isToken ( ) const override {"
LLVM,RISCV,161,"Predict the next statement of this code snippet:
 <s> return Kind == KindToken ;"
LLVM,RISCV,162,"Predict the next statement of this code snippet:
 <s> return isImm ( <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,163,"Predict the next statement of this code snippet:
 <s> return isImm ( <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,164,"Predict the next statement of this code snippet:
 <s> bool isU32Imm ( ) const {"
LLVM,RISCV,165,"Predict the next statement of this code snippet:
 <s> return isImm ( <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,166,"Predict the next statement of this code snippet:
 <s> bool isU4Imm ( ) const {"
LLVM,RISCV,167,"Predict the next statement of this code snippet:
 <s> bool isU64Imm ( ) const { return isImm ( <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,168,"Predict the next statement of this code snippet:
 <s> return isImm ( <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,169,"Predict the next statement of this code snippet:
 <s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( The<ISA_LIT>64Target ) ;"
LLVM,RISCV,170,"Predict the next statement of this code snippet:
 <s> Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail :"
LLVM,RISCV,171,"Predict the next statement of this code snippet:
 <s> Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ;"
LLVM,RISCV,172,"Predict the next statement of this code snippet:
 <s> SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * Disp ; if ( getParser ( ) . parseExpression ( Disp ) ) return MatchOperand_NoMatch ; unsigned Index = <NUM_LIT> ; unsigned Base = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Parser . Lex ( ) ; Register Reg ; OperandMatchResultTy Result = parseRegister ( Reg , 'x' , GR32Regs , true ) ; if ( Result != MatchOperand_Success ) return Result ; if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ! HasIndex ) { Error ( Reg . StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Index = Reg . Number ; Result = parseRegister ( Reg , 'x' , GR32Regs , true ) ; if ( Result != MatchOperand_Success ) return Result ;"
LLVM,RISCV,173,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ;"
LLVM,RISCV,174,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy parseFP32 ( OperandVector & Operands ) { return parseRegister ( Operands , 'f' , FP32Regs , <ISA_LIT>Operand :: FP32Reg ) ;"
LLVM,RISCV,175,"Predict the next statement of this code snippet:
 <s> return parseRegister ( Operands , 'f' , FP64Regs , <ISA_LIT>Operand :: FP64Reg ) ;"
LLVM,RISCV,176,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy parseFP64 ( OperandVector & Operands ) { return parseRegister ( Operands , 'f' , FP64Regs , <ISA_LIT>Operand :: FP64Reg ) ;"
LLVM,RISCV,177,"Predict the next statement of this code snippet:
 <s> return parseRegister ( Operands , 'x' , GR32Regs , <ISA_LIT>Operand :: GR32Reg ) ;"
LLVM,RISCV,178,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy parseGR32 ( OperandVector & Operands ) { return parseRegister ( Operands , 'x' , GR32Regs , <ISA_LIT>Operand :: GR32Reg ) ;"
LLVM,RISCV,179,"Predict the next statement of this code snippet:
 <s> SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;"
LLVM,RISCV,180,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy == MatchOperand_Success ) return false ; if ( ResTy == MatchOperand_ParseFail ) return true ; const MCExpr * Expr ;"
LLVM,RISCV,181,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy parsePairFP128 ( OperandVector & Operands ) { return parseRegister ( Operands , 'f' , PairFP128Regs , <ISA_LIT>Operand :: PairFP128Reg ) ;"
LLVM,RISCV,182,"Predict the next statement of this code snippet:
 <s> Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ;"
LLVM,RISCV,183,"Predict the next statement of this code snippet:
 <s> else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ;"
LLVM,RISCV,184,"Predict the next statement of this code snippet:
 <s> else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else return MatchOperand_ParseFail ; Operands . push_back ( std :: move ( op ) ) ; Parser . Lex ( ) ; return MatchOperand_Success ; } else { return MatchOperand_ParseFail ; } } else { return MatchOperand_ParseFail ; } } else { return MatchOperand_NoMatch ; } return parseRegister ( Operands , 'p' , PCRRegs , <ISA_LIT>Operand :: PCRReg ) ;"
LLVM,RISCV,185,"Predict the next statement of this code snippet:
 <s> if ( parseRegister ( Reg ) ) return Error ( Reg . StartLoc , <STR_LIT> ) ; if ( Reg . Prefix == 'x' && Reg . Number < <NUM_LIT> ) RegNo = GR32Regs [ Reg . Number ] ; else if ( Reg . Prefix == 'f' && Reg . Number < <NUM_LIT> ) RegNo = FP32Regs [ Reg . Number ] ; else if ( Reg . Prefix == 'e' && Reg . Number <= <NUM_LIT> ) RegNo = ER64Regs [ Reg . Number ] ; else return Error ( Reg . StartLoc , <STR_LIT> ) ; StartLoc = Reg . StartLoc ;"
LLVM,RISCV,186,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>Operand :: print ( raw_ostream & OS ) const { llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,187,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , STI ( sti ) , Parser ( parser ) {"
LLVM,RISCV,188,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , STI ( sti ) , Parser ( parser ) { MCAsmParserExtension :: Initialize ( Parser ) ;"
LLVM,RISCV,189,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Operand ( OperandKind kind , SMLoc startLoc , SMLoc endLoc ) : Kind ( kind ) , StartLoc ( startLoc ) , EndLoc ( endLoc ) {"
LLVM,RISCV,190,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Operand ( OperandKind kind , SMLoc startLoc , SMLoc endLoc ) : Kind ( kind ) , StartLoc ( startLoc ) , EndLoc ( endLoc ) {"
LLVM,RISCV,191,"Predict the next statement of this code snippet:
 <s> void addCSRSystemRegisterOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SysReg . Encoding ) ) ;"
LLVM,RISCV,192,"Predict the next statement of this code snippet:
 <s> int64_t Imm = <NUM_LIT> ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,193,"Predict the next statement of this code snippet:
 <s> bool IsConstant = evaluateConstantImm ( Expr , Imm , VK ) ; if ( IsConstant ) Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;"
LLVM,RISCV,194,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( evaluateConstantImm ( getImm ( ) , Constant , VK ) ) { if ( Constant == <NUM_LIT> ) { Inst . addOperand ( MCOperand :: createImm ( Constant ) ) ; return ; } llvm_unreachable ( <STR_LIT> ) ; } auto SE = cast < MCSymbolRefExpr > ( getImm ( ) ) ; unsigned Imm = <NUM_LIT> ; for ( char c : SE -> getSymbol ( ) . getName ( ) ) { switch ( c ) { default : llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ;"
LLVM,RISCV,195,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( getRoundingMode ( ) ) ) ;"
LLVM,RISCV,196,"Predict the next statement of this code snippet:
 <s> void addImmOperands ( MCInst & Inst , unsigned N ) const {"
LLVM,RISCV,197,"Predict the next statement of this code snippet:
 <s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;"
LLVM,RISCV,198,"Predict the next statement of this code snippet:
 <s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,199,"Predict the next statement of this code snippet:
 <s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,200,"Predict the next statement of this code snippet:
 <s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Imm = <NUM_LIT> ; if ( Kind == KindTy :: Immediate ) { <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; ( void ) IsConstantImm ;"
LLVM,RISCV,201,"Predict the next statement of this code snippet:
 <s> SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,202,"Predict the next statement of this code snippet:
 <s> Expr = RE -> getSubExpr ( ) ; } MCValue Res ; MCFixup Fixup ; if ( Expr -> evaluateAsRelocatable ( Res , nullptr , & Fixup ) ) return Res . getRefKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; return false ;"
LLVM,RISCV,203,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: classifySymbolRef ( const MCExpr * Expr , <ISA_LIT>MCExpr :: VariantKind & Kind ) { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,204,"Predict the next statement of this code snippet:
 <s> if ( getSTI ( ) . getFeatureBits ( ) [ Feature ] ) {"
LLVM,RISCV,205,"Predict the next statement of this code snippet:
 <s> assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ; return Reg - <STR_LIT> + <STR_LIT> ;"
LLVM,RISCV,206,"Predict the next statement of this code snippet:
 <s> assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ; return Reg - <STR_LIT> + <STR_LIT> ;"
LLVM,RISCV,207,"Predict the next statement of this code snippet:
 <s> else if ( Kind == MCK_VRM8 ) RegClassID = <STR_LIT> ; else return <NUM_LIT> ; return RI . getMatchingSuperReg ( Reg , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ RegClassID ] ) ;"
LLVM,RISCV,208,"Predict the next statement of this code snippet:
 <s> Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> IsRV64 = IsRV64 ; return Op ;"
LLVM,RISCV,209,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned RegNo , SMLoc S , SMLoc E , bool IsRV64 , bool IsGPRAsFPR = false ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: Register ) ;"
LLVM,RISCV,210,"Predict the next statement of this code snippet:
 <s> Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . Encoding = Encoding ;"
LLVM,RISCV,211,"Predict the next statement of this code snippet:
 <s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: Token ) ; Op -> Tok = Str ;"
LLVM,RISCV,212,"Predict the next statement of this code snippet:
 <s> Op -> VType . Val = VTypeI ; Op -> StartLoc = S ;"
LLVM,RISCV,213,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createVType ( unsigned VTypeI , SMLoc S , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: VType ) ; Op -> VType . Val = VTypeI ;"
LLVM,RISCV,214,"Predict the next statement of this code snippet:
 <s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: defaultMaskRegOp ( ) const { return <ISA_LIT>Operand :: createReg ( <STR_LIT> , llvm :: SMLoc ( ) , llvm :: SMLoc ( ) , isRV64 ( ) ) ;"
LLVM,RISCV,215,"Predict the next statement of this code snippet:
 <s> MCSymbol * TmpLabel = Ctx . createNamedTempSymbol ( <STR_LIT> ) ; Out . emitLabel ( TmpLabel ) ; const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ;"
LLVM,RISCV,216,"Predict the next statement of this code snippet:
 <s> MCSymbol * TmpLabel = Ctx . createNamedTempSymbol ( <STR_LIT> ) ; Out . emitLabel ( TmpLabel ) ; const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ;"
LLVM,RISCV,217,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmParser :: emitLoadAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; unsigned SecondOpcode ; <ISA_LIT>MCExpr :: VariantKind VKHi ; if ( ParserOptions . IsPicEnabled ) { SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,218,"Predict the next statement of this code snippet:
 <s> switch ( Inst . getOpndKind ( ) ) { case <STR_LIT> : emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; break ; case <STR_LIT> : emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ) ; break ;"
LLVM,RISCV,219,"Predict the next statement of this code snippet:
 <s> MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,220,"Predict the next statement of this code snippet:
 <s> const MCExpr * Symbol = Inst . getOperand ( SymbolOpIdx ) . getExpr ( ) ; emitAuipcInstPair ( DestReg , TmpReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI , Opcode , IDLoc , Out ) ;"
LLVM,RISCV,221,"Predict the next statement of this code snippet:
 <s> const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ;"
LLVM,RISCV,222,"Predict the next statement of this code snippet:
 <s> emitAuipcInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI , <STR_LIT> , IDLoc , Out ) ;"
LLVM,RISCV,223,"Predict the next statement of this code snippet:
 <s> MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; unsigned SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,224,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmParser :: emitPseudoExtend ( MCInst & Inst , bool SignExtend , int64_t Width , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; MCOperand SourceReg = Inst . getOperand ( <NUM_LIT> ) ; unsigned SecondOpcode = SignExtend ? <STR_LIT> : <STR_LIT> ; int64_t ShAmt = ( isRV64 ( ) ? <NUM_LIT> : <NUM_LIT> ) - Width ; assert ( ShAmt > <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,225,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmParser :: emitPseudoExtend ( MCInst & Inst , bool SignExtend , int64_t Width , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; MCOperand SourceReg = Inst . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,226,"Predict the next statement of this code snippet:
 <s> MCInst CInst ; bool Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ;"
LLVM,RISCV,227,"Predict the next statement of this code snippet:
 <s> } else if ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,228,"Predict the next statement of this code snippet:
 <s> return RE -> evaluateAsConstant ( Imm ) ; } if ( auto CE = dyn_cast < MCConstantExpr > ( Expr ) ) {"
LLVM,RISCV,229,"Predict the next statement of this code snippet:
 <s> return Error ( ErrorLoc , Msg + <STR_LIT> + Twine ( Lower ) + <STR_LIT> + Twine ( Upper ) + <STR_LIT> ) ;"
LLVM,RISCV,230,"Predict the next statement of this code snippet:
 <s> SMLoc getEndLoc ( ) const override { return EndLoc ;"
LLVM,RISCV,231,"Predict the next statement of this code snippet:
 <s> return EndLoc ;"
LLVM,RISCV,232,"Predict the next statement of this code snippet:
 <s> bool getFeatureBits ( uint64_t Feature ) {"
LLVM,RISCV,233,"Predict the next statement of this code snippet:
 <s> return getSTI ( ) . getFeatureBits ( ) [ Feature ] ;"
LLVM,RISCV,234,"Predict the next statement of this code snippet:
 <s> assert ( Kind == KindTy :: Immediate && <STR_LIT> ) ; return Imm . Val ;"
LLVM,RISCV,235,"Predict the next statement of this code snippet:
 <s> SMLoc getLoc ( ) const {"
LLVM,RISCV,236,"Predict the next statement of this code snippet:
 <s> SMLoc getLoc ( ) const {"
LLVM,RISCV,237,"Predict the next statement of this code snippet:
 <s> assert ( Kind == KindTy :: Register && <STR_LIT> ) ;"
LLVM,RISCV,238,"Predict the next statement of this code snippet:
 <s> <STR_LIT> FRM = <STR_LIT> ( SE -> getSymbol ( ) . getName ( ) ) ;"
LLVM,RISCV,239,"Predict the next statement of this code snippet:
 <s> <STR_LIT> FRM = <STR_LIT> ( SE -> getSymbol ( ) . getName ( ) ) ;"
LLVM,RISCV,240,"Predict the next statement of this code snippet:
 <s> SMLoc getStartLoc ( ) const override {"
LLVM,RISCV,241,"Predict the next statement of this code snippet:
 <s> SMLoc getStartLoc ( ) const override { return StartLoc ;"
LLVM,RISCV,242,"Predict the next statement of this code snippet:
 <s> StringRef getSysReg ( ) const { assert ( Kind == KindTy :: SystemRegister && <STR_LIT> ) ;"
LLVM,RISCV,243,"Predict the next statement of this code snippet:
 <s> StringRef getSysReg ( ) const { assert ( Kind == KindTy :: SystemRegister && <STR_LIT> ) ; return StringRef ( SysReg . Data , SysReg . Length ) ;"
LLVM,RISCV,244,"Predict the next statement of this code snippet:
 <s> assert ( Kind == KindTy :: Token && <STR_LIT> ) ; return Tok ;"
LLVM,RISCV,245,"Predict the next statement of this code snippet:
 <s> unsigned getVType ( ) const {"
LLVM,RISCV,246,"Predict the next statement of this code snippet:
 <s> unsigned getVType ( ) const { assert ( Kind == KindTy :: VType && <STR_LIT> ) ;"
LLVM,RISCV,247,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,248,"Predict the next statement of this code snippet:
 <s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) ;"
LLVM,RISCV,249,"Predict the next statement of this code snippet:
 <s> bool isBareSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,250,"Predict the next statement of this code snippet:
 <s> bool isBareSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,251,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,252,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ;"
LLVM,RISCV,253,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,254,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,255,"Predict the next statement of this code snippet:
 <s> bool isCSRSystemRegister ( ) const {"
LLVM,RISCV,256,"Predict the next statement of this code snippet:
 <s> char Prev = '\0' ; for ( char c : Str ) { if ( c != 'i' && c != 'o' && c != 'r' && c != 'w' ) return false ; if ( c <= Prev ) return false ;"
LLVM,RISCV,257,"Predict the next statement of this code snippet:
 <s> auto * SVal = dyn_cast < MCSymbolRefExpr > ( getImm ( ) ) ; if ( ! SVal || SVal -> getKind ( ) != MCSymbolRefExpr :: VK_None ) return false ; StringRef Str = SVal -> getSymbol ( ) . getName ( ) ; char Prev = '\0' ; for ( char c : Str ) { if ( c != 'i' && c != 'o' && c != 'r' && c != 'w' ) return false ;"
LLVM,RISCV,258,"Predict the next statement of this code snippet:
 <s> auto * SVal = dyn_cast < MCSymbolRefExpr > ( Val ) ; if ( ! SVal || SVal -> getKind ( ) != MCSymbolRefExpr :: VK_None ) return false ; StringRef Str = SVal -> getSymbol ( ) . getName ( ) ;"
LLVM,RISCV,259,"Predict the next statement of this code snippet:
 <s> const MCExpr * Val = getImm ( ) ; auto * SVal = dyn_cast < MCSymbolRefExpr > ( Val ) ;"
LLVM,RISCV,260,"Predict the next statement of this code snippet:
 <s> return isGPR ( ) && IsGPRAsFPR ;"
LLVM,RISCV,261,"Predict the next statement of this code snippet:
 <s> bool isGPRAsFPR ( ) const { return isGPR ( ) && IsGPRAsFPR ;"
LLVM,RISCV,262,"Predict the next statement of this code snippet:
 <s> return isGPR ( ) && IsGPRAsFPR && IsRV64 ;"
LLVM,RISCV,263,"Predict the next statement of this code snippet:
 <s> bool isGPRF64AsFPR ( ) const { return isGPR ( ) && IsGPRAsFPR && IsRV64 ;"
LLVM,RISCV,264,"Predict the next statement of this code snippet:
 <s> bool isGPRPF64AsFPR ( ) const {"
LLVM,RISCV,265,"Predict the next statement of this code snippet:
 <s> return isGPR ( ) && IsGPRAsFPR && ! IsRV64 && ! ( ( Reg . RegNum - <STR_LIT> ) & <NUM_LIT> ) ;"
LLVM,RISCV,266,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ;"
LLVM,RISCV,267,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) return true ;"
LLVM,RISCV,268,"Predict the next statement of this code snippet:
 <s> bool isImmZero ( ) const { if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,269,"Predict the next statement of this code snippet:
 <s> bool isMem ( ) const override { return false ;"
LLVM,RISCV,270,"Predict the next statement of this code snippet:
 <s> return false ;"
LLVM,RISCV,271,"Predict the next statement of this code snippet:
 <s> bool isPseudoJumpSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ;"
LLVM,RISCV,272,"Predict the next statement of this code snippet:
 <s> bool isPseudoJumpSymbol ( ) const { int64_t Imm ;"
LLVM,RISCV,273,"Predict the next statement of this code snippet:
 <s> bool isRnumArg ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && Imm >= INT64_C ( <NUM_LIT> ) && Imm <= INT64_C ( <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,274,"Predict the next statement of this code snippet:
 <s> return getSTI ( ) . hasFeature ( <STR_LIT> ) ;"
LLVM,RISCV,275,"Predict the next statement of this code snippet:
 <s> return getSTI ( ) . hasFeature ( <STR_LIT> ) ;"
LLVM,RISCV,276,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && ( Imm != <NUM_LIT> ) && isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,277,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,278,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,279,"Predict the next statement of this code snippet:
 <s> bool isSImm12Lsb0 ( ) const { return isBareSimmNLsb0 < <NUM_LIT> > ( ) ;"
LLVM,RISCV,280,"Predict the next statement of this code snippet:
 <s> return isBareSimmNLsb0 < <NUM_LIT> > ( ) ;"
LLVM,RISCV,281,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,282,"Predict the next statement of this code snippet:
 <s> bool isSImm5 ( ) const { if ( ! isImm ( ) ) return false ;"
LLVM,RISCV,283,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,284,"Predict the next statement of this code snippet:
 <s> bool isSImm5Plus1 ( ) const { if ( ! isImm ( ) ) return false ;"
LLVM,RISCV,285,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,286,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,287,"Predict the next statement of this code snippet:
 <s> return isBareSimmNLsb0 < <NUM_LIT> > ( ) ;"
LLVM,RISCV,288,"Predict the next statement of this code snippet:
 <s> bool isSystemRegister ( ) const { return Kind == KindTy :: SystemRegister ;"
LLVM,RISCV,289,"Predict the next statement of this code snippet:
 <s> bool isSystemRegister ( ) const {"
LLVM,RISCV,290,"Predict the next statement of this code snippet:
 <s> bool isToken ( ) const override { return Kind == KindTy :: Token ;"
LLVM,RISCV,291,"Predict the next statement of this code snippet:
 <s> return Kind == KindTy :: Token ;"
LLVM,RISCV,292,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ;"
LLVM,RISCV,293,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,294,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,295,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,296,"Predict the next statement of this code snippet:
 <s> return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI ) ;"
LLVM,RISCV,297,"Predict the next statement of this code snippet:
 <s> return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI ) ; } else { return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI ) ; }"
LLVM,RISCV,298,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) ;"
LLVM,RISCV,299,"Predict the next statement of this code snippet:
 <s> bool isUImm3 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,300,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,301,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ;"
LLVM,RISCV,302,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,303,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,304,"Predict the next statement of this code snippet:
 <s> bool isUImm8Lsb00 ( ) const { if ( ! isImm ( ) ) return false ; int64_t Imm ;"
LLVM,RISCV,305,"Predict the next statement of this code snippet:
 <s> bool isUImm8Lsb00 ( ) const { if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,306,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,307,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,308,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,309,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; int64_t Imm ;"
LLVM,RISCV,310,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,311,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ;"
LLVM,RISCV,312,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,313,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ;"
LLVM,RISCV,314,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; if ( Imm == <NUM_LIT> ) return false ; return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,315,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; if ( Imm == <NUM_LIT> ) return false ; return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,316,"Predict the next statement of this code snippet:
 <s> return Kind == KindTy :: Register && Reg . RegNum == <STR_LIT> ;"
LLVM,RISCV,317,"Predict the next statement of this code snippet:
 <s> bool isV0Reg ( ) const {"
LLVM,RISCV,318,"Predict the next statement of this code snippet:
 <s> bool isVTypeI10 ( ) const {"
LLVM,RISCV,319,"Predict the next statement of this code snippet:
 <s> if ( Kind == KindTy :: Immediate ) return isVTypeImm ( <NUM_LIT> ) ;"
LLVM,RISCV,320,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,321,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ;"
LLVM,RISCV,322,"Predict the next statement of this code snippet:
 <s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>32Target ( ) ) ;"
LLVM,RISCV,323,"Predict the next statement of this code snippet:
 <s> RegNo = MatchRegisterName ( Name ) ; assert ( ! ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) ) ; assert ( ! ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) ) ; static_assert ( <STR_LIT> < <STR_LIT> , <STR_LIT> ) ; static_assert ( <STR_LIT> < <STR_LIT> , <STR_LIT> ) ; if ( RegNo == <STR_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; if ( IsRV32E && RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) RegNo = <STR_LIT> ;"
LLVM,RISCV,324,"Predict the next statement of this code snippet:
 <s> SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) + Identifier . size ( ) ) ; if ( Identifier . consume_back ( <STR_LIT> ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) { getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; }"
LLVM,RISCV,325,"Predict the next statement of this code snippet:
 <s> if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; if ( getLexer ( ) . peekTok ( ) . getKind ( ) != AsmToken :: EndOfStatement ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) + Identifier . size ( ) ) ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ;"
LLVM,RISCV,326,"Predict the next statement of this code snippet:
 <s> if ( CE ) { int64_t Imm = CE -> getValue ( ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { auto SysReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( SysReg ? SysReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SysReg = <STR_LIT> ( Identifier ) ; if ( ! SysReg ) SysReg = <STR_LIT> ( Identifier ) ; if ( ! SysReg ) if ( ( SysReg = <STR_LIT> ( Identifier ) ) ) Warning ( S , <STR_LIT> + Identifier + <STR_LIT> + SysReg -> Name + <STR_LIT> ) ; if ( SysReg ) { if ( ! SysReg -> haveRequiredFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( Identifier , S , SysReg -> Encoding , isRV64 ( ) ) ) ; return MatchOperand_Success ; } Twine Msg = <STR_LIT> <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ;"
LLVM,RISCV,327,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseCSRSystemRegister ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; const MCExpr * Res ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Exclaim : case AsmToken :: Tilde : case AsmToken :: Integer : case AsmToken :: String : { if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; auto * CE = dyn_cast < MCConstantExpr > ( Res ) ; if ( CE ) { int64_t Imm = CE -> getValue ( ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { auto SysReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( SysReg ? SysReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SysReg = <STR_LIT> ( Identifier ) ; if ( ! SysReg ) SysReg = <STR_LIT> ( Identifier ) ; if ( ! SysReg ) if ( ( SysReg = <STR_LIT> ( Identifier ) ) ) Warning ( S , <STR_LIT> + Identifier + <STR_LIT> + SysReg -> Name + <STR_LIT> ) ; if ( SysReg ) { if ( ! SysReg -> haveRequiredFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( Identifier , S , SysReg -> Encoding , isRV64 ( ) ) ) ; return MatchOperand_Success ; } Twine Msg = <STR_LIT> <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Percent : { Twine Msg = <STR_LIT> ;"
LLVM,RISCV,328,"Predict the next statement of this code snippet:
 <s> StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveOption ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveAttribute ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveInsn ( DirectiveID . getLoc ( ) ) ;"
LLVM,RISCV,329,"Predict the next statement of this code snippet:
 <s> bool IsIntegerValue = true ; if ( Tag % <NUM_LIT> ) IsIntegerValue = false ; SMLoc ValueExprLoc = Parser . getTok ( ) . getLoc ( ) ; if ( IsIntegerValue ) { const MCExpr * ValueExpr ; if ( Parser . parseExpression ( ValueExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ValueExpr ) ; if ( ! CE ) return Error ( ValueExprLoc , <STR_LIT> ) ; IntegerValue = CE -> getValue ( ) ; } else { if ( Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; StringValue = Parser . getTok ( ) . getStringContents ( ) ; Parser . Lex ( ) ; } if ( Parser . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( IsIntegerValue ) getTargetStreamer ( ) . emitAttribute ( Tag , IntegerValue ) ; else if ( Tag != <STR_LIT> ) getTargetStreamer ( ) . emitTextAttribute ( Tag , StringValue ) ; else { StringRef Arch = StringValue ; for ( auto Feature : <ISA_LIT>FeatureKV ) if ( llvm :: <STR_LIT> ( Feature . Key ) ) clearFeatureBits ( Feature . Value , Feature . Key ) ; auto ParseResult = llvm :: <STR_LIT> ( StringValue , true , true ) ; if ( ! ParseResult ) { std :: string Buffer ; raw_string_ostream OutputErrMsg ( Buffer ) ; handleAllErrors ( ParseResult . takeError ( ) , [ & ] ( llvm :: StringError & ErrMsg ) { OutputErrMsg << <STR_LIT> << Arch << <STR_LIT> << ErrMsg . getMessage ( ) ;"
LLVM,RISCV,330,"Predict the next statement of this code snippet:
 <s> SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Operands ; if ( ParseInstruction ( Info , FormatName , L , Operands ) ) return true ; unsigned Opcode ; uint64_t ErrorInfo ; return MatchAndEmitInstruction ( L , Opcode , Operands , Parser . getStreamer ( ) , ErrorInfo , false ) ;"
LLVM,RISCV,331,"Predict the next statement of this code snippet:
 <s> AsmToken Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; StringRef Option = Tok . getIdentifier ( ) ; if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPush ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; pushFeatureBits ( ) ; return false ; } if ( Option == <STR_LIT> ) { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; getTargetStreamer ( ) . emitDirectiveOptionPop ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; if ( popFeatureBits ( ) ) return Error ( StartLoc , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionRVC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRVC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = true ; return false ;"
LLVM,RISCV,332,"Predict the next statement of this code snippet:
 <s> switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ;"
LLVM,RISCV,333,"Predict the next statement of this code snippet:
 <s> case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Exclaim : case AsmToken :: Tilde : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res , E ) ) return MatchOperand_ParseFail ; break ;"
LLVM,RISCV,334,"Predict the next statement of this code snippet:
 <s> case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Exclaim : case AsmToken :: Tilde : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Percent : return parseOperandWithModifier ( Operands ) ; }"
LLVM,RISCV,335,"Predict the next statement of this code snippet:
 <s> if ( parseOperand ( Operands , Name ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex ( ) ;"
LLVM,RISCV,336,"Predict the next statement of this code snippet:
 <s> if ( RegNo == <STR_LIT> ) return MatchOperand_NoMatch ; if ( RegNo != <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) + Name . size ( ) ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ;"
LLVM,RISCV,337,"Predict the next statement of this code snippet:
 <s> if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; return MatchOperand_Success ;"
LLVM,RISCV,338,"Predict the next statement of this code snippet:
 <s> Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ;"
LLVM,RISCV,339,"Predict the next statement of this code snippet:
 <s> if ( parseRegister ( Operands , true ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ;"
LLVM,RISCV,340,"Predict the next statement of this code snippet:
 <s> Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ;"
LLVM,RISCV,341,"Predict the next statement of this code snippet:
 <s> Res = <ISA_LIT>MCExpr :: create ( Res , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success ;"
LLVM,RISCV,342,"Predict the next statement of this code snippet:
 <s> matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) + Name . size ( ) ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ;"
LLVM,RISCV,343,"Predict the next statement of this code snippet:
 <s> Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( OptionalImmOp && ! OptionalImmOp -> isImmZero ( ) ) { Error ( OptionalImmOp -> getStartLoc ( ) , <STR_LIT> , SMRange ( OptionalImmOp -> getStartLoc ( ) , OptionalImmOp -> getEndLoc ( ) ) ) ; return MatchOperand_ParseFail ;"
LLVM,RISCV,344,"Predict the next statement of this code snippet:
 <s> std :: unique_ptr < <ISA_LIT>Operand > OptionalImmOp ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { int64_t ImmVal ; SMLoc ImmStart = getLoc ( ) ; if ( getParser ( ) . parseIntToken ( ImmVal , <STR_LIT> ) ) return MatchOperand_ParseFail ; SMLoc ImmEnd = getLoc ( ) ; OptionalImmOp = <ISA_LIT>Operand :: createImm ( MCConstantExpr :: create ( ImmVal , getContext ( ) ) , ImmStart , ImmEnd , isRV64 ( ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , OptionalImmOp ? <STR_LIT> : <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; }"
LLVM,RISCV,345,"Predict the next statement of this code snippet:
 <s> copySTI ( ) . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( FeatureBits ) ) ; ParserOptions = ParserOptionsStack . pop_back_val ( ) ;"
LLVM,RISCV,346,"Predict the next statement of this code snippet:
 <s> bool popFeatureBits ( ) { assert ( FeatureBitStack . size ( ) == ParserOptionsStack . size ( ) && <STR_LIT> ) ; if ( FeatureBitStack . empty ( ) ) return true ; FeatureBitset FeatureBits = FeatureBitStack . pop_back_val ( ) ; copySTI ( ) . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( FeatureBits ) ) ; ParserOptions = ParserOptionsStack . pop_back_val ( ) ;"
LLVM,RISCV,347,"Predict the next statement of this code snippet:
 <s> case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case KindTy :: Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case KindTy :: SystemRegister : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; case KindTy :: VType : OS << <STR_LIT> ; <ISA_LIT>VType :: printVType ( getVType ( ) , OS ) ; OS << '>' ;"
LLVM,RISCV,348,"Predict the next statement of this code snippet:
 <s> switch ( Kind ) { case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ;"
LLVM,RISCV,349,"Predict the next statement of this code snippet:
 <s> FeatureBitStack . push_back ( getSTI ( ) . getFeatureBits ( ) ) ; ParserOptionsStack . push_back ( ParserOptions ) ;"
LLVM,RISCV,350,"Predict the next statement of this code snippet:
 <s> void pushFeatureBits ( ) { assert ( FeatureBitStack . size ( ) == ParserOptionsStack . size ( ) && <STR_LIT> ) ;"
LLVM,RISCV,351,"Predict the next statement of this code snippet:
 <s> if ( ABIName . endswith ( <STR_LIT> ) && ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; } <STR_LIT> ( STI . getTargetTriple ( ) , STI . getFeatureBits ( ) , ABIName ) ; const MCObjectFileInfo * MOFI = Parser . getContext ( ) . getObjectFileInfo ( ) ; ParserOptions . IsPicEnabled = MOFI -> isPositionIndependent ( ) ;"
LLVM,RISCV,352,"Predict the next statement of this code snippet:
 <s> if ( ! ( getSTI ( ) . getFeatureBits ( ) [ Feature ] ) ) { MCSubtargetInfo & STI = copySTI ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString ) ) ) ; }"
LLVM,RISCV,353,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) {"
LLVM,RISCV,354,"Predict the next statement of this code snippet:
 <s> RegNo = <NUM_LIT> ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( isRV32E ( ) , ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex ( ) ; return MatchOperand_Success ;"
LLVM,RISCV,355,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: validateInstruction ( MCInst & Inst , OperandVector & Operands ) { if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { unsigned DestReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TempReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == TempReg ) { SMLoc Loc = Operands . back ( ) -> getStartLoc ( ) ; return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } const MCInstrDesc & MCID = MII . get ( Inst . getOpcode ( ) ) ; <STR_LIT> Constraints = <STR_LIT> ( MCID . TSFlags ) ; if ( Constraints == <STR_LIT> ) return false ; unsigned DestReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; SMLoc Loc = Operands [ <NUM_LIT> ] -> getStartLoc ( ) ; if ( Constraints & <STR_LIT> ) { unsigned CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( Constraints & <STR_LIT> ) && ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { unsigned CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( Constraints & <STR_LIT> ) && ( DestReg == <STR_LIT> ) ) { unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; unsigned CheckReg = Inst . getOperand ( Inst . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) ; assert ( ( CheckReg == <STR_LIT> || CheckReg == <STR_LIT> ) && <STR_LIT> ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,356,"Predict the next statement of this code snippet:
 <s> bool IsRegFPR64 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegVR = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } if ( IsRegFPR64 && Kind == MCK_FPR16 ) { Op . Reg . RegNum = convertFPR64ToFPR16 ( Reg ) ; return Match_Success ; } if ( IsRegVR && ( Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8 ) ) { Op . Reg . RegNum = convertVRToVRMx ( * getContext ( ) . getRegisterInfo ( ) , Reg , Kind ) ;"
LLVM,RISCV,357,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmParser :: emitLoadImm ( MCRegister DestReg , int64_t Value , MCStreamer & Out ) { <STR_LIT> Seq ; <STR_LIT> ( Value , isRV64 ( ) , Seq ) ; MCRegister SrcReg = <STR_LIT> ; for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; } else { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ; } SrcReg = DestReg ; }"
LLVM,RISCV,358,"Predict the next statement of this code snippet:
 <s> for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) {"
LLVM,RISCV,359,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmParser :: emitLoadStoreSymbol ( MCInst & Inst , unsigned Opcode , SMLoc IDLoc , MCStreamer & Out , bool HasTmpReg ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; unsigned SymbolOpIdx = HasTmpReg ? <NUM_LIT> : <NUM_LIT> ; unsigned TmpRegOpIdx = HasTmpReg ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,360,"Predict the next statement of this code snippet:
 <s> emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ) ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ;"
LLVM,RISCV,361,"Predict the next statement of this code snippet:
 <s> assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ;"
LLVM,RISCV,362,"Predict the next statement of this code snippet:
 <s> if ( CE ) { int64_t Imm = CE -> getValue ( ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { auto SysReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( SysReg ? SysReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SysReg = <STR_LIT> ( Identifier ) ; if ( ! SysReg ) SysReg = <STR_LIT> ( Identifier ) ; if ( SysReg ) {"
LLVM,RISCV,363,"Predict the next statement of this code snippet:
 <s> StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveOption ( ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveAttribute ( ) ; return true ;"
LLVM,RISCV,364,"Predict the next statement of this code snippet:
 <s> else if ( IDVal == <STR_LIT> ) return parseDirectiveAttribute ( ) ; return true ;"
LLVM,RISCV,365,"Predict the next statement of this code snippet:
 <s> } if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { unsigned CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( DestReg == <STR_LIT> ) ) { unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; unsigned CheckReg = Inst . getOperand ( Inst . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) ; assert ( ( CheckReg == <STR_LIT> || CheckReg == <STR_LIT> ) && <STR_LIT> ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,366,"Predict the next statement of this code snippet:
 <s> MCRegister Reg = Op . getReg ( ) ; bool IsRegFPR64 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } if ( IsRegFPR64 && Kind == MCK_FPR16 ) { Op . Reg . RegNum = convertFPR64ToFPR16 ( Reg ) ;"
LLVM,RISCV,367,"Predict the next statement of this code snippet:
 <s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { assert ( Expr && <STR_LIT> ) ; int64_t Imm = <NUM_LIT> ; bool IsConstant = false ; if ( auto * RE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { IsConstant = RE -> evaluateAsConstant ( Imm ) ; } else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { IsConstant = true ; Imm = CE -> getValue ( ) ; }"
LLVM,RISCV,368,"Predict the next statement of this code snippet:
 <s> int64_t Imm = <NUM_LIT> ; bool IsConstant = false ; if ( auto * RE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { IsConstant = RE -> evaluateAsConstant ( Imm ) ; } else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { IsConstant = true ; Imm = CE -> getValue ( ) ; }"
LLVM,RISCV,369,"Predict the next statement of this code snippet:
 <s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; auto SE = cast < MCSymbolRefExpr > ( getImm ( ) ) ; unsigned Imm = <NUM_LIT> ; for ( char c : SE -> getSymbol ( ) . getName ( ) ) { switch ( c ) { default : llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ; case 'w' : Imm |= <STR_LIT> ; break ; } } Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;"
LLVM,RISCV,370,"Predict the next statement of this code snippet:
 <s> case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ; case 'w' : Imm |= <STR_LIT> ; break ; } }"
LLVM,RISCV,371,"Predict the next statement of this code snippet:
 <s> if ( Hi20 ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Hi20 ) ) ; SrcReg = DestReg ; } if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpcode = STI -> hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitToStreamer ( Out , MCInstBuilder ( AddiOpcode ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Lo12 ) ) ; } return ; } assert ( STI -> hasFeature ( <STR_LIT> ) && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Value ) ; int64_t Hi52 = ( Value + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; emitLoadImm ( DestReg , Hi52 , Out ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addReg ( DestReg ) . addImm ( ShiftAmount ) ) ; if ( Lo12 ) emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addReg ( DestReg ) . addImm ( Lo12 ) ) ;"
LLVM,RISCV,372,"Predict the next statement of this code snippet:
 <s> unsigned SrcReg = <STR_LIT> ; if ( Hi20 ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Hi20 ) ) ; SrcReg = DestReg ; } if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpcode = STI -> hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitToStreamer ( Out , MCInstBuilder ( AddiOpcode ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Lo12 ) ) ; } return ; } assert ( STI -> hasFeature ( <STR_LIT> ) && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Value ) ; int64_t Hi52 = ( Value + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ;"
LLVM,RISCV,373,"Predict the next statement of this code snippet:
 <s> Ret = RE -> evaluateAsConstant ( Imm ) ; VK = RE -> getKind ( ) ; } else if ( auto CE = dyn_cast < MCConstantExpr > ( Val ) ) { Ret = true ;"
LLVM,RISCV,374,"Predict the next statement of this code snippet:
 <s> bool evaluateConstantImm ( int64_t & Imm , <ISA_LIT>MCExpr :: VariantKind & VK ) const { const MCExpr * Val = getImm ( ) ; bool Ret = false ;"
LLVM,RISCV,375,"Predict the next statement of this code snippet:
 <s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isShiftedInt < N - <NUM_LIT> , <NUM_LIT> > ( Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,376,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) || evaluateConstantImm ( Imm , VK ) ) return false ;"
LLVM,RISCV,377,"Predict the next statement of this code snippet:
 <s> bool isBareSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ;"
LLVM,RISCV,378,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;"
LLVM,RISCV,379,"Predict the next statement of this code snippet:
 <s> bool isSImm10Lsb0000NonZero ( ) const { if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && ( Imm != <NUM_LIT> ) && isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,380,"Predict the next statement of this code snippet:
 <s> bool isSImm12 ( ) const { <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) ;"
LLVM,RISCV,381,"Predict the next statement of this code snippet:
 <s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,382,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;"
LLVM,RISCV,383,"Predict the next statement of this code snippet:
 <s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = ( ( Imm != <NUM_LIT> ) && isInt < <NUM_LIT> > ( Imm ) ) ;"
LLVM,RISCV,384,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,385,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ;"
LLVM,RISCV,386,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,387,"Predict the next statement of this code snippet:
 <s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,388,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,389,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,390,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,391,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,392,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; int64_t Imm ;"
LLVM,RISCV,393,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;"
LLVM,RISCV,394,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;"
LLVM,RISCV,395,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ;"
LLVM,RISCV,396,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,397,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,398,"Predict the next statement of this code snippet:
 <s> return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,399,"Predict the next statement of this code snippet:
 <s> if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRVC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ;"
LLVM,RISCV,400,"Predict the next statement of this code snippet:
 <s> SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String :"
LLVM,RISCV,401,"Predict the next statement of this code snippet:
 <s> unsigned OperandIdx = <NUM_LIT> ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands , shouldForceImediateOperand ( Name , OperandIdx ) ) ) return true ; ++ OperandIdx ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; }"
LLVM,RISCV,402,"Predict the next statement of this code snippet:
 <s> if ( ! ForceImmediate && parseRegister ( Operands , true ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; }"
LLVM,RISCV,403,"Predict the next statement of this code snippet:
 <s> if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; }"
LLVM,RISCV,404,"Predict the next statement of this code snippet:
 <s> break ; case Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; }"
LLVM,RISCV,405,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: processInstruction ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { Inst . setLoc ( IDLoc ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { auto Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } else if ( Inst . getOpcode ( ) == <STR_LIT> ) { emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; } emitToStreamer ( Out , Inst ) ; return false ;"
LLVM,RISCV,406,"Predict the next statement of this code snippet:
 <s> Kind = o . Kind ; IsRV64 = o . IsRV64 ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case Register : Reg = o . Reg ; break ; case Immediate : Imm = o . Imm ; break ;"
LLVM,RISCV,407,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ; IsRV64 = o . IsRV64 ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case Register :"
LLVM,RISCV,408,"Predict the next statement of this code snippet:
 <s> static bool shouldForceImediateOperand ( StringRef Name , unsigned OperandIdx ) { switch ( OperandIdx ) { case <NUM_LIT> : return Name == <STR_LIT> || Name == <STR_LIT> ; case <NUM_LIT> :"
LLVM,RISCV,409,"Predict the next statement of this code snippet:
 <s> static bool shouldForceImediateOperand ( StringRef Name , unsigned OperandIdx ) { switch ( OperandIdx ) { case <NUM_LIT> : return Name == <STR_LIT> || Name == <STR_LIT> ; case <NUM_LIT> : return Name == <STR_LIT> ; default : return false ;"
LLVM,RISCV,410,"Predict the next statement of this code snippet:
 <s> if ( parseRegister ( Reg ) ) return Error ( Reg . StartLoc , <STR_LIT> ) ; if ( Reg . Prefix == 'x' && Reg . Number < <NUM_LIT> ) RegNo = GR32Regs [ Reg . Number ] ; else if ( Reg . Prefix == 'f' && Reg . Number < <NUM_LIT> ) RegNo = FP32Regs [ Reg . Number ] ; else return Error ( Reg . StartLoc , <STR_LIT> ) ; StartLoc = Reg . StartLoc ; EndLoc = Reg . EndLoc ; return false ;"
LLVM,RISCV,411,"Predict the next statement of this code snippet:
 <s> assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,412,"Predict the next statement of this code snippet:
 <s> MCSymbol * TmpLabel = Ctx . createTempSymbol ( <STR_LIT> , true , false ) ; Out . emitLabel ( TmpLabel ) ; const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ;"
LLVM,RISCV,413,"Predict the next statement of this code snippet:
 <s> emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( SecondOpcode ) . addOperand ( DestReg ) . addOperand ( TmpReg ) . addExpr ( RefToLinkTmpLabel ) ) ;"
LLVM,RISCV,414,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmParser :: emitLoadAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; unsigned SecondOpcode ; <ISA_LIT>MCExpr :: VariantKind VKHi ; if ( getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ) { SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; VKHi = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ; } else { SecondOpcode = <STR_LIT> ; VKHi = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI ; }"
LLVM,RISCV,415,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmParser :: emitLoadAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ;"
LLVM,RISCV,416,"Predict the next statement of this code snippet:
 <s> for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; } else { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ;"
LLVM,RISCV,417,"Predict the next statement of this code snippet:
 <s> <STR_LIT> Seq ; <STR_LIT> ( Value , isRV64 ( ) , Seq ) ; Register SrcReg = <STR_LIT> ; for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; } else { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ; }"
LLVM,RISCV,418,"Predict the next statement of this code snippet:
 <s> return StringRef ( SysReg . Data , SysReg . Length ) ;"
LLVM,RISCV,419,"Predict the next statement of this code snippet:
 <s> StringRef getSysReg ( ) const { assert ( Kind == KindTy :: SystemRegister && <STR_LIT> ) ;"
LLVM,RISCV,420,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,421,"Predict the next statement of this code snippet:
 <s> bool isBareSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,422,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ;"
LLVM,RISCV,423,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,424,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ;"
LLVM,RISCV,425,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( ( IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO ) ;"
LLVM,RISCV,426,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,427,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,428,"Predict the next statement of this code snippet:
 <s> bool isTPRelAddSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD ;"
LLVM,RISCV,429,"Predict the next statement of this code snippet:
 <s> IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI ) ; } else { return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI ) ;"
LLVM,RISCV,430,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,431,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,432,"Predict the next statement of this code snippet:
 <s> static_assert ( <STR_LIT> < <STR_LIT> , <STR_LIT> ) ; if ( RegNo == <STR_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; if ( IsRV32E && RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) RegNo = <STR_LIT> ;"
LLVM,RISCV,433,"Predict the next statement of this code snippet:
 <s> if ( isUInt < <NUM_LIT> > ( Imm ) ) { auto SysReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( SysReg ? SysReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SysReg = <STR_LIT> ( Identifier ) ; if ( SysReg ) { if ( ! SysReg -> haveRequiredFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( Identifier , S , SysReg -> Encoding , isRV64 ( ) ) ) ;"
LLVM,RISCV,434,"Predict the next statement of this code snippet:
 <s> if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ;"
LLVM,RISCV,435,"Predict the next statement of this code snippet:
 <s> case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case KindTy :: Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case KindTy :: SystemRegister : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; }"
LLVM,RISCV,436,"Predict the next statement of this code snippet:
 <s> case KindTy :: Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case KindTy :: Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case KindTy :: SystemRegister : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; }"
LLVM,RISCV,437,"Predict the next statement of this code snippet:
 <s> return false ; } int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } case <STR_LIT> : emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSIEAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSGDAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ;"
LLVM,RISCV,438,"Predict the next statement of this code snippet:
 <s> Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; auto ABIName = StringRef ( Options . ABIName ) ; if ( ABIName . endswith ( <STR_LIT> ) && ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ;"
LLVM,RISCV,439,"Predict the next statement of this code snippet:
 <s> Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; auto ABIName = StringRef ( Options . ABIName ) ; if ( ABIName . endswith ( <STR_LIT> ) && ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ;"
LLVM,RISCV,440,"Predict the next statement of this code snippet:
 <s> StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case KindTy :: Register : Reg = o . Reg ; break ; case KindTy :: Immediate :"
LLVM,RISCV,441,"Predict the next statement of this code snippet:
 <s> StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case KindTy :: Register : Reg = o . Reg ; break ; case KindTy :: Immediate : Imm = o . Imm ; break ;"
LLVM,RISCV,442,"Predict the next statement of this code snippet:
 <s> StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( isRV32E ( ) , ( Register & ) RegNo , Name ) ) return MatchOperand_NoMatch ;"
LLVM,RISCV,443,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; Register Reg = Op . getReg ( ) ; bool IsRegFPR64 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ;"
LLVM,RISCV,444,"Predict the next statement of this code snippet:
 <s> emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( SecondOpcode ) . addOperand ( DestReg ) . addOperand ( TmpReg ) . addExpr ( RefToLinkTmpLabel ) ) ;"
LLVM,RISCV,445,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ;"
LLVM,RISCV,446,"Predict the next statement of this code snippet:
 <s> bool Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ;"
LLVM,RISCV,447,"Predict the next statement of this code snippet:
 <s> MCInst CInst ; bool Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ; if ( Res ) ++ <ISA_LIT>NumInstrsCompressed ;"
LLVM,RISCV,448,"Predict the next statement of this code snippet:
 <s> return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCLUIImm : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm13Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm20LUI : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidUImm20AUIPC : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm21Lsb0JAL : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCSRSystemRegister : { return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ;"
LLVM,RISCV,449,"Predict the next statement of this code snippet:
 <s> StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( isRV32E ( ) , ( Register & ) RegNo , Name ) ) return Error ( StartLoc , <STR_LIT> ) ; getParser ( ) . Lex ( ) ;"
LLVM,RISCV,450,"Predict the next statement of this code snippet:
 <s> return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ) ;"
LLVM,RISCV,451,"Predict the next statement of this code snippet:
 <s> bool isSImm12 ( ) const { <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,452,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD ;"
LLVM,RISCV,453,"Predict the next statement of this code snippet:
 <s> bool isUImm20AUIPC ( ) const { <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) {"
LLVM,RISCV,454,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI ) ;"
LLVM,RISCV,455,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI ) ; } else { return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI ) ;"
LLVM,RISCV,456,"Predict the next statement of this code snippet:
 <s> case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } } if ( Result > FIRST_TARGET_MATCH_RESULT_TY ) { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> && ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; } switch ( Result ) { default : break ; case Match_InvalidImmXLenLI : if ( isRV64 ( ) ) { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } return generateImmOutOfRangeError ( Operands , ErrorInfo , std :: numeric_limits < int32_t > :: min ( ) , std :: numeric_limits < uint32_t > :: max ( ) ) ; case Match_InvalidUImmLog2XLen : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImmLog2XLenNonZero : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6NonZero :"
LLVM,RISCV,457,"Predict the next statement of this code snippet:
 <s> static bool matchRegisterNameHelper ( bool IsRV32E , unsigned & RegNo , StringRef Name ) { RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; if ( IsRV32E && RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) RegNo = <NUM_LIT> ; return RegNo == <NUM_LIT> ;"
LLVM,RISCV,458,"Predict the next statement of this code snippet:
 <s> static bool matchRegisterNameHelper ( bool IsRV32E , unsigned & RegNo , StringRef Name ) { RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; if ( IsRV32E && RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) RegNo = <NUM_LIT> ;"
LLVM,RISCV,459,"Predict the next statement of this code snippet:
 <s> if ( ReadCount == <NUM_LIT> && Buf [ <NUM_LIT> ] . getKind ( ) == AsmToken :: RParen ) { HadParens = true ; LParen = getParser ( ) . getTok ( ) ; getParser ( ) . Lex ( ) ; } } switch ( getLexer ( ) . getKind ( ) ) { default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ;"
LLVM,RISCV,460,"Predict the next statement of this code snippet:
 <s> emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ;"
LLVM,RISCV,461,"Predict the next statement of this code snippet:
 <s> emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addExpr ( Op1 . getExpr ( ) ) ) ; return false ; } int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } case <STR_LIT> : emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSIEAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSGDAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : if ( checkPseudoAddTPRel ( Inst , Operands ) ) return true ; break ;"
LLVM,RISCV,462,"Predict the next statement of this code snippet:
 <s> return Error ( ErrorLoc , Msg + <STR_LIT> + Twine ( Lower ) + <STR_LIT> + Twine ( Upper ) + <STR_LIT> ) ;"
LLVM,RISCV,463,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int Lower , int Upper , Twine Msg = <STR_LIT> ) { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ;"
LLVM,RISCV,464,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;"
LLVM,RISCV,465,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,466,"Predict the next statement of this code snippet:
 <s> else IsValid = isInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,467,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;"
LLVM,RISCV,468,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,469,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,470,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;"
LLVM,RISCV,471,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,472,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;"
LLVM,RISCV,473,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;"
LLVM,RISCV,474,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ;"
LLVM,RISCV,475,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,476,"Predict the next statement of this code snippet:
 <s> bool isUImm9Lsb000 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;"
LLVM,RISCV,477,"Predict the next statement of this code snippet:
 <s> ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidUImmLog2XLen : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImmLog2XLenNonZero : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000 :"
LLVM,RISCV,478,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { Operands . push_back ( <ISA_LIT>Operand :: createToken ( Name , NameLoc , isRV64 ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( parseOperand ( Operands ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ;"
LLVM,RISCV,479,"Predict the next statement of this code snippet:
 <s> getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ;"
LLVM,RISCV,480,"Predict the next statement of this code snippet:
 <s> if ( parseRegister ( Operands , true ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; }"
LLVM,RISCV,481,"Predict the next statement of this code snippet:
 <s> if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; } Error ( getLoc ( ) , <STR_LIT> ) ; return true ;"
LLVM,RISCV,482,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;"
LLVM,RISCV,483,"Predict the next statement of this code snippet:
 <s> MCRegister SrcReg = <STR_LIT> ; for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; } else if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( <STR_LIT> ) ) ; } else { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ;"
LLVM,RISCV,484,"Predict the next statement of this code snippet:
 <s> for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; } else if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( <STR_LIT> ) ) ; } else { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ;"
LLVM,RISCV,485,"Predict the next statement of this code snippet:
 <s> } else if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( <STR_LIT> ) ) ; } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ) ;"
LLVM,RISCV,486,"Predict the next statement of this code snippet:
 <s> Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) { getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } Res = V ; } else Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; MCBinaryExpr :: Opcode Opcode ; switch ( getLexer ( ) . getKind ( ) ) { default :"
LLVM,RISCV,487,"Predict the next statement of this code snippet:
 <s> return false ; } if ( parseOperand ( Operands , Name ) ) return true ; unsigned OperandIdx = <NUM_LIT> ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) return true ; ++ OperandIdx ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ;"
LLVM,RISCV,488,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ; case 'w' : Imm |= <STR_LIT> ; break ; } } Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;"
LLVM,RISCV,489,"Predict the next statement of this code snippet:
 <s> void addVTypeIOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,490,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned RegNo , SMLoc S , SMLoc E , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> IsRV64 = IsRV64 ;"
LLVM,RISCV,491,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createSysReg ( StringRef Str , SMLoc S , unsigned Encoding , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: SystemRegister ) ; Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . Encoding = Encoding ; Op -> StartLoc = S ;"
LLVM,RISCV,492,"Predict the next statement of this code snippet:
 <s> } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ) ; } else { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ; } SrcReg = DestReg ; }"
LLVM,RISCV,493,"Predict the next statement of this code snippet:
 <s> emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ) ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ;"
LLVM,RISCV,494,"Predict the next statement of this code snippet:
 <s> emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ) ;"
LLVM,RISCV,495,"Predict the next statement of this code snippet:
 <s> return Kind == KindTy :: VType ;"
LLVM,RISCV,496,"Predict the next statement of this code snippet:
 <s> bool isVType ( ) const { return Kind == KindTy :: VType ;"
LLVM,RISCV,497,"Predict the next statement of this code snippet:
 <s> return isVType ( ) ;"
LLVM,RISCV,498,"Predict the next statement of this code snippet:
 <s> return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImmLog2XLenNonZero : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImmLog2XLenHalf : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm3 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm7 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCLUIImm : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm12Lsb0 :"
LLVM,RISCV,499,"Predict the next statement of this code snippet:
 <s> } getParser ( ) . Lex ( ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( OptionalImmOp && ! OptionalImmOp -> isImmZero ( ) ) { Error ( OptionalImmOp -> getStartLoc ( ) , <STR_LIT> , SMRange ( OptionalImmOp -> getStartLoc ( ) , OptionalImmOp -> getEndLoc ( ) ) ) ; return MatchOperand_ParseFail ; } return MatchOperand_Success ;"
LLVM,RISCV,500,"Predict the next statement of this code snippet:
 <s> std :: unique_ptr < <ISA_LIT>Operand > OptionalImmOp ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { int64_t ImmVal ; SMLoc ImmStart = getLoc ( ) ; if ( getParser ( ) . parseIntToken ( ImmVal , <STR_LIT> ) ) return MatchOperand_ParseFail ; SMLoc ImmEnd = getLoc ( ) ; OptionalImmOp = <ISA_LIT>Operand :: createImm ( MCConstantExpr :: create ( ImmVal , getContext ( ) ) , ImmStart , ImmEnd , isRV64 ( ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , OptionalImmOp ? <STR_LIT> : <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) {"
LLVM,RISCV,501,"Predict the next statement of this code snippet:
 <s> SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ; AsmToken Tok = getLexer ( ) . getTok ( ) ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; if ( Identifier . consume_back ( <STR_LIT> ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) { getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } Res = V ; } else Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; MCBinaryExpr :: Opcode Opcode ; switch ( getLexer ( ) . getKind ( ) ) { default : Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success ; case AsmToken :: Plus : Opcode = MCBinaryExpr :: Add ; break ; case AsmToken :: Minus : Opcode = MCBinaryExpr :: Sub ; break ; } const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success ;"
LLVM,RISCV,502,"Predict the next statement of this code snippet:
 <s> const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ; AsmToken Tok = getLexer ( ) . getTok ( ) ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; if ( Identifier . consume_back ( <STR_LIT> ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) {"
LLVM,RISCV,503,"Predict the next statement of this code snippet:
 <s> if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ;"
LLVM,RISCV,504,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success ;"
LLVM,RISCV,505,"Predict the next statement of this code snippet:
 <s> const MCExpr * ValueExpr ; if ( Parser . parseExpression ( ValueExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ValueExpr ) ; if ( ! CE ) return Error ( ValueExprLoc , <STR_LIT> ) ; IntegerValue = CE -> getValue ( ) ; } else { if ( Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; StringValue = Parser . getTok ( ) . getStringContents ( ) ; Parser . Lex ( ) ; } if ( Parser . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( Tag == <STR_LIT> ) { StringRef Arch = StringValue ; for ( auto Feature : <ISA_LIT>FeatureKV ) if ( llvm :: <STR_LIT> ( Feature . Key ) ) clearFeatureBits ( Feature . Value , Feature . Key ) ; auto ParseResult = llvm :: <STR_LIT> ( StringValue , true , false ) ; if ( ! ParseResult ) { std :: string Buffer ; raw_string_ostream OutputErrMsg ( Buffer ) ; handleAllErrors ( ParseResult . takeError ( ) , [ & ] ( llvm :: StringError & ErrMsg ) { OutputErrMsg << <STR_LIT> << Arch << <STR_LIT> << ErrMsg . getMessage ( ) ; } ) ; return Error ( ValueExprLoc , OutputErrMsg . str ( ) ) ; } auto & ISAInfo = * ParseResult ; for ( auto Feature : <ISA_LIT>FeatureKV ) if ( ISAInfo -> hasExtension ( Feature . Key ) ) setFeatureBits ( Feature . Value , Feature . Key ) ; if ( ISAInfo -> getXLen ( ) == <NUM_LIT> ) clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; else if ( ISAInfo -> getXLen ( ) == <NUM_LIT> ) setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; else return Error ( ValueExprLoc , <STR_LIT> + Arch ) ; } if ( IsIntegerValue ) getTargetStreamer ( ) . emitAttribute ( Tag , IntegerValue ) ; else { if ( Tag != <STR_LIT> ) { getTargetStreamer ( ) . emitTextAttribute ( Tag , StringValue ) ; } else { std :: vector < std :: string > FeatureVector ; <STR_LIT> ( FeatureVector , getSTI ( ) . getFeatureBits ( ) ) ; unsigned XLen = getFeatureBits ( <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; auto ParseResult = llvm :: <STR_LIT> ( XLen , FeatureVector ) ; if ( ! ParseResult ) { std :: string Buffer ; raw_string_ostream OutputErrMsg ( Buffer ) ; handleAllErrors ( ParseResult . takeError ( ) , [ & ] ( llvm :: StringError & ErrMsg ) { OutputErrMsg << ErrMsg . getMessage ( ) ; } ) ; return Error ( ValueExprLoc , OutputErrMsg . str ( ) ) ; } auto & ISAInfo = * ParseResult ; getTargetStreamer ( ) . emitTextAttribute ( Tag , ISAInfo -> toString ( ) ) ;"
LLVM,RISCV,506,"Predict the next statement of this code snippet:
 <s> default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Dot : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Exclaim : case AsmToken :: Tilde : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Percent :"
LLVM,RISCV,507,"Predict the next statement of this code snippet:
 <s> if ( RegNo == <STR_LIT> ) return MatchOperand_NoMatch ; if ( RegNo != <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ;"
LLVM,RISCV,508,"Predict the next statement of this code snippet:
 <s> if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; if ( Res -> getKind ( ) != MCExpr :: ExprKind :: SymbolRef || cast < MCSymbolRefExpr > ( Res ) -> getKind ( ) == MCSymbolRefExpr :: VariantKind :: VK_PLT ) { Error ( S , <STR_LIT> ) ;"
LLVM,RISCV,509,"Predict the next statement of this code snippet:
 <s> if ( ReadCount == <NUM_LIT> && Buf [ <NUM_LIT> ] . getKind ( ) == AsmToken :: RParen ) { HadParens = true ; LParen = getParser ( ) . getTok ( ) ; getParser ( ) . Lex ( ) ; } } switch ( getLexer ( ) . getKind ( ) ) { default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ;"
LLVM,RISCV,510,"Predict the next statement of this code snippet:
 <s> size_t ReadCount = getLexer ( ) . peekTokens ( Buf ) ; if ( ReadCount == <NUM_LIT> && Buf [ <NUM_LIT> ] . getKind ( ) == AsmToken :: RParen ) { HadParens = true ; LParen = getParser ( ) . getTok ( ) ; getParser ( ) . Lex ( ) ; } } switch ( getLexer ( ) . getKind ( ) ) { default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; }"
LLVM,RISCV,511,"Predict the next statement of this code snippet:
 <s> if ( Name . getAsInteger ( <NUM_LIT> , Sew ) ) goto MatchFail ; if ( ! <ISA_LIT>VType :: isValidSEW ( Sew ) ) goto MatchFail ; Name = VTypeIElements [ <NUM_LIT> ] . getIdentifier ( ) ; if ( ! Name . consume_front ( <STR_LIT> ) ) goto MatchFail ; bool Fractional = Name . consume_front ( <STR_LIT> ) ; unsigned Lmul ; if ( Name . getAsInteger ( <NUM_LIT> , Lmul ) ) goto MatchFail ; if ( ! <ISA_LIT>VType :: isValidLMUL ( Lmul , Fractional ) ) goto MatchFail ; Name = VTypeIElements [ <NUM_LIT> ] . getIdentifier ( ) ; bool TailAgnostic ; if ( Name == <STR_LIT> ) TailAgnostic = true ; else if ( Name == <STR_LIT> ) TailAgnostic = false ; else goto MatchFail ; Name = VTypeIElements [ <NUM_LIT> ] . getIdentifier ( ) ; bool MaskAgnostic ; if ( Name == <STR_LIT> ) MaskAgnostic = true ; else if ( Name == <STR_LIT> ) MaskAgnostic = false ; else goto MatchFail ; unsigned LmulLog2 = Log2_32 ( Lmul ) ; <STR_LIT> VLMUL = static_cast < <STR_LIT> > ( Fractional ? <NUM_LIT> - LmulLog2 : LmulLog2 ) ; unsigned VTypeI = <ISA_LIT>VType :: encodeVTYPE ( VLMUL , Sew , TailAgnostic , MaskAgnostic ) ; Operands . push_back ( <ISA_LIT>Operand :: createVType ( VTypeI , S , isRV64 ( ) ) ) ; return MatchOperand_Success ; } MatchFail : while ( ! VTypeIElements . empty ( ) ) getLexer ( ) . UnLex ( VTypeIElements . pop_back_val ( ) ) ;"
LLVM,RISCV,512,"Predict the next statement of this code snippet:
 <s> Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; auto ABIName = StringRef ( Options . ABIName ) ; if ( ABIName . endswith ( <STR_LIT> ) && ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) {"
LLVM,RISCV,513,"Predict the next statement of this code snippet:
 <s> auto Op = make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ;"
LLVM,RISCV,514,"Predict the next statement of this code snippet:
 <s> auto Op = make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ;"
LLVM,RISCV,515,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isShiftedInt < N - <NUM_LIT> , <NUM_LIT> > ( Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,516,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; bool IsValid ;"
LLVM,RISCV,517,"Predict the next statement of this code snippet:
 <s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;"
LLVM,RISCV,518,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,519,"Predict the next statement of this code snippet:
 <s> bool isUImm12 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,520,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,521,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; bool IsValid ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,522,"Predict the next statement of this code snippet:
 <s> else IsValid = isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,523,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,524,"Predict the next statement of this code snippet:
 <s> bool isUImm5 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;"
LLVM,RISCV,525,"Predict the next statement of this code snippet:
 <s> MCInst Inst ; switch ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ) { default : break ; case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;"
LLVM,RISCV,526,"Predict the next statement of this code snippet:
 <s> switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Identifier : { StringRef Identifier ;"
LLVM,RISCV,527,"Predict the next statement of this code snippet:
 <s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex ( ) ;"
LLVM,RISCV,528,"Predict the next statement of this code snippet:
 <s> if ( parseOperand ( Operands ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; }"
LLVM,RISCV,529,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMemOpBaseReg ( OperandVector & Operands ) { if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) {"
LLVM,RISCV,530,"Predict the next statement of this code snippet:
 <s> } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) ) ) ;"
LLVM,RISCV,531,"Predict the next statement of this code snippet:
 <s> if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; } Error ( getLoc ( ) , <STR_LIT> ) ; return true ;"
LLVM,RISCV,532,"Predict the next statement of this code snippet:
 <s> if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ; if ( getParser ( ) . parseParenExpression ( SubExpr , E ) ) { return MatchOperand_ParseFail ; } const MCExpr * ModExpr = <ISA_LIT>MCExpr :: create ( SubExpr , VK , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( ModExpr , S , E , getContext ( ) ) ) ; return MatchOperand_Success ;"
LLVM,RISCV,533,"Predict the next statement of this code snippet:
 <s> } StringRef Identifier = getParser ( ) . getTok ( ) . getIdentifier ( ) ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: getVariantKindForName ( Identifier ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ; if ( getParser ( ) . parseParenExpression ( SubExpr , E ) ) {"
LLVM,RISCV,534,"Predict the next statement of this code snippet:
 <s> unsigned RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) { RegNo = MatchRegisterAltName ( Name ) ; if ( RegNo == <NUM_LIT> ) return MatchOperand_NoMatch ; } getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E ) ) ; }"
LLVM,RISCV,535,"Predict the next statement of this code snippet:
 <s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;"
LLVM,RISCV,536,"Predict the next statement of this code snippet:
 <s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;"
LLVM,RISCV,537,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ;"
LLVM,RISCV,538,"Predict the next statement of this code snippet:
 <s> CInst . setLoc ( IDLoc ) ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( ( Res ? CInst : Inst ) , getSTI ( ) ) ; return false ; } case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidUImmLog2XLen : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImmLog2XLenNonZero : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCLUIImm : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,539,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( ( IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) ;"
LLVM,RISCV,540,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,541,"Predict the next statement of this code snippet:
 <s> bool isSImm6 ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ;"
LLVM,RISCV,542,"Predict the next statement of this code snippet:
 <s> bool isSImm6NonZero ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,543,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;"
LLVM,RISCV,544,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) {"
LLVM,RISCV,545,"Predict the next statement of this code snippet:
 <s> bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; } else {"
LLVM,RISCV,546,"Predict the next statement of this code snippet:
 <s> bool isUImm20LUI ( ) const { <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ;"
LLVM,RISCV,547,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { Operands . push_back ( <ISA_LIT>Operand :: createToken ( Name , NameLoc , isRV64 ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( parseOperand ( Operands , Name ) ) return true ; unsigned OperandIdx = <NUM_LIT> ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) return true ; ++ OperandIdx ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; }"
LLVM,RISCV,548,"Predict the next statement of this code snippet:
 <s> } case Match_InvalidUImmLog2XLen : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImmLog2XLenNonZero : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm12Lsb0 :"
LLVM,RISCV,549,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,550,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,551,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = ( ( Imm != <NUM_LIT> ) && isInt < <NUM_LIT> > ( Imm ) ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;"
LLVM,RISCV,552,"Predict the next statement of this code snippet:
 <s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = ( ( Imm != <NUM_LIT> ) && isInt < <NUM_LIT> > ( Imm ) ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;"
LLVM,RISCV,553,"Predict the next statement of this code snippet:
 <s> case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCLUIImm : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,554,"Predict the next statement of this code snippet:
 <s> } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex ( ) ; return false ;"
LLVM,RISCV,555,"Predict the next statement of this code snippet:
 <s> if ( parseOperand ( Operands , ForceImmediate ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands , false ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ;"
LLVM,RISCV,556,"Predict the next statement of this code snippet:
 <s> int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,557,"Predict the next statement of this code snippet:
 <s> <STR_LIT> Seq = <STR_LIT> ( Value , isRV64 ( ) ) ; MCRegister SrcReg = <STR_LIT> ; for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) {"
LLVM,RISCV,558,"Predict the next statement of this code snippet:
 <s> emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; } else { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ; } SrcReg = DestReg ; }"
LLVM,RISCV,559,"Predict the next statement of this code snippet:
 <s> return false ; case <STR_LIT> : emitLoadTLSIEAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSGDAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> :"
LLVM,RISCV,560,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : if ( checkPseudoAddTPRel ( Inst , Operands ) ) return true ; }"
LLVM,RISCV,561,"Predict the next statement of this code snippet:
 <s> void addSImm5Plus1Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Imm = <NUM_LIT> ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstant = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; assert ( IsConstant && <STR_LIT> ) ; ( void ) IsConstant ;"
LLVM,RISCV,562,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstant = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,563,"Predict the next statement of this code snippet:
 <s> if ( TargetFlags == <STR_LIT> ) return false ; unsigned DestReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CheckReg ; SMLoc Loc = Operands [ <NUM_LIT> ] -> getStartLoc ( ) ; if ( TargetFlags & <STR_LIT> ) { CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( DestReg == <STR_LIT> ) ) { unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getNumOperands ( ) == <NUM_LIT> ) ) CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,564,"Predict the next statement of this code snippet:
 <s> if ( TargetFlags == <STR_LIT> ) return false ; unsigned DestReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CheckReg ; SMLoc Loc = Operands [ <NUM_LIT> ] -> getStartLoc ( ) ; if ( TargetFlags & <STR_LIT> ) { CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( DestReg == <STR_LIT> ) ) { unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getNumOperands ( ) == <NUM_LIT> ) ) CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,565,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( VType . Encoding ) ) ;"
LLVM,RISCV,566,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( VType . Encoding ) ) ;"
LLVM,RISCV,567,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createVType ( APInt Sew , APInt Lmul , bool Fractional , bool TailAgnostic , bool MaskedoffAgnostic , SMLoc S , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: VType ) ; Sew . ashrInPlace ( <NUM_LIT> ) ; unsigned SewLog2 = Sew . logBase2 ( ) ; unsigned LmulLog2 = Lmul . logBase2 ( ) ; Op -> VType . Sew = static_cast < VSEW > ( SewLog2 ) ; if ( Fractional ) { unsigned Flmul = <NUM_LIT> - LmulLog2 ; Op -> VType . Lmul = static_cast < VLMUL > ( Flmul ) ; Op -> VType . Encoding = ( SewLog2 << <NUM_LIT> ) | Flmul ; } else { Op -> VType . Lmul = static_cast < VLMUL > ( LmulLog2 ) ;"
LLVM,RISCV,568,"Predict the next statement of this code snippet:
 <s> Op -> VType . Encoding = ( SewLog2 << <NUM_LIT> ) | Flmul ; } else { Op -> VType . Lmul = static_cast < VLMUL > ( LmulLog2 ) ; Op -> VType . Encoding = ( SewLog2 << <NUM_LIT> ) | LmulLog2 ; } if ( TailAgnostic ) { Op -> VType . Encoding |= <NUM_LIT> ; } if ( MaskedoffAgnostic ) {"
LLVM,RISCV,569,"Predict the next statement of this code snippet:
 <s> switch ( Lmul ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,570,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,571,"Predict the next statement of this code snippet:
 <s> StringRef getVType ( SmallString < <NUM_LIT> > & Buf ) const { assert ( Kind == KindTy :: VType && <STR_LIT> ) ; Buf . append ( getSEWStr ( VType . Sew ) ) ; Buf . append ( <STR_LIT> ) ; Buf . append ( getLMULStr ( VType . Lmul ) ) ;"
LLVM,RISCV,572,"Predict the next statement of this code snippet:
 <s> StringRef getVType ( SmallString < <NUM_LIT> > & Buf ) const { assert ( Kind == KindTy :: VType && <STR_LIT> ) ; Buf . append ( getSEWStr ( VType . Sew ) ) ; Buf . append ( <STR_LIT> ) ; Buf . append ( getLMULStr ( VType . Lmul ) ) ;"
LLVM,RISCV,573,"Predict the next statement of this code snippet:
 <s> return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm13Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm20LUI : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidUImm20AUIPC : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm21Lsb0JAL : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCSRSystemRegister : { return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidFRMArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidBareSymbol : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; }"
LLVM,RISCV,574,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMaskReg ( OperandVector & Operands ) { switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ! Name . consume_back ( <STR_LIT> ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Register RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) return MatchOperand_NoMatch ; if ( RegNo != <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; }"
LLVM,RISCV,575,"Predict the next statement of this code snippet:
 <s> if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ! Name . consume_front ( <STR_LIT> ) ) return MatchOperand_NoMatch ; bool Fractional = false ; if ( Name . consume_front ( <STR_LIT> ) ) { Fractional = true ; } APInt Lmul ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; bool TailAgnostic ;"
LLVM,RISCV,576,"Predict the next statement of this code snippet:
 <s> if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( DestReg == <STR_LIT> ) ) { unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getNumOperands ( ) == <NUM_LIT> ) ) CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,577,"Predict the next statement of this code snippet:
 <s> const MCInstrDesc & MCID = MII . get ( Inst . getOpcode ( ) ) ; unsigned TargetFlags = ( MCID . TSFlags >> <STR_LIT> ) & <STR_LIT> ; if ( TargetFlags == <STR_LIT> ) return false ; unsigned DestReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CheckReg ; SMLoc Loc = Operands [ <NUM_LIT> ] -> getStartLoc ( ) ; if ( TargetFlags & <STR_LIT> ) { CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( DestReg == <STR_LIT> ) ) { unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getNumOperands ( ) == <NUM_LIT> ) ) CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,578,"Predict the next statement of this code snippet:
 <s> bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR16 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ;"
LLVM,RISCV,579,"Predict the next statement of this code snippet:
 <s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,580,"Predict the next statement of this code snippet:
 <s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,581,"Predict the next statement of this code snippet:
 <s> SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> <STR_LIT> ) ; } return false ;"
LLVM,RISCV,582,"Predict the next statement of this code snippet:
 <s> Op -> SpecialCapReg . Data = Str . data ( ) ; Op -> SpecialCapReg . Length = Str . size ( ) ; Op -> SpecialCapReg . Encoding = Encoding ; Op -> StartLoc = S ; Op -> IsRV64 = IsRV64 ; return Op ;"
LLVM,RISCV,583,"Predict the next statement of this code snippet:
 <s> Out . emitLabel ( TmpLabel ) ; const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ;"
LLVM,RISCV,584,"Predict the next statement of this code snippet:
 <s> const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ;"
LLVM,RISCV,585,"Predict the next statement of this code snippet:
 <s> const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; unsigned SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; emitAuipccInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CAPTAB_PCREL_HI , SecondOpcode , IDLoc , Out ) ;"
LLVM,RISCV,586,"Predict the next statement of this code snippet:
 <s> unsigned SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,587,"Predict the next statement of this code snippet:
 <s> const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ;"
LLVM,RISCV,588,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmParser :: emitCapLoadLocalCap ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; emitAuipccInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI , <STR_LIT> , IDLoc , Out ) ;"
LLVM,RISCV,589,"Predict the next statement of this code snippet:
 <s> MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; emitAuipccInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI , <STR_LIT> , IDLoc , Out ) ;"
LLVM,RISCV,590,"Predict the next statement of this code snippet:
 <s> emitAuipccInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI , <STR_LIT> , IDLoc , Out ) ;"
LLVM,RISCV,591,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmParser :: emitCapLoadTLSIEAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,592,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmParser :: emitCapLoadTLSIEAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; MCOperand TmpReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; unsigned SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; emitAuipccInstPair ( DestReg , TmpReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI , SecondOpcode , IDLoc , Out ) ;"
LLVM,RISCV,593,"Predict the next statement of this code snippet:
 <s> unsigned getCheriCapabilitySize ( ) const override {"
LLVM,RISCV,594,"Predict the next statement of this code snippet:
 <s> return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CCALL ;"
LLVM,RISCV,595,"Predict the next statement of this code snippet:
 <s> bool isCCallSymbol ( ) const { int64_t Imm ;"
LLVM,RISCV,596,"Predict the next statement of this code snippet:
 <s> return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;"
LLVM,RISCV,597,"Predict the next statement of this code snippet:
 <s> return Kind == KindTy :: Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;"
LLVM,RISCV,598,"Predict the next statement of this code snippet:
 <s> bool isPseudoCJumpSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CCALL ;"
LLVM,RISCV,599,"Predict the next statement of this code snippet:
 <s> bool isSpecialCapRegister ( ) const { return Kind == KindTy :: SpecialCapRegister ;"
LLVM,RISCV,600,"Predict the next statement of this code snippet:
 <s> return Kind == KindTy :: SpecialCapRegister ;"
LLVM,RISCV,601,"Predict the next statement of this code snippet:
 <s> bool isTPRelCIncOffsetSymbol ( ) const { int64_t Imm ;"
LLVM,RISCV,602,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,603,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,604,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,605,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,606,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK ;"
LLVM,RISCV,607,"Predict the next statement of this code snippet:
 <s> bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CAPTAB_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI ) ; } else { return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CAPTAB_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI ) ; }"
LLVM,RISCV,608,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CAPTAB_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI ) ; } else { return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CAPTAB_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI ) ;"
LLVM,RISCV,609,"Predict the next statement of this code snippet:
 <s> int64_t Imm ;"
LLVM,RISCV,610,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,611,"Predict the next statement of this code snippet:
 <s> const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; if ( getLexer ( ) . peekTok ( ) . getKind ( ) != AsmToken :: EndOfStatement ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind ; if ( IsCap ) { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CCALL ; Identifier . consume_back ( <STR_LIT> ) ; } else { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success ;"
LLVM,RISCV,612,"Predict the next statement of this code snippet:
 <s> SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; if ( getLexer ( ) . peekTok ( ) . getKind ( ) != AsmToken :: EndOfStatement ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind ; if ( IsCap ) { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CCALL ; Identifier . consume_back ( <STR_LIT> ) ; } else { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ;"
LLVM,RISCV,613,"Predict the next statement of this code snippet:
 <s> Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRVC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = true ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = false ; return false ; } if ( Option == <STR_LIT> ) {"
LLVM,RISCV,614,"Predict the next statement of this code snippet:
 <s> return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = false ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionRelax ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRelax ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { if ( ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveOptionCapMode ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { if ( ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveOptionNoCapMode ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ;"
LLVM,RISCV,615,"Predict the next statement of this code snippet:
 <s> if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; if ( Res -> getKind ( ) != MCExpr :: ExprKind :: SymbolRef || cast < MCSymbolRefExpr > ( Res ) -> getKind ( ) == MCSymbolRefExpr :: VariantKind :: VK_PLT ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; }"
LLVM,RISCV,616,"Predict the next statement of this code snippet:
 <s> default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; auto * CE = dyn_cast < MCConstantExpr > ( Res ) ; if ( CE ) { int64_t Imm = CE -> getValue ( ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { auto SpecialCapReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSpecialCapReg ( SpecialCapReg ? SpecialCapReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SpecialCapReg = <STR_LIT> ( Identifier ) ; if ( SpecialCapReg ) { Operands . push_back ( <ISA_LIT>Operand :: createSpecialCapReg ( Identifier , S , SpecialCapReg -> Encoding , isRV64 ( ) ) ) ; return MatchOperand_Success ;"
LLVM,RISCV,617,"Predict the next statement of this code snippet:
 <s> if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; auto * CE = dyn_cast < MCConstantExpr > ( Res ) ; if ( CE ) { int64_t Imm = CE -> getValue ( ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { auto SpecialCapReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSpecialCapReg ( SpecialCapReg ? SpecialCapReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SpecialCapReg = <STR_LIT> ( Identifier ) ; if ( SpecialCapReg ) { Operands . push_back ( <ISA_LIT>Operand :: createSpecialCapReg ( Identifier , S , SpecialCapReg -> Encoding , isRV64 ( ) ) ) ; return MatchOperand_Success ; } Twine Msg = <STR_LIT> <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; }"
LLVM,RISCV,618,"Predict the next statement of this code snippet:
 <s> auto RegName = [ ] ( unsigned Reg ) { if ( Reg ) return <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; else return <STR_LIT> ; } ; switch ( Kind ) { case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case KindTy :: Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case KindTy :: SystemRegister : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; case KindTy :: SpecialCapRegister :"
LLVM,RISCV,619,"Predict the next statement of this code snippet:
 <s> void print ( raw_ostream & OS ) const override { auto RegName = [ ] ( unsigned Reg ) { if ( Reg ) return <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; else return <STR_LIT> ; } ; switch ( Kind ) { case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ;"
LLVM,RISCV,620,"Predict the next statement of this code snippet:
 <s> if ( Op1 . isExpr ( ) ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addExpr ( Op1 . getExpr ( ) ) ) ; return false ; } int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } case <STR_LIT> : emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSIEAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSGDAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ;"
LLVM,RISCV,621,"Predict the next statement of this code snippet:
 <s> emitLoadTLSGDAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : if ( checkPseudoAddTPRel ( Inst , Operands ) ) return true ; break ; case <STR_LIT> : emitCapLoadLocalCap ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitCapLoadGlobalCap ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitCapLoadTLSIEAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitCapLoadTLSGDCap ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : if ( checkPseudoCIncOffsetTPRel ( Inst , Operands ) ) return true ; break ; case <STR_LIT> : emitPseudoExtend ( Inst , true , <NUM_LIT> , IDLoc , Out ) ; return false ; case <STR_LIT> : emitPseudoExtend ( Inst , true , <NUM_LIT> , IDLoc , Out ) ; return false ; case <STR_LIT> : emitPseudoExtend ( Inst , false , <NUM_LIT> , IDLoc , Out ) ; return false ; case <STR_LIT> : emitPseudoExtend ( Inst , false , <NUM_LIT> , IDLoc , Out ) ; return false ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,622,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ) ; } else { return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ) ; }"
LLVM,RISCV,623,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ) ;"
LLVM,RISCV,624,"Predict the next statement of this code snippet:
 <s> unsigned Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCOperand & Op1 = Inst . getOperand ( <NUM_LIT> ) ; if ( Op1 . isExpr ( ) ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addExpr ( Op1 . getExpr ( ) ) ) ; return false ; } int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } case <STR_LIT> : emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> :"
LLVM,RISCV,625,"Predict the next statement of this code snippet:
 <s> Inst . setLoc ( IDLoc ) ; switch ( Inst . getOpcode ( ) ) { default : break ; case <STR_LIT> : { unsigned Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCOperand & Op1 = Inst . getOperand ( <NUM_LIT> ) ; if ( Op1 . isExpr ( ) ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addExpr ( Op1 . getExpr ( ) ) ) ; return false ;"
LLVM,RISCV,626,"Predict the next statement of this code snippet:
 <s> case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm13Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm20LUI : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidUImm20AUIPC : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm21Lsb0JAL : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCSRSystemRegister : { return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidFRMArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidBareSymbol : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidPseudoJumpSymbol : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidCallSymbol : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ;"
LLVM,RISCV,627,"Predict the next statement of this code snippet:
 <s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,628,"Predict the next statement of this code snippet:
 <s> Op -> VReg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> IsRV64 = IsRV64 ; return Op ;"
LLVM,RISCV,629,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createVTypeImm ( APInt sew , APInt lmul , APInt ediv , SMLoc S , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: VTypeImm ) ; sew . ashrInPlace ( <NUM_LIT> ) ; Op -> Vtypei . Sew = static_cast < VSEW > ( sew . logBase2 ( ) ) ; Op -> Vtypei . Lmul = static_cast < VLMUL > ( lmul . logBase2 ( ) ) ; Op -> Vtypei . Ediv = static_cast < VEDIV > ( ediv . logBase2 ( ) ) ; Op -> Vtypei . Encoding = ( ediv . logBase2 ( ) << <NUM_LIT> ) | ( sew . logBase2 ( ) << <NUM_LIT> ) | ( lmul . logBase2 ( ) ) ; Op -> StartLoc = S ; Op -> IsRV64 = IsRV64 ; return Op ;"
LLVM,RISCV,630,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }"
LLVM,RISCV,631,"Predict the next statement of this code snippet:
 <s> switch ( lmul ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,632,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,633,"Predict the next statement of this code snippet:
 <s> assert ( Kind == KindTy :: VTypeImm && <STR_LIT> ) ; Twine vtypei ( getSEW ( Vtypei . Sew ) ) ;"
LLVM,RISCV,634,"Predict the next statement of this code snippet:
 <s> assert ( Kind == KindTy :: VTypeImm && <STR_LIT> ) ; Twine vtypei ( getSEW ( Vtypei . Sew ) ) ; vtypei . concat ( Twine ( <STR_LIT> ) ) ; vtypei . concat ( Twine ( getLMUL ( Vtypei . Lmul ) ) ) ; vtypei . concat ( Twine ( <STR_LIT> ) ) ; vtypei . concat ( Twine ( getEDIV ( Vtypei . Ediv ) ) ) ; return vtypei . toStringRef ( Out ) ;"
LLVM,RISCV,635,"Predict the next statement of this code snippet:
 <s> bool isUImm7 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,636,"Predict the next statement of this code snippet:
 <s> bool isVectorRegister ( ) const { return Kind == KindTy :: VectorRegister ;"
LLVM,RISCV,637,"Predict the next statement of this code snippet:
 <s> return Kind == KindTy :: VTypeImm ;"
LLVM,RISCV,638,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: parseOperand ( OperandVector & Operands , StringRef Mnemonic ) { OperandMatchResultTy Result = MatchOperandParserImpl ( Operands , Mnemonic , true ) ; if ( Result == MatchOperand_Success ) return false ; if ( Result == MatchOperand_ParseFail ) return true ; if ( Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> ) { if ( parseRegisterV0asV0T ( Operands , true ) == MatchOperand_Success ) return false ; } if ( parseRegister ( Operands , true ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; }"
LLVM,RISCV,639,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: parseOperand ( OperandVector & Operands , StringRef Mnemonic ) { OperandMatchResultTy Result = MatchOperandParserImpl ( Operands , Mnemonic , true ) ; if ( Result == MatchOperand_Success ) return false ; if ( Result == MatchOperand_ParseFail ) return true ; if ( Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> ) { if ( parseRegisterV0asV0T ( Operands , true ) == MatchOperand_Success ) return false ; } if ( parseRegister ( Operands , true ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; } Error ( getLoc ( ) , <STR_LIT> ) ; return true ;"
LLVM,RISCV,640,"Predict the next statement of this code snippet:
 <s> default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; Register RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) RegNo = <STR_LIT> ; if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; }"
LLVM,RISCV,641,"Predict the next statement of this code snippet:
 <s> StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; Register RegNo = MatchRegisterName ( Name ) ; getLexer ( ) . Lex ( ) ;"
LLVM,RISCV,642,"Predict the next statement of this code snippet:
 <s> SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ;"
LLVM,RISCV,643,"Predict the next statement of this code snippet:
 <s> getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( Name . consume_front ( <STR_LIT> ) ) { lmul = APInt ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( lmul != <NUM_LIT> && lmul != <NUM_LIT> && lmul != <NUM_LIT> && lmul != <NUM_LIT> ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { Operands . push_back ( <ISA_LIT>Operand :: createVTypeImm ( sew , lmul , ediv , S , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( Name . consume_front ( <STR_LIT> ) ) { ediv = APInt ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( ediv != <NUM_LIT> && ediv != <NUM_LIT> && ediv != <NUM_LIT> && ediv != <NUM_LIT> ) return MatchOperand_NoMatch ;"
LLVM,RISCV,644,"Predict the next statement of this code snippet:
 <s> case KindTy :: Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case KindTy :: Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ;"
LLVM,RISCV,645,"Predict the next statement of this code snippet:
 <s> case KindTy :: VectorRegister : OS << <STR_LIT> << getVecReg ( ) << '>' ; break ; case KindTy :: VTypeImm : SmallVector < char , <NUM_LIT> > VTypeBuf ; OS << <STR_LIT> << getVTypeImm ( VTypeBuf ) << '>' ;"
LLVM,RISCV,646,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ; IsRV64 = o . IsRV64 ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case KindTy :: Register : Reg = o . Reg ; break ; case KindTy :: Immediate : Imm = o . Imm ; break ; case KindTy :: Token : Tok = o . Tok ; break ; case KindTy :: SystemRegister : SysReg = o . SysReg ; break ; case KindTy :: VectorRegister : VReg = o . VReg ; break ; case KindTy :: VTypeImm : Vtypei = o . Vtypei ; break ; }"
LLVM,RISCV,647,"Predict the next statement of this code snippet:
 <s> StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case KindTy :: Register : Reg = o . Reg ; break ; case KindTy :: Immediate : Imm = o . Imm ; break ; case KindTy :: Token : Tok = o . Tok ; break ; case KindTy :: SystemRegister : SysReg = o . SysReg ; break ; case KindTy :: VectorRegister :"
LLVM,RISCV,648,"Predict the next statement of this code snippet:
 <s> Op -> Imm . Val = Val ; Op -> StartLoc = S ;"
LLVM,RISCV,649,"Predict the next statement of this code snippet:
 <s> case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; break ; } case AsmToken :: Percent : return parseOperandWithModifier ( Operands ) ; } Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E ) ) ; return MatchOperand_Success ;"
LLVM,RISCV,650,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseOperandWithModifier ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Identifier = getParser ( ) . getTok ( ) . getIdentifier ( ) ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: getVariantKindForName ( Identifier ) ;"
LLVM,RISCV,651,"Predict the next statement of this code snippet:
 <s> if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) ) ) ; } return MatchOperand_Success ;"
LLVM,RISCV,652,"Predict the next statement of this code snippet:
 <s> case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; unsigned RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) { RegNo = MatchRegisterAltName ( Name ) ; if ( RegNo == <NUM_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( Buf [ <NUM_LIT> ] ) ; return MatchOperand_NoMatch ; } } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS ) ) ;"
LLVM,RISCV,653,"Predict the next statement of this code snippet:
 <s> case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm13Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm20LUI : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidUImm20AUIPC : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm21Lsb0JAL : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCSRSystemRegister : { return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidFRMArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidBareSymbol : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidPseudoJumpSymbol : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidCallSymbol : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidTPRelAddSymbol : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidVTypeI : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> <STR_LIT> ) ; } case Match_InvalidVMaskRegister : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ;"
LLVM,RISCV,654,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,655,"Predict the next statement of this code snippet:
 <s> bool IsInRange = isRV64 ( ) ? true : isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ; return IsConstantImm && IsInRange && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,656,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) return true ; bool IsInRange = isRV64 ( ) ? true : isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,657,"Predict the next statement of this code snippet:
 <s> static bool matchRegisterNameHelper ( bool IsRV32E , Register & RegNo , StringRef Name ) {"
LLVM,RISCV,658,"Predict the next statement of this code snippet:
 <s> if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; if ( IsRV32E && RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) RegNo = <NUM_LIT> ; return RegNo == <NUM_LIT> ;"
LLVM,RISCV,659,"Predict the next statement of this code snippet:
 <s> Register RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <NUM_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ;"
LLVM,RISCV,660,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; Register Reg = Op . getReg ( ) ; bool IsRegFPR32 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ;"
LLVM,RISCV,661,"Predict the next statement of this code snippet:
 <s> if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; Register Reg = Op . getReg ( ) ; bool IsRegFPR32 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR32C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR32 && Kind == MCK_FPR64 ) || ( IsRegFPR32C && Kind == MCK_FPR64C ) ) { Op . Reg . RegNum = convertFPR32ToFPR64 ( Reg ) ; return Match_Success ; } return Match_InvalidOperand ;"
LLVM,RISCV,662,"Predict the next statement of this code snippet:
 <s> SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ;"
LLVM,RISCV,663,"Predict the next statement of this code snippet:
 <s> SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ;"
LLVM,RISCV,664,"Predict the next statement of this code snippet:
 <s> } } switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; unsigned RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <NUM_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( Buf [ <NUM_LIT> ] ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) {"
LLVM,RISCV,665,"Predict the next statement of this code snippet:
 <s> unsigned RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <NUM_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( Buf [ <NUM_LIT> ] ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; }"
LLVM,RISCV,666,"Predict the next statement of this code snippet:
 <s> bool isImmXLen ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) ) return false ;"
LLVM,RISCV,667,"Predict the next statement of this code snippet:
 <s> bool isImmXLen ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,668,"Predict the next statement of this code snippet:
 <s> case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm13Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm20LUI : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidUImm20AUIPC : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm21Lsb0JAL : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCSRSystemRegister : { return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidFRMArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidBareSymbol : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ;"
LLVM,RISCV,669,"Predict the next statement of this code snippet:
 <s> if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) { getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } Res = V ; } else Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ;"
LLVM,RISCV,670,"Predict the next statement of this code snippet:
 <s> emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ;"
LLVM,RISCV,671,"Predict the next statement of this code snippet:
 <s> Sew . ashrInPlace ( <NUM_LIT> ) ; unsigned SewLog2 = Sew . logBase2 ( ) ; unsigned LmulLog2 = Lmul . logBase2 ( ) ; Op -> VType . Sew = static_cast < VSEW > ( SewLog2 ) ; if ( Fractional ) { unsigned Flmul = <NUM_LIT> - LmulLog2 ; Op -> VType . Lmul = static_cast < VLMUL > ( Flmul ) ;"
LLVM,RISCV,672,"Predict the next statement of this code snippet:
 <s> return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm13Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm20 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm21Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; }"
LLVM,RISCV,673,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,674,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,675,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,676,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,677,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,678,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,679,"Predict the next statement of this code snippet:
 <s> bool isUImm6 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,680,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,681,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid ;"
LLVM,RISCV,682,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMemOpBaseReg ( OperandVector & Operands ) { if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; }"
LLVM,RISCV,683,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy Result = MatchOperandParserImpl ( Operands , Mnemonic , true ) ; if ( Result == MatchOperand_Success ) return false ; if ( Result == MatchOperand_ParseFail ) return true ; if ( parseRegister ( Operands , true ) == MatchOperand_Success ) { if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; }"
LLVM,RISCV,684,"Predict the next statement of this code snippet:
 <s> return isImm ( <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,685,"Predict the next statement of this code snippet:
 <s> return isU32Imm ( ) ;"
LLVM,RISCV,686,"Predict the next statement of this code snippet:
 <s> return isU32Imm ( ) ;"
LLVM,RISCV,687,"Predict the next statement of this code snippet:
 <s> return isU32Imm ( ) ;"
LLVM,RISCV,688,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,689,"Predict the next statement of this code snippet:
 <s> } if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , FoundInteger ? <STR_LIT> : <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ;"
LLVM,RISCV,690,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,691,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,692,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,693,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ;"
LLVM,RISCV,694,"Predict the next statement of this code snippet:
 <s> bool isUImm8 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ;"
LLVM,RISCV,695,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createVType ( APInt Sew , APInt Lmul , SMLoc S , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: VType ) ;"
LLVM,RISCV,696,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,697,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }"
LLVM,RISCV,698,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,699,"Predict the next statement of this code snippet:
 <s> return MatchOperand_Success ; } if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ! Name . consume_front ( <STR_LIT> ) ) return MatchOperand_NoMatch ; APInt Lmul ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> ) return MatchOperand_NoMatch ;"
LLVM,RISCV,700,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: validateInstruction ( MCInst & Inst , OperandVector & Operands ) { const MCInstrDesc & MCID = MII . get ( Inst . getOpcode ( ) ) ; unsigned TargetFlags = ( MCID . TSFlags >> <STR_LIT> ) & <STR_LIT> ; if ( TargetFlags == <STR_LIT> ) return false ; unsigned DestReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; SMLoc Loc = Operands [ <NUM_LIT> ] -> getStartLoc ( ) ; if ( ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) ) { if ( TargetFlags != <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } if ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned Src1Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src1Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> || TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src1Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } }"
LLVM,RISCV,701,"Predict the next statement of this code snippet:
 <s> if ( ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) ) { if ( TargetFlags != <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } if ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned Src1Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src1Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> || TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src1Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { unsigned MaskReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == MaskReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } else if ( TargetFlags == <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( DestReg == Src2Reg + <NUM_LIT> ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } else if ( TargetFlags == <STR_LIT> || TargetFlags == <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { unsigned MaskReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,702,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,703,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,704,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isUInt < <NUM_LIT> > ( Imm ) && ( Imm & <NUM_LIT> ) == <NUM_LIT> ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,705,"Predict the next statement of this code snippet:
 <s> else IsValid = isUInt < <NUM_LIT> > ( Imm ) && ( Imm & <NUM_LIT> ) == <NUM_LIT> ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,706,"Predict the next statement of this code snippet:
 <s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMemOpBaseReg ( OperandVector & Operands ) { if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) {"
LLVM,RISCV,707,"Predict the next statement of this code snippet:
 <s> if ( Result == MatchOperand_Success ) return false ; if ( Result == MatchOperand_ParseFail ) return true ; if ( parseRegister ( Operands , true ) == MatchOperand_Success ) { if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; } return false ; }"
LLVM,RISCV,708,"Predict the next statement of this code snippet:
 <s> if ( IsConstant ) Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;"
LLVM,RISCV,709,"Predict the next statement of this code snippet:
 <s> unsigned Imm = <NUM_LIT> ; for ( char c : SE -> getSymbol ( ) . getName ( ) ) { switch ( c ) { default : llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ;"
LLVM,RISCV,710,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ;"
LLVM,RISCV,711,"Predict the next statement of this code snippet:
 <s> Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; Addend = <NUM_LIT> ; if ( const <ISA_LIT>MCExpr * RE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { Kind = RE -> getKind ( ) ; Expr = RE -> getSubExpr ( ) ; } if ( isa < MCConstantExpr > ( Expr ) || isa < MCSymbolRefExpr > ( Expr ) ) return true ; const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ; if ( ! BE ) return false ; if ( ! isa < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ) return false ; if ( BE -> getOpcode ( ) != MCBinaryExpr :: Add && BE -> getOpcode ( ) != MCBinaryExpr :: Sub ) return false ; if ( BE -> getOpcode ( ) == MCBinaryExpr :: Sub && isa < MCSymbolRefExpr > ( BE -> getRHS ( ) ) ) return true ; auto AddendExpr = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; if ( ! AddendExpr ) return false ; Addend = AddendExpr -> getValue ( ) ; if ( BE -> getOpcode ( ) == MCBinaryExpr :: Sub ) Addend = - Addend ; return Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid ;"
LLVM,RISCV,712,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createImm ( const MCExpr * Val , SMLoc S , SMLoc E , bool IsRV64 ) {"
LLVM,RISCV,713,"Predict the next statement of this code snippet:
 <s> auto Op = make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ;"
LLVM,RISCV,714,"Predict the next statement of this code snippet:
 <s> static std :: unique_ptr < <ISA_LIT>Operand > createSysReg ( StringRef Str , SMLoc S , unsigned Encoding , bool IsRV64 ) { auto Op = make_unique < <ISA_LIT>Operand > ( SystemRegister ) ; Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . Encoding = Encoding ;"
LLVM,RISCV,715,"Predict the next statement of this code snippet:
 <s> auto Op = make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ; Op -> StartLoc = S ; Op -> EndLoc = S ; Op -> IsRV64 = IsRV64 ;"
LLVM,RISCV,716,"Predict the next statement of this code snippet:
 <s> emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; } else { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ;"
LLVM,RISCV,717,"Predict the next statement of this code snippet:
 <s> MCContext & Ctx = getContext ( ) ; MCSymbol * TmpLabel = Ctx . createTempSymbol ( <STR_LIT> , true , false ) ; Out . EmitLabel ( TmpLabel ) ; MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const <ISA_LIT>MCExpr * Symbol = <ISA_LIT>MCExpr :: create ( Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( DestReg ) . addExpr ( Symbol ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( DestReg ) . addOperand ( DestReg ) . addExpr ( RefToLinkTmpLabel ) ) ;"
LLVM,RISCV,718,"Predict the next statement of this code snippet:
 <s> CInst . setLoc ( Inst . getLoc ( ) ) ; S . EmitInstruction ( ( Res ? CInst : Inst ) , getSTI ( ) ) ;"
LLVM,RISCV,719,"Predict the next statement of this code snippet:
 <s> bool Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ; CInst . setLoc ( Inst . getLoc ( ) ) ;"
LLVM,RISCV,720,"Predict the next statement of this code snippet:
 <s> assert ( Kind == Immediate && <STR_LIT> ) ; return Imm . Val ;"
LLVM,RISCV,721,"Predict the next statement of this code snippet:
 <s> unsigned getReg ( ) const override { assert ( Kind == Register && <STR_LIT> ) ; return Reg . RegNum ;"
LLVM,RISCV,722,"Predict the next statement of this code snippet:
 <s> StringRef getSysReg ( ) const { assert ( Kind == SystemRegister && <STR_LIT> ) ; return StringRef ( SysReg . Data , SysReg . Length ) ;"
LLVM,RISCV,723,"Predict the next statement of this code snippet:
 <s> StringRef getToken ( ) const {"
LLVM,RISCV,724,"Predict the next statement of this code snippet:
 <s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,725,"Predict the next statement of this code snippet:
 <s> bool isBareSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,726,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,727,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,728,"Predict the next statement of this code snippet:
 <s> StringRef Str = SVal -> getSymbol ( ) . getName ( ) ; char Prev = '\0' ; for ( char c : Str ) { if ( c != 'i' && c != 'o' && c != 'r' && c != 'w' ) return false ; if ( c <= Prev ) return false ; Prev = c ; }"
LLVM,RISCV,729,"Predict the next statement of this code snippet:
 <s> StringRef Str = SVal -> getSymbol ( ) . getName ( ) ; char Prev = '\0' ; for ( char c : Str ) { if ( c != 'i' && c != 'o' && c != 'r' && c != 'w' ) return false ; if ( c <= Prev ) return false ; Prev = c ;"
LLVM,RISCV,730,"Predict the next statement of this code snippet:
 <s> if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) return true ; bool IsInRange = isRV64 ( ) ? true : isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ; return IsConstantImm && IsInRange && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,731,"Predict the next statement of this code snippet:
 <s> bool isReg ( ) const override { return Kind == Register ;"
LLVM,RISCV,732,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && ( Imm != <NUM_LIT> ) && isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,733,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ;"
LLVM,RISCV,734,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,735,"Predict the next statement of this code snippet:
 <s> int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,736,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,737,"Predict the next statement of this code snippet:
 <s> bool isToken ( ) const override {"
LLVM,RISCV,738,"Predict the next statement of this code snippet:
 <s> return Kind == Token ;"
LLVM,RISCV,739,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ;"
LLVM,RISCV,740,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) {"
LLVM,RISCV,741,"Predict the next statement of this code snippet:
 <s> bool isUImm20LUI ( ) const { <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ;"
LLVM,RISCV,742,"Predict the next statement of this code snippet:
 <s> bool isUImm5NonZero ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ;"
LLVM,RISCV,743,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,744,"Predict the next statement of this code snippet:
 <s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,745,"Predict the next statement of this code snippet:
 <s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,746,"Predict the next statement of this code snippet:
 <s> if ( ! isImm ( ) ) return false ;"
LLVM,RISCV,747,"Predict the next statement of this code snippet:
 <s> return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,748,"Predict the next statement of this code snippet:
 <s> if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; if ( Imm == <NUM_LIT> ) return false ; return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,749,"Predict the next statement of this code snippet:
 <s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>32Target ( ) ) ;"
LLVM,RISCV,750,"Predict the next statement of this code snippet:
 <s> if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success ;"
LLVM,RISCV,751,"Predict the next statement of this code snippet:
 <s> StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ;"
LLVM,RISCV,752,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) {"
LLVM,RISCV,753,"Predict the next statement of this code snippet:
 <s> StringRef IDVal = DirectiveID . getString ( ) ;"
LLVM,RISCV,754,"Predict the next statement of this code snippet:
 <s> Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; if ( popFeatureBits ( ) ) return Error ( StartLoc , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionRVC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRVC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionRelax ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRelax ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } Warning ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ;"
LLVM,RISCV,755,"Predict the next statement of this code snippet:
 <s> SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Percent : return parseOperandWithModifier ( Operands ) ;"
LLVM,RISCV,756,"Predict the next statement of this code snippet:
 <s> MAB . setForceRelocs ( ) ; } } Operands . push_back ( <ISA_LIT>Operand :: createToken ( Name , NameLoc , isRV64 ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( parseOperand ( Operands , Name ) ) return true ; unsigned OperandIdx = <NUM_LIT> ;"
LLVM,RISCV,757,"Predict the next statement of this code snippet:
 <s> } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ; if ( getParser ( ) . parseParenExpression ( SubExpr , E ) ) { return MatchOperand_ParseFail ; } const MCExpr * ModExpr = <ISA_LIT>MCExpr :: create ( SubExpr , VK , getContext ( ) ) ;"
LLVM,RISCV,758,"Predict the next statement of this code snippet:
 <s> StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; unsigned RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) { RegNo = MatchRegisterAltName ( Name ) ; if ( RegNo == <NUM_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( Buf [ <NUM_LIT> ] ) ; return MatchOperand_NoMatch ; } } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ;"
LLVM,RISCV,759,"Predict the next statement of this code snippet:
 <s> if ( FeatureBitStack . empty ( ) ) return true ; FeatureBitset FeatureBits = FeatureBitStack . pop_back_val ( ) ; copySTI ( ) . setFeatureBits ( FeatureBits ) ;"
LLVM,RISCV,760,"Predict the next statement of this code snippet:
 <s> case Immediate : OS << * getImm ( ) ; break ; case Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ;"
LLVM,RISCV,761,"Predict the next statement of this code snippet:
 <s> case Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case SystemRegister : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; }"
LLVM,RISCV,762,"Predict the next statement of this code snippet:
 <s> unsigned Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCOperand & Op1 = Inst . getOperand ( <NUM_LIT> ) ; if ( Op1 . isExpr ( ) ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addExpr ( Op1 . getExpr ( ) ) ) ; return false ;"
LLVM,RISCV,763,"Predict the next statement of this code snippet:
 <s> Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,764,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) {"
LLVM,RISCV,765,"Predict the next statement of this code snippet:
 <s> Imm = o . Imm ; break ; case Token : Tok = o . Tok ; break ; case SystemRegister : SysReg = o . SysReg ; break ;"
LLVM,RISCV,766,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; unsigned Reg = Op . getReg ( ) ; bool IsRegFPR32 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR32C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR32 && Kind == MCK_FPR64 ) || ( IsRegFPR32C && Kind == MCK_FPR64C ) ) { Op . Reg . RegNum = convertFPR32ToFPR64 ( Reg ) ; return Match_Success ; }"
LLVM,RISCV,767,"Predict the next statement of this code snippet:
 <s> const DataLayout TD = getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; OutStreamer -> EmitSymbolValue ( Stubs [ i ] . second . getPointer ( ) , TD . getPointerSize ( <NUM_LIT> ) , <NUM_LIT> ) ; } Stubs . clear ( ) ; }"
LLVM,RISCV,768,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) {"
LLVM,RISCV,769,"Predict the next statement of this code snippet:
 <s> Lower . lower ( MI , LoweredMI ) ;"
LLVM,RISCV,770,"Predict the next statement of this code snippet:
 <s> const MCExpr * Expr = MCSymbolRefExpr :: create ( getSymbol ( RVCPV -> getGlobalValue ( ) ) , getModifierVariantKind ( RVCPV -> getModifier ( ) ) , OutContext ) ; uint64_t Size = getDataLayout ( ) . getTypeAllocSize ( RVCPV -> getType ( ) ) ; OutStreamer -> EmitValue ( Expr , Size ) ;"
LLVM,RISCV,771,"Predict the next statement of this code snippet:
 <s> static MCSymbolRefExpr :: VariantKind getModifierVariantKind ( <STR_LIT> Modifier ) { switch ( Modifier ) { case <STR_LIT> : return MCSymbolRefExpr :: VK_NTPOFF ; }"
LLVM,RISCV,772,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( The<ISA_LIT>Target ) ;"
LLVM,RISCV,773,"Predict the next statement of this code snippet:
 <s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( The<ISA_LIT>Target ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > B ( The<ISA_LIT>64Target ) ;"
LLVM,RISCV,774,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { <ISA_LIT>InstPrinter :: printAddress ( MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) , OS ) ; return false ;"
LLVM,RISCV,775,"Predict the next statement of this code snippet:
 <s> OS << '%' << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( opNum ) . getReg ( ) ) ;"
LLVM,RISCV,776,"Predict the next statement of this code snippet:
 <s> OS << '%' << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( opNum ) . getReg ( ) ) ; OS << <STR_LIT> ;"
LLVM,RISCV,777,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : case MachineOperand :: MO_Immediate : {"
LLVM,RISCV,778,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : case MachineOperand :: MO_Immediate : { <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MC ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; <ISA_LIT>InstPrinter :: printOperand ( MC , O ) ; break ; } case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,RISCV,779,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;"
LLVM,RISCV,780,"Predict the next statement of this code snippet:
 <s> if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ;"
LLVM,RISCV,781,"Predict the next statement of this code snippet:
 <s> Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ;"
LLVM,RISCV,782,"Predict the next statement of this code snippet:
 <s> if ( Res ) ++ <ISA_LIT>NumInstrsCompressed ;"
LLVM,RISCV,783,"Predict the next statement of this code snippet:
 <s> bool Res = compressInst ( CInst , Inst , * TM . getMCSubtargetInfo ( ) , OutStreamer -> getContext ( ) ) ; if ( Res ) ++ <ISA_LIT>NumInstrsCompressed ;"
LLVM,RISCV,784,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {"
LLVM,RISCV,785,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {"
LLVM,RISCV,786,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ;"
LLVM,RISCV,787,"Predict the next statement of this code snippet:
 <s> bool Res = compressInst ( CInst , Inst , * TM . getMCSubtargetInfo ( ) , OutStreamer -> getContext ( ) ) ; AsmPrinter :: EmitToStreamer ( * OutStreamer , Res ? CInst : Inst ) ;"
LLVM,RISCV,788,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) { MCInst CInst ; bool Res = compressInst ( CInst , Inst , * TM . getMCSubtargetInfo ( ) , OutStreamer -> getContext ( ) ) ;"
LLVM,RISCV,789,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>64Target ( ) ) ;"
LLVM,RISCV,790,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ;"
LLVM,RISCV,791,"Predict the next statement of this code snippet:
 <s> if ( AsmVariant != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ;"
LLVM,RISCV,792,"Predict the next statement of this code snippet:
 <s> if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ! MO . isReg ( ) ) return true ;"
LLVM,RISCV,793,"Predict the next statement of this code snippet:
 <s> if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , OS ) ) return false ; if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; default :"
LLVM,RISCV,794,"Predict the next statement of this code snippet:
 <s> case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; default : break ; }"
LLVM,RISCV,795,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitAttributes ( ) { <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; RTS . emitTargetAttributes ( * STI ) ;"
LLVM,RISCV,796,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ;"
LLVM,RISCV,797,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = TM . getTargetCPU ( ) ;"
LLVM,RISCV,798,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( ) ) ; break ; default :"
LLVM,RISCV,799,"Predict the next statement of this code snippet:
 <s> if ( MO . isImm ( ) && MO . getImm ( ) == <NUM_LIT> ) { OS << <ISA_LIT>InstPrinter :: getRegisterName ( <STR_LIT> ) ; return false ; } break ; case 'i' : if ( ! MO . isReg ( ) ) OS << 'i' ; return false ; } } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; default : break ; } return true ;"
LLVM,RISCV,800,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ;"
LLVM,RISCV,801,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetMachine & RTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , CPU , FS , <STR_LIT> , RTM ) ;"
LLVM,RISCV,802,"Predict the next statement of this code snippet:
 <s> auto * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( RVFI -> isHwlpBasicBlock ( & MBB ) ) { RTS . emitDirectiveOptionPop ( ) ; }"
LLVM,RISCV,803,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ;"
LLVM,RISCV,804,"Predict the next statement of this code snippet:
 <s> AsmPrinter :: emitBasicBlockStart ( MBB ) ; auto * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( RVFI -> isHwlpBasicBlock ( & MBB ) ) { RTS . emitDirectiveOptionPush ( ) ; RTS . emitDirectiveOptionNoRVC ( ) ; }"
LLVM,RISCV,805,"Predict the next statement of this code snippet:
 <s> auto * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( RVFI -> isHwlpBasicBlock ( & MBB ) ) {"
LLVM,RISCV,806,"Predict the next statement of this code snippet:
 <s> auto * RVFI = MI -> getMF ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;"
LLVM,RISCV,807,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , STI ( TM . getMCSubtargetInfo ( ) ) {"
LLVM,RISCV,808,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , STI ( TM . getMCSubtargetInfo ( ) ) {"
LLVM,RISCV,809,"Predict the next statement of this code snippet:
 <s> NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; STI = & NewSTI ; SetupMachineFunction ( MF ) ; emitFunctionBody ( ) ; return false ;"
LLVM,RISCV,810,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) {"
LLVM,RISCV,811,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) return false ; if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate :"
LLVM,RISCV,812,"Predict the next statement of this code snippet:
 <s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , * this ) ;"
LLVM,RISCV,813,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitAttributes ( ) { <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; RTS . emitTargetAttributes ( * MCSTI ) ;"
LLVM,RISCV,814,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitAttributes ( ) { <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; RTS . emitTargetAttributes ( * MCSTI ) ;"
LLVM,RISCV,815,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitEndOfAsmFile ( Module & M ) { <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ;"
LLVM,RISCV,816,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ;"
LLVM,RISCV,817,"Predict the next statement of this code snippet:
 <s> AsmPrinter :: emitFunctionEntryLabel ( ) ;"
LLVM,RISCV,818,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; RTS . setTargetABI ( STI -> getTargetABI ( ) ) ;"
LLVM,RISCV,819,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ;"
LLVM,RISCV,820,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ;"
LLVM,RISCV,821,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) { MCInst CInst ; bool Res = compressInst ( CInst , Inst , * STI , OutStreamer -> getContext ( ) ) ;"
LLVM,RISCV,822,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) {"
LLVM,RISCV,823,"Predict the next statement of this code snippet:
 <s> const char * getPassName ( ) const override { return <STR_LIT> ;"
LLVM,RISCV,824,"Predict the next statement of this code snippet:
 <s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ;"
LLVM,RISCV,825,"Predict the next statement of this code snippet:
 <s> if ( ! MO . isReg ( ) ) OS << 'i' ; return false ; } } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; case MachineOperand :: MO_GlobalAddress :"
LLVM,RISCV,826,"Predict the next statement of this code snippet:
 <s> case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , OS ) ; return false ; case MachineOperand :: MO_BlockAddress : { MCSymbol * Sym = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Sym -> print ( OS , MAI ) ; return false ; }"
LLVM,RISCV,827,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCSTI ( TM . getMCSubtargetInfo ( ) ) {"
LLVM,RISCV,828,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCSTI ( TM . getMCSubtargetInfo ( ) ) {"
LLVM,RISCV,829,"Predict the next statement of this code snippet:
 <s> MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; MCSTI = & NewSTI ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SetupMachineFunction ( MF ) ; emitFunctionBody ( ) ;"
LLVM,RISCV,830,"Predict the next statement of this code snippet:
 <s> if ( isRV32Only && ActiveFeatures [ <STR_LIT> ] ) return false ; if ( FeaturesRequired . none ( ) ) return true ;"
LLVM,RISCV,831,"Predict the next statement of this code snippet:
 <s> TargetABI = ABI_Unknown ; } else if ( ( ABIName . startswith ( <STR_LIT> ) || ABIName . startswith ( <STR_LIT> ) ) && ! IsRV64 ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ( ABIName . startswith ( <STR_LIT> ) || ABIName . startswith ( <STR_LIT> ) ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_IL32PC64E && TargetABI != ABI_Unknown ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } if ( TargetABI != ABI_Unknown ) return TargetABI ; if ( IsRV32E ) return ABI_ILP32E ;"
LLVM,RISCV,832,"Predict the next statement of this code snippet:
 <s> TargetABI = ABI_Unknown ; } else if ( ( ABIName . startswith ( <STR_LIT> ) || ABIName . startswith ( <STR_LIT> ) ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_IL32PC64E && TargetABI != ABI_Unknown ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } if ( TargetABI != ABI_Unknown ) return TargetABI ; if ( IsRV32E ) return ABI_ILP32E ; if ( IsRV64 ) return ABI_LP64 ; return ABI_ILP32 ;"
LLVM,RISCV,833,"Predict the next statement of this code snippet:
 <s> return std :: make_pair ( <NUM_LIT> << static_cast < unsigned > ( VLMUL ) , false ) ; case <STR_LIT> :: LMUL_F2 : case <STR_LIT> :: LMUL_F4 : case <STR_LIT> :: LMUL_F8 :"
LLVM,RISCV,834,"Predict the next statement of this code snippet:
 <s> inline static unsigned encodeSEW ( unsigned SEW ) {"
LLVM,RISCV,835,"Predict the next statement of this code snippet:
 <s> assert ( isValidSEW ( SEW ) && <STR_LIT> ) ;"
LLVM,RISCV,836,"Predict the next statement of this code snippet:
 <s> assert ( isValidSEW ( SEW ) && <STR_LIT> ) ; unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ; unsigned VSEWBits = Log2_32 ( SEW ) - <NUM_LIT> ;"
LLVM,RISCV,837,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>VType :: encodeVTYPE ( <STR_LIT> VLMUL , unsigned SEW , bool TailAgnostic , bool MaskAgnostic ) {"
LLVM,RISCV,838,"Predict the next statement of this code snippet:
 <s> return isCheriPureCapABI ( TargetABI ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,839,"Predict the next statement of this code snippet:
 <s> static inline VConstraintType getConstraint ( uint64_t TSFlags ) {"
LLVM,RISCV,840,"Predict the next statement of this code snippet:
 <s> static inline VConstraintType getConstraint ( uint64_t TSFlags ) {"
LLVM,RISCV,841,"Predict the next statement of this code snippet:
 <s> auto TargetABI = StringSwitch < ABI > ( ABIName ) . Case ( <STR_LIT> , ABI_ILP32 ) . Case ( <STR_LIT> , ABI_ILP32F ) . Case ( <STR_LIT> , ABI_ILP32D ) . Case ( <STR_LIT> , ABI_ILP32E ) . Case ( <STR_LIT> , ABI_IL32PC64 ) . Case ( <STR_LIT> , ABI_IL32PC64F ) . Case ( <STR_LIT> , ABI_IL32PC64D ) . Case ( <STR_LIT> , ABI_IL32PC64E ) . Case ( <STR_LIT> , ABI_LP64 ) . Case ( <STR_LIT> , ABI_LP64F ) . Case ( <STR_LIT> , ABI_LP64D ) . Case ( <STR_LIT> , ABI_L64PC128 ) . Case ( <STR_LIT> , ABI_L64PC128F ) . Case ( <STR_LIT> , ABI_L64PC128D ) . Default ( ABI_Unknown ) ;"
LLVM,RISCV,842,"Predict the next statement of this code snippet:
 <s> return TSFlags & IsRVVWideningReductionMask ;"
LLVM,RISCV,843,"Predict the next statement of this code snippet:
 <s> static inline bool isRVVWideningReduction ( uint64_t TSFlags ) {"
LLVM,RISCV,844,"Predict the next statement of this code snippet:
 <s> if ( Fractional ) OS << <STR_LIT> ; else OS << <STR_LIT> ; OS << LMul ; if ( isTailAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ;"
LLVM,RISCV,845,"Predict the next statement of this code snippet:
 <s> static inline bool UsesMaskPolicy ( uint64_t TSFlags ) { return TSFlags & UsesMaskPolicyMask ;"
LLVM,RISCV,846,"Predict the next statement of this code snippet:
 <s> if ( TT . isArch64Bit ( ) && ! FeatureBits [ <STR_LIT> ] ) report_fatal_error ( <STR_LIT> ) ;"
LLVM,RISCV,847,"Predict the next statement of this code snippet:
 <s> return static_cast < <STR_LIT> > ( Fractional ? <NUM_LIT> - LmulLog2 : LmulLog2 ) ;"
LLVM,RISCV,848,"Predict the next statement of this code snippet:
 <s> unsigned LMul = <NUM_LIT> << ( <NUM_LIT> - static_cast < unsigned > ( VLMUL ) ) ; OS << <STR_LIT> << LMul ; break ; } } if ( isTailAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; if ( isMaskAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ;"
LLVM,RISCV,849,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> << Sew ; switch ( VLMUL ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned LMul = <NUM_LIT> << static_cast < unsigned > ( VLMUL ) ; OS << <STR_LIT> << LMul ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned LMul = <NUM_LIT> << ( <NUM_LIT> - static_cast < unsigned > ( VLMUL ) ) ; OS << <STR_LIT> << LMul ; break ; } } if ( isTailAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ;"
LLVM,RISCV,850,"Predict the next statement of this code snippet:
 <s> errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown ) { errs ( ) << <STR_LIT> ; TargetABI = ABI_Unknown ;"
LLVM,RISCV,851,"Predict the next statement of this code snippet:
 <s> inline static unsigned encodeVTYPE ( <ISA_LIT>VLMUL VLMUL , <ISA_LIT>VSEW VSEW , bool TailAgnostic , bool MaskAgnostic ) { unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ; unsigned VSEWBits = static_cast < unsigned > ( VSEW ) ; unsigned VTypeI = ( ( VLMULBits & <NUM_LIT> ) << <NUM_LIT> ) | ( VSEWBits << <NUM_LIT> ) | ( VLMULBits & <NUM_LIT> ) ;"
LLVM,RISCV,852,"Predict the next statement of this code snippet:
 <s> return static_cast < int8_t > ( MergeOpIndex ) ;"
LLVM,RISCV,853,"Predict the next statement of this code snippet:
 <s> int getSEWIndex ( ) const {"
LLVM,RISCV,854,"Predict the next statement of this code snippet:
 <s> int getSEWIndex ( ) const { return static_cast < int8_t > ( SEWIndex ) ;"
LLVM,RISCV,855,"Predict the next statement of this code snippet:
 <s> return static_cast < int8_t > ( VLIndex ) ;"
LLVM,RISCV,856,"Predict the next statement of this code snippet:
 <s> int getVLIndex ( ) const {"
LLVM,RISCV,857,"Predict the next statement of this code snippet:
 <s> unsigned VLMUL = ( VType & <NUM_LIT> ) | ( ( VType & <NUM_LIT> ) >> <NUM_LIT> ) ;"
LLVM,RISCV,858,"Predict the next statement of this code snippet:
 <s> unsigned VLMUL = ( VType & <NUM_LIT> ) | ( ( VType & <NUM_LIT> ) >> <NUM_LIT> ) ;"
LLVM,RISCV,859,"Predict the next statement of this code snippet:
 <s> return static_cast < <ISA_LIT>VSEW > ( VSEW ) ;"
LLVM,RISCV,860,"Predict the next statement of this code snippet:
 <s> unsigned VSEW = ( VType >> <NUM_LIT> ) & <NUM_LIT> ;"
LLVM,RISCV,861,"Predict the next statement of this code snippet:
 <s> bool hasDummyMask ( ) const { return HasDummyMask ;"
LLVM,RISCV,862,"Predict the next statement of this code snippet:
 <s> unsigned Offset = <NUM_LIT> ;"
LLVM,RISCV,863,"Predict the next statement of this code snippet:
 <s> assert ( hasSEWOp ( TSFlags ) ) ; unsigned Offset = <NUM_LIT> ; if ( hasVecPolicyOp ( TSFlags ) ) Offset = <NUM_LIT> ;"
LLVM,RISCV,864,"Predict the next statement of this code snippet:
 <s> assert ( hasSEWOp ( TSFlags ) && hasVLOp ( TSFlags ) ) ;"
LLVM,RISCV,865,"Predict the next statement of this code snippet:
 <s> assert ( hasSEWOp ( TSFlags ) && hasVLOp ( TSFlags ) ) ; unsigned Offset = <NUM_LIT> ; if ( hasVecPolicyOp ( TSFlags ) ) Offset = <NUM_LIT> ; return Desc . getNumOperands ( ) - Offset ;"
LLVM,RISCV,866,"Predict the next statement of this code snippet:
 <s> static inline bool usesMaskPolicy ( uint64_t TSFlags ) { return TSFlags & UsesMaskPolicyMask ;"
LLVM,RISCV,867,"Predict the next statement of this code snippet:
 <s> return TSFlags & UsesMaskPolicyMask ;"
LLVM,RISCV,868,"Predict the next statement of this code snippet:
 <s> Register getBPReg ( ) { return <STR_LIT> ;"
LLVM,RISCV,869,"Predict the next statement of this code snippet:
 <s> Register getSCSPReg ( ) {"
LLVM,RISCV,870,"Predict the next statement of this code snippet:
 <s> case ABI_LP64D : return false ; case ABI_IL32PC64 : case ABI_IL32PC64F : case ABI_IL32PC64D : case ABI_IL32PC64E : case ABI_L64PC128 : case ABI_L64PC128F : case ABI_L64PC128D : return true ;"
LLVM,RISCV,871,"Predict the next statement of this code snippet:
 <s> unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ; unsigned VSEWBits = static_cast < unsigned > ( VSEW ) ; unsigned VTypeI = ( VSEWBits << <NUM_LIT> ) | ( VLMULBits & <NUM_LIT> ) ; if ( TailAgnostic ) VTypeI |= <NUM_LIT> ; if ( MaskAgnostic ) VTypeI |= <NUM_LIT> ; return VTypeI ;"
LLVM,RISCV,872,"Predict the next statement of this code snippet:
 <s> return static_cast < <ISA_LIT>VLMUL > ( VLMUL ) ;"
LLVM,RISCV,873,"Predict the next statement of this code snippet:
 <s> unsigned VLMUL = VType & <NUM_LIT> ;"
LLVM,RISCV,874,"Predict the next statement of this code snippet:
 <s> unsigned VSEW = ( VType >> <NUM_LIT> ) & <NUM_LIT> ; return static_cast < <ISA_LIT>VSEW > ( VSEW ) ;"
LLVM,RISCV,875,"Predict the next statement of this code snippet:
 <s> errs ( ) << <STR_LIT> << ABIName << <STR_LIT> ; } else if ( ABIName . startswith ( <STR_LIT> ) && IsRV64 ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . startswith ( <STR_LIT> ) && ! IsRV64 ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ;"
LLVM,RISCV,876,"Predict the next statement of this code snippet:
 <s> errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ;"
LLVM,RISCV,877,"Predict the next statement of this code snippet:
 <s> return WritesElement0 ;"
LLVM,RISCV,878,"Predict the next statement of this code snippet:
 <s> bool writesElement0 ( ) const {"
LLVM,RISCV,879,"Predict the next statement of this code snippet:
 <s> void toFeatureVector ( std :: vector < std :: string > & FeatureVector , const FeatureBitset & FeatureBits ) { for ( auto Feature : <ISA_LIT>FeatureKV ) { if ( FeatureBits [ Feature . Value ] && llvm :: <STR_LIT> ( Feature . Key ) ) FeatureVector . push_back ( std :: string ( <STR_LIT> ) + Feature . Key ) ; }"
LLVM,RISCV,880,"Predict the next statement of this code snippet:
 <s> void toFeatureVector ( std :: vector < std :: string > & FeatureVector , const FeatureBitset & FeatureBits ) { for ( auto Feature : <ISA_LIT>FeatureKV ) { if ( FeatureBits [ Feature . Value ] && llvm :: <STR_LIT> ( Feature . Key ) ) FeatureVector . push_back ( std :: string ( <STR_LIT> ) + Feature . Key ) ;"
LLVM,RISCV,881,"Predict the next statement of this code snippet:
 <s> bool IsRV64 = TT . isArch64Bit ( ) ; bool IsRV32E = FeatureBits [ <STR_LIT> ] ; if ( ! ABIName . empty ( ) && TargetABI == ABI_Unknown ) { errs ( ) << <STR_LIT> << ABIName << <STR_LIT> ; } else if ( ABIName . startswith ( <STR_LIT> ) && IsRV64 ) {"
LLVM,RISCV,882,"Predict the next statement of this code snippet:
 <s> assert ( isValidSEW ( SEW ) && <STR_LIT> ) ; unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ; unsigned VSEWBits = encodeSEW ( SEW ) ; unsigned VTypeI = ( VSEWBits << <NUM_LIT> ) | ( VLMULBits & <NUM_LIT> ) ; if ( TailAgnostic ) VTypeI |= <NUM_LIT> ;"
LLVM,RISCV,883,"Predict the next statement of this code snippet:
 <s> unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ; unsigned VSEWBits = encodeSEW ( SEW ) ; unsigned VTypeI = ( VSEWBits << <NUM_LIT> ) | ( VLMULBits & <NUM_LIT> ) ; if ( TailAgnostic ) VTypeI |= <NUM_LIT> ;"
LLVM,RISCV,884,"Predict the next statement of this code snippet:
 <s> unsigned XLen = IsRV64 ? <NUM_LIT> : <NUM_LIT> ; std :: vector < std :: string > FeatureVector ; for ( auto Feature : <ISA_LIT>FeatureKV ) { if ( FeatureBits [ Feature . Value ] && llvm :: <STR_LIT> ( Feature . Key ) ) FeatureVector . push_back ( std :: string ( <STR_LIT> ) + Feature . Key ) ; }"
LLVM,RISCV,885,"Predict the next statement of this code snippet:
 <s> switch ( VLMUL ) { case <STR_LIT> :: LMUL_RESERVED : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :: LMUL_1 : case <STR_LIT> :: LMUL_2 : case <STR_LIT> :: LMUL_4 : case <STR_LIT> :: LMUL_8 : { unsigned LMul = <NUM_LIT> << static_cast < unsigned > ( VLMUL ) ; OS << <STR_LIT> << LMul ; break ; } case <STR_LIT> :: LMUL_F2 : case <STR_LIT> :: LMUL_F4 : case <STR_LIT> :: LMUL_F8 : { unsigned LMul = <NUM_LIT> << ( <NUM_LIT> - static_cast < unsigned > ( VLMUL ) ) ; OS << <STR_LIT> << LMul ; break ; } } if ( isTailAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; if ( isMaskAgnostic ( VType ) ) OS << <STR_LIT> ;"
LLVM,RISCV,886,"Predict the next statement of this code snippet:
 <s> unsigned Sew = <NUM_LIT> << ( static_cast < unsigned > ( VSEW ) + <NUM_LIT> ) ; OS << <STR_LIT> << Sew ; switch ( VLMUL ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned LMul = <NUM_LIT> << static_cast < unsigned > ( VLMUL ) ; OS << <STR_LIT> << LMul ; break ;"
LLVM,RISCV,887,"Predict the next statement of this code snippet:
 <s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned LMul = <NUM_LIT> << ( <NUM_LIT> - static_cast < unsigned > ( VLMUL ) ) ; OS << <STR_LIT> << LMul ; break ; } } if ( isTailAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; if ( isMaskAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ;"
LLVM,RISCV,888,"Predict the next statement of this code snippet:
 <s> } else if ( ABIName . startswith ( <STR_LIT> ) && ! IsRV64 ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown ) { errs ( ) << <STR_LIT> ; TargetABI = ABI_Unknown ; } if ( TargetABI != ABI_Unknown ) return TargetABI ; if ( IsRV32E ) return ABI_ILP32E ;"
LLVM,RISCV,889,"Predict the next statement of this code snippet:
 <s> ABI computeTargetABI ( const Triple & TT , FeatureBitset FeatureBits , StringRef ABIName ) { auto TargetABI = getTargetABI ( ABIName ) ; bool IsRV64 = TT . isArch64Bit ( ) ; bool IsRV32E = FeatureBits [ <STR_LIT> ] ; if ( ! ABIName . empty ( ) && TargetABI == ABI_Unknown ) { errs ( ) << <STR_LIT> << ABIName << <STR_LIT> ; } else if ( ABIName . startswith ( <STR_LIT> ) && IsRV64 ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . startswith ( <STR_LIT> ) && ! IsRV64 ) {"
LLVM,RISCV,890,"Predict the next statement of this code snippet:
 <s> inline static unsigned decodeVSEW ( unsigned VSEW ) { assert ( VSEW < <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,891,"Predict the next statement of this code snippet:
 <s> return TSFlags & ForceTailAgnosticMask ;"
LLVM,RISCV,892,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,RISCV,893,"Predict the next statement of this code snippet:
 <s> MCRegister getBPReg ( ) {"
LLVM,RISCV,894,"Predict the next statement of this code snippet:
 <s> return ( TSFlags & InstFormatMask ) >> InstFormatShift ;"
LLVM,RISCV,895,"Predict the next statement of this code snippet:
 <s> static inline unsigned getFormat ( uint64_t TSFlags ) { return ( TSFlags & InstFormatMask ) >> InstFormatShift ;"
LLVM,RISCV,896,"Predict the next statement of this code snippet:
 <s> MCRegister getSCSPReg ( ) {"
LLVM,RISCV,897,"Predict the next statement of this code snippet:
 <s> unsigned VSEW = ( VType >> <NUM_LIT> ) & <NUM_LIT> ; return decodeVSEW ( VSEW ) ;"
LLVM,RISCV,898,"Predict the next statement of this code snippet:
 <s> return static_cast < <STR_LIT> > ( VLMUL ) ;"
LLVM,RISCV,899,"Predict the next statement of this code snippet:
 <s> inline static <STR_LIT> getVLMUL ( unsigned VType ) {"
LLVM,RISCV,900,"Predict the next statement of this code snippet:
 <s> return TSFlags & HasDummyMaskOpMask ;"
LLVM,RISCV,901,"Predict the next statement of this code snippet:
 <s> static inline bool hasDummyMaskOp ( uint64_t TSFlags ) { return TSFlags & HasDummyMaskOpMask ;"
LLVM,RISCV,902,"Predict the next statement of this code snippet:
 <s> static inline bool hasMergeOp ( uint64_t TSFlags ) { return TSFlags & HasMergeOpMask ;"
LLVM,RISCV,903,"Predict the next statement of this code snippet:
 <s> return TSFlags & HasSEWOpMask ;"
LLVM,RISCV,904,"Predict the next statement of this code snippet:
 <s> static inline bool hasVecPolicyOp ( uint64_t TSFlags ) {"
LLVM,RISCV,905,"Predict the next statement of this code snippet:
 <s> static inline bool hasVLOp ( uint64_t TSFlags ) { return TSFlags & HasVLOpMask ;"
LLVM,RISCV,906,"Predict the next statement of this code snippet:
 <s> return TSFlags & HasVLOpMask ;"
LLVM,RISCV,907,"Predict the next statement of this code snippet:
 <s> bool haveRequiredFeatures ( const FeatureBitset & ActiveFeatures ) const { if ( isRV32Only && ActiveFeatures [ <STR_LIT> ] ) return false ; if ( FeaturesRequired . none ( ) ) return true ; return ( FeaturesRequired & ActiveFeatures ) == FeaturesRequired ;"
LLVM,RISCV,908,"Predict the next statement of this code snippet:
 <s> inline static bool isMaskAgnostic ( unsigned VType ) {"
LLVM,RISCV,909,"Predict the next statement of this code snippet:
 <s> return VType & <NUM_LIT> ;"
LLVM,RISCV,910,"Predict the next statement of this code snippet:
 <s> return VType & <NUM_LIT> ;"
LLVM,RISCV,911,"Predict the next statement of this code snippet:
 <s> return isPowerOf2_32 ( SEW ) && SEW >= <NUM_LIT> && SEW <= <NUM_LIT> ;"
LLVM,RISCV,912,"Predict the next statement of this code snippet:
 <s> inline static bool isValidSEW ( unsigned SEW ) { return isPowerOf2_32 ( SEW ) && SEW >= <NUM_LIT> && SEW <= <NUM_LIT> ;"
LLVM,RISCV,913,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,914,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }"
LLVM,RISCV,915,"Predict the next statement of this code snippet:
 <s> inline static RoundingMode stringToRoundingMode ( StringRef Str ) {"
LLVM,RISCV,916,"Predict the next statement of this code snippet:
 <s> inline static RoundingMode stringToRoundingMode ( StringRef Str ) { return StringSwitch < RoundingMode > ( Str ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;"
LLVM,RISCV,917,"Predict the next statement of this code snippet:
 <s> if ( TT . isArch64Bit ( ) && FeatureBits [ <STR_LIT> ] ) report_fatal_error ( <STR_LIT> ) ;"
LLVM,RISCV,918,"Predict the next statement of this code snippet:
 <s> void validate ( const Triple & TT , const FeatureBitset & FeatureBits ) {"
LLVM,RISCV,919,"Predict the next statement of this code snippet:
 <s> bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * Dest = <NUM_LIT> ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const MachineOperand * DestOp ; if ( ! TII -> isBranch ( I , Cond , DestOp ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * FBB = <NUM_LIT> ; Cond . clear ( ) ; if ( TII -> AnalyzeBranch ( MBB , Dest , FBB , Cond , false ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } if ( Cond . empty ( ) || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } MachineInstr * OldBranch = I ; DebugLoc dl = OldBranch -> getDebugLoc ( ) ; TII -> ReverseBranchCondition ( Cond ) ; TII -> InsertConstBranchAtInst ( MBB , I , <NUM_LIT> , Cond , dl ) ; I = BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( Dest ) ; OldBranch -> eraseFromParent ( ) ; BlockSizes [ MBB . getNumber ( ) ] += <NUM_LIT> ; MBBStartOffset += <NUM_LIT> ; ++ NumExpanded ; MadeChange = true ; } } EverMadeChange |= MadeChange ; }"
LLVM,RISCV,920,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock * FBB = <NUM_LIT> ; Cond . clear ( ) ; if ( TII -> AnalyzeBranch ( MBB , Dest , FBB , Cond , false ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } if ( Cond . empty ( ) || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; }"
LLVM,RISCV,921,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>BranchSelectionPass ( ) { return new <ISA_LIT>BSel ( ) ;"
LLVM,RISCV,922,"Predict the next statement of this code snippet:
 <s> virtual const char * getPassName ( ) const { return <STR_LIT> ;"
LLVM,RISCV,923,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>BSel ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>BSelPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,RISCV,924,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>BSel ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,925,"Predict the next statement of this code snippet:
 <s> } MachineBasicBlock * FBB = <NUM_LIT> ; Cond . clear ( ) ; if ( TII -> analyzeBranch ( MBB , Dest , FBB , Cond , false ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } if ( Cond . empty ( ) || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } MachineInstr * OldBranch = I ; DebugLoc dl = OldBranch -> getDebugLoc ( ) ; TII -> ReverseBranchCondition ( Cond ) ; TII -> InsertConstBranchAtInst ( MBB , I , <NUM_LIT> , Cond , dl ) ; I = BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( Dest ) ; OldBranch -> eraseFromParent ( ) ; BlockSizes [ MBB . getNumber ( ) ] += <NUM_LIT> ; MBBStartOffset += <NUM_LIT> ; ++ NumExpanded ; MadeChange = true ; } } EverMadeChange |= MadeChange ; }"
LLVM,RISCV,926,"Predict the next statement of this code snippet:
 <s> if ( F . arg_empty ( ) ) return true ; return false ;"
LLVM,RISCV,927,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const {"
LLVM,RISCV,928,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const {"
LLVM,RISCV,929,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {"
LLVM,RISCV,930,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {"
LLVM,RISCV,931,"Predict the next statement of this code snippet:
 <s> MachineInstr & MI = * MII ++ ; if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) { if ( PrevVSETVLI && ( MI . isCall ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) ) { PrevVSETVLI = nullptr ; } continue ; } if ( ! PrevVSETVLI || ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { PrevVSETVLI = & MI ; continue ; } if ( PrevVSETVLI -> getOpcode ( ) != MI . getOpcode ( ) ) { PrevVSETVLI = & MI ; continue ; } Register AVLReg ; bool SameAVL = false ; if ( MI . getOpcode ( ) == <STR_LIT> ) { AVLReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SameAVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) == AVLReg ; } else { SameAVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) == MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } int64_t PrevVTYPEImm = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VTYPEImm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! SameAVL || PrevVTYPEImm != VTYPEImm ) { PrevVSETVLI = & MI ; continue ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && ( AVLReg == <STR_LIT> ) ) { assert ( ( PrevVSETVLI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; Register PrevOutVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OutVL = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PrevOutVL == <STR_LIT> && OutVL != <STR_LIT> ) {"
LLVM,RISCV,932,"Predict the next statement of this code snippet:
 <s> bool Changed = false ; MachineInstr * PrevVSETVLI = nullptr ; for ( auto MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ++ ; if ( MI . getOpcode ( ) != <STR_LIT> ) { if ( PrevVSETVLI && ( MI . isCall ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) ) { PrevVSETVLI = nullptr ;"
LLVM,RISCV,933,"Predict the next statement of this code snippet:
 <s> int64_t PrevVTYPEImm = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VTYPEImm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( PrevAVLReg != AVLReg || PrevVTYPEImm != VTYPEImm ) { PrevVSETVLI = & MI ; continue ; } if ( AVLReg == <STR_LIT> ) { Register PrevOutVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OutVL = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PrevOutVL == <STR_LIT> && OutVL != <STR_LIT> ) { PrevVSETVLI = & MI ; continue ; } }"
LLVM,RISCV,934,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;"
LLVM,RISCV,935,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;"
LLVM,RISCV,936,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <ISA_LIT>_CLEANUP_VSETVLI_NAME ;"
LLVM,RISCV,937,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <ISA_LIT>_CLEANUP_VSETVLI_NAME ;"
LLVM,RISCV,938,"Predict the next statement of this code snippet:
 <s> MachineFunctionProperties getRequiredProperties ( ) const override { return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: IsSSA ) ;"
LLVM,RISCV,939,"Predict the next statement of this code snippet:
 <s> if ( AVLReg == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; if ( AVLReg . isVirtual ( ) && AVLReg == PrevOutVL ) return true ; if ( PrevVSETVLI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( AVLReg != PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return false ; if ( AVLReg == <STR_LIT> ) {"
LLVM,RISCV,940,"Predict the next statement of this code snippet:
 <s> int64_t VTYPEImm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( PrevVTYPEImm != VTYPEImm ) return false ; if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( PrevVSETVLI -> getOpcode ( ) != <STR_LIT> ) return false ; return PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) == MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } assert ( MI . getOpcode ( ) == <STR_LIT> ) ; Register AVLReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,941,"Predict the next statement of this code snippet:
 <s> initialize<ISA_LIT>CleanupVSETVLIPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,RISCV,942,"Predict the next statement of this code snippet:
 <s> MachineInstr * PrevVSETVLI = nullptr ; for ( auto MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ++ ; if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) { if ( PrevVSETVLI && ( MI . isCall ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) ) {"
LLVM,RISCV,943,"Predict the next statement of this code snippet:
 <s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasStdExtV ( ) ) return false ;"
LLVM,RISCV,944,"Predict the next statement of this code snippet:
 <s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ;"
LLVM,RISCV,945,"Predict the next statement of this code snippet:
 <s> uint64_t getAlignmentMask ( uint64_t Length , bool IsRV64 ) {"
LLVM,RISCV,946,"Predict the next statement of this code snippet:
 <s> } else { return cc64_get_representable_length ( Length ) ;"
LLVM,RISCV,947,"Predict the next statement of this code snippet:
 <s> Align getRequiredAlignment ( uint64_t Size , bool IsRV64 ) { if ( IsRV64 ) { return Align ( cc128_get_required_alignment ( Size ) ) ;"
LLVM,RISCV,948,"Predict the next statement of this code snippet:
 <s> if ( IsRV64 ) { return Align ( cc128_get_required_alignment ( Size ) ) ; } else {"
LLVM,RISCV,949,"Predict the next statement of this code snippet:
 <s> } else { return static_cast < TailPaddingAmount > ( llvm :: alignTo ( Size , cc64_get_required_alignment ( Size ) ) - Size ) ;"
LLVM,RISCV,950,"Predict the next statement of this code snippet:
 <s> ID . AddInteger ( Modifier ) ;"
LLVM,RISCV,951,"Predict the next statement of this code snippet:
 <s> const std :: vector < MachineConstantPoolEntry > Constants = CP -> getConstants ( ) ; for ( unsigned I = <NUM_LIT> , E = Constants . size ( ) ; I != E ; ++ I ) { if ( Constants [ I ] . isMachineConstantPoolEntry ( ) && ( Constants [ I ] . getAlignment ( ) & AlignMask ) == <NUM_LIT> ) { <ISA_LIT>ConstantPoolValue * RCPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( Constants [ I ] . Val . MachineCPVal ) ; if ( RCPV -> GV == GV && RCPV -> Modifier == Modifier ) return I ; }"
LLVM,RISCV,952,"Predict the next statement of this code snippet:
 <s> if ( Constants [ I ] . isMachineConstantPoolEntry ( ) && ( Constants [ I ] . getAlignment ( ) & AlignMask ) == <NUM_LIT> ) { <ISA_LIT>ConstantPoolValue * RCPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( Constants [ I ] . Val . MachineCPVal ) ; if ( RCPV -> GV == GV && RCPV -> Modifier == Modifier ) return I ; }"
LLVM,RISCV,953,"Predict the next statement of this code snippet:
 <s> return GV ;"
LLVM,RISCV,954,"Predict the next statement of this code snippet:
 <s> <STR_LIT> getModifier ( ) const { return Modifier ;"
LLVM,RISCV,955,"Predict the next statement of this code snippet:
 <s> O << GV ;"
LLVM,RISCV,956,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>ConstantPoolValue :: print ( raw_ostream & O ) const {"
LLVM,RISCV,957,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ConstantPoolValue :: <ISA_LIT>ConstantPoolValue ( const GlobalValue * gv , <STR_LIT> modifier ) : MachineConstantPoolValue ( gv -> getType ( ) ) , GV ( gv ) , Modifier ( modifier ) {"
LLVM,RISCV,958,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ConstantPoolValue ::"
LLVM,RISCV,959,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>CoreVHwlpBlocks ( ) ;"
LLVM,RISCV,960,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {"
LLVM,RISCV,961,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return COREV_HWLP_BLOCKS_NAME ;"
LLVM,RISCV,962,"Predict the next statement of this code snippet:
 <s> for ( auto Inner : * ML ) { Changed |= ProcessLoop ( Inner , MF ) ; } return Changed ; } auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock * BB = Preheader ; while ( BB != Latch ) { assert ( BB -> succ_size ( ) <= <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock * Next = * BB -> succ_begin ( ) ; if ( BB -> succ_size ( ) == <NUM_LIT> ) { hwlp = false ; for ( auto & MI : BB -> terminators ( ) ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { hwlp = true ; if ( Next == MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) { Next = * BB -> succ_rbegin ( ) ; } break ; } } assert ( hwlp && <STR_LIT> ) ; } if ( ! BB -> isLayoutSuccessor ( Next ) ) { MachineBasicBlock * OldPred = Next -> getPrevNode ( ) ; MachineBasicBlock * OldSucc1 = Next -> getNextNode ( ) ; MachineBasicBlock * OldSucc2 = BB -> getNextNode ( ) ; Next -> moveAfter ( BB ) ; OldPred -> updateTerminator ( Next ) ; Next -> updateTerminator ( OldSucc1 ) ;"
LLVM,RISCV,963,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>CoreVHwlpBlocks ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,964,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>CoreVHwlpBlocks ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,965,"Predict the next statement of this code snippet:
 <s> for ( auto & ML : MLI ) { Changed |= ProcessLoop ( ML , MF ) ; } return Changed ;"
LLVM,RISCV,966,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR32CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) {"
LLVM,RISCV,967,"Predict the next statement of this code snippet:
 <s> Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,968,"Predict the next statement of this code snippet:
 <s> return MCDisassembler :: Fail ; } Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,969,"Predict the next statement of this code snippet:
 <s> Register Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,970,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;"
LLVM,RISCV,971,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {"
LLVM,RISCV,972,"Predict the next statement of this code snippet:
 <s> Register Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,973,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,974,"Predict the next statement of this code snippet:
 <s> bool IsRV32E = FeatureBits [ <STR_LIT> ] ; if ( RegNo >= <NUM_LIT> || ( IsRV32E && RegNo >= <NUM_LIT> ) ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,975,"Predict the next statement of this code snippet:
 <s> const FeatureBitset & FeatureBits = static_cast < const MCDisassembler * > ( Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; bool IsRV32E = FeatureBits [ <STR_LIT> ] ; if ( RegNo >= <NUM_LIT> || ( IsRV32E && RegNo >= <NUM_LIT> ) ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,976,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; DecodeGPRRegisterClass ( Inst , Rs2 , Address , Decoder ) ;"
LLVM,RISCV,977,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeRVCInstrRdRs1Rs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rs2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ;"
LLVM,RISCV,978,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; uint64_t UImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeUImmOperand < <NUM_LIT> > ( Inst , UImm6 , Address , Decoder ) ; ( void ) Result ;"
LLVM,RISCV,979,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeRVCInstrRdRs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rs2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ;"
LLVM,RISCV,980,"Predict the next statement of this code snippet:
 <s> unsigned Rs2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ;"
LLVM,RISCV,981,"Predict the next statement of this code snippet:
 <s> uint64_t SImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeSImmOperand < <NUM_LIT> > ( Inst , SImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler :: Success && <STR_LIT> ) ;"
LLVM,RISCV,982,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeRVCInstrSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { uint64_t SImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeSImmOperand < <NUM_LIT> > ( Inst , SImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler :: Success && <STR_LIT> ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,983,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeRVCInstrSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { uint64_t SImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeSImmOperand < <NUM_LIT> > ( Inst , SImm6 , Address , Decoder ) ;"
LLVM,RISCV,984,"Predict the next statement of this code snippet:
 <s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) {"
LLVM,RISCV,985,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,986,"Predict the next statement of this code snippet:
 <s> if ( ( Bytes [ <NUM_LIT> ] & <NUM_LIT> ) == <NUM_LIT> ) { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read32le ( Bytes . data ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } else { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ;"
LLVM,RISCV,987,"Predict the next statement of this code snippet:
 <s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>Disassembler ) ;"
LLVM,RISCV,988,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>32Target ( ) , create<ISA_LIT>Disassembler ) ;"
LLVM,RISCV,989,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) {"
LLVM,RISCV,990,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) {"
LLVM,RISCV,991,"Predict the next statement of this code snippet:
 <s> } if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { DecodeGPCRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ; }"
LLVM,RISCV,992,"Predict the next statement of this code snippet:
 <s> DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ; } if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { DecodeGPCRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ;"
LLVM,RISCV,993,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR16RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {"
LLVM,RISCV,994,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR32CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) { return MCDisassembler :: Fail ;"
LLVM,RISCV,995,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,996,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,997,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) { return MCDisassembler :: Fail ; } MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,998,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) { return MCDisassembler :: Fail ; } MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,999,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;"
LLVM,RISCV,1000,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPCRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {"
LLVM,RISCV,1001,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1002,"Predict the next statement of this code snippet:
 <s> } return DecodeGPCRRegisterClass ( Inst , RegNo , Address , Decoder ) ;"
LLVM,RISCV,1003,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> || ( IsRV32E && RegNo >= <NUM_LIT> ) ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1004,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1005,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,1006,"Predict the next statement of this code snippet:
 <s> const FeatureBitset & FeatureBits = static_cast < const MCDisassembler * > ( Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; bool IsRV32E = FeatureBits [ <STR_LIT> ] ; if ( RegNo >= <NUM_LIT> || ( IsRV32E && RegNo >= <NUM_LIT> ) ) return MCDisassembler :: Fail ;"
LLVM,RISCV,1007,"Predict the next statement of this code snippet:
 <s> MCRegister Reg = <STR_LIT> ; switch ( RegNo ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : Reg = <STR_LIT> ; break ; case <NUM_LIT> : break ; }"
LLVM,RISCV,1008,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeVRM2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1009,"Predict the next statement of this code snippet:
 <s> const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ;"
LLVM,RISCV,1010,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1011,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeVRM4RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1012,"Predict the next statement of this code snippet:
 <s> MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1013,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ;"
LLVM,RISCV,1014,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,1015,"Predict the next statement of this code snippet:
 <s> if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCapModeOnly_32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } else { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32CapModeOnly_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) {"
LLVM,RISCV,1016,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1017,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1018,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeVGRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1019,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1020,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1021,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1022,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1023,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {"
LLVM,RISCV,1024,"Predict the next statement of this code snippet:
 <s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1025,"Predict the next statement of this code snippet:
 <s> uint32_t Inst = <STR_LIT> :: read32le ( Bytes . data ( ) ) ;"
LLVM,RISCV,1026,"Predict the next statement of this code snippet:
 <s> unsigned Reg = FPR32DecoderTable [ RegNo ] ;"
LLVM,RISCV,1027,"Predict the next statement of this code snippet:
 <s> if ( RegNo > array_lengthof ( FPR32DecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = FPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1028,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {"
LLVM,RISCV,1029,"Predict the next statement of this code snippet:
 <s> if ( RegNo > array_lengthof ( FPR64DecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = FPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1030,"Predict the next statement of this code snippet:
 <s> return decodeSImmOperand < N > ( Inst , Imm , Address , Decoder ) ;"
LLVM,RISCV,1031,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeSImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { if ( Imm == <NUM_LIT> ) return MCDisassembler :: Fail ; return decodeSImmOperand < N > ( Inst , Imm , Address , Decoder ) ;"
LLVM,RISCV,1032,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeUImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {"
LLVM,RISCV,1033,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> || RegNo & <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,1034,"Predict the next statement of this code snippet:
 <s> MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1035,"Predict the next statement of this code snippet:
 <s> Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read32le ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] && ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableRV32Zdinx32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableRVZfinx32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } else { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ;"
LLVM,RISCV,1036,"Predict the next statement of this code snippet:
 <s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] && ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableRV32Zdinx32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableRVZfinx32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } else { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable16 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } return Result ;"
LLVM,RISCV,1037,"Predict the next statement of this code snippet:
 <s> Size = <NUM_LIT> ; return Result ; } } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableRVBC16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable16 , MI , Insn , Address , this , STI ) ;"
LLVM,RISCV,1038,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodePulpV2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {"
LLVM,RISCV,1039,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodePulpV4RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;"
LLVM,RISCV,1040,"Predict the next statement of this code snippet:
 <s> Register Reg = FPR32DecoderTable [ RegNo + <NUM_LIT> ] ;"
LLVM,RISCV,1041,"Predict the next statement of this code snippet:
 <s> Register Reg = FPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1042,"Predict the next statement of this code snippet:
 <s> if ( RegNo > array_lengthof ( FPR32DecoderTable ) ) return MCDisassembler :: Fail ; Register Reg = FPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1043,"Predict the next statement of this code snippet:
 <s> return MCDisassembler :: Fail ; } Register Reg = FPR64DecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1044,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) { return MCDisassembler :: Fail ; } Register Reg = FPR64DecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1045,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > array_lengthof ( FPR64DecoderTable ) ) return MCDisassembler :: Fail ;"
LLVM,RISCV,1046,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1047,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {"
LLVM,RISCV,1048,"Predict the next statement of this code snippet:
 <s> return MCDisassembler :: Fail ; } unsigned Reg = VRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1049,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } else { Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable16 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; }"
LLVM,RISCV,1050,"Predict the next statement of this code snippet:
 <s> if ( RegNo > sizeof ( GPRDecoderTable ) ) { return MCDisassembler :: Fail ; } unsigned Reg = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1051,"Predict the next statement of this code snippet:
 <s> return MCDisassembler :: Fail ; } unsigned Reg = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1052,"Predict the next statement of this code snippet:
 <s> if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ; }"
LLVM,RISCV,1053,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeCLUIImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) {"
LLVM,RISCV,1054,"Predict the next statement of this code snippet:
 <s> MCRegister Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,1055,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;"
LLVM,RISCV,1056,"Predict the next statement of this code snippet:
 <s> } MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1057,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR32RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,1058,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) { return MCDisassembler :: Fail ; } MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1059,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;"
LLVM,RISCV,1060,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeFRMArg ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; if ( ! llvm :: <STR_LIT> ( Imm ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1061,"Predict the next statement of this code snippet:
 <s> if ( ! llvm :: <STR_LIT> ( Imm ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1062,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;"
LLVM,RISCV,1063,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;"
LLVM,RISCV,1064,"Predict the next statement of this code snippet:
 <s> } return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;"
LLVM,RISCV,1065,"Predict the next statement of this code snippet:
 <s> return MCDisassembler :: Fail ; }"
LLVM,RISCV,1066,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) {"
LLVM,RISCV,1067,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPRPF64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> || RegNo & <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1068,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPRPF64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> || RegNo & <NUM_LIT> ) return MCDisassembler :: Fail ;"
LLVM,RISCV,1069,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> || ( IsRV32E && RegNo >= <NUM_LIT> ) ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ;"
LLVM,RISCV,1070,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeRVCInstrRdRs1Rs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) {"
LLVM,RISCV,1071,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeRVCInstrRdRs1UImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ; Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; uint64_t UImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeUImmOperand < <NUM_LIT> > ( Inst , UImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler :: Success && <STR_LIT> ) ;"
LLVM,RISCV,1072,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeRVCInstrRdRs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rs2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,1073,"Predict the next statement of this code snippet:
 <s> DecodeStatus Result = decodeSImmOperand < <NUM_LIT> > ( Inst , SImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler :: Success && <STR_LIT> ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1074,"Predict the next statement of this code snippet:
 <s> uint64_t SImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,1075,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeSImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { if ( Imm == <NUM_LIT> ) return MCDisassembler :: Fail ; return decodeSImmOperand < N > ( Inst , Imm , Address , Decoder ) ;"
LLVM,RISCV,1076,"Predict the next statement of this code snippet:
 <s> if ( Imm == <NUM_LIT> ) return MCDisassembler :: Fail ;"
LLVM,RISCV,1077,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; addImplySP ( Inst , Address , Decoder ) ;"
LLVM,RISCV,1078,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << <NUM_LIT> ) ) ) ;"
LLVM,RISCV,1079,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << <NUM_LIT> ) ) ) ;"
LLVM,RISCV,1080,"Predict the next statement of this code snippet:
 <s> return decodeUImmOperand < N > ( Inst , Imm , Address , Decoder ) ;"
LLVM,RISCV,1081,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeUImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { if ( Imm == <NUM_LIT> ) return MCDisassembler :: Fail ;"
LLVM,RISCV,1082,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; addImplySP ( Inst , Address , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1083,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1084,"Predict the next statement of this code snippet:
 <s> MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1085,"Predict the next statement of this code snippet:
 <s> if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1086,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ;"
LLVM,RISCV,1087,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ;"
LLVM,RISCV,1088,"Predict the next statement of this code snippet:
 <s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1089,"Predict the next statement of this code snippet:
 <s> if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ; DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ;"
LLVM,RISCV,1090,"Predict the next statement of this code snippet:
 <s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) {"
LLVM,RISCV,1091,"Predict the next statement of this code snippet:
 <s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx ) ;"
LLVM,RISCV,1092,"Predict the next statement of this code snippet:
 <s> if ( Imm > <NUM_LIT> ) { Imm = ( SignExtend64 < <NUM_LIT> > ( Imm ) & <NUM_LIT> ) ; } Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;"
LLVM,RISCV,1093,"Predict the next statement of this code snippet:
 <s> if ( Imm > <NUM_LIT> ) { Imm = ( SignExtend64 < <NUM_LIT> > ( Imm ) & <NUM_LIT> ) ; } Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1094,"Predict the next statement of this code snippet:
 <s> return MCDisassembler :: Fail ; } unsigned Reg = FPR32DecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1095,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR32RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > sizeof ( FPR32DecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = FPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;"
LLVM,RISCV,1096,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) { return MCDisassembler :: Fail ; } unsigned Reg = FPR64DecoderTable [ RegNo + <NUM_LIT> ] ;"
LLVM,RISCV,1097,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) { return MCDisassembler :: Fail ; }"
LLVM,RISCV,1098,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > sizeof ( FPR64DecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = FPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1099,"Predict the next statement of this code snippet:
 <s> if ( RegNo > sizeof ( FPR64DecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = FPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1100,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeFRMArg ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ;"
LLVM,RISCV,1101,"Predict the next statement of this code snippet:
 <s> assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ;"
LLVM,RISCV,1102,"Predict the next statement of this code snippet:
 <s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = GPRDecoderTable [ RegNo + <NUM_LIT> ] ;"
LLVM,RISCV,1103,"Predict the next statement of this code snippet:
 <s> unsigned Reg = GPRDecoderTable [ RegNo + <NUM_LIT> ] ;"
LLVM,RISCV,1104,"Predict the next statement of this code snippet:
 <s> } return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;"
LLVM,RISCV,1105,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo == <NUM_LIT> ) { return MCDisassembler :: Fail ; }"
LLVM,RISCV,1106,"Predict the next statement of this code snippet:
 <s> static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {"
LLVM,RISCV,1107,"Predict the next statement of this code snippet:
 <s> unsigned Reg = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1108,"Predict the next statement of this code snippet:
 <s> if ( RegNo > sizeof ( GPRDecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;"
LLVM,RISCV,1109,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {"
LLVM,RISCV,1110,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ;"
LLVM,RISCV,1111,"Predict the next statement of this code snippet:
 <s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << <NUM_LIT> ) ) ) ;"
LLVM,RISCV,1112,"Predict the next statement of this code snippet:
 <s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {"
LLVM,RISCV,1113,"Predict the next statement of this code snippet:
 <s> } else { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } }"
LLVM,RISCV,1114,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>Disassembler ) ;"
LLVM,RISCV,1115,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {"
LLVM,RISCV,1116,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {"
LLVM,RISCV,1117,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> :"
LLVM,RISCV,1118,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , ELF :: EM_<ISA_LIT> , true ) {"
LLVM,RISCV,1119,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , ELF :: EM_<ISA_LIT> , true ) {"
LLVM,RISCV,1120,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {"
LLVM,RISCV,1121,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {"
LLVM,RISCV,1122,"Predict the next statement of this code snippet:
 <s> case FK_PCRel_4 : return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_CAPTAB_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_TLS_IE_CAPTAB_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_TLS_GD_CAPTAB_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_CJAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_CCALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_RVC_CJUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB64 ; } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ;"
LLVM,RISCV,1123,"Predict the next statement of this code snippet:
 <s> const MCExpr * Expr = Fixup . getValue ( ) ; unsigned Kind = Fixup . getTargetKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return Kind - FirstLiteralRelocationKind ; if ( IsPCRel ) { switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : case FK_PCRel_4 : return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_CAPTAB_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_TLS_IE_CAPTAB_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_TLS_GD_CAPTAB_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_CJAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_CCALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CHERI_RVC_CJUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB64 ; } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> :"
LLVM,RISCV,1124,"Predict the next statement of this code snippet:
 <s> return createELFObjectWriter ( llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI , Is64Bit ) , OS , true ) ;"
LLVM,RISCV,1125,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> :"
LLVM,RISCV,1126,"Predict the next statement of this code snippet:
 <s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool Is64Bit ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI , Is64Bit ) ;"
LLVM,RISCV,1127,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {"
LLVM,RISCV,1128,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , ELF :: EM_<ISA_LIT> , false ) {"
LLVM,RISCV,1129,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , ELF :: EM_<ISA_LIT> , false ) {"
LLVM,RISCV,1130,"Predict the next statement of this code snippet:
 <s> return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> :"
LLVM,RISCV,1131,"Predict the next statement of this code snippet:
 <s> } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RELAX ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ALIGN ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD64 ;"
LLVM,RISCV,1132,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } } switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> :"
LLVM,RISCV,1133,"Predict the next statement of this code snippet:
 <s> case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RELAX ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ALIGN ; }"
LLVM,RISCV,1134,"Predict the next statement of this code snippet:
 <s> return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 :"
LLVM,RISCV,1135,"Predict the next statement of this code snippet:
 <s> switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : case FK_PCRel_4 : return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RELAX ;"
LLVM,RISCV,1136,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : case FK_PCRel_4 : return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } } switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ;"
LLVM,RISCV,1137,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ;"
LLVM,RISCV,1138,"Predict the next statement of this code snippet:
 <s> switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> :"
LLVM,RISCV,1139,"Predict the next statement of this code snippet:
 <s> return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } } switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ;"
LLVM,RISCV,1140,"Predict the next statement of this code snippet:
 <s> return std :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI , Is64Bit ) ;"
LLVM,RISCV,1141,"Predict the next statement of this code snippet:
 <s> case FK_PCRel_4 : return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CVPCREL_UI12 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CVPCREL_URS1 ; } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ;"
LLVM,RISCV,1142,"Predict the next statement of this code snippet:
 <s> Result += getULEB128Size ( item . IntValue ) ; break ; case AttributeType :: Text : Result += getULEB128Size ( item . Tag ) ; Result += item . StringValue . size ( ) + <NUM_LIT> ; break ;"
LLVM,RISCV,1143,"Predict the next statement of this code snippet:
 <s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > MOW , std :: unique_ptr < MCCodeEmitter > MCE , bool RelaxAll ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( C , std :: move ( MAB ) , std :: move ( MOW ) , std :: move ( MCE ) ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ;"
LLVM,RISCV,1144,"Predict the next statement of this code snippet:
 <s> setAttributeItem ( Attribute , Value , true ) ;"
LLVM,RISCV,1145,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoPIC ( ) {"
LLVM,RISCV,1146,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoPIC ( ) {"
LLVM,RISCV,1147,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoRelax ( ) {"
LLVM,RISCV,1148,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoRelax ( ) {"
LLVM,RISCV,1149,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoRVC ( ) {"
LLVM,RISCV,1150,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoRVC ( ) {"
LLVM,RISCV,1151,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPIC ( ) {"
LLVM,RISCV,1152,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPIC ( ) {"
LLVM,RISCV,1153,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPop ( ) {"
LLVM,RISCV,1154,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPop ( ) {"
LLVM,RISCV,1155,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPush ( ) {"
LLVM,RISCV,1156,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPush ( ) {"
LLVM,RISCV,1157,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionRelax ( ) {"
LLVM,RISCV,1158,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionRelax ( ) {"
LLVM,RISCV,1159,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionRVC ( ) {"
LLVM,RISCV,1160,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionRVC ( ) {"
LLVM,RISCV,1161,"Predict the next statement of this code snippet:
 <s> unsigned Add , Sub ; std :: tie ( Add , Sub ) = getRelocPairForSize ( Size ) ; DF -> getFixups ( ) . push_back ( MCFixup :: create ( DF -> getContents ( ) . size ( ) , A , static_cast < MCFixupKind > ( Add ) , Loc ) ) ;"
LLVM,RISCV,1162,"Predict the next statement of this code snippet:
 <s> DF -> getFixups ( ) . push_back ( MCFixup :: create ( DF -> getContents ( ) . size ( ) , A , static_cast < MCFixupKind > ( Add ) , Loc ) ) ; DF -> getFixups ( ) . push_back ( MCFixup :: create ( DF -> getContents ( ) . size ( ) , B , static_cast < MCFixupKind > ( Sub ) , Loc ) ) ;"
LLVM,RISCV,1163,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_FLOAT_ABI_SINGLE ; break ; case <STR_LIT> : case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_FLOAT_ABI_DOUBLE ; break ; case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_RVE ; break ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,RISCV,1164,"Predict the next statement of this code snippet:
 <s> switch ( item . Type ) { default : llvm_unreachable ( <STR_LIT> ) ; case AttributeType :: Numeric : Streamer . emitULEB128IntValue ( item . IntValue ) ; break ; case AttributeType :: Text : Streamer . emitBytes ( item . StringValue ) ; Streamer . emitInt8 ( <NUM_LIT> ) ; break ; case AttributeType :: NumericAndText : Streamer . emitULEB128IntValue ( item . IntValue ) ; Streamer . emitBytes ( item . StringValue ) ; Streamer . emitInt8 ( <NUM_LIT> ) ; break ; } } Contents . clear ( ) ;"
LLVM,RISCV,1165,"Predict the next statement of this code snippet:
 <s> const size_t ContentsSize = calculateContentSize ( ) ; Streamer . emitInt32 ( VendorHeaderSize + TagHeaderSize + ContentsSize ) ; Streamer . emitBytes ( CurrentVendor ) ; Streamer . emitInt8 ( <NUM_LIT> ) ; Streamer . emitInt8 ( ELFAttrs :: File ) ; Streamer . emitInt32 ( TagHeaderSize + ContentsSize ) ; for ( AttributeItem item : Contents ) { Streamer . emitULEB128IntValue ( item . Tag ) ; switch ( item . Type ) { default : llvm_unreachable ( <STR_LIT> ) ; case AttributeType :: Numeric : Streamer . emitULEB128IntValue ( item . IntValue ) ; break ; case AttributeType :: Text : Streamer . emitBytes ( item . StringValue ) ; Streamer . emitInt8 ( <NUM_LIT> ) ; break ; case AttributeType :: NumericAndText :"
LLVM,RISCV,1166,"Predict the next statement of this code snippet:
 <s> return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> :"
LLVM,RISCV,1167,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> :"
LLVM,RISCV,1168,"Predict the next statement of this code snippet:
 <s> static bool requiresFixups ( MCContext & C , const MCExpr * Value , const MCExpr * & LHS , const MCExpr * & RHS ) { const auto * MBE = dyn_cast < MCBinaryExpr > ( Value ) ; if ( MBE == nullptr ) return false ; MCValue E ; if ( ! Value -> evaluateAsRelocatable ( E , nullptr , nullptr ) ) return false ; if ( E . getSymA ( ) == nullptr || E . getSymB ( ) == nullptr ) return false ; const auto & A = E . getSymA ( ) -> getSymbol ( ) ; const auto & B = E . getSymB ( ) -> getSymbol ( ) ; LHS = MCBinaryExpr :: create ( MCBinaryExpr :: Add , MCSymbolRefExpr :: create ( & A , C ) , MCConstantExpr :: create ( E . getConstant ( ) , C ) , C ) ;"
LLVM,RISCV,1169,"Predict the next statement of this code snippet:
 <s> MCValue E ; if ( ! Value -> evaluateAsRelocatable ( E , nullptr , nullptr ) ) return false ; if ( E . getSymA ( ) == nullptr || E . getSymB ( ) == nullptr ) return false ; const auto & A = E . getSymA ( ) -> getSymbol ( ) ; const auto & B = E . getSymB ( ) -> getSymbol ( ) ; LHS = MCBinaryExpr :: create ( MCBinaryExpr :: Add , MCSymbolRefExpr :: create ( & A , C ) , MCConstantExpr :: create ( E . getConstant ( ) , C ) , C ) ; RHS = E . getSymB ( ) ;"
LLVM,RISCV,1170,"Predict the next statement of this code snippet:
 <s> static_cast < <ISA_LIT>TargetStreamer * > ( getTargetStreamer ( ) ) -> reset ( ) ; MCELFStreamer :: reset ( ) ;"
LLVM,RISCV,1171,"Predict the next statement of this code snippet:
 <s> void reset ( ) override {"
LLVM,RISCV,1172,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ELFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > MOW , std :: unique_ptr < MCCodeEmitter > MCE ) : MCELFStreamer ( C , std :: move ( MAB ) , std :: move ( MOW ) , std :: move ( MCE ) ) {"
LLVM,RISCV,1173,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ELFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > MOW , std :: unique_ptr < MCCodeEmitter > MCE ) : MCELFStreamer ( C , std :: move ( MAB ) , std :: move ( MOW ) , std :: move ( MCE ) ) {"
LLVM,RISCV,1174,"Predict the next statement of this code snippet:
 <s> auto & MAB = static_cast < <ISA_LIT>AsmBackend & > ( MCA . getBackend ( ) ) ;"
LLVM,RISCV,1175,"Predict the next statement of this code snippet:
 <s> const FeatureBitset & Features = STI . getFeatureBits ( ) ; auto & MAB = static_cast < <ISA_LIT>AsmBackend & > ( MCA . getBackend ( ) ) ; <STR_LIT> ABI = MAB . getTargetABI ( ) ; assert ( ABI != <STR_LIT> && <STR_LIT> ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_RVC ; switch ( ABI ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_FLOAT_ABI_SINGLE ; break ; case <STR_LIT> : case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_FLOAT_ABI_DOUBLE ; break ; case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_RVE ; break ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,RISCV,1176,"Predict the next statement of this code snippet:
 <s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_RVC ;"
LLVM,RISCV,1177,"Predict the next statement of this code snippet:
 <s> const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_RVC ;"
LLVM,RISCV,1178,"Predict the next statement of this code snippet:
 <s> visitUsedSymbol ( * Symbol ) ; MCContext & Context = getContext ( ) ; const MCSymbolRefExpr * SRE = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , Context , Loc ) ; const MCBinaryExpr * CapExpr = MCBinaryExpr :: createAdd ( SRE , Addend , Context ) ; emitValueToAlignment ( CapSize , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; MCDataFragment * DF = new MCDataFragment ( ) ; MCFixup CapFixup = MCFixup :: create ( <NUM_LIT> , CapExpr , MCFixupKind ( <STR_LIT> ) ) ;"
LLVM,RISCV,1179,"Predict the next statement of this code snippet:
 <s> assert ( CapSize == ( getContext ( ) . getTargetTriple ( ) . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ;"
LLVM,RISCV,1180,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionCapMode ( ) {"
LLVM,RISCV,1181,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionCapMode ( ) {"
LLVM,RISCV,1182,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoCapMode ( ) {"
LLVM,RISCV,1183,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoCapMode ( ) {"
LLVM,RISCV,1184,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetELFStreamer :: <ISA_LIT>TargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : <ISA_LIT>TargetStreamer ( S ) , CurrentVendor ( <STR_LIT> ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const FeatureBitset & Features = STI . getFeatureBits ( ) ; auto & MAB = static_cast < <ISA_LIT>AsmBackend & > ( MCA . getBackend ( ) ) ; <STR_LIT> ABI = MAB . getTargetABI ( ) ; assert ( ABI != <STR_LIT> && <STR_LIT> ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_RVC ;"
LLVM,RISCV,1185,"Predict the next statement of this code snippet:
 <s> AttributeItem * getAttributeItem ( unsigned Attribute ) { for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) if ( Contents [ i ] . Tag == Attribute ) return & Contents [ i ] ; return nullptr ;"
LLVM,RISCV,1186,"Predict the next statement of this code snippet:
 <s> void setAttributeItem ( unsigned Attribute , StringRef Value , bool OverwriteExisting ) { if ( AttributeItem * Item = getAttributeItem ( Attribute ) ) { if ( ! OverwriteExisting ) return ; Item -> Type = AttributeType :: Text ; Item -> StringValue = std :: string ( Value ) ; return ; }"
LLVM,RISCV,1187,"Predict the next statement of this code snippet:
 <s> if ( AttributeItem * Item = getAttributeItem ( Attribute ) ) { if ( ! OverwriteExisting ) return ; Item -> Type = AttributeType :: Text ; Item -> StringValue = std :: string ( Value ) ;"
LLVM,RISCV,1188,"Predict the next statement of this code snippet:
 <s> if ( ! OverwriteExisting ) return ; Item -> Type = AttributeType :: NumericAndText ; Item -> IntValue = IntValue ; Item -> StringValue = std :: string ( StringValue ) ;"
LLVM,RISCV,1189,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Add : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Sub : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: And : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Or :"
LLVM,RISCV,1190,"Predict the next statement of this code snippet:
 <s> Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW ( PtrIsCap , Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Add : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Sub : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: And : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ;"
LLVM,RISCV,1191,"Predict the next statement of this code snippet:
 <s> MF -> insert ( ++ LoopMBB -> getIterator ( ) , DoneMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopMBB ) ; if ( ! IsMasked ) doAtomicBinOpExpansion ( TII , MI , DL , & MBB , LoopMBB , DoneMBB , BinOp , Width , PtrIsCap ) ; else doMaskedAtomicBinOpExpansion ( TII , MI , DL , & MBB , LoopMBB , DoneMBB , BinOp , Width ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ;"
LLVM,RISCV,1192,"Predict the next statement of this code snippet:
 <s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoopHeadMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto LoopTailMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoopHeadMBB ) ; MF -> insert ( ++ LoopHeadMBB -> getIterator ( ) , LoopTailMBB ) ; MF -> insert ( ++ LoopTailMBB -> getIterator ( ) , DoneMBB ) ; LoopHeadMBB -> addSuccessor ( LoopTailMBB ) ; LoopHeadMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register CmpValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsMasked ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; if ( ! IsMasked ) { BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( PtrIsCap , Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW ( PtrIsCap , Ordering , Width ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } else { assert ( ! PtrIsCap && <STR_LIT> ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( false , Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ;"
LLVM,RISCV,1193,"Predict the next statement of this code snippet:
 <s> MachineFunction * MF = MBB . getParent ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; int CLen = TRI -> getRegSizeInBits ( <STR_LIT> ) ; auto LoopHeadMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto LoopTailMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoopHeadMBB ) ; MF -> insert ( ++ LoopHeadMBB -> getIterator ( ) , LoopTailMBB ) ; MF -> insert ( ++ LoopTailMBB -> getIterator ( ) , DoneMBB ) ; LoopHeadMBB -> addSuccessor ( LoopTailMBB ) ; LoopHeadMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register CmpValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMWCap ( PtrIsCap , Ordering , CLen ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( TRI -> getSubReg ( DestReg , <STR_LIT> ) ) . addReg ( TRI -> getSubReg ( CmpValReg , <STR_LIT> ) ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMWCap ( PtrIsCap , Ordering , CLen ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ;"
LLVM,RISCV,1194,"Predict the next statement of this code snippet:
 <s> if ( Width == <NUM_LIT> ) return getLRForRMW8 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return getLRForRMW16 ( PtrIsCap , Ordering ) ;"
LLVM,RISCV,1195,"Predict the next statement of this code snippet:
 <s> static unsigned getLRForRMW ( bool PtrIsCap , AtomicOrdering Ordering , int Width ) { if ( Width == <NUM_LIT> ) return getLRForRMW8 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return getLRForRMW16 ( PtrIsCap , Ordering ) ;"
LLVM,RISCV,1196,"Predict the next statement of this code snippet:
 <s> assert ( PtrIsCap ) ; switch ( Ordering ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire :"
LLVM,RISCV,1197,"Predict the next statement of this code snippet:
 <s> return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: SequentiallyConsistent :"
LLVM,RISCV,1198,"Predict the next statement of this code snippet:
 <s> return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return PtrIsCap ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,1199,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Acquire : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: AcquireRelease :"
LLVM,RISCV,1200,"Predict the next statement of this code snippet:
 <s> return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Acquire : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: SequentiallyConsistent :"
LLVM,RISCV,1201,"Predict the next statement of this code snippet:
 <s> assert ( PtrIsCap ) ; switch ( Ordering ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ;"
LLVM,RISCV,1202,"Predict the next statement of this code snippet:
 <s> if ( Width == <NUM_LIT> ) return getSCForRMW32 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return getSCForRMW64 ( PtrIsCap , Ordering ) ; llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,1203,"Predict the next statement of this code snippet:
 <s> if ( Width == <NUM_LIT> ) return getSCForRMW16 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return getSCForRMW32 ( PtrIsCap , Ordering ) ;"
LLVM,RISCV,1204,"Predict the next statement of this code snippet:
 <s> case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return <STR_LIT> ; case AtomicOrdering :: SequentiallyConsistent : return <STR_LIT> ; }"
LLVM,RISCV,1205,"Predict the next statement of this code snippet:
 <s> static unsigned getSCForRMW32 ( bool PtrIsCap , AtomicOrdering Ordering ) { switch ( Ordering ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Acquire : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release :"
LLVM,RISCV,1206,"Predict the next statement of this code snippet:
 <s> static unsigned getSCForRMW64 ( bool PtrIsCap , AtomicOrdering Ordering ) { switch ( Ordering ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Acquire : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release :"
LLVM,RISCV,1207,"Predict the next statement of this code snippet:
 <s> case AtomicOrdering :: Monotonic : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Acquire : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,1208,"Predict the next statement of this code snippet:
 <s> case AtomicOrdering :: Acquire : return CLen == <NUM_LIT> ? ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) : ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) ; case AtomicOrdering :: Release : return CLen == <NUM_LIT> ? ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) : ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) ; case AtomicOrdering :: AcquireRelease :"
LLVM,RISCV,1209,"Predict the next statement of this code snippet:
 <s> BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Nand : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ;"
LLVM,RISCV,1210,"Predict the next statement of this code snippet:
 <s> Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( IncrReg ) . addImm ( <NUM_LIT> ) ; break ; case AtomicRMWInst :: Add : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Sub : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ;"
LLVM,RISCV,1211,"Predict the next statement of this code snippet:
 <s> BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Nand : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( - <NUM_LIT> ) ; break ; } insertMaskedMerge ( TII , DL , LoopMBB , ScratchReg , DestReg , ScratchReg , MaskReg , ScratchReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopMBB ) ;"
LLVM,RISCV,1212,"Predict the next statement of this code snippet:
 <s> LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopMBB ) ;"
LLVM,RISCV,1213,"Predict the next statement of this code snippet:
 <s> BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW ( Ordering , Width ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } else { Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ;"
LLVM,RISCV,1214,"Predict the next statement of this code snippet:
 <s> bool IsSigned = BinOp == AtomicRMWInst :: Min || BinOp == AtomicRMWInst :: Max ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsSigned ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch2Reg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch1Reg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Max : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Scratch2Reg ) . addReg ( IncrReg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: Min : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IncrReg ) . addReg ( Scratch2Reg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: UMax :"
LLVM,RISCV,1215,"Predict the next statement of this code snippet:
 <s> Register Scratch1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Scratch2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsSigned = BinOp == AtomicRMWInst :: Min || BinOp == AtomicRMWInst :: Max ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsSigned ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch2Reg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch1Reg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Max : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Scratch2Reg ) . addReg ( IncrReg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: Min : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IncrReg ) . addReg ( Scratch2Reg ) . addMBB ( LoopTailMBB ) ;"
LLVM,RISCV,1216,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= expandMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ;"
LLVM,RISCV,1217,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Min , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMax , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> :"
LLVM,RISCV,1218,"Predict the next statement of this code snippet:
 <s> return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Min , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMax , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> :"
LLVM,RISCV,1219,"Predict the next statement of this code snippet:
 <s> if ( Width == <NUM_LIT> ) return getLRForRMW32 ( Ordering ) ; if ( Width == <NUM_LIT> ) return getLRForRMW64 ( Ordering ) ;"
LLVM,RISCV,1220,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return <STR_LIT> ; case AtomicOrdering :: SequentiallyConsistent :"
LLVM,RISCV,1221,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return <STR_LIT> ; case AtomicOrdering :: SequentiallyConsistent : return <STR_LIT> ;"
LLVM,RISCV,1222,"Predict the next statement of this code snippet:
 <s> switch ( Ordering ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return <STR_LIT> ;"
LLVM,RISCV,1223,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override {"
LLVM,RISCV,1224,"Predict the next statement of this code snippet:
 <s> static unsigned getSCForRMW ( AtomicOrdering Ordering , int Width ) {"
LLVM,RISCV,1225,"Predict the next statement of this code snippet:
 <s> switch ( Ordering ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return <STR_LIT> ; case AtomicOrdering :: SequentiallyConsistent :"
LLVM,RISCV,1226,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ;"
LLVM,RISCV,1227,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release :"
LLVM,RISCV,1228,"Predict the next statement of this code snippet:
 <s> assert ( ScratchReg != MaskReg && <STR_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( OldValReg ) . addReg ( NewValReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( MaskReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( OldValReg ) . addReg ( ScratchReg ) ;"
LLVM,RISCV,1229,"Predict the next statement of this code snippet:
 <s> assert ( OldValReg != MaskReg && <STR_LIT> ) ; assert ( ScratchReg != MaskReg && <STR_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( OldValReg ) . addReg ( NewValReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( MaskReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( OldValReg ) . addReg ( ScratchReg ) ;"
LLVM,RISCV,1230,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ValReg ) . addReg ( ValReg ) . addReg ( ShamtReg ) ;"
LLVM,RISCV,1231,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ;"
LLVM,RISCV,1232,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>ExpandCoreVHwlpPseudoPass ( ) {"
LLVM,RISCV,1233,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>ExpandCoreVHwlpPseudoPass ( ) {"
LLVM,RISCV,1234,"Predict the next statement of this code snippet:
 <s> return COREV_EXPAND_HWLP_PSEUDO_NAME ;"
LLVM,RISCV,1235,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : InnerEndSymbol = MI -> getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; break ; default : break ; } if ( InnerEndSymbol && InnerEndSymbol == MI -> getPreInstrSymbol ( ) ) { InnerHwlpEndOffset = Offset ; } unsigned Size = TII -> getInstSizeInBytes ( * MI ) ; if ( Size == <NUM_LIT> ) { Size = <NUM_LIT> ; } Offset += Size ; MachineInstr * Next = MI -> getNextNode ( ) ; if ( ! Next ) { Next = & MI -> getParent ( ) -> getNextNode ( ) -> front ( ) ; } MI = Next ; } assert ( isUInt < <NUM_LIT> > ( StartOffset ) && <STR_LIT> ) ; assert ( isUInt < <NUM_LIT> > ( EndOffset ) && <STR_LIT> ) ; MCSymbol * LastInstrSymbol = LastInstr -> getPreInstrSymbol ( ) ; if ( ! LastInstrSymbol ) { LastInstrSymbol = MF . getContext ( ) . createLinkerPrivateTempSymbol ( ) ; LastInstr -> setPreInstrSymbol ( MF , LastInstrSymbol ) ; } DebugLoc DL = HwlpSetup -> getDebugLoc ( ) ; int64_t LoopNum = Changed ? <NUM_LIT> : <NUM_LIT> ; if ( HwlpSetup -> getOpcode ( ) == <STR_LIT> ) { Register count = HwlpSetup -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( StartOffset == <NUM_LIT> ) { BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addReg ( count ) . addSym ( LastInstrSymbol ) ; } else { BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addReg ( count ) ; BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addMBB ( LoopHeader ) ; BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addSym ( LastInstrSymbol ) ; } } else { int64_t count = HwlpSetup -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( StartOffset == <NUM_LIT> && EndOffset < <NUM_LIT> ) { BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addImm ( count ) . addSym ( LastInstrSymbol ) ;"
LLVM,RISCV,1236,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ExpandCoreVHwlpPseudo ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,1237,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ExpandCoreVHwlpPseudo ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,1238,"Predict the next statement of this code snippet:
 <s> bool Changed = false ; for ( auto & ML : MLI ) { Changed |= ProcessLoop ( ML , MF ) ; }"
LLVM,RISCV,1239,"Predict the next statement of this code snippet:
 <s> return expandLoadLocalAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadTLSIEAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadTLSGDAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandReadCSRs ( MBB , MBBI , <NUM_LIT> ) ;"
LLVM,RISCV,1240,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( Address ) . addReg ( <STR_LIT> ) ; MBBI -> eraseFromParent ( ) ; return true ;"
LLVM,RISCV,1241,"Predict the next statement of this code snippet:
 <s> MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII -> get ( BaseInstr ) ) ; for ( MachineInstr :: const_mop_iterator Op = MI . operands_begin ( ) ; Op != MI . operands_end ( ) ; Op ++ ) { int Op_num = ( int ) MI . getOperandNo ( Op ) ; if ( Op_num == MergeOpIndex || Op_num == SEWIndex ) continue ; if ( ! Op -> isReg ( ) || Op -> getReg ( ) == <STR_LIT> ) { MIB . add ( * Op ) ; continue ; } Register Reg = Op -> getReg ( ) ; if ( ( & <STR_LIT> ) -> contains ( Reg ) || ( & <STR_LIT> ) -> contains ( Reg ) || ( & <STR_LIT> ) -> contains ( Reg ) ) { Reg = <ISA_LIT>RegInfo -> getSubReg ( Reg , <STR_LIT> ) ;"
LLVM,RISCV,1242,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandAuipccInstPair ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI , unsigned FlagsHi , unsigned SecondOpcode ) { MachineFunction * MF = MBB . getParent ( ) ; MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; bool HasTmpReg = MI . getNumOperands ( ) > <NUM_LIT> ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register TmpReg = MI . getOperand ( HasTmpReg ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; const MachineOperand & Symbol = MI . getOperand ( HasTmpReg ? <NUM_LIT> : <NUM_LIT> ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addDisp ( Symbol , <NUM_LIT> , FlagsHi ) ; BuildMI ( NewMBB , DL , TII -> get ( SecondOpcode ) , DestReg ) . addReg ( TmpReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ;"
LLVM,RISCV,1243,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandCapLoadGlobalCap ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {"
LLVM,RISCV,1244,"Predict the next statement of this code snippet:
 <s> unsigned SecondOpcode = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return expandAuipccInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , SecondOpcode ) ;"
LLVM,RISCV,1245,"Predict the next statement of this code snippet:
 <s> return expandAuipccInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,1246,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandCapLoadTLSGDCap ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {"
LLVM,RISCV,1247,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandCapLoadTLSGDCap ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { return expandAuipccInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,1248,"Predict the next statement of this code snippet:
 <s> unsigned SecondOpcode = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,1249,"Predict the next statement of this code snippet:
 <s> SubRegIdx = <STR_LIT> ; static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; } else if ( LMUL == <NUM_LIT> ) { Opcode = <STR_LIT> ; SubRegIdx = <STR_LIT> ; static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; } else assert ( LMUL == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) , TRI -> getSubReg ( DestReg , SubRegIdx + I ) ) . addReg ( Base ) . addMemOperand ( * ( MBBI -> memoperands_begin ( ) ) ) ; if ( I != NF - <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Base ) . addReg ( Base ) . addReg ( VL ) ;"
LLVM,RISCV,1250,"Predict the next statement of this code snippet:
 <s> } else assert ( LMUL == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) ) . addReg ( TRI -> getSubReg ( SrcReg , SubRegIdx + I ) ) . addReg ( Base ) . addMemOperand ( * ( MBBI -> memoperands_begin ( ) ) ) ; if ( I != NF - <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Base ) . addReg ( Base ) . addReg ( VL ) ; } MBBI -> eraseFromParent ( ) ;"
LLVM,RISCV,1251,"Predict the next statement of this code snippet:
 <s> static void doAtomicBinOpExpansion ( const <ISA_LIT>InstrInfo * TII , MachineInstr & MI , DebugLoc DL , MachineBasicBlock * ThisMBB , MachineBasicBlock * LoopMBB , MachineBasicBlock * DoneMBB , AtomicRMWInst :: BinOp BinOp , int Width ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ;"
LLVM,RISCV,1252,"Predict the next statement of this code snippet:
 <s> assert ( Width == <NUM_LIT> && <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default :"
LLVM,RISCV,1253,"Predict the next statement of this code snippet:
 <s> switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Add : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Sub : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Nand : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( - <NUM_LIT> ) ; break ;"
LLVM,RISCV,1254,"Predict the next statement of this code snippet:
 <s> DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CmpValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsMasked ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; if ( ! IsMasked ) { BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW ( Ordering , Width ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } else { unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; insertMaskedMerge ( TII , DL , LoopTailMBB , ScratchReg , DestReg , NewValReg , MaskReg , ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW ( Ordering , Width ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * LoopHeadMBB ) ;"
LLVM,RISCV,1255,"Predict the next statement of this code snippet:
 <s> LoopIfBodyMBB -> addSuccessor ( LoopTailMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; LoopTailMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scratch1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scratch2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsSigned = BinOp == AtomicRMWInst :: Min || BinOp == AtomicRMWInst :: Max ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsSigned ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch2Reg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch1Reg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Max : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Scratch2Reg ) . addReg ( IncrReg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: Min : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IncrReg ) . addReg ( Scratch2Reg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: UMax : BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Scratch2Reg ) . addReg ( IncrReg ) . addMBB ( LoopTailMBB ) ; break ; case AtomicRMWInst :: UMin : BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IncrReg ) . addReg ( Scratch2Reg ) . addMBB ( LoopTailMBB ) ; break ; }"
LLVM,RISCV,1256,"Predict the next statement of this code snippet:
 <s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & Symbol = MI . getOperand ( <NUM_LIT> ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addDisp ( Symbol , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( NewMBB ) ; LivePhysRegs LiveRegs ;"
LLVM,RISCV,1257,"Predict the next statement of this code snippet:
 <s> NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addDisp ( Symbol , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ;"
LLVM,RISCV,1258,"Predict the next statement of this code snippet:
 <s> switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Min , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMax , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandLoadLocalAddress ( MBB , MBBI , NextMBBI ) ; } return false ;"
LLVM,RISCV,1259,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVMSET_VMCLR ( MBB , MBBI , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVMSET_VMCLR ( MBB , MBBI , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVSPILL ( MBB , MBBI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1260,"Predict the next statement of this code snippet:
 <s> assert ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned Opcode ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; const MCInstrDesc & Desc = TII -> get ( Opcode ) ;"
LLVM,RISCV,1261,"Predict the next statement of this code snippet:
 <s> assert ( Desc . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Register DstReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MBBI -> getOperand ( <NUM_LIT> ) . isDead ( ) ;"
LLVM,RISCV,1262,"Predict the next statement of this code snippet:
 <s> AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsMasked ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; if ( ! IsMasked ) { BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW ( Ordering , Width ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } else { Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; insertMaskedMerge ( TII , DL , LoopTailMBB , ScratchReg , DestReg , NewValReg , MaskReg , ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW ( Ordering , Width ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) ;"
LLVM,RISCV,1263,"Predict the next statement of this code snippet:
 <s> assert ( Width == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoopHeadMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto LoopIfBodyMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto LoopTailMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoopHeadMBB ) ; MF -> insert ( ++ LoopHeadMBB -> getIterator ( ) , LoopIfBodyMBB ) ; MF -> insert ( ++ LoopIfBodyMBB -> getIterator ( ) , LoopTailMBB ) ; MF -> insert ( ++ LoopTailMBB -> getIterator ( ) , DoneMBB ) ; LoopHeadMBB -> addSuccessor ( LoopIfBodyMBB ) ; LoopHeadMBB -> addSuccessor ( LoopTailMBB ) ; LoopIfBodyMBB -> addSuccessor ( LoopTailMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; LoopTailMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Scratch1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Scratch2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsSigned = BinOp == AtomicRMWInst :: Min || BinOp == AtomicRMWInst :: Max ;"
LLVM,RISCV,1264,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVSetVL ( MBB , MBBI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVMSET_VMCLR ( MBB , MBBI , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVMSET_VMCLR ( MBB , MBBI , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVSPILL ( MBB , MBBI ) ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1265,"Predict the next statement of this code snippet:
 <s> bool DstIsDead = MBBI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; BuildMI ( MBB , MBBI , DL , Desc ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) ; MBBI -> eraseFromParent ( ) ; return true ;"
LLVM,RISCV,1266,"Predict the next statement of this code snippet:
 <s> assert ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned Opcode ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; const MCInstrDesc & Desc = TII -> get ( Opcode ) ; assert ( Desc . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Register DstReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MBBI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; BuildMI ( MBB , MBBI , DL , Desc ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,1267,"Predict the next statement of this code snippet:
 <s> unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & Symbol = MI . getOperand ( <NUM_LIT> ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addDisp ( Symbol , <NUM_LIT> , FlagsHi ) ; BuildMI ( NewMBB , DL , TII -> get ( SecondOpcode ) , DestReg ) . addReg ( DestReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( NewMBB ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * NewMBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; return true ;"
LLVM,RISCV,1268,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandAuipcInstPair ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI , unsigned FlagsHi , unsigned SecondOpcode ) { MachineFunction * MF = MBB . getParent ( ) ; MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & Symbol = MI . getOperand ( <NUM_LIT> ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addDisp ( Symbol , <NUM_LIT> , FlagsHi ) ; BuildMI ( NewMBB , DL , TII -> get ( SecondOpcode ) , DestReg ) . addReg ( DestReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( NewMBB ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * NewMBB ) ;"
LLVM,RISCV,1269,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ;"
LLVM,RISCV,1270,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Min , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMax , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandLoadLocalAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadAddress ( MBB , MBBI , NextMBBI ) ; }"
LLVM,RISCV,1271,"Predict the next statement of this code snippet:
 <s> SubRegIdx = <STR_LIT> ; static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; } else assert ( LMUL == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) , TRI -> getSubReg ( DestReg , SubRegIdx + I ) ) . addReg ( Base ) . addMemOperand ( * ( MBBI -> memoperands_begin ( ) ) ) ; if ( I != NF - <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , AddrInc ) . addReg ( Base ) . addReg ( VL ) ; Base = AddrInc ; } } MBBI -> eraseFromParent ( ) ;"
LLVM,RISCV,1272,"Predict the next statement of this code snippet:
 <s> static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; } else if ( LMUL == <NUM_LIT> ) { Opcode = <STR_LIT> ; SubRegIdx = <STR_LIT> ; static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; } else assert ( LMUL == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) ) . addReg ( TRI -> getSubReg ( SrcReg , SubRegIdx + I ) ) . addReg ( Base ) . addMemOperand ( * ( MBBI -> memoperands_begin ( ) ) ) ; if ( I != NF - <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , AddrInc ) . addReg ( Base ) . addReg ( VL ) ; Base = AddrInc ; } } MBBI -> eraseFromParent ( ) ;"
LLVM,RISCV,1273,"Predict the next statement of this code snippet:
 <s> static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; if ( LMUL == <NUM_LIT> ) { Opcode = <STR_LIT> ; SubRegIdx = <STR_LIT> ; static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; } else if ( LMUL == <NUM_LIT> ) { Opcode = <STR_LIT> ; SubRegIdx = <STR_LIT> ; static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; } else assert ( LMUL == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) ) . addReg ( TRI -> getSubReg ( SrcReg , SubRegIdx + I ) ) . addReg ( Base ) . addMemOperand ( * ( MBBI -> memoperands_begin ( ) ) ) ; if ( I != NF - <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , AddrInc ) . addReg ( Base ) . addReg ( VL ) ; Base = AddrInc ; } } MBBI -> eraseFromParent ( ) ; return true ;"
LLVM,RISCV,1274,"Predict the next statement of this code snippet:
 <s> static void doAtomicBinOpExpansion ( const <ISA_LIT>InstrInfo * TII , MachineInstr & MI , DebugLoc DL , MachineBasicBlock * ThisMBB , MachineBasicBlock * LoopMBB , MachineBasicBlock * DoneMBB , AtomicRMWInst :: BinOp BinOp , int Width ) { assert ( Width == <NUM_LIT> && <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,1275,"Predict the next statement of this code snippet:
 <s> static void doMaskedAtomicBinOpExpansion ( const <ISA_LIT>InstrInfo * TII , MachineInstr & MI , DebugLoc DL , MachineBasicBlock * ThisMBB , MachineBasicBlock * LoopMBB , MachineBasicBlock * DoneMBB , AtomicRMWInst :: BinOp BinOp , int Width ) { assert ( Width == <NUM_LIT> && <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,1276,"Predict the next statement of this code snippet:
 <s> MF -> insert ( ++ MBB . getIterator ( ) , LoopMBB ) ; MF -> insert ( ++ LoopMBB -> getIterator ( ) , DoneMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopMBB ) ;"
LLVM,RISCV,1277,"Predict the next statement of this code snippet:
 <s> BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } else { unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; insertMaskedMerge ( TII , DL , LoopTailMBB , ScratchReg , DestReg , NewValReg , MaskReg , ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * LoopHeadMBB ) ;"
LLVM,RISCV,1278,"Predict the next statement of this code snippet:
 <s> LoopTailMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CmpValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsMasked ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; if ( ! IsMasked ) { BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ;"
LLVM,RISCV,1279,"Predict the next statement of this code snippet:
 <s> unsigned Scratch2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsSigned = BinOp == AtomicRMWInst :: Min || BinOp == AtomicRMWInst :: Max ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsSigned ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch2Reg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch1Reg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Max : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Scratch2Reg ) . addReg ( IncrReg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: Min : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IncrReg ) . addReg ( Scratch2Reg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: UMax : BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Scratch2Reg ) . addReg ( IncrReg ) . addMBB ( LoopTailMBB ) ;"
LLVM,RISCV,1280,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( OldValReg ) . addReg ( NewValReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( MaskReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( OldValReg ) . addReg ( ScratchReg ) ;"
LLVM,RISCV,1281,"Predict the next statement of this code snippet:
 <s> assert ( OldValReg != MaskReg && <STR_LIT> ) ; assert ( ScratchReg != MaskReg && <STR_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( OldValReg ) . addReg ( NewValReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( MaskReg ) ;"
LLVM,RISCV,1282,"Predict the next statement of this code snippet:
 <s> static void insertSext ( const <ISA_LIT>InstrInfo * TII , DebugLoc DL , MachineBasicBlock * MBB , unsigned ValReg , unsigned ShamtReg ) {"
LLVM,RISCV,1283,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ValReg ) . addReg ( ValReg ) . addReg ( ShamtReg ) ;"
LLVM,RISCV,1284,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : return expandLoadLocalAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadAddress ( MBB , MBBI , NextMBBI ) ;"
LLVM,RISCV,1285,"Predict the next statement of this code snippet:
 <s> assert ( Width == <NUM_LIT> && <STR_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Add : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ;"
LLVM,RISCV,1286,"Predict the next statement of this code snippet:
 <s> static void doMaskedAtomicBinOpExpansion ( const <ISA_LIT>InstrInfo * TII , MachineInstr & MI , DebugLoc DL , MachineBasicBlock * ThisMBB , MachineBasicBlock * LoopMBB , MachineBasicBlock * DoneMBB , AtomicRMWInst :: BinOp BinOp , int Width ) { assert ( Width == <NUM_LIT> && <STR_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Add : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Sub : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Nand : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( - <NUM_LIT> ) ; break ; } insertMaskedMerge ( TII , DL , LoopMBB , ScratchReg , DestReg , ScratchReg , MaskReg , ScratchReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) ;"
LLVM,RISCV,1287,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Min , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMax , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , <NUM_LIT> , NextMBBI ) ;"
LLVM,RISCV,1288,"Predict the next statement of this code snippet:
 <s> return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ;"
LLVM,RISCV,1289,"Predict the next statement of this code snippet:
 <s> switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> :"
LLVM,RISCV,1290,"Predict the next statement of this code snippet:
 <s> switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : return expandLoadLocalAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadTLSIEAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadTLSGDAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandVSetVL ( MBB , MBBI ) ; } return false ;"
LLVM,RISCV,1291,"Predict the next statement of this code snippet:
 <s> FunctionPass * create<ISA_LIT>ExpandPseudoPass ( ) { return new <ISA_LIT>ExpandPseudo ( ) ;"
LLVM,RISCV,1292,"Predict the next statement of this code snippet:
 <s> FunctionPass * create<ISA_LIT>ExpandPseudoPass ( ) {"
LLVM,RISCV,1293,"Predict the next statement of this code snippet:
 <s> NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addDisp ( Symbol , <NUM_LIT> , FlagsHi ) ; BuildMI ( NewMBB , DL , TII -> get ( SecondOpcode ) , DestReg ) . addReg ( DestReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ;"
LLVM,RISCV,1294,"Predict the next statement of this code snippet:
 <s> MachineFunction * MF = MBB . getParent ( ) ; unsigned SecondOpcode ; unsigned FlagsHi ; if ( MF -> getTarget ( ) . isPositionIndependent ( ) ) { const auto & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; SecondOpcode = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; FlagsHi = <STR_LIT> ;"
LLVM,RISCV,1295,"Predict the next statement of this code snippet:
 <s> const auto & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; SecondOpcode = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; FlagsHi = <STR_LIT> ; } else { SecondOpcode = <STR_LIT> ; FlagsHi = <STR_LIT> ; }"
LLVM,RISCV,1296,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandLoadLocalAddress ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { return expandAuipcInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,1297,"Predict the next statement of this code snippet:
 <s> return expandAuipcInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,1298,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandLoadTLSGDAddress ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {"
LLVM,RISCV,1299,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandLoadTLSGDAddress ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {"
LLVM,RISCV,1300,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandMBB ( MachineBasicBlock & MBB ) { bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= expandMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ; }"
LLVM,RISCV,1301,"Predict the next statement of this code snippet:
 <s> const MCInstrDesc & Desc = TII -> get ( Opcode ) ; BuildMI ( MBB , MBBI , DL , Desc , DstReg ) . addReg ( DstReg , RegState :: Undef ) . addReg ( DstReg , RegState :: Undef ) ; MBBI -> eraseFromParent ( ) ; return true ;"
LLVM,RISCV,1302,"Predict the next statement of this code snippet:
 <s> const MCInstrDesc & Desc = TII -> get ( Opcode ) ; BuildMI ( MBB , MBBI , DL , Desc , DstReg ) . addReg ( DstReg , RegState :: Undef ) . addReg ( DstReg , RegState :: Undef ) ; MBBI -> eraseFromParent ( ) ; return true ;"
LLVM,RISCV,1303,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ExpandPseudo :: expandVSetVL ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { assert ( MBBI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,1304,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , DL , Desc ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,1305,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <ISA_LIT>_EXPAND_PSEUDO_NAME ;"
LLVM,RISCV,1306,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override {"
LLVM,RISCV,1307,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,1308,"Predict the next statement of this code snippet:
 <s> for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ;"
LLVM,RISCV,1309,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned FP = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) SavedRegs . set ( FP ) ; if ( <ISA_LIT>FI -> getCallsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( ) ;"
LLVM,RISCV,1310,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>FrameLowering :: ehDataReg ( unsigned I ) const {"
LLVM,RISCV,1311,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; unsigned SP = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ;"
LLVM,RISCV,1312,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned SP = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FP = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ;"
LLVM,RISCV,1313,"Predict the next statement of this code snippet:
 <s> unsigned ZERO = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . adjustStackPtr ( SP , - StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; for ( const auto & I : CSI ) { int64_t Offset = MFI -> getObjectOffset ( I . getFrameIdx ( ) ) ; unsigned Reg = I . getReg ( ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , <NUM_LIT> ) , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( <ISA_LIT>FI -> getCallsEhReturn ( ) ) { const TargetRegisterClass * RC = & <STR_LIT> ;"
LLVM,RISCV,1314,"Predict the next statement of this code snippet:
 <s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ;"
LLVM,RISCV,1315,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI -> hasVarSizedObjects ( ) ;"
LLVM,RISCV,1316,"Predict the next statement of this code snippet:
 <s> return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI -> hasVarSizedObjects ( ) ;"
LLVM,RISCV,1317,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {"
LLVM,RISCV,1318,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {"
LLVM,RISCV,1319,"Predict the next statement of this code snippet:
 <s> int64_t MaxPosAdjStep = <NUM_LIT> - getStackAlign ( ) . value ( ) ; if ( Val > - <NUM_LIT> && Val <= ( <NUM_LIT> * MaxPosAdjStep ) ) { int64_t FirstAdj = Val < <NUM_LIT> ? - <NUM_LIT> : MaxPosAdjStep ; Val -= FirstAdj ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( FirstAdj ) . setMIFlag ( Flag ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( Val ) . setMIFlag ( Flag ) ; return ; } unsigned Opc = <STR_LIT> ; if ( Val < <NUM_LIT> ) { Val = - Val ; Opc = <STR_LIT> ; } Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , MBBI , DL , ScratchReg , Val , Flag ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addReg ( ScratchReg , RegState :: Kill ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,1320,"Predict the next statement of this code snippet:
 <s> return ; } assert ( getStackAlign ( ) . value ( ) < <NUM_LIT> && <STR_LIT> ) ; int64_t MaxPosAdjStep = <NUM_LIT> - getStackAlign ( ) . value ( ) ; if ( Val > - <NUM_LIT> && Val <= ( <NUM_LIT> * MaxPosAdjStep ) ) { int64_t FirstAdj = Val < <NUM_LIT> ? - <NUM_LIT> : MaxPosAdjStep ; Val -= FirstAdj ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( FirstAdj ) . setMIFlag ( Flag ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( Val ) . setMIFlag ( Flag ) ; return ; } unsigned Opc = <STR_LIT> ; if ( Val < <NUM_LIT> ) { Val = - Val ; Opc = <STR_LIT> ; } Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , MBBI , DL , ScratchReg , Val , Flag ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addReg ( ScratchReg , RegState :: Kill ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,1321,"Predict the next statement of this code snippet:
 <s> Register FactorRegister = TII -> getVLENFactoredAmount ( MF , MBB , MBBI , DL , Amount , Flag ) ;"
LLVM,RISCV,1322,"Predict the next statement of this code snippet:
 <s> unsigned Opc = <STR_LIT> ; if ( Amount < <NUM_LIT> ) { Amount = - Amount ; Opc = <STR_LIT> ; } Register FactorRegister = TII -> getVLENFactoredAmount ( MF , MBB , MBBI , DL , Amount , Flag ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , SPReg ) . addReg ( SPReg ) . addReg ( FactorRegister , RegState :: Kill ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,1323,"Predict the next statement of this code snippet:
 <s> unsigned StackID = MFI . getStackID ( I ) ; if ( StackID != TargetStackID :: ScalableVector ) continue ; if ( MFI . isDeadObjectIndex ( I ) ) continue ; ObjectsToAllocate . push_back ( I ) ; } int64_t Offset = <NUM_LIT> ; Align RVVStackAlign ( <NUM_LIT> ) ; for ( int FI : ObjectsToAllocate ) { int64_t ObjectSize = MFI . getObjectSize ( FI ) ; auto ObjectAlign = std :: max ( Align ( <NUM_LIT> ) , MFI . getObjectAlign ( FI ) ) ; if ( ObjectSize < <NUM_LIT> ) ObjectSize = <NUM_LIT> ; Offset = alignTo ( Offset + ObjectSize , ObjectAlign ) ; MFI . setObjectOffset ( FI , - Offset ) ; RVVStackAlign = std :: max ( RVVStackAlign , ObjectAlign ) ; } uint64_t StackSize = Offset ;"
LLVM,RISCV,1324,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const auto * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( * MF ) ) return true ;"
LLVM,RISCV,1325,"Predict the next statement of this code snippet:
 <s> SavedRegs . set ( <STR_LIT> ) ; } if ( hasBP ( MF ) ) SavedRegs . set ( <STR_LIT> ( ) ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; Regs [ i ] ; ++ i ) if ( <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; }"
LLVM,RISCV,1326,"Predict the next statement of this code snippet:
 <s> if ( hasBP ( MF ) ) SavedRegs . set ( <STR_LIT> ( ) ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ;"
LLVM,RISCV,1327,"Predict the next statement of this code snippet:
 <s> auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;"
LLVM,RISCV,1328,"Predict the next statement of this code snippet:
 <s> DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ;"
LLVM,RISCV,1329,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; MBBI = MBB . getFirstTerminator ( ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = getStackSizeWithRVVPadding ( MF ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = getStackSizeWithRVVPadding ( MF ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ;"
LLVM,RISCV,1330,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; MBBI = MBB . getFirstTerminator ( ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = getStackSizeWithRVVPadding ( MF ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = getStackSizeWithRVVPadding ( MF ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ;"
LLVM,RISCV,1331,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , RealStackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , RVFI -> getVarArgsSaveSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = getStackSizeWithRVVPadding ( MF ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , getStackSizeWithRVVPadding ( MF ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , MBBI , DL , - RVVStackSize , MachineInstr :: FrameSetup ) ; if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> hasStackRealignment ( MF ) ) { Align MaxAlignment = MFI . getMaxAlign ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment . value ( ) ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment . value ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else {"
LLVM,RISCV,1332,"Predict the next statement of this code snippet:
 <s> const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ; std :: vector < CalleeSavedInfo > & CSI = MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ; if ( std :: none_of ( CSI . begin ( ) , CSI . end ( ) , [ & ] ( CalleeSavedInfo & CSR ) { return CSR . getReg ( ) == RAReg ; } ) ) return ; Register SCSPReg = <STR_LIT> ( ) ; auto & Ctx = MF . getFunction ( ) . getContext ( ) ; if ( ! STI . isRegisterReservedByUser ( SCSPReg ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( RVFI -> useSaveRestoreLibCalls ( MF ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ;"
LLVM,RISCV,1333,"Predict the next statement of this code snippet:
 <s> } const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; bool IsRV64 = STI . hasFeature ( <STR_LIT> ) ; int64_t SlotSize = STI . getXLen ( ) / <NUM_LIT> ; BuildMI ( MBB , MI , DL , TII -> get ( IsRV64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RAReg ) . addReg ( SCSPReg ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;"
LLVM,RISCV,1334,"Predict the next statement of this code snippet:
 <s> if ( RVFI -> getLibCallStackSize ( ) ) return <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( StackSize ) && ( CSI . size ( ) > <NUM_LIT> ) ) {"
LLVM,RISCV,1335,"Predict the next statement of this code snippet:
 <s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; uint64_t StackSize = getStackSizeWithRVVPadding ( MF ) ; if ( RVFI -> getLibCallStackSize ( ) ) return <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( StackSize ) && ( CSI . size ( ) > <NUM_LIT> ) ) {"
LLVM,RISCV,1336,"Predict the next statement of this code snippet:
 <s> static Register getFPReg ( const <ISA_LIT>Subtarget & STI ) {"
LLVM,RISCV,1337,"Predict the next statement of this code snippet:
 <s> if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += StackOffset :: getFixed ( FirstSPAdjustAmount ) ; else Offset += StackOffset :: getFixed ( getStackSizeWithRVVPadding ( MF ) ) ; return Offset ; } if ( RI -> hasStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) { FrameReg = <STR_LIT> ( ) ; } else { assert ( ! MFI . hasVarSizedObjects ( ) ) ; FrameReg = <STR_LIT> ; } } else { FrameReg = RI -> getFrameRegister ( MF ) ; } if ( FrameReg == getFPReg ( STI ) ) { Offset += StackOffset :: getFixed ( RVFI -> getVarArgsSaveSize ( ) ) ; if ( FI >= <NUM_LIT> ) Offset -= StackOffset :: getFixed ( RVFI -> getLibCallStackSize ( ) ) ; if ( MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ) { assert ( ! RI -> hasStackRealignment ( MF ) && <STR_LIT> ) ; assert ( MFI . getStackSize ( ) == getStackSizeWithRVVPadding ( MF ) && <STR_LIT> ) ; Offset -= StackOffset :: getFixed ( MFI . getStackSize ( ) ) ; } return Offset ; } assert ( FrameReg == <STR_LIT> ( ) || ! MFI . hasVarSizedObjects ( ) ) ; if ( MFI . getStackID ( FI ) == TargetStackID :: Default ) { if ( MFI . isFixedObjectIndex ( FI ) ) { assert ( ! RI -> hasStackRealignment ( MF ) && <STR_LIT> ) ; Offset += StackOffset :: get ( getStackSizeWithRVVPadding ( MF ) + RVFI -> getLibCallStackSize ( ) , RVFI -> getRVVStackSize ( ) ) ; } else { Offset += StackOffset :: getFixed ( MFI . getStackSize ( ) ) ; } } else if ( MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ) { int ScalarLocalVarSize = MFI . getStackSize ( ) - RVFI -> getCalleeSavedStackSize ( ) - RVFI -> getVarArgsSaveSize ( ) + RVFI -> getRVVPadding ( ) ; Offset += StackOffset :: get ( ScalarLocalVarSize , RVFI -> getRVVStackSize ( ) ) ;"
LLVM,RISCV,1338,"Predict the next statement of this code snippet:
 <s> static int getLibCallID ( const MachineFunction & MF , const std :: vector < CalleeSavedInfo > & CSI ) { const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( CSI . empty ( ) || ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return - <NUM_LIT> ; Register MaxReg = <STR_LIT> ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) < <NUM_LIT> ) MaxReg = std :: max ( MaxReg . id ( ) , CS . getReg ( ) . id ( ) ) ; if ( MaxReg == <STR_LIT> ) return - <NUM_LIT> ; switch ( MaxReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;"
LLVM,RISCV,1339,"Predict the next statement of this code snippet:
 <s> int LibCallID = getLibCallID ( MF , CSI ) ; if ( LibCallID == - <NUM_LIT> ) return nullptr ; return RestoreLibCalls [ LibCallID ] ;"
LLVM,RISCV,1340,"Predict the next statement of this code snippet:
 <s> static const char * getSpillLibCallName ( const MachineFunction & MF , const std :: vector < CalleeSavedInfo > & CSI ) { static const char * const SpillLibCalls [ ] = {"
LLVM,RISCV,1341,"Predict the next statement of this code snippet:
 <s> static Register getSPReg ( const <ISA_LIT>Subtarget & STI ) {"
LLVM,RISCV,1342,"Predict the next statement of this code snippet:
 <s> static Register getSPReg ( const <ISA_LIT>Subtarget & STI ) {"
LLVM,RISCV,1343,"Predict the next statement of this code snippet:
 <s> return TargetStackID :: ScalableVector ;"
LLVM,RISCV,1344,"Predict the next statement of this code snippet:
 <s> TargetStackID :: Value <ISA_LIT>FrameLowering :: getStackIDForScalableVectors ( ) const {"
LLVM,RISCV,1345,"Predict the next statement of this code snippet:
 <s> return alignTo ( MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) , getStackAlign ( ) ) ;"
LLVM,RISCV,1346,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return ( MFI . hasVarSizedObjects ( ) || ( ! hasReservedCallFrame ( MF ) && ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) != <NUM_LIT> ) ) ) && TRI -> hasStackRealignment ( MF ) ;"
LLVM,RISCV,1347,"Predict the next statement of this code snippet:
 <s> return ( MFI . hasVarSizedObjects ( ) || ( ! hasReservedCallFrame ( MF ) && ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) != <NUM_LIT> ) ) ) && TRI -> hasStackRealignment ( MF ) ;"
LLVM,RISCV,1348,"Predict the next statement of this code snippet:
 <s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;"
LLVM,RISCV,1349,"Predict the next statement of this code snippet:
 <s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;"
LLVM,RISCV,1350,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const {"
LLVM,RISCV,1351,"Predict the next statement of this code snippet:
 <s> return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! ( hasFP ( MF ) && hasRVVFrameObject ( MF ) ) ;"
LLVM,RISCV,1352,"Predict the next statement of this code snippet:
 <s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasVInstructions ( ) ;"
LLVM,RISCV,1353,"Predict the next statement of this code snippet:
 <s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasVInstructions ( ) ;"
LLVM,RISCV,1354,"Predict the next statement of this code snippet:
 <s> return any_of ( MF , [ & TII ] ( const MachineBasicBlock & MBB ) { return any_of ( MBB , [ & TII ] ( const MachineInstr & MI ) { return TII . isRVVSpill ( MI , true ) ; } ) ; } ) ;"
LLVM,RISCV,1355,"Predict the next statement of this code snippet:
 <s> return any_of ( MF , [ & TII ] ( const MachineBasicBlock & MBB ) { return any_of ( MBB , [ & TII ] ( const MachineInstr & MI ) { return TII . isRVVSpill ( MI , true ) ; } ) ; } ) ;"
LLVM,RISCV,1356,"Predict the next statement of this code snippet:
 <s> switch ( ID ) { case TargetStackID :: Default : case TargetStackID :: ScalableVector : return true ; case TargetStackID :: NoAlloc :"
LLVM,RISCV,1357,"Predict the next statement of this code snippet:
 <s> if ( RVVStackSize != <NUM_LIT> ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( <NUM_LIT> ) ; return ; } unsigned Size = <NUM_LIT> ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) {"
LLVM,RISCV,1358,"Predict the next statement of this code snippet:
 <s> if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( * MF , CSI ) ; for ( auto & CS : NonLibcallCSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; } const char * RestoreLibCall = getRestoreLibCallName ( * MF , CSI ) ; if ( RestoreLibCall ) { MachineBasicBlock :: iterator NewMI = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( RestoreLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ;"
LLVM,RISCV,1359,"Predict the next statement of this code snippet:
 <s> MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( SpillLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn ( CS . getReg ( ) ) ; } const auto & NonLibcallCSI = getNonLibcallCSI ( * MF , CSI ) ; for ( auto & CS : NonLibcallCSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! MBB . isLiveIn ( Reg ) , CS . getFrameIdx ( ) , RC , TRI ) ; }"
LLVM,RISCV,1360,"Predict the next statement of this code snippet:
 <s> if ( isInt < <NUM_LIT> > ( Val ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( Val ) . setMIFlag ( Flag ) ; } else if ( isInt < <NUM_LIT> > ( Val ) ) { unsigned Opc = <STR_LIT> ; bool isSub = Val < <NUM_LIT> ; if ( isSub ) {"
LLVM,RISCV,1361,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( Val ) . setMIFlag ( Flag ) ; } else if ( isInt < <NUM_LIT> > ( Val ) ) { unsigned Opc = <STR_LIT> ; bool isSub = Val < <NUM_LIT> ; if ( isSub ) { Val = - Val ; Opc = <STR_LIT> ; } unsigned ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm32 ( MBB , MBBI , DL , ScratchReg , Val , Flag ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addReg ( ScratchReg , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { report_fatal_error ( <STR_LIT> ) ; }"
LLVM,RISCV,1362,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtD ( ) || MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; Regs [ i ] ; ++ i ) if ( <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; }"
LLVM,RISCV,1363,"Predict the next statement of this code snippet:
 <s> static const MCPhysReg CSRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtD ( ) || MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; Regs [ i ] ; ++ i ) if ( <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; }"
LLVM,RISCV,1364,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ;"
LLVM,RISCV,1365,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ;"
LLVM,RISCV,1366,"Predict the next statement of this code snippet:
 <s> if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } }"
LLVM,RISCV,1367,"Predict the next statement of this code snippet:
 <s> if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI ) ;"
LLVM,RISCV,1368,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ;"
LLVM,RISCV,1369,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ;"
LLVM,RISCV,1370,"Predict the next statement of this code snippet:
 <s> if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ;"
LLVM,RISCV,1371,"Predict the next statement of this code snippet:
 <s> static unsigned getFPReg ( const <ISA_LIT>Subtarget & STI ) { return <STR_LIT> ;"
LLVM,RISCV,1372,"Predict the next statement of this code snippet:
 <s> TargetStackID :: Value getStackIDForScalableVectors ( ) const override { return TargetStackID :: <ISA_LIT>Vector ;"
LLVM,RISCV,1373,"Predict the next statement of this code snippet:
 <s> case TargetStackID :: Default : case TargetStackID :: <ISA_LIT>Vector :"
LLVM,RISCV,1374,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) {"
LLVM,RISCV,1375,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlignment ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ;"
LLVM,RISCV,1376,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) , STI ( STI ) {"
LLVM,RISCV,1377,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) , STI ( STI ) {"
LLVM,RISCV,1378,"Predict the next statement of this code snippet:
 <s> for ( int FI : ObjectsToAllocate ) { int64_t ObjectSize = MFI . getObjectSize ( FI ) ; if ( ObjectSize < <NUM_LIT> ) ObjectSize = <NUM_LIT> ; Offset = alignTo ( Offset + ObjectSize , <NUM_LIT> ) ; MFI . setObjectOffset ( FI , - Offset ) ; }"
LLVM,RISCV,1379,"Predict the next statement of this code snippet:
 <s> for ( int FI : ObjectsToAllocate ) { int64_t ObjectSize = MFI . getObjectSize ( FI ) ; if ( ObjectSize < <NUM_LIT> ) ObjectSize = <NUM_LIT> ; Offset = alignTo ( Offset + ObjectSize , <NUM_LIT> ) ; MFI . setObjectOffset ( FI , - Offset ) ; } return Offset ;"
LLVM,RISCV,1380,"Predict the next statement of this code snippet:
 <s> uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ;"
LLVM,RISCV,1381,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ;"
LLVM,RISCV,1382,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,1383,"Predict the next statement of this code snippet:
 <s> if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , MBBI , DL , - RVVStackSize , MachineInstr :: FrameSetup ) ; if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> hasStackRealignment ( MF ) ) { Align MaxAlignment = MFI . getMaxAlign ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment . value ( ) ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment . value ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { unsigned ShiftAmount = Log2 ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) . setMIFlag ( MachineInstr :: FrameSetup ) ; }"
LLVM,RISCV,1384,"Predict the next statement of this code snippet:
 <s> int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; if ( RVVStackSize != <NUM_LIT> ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( <NUM_LIT> ) ; return ; } unsigned Size = <NUM_LIT> ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ; if ( MFI . getStackID ( FrameIdx ) != TargetStackID :: Default ) continue ; Size += MFI . getObjectSize ( FrameIdx ) ; }"
LLVM,RISCV,1385,"Predict the next statement of this code snippet:
 <s> if ( RVVStackSize != <NUM_LIT> ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( <NUM_LIT> ) ; return ; } unsigned Size = <NUM_LIT> ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ; if ( MFI . getStackID ( FrameIdx ) != TargetStackID :: Default ) continue ; Size += MFI . getObjectSize ( FrameIdx ) ; } RVFI -> setCalleeSavedStackSize ( Size ) ;"
LLVM,RISCV,1386,"Predict the next statement of this code snippet:
 <s> if ( MF . getFunction ( ) . hasOptNone ( ) ) return false ; return true ;"
LLVM,RISCV,1387,"Predict the next statement of this code snippet:
 <s> if ( MF . getFunction ( ) . hasOptNone ( ) ) return false ; return true ;"
LLVM,RISCV,1388,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MFI . hasVarSizedObjects ( ) && TRI -> hasStackRealignment ( MF ) ;"
LLVM,RISCV,1389,"Predict the next statement of this code snippet:
 <s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;"
LLVM,RISCV,1390,"Predict the next statement of this code snippet:
 <s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; for ( int I = <NUM_LIT> , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) if ( MFI . getStackID ( I ) == TargetStackID :: ScalableVector ) return true ;"
LLVM,RISCV,1391,"Predict the next statement of this code snippet:
 <s> if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtV ( ) ) return false ;"
LLVM,RISCV,1392,"Predict the next statement of this code snippet:
 <s> if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( * MF , CSI ) ; for ( auto & CS : reverse ( NonLibcallCSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; } const char * RestoreLibCall = getRestoreLibCallName ( * MF , CSI ) ; if ( RestoreLibCall ) { MachineBasicBlock :: iterator NewMI = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( RestoreLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ;"
LLVM,RISCV,1393,"Predict the next statement of this code snippet:
 <s> MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( * MF , CSI ) ; for ( auto & CS : reverse ( NonLibcallCSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ;"
LLVM,RISCV,1394,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {"
LLVM,RISCV,1395,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {"
LLVM,RISCV,1396,"Predict the next statement of this code snippet:
 <s> MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( SpillLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn ( CS . getReg ( ) ) ;"
LLVM,RISCV,1397,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ;"
LLVM,RISCV,1398,"Predict the next statement of this code snippet:
 <s> uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ;"
LLVM,RISCV,1399,"Predict the next statement of this code snippet:
 <s> if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ;"
LLVM,RISCV,1400,"Predict the next statement of this code snippet:
 <s> if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ; } if ( FirstSPAdjustAmount ) StackSize = FirstSPAdjustAmount ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , StackSize , MachineInstr :: FrameDestroy ) ;"
LLVM,RISCV,1401,"Predict the next statement of this code snippet:
 <s> FrameSize += ( MaxStackAlign - StackAlign ) ; StackAlign = MaxStackAlign ; } uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ;"
LLVM,RISCV,1402,"Predict the next statement of this code snippet:
 <s> DebugLoc DL = MBBI -> getDebugLoc ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; }"
LLVM,RISCV,1403,"Predict the next statement of this code snippet:
 <s> uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ; } if ( FirstSPAdjustAmount ) StackSize = FirstSPAdjustAmount ;"
LLVM,RISCV,1404,"Predict the next statement of this code snippet:
 <s> adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { unsigned ShiftAmount = countTrailingZeros ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ;"
LLVM,RISCV,1405,"Predict the next statement of this code snippet:
 <s> int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { unsigned ShiftAmount = countTrailingZeros ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ; } if ( hasBP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , BPReg ) . addReg ( SPReg ) . addImm ( <NUM_LIT> ) ; } }"
LLVM,RISCV,1406,"Predict the next statement of this code snippet:
 <s> uint64_t StackAlign = getStackAlignment ( ) ; if ( ! isInt < <NUM_LIT> > ( StackSize ) && ( CSI . size ( ) > <NUM_LIT> ) ) {"
LLVM,RISCV,1407,"Predict the next statement of this code snippet:
 <s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;"
LLVM,RISCV,1408,"Predict the next statement of this code snippet:
 <s> if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ;"
LLVM,RISCV,1409,"Predict the next statement of this code snippet:
 <s> if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return true ; if ( MBB . succ_size ( ) > <NUM_LIT> ) return false ;"
LLVM,RISCV,1410,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const auto * RVFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return true ; RegScavenger RS ; RS . enterBasicBlock ( * TmpMBB ) ;"
LLVM,RISCV,1411,"Predict the next statement of this code snippet:
 <s> const auto * RVFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return true ;"
LLVM,RISCV,1412,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ;"
LLVM,RISCV,1413,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ;"
LLVM,RISCV,1414,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const auto & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , getNonLibcallCSI ( CSI ) . size ( ) ) ; for ( const auto & Entry : CSI ) { int FrameIdx = Entry . getFrameIdx ( ) ; int64_t Offset ; if ( FrameIdx < <NUM_LIT> ) Offset = FrameIdx * ( int64_t ) STI . getXLen ( ) / <NUM_LIT> ; else Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) - RVFI -> getLibCallStackSize ( ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , RealStackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , RVFI -> getVarArgsSaveSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ;"
LLVM,RISCV,1415,"Predict the next statement of this code snippet:
 <s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( CSI . empty ( ) || ! RVFI -> useSaveRestoreLibCalls ( ) ) return - <NUM_LIT> ; Register MaxReg = <STR_LIT> ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) < <NUM_LIT> ) MaxReg = std :: max ( MaxReg . id ( ) , CS . getReg ( ) ) ; if ( MaxReg == <STR_LIT> ) return - <NUM_LIT> ; switch ( MaxReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;"
LLVM,RISCV,1416,"Predict the next statement of this code snippet:
 <s> Register MaxReg = <STR_LIT> ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) < <NUM_LIT> ) MaxReg = std :: max ( MaxReg . id ( ) , CS . getReg ( ) ) ; if ( MaxReg == <STR_LIT> ) return - <NUM_LIT> ; switch ( MaxReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;"
LLVM,RISCV,1417,"Predict the next statement of this code snippet:
 <s> else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= <NUM_LIT> ) Offset -= RVFI -> getLibCallStackSize ( ) ;"
LLVM,RISCV,1418,"Predict the next statement of this code snippet:
 <s> SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT> ) ; } if ( hasBP ( MF ) ) SavedRegs . set ( <STR_LIT> ( ) ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtD ( ) || MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; Regs [ i ] ; ++ i ) if ( <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; }"
LLVM,RISCV,1419,"Predict the next statement of this code snippet:
 <s> uint64_t FrameSize = MFI . getStackSize ( ) ; for ( int ID = MFI . getObjectIndexBegin ( ) , EID = MFI . getObjectIndexEnd ( ) ; ID < EID ; ID ++ ) { if ( MFI . getStackID ( ID ) == TargetStackID :: <ISA_LIT>Vector && ! MFI . isDeadObjectIndex ( ID ) ) { FrameSize = alignTo ( FrameSize , TRI -> getSpillAlignment ( <STR_LIT> ) ) ;"
LLVM,RISCV,1420,"Predict the next statement of this code snippet:
 <s> while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || RVFI -> hasSpillVRs ( ) ) {"
LLVM,RISCV,1421,"Predict the next statement of this code snippet:
 <s> if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) {"
LLVM,RISCV,1422,"Predict the next statement of this code snippet:
 <s> const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= <NUM_LIT> ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } }"
LLVM,RISCV,1423,"Predict the next statement of this code snippet:
 <s> auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;"
LLVM,RISCV,1424,"Predict the next statement of this code snippet:
 <s> auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return ( ( MFI . hasVarSizedObjects ( ) || RVFI -> hasSpillVRs ( ) ) && TRI -> needsStackRealignment ( MF ) ) ;"
LLVM,RISCV,1425,"Predict the next statement of this code snippet:
 <s> auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;"
LLVM,RISCV,1426,"Predict the next statement of this code snippet:
 <s> if ( MFI . getStackID ( FI ) == TargetStackID :: <ISA_LIT>Vector && ! MFI . isDeadObjectIndex ( FI ) ) RVFI -> setHasSpillVRs ( ) ; } if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; }"
LLVM,RISCV,1427,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; Register SPReg = getSPReg ( ) ; unsigned Opc = <STR_LIT> ; if ( Amount < <NUM_LIT> ) { Amount = - Amount ; Opc = <STR_LIT> ; } Register FactorRegister = TII -> getVLENFactoredAmount ( MF , MBB , MBBI , DL , Amount , Flag ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , SPReg ) . addReg ( SPReg ) . addReg ( FactorRegister , RegState :: Kill ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,1428,"Predict the next statement of this code snippet:
 <s> static const MCPhysReg CSGPCRs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; ArrayRef < MCPhysReg > CSRegs ; if ( <STR_LIT> ( STI . getTargetABI ( ) ) ) CSRegs = CSGPCRs ; else CSRegs = CSGPRs ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; Regs [ i ] ; ++ i ) if ( <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; } }"
LLVM,RISCV,1429,"Predict the next statement of this code snippet:
 <s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Opcode = MI -> getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) == <STR_LIT> ( STI . getTargetABI ( ) ) && <STR_LIT> ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI ) ;"
LLVM,RISCV,1430,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( ) ; Register SPReg = getSPReg ( ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ;"
LLVM,RISCV,1431,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>FrameLowering :: getFPReg ( ) const { if ( <STR_LIT> ( STI . getTargetABI ( ) ) ) return <STR_LIT> ;"
LLVM,RISCV,1432,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>FrameLowering :: getSPReg ( ) const { if ( <STR_LIT> ( STI . getTargetABI ( ) ) ) return <STR_LIT> ;"
LLVM,RISCV,1433,"Predict the next statement of this code snippet:
 <s> int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; if ( RVVStackSize != <NUM_LIT> ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( <NUM_LIT> ) ; return ; } unsigned Size = <NUM_LIT> ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ; if ( MFI . getStackID ( FrameIdx ) != TargetStackID :: Default ) continue ; Size += MFI . getObjectSize ( FrameIdx ) ;"
LLVM,RISCV,1434,"Predict the next statement of this code snippet:
 <s> TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; } const char * RestoreLibCall = getRestoreLibCallName ( * MF , CSI ) ; if ( RestoreLibCall ) { assert ( ! <STR_LIT> ( STI . getTargetABI ( ) ) && <STR_LIT> ) ; MachineBasicBlock :: iterator NewMI = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( RestoreLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; if ( MI != MBB . end ( ) && MI -> getOpcode ( ) == <STR_LIT> ) { NewMI -> copyImplicitOps ( * MF , * MI ) ; MI -> eraseFromParent ( ) ;"
LLVM,RISCV,1435,"Predict the next statement of this code snippet:
 <s> if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( * MF , CSI ) ; for ( auto & CS : reverse ( NonLibcallCSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;"
LLVM,RISCV,1436,"Predict the next statement of this code snippet:
 <s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t StackAlign = getStackAlignment ( ) ; if ( RVFI -> getLibCallStackSize ( ) ) return <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( StackSize ) && ( CSI . size ( ) > <NUM_LIT> ) ) { return <NUM_LIT> - StackAlign ;"
LLVM,RISCV,1437,"Predict the next statement of this code snippet:
 <s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t StackAlign = getStackAlignment ( ) ; if ( RVFI -> getLibCallStackSize ( ) ) return <NUM_LIT> ;"
LLVM,RISCV,1438,"Predict the next statement of this code snippet:
 <s> int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ;"
LLVM,RISCV,1439,"Predict the next statement of this code snippet:
 <s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= <NUM_LIT> ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ;"
LLVM,RISCV,1440,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; } auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ;"
LLVM,RISCV,1441,"Predict the next statement of this code snippet:
 <s> if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { unsigned ShiftAmount = countTrailingZeros ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ; } if ( hasBP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , BPReg ) . addReg ( SPReg ) . addImm ( <NUM_LIT> ) ; }"
LLVM,RISCV,1442,"Predict the next statement of this code snippet:
 <s> std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , - RVFI -> getVarArgsSaveSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;"
LLVM,RISCV,1443,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {"
LLVM,RISCV,1444,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {"
LLVM,RISCV,1445,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {"
LLVM,RISCV,1446,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {"
LLVM,RISCV,1447,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ;"
LLVM,RISCV,1448,"Predict the next statement of this code snippet:
 <s> } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) { Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , RI -> getDwarfRegNum ( Reg , true ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } adjustReg ( MBB , MBBI , DL , SPReg , SPReg , StackSize , MachineInstr :: FrameDestroy ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> ) ) ;"
LLVM,RISCV,1449,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) { const DataLayout & DL = MF . getDataLayout ( ) ;"
LLVM,RISCV,1450,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ;"
LLVM,RISCV,1451,"Predict the next statement of this code snippet:
 <s> Register FactorRegister = TII -> getVLENFactoredAmount ( MF , MBB , MBBI , DL , Amount ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , SPReg ) . addReg ( SPReg ) . addReg ( FactorRegister , RegState :: Kill ) ;"
LLVM,RISCV,1452,"Predict the next statement of this code snippet:
 <s> Amount = - Amount ; Opc = <STR_LIT> ; } Register FactorRegister = TII -> getVLENFactoredAmount ( MF , MBB , MBBI , DL , Amount ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , SPReg ) . addReg ( SPReg ) . addReg ( FactorRegister , RegState :: Kill ) ;"
LLVM,RISCV,1453,"Predict the next statement of this code snippet:
 <s> if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ;"
LLVM,RISCV,1454,"Predict the next statement of this code snippet:
 <s> if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) {"
LLVM,RISCV,1455,"Predict the next statement of this code snippet:
 <s> int FrameIdx = Entry . getFrameIdx ( ) ; int64_t Offset ; if ( FrameIdx < <NUM_LIT> ) Offset = FrameIdx * ( int64_t ) STI . getXLen ( ) / <NUM_LIT> ; else Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) - RVFI -> getLibCallStackSize ( ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , RealStackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , RVFI -> getVarArgsSaveSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , MBBI , DL , - RVVStackSize ) ; if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ;"
LLVM,RISCV,1456,"Predict the next statement of this code snippet:
 <s> case TargetStackID :: ScalableVector : return true ; case TargetStackID :: NoAlloc : case TargetStackID :: SGPRSpill : return false ; }"
LLVM,RISCV,1457,"Predict the next statement of this code snippet:
 <s> int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; if ( RVVStackSize != <NUM_LIT> ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( <NUM_LIT> ) ; return ; } unsigned Size = <NUM_LIT> ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ;"
LLVM,RISCV,1458,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( <STR_LIT> ) ;"
LLVM,RISCV,1459,"Predict the next statement of this code snippet:
 <s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;"
LLVM,RISCV,1460,"Predict the next statement of this code snippet:
 <s> unsigned SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator LastFrameDestroy = MBBI ; std :: advance ( LastFrameDestroy , - MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ;"
LLVM,RISCV,1461,"Predict the next statement of this code snippet:
 <s> Register BPReg = <STR_LIT> ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL ; determineFrameLayout ( MF ) ; if ( int LibCallRegs = getLibCallID ( MF , MFI . getCalleeSavedInfo ( ) ) + <NUM_LIT> ) { unsigned LibCallFrameSize = alignTo ( ( STI . getXLen ( ) / <NUM_LIT> ) * LibCallRegs , <NUM_LIT> ) ; RVFI -> setLibCallStackSize ( LibCallFrameSize ) ; } uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; if ( RealStackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; if ( STI . isRegisterReservedByUser ( SPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { StackSize = FirstSPAdjustAmount ; RealStackSize = FirstSPAdjustAmount ; } adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - RealStackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const auto & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , getNonLibcallCSI ( CSI ) . size ( ) ) ; for ( const auto & Entry : CSI ) { int FrameIdx = Entry . getFrameIdx ( ) ; int64_t Offset ; if ( FrameIdx < <NUM_LIT> ) Offset = FrameIdx * ( int64_t ) STI . getXLen ( ) / <NUM_LIT> ; else Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) - RVFI -> getLibCallStackSize ( ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ;"
LLVM,RISCV,1462,"Predict the next statement of this code snippet:
 <s> const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( CSI ) ; for ( auto & CS : reverse ( NonLibcallCSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;"
LLVM,RISCV,1463,"Predict the next statement of this code snippet:
 <s> if ( ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ;"
LLVM,RISCV,1464,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT> ) ;"
LLVM,RISCV,1465,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;"
LLVM,RISCV,1466,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ;"
LLVM,RISCV,1467,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; uint64_t MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ;"
LLVM,RISCV,1468,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { if ( ! hasFP ( MF ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator LastFrameDestroy = MBBI ; std :: advance ( LastFrameDestroy , - MFI . getCalleeSavedInfo ( ) . size ( ) ) ;"
LLVM,RISCV,1469,"Predict the next statement of this code snippet:
 <s> unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ;"
LLVM,RISCV,1470,"Predict the next statement of this code snippet:
 <s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; }"
LLVM,RISCV,1471,"Predict the next statement of this code snippet:
 <s> if ( FI < <NUM_LIT> ) Offset += StackOffset :: getFixed ( RVFI -> getLibCallStackSize ( ) ) ; } else if ( MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ) { Offset += StackOffset :: get ( alignTo ( MFI . getStackSize ( ) - RVFI -> getCalleeSavedStackSize ( ) , <NUM_LIT> ) , RVFI -> getRVVStackSize ( ) ) ; } } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += StackOffset :: getFixed ( RVFI -> getVarArgsSaveSize ( ) ) ; if ( FI >= <NUM_LIT> ) Offset -= StackOffset :: getFixed ( RVFI -> getLibCallStackSize ( ) ) ; if ( MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ) Offset -= StackOffset :: getFixed ( MFI . getStackSize ( ) ) ; } else { if ( MFI . getStackID ( FI ) == TargetStackID :: Default ) { if ( MFI . isFixedObjectIndex ( FI ) ) {"
LLVM,RISCV,1472,"Predict the next statement of this code snippet:
 <s> unsigned SPReg = getSPReg ( STI ) ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } if ( hasFP ( MF ) ) { for ( auto & I = LastFrameDestroy ; I != MBBI ; ++ I ) { if ( I -> mayLoad ( ) && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned DestReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == FPReg ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( SPReg , true ) , - FPOffset ) ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; break ; } } }"
LLVM,RISCV,1473,"Predict the next statement of this code snippet:
 <s> uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; unsigned Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ;"
LLVM,RISCV,1474,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; if ( RI -> needsStackRealignment ( MF ) && MFI . hasVarSizedObjects ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) StackSize = FirstSPAdjustAmount ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) {"
LLVM,RISCV,1475,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; unsigned SP = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ; } return MBB . erase ( I ) ;"
LLVM,RISCV,1476,"Predict the next statement of this code snippet:
 <s> auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - FirstSPAdjustAmount ) ) ; BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { for ( auto & I = LastFrameDestroy ; I != MBBI ; ++ I ) { if ( I -> mayLoad ( ) && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register DestReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == FPReg ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( SPReg , true ) , - FPOffset ) ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; break ; } } } } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) {"
LLVM,RISCV,1477,"Predict the next statement of this code snippet:
 <s> uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - FirstSPAdjustAmount ) ) ; BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { for ( auto & I = LastFrameDestroy ; I != MBBI ; ++ I ) { if ( I -> mayLoad ( ) && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register DestReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == FPReg ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( SPReg , true ) , - FPOffset ) ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;"
LLVM,RISCV,1478,"Predict the next statement of this code snippet:
 <s> for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { unsigned ShiftAmount = countTrailingZeros ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ;"
LLVM,RISCV,1479,"Predict the next statement of this code snippet:
 <s> if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { unsigned ShiftAmount = countTrailingZeros ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ;"
LLVM,RISCV,1480,"Predict the next statement of this code snippet:
 <s> else Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) ) { assert ( ! MFI . hasVarSizedObjects ( ) && <STR_LIT> ) ; FrameReg = <STR_LIT> ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) Offset += RVFI -> getVarArgsSaveSize ( ) ;"
LLVM,RISCV,1481,"Predict the next statement of this code snippet:
 <s> assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; if ( hasFP ( MF ) ) adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; const MCRegisterInfo * MRI = MF . getMMI ( ) . getContext ( ) . getRegisterInfo ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; for ( const auto & Entry : CSI ) { unsigned Reg = Entry . getReg ( ) ; int FI = Entry . getFrameIdx ( ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , MFI . getObjectOffset ( FI ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ;"
LLVM,RISCV,1482,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; if ( hasFP ( MF ) ) adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; const MCRegisterInfo * MRI = MF . getMMI ( ) . getContext ( ) . getRegisterInfo ( ) ;"
LLVM,RISCV,1483,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - StackSize + RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameDestroy ) ; }"
LLVM,RISCV,1484,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; DebugLoc DL ; if ( shouldEnableVectorUnit ( MF ) ) { BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ;"
LLVM,RISCV,1485,"Predict the next statement of this code snippet:
 <s> auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . hasStdExtV ( ) ) return false ;"
LLVM,RISCV,1486,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: shouldEnableVectorUnit ( MachineFunction & MF ) const {"
LLVM,RISCV,1487,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: hasBP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;"
LLVM,RISCV,1488,"Predict the next statement of this code snippet:
 <s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;"
LLVM,RISCV,1489,"Predict the next statement of this code snippet:
 <s> std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; unsigned Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) {"
LLVM,RISCV,1490,"Predict the next statement of this code snippet:
 <s> uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; if ( STI . isRegisterReservedByUser ( SPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) StackSize = FirstSPAdjustAmount ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;"
LLVM,RISCV,1491,"Predict the next statement of this code snippet:
 <s> if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtD ( ) || MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; Regs [ i ] ; ++ i ) if ( <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; } }"
LLVM,RISCV,1492,"Predict the next statement of this code snippet:
 <s> SavedRegs . set ( <STR_LIT> ) ; } if ( hasBP ( MF ) ) SavedRegs . set ( <STR_LIT> ( ) ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) && MFI . hasCalls ( ) ) {"
LLVM,RISCV,1493,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { Align MaxStackAlign = std :: max ( StackAlign , MFI . getMaxAlign ( ) ) ; FrameSize += ( MaxStackAlign . value ( ) - StackAlign . value ( ) ) ; StackAlign = MaxStackAlign ; } uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ;"
LLVM,RISCV,1494,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override { return MBB . erase ( MI ) ;"
LLVM,RISCV,1495,"Predict the next statement of this code snippet:
 <s> Register SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) {"
LLVM,RISCV,1496,"Predict the next statement of this code snippet:
 <s> while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; }"
LLVM,RISCV,1497,"Predict the next statement of this code snippet:
 <s> Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; Register BPReg = <STR_LIT> ( ) ; DebugLoc DL ; emitSCSPrologue ( MF , MBB , MBBI , DL ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; determineFrameLayout ( MF ) ; if ( int LibCallRegs = getLibCallID ( MF , MFI . getCalleeSavedInfo ( ) ) + <NUM_LIT> ) { unsigned LibCallFrameSize = alignTo ( ( STI . getXLen ( ) / <NUM_LIT> ) * LibCallRegs , <NUM_LIT> ) ; RVFI -> setLibCallStackSize ( LibCallFrameSize ) ; } uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; if ( RealStackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; if ( STI . isRegisterReservedByUser ( SPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { StackSize = FirstSPAdjustAmount ; RealStackSize = FirstSPAdjustAmount ; } adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , RealStackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const auto & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , getNonLibcallCSI ( CSI ) . size ( ) ) ; for ( const auto & Entry : CSI ) { int FrameIdx = Entry . getFrameIdx ( ) ; int64_t Offset ; if ( FrameIdx < <NUM_LIT> ) Offset = FrameIdx * ( int64_t ) STI . getXLen ( ) / <NUM_LIT> ; else Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) - RVFI -> getLibCallStackSize ( ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported {"
LLVM,RISCV,1498,"Predict the next statement of this code snippet:
 <s> if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) return ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ; std :: vector < CalleeSavedInfo > & CSI = MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ; if ( std :: none_of ( CSI . begin ( ) , CSI . end ( ) , [ & ] ( CalleeSavedInfo & CSR ) { return CSR . getReg ( ) == RAReg ; } ) ) return ; Register SCSPReg = <STR_LIT> ( ) ; auto & Ctx = MF . getFunction ( ) . getContext ( ) ; if ( ! STI . isRegisterReservedByUser ( SCSPReg ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( RVFI -> useSaveRestoreLibCalls ( MF ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; }"
LLVM,RISCV,1499,"Predict the next statement of this code snippet:
 <s> Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ; std :: vector < CalleeSavedInfo > & CSI = MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ; if ( std :: none_of ( CSI . begin ( ) , CSI . end ( ) , [ & ] ( CalleeSavedInfo & CSR ) { return CSR . getReg ( ) == RAReg ; } ) ) return ; Register SCSPReg = <STR_LIT> ( ) ; auto & Ctx = MF . getFunction ( ) . getContext ( ) ; if ( ! STI . isRegisterReservedByUser ( SCSPReg ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( RVFI -> useSaveRestoreLibCalls ( MF ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; }"
LLVM,RISCV,1500,"Predict the next statement of this code snippet:
 <s> Register SCSPReg = <STR_LIT> ( ) ; auto & Ctx = MF . getFunction ( ) . getContext ( ) ; if ( ! STI . isRegisterReservedByUser ( SCSPReg ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( RVFI -> useSaveRestoreLibCalls ( MF ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; bool IsRV64 = STI . hasFeature ( <STR_LIT> ) ; int64_t SlotSize = STI . getXLen ( ) / <NUM_LIT> ; BuildMI ( MBB , MI , DL , TII -> get ( IsRV64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RAReg ) . addReg ( SCSPReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( SCSPReg , RegState :: Define ) . addReg ( SCSPReg ) . addImm ( SlotSize ) ;"
LLVM,RISCV,1501,"Predict the next statement of this code snippet:
 <s> if ( RVFI -> getLibCallStackSize ( ) ) return <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( StackSize ) && ( CSI . size ( ) > <NUM_LIT> ) ) { return <NUM_LIT> - getStackAlign ( ) . value ( ) ; } return <NUM_LIT> ;"
LLVM,RISCV,1502,"Predict the next statement of this code snippet:
 <s> int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ;"
LLVM,RISCV,1503,"Predict the next statement of this code snippet:
 <s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( CSI . empty ( ) || ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return - <NUM_LIT> ; Register MaxReg = <STR_LIT> ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) < <NUM_LIT> ) MaxReg = std :: max ( MaxReg . id ( ) , CS . getReg ( ) ) ; if ( MaxReg == <STR_LIT> ) return - <NUM_LIT> ; switch ( MaxReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;"
LLVM,RISCV,1504,"Predict the next statement of this code snippet:
 <s> static SmallVector < CalleeSavedInfo , <NUM_LIT> > getNonLibcallCSI ( const std :: vector < CalleeSavedInfo > & CSI ) { SmallVector < CalleeSavedInfo , <NUM_LIT> > NonLibcallCSI ;"
LLVM,RISCV,1505,"Predict the next statement of this code snippet:
 <s> static SmallVector < CalleeSavedInfo , <NUM_LIT> > getNonLibcallCSI ( const std :: vector < CalleeSavedInfo > & CSI ) { SmallVector < CalleeSavedInfo , <NUM_LIT> > NonLibcallCSI ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) >= <NUM_LIT> ) NonLibcallCSI . push_back ( CS ) ;"
LLVM,RISCV,1506,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;"
LLVM,RISCV,1507,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: hasBP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;"
LLVM,RISCV,1508,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;"
LLVM,RISCV,1509,"Predict the next statement of this code snippet:
 <s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;"
LLVM,RISCV,1510,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const {"
LLVM,RISCV,1511,"Predict the next statement of this code snippet:
 <s> int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ;"
LLVM,RISCV,1512,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) {"
LLVM,RISCV,1513,"Predict the next statement of this code snippet:
 <s> const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( CSI ) ; for ( auto & CS : reverse ( NonLibcallCSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; } const char * RestoreLibCall = getRestoreLibCallName ( * MF , CSI ) ;"
LLVM,RISCV,1514,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( STI ) {"
LLVM,RISCV,1515,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( STI ) {"
LLVM,RISCV,1516,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( SpillLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;"
LLVM,RISCV,1517,"Predict the next statement of this code snippet:
 <s> MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( SpillLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn ( CS . getReg ( ) ) ; } const auto & NonLibcallCSI = getNonLibcallCSI ( CSI ) ; for ( auto & CS : NonLibcallCSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;"
LLVM,RISCV,1518,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = GEP -> getNumOperands ( ) ; i != e ; ++ i , ++ GTI ) { if ( ! Ops [ i ] -> getType ( ) -> isVectorTy ( ) ) continue ; if ( VecOperand ) return std :: make_pair ( nullptr , nullptr ) ; VecOperand = i ; TypeSize TS = DL -> getTypeAllocSize ( GTI . getIndexedType ( ) ) ; if ( TS . isScalable ( ) ) return std :: make_pair ( nullptr , nullptr ) ; TypeScale = TS . getFixedSize ( ) ; } if ( ! VecOperand ) return std :: make_pair ( nullptr , nullptr ) ; Value * VecIndex = Ops [ * VecOperand ] ; Type * VecIntPtrTy = DL -> getIntPtrType ( GEP -> getType ( ) ) ; if ( VecIndex -> getType ( ) != VecIntPtrTy ) return std :: make_pair ( nullptr , nullptr ) ; Value * Stride ; BinaryOperator * Inc ; PHINode * BasePhi ; if ( ! matchStridedRecurrence ( VecIndex , L , Stride , BasePhi , Inc , Builder ) ) return std :: make_pair ( nullptr , nullptr ) ; assert ( BasePhi -> getNumIncomingValues ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned IncrementingBlock = BasePhi -> getOperand ( <NUM_LIT> ) == Inc ? <NUM_LIT> : <NUM_LIT> ; assert ( BasePhi -> getIncomingValue ( IncrementingBlock ) == Inc && <STR_LIT> ) ; Builder . SetInsertPoint ( GEP ) ; Ops [ * VecOperand ] = BasePhi ;"
LLVM,RISCV,1519,"Predict the next statement of this code snippet:
 <s> assert ( BasePhi -> getNumIncomingValues ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned IncrementingBlock = BasePhi -> getOperand ( <NUM_LIT> ) == Inc ? <NUM_LIT> : <NUM_LIT> ; assert ( BasePhi -> getIncomingValue ( IncrementingBlock ) == Inc && <STR_LIT> ) ; Builder . SetInsertPoint ( GEP ) ; Ops [ * VecOperand ] = BasePhi ; Type * SourceTy = GEP -> getSourceElementType ( ) ; Value * BasePtr = Builder . CreateGEP ( SourceTy , Ops [ <NUM_LIT> ] , makeArrayRef ( Ops ) . drop_front ( ) ) ; Builder . SetInsertPoint ( BasePhi -> getIncomingBlock ( <NUM_LIT> - IncrementingBlock ) -> getTerminator ( ) ) ; Type * IntPtrTy = DL -> getIntPtrType ( BasePtr -> getType ( ) ) ; assert ( Stride -> getType ( ) == IntPtrTy && <STR_LIT> ) ; if ( TypeScale != <NUM_LIT> ) Stride = Builder . CreateMul ( Stride , ConstantInt :: get ( IntPtrTy , TypeScale ) ) ; auto P = std :: make_pair ( BasePtr , Stride ) ; StridedAddrs [ GEP ] = P ;"
LLVM,RISCV,1520,"Predict the next statement of this code snippet:
 <s> for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; } else if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; } } } for ( auto * II : Gathers ) Changed |= tryCreateStridedLoadStore ( II , II -> getType ( ) , II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ; for ( auto * II : Scatters ) Changed |= tryCreateStridedLoadStore ( II , II -> getArgOperand ( <NUM_LIT> ) -> getType ( ) , II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ; while ( ! MaybeDeadPHIs . empty ( ) ) { if ( auto * Phi = dyn_cast_or_null < PHINode > ( MaybeDeadPHIs . pop_back_val ( ) ) ) RecursivelyDeleteDeadPHINode ( Phi ) ; } return Changed ;"
LLVM,RISCV,1521,"Predict the next statement of this code snippet:
 <s> if ( BO -> getOpcode ( ) == Instruction :: Or && ! haveNoCommonBitsSet ( BO -> getOperand ( <NUM_LIT> ) , BO -> getOperand ( <NUM_LIT> ) , * DL ) ) return false ; Value * OtherOp ; if ( isa < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) && L -> contains ( cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ) ) { Index = cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ; OtherOp = BO -> getOperand ( <NUM_LIT> ) ; } else if ( isa < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) && L -> contains ( cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ) ) { Index = cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ; OtherOp = BO -> getOperand ( <NUM_LIT> ) ; } else { return false ; } if ( ! L -> isLoopInvariant ( OtherOp ) ) return false ; Value * SplatOp = getSplatValue ( OtherOp ) ; if ( ! SplatOp ) return false ; if ( ! matchStridedRecurrence ( Index , L , Stride , BasePtr , Inc , Builder ) ) return false ; unsigned StepIndex = Inc -> getOperand ( <NUM_LIT> ) == BasePtr ? <NUM_LIT> : <NUM_LIT> ; unsigned StartBlock = BasePtr -> getOperand ( <NUM_LIT> ) == Inc ? <NUM_LIT> : <NUM_LIT> ; Value * Step = Inc -> getOperand ( StepIndex ) ; Value * Start = BasePtr -> getOperand ( StartBlock ) ; Builder . SetInsertPoint ( BasePtr -> getIncomingBlock ( StartBlock ) -> getTerminator ( ) ) ; Builder . SetCurrentDebugLocation ( DebugLoc ( ) ) ; switch ( BO -> getOpcode ( ) ) {"
LLVM,RISCV,1522,"Predict the next statement of this code snippet:
 <s> auto & TM = TPC . getTM < <ISA_LIT>TargetMachine > ( ) ; ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> hasStdExtV ( ) || ! ST -> useRVVForFixedLengthVectors ( ) ) return false ; TLI = ST -> getTargetLowering ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > Gathers ; SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; } else if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; } } } for ( auto * II : Gathers ) Changed |= tryCreateStridedLoadStore ( II , II -> getType ( ) , II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ; for ( auto * II : Scatters ) Changed |= tryCreateStridedLoadStore ( II , II -> getArgOperand ( <NUM_LIT> ) -> getType ( ) , II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ; while ( ! MaybeDeadPHIs . empty ( ) ) { if ( auto * Phi = dyn_cast_or_null < PHINode > ( MaybeDeadPHIs . pop_back_val ( ) ) ) RecursivelyDeleteDeadPHINode ( Phi ) ; } return Changed ;"
LLVM,RISCV,1523,"Predict the next statement of this code snippet:
 <s> SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; } else if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; } } } for ( auto * II : Gathers ) Changed |= tryCreateStridedLoadStore ( II , II -> getType ( ) , II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,1524,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>GatherScatterLoweringPass ( ) {"
LLVM,RISCV,1525,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ;"
LLVM,RISCV,1526,"Predict the next statement of this code snippet:
 <s> AU . addRequired < TargetPassConfig > ( ) ;"
LLVM,RISCV,1527,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <STR_LIT> ;"
LLVM,RISCV,1528,"Predict the next statement of this code snippet:
 <s> Type * ScalarType = DataType -> getScalarType ( ) ; if ( ! TLI -> isLegalElementTypeForRVV ( ScalarType ) ) return false ;"
LLVM,RISCV,1529,"Predict the next statement of this code snippet:
 <s> if ( ! StartVal ) return std :: make_pair ( nullptr , nullptr ) ; APInt StrideVal ( StartVal -> getValue ( ) . getBitWidth ( ) , <NUM_LIT> ) ; ConstantInt * Prev = StartVal ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { auto * C = dyn_cast_or_null < ConstantInt > ( StartC -> getAggregateElement ( i ) ) ; if ( ! C ) return std :: make_pair ( nullptr , nullptr ) ; APInt LocalStride = C -> getValue ( ) - Prev -> getValue ( ) ; if ( i == <NUM_LIT> ) StrideVal = LocalStride ; else if ( StrideVal != LocalStride ) return std :: make_pair ( nullptr , nullptr ) ; Prev = C ; } Value * Stride = ConstantInt :: get ( StartVal -> getType ( ) , StrideVal ) ;"
LLVM,RISCV,1530,"Predict the next statement of this code snippet:
 <s> return true ; } auto * BO = dyn_cast < BinaryOperator > ( Index ) ; if ( ! BO ) return false ; if ( BO -> getOpcode ( ) != Instruction :: Add && BO -> getOpcode ( ) != Instruction :: Or && BO -> getOpcode ( ) != Instruction :: Mul && BO -> getOpcode ( ) != Instruction :: Shl ) return false ; if ( BO -> getOpcode ( ) == Instruction :: Shl && ! isa < Constant > ( BO -> getOperand ( <NUM_LIT> ) ) ) return false ; if ( BO -> getOpcode ( ) == Instruction :: Or && ! haveNoCommonBitsSet ( BO -> getOperand ( <NUM_LIT> ) , BO -> getOperand ( <NUM_LIT> ) , * DL ) ) return false ; Value * OtherOp ; if ( isa < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) && L -> contains ( cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ) ) { Index = cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ; OtherOp = BO -> getOperand ( <NUM_LIT> ) ; } else if ( isa < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) && L -> contains ( cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ) ) { Index = cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ; OtherOp = BO -> getOperand ( <NUM_LIT> ) ; } else { return false ; } if ( ! L -> isLoopInvariant ( OtherOp ) ) return false ; Value * SplatOp = getSplatValue ( OtherOp ) ; if ( ! SplatOp ) return false ; if ( ! matchStridedRecurrence ( Index , L , Stride , BasePtr , Inc , Builder ) ) return false ; unsigned StepIndex = Inc -> getOperand ( <NUM_LIT> ) == BasePtr ? <NUM_LIT> : <NUM_LIT> ; unsigned StartBlock = BasePtr -> getOperand ( <NUM_LIT> ) == Inc ? <NUM_LIT> : <NUM_LIT> ; Value * Step = Inc -> getOperand ( StepIndex ) ;"
LLVM,RISCV,1531,"Predict the next statement of this code snippet:
 <s> static std :: pair < Value * , Value * > matchStridedStart ( Value * Start , IRBuilder < > & Builder ) { auto * StartC = dyn_cast < Constant > ( Start ) ; if ( StartC ) return matchStridedConstant ( StartC ) ; auto * BO = dyn_cast < BinaryOperator > ( Start ) ; if ( ! BO || BO -> getOpcode ( ) != Instruction :: Add ) return std :: make_pair ( nullptr , nullptr ) ; unsigned OtherIndex = <NUM_LIT> ; Value * Splat = getSplatValue ( BO -> getOperand ( <NUM_LIT> ) ) ; if ( ! Splat ) { Splat = getSplatValue ( BO -> getOperand ( <NUM_LIT> ) ) ; OtherIndex = <NUM_LIT> ; }"
LLVM,RISCV,1532,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>GatherScatterLowering ( ) : FunctionPass ( ID ) {"
LLVM,RISCV,1533,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>GatherScatterLowering ( ) : FunctionPass ( ID ) {"
LLVM,RISCV,1534,"Predict the next statement of this code snippet:
 <s> auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < <ISA_LIT>TargetMachine > ( ) ; ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> hasVInstructions ( ) || ! ST -> useRVVForFixedLengthVectors ( ) ) return false ; TLI = ST -> getTargetLowering ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > Gathers ; SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ;"
LLVM,RISCV,1535,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>GatherScatterLowering :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < <ISA_LIT>TargetMachine > ( ) ; ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> hasVInstructions ( ) || ! ST -> useRVVForFixedLengthVectors ( ) ) return false ; TLI = ST -> getTargetLowering ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ;"
LLVM,RISCV,1536,"Predict the next statement of this code snippet:
 <s> if ( ! BasePtr ) return false ; assert ( Stride != nullptr ) ; Builder . SetInsertPoint ( II ) ; CallInst * Call ; if ( II -> getIntrinsicID ( ) == <STR_LIT> ) Call = Builder . CreateIntrinsic ( <STR_LIT> , { DataType , BasePtr -> getType ( ) , Stride -> getType ( ) } , { II -> getArgOperand ( <NUM_LIT> ) , BasePtr , Stride , II -> getArgOperand ( <NUM_LIT> ) } ) ; else Call = Builder . CreateIntrinsic ( <STR_LIT> , { DataType , BasePtr -> getType ( ) , Stride -> getType ( ) } , { II -> getArgOperand ( <NUM_LIT> ) , BasePtr , Stride , II -> getArgOperand ( <NUM_LIT> ) } ) ; Call -> takeName ( II ) ; II -> replaceAllUsesWith ( Call ) ; II -> eraseFromParent ( ) ; if ( GEP -> use_empty ( ) ) RecursivelyDeleteTriviallyDeadInstructions ( GEP ) ; return true ;"
LLVM,RISCV,1537,"Predict the next statement of this code snippet:
 <s> if ( ! BasePtr ) return false ; assert ( Stride != nullptr ) ; Builder . SetInsertPoint ( II ) ; CallInst * Call ; if ( II -> getIntrinsicID ( ) == <STR_LIT> ) Call = Builder . CreateIntrinsic ( <STR_LIT> , { DataType , BasePtr -> getType ( ) , Stride -> getType ( ) } , { II -> getArgOperand ( <NUM_LIT> ) , BasePtr , Stride , II -> getArgOperand ( <NUM_LIT> ) } ) ; else Call = Builder . CreateIntrinsic ( <STR_LIT> , { DataType , BasePtr -> getType ( ) , Stride -> getType ( ) } , { II -> getArgOperand ( <NUM_LIT> ) , BasePtr , Stride , II -> getArgOperand ( <NUM_LIT> ) } ) ; Call -> takeName ( II ) ;"
LLVM,RISCV,1538,"Predict the next statement of this code snippet:
 <s> if ( InstrInfo . hasAVLReg ( ) && InstrInfo . AVLReg == <STR_LIT> ) { if ( SEW == InstrInfo . SEW ) return true ; } if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( hasSameVTYPE ( InstrInfo ) ) return true ; if ( InstrInfo . MaskRegOp && hasSameVLMAX ( InstrInfo ) && TailAgnostic == InstrInfo . TailAgnostic && MaskAgnostic == InstrInfo . MaskAgnostic ) return true ;"
LLVM,RISCV,1539,"Predict the next statement of this code snippet:
 <s> assert ( isValid ( ) && <STR_LIT> ) ;"
LLVM,RISCV,1540,"Predict the next statement of this code snippet:
 <s> if ( CurInfo . isCompatible ( Require ) ) return false ; if ( ! CurInfo . isUnknown ( ) && Require . hasAVLReg ( ) && Require . getAVLReg ( ) . isVirtual ( ) && ! CurInfo . hasSEWLMULRatioOnly ( ) && Require . hasSameVTYPE ( CurInfo ) ) { if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) {"
LLVM,RISCV,1541,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo InstrInfo ; unsigned NumOperands = MI . getNumExplicitOperands ( ) ; bool HasPolicy = <STR_LIT> ( TSFlags ) ; bool ForceTailAgnostic = <STR_LIT> ( TSFlags ) ; bool TailAgnostic = true ; if ( HasPolicy ) { const MachineOperand & Op = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; TailAgnostic = Op . getImm ( ) & <NUM_LIT> ; } unsigned UseOpIdx ; if ( ! ( ForceTailAgnostic || ( HasPolicy && TailAgnostic ) ) && MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) ) { TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI -> getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } } if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ;"
LLVM,RISCV,1542,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo InstrInfo ; unsigned NumOperands = MI . getNumExplicitOperands ( ) ; bool HasPolicy = <STR_LIT> ( TSFlags ) ; bool ForceTailAgnostic = <STR_LIT> ( TSFlags ) ; bool TailAgnostic = true ; if ( HasPolicy ) { const MachineOperand & Op = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; TailAgnostic = Op . getImm ( ) & <NUM_LIT> ; } unsigned UseOpIdx ; if ( ! ( ForceTailAgnostic || ( HasPolicy && TailAgnostic ) ) && MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) ) { TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI -> getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } } if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; bool StoreOp = MI . getNumExplicitDefs ( ) == <NUM_LIT> ; bool ScalarMovOp = isScalarMoveInstr ( MI ) ; if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( NumOperands - <NUM_LIT> ) ; if ( VLOp . isImm ( ) ) { int64_t Imm = VLOp . getImm ( ) ; if ( Imm == <STR_LIT> ) InstrInfo . setAVLReg ( <STR_LIT> ) ; else InstrInfo . setAVLImm ( Imm ) ; } else { InstrInfo . setAVLReg ( VLOp . getReg ( ) ) ; } } else InstrInfo . setAVLReg ( <STR_LIT> ) ; InstrInfo . setVTYPE ( VLMul , SEW , TailAgnostic , false , MaskRegOp , StoreOp , ScalarMovOp ) ;"
LLVM,RISCV,1543,"Predict the next statement of this code snippet:
 <s> MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; if ( ! CurInfo . isValid ( ) ) { assert ( BlockInfo [ MBB . getNumber ( ) ] . Pred . isValid ( ) && <STR_LIT> ) ; if ( needVSETVLI ( NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) && needVSETVLIPHI ( NewInfo , MBB ) ) { insertVSETVLI ( MBB , MI , NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) ; CurInfo = NewInfo ; } } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , CurInfo ) && needVSETVLI ( NewInfo , CurInfo ) ) { bool NeedInsertVSETVLI = true ; if ( PrevVSETVLIMI ) { bool HasSameAVL = CurInfo . hasSameAVL ( NewInfo ) || ( NewInfo . hasAVLReg ( ) && NewInfo . getAVLReg ( ) . isVirtual ( ) && NewInfo . getAVLReg ( ) == PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( HasSameAVL && CurInfo . getSEWLMULRatio ( ) == NewInfo . getSEWLMULRatio ( ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI = false ; } if ( isScalarMoveInstr ( MI ) && ( ( CurInfo . hasNonZeroAVL ( ) && NewInfo . hasNonZeroAVL ( ) ) || ( CurInfo . hasZeroAVL ( ) && NewInfo . hasZeroAVL ( ) ) ) && NewInfo . hasSameVLMAX ( CurInfo ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI = false ; } } if ( NeedInsertVSETVLI ) insertVSETVLI ( MBB , MI , NewInfo , CurInfo ) ; CurInfo = NewInfo ; } } PrevVSETVLIMI = nullptr ; }"
LLVM,RISCV,1544,"Predict the next statement of this code snippet:
 <s> if ( PrevVSETVLIMI ) { bool HasSameAVL = CurInfo . hasSameAVL ( NewInfo ) || ( NewInfo . hasAVLReg ( ) && NewInfo . getAVLReg ( ) . isVirtual ( ) && NewInfo . getAVLReg ( ) == PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( HasSameAVL && CurInfo . getSEWLMULRatio ( ) == NewInfo . getSEWLMULRatio ( ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI = false ; } if ( isScalarMoveInstr ( MI ) && ( ( CurInfo . hasNonZeroAVL ( ) && NewInfo . hasNonZeroAVL ( ) ) || ( CurInfo . hasZeroAVL ( ) && NewInfo . hasZeroAVL ( ) ) ) && NewInfo . hasSameVLMAX ( CurInfo ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI = false ; } } if ( NeedInsertVSETVLI ) insertVSETVLI ( MBB , MI , NewInfo , CurInfo ) ; CurInfo = NewInfo ; } } PrevVSETVLIMI = nullptr ; } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { CurInfo = <STR_LIT> ( ) ; PrevVSETVLIMI = nullptr ;"
LLVM,RISCV,1545,"Predict the next statement of this code snippet:
 <s> if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( DefInfo . hasSameAVL ( CurInfo ) && DefInfo . hasSameVTYPE ( CurInfo ) ) return false ;"
LLVM,RISCV,1546,"Predict the next statement of this code snippet:
 <s> Register AVLReg = Require . getAVLReg ( ) ; if ( ! AVLReg . isVirtual ( ) ) return true ; MachineInstr * PHI = MRI -> getVRegDef ( AVLReg ) ; if ( ! PHI || PHI -> getOpcode ( ) != <STR_LIT> || PHI -> getParent ( ) != & MBB ) return true ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = PHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register InReg = PHI -> getOperand ( PHIOp ) . getReg ( ) ; MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ;"
LLVM,RISCV,1547,"Predict the next statement of this code snippet:
 <s> if ( PBBInfo . Exit . isUnknown ( ) || ! PBBInfo . Exit . hasCompatibleVTYPE ( Require , false ) ) return true ; MachineInstr * DefMI = MRI -> getVRegDef ( InReg ) ; if ( ! DefMI || ( DefMI -> getOpcode ( ) != <STR_LIT> && DefMI -> getOpcode ( ) != <STR_LIT> && DefMI -> getOpcode ( ) != <STR_LIT> ) ) return true ; VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( ! DefInfo . hasSameAVL ( PBBInfo . Exit ) || ! DefInfo . hasSameVTYPE ( PBBInfo . Exit ) ) return true ;"
LLVM,RISCV,1548,"Predict the next statement of this code snippet:
 <s> } if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; bool StoreOp = MI . getNumExplicitDefs ( ) == <NUM_LIT> ; bool ScalarMovOp = isScalarMoveInstr ( MI ) ; if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( NumOperands - <NUM_LIT> ) ; if ( VLOp . isImm ( ) ) { int64_t Imm = VLOp . getImm ( ) ; if ( Imm == <STR_LIT> ) InstrInfo . setAVLReg ( <STR_LIT> ) ; else InstrInfo . setAVLImm ( Imm ) ; } else { InstrInfo . setAVLReg ( VLOp . getReg ( ) ) ; }"
LLVM,RISCV,1549,"Predict the next statement of this code snippet:
 <s> if ( isVectorConfigInstr ( MI ) ) { HadVectorOp = true ; BBInfo . Change = getInfoForVSETVLI ( MI ) ; continue ; } uint64_t TSFlags = MI . getDesc ( ) . TSFlags ; if ( <STR_LIT> ( TSFlags ) ) { HadVectorOp = true ; VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( ! BBInfo . Change . isValid ( ) ) { BBInfo . Change = NewInfo ; } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , BBInfo . Change ) && needVSETVLI ( NewInfo , BBInfo . Change ) ) BBInfo . Change = NewInfo ; } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { BBInfo . Change = <STR_LIT> ( ) ; }"
LLVM,RISCV,1550,"Predict the next statement of this code snippet:
 <s> MachineOperand & VLOp = MI . getOperand ( MI . getNumExplicitOperands ( ) - Offset ) ; if ( VLOp . isReg ( ) ) { VLOp . setReg ( <STR_LIT> ) ; VLOp . setIsKill ( false ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; if ( ! CurInfo . isValid ( ) ) { assert ( BlockInfo [ MBB . getNumber ( ) ] . Pred . isValid ( ) && <STR_LIT> ) ; if ( needVSETVLI ( NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) && needVSETVLIPHI ( NewInfo , MBB ) ) { insertVSETVLI ( MBB , MI , NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) ; CurInfo = NewInfo ; } } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , CurInfo ) && needVSETVLI ( NewInfo , CurInfo ) ) { bool NeedInsertVSETVLI = true ; if ( PrevVSETVLIMI ) { bool HasSameAVL = CurInfo . hasSameAVL ( NewInfo ) || ( NewInfo . hasAVLReg ( ) && NewInfo . getAVLReg ( ) . isVirtual ( ) && NewInfo . getAVLReg ( ) == PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( HasSameAVL && CurInfo . getSEWLMULRatio ( ) == NewInfo . getSEWLMULRatio ( ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ;"
LLVM,RISCV,1551,"Predict the next statement of this code snippet:
 <s> bool hasCompatibleVTYPE ( const VSETVLIInfo & InstrInfo , bool Strict ) const { if ( hasSameVTYPE ( InstrInfo ) ) return true ; if ( Strict ) return false ; if ( InstrInfo . MaskRegOp && hasSameVLMAX ( InstrInfo ) && TailAgnostic == InstrInfo . TailAgnostic && MaskAgnostic == InstrInfo . MaskAgnostic ) return true ; return false ;"
LLVM,RISCV,1552,"Predict the next statement of this code snippet:
 <s> if ( InstrInfo . MaskRegOp && hasSameVLMAX ( InstrInfo ) && TailAgnostic == InstrInfo . TailAgnostic && MaskAgnostic == InstrInfo . MaskAgnostic ) return true ;"
LLVM,RISCV,1553,"Predict the next statement of this code snippet:
 <s> if ( hasAVLReg ( ) ) return getAVLReg ( ) == <STR_LIT> ;"
LLVM,RISCV,1554,"Predict the next statement of this code snippet:
 <s> bool hasSamePolicy ( const VSETVLIInfo & Other ) const {"
LLVM,RISCV,1555,"Predict the next statement of this code snippet:
 <s> bool hasSameSEW ( const VSETVLIInfo & Other ) const { assert ( isValid ( ) && Other . isValid ( ) && <STR_LIT> ) ;"
LLVM,RISCV,1556,"Predict the next statement of this code snippet:
 <s> if ( hasAVLImm ( ) ) return getAVLImm ( ) == <NUM_LIT> ; return false ;"
LLVM,RISCV,1557,"Predict the next statement of this code snippet:
 <s> assert ( ! InstrInfo . SEWLMULRatioOnly && <STR_LIT> ) ; if ( isUnknown ( ) || InstrInfo . isUnknown ( ) ) return false ; if ( SEWLMULRatioOnly ) return false ; if ( ! Strict && InstrInfo . hasAVLReg ( ) && InstrInfo . AVLReg == <STR_LIT> ) {"
LLVM,RISCV,1558,"Predict the next statement of this code snippet:
 <s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }"
LLVM,RISCV,1559,"Predict the next statement of this code snippet:
 <s> return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;"
LLVM,RISCV,1560,"Predict the next statement of this code snippet:
 <s> if ( ! CurInfo . isUnknown ( ) && Require . hasAVLReg ( ) && Require . getAVLReg ( ) . isVirtual ( ) && ! CurInfo . hasSEWLMULRatioOnly ( ) && CurInfo . hasCompatibleVTYPE ( Require , false ) ) { if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( isVectorConfigInstr ( * DefMI ) ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( DefInfo . hasSameAVL ( CurInfo ) && DefInfo . hasSameVTYPE ( CurInfo ) ) return false ; } }"
LLVM,RISCV,1561,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InsertVSETVLI :: needVSETVLIPHI ( const VSETVLIInfo & Require , const MachineBasicBlock & MBB ) { if ( DisableInsertVSETVLPHIOpt ) return true ; if ( ! Require . hasAVLReg ( ) ) return true ; Register AVLReg = Require . getAVLReg ( ) ; if ( ! AVLReg . isVirtual ( ) ) return true ; MachineInstr * PHI = MRI -> getVRegDef ( AVLReg ) ; if ( ! PHI || PHI -> getOpcode ( ) != <STR_LIT> || PHI -> getParent ( ) != & MBB ) return true ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = PHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) {"
LLVM,RISCV,1562,"Predict the next statement of this code snippet:
 <s> if ( ! Require . hasAVLReg ( ) ) return true ; Register AVLReg = Require . getAVLReg ( ) ; if ( ! AVLReg . isVirtual ( ) ) return true ; MachineInstr * PHI = MRI -> getVRegDef ( AVLReg ) ; if ( ! PHI || PHI -> getOpcode ( ) != <STR_LIT> || PHI -> getParent ( ) != & MBB ) return true ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = PHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register InReg = PHI -> getOperand ( PHIOp ) . getReg ( ) ; MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ;"
LLVM,RISCV,1563,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InsertVSETVLI :: runOnMachineFunction ( MachineFunction & MF ) { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasVInstructions ( ) ) return false ; TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; assert ( BlockInfo . empty ( ) && <STR_LIT> ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; bool HaveVectorOp = false ; for ( const MachineBasicBlock & MBB : MF ) HaveVectorOp |= computeVLVTYPEChanges ( MBB ) ; if ( HaveVectorOp ) { for ( const MachineBasicBlock & MBB : MF ) {"
LLVM,RISCV,1564,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) , TailAgnostic ( false ) , MaskAgnostic ( false ) , MaskRegOp ( false ) , StoreOp ( false ) , ScalarMovOp ( false ) , SEWLMULRatioOnly ( false ) {"
LLVM,RISCV,1565,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) , TailAgnostic ( false ) , MaskAgnostic ( false ) , MaskRegOp ( false ) , StoreOp ( false ) , ScalarMovOp ( false ) , SEWLMULRatioOnly ( false ) {"
LLVM,RISCV,1566,"Predict the next statement of this code snippet:
 <s> if ( ! CurInfo . isValid ( ) ) { assert ( BlockInfo [ MBB . getNumber ( ) ] . Pred . isValid ( ) && <STR_LIT> ) ; if ( ! ( BBLocalInfo . isValid ( ) && canSkipVSETVLIForLoadStore ( MI , NewInfo , BBLocalInfo ) ) && needVSETVLI ( NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) && needVSETVLIPHI ( NewInfo , MBB ) ) { insertVSETVLI ( MBB , MI , NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) ; CurInfo = NewInfo ; BBLocalInfo = NewInfo ; } if ( ! BBLocalInfo . isValid ( ) ) BBLocalInfo = NewInfo ; } else { assert ( BBLocalInfo . isValid ( ) ) ; if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , CurInfo ) && needVSETVLI ( NewInfo , CurInfo ) ) { bool NeedInsertVSETVLI = true ; if ( PrevVSETVLIMI ) { bool HasSameAVL = CurInfo . hasSameAVL ( NewInfo ) || ( NewInfo . hasAVLReg ( ) && NewInfo . getAVLReg ( ) . isVirtual ( ) && NewInfo . getAVLReg ( ) == PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( HasSameAVL && CurInfo . getSEWLMULRatio ( ) == NewInfo . getSEWLMULRatio ( ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI = false ; } if ( isScalarMoveInstr ( MI ) && ( ( CurInfo . hasNonZeroAVL ( ) && NewInfo . hasNonZeroAVL ( ) ) || ( CurInfo . hasZeroAVL ( ) && NewInfo . hasZeroAVL ( ) ) ) && NewInfo . hasSameVLMAX ( CurInfo ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI = false ; } } if ( NeedInsertVSETVLI ) insertVSETVLI ( MBB , MI , NewInfo , CurInfo ) ; CurInfo = NewInfo ; BBLocalInfo = NewInfo ; } } PrevVSETVLIMI = nullptr ; } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { CurInfo = <STR_LIT> ( ) ;"
LLVM,RISCV,1567,"Predict the next statement of this code snippet:
 <s> } if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( hasCompatibleVTYPE ( InstrInfo , Strict ) ) return true ; if ( Strict ) return false ;"
LLVM,RISCV,1568,"Predict the next statement of this code snippet:
 <s> if ( SEWLMULRatioOnly ) return false ; if ( ! Strict && InstrInfo . hasAVLReg ( ) && InstrInfo . AVLReg == <STR_LIT> ) { if ( SEW == InstrInfo . SEW ) return true ; } if ( ! hasSameAVL ( InstrInfo ) ) return false ;"
LLVM,RISCV,1569,"Predict the next statement of this code snippet:
 <s> bool TailAgnostic = true ; bool UsesMaskPolicy = <STR_LIT> ( TSFlags ) ; bool MaskAgnostic = UsesMaskPolicy ; unsigned UseOpIdx ; if ( HasPolicy ) { const MachineOperand & Op = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; uint64_t Policy = Op . getImm ( ) ; assert ( Policy <= ( <STR_LIT> | <STR_LIT> ) && <STR_LIT> ) ; TailAgnostic = Policy & <STR_LIT> ; MaskAgnostic = Policy & <STR_LIT> ; } else if ( MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) ) { TailAgnostic = false ; if ( UsesMaskPolicy ) MaskAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI -> getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) { TailAgnostic = true ; if ( UsesMaskPolicy ) MaskAgnostic = true ; } } if ( <STR_LIT> ( TSFlags ) ) TailAgnostic = true ; } if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ;"
LLVM,RISCV,1570,"Predict the next statement of this code snippet:
 <s> const MachineOperand & Op = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; TailAgnostic = Op . getImm ( ) & <NUM_LIT> ; } unsigned UseOpIdx ; if ( ! ( ForceTailAgnostic || ( HasPolicy && TailAgnostic ) ) && MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) ) { TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI -> getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } } if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ;"
LLVM,RISCV,1571,"Predict the next statement of this code snippet:
 <s> bool TailAgnostic = true ; if ( HasPolicy ) { const MachineOperand & Op = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; TailAgnostic = Op . getImm ( ) & <NUM_LIT> ; } unsigned UseOpIdx ; if ( ! ( ForceTailAgnostic || ( HasPolicy && TailAgnostic ) ) && MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) ) { TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI -> getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } } if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( NumOperands - <NUM_LIT> ) ;"
LLVM,RISCV,1572,"Predict the next statement of this code snippet:
 <s> } if ( ! hasSameVTYPE ( InstrInfo ) && ! ( InstrInfo . MaskRegOp && hasSameVLMAX ( InstrInfo ) && TailAgnostic == InstrInfo . TailAgnostic && MaskAgnostic == InstrInfo . MaskAgnostic ) ) return false ; return hasSameAVL ( InstrInfo ) ;"
LLVM,RISCV,1573,"Predict the next statement of this code snippet:
 <s> if ( isUnknown ( ) || hasSEWLMULRatioOnly ( ) ) return false ; if ( ! hasSameAVL ( InstrInfo ) ) return false ;"
LLVM,RISCV,1574,"Predict the next statement of this code snippet:
 <s> if ( isUnknown ( ) || hasSEWLMULRatioOnly ( ) ) return false ; if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( TailAgnostic != InstrInfo . TailAgnostic || MaskAgnostic != InstrInfo . MaskAgnostic ) return false ;"
LLVM,RISCV,1575,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) , TailAgnostic ( false ) , MaskAgnostic ( false ) , MaskRegOp ( false ) , SEWLMULRatioOnly ( false ) {"
LLVM,RISCV,1576,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) , TailAgnostic ( false ) , MaskAgnostic ( false ) , MaskRegOp ( false ) , SEWLMULRatioOnly ( false ) {"
LLVM,RISCV,1577,"Predict the next statement of this code snippet:
 <s> BBInfo . InQueue = false ; VSETVLIInfo InInfo ; if ( MBB . pred_empty ( ) ) { InInfo . setUnknown ( ) ; } else { for ( MachineBasicBlock * P : MBB . predecessors ( ) ) InInfo = InInfo . intersect ( BlockInfo [ P -> getNumber ( ) ] . Exit ) ; }"
LLVM,RISCV,1578,"Predict the next statement of this code snippet:
 <s> if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) { TailAgnostic = true ; if ( UsesMaskPolicy ) MaskAgnostic = true ; } } if ( <STR_LIT> ( TSFlags ) ) TailAgnostic = true ; } <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( getSEWOpNum ( MI ) ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; bool StoreOp = MI . getNumExplicitDefs ( ) == <NUM_LIT> ; bool ScalarMovOp = isScalarMoveInstr ( MI ) ; if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( getVLOpNum ( MI ) ) ; if ( VLOp . isImm ( ) ) { int64_t Imm = VLOp . getImm ( ) ; if ( Imm == <STR_LIT> ) InstrInfo . setAVLReg ( <STR_LIT> ) ; else InstrInfo . setAVLImm ( Imm ) ; } else { InstrInfo . setAVLReg ( VLOp . getReg ( ) ) ; }"
LLVM,RISCV,1579,"Predict the next statement of this code snippet:
 <s> if ( UseMI && UseMI -> isImplicitDef ( ) ) { TailAgnostic = true ; if ( UsesMaskPolicy ) MaskAgnostic = true ; } } if ( <STR_LIT> ( TSFlags ) ) TailAgnostic = true ; } <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( getSEWOpNum ( MI ) ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; bool StoreOp = MI . getNumExplicitDefs ( ) == <NUM_LIT> ; bool ScalarMovOp = isScalarMoveInstr ( MI ) ; if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( getVLOpNum ( MI ) ) ; if ( VLOp . isImm ( ) ) { int64_t Imm = VLOp . getImm ( ) ; if ( Imm == <STR_LIT> ) InstrInfo . setAVLReg ( <STR_LIT> ) ;"
LLVM,RISCV,1580,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InsertVSETVLI :: computeVLVTYPEChanges ( const MachineBasicBlock & MBB ) { bool HadVectorOp = false ; BlockData & BBInfo = BlockInfo [ MBB . getNumber ( ) ] ; BBInfo . Change = BBInfo . Pred ; for ( const MachineInstr & MI : MBB ) { if ( isVectorConfigInstr ( MI ) ) { HadVectorOp = true ; BBInfo . Change = getInfoForVSETVLI ( MI ) ; continue ; } uint64_t TSFlags = MI . getDesc ( ) . TSFlags ; if ( <STR_LIT> ( TSFlags ) ) { HadVectorOp = true ; VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( ! BBInfo . Change . isValid ( ) ) { BBInfo . Change = NewInfo ; } else { if ( needVSETVLI ( MI , NewInfo , BBInfo . Change ) ) BBInfo . Change = NewInfo ; }"
LLVM,RISCV,1581,"Predict the next statement of this code snippet:
 <s> if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . readsRegister ( <STR_LIT> ) ) UsedVL = true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . readsRegister ( <STR_LIT> ) ) UsedVTYPE = true ; if ( ! isVectorConfigInstr ( MI ) ) continue ; if ( PrevMI ) { if ( ! UsedVL && ! UsedVTYPE ) { ToDelete . push_back ( PrevMI ) ; } else if ( ! UsedVTYPE && isVLPreservingConfig ( MI ) ) { PrevMI -> getOperand ( <NUM_LIT> ) . setImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; ToDelete . push_back ( & MI ) ; continue ; } } PrevMI = & MI ; UsedVL = false ; UsedVTYPE = false ; Register VRegDef = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,1582,"Predict the next statement of this code snippet:
 <s> if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . readsRegister ( <STR_LIT> ) ) UsedVTYPE = true ; if ( ! isVectorConfigInstr ( MI ) ) continue ; if ( PrevMI ) { if ( ! UsedVL && ! UsedVTYPE ) { ToDelete . push_back ( PrevMI ) ; } else if ( ! UsedVTYPE && isVLPreservingConfig ( MI ) ) { PrevMI -> getOperand ( <NUM_LIT> ) . setImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; ToDelete . push_back ( & MI ) ; continue ;"
LLVM,RISCV,1583,"Predict the next statement of this code snippet:
 <s> } } if ( Require . hasAVLReg ( ) && Require . getAVLReg ( ) . isVirtual ( ) ) { if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( isVectorConfigInstr ( * DefMI ) ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( DefInfo . hasSameVLMAX ( Require ) && ( DefInfo . hasAVLImm ( ) || DefInfo . getAVLReg ( ) == <STR_LIT> ) ) { MachineOperand & VLOp = MI . getOperand ( getVLOpNum ( MI ) ) ; if ( DefInfo . hasAVLImm ( ) ) VLOp . ChangeToImmediate ( DefInfo . getAVLImm ( ) ) ; else VLOp . ChangeToRegister ( DefInfo . getAVLReg ( ) , false ) ; CurInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; continue ; } } } } } CurInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; continue ; }"
LLVM,RISCV,1584,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> ( TSFlags ) ) { if ( AvailableInfo != computeInfoForInstr ( MI , TSFlags , MRI ) ) return ; Found = true ; break ; } } if ( ! Found ) return ; auto OldInfo = BlockInfo [ UnavailablePred -> getNumber ( ) ] . Exit ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> << UnavailablePred -> getName ( ) << <STR_LIT> << AvailableInfo << <STR_LIT> ) ; BlockInfo [ UnavailablePred -> getNumber ( ) ] . Exit = AvailableInfo ; BlockInfo [ MBB . getNumber ( ) ] . Pred = AvailableInfo ;"
LLVM,RISCV,1585,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo AvailableInfo ; for ( MachineBasicBlock * P : MBB . predecessors ( ) ) { const VSETVLIInfo & PredInfo = BlockInfo [ P -> getNumber ( ) ] . Exit ; if ( PredInfo . isUnknown ( ) ) { if ( UnavailablePred ) return ; UnavailablePred = P ; } else if ( ! AvailableInfo . isValid ( ) ) { AvailableInfo = PredInfo ; } else if ( AvailableInfo != PredInfo ) { return ; } } if ( ! UnavailablePred || ! AvailableInfo . isValid ( ) ) return ; if ( UnavailablePred -> succ_size ( ) != <NUM_LIT> ) return ; if ( ! hasFixedResult ( AvailableInfo , ST ) ) return ; bool Found = false ; for ( auto & MI : MBB ) {"
LLVM,RISCV,1586,"Predict the next statement of this code snippet:
 <s> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ;"
LLVM,RISCV,1587,"Predict the next statement of this code snippet:
 <s> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ;"
LLVM,RISCV,1588,"Predict the next statement of this code snippet:
 <s> MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; if ( ! CurInfo . isValid ( ) ) { CurInfo = BlockInfo [ MBB . getNumber ( ) ] . Pred ; assert ( CurInfo . isValid ( ) && <STR_LIT> ) ; if ( needVSETVLI ( NewInfo , CurInfo ) ) { if ( needVSETVLIPHI ( NewInfo , MBB ) ) insertVSETVLI ( MBB , MI , NewInfo , CurInfo ) ; CurInfo = NewInfo ; } } else { if ( needVSETVLI ( MI , NewInfo , CurInfo ) ) { insertVSETVLI ( MBB , MI , NewInfo , CurInfo ) ; CurInfo = NewInfo ; } } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { CurInfo = <STR_LIT> ( ) ; } } if ( ! UseStrictAsserts ) { const VSETVLIInfo & ExitInfo = BlockInfo [ MBB . getNumber ( ) ] . Exit ; if ( CurInfo . isValid ( ) && ExitInfo . isValid ( ) && ! ExitInfo . isUnknown ( ) && CurInfo != ExitInfo ) { auto InsertPt = MBB . getFirstInstrTerminator ( ) ; insertVSETVLI ( MBB , InsertPt , MBB . findDebugLoc ( InsertPt ) , ExitInfo , CurInfo ) ; CurInfo = ExitInfo ; } }"
LLVM,RISCV,1589,"Predict the next statement of this code snippet:
 <s> unsigned getSEW ( ) const { return SEW ;"
LLVM,RISCV,1590,"Predict the next statement of this code snippet:
 <s> unsigned getSEW ( ) const { return SEW ;"
LLVM,RISCV,1591,"Predict the next statement of this code snippet:
 <s> <STR_LIT> getVLMUL ( ) const { return VLMul ;"
LLVM,RISCV,1592,"Predict the next statement of this code snippet:
 <s> return VLMul ;"
LLVM,RISCV,1593,"Predict the next statement of this code snippet:
 <s> static unsigned getVLOpNum ( const MachineInstr & MI ) { return <STR_LIT> ( MI . getDesc ( ) ) ;"
LLVM,RISCV,1594,"Predict the next statement of this code snippet:
 <s> if ( hasSameVTYPE ( Require ) ) return true ;"
LLVM,RISCV,1595,"Predict the next statement of this code snippet:
 <s> bool hasCompatibleVTYPE ( const VSETVLIInfo & Require ) const { if ( hasSameVTYPE ( Require ) ) return true ;"
LLVM,RISCV,1596,"Predict the next statement of this code snippet:
 <s> static bool hasFixedResult ( const VSETVLIInfo & Info , const <ISA_LIT>Subtarget & ST ) { if ( ! Info . hasAVLImm ( ) ) return <STR_LIT> == Info . getAVLReg ( ) ;"
LLVM,RISCV,1597,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addImm ( Info . getAVLImm ( ) ) . addImm ( Info . encodeVTYPE ( ) ) ; return ; } Register AVLReg = Info . getAVLReg ( ) ; if ( AVLReg == <STR_LIT> ) { if ( PrevInfo . isValid ( ) && ! PrevInfo . isUnknown ( ) && Info . hasSameVLMAX ( PrevInfo ) ) { BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Info . encodeVTYPE ( ) ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return ; }"
LLVM,RISCV,1598,"Predict the next statement of this code snippet:
 <s> if ( SEWLMULRatioOnly ) return false ; if ( Require . hasAVLReg ( ) && Require . AVLReg == <STR_LIT> ) if ( SEW == Require . SEW ) return true ; if ( Require . ScalarMovOp && Require . hasAVLImm ( ) && ( ( hasNonZeroAVL ( ) && Require . hasNonZeroAVL ( ) ) || ( hasZeroAVL ( ) && Require . hasZeroAVL ( ) ) ) && hasSameSEW ( Require ) && hasSamePolicy ( Require ) ) return true ; if ( ! hasSameAVL ( Require ) ) return false ; if ( hasCompatibleVTYPE ( Require ) ) return true ; if ( Require . StoreOp && VLMul == Require . VLMul && SEW == Require . SEW ) return true ;"
LLVM,RISCV,1599,"Predict the next statement of this code snippet:
 <s> if ( ! hasSameAVL ( Require ) ) return false ;"
LLVM,RISCV,1600,"Predict the next statement of this code snippet:
 <s> assert ( <STR_LIT> == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;"
LLVM,RISCV,1601,"Predict the next statement of this code snippet:
 <s> static bool isVLPreservingConfig ( const MachineInstr & MI ) { if ( MI . getOpcode ( ) != <STR_LIT> ) return false ;"
LLVM,RISCV,1602,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InsertVSETVLI :: needVSETVLI ( const MachineInstr & MI , const VSETVLIInfo & Require , const VSETVLIInfo & CurInfo ) const { if ( ! needVSETVLI ( Require , CurInfo ) ) return false ; return ! canSkipVSETVLIForLoadStore ( MI , Require , CurInfo ) ;"
LLVM,RISCV,1603,"Predict the next statement of this code snippet:
 <s> const BlockData & PBBInfo = BlockInfo [ PBB -> getNumber ( ) ] ; if ( PBBInfo . Exit . isUnknown ( ) || ! PBBInfo . Exit . hasCompatibleVTYPE ( Require ) ) return true ; MachineInstr * DefMI = MRI -> getVRegDef ( InReg ) ; if ( ! DefMI || ! isVectorConfigInstr ( * DefMI ) ) return true ; VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( ! DefInfo . hasSameAVL ( PBBInfo . Exit ) || ! DefInfo . hasSameVTYPE ( PBBInfo . Exit ) ) return true ;"
LLVM,RISCV,1604,"Predict the next statement of this code snippet:
 <s> if ( hasAVLReg ( ) ) OS << <STR_LIT> << ( unsigned ) AVLReg ; if ( hasAVLImm ( ) ) OS << <STR_LIT> << ( unsigned ) AVLImm ;"
LLVM,RISCV,1605,"Predict the next statement of this code snippet:
 <s> assert ( BlockInfo . empty ( ) && <STR_LIT> ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineBasicBlock & MBB : MF ) doLocalPrepass ( MBB ) ; bool HaveVectorOp = false ; for ( const MachineBasicBlock & MBB : MF ) { HaveVectorOp |= computeVLVTYPEChanges ( MBB ) ; BlockData & BBInfo = BlockInfo [ MBB . getNumber ( ) ] ; BBInfo . Exit = BBInfo . Change ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( MBB ) << <STR_LIT> << BBInfo . Exit << <STR_LIT> ) ; } if ( ! HaveVectorOp ) { BlockInfo . clear ( ) ; return false ; } for ( const MachineBasicBlock & MBB : MF ) { WorkList . push ( & MBB ) ; BlockInfo [ MBB . getNumber ( ) ] . InQueue = true ; } while ( ! WorkList . empty ( ) ) { const MachineBasicBlock & MBB = * WorkList . front ( ) ; WorkList . pop ( ) ; computeIncomingVLVTYPE ( MBB ) ; } for ( MachineBasicBlock & MBB : MF ) doPRE ( MBB ) ; for ( MachineBasicBlock & MBB : MF ) emitVSETVLIs ( MBB ) ; for ( MachineBasicBlock & MBB : MF ) doLocalPostpass ( MBB ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) {"
LLVM,RISCV,1606,"Predict the next statement of this code snippet:
 <s> UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } } if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; if ( VLOp . isImm ( ) ) InstrInfo . setAVLImm ( VLOp . getImm ( ) ) ; else InstrInfo . setAVLReg ( VLOp . getReg ( ) ) ; } else InstrInfo . setAVLReg ( <STR_LIT> ) ; InstrInfo . setVTYPE ( VLMul , SEW , TailAgnostic , false ) ;"
LLVM,RISCV,1607,"Predict the next statement of this code snippet:
 <s> if ( ! BBInfo . Change . isValid ( ) ) { BBInfo . Change = NewInfo ; } else { if ( needVSETVLI ( NewInfo , BBInfo . Change ) ) BBInfo . Change = NewInfo ; } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) {"
LLVM,RISCV,1608,"Predict the next statement of this code snippet:
 <s> BlockData & BBInfo = BlockInfo [ MBB . getNumber ( ) ] ; for ( const MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { HadVectorOp = true ; BBInfo . Change = getInfoForVSETVLI ( MI ) ; continue ; } uint64_t TSFlags = MI . getDesc ( ) . TSFlags ; if ( <STR_LIT> ( TSFlags ) ) { HadVectorOp = true ; VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( ! BBInfo . Change . isValid ( ) ) { BBInfo . Change = NewInfo ; } else { if ( needVSETVLI ( NewInfo , BBInfo . Change ) ) BBInfo . Change = NewInfo ; } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { BBInfo . Change = <STR_LIT> ( ) ; }"
LLVM,RISCV,1609,"Predict the next statement of this code snippet:
 <s> MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; if ( ! CurInfo . isValid ( ) ) { assert ( BlockInfo [ MBB . getNumber ( ) ] . Pred . isValid ( ) && <STR_LIT> ) ; if ( needVSETVLI ( NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) ) { insertVSETVLI ( MBB , MI , NewInfo ) ; CurInfo = NewInfo ; } } else { if ( needVSETVLI ( NewInfo , CurInfo ) ) { insertVSETVLI ( MBB , MI , NewInfo ) ; CurInfo = NewInfo ; } } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { CurInfo = <STR_LIT> ( ) ; }"
LLVM,RISCV,1610,"Predict the next statement of this code snippet:
 <s> return <ISA_LIT>VType :: encodeVTYPE ( VLMul , SEW , TailAgnostic , MaskAgnostic ) ;"
LLVM,RISCV,1611,"Predict the next statement of this code snippet:
 <s> return <ISA_LIT>VType :: encodeVTYPE ( VLMul , SEW , TailAgnostic , MaskAgnostic ) ;"
LLVM,RISCV,1612,"Predict the next statement of this code snippet:
 <s> NewInfo . setAVLReg ( AVLReg ) ; } else { assert ( MI . getOpcode ( ) == <STR_LIT> ) ; NewInfo . setAVLImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } NewInfo . setVTYPE ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return NewInfo ;"
LLVM,RISCV,1613,"Predict the next statement of this code snippet:
 <s> bool hasSameVTYPE ( const VSETVLIInfo & Other ) const { assert ( isValid ( ) && Other . isValid ( ) && <STR_LIT> ) ;"
LLVM,RISCV,1614,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Info . encodeVTYPE ( ) ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return ; } Register DestReg = <STR_LIT> ; if ( AVLReg == <STR_LIT> ) DestReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ;"
LLVM,RISCV,1615,"Predict the next statement of this code snippet:
 <s> if ( * this == Other ) return * this ;"
LLVM,RISCV,1616,"Predict the next statement of this code snippet:
 <s> if ( ! isValid ( ) ) return Other ; if ( * this == Other ) return * this ; return <STR_LIT> ( ) ;"
LLVM,RISCV,1617,"Predict the next statement of this code snippet:
 <s> if ( hasAVLImm ( ) != Other . hasAVLImm ( ) ) return false ; if ( hasAVLImm ( ) ) return getAVLImm ( ) == Other . getAVLImm ( ) ;"
LLVM,RISCV,1618,"Predict the next statement of this code snippet:
 <s> if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( DefInfo . hasSameAVL ( CurInfo ) && DefInfo . hasSameVTYPE ( CurInfo ) ) return false ; } }"
LLVM,RISCV,1619,"Predict the next statement of this code snippet:
 <s> void setVTYPE ( <STR_LIT> L , unsigned S , bool TA , bool MA ) { assert ( isValid ( ) && ! isUnknown ( ) && <STR_LIT> ) ;"
LLVM,RISCV,1620,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) {"
LLVM,RISCV,1621,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) {"
LLVM,RISCV,1622,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> ( TSFlags ) ) { HadVectorOp = true ; VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( ! BBInfo . Change . isValid ( ) ) { BBInfo . Change = NewInfo ; } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , BBInfo . Change ) && needVSETVLI ( NewInfo , BBInfo . Change ) ) BBInfo . Change = NewInfo ; } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) {"
LLVM,RISCV,1623,"Predict the next statement of this code snippet:
 <s> DebugLoc DL = MI . getDebugLoc ( ) ; if ( PrevInfo . isValid ( ) && ! PrevInfo . isUnknown ( ) && Info . hasSameAVL ( PrevInfo ) && Info . hasSameVLMAX ( PrevInfo ) ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Info . encodeVTYPE ( ) ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return ; } if ( Info . hasAVLImm ( ) ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addImm ( Info . getAVLImm ( ) ) . addImm ( Info . encodeVTYPE ( ) ) ;"
LLVM,RISCV,1624,"Predict the next statement of this code snippet:
 <s> return ; } if ( Info . hasAVLImm ( ) ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addImm ( Info . getAVLImm ( ) ) . addImm ( Info . encodeVTYPE ( ) ) ; return ; } Register AVLReg = Info . getAVLReg ( ) ; if ( AVLReg == <STR_LIT> ) { if ( PrevInfo . isValid ( ) && ! PrevInfo . isUnknown ( ) && Info . hasSameVLMAX ( PrevInfo ) ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Info . encodeVTYPE ( ) ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return ; }"
LLVM,RISCV,1625,"Predict the next statement of this code snippet:
 <s> if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ;"
LLVM,RISCV,1626,"Predict the next statement of this code snippet:
 <s> Register InReg = PHI -> getOperand ( PHIOp ) . getReg ( ) ; MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ; const BlockData & PBBInfo = BlockInfo [ PBB -> getNumber ( ) ] ; if ( PBBInfo . Exit . isUnknown ( ) || ! PBBInfo . Exit . hasSameVTYPE ( Require ) ) return true ; MachineInstr * DefMI = MRI -> getVRegDef ( InReg ) ;"
LLVM,RISCV,1627,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ; const BlockData & PBBInfo = BlockInfo [ PBB -> getNumber ( ) ] ; if ( PBBInfo . Exit . isUnknown ( ) || ! PBBInfo . Exit . hasSameVTYPE ( Require ) ) return true ; MachineInstr * DefMI = MRI -> getVRegDef ( InReg ) ; if ( ! DefMI || ( DefMI -> getOpcode ( ) != <STR_LIT> && DefMI -> getOpcode ( ) != <STR_LIT> ) ) return true ; VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( ! DefInfo . hasSameAVL ( PBBInfo . Exit ) || ! DefInfo . hasSameVTYPE ( PBBInfo . Exit ) ) return true ; } return false ;"
LLVM,RISCV,1628,"Predict the next statement of this code snippet:
 <s> TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI -> getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } } if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; if ( VLOp . isImm ( ) ) InstrInfo . setAVLImm ( VLOp . getImm ( ) ) ; else InstrInfo . setAVLReg ( VLOp . getReg ( ) ) ; } else InstrInfo . setAVLReg ( <STR_LIT> ) ; InstrInfo . setVTYPE ( VLMul , SEW , TailAgnostic , false , MaskRegOp ) ;"
LLVM,RISCV,1629,"Predict the next statement of this code snippet:
 <s> std :: tie ( LMul , Fractional ) = <ISA_LIT>VType :: decodeVLMUL ( VLMul ) ; LMul = Fractional ? ( <NUM_LIT> / LMul ) : ( LMul * <NUM_LIT> ) ;"
LLVM,RISCV,1630,"Predict the next statement of this code snippet:
 <s> BlockData ( ) {"
LLVM,RISCV,1631,"Predict the next statement of this code snippet:
 <s> BlockData ( ) {"
LLVM,RISCV,1632,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo InInfo ; if ( MBB . pred_empty ( ) ) { InInfo . setUnknown ( ) ; } else { for ( MachineBasicBlock * P : MBB . predecessors ( ) ) InInfo = InInfo . intersect ( BlockInfo [ P -> getNumber ( ) ] . Exit ) ; } if ( ! InInfo . isValid ( ) ) return ; BBInfo . Pred = InInfo ; VSETVLIInfo TmpStatus = BBInfo . Pred . merge ( BBInfo . Change ) ; if ( BBInfo . Exit == TmpStatus ) return ; BBInfo . Exit = TmpStatus ;"
LLVM,RISCV,1633,"Predict the next statement of this code snippet:
 <s> if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; bool StoreOp = MI . getNumExplicitDefs ( ) == <NUM_LIT> ; if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( NumOperands - <NUM_LIT> ) ; if ( VLOp . isImm ( ) ) {"
LLVM,RISCV,1634,"Predict the next statement of this code snippet:
 <s> if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { HadVectorOp = true ; BBInfo . Change = getInfoForVSETVLI ( MI ) ; continue ; } uint64_t TSFlags = MI . getDesc ( ) . TSFlags ; if ( <STR_LIT> ( TSFlags ) ) { HadVectorOp = true ; VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( ! BBInfo . Change . isValid ( ) ) { BBInfo . Change = NewInfo ;"
LLVM,RISCV,1635,"Predict the next statement of this code snippet:
 <s> HadVectorOp = true ; VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( ! BBInfo . Change . isValid ( ) ) { BBInfo . Change = NewInfo ; } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , BBInfo . Change ) && needVSETVLI ( NewInfo , BBInfo . Change ) ) BBInfo . Change = NewInfo ; } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { BBInfo . Change = <STR_LIT> ( ) ;"
LLVM,RISCV,1636,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>InsertVSETVLIPass ( ) {"
LLVM,RISCV,1637,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>InsertVSETVLI ( ) ;"
LLVM,RISCV,1638,"Predict the next statement of this code snippet:
 <s> if ( ! Register :: isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ; MI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MI ) return nullptr ;"
LLVM,RISCV,1639,"Predict the next statement of this code snippet:
 <s> static MachineInstr * elideCopies ( MachineInstr * MI , const MachineRegisterInfo * MRI ) { while ( true ) {"
LLVM,RISCV,1640,"Predict the next statement of this code snippet:
 <s> MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; if ( ! CurInfo . isValid ( ) ) { assert ( BlockInfo [ MBB . getNumber ( ) ] . Pred . isValid ( ) && <STR_LIT> ) ; if ( needVSETVLI ( NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) && needVSETVLIPHI ( NewInfo , MBB ) ) { insertVSETVLI ( MBB , MI , NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) ; CurInfo = NewInfo ; } } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , CurInfo ) && needVSETVLI ( NewInfo , CurInfo ) ) { bool NeedInsertVSETVLI = true ; if ( PrevVSETVLIMI ) { bool HasSameAVL = CurInfo . hasSameAVL ( NewInfo ) || ( NewInfo . hasAVLReg ( ) && NewInfo . getAVLReg ( ) . isVirtual ( ) && NewInfo . getAVLReg ( ) == PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( HasSameAVL && CurInfo . getSEWLMULRatio ( ) == NewInfo . getSEWLMULRatio ( ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI = false ; } } if ( NeedInsertVSETVLI ) insertVSETVLI ( MBB , MI , NewInfo , CurInfo ) ; CurInfo = NewInfo ; } }"
LLVM,RISCV,1641,"Predict the next statement of this code snippet:
 <s> if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setIsDead ( false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDead ( false ) ; CurInfo = getInfoForVSETVLI ( MI ) ; PrevVSETVLIMI = & MI ; continue ; } uint64_t TSFlags = MI . getDesc ( ) . TSFlags ; if ( <STR_LIT> ( TSFlags ) ) { VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( <STR_LIT> ( TSFlags ) ) { unsigned Offset = <NUM_LIT> ; if ( <STR_LIT> ( TSFlags ) ) Offset = <NUM_LIT> ; MachineOperand & VLOp = MI . getOperand ( MI . getNumExplicitOperands ( ) - Offset ) ; if ( VLOp . isReg ( ) ) { VLOp . setReg ( <STR_LIT> ) ; VLOp . setIsKill ( false ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; }"
LLVM,RISCV,1642,"Predict the next statement of this code snippet:
 <s> assert ( hasAVLImm ( ) ) ; return AVLImm ;"
LLVM,RISCV,1643,"Predict the next statement of this code snippet:
 <s> unsigned getAVLImm ( ) const { assert ( hasAVLImm ( ) ) ; return AVLImm ;"
LLVM,RISCV,1644,"Predict the next statement of this code snippet:
 <s> assert ( hasAVLReg ( ) ) ; return AVLReg ;"
LLVM,RISCV,1645,"Predict the next statement of this code snippet:
 <s> assert ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ; Register AVLReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ( AVLReg != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) && <STR_LIT> ) ; NewInfo . setAVLReg ( AVLReg ) ;"
LLVM,RISCV,1646,"Predict the next statement of this code snippet:
 <s> static VSETVLIInfo getInfoForVSETVLI ( const MachineInstr & MI ) { VSETVLIInfo NewInfo ; if ( MI . getOpcode ( ) == <STR_LIT> ) { NewInfo . setAVLImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else { assert ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ; Register AVLReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ( AVLReg != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) && <STR_LIT> ) ; NewInfo . setAVLReg ( AVLReg ) ; } NewInfo . setVTYPE ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ;"
LLVM,RISCV,1647,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <ISA_LIT>_INSERT_VSETVLI_NAME ;"
LLVM,RISCV,1648,"Predict the next statement of this code snippet:
 <s> return <ISA_LIT>_INSERT_VSETVLI_NAME ;"
LLVM,RISCV,1649,"Predict the next statement of this code snippet:
 <s> unsigned getSEWLMULRatio ( ) const {"
LLVM,RISCV,1650,"Predict the next statement of this code snippet:
 <s> assert ( isValid ( ) && ! isUnknown ( ) && <STR_LIT> ) ; return getSEWLMULRatio ( SEW , VLMul ) ;"
LLVM,RISCV,1651,"Predict the next statement of this code snippet:
 <s> Info . setUnknown ( ) ; return Info ;"
LLVM,RISCV,1652,"Predict the next statement of this code snippet:
 <s> bool hasAVLImm ( ) const { return State == AVLIsImm ;"
LLVM,RISCV,1653,"Predict the next statement of this code snippet:
 <s> bool hasAVLImm ( ) const { return State == AVLIsImm ;"
LLVM,RISCV,1654,"Predict the next statement of this code snippet:
 <s> return State == AVLIsReg ;"
LLVM,RISCV,1655,"Predict the next statement of this code snippet:
 <s> assert ( ! isUnknown ( ) && ! Other . isUnknown ( ) && <STR_LIT> ) ; if ( hasAVLReg ( ) && Other . hasAVLReg ( ) ) return getAVLReg ( ) == Other . getAVLReg ( ) ; if ( hasAVLImm ( ) && Other . hasAVLImm ( ) ) return getAVLImm ( ) == Other . getAVLImm ( ) ; return false ;"
LLVM,RISCV,1656,"Predict the next statement of this code snippet:
 <s> if ( hasAVLReg ( ) && Other . hasAVLReg ( ) ) return getAVLReg ( ) == Other . getAVLReg ( ) ; if ( hasAVLImm ( ) && Other . hasAVLImm ( ) ) return getAVLImm ( ) == Other . getAVLImm ( ) ;"
LLVM,RISCV,1657,"Predict the next statement of this code snippet:
 <s> bool hasSameVLMAX ( const VSETVLIInfo & Other ) const { assert ( isValid ( ) && Other . isValid ( ) && <STR_LIT> ) ;"
LLVM,RISCV,1658,"Predict the next statement of this code snippet:
 <s> assert ( ! isUnknown ( ) && ! Other . isUnknown ( ) && <STR_LIT> ) ; return getSEWLMULRatio ( ) == Other . getSEWLMULRatio ( ) ;"
LLVM,RISCV,1659,"Predict the next statement of this code snippet:
 <s> bool hasSameVTYPE ( const VSETVLIInfo & Other ) const { assert ( isValid ( ) && Other . isValid ( ) && <STR_LIT> ) ; assert ( ! isUnknown ( ) && ! Other . isUnknown ( ) && <STR_LIT> ) ; assert ( ! SEWLMULRatioOnly && ! Other . SEWLMULRatioOnly && <STR_LIT> ) ; return std :: tie ( VLMul , SEW , TailAgnostic , MaskAgnostic ) == std :: tie ( Other . VLMul , Other . SEW , Other . TailAgnostic , Other . MaskAgnostic ) ;"
LLVM,RISCV,1660,"Predict the next statement of this code snippet:
 <s> bool hasSEWLMULRatioOnly ( ) const { return SEWLMULRatioOnly ;"
LLVM,RISCV,1661,"Predict the next statement of this code snippet:
 <s> return ; } if ( Info . hasAVLImm ( ) ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addImm ( Info . getAVLImm ( ) ) . addImm ( Info . encodeVTYPE ( ) ) ; return ; } Register AVLReg = Info . getAVLReg ( ) ; if ( AVLReg == <STR_LIT> ) { if ( PrevInfo . isValid ( ) && ! PrevInfo . isUnknown ( ) && Info . hasSameVLMAX ( PrevInfo ) ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Info . encodeVTYPE ( ) ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return ; }"
LLVM,RISCV,1662,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo intersect ( const VSETVLIInfo & Other ) const { if ( ! Other . isValid ( ) ) return * this ;"
LLVM,RISCV,1663,"Predict the next statement of this code snippet:
 <s> if ( hasSameVTYPE ( InstrInfo ) ) return true ; if ( Strict ) return false ; if ( InstrInfo . MaskRegOp && hasSameVLMAX ( InstrInfo ) && TailAgnostic == InstrInfo . TailAgnostic && MaskAgnostic == InstrInfo . MaskAgnostic ) return true ;"
LLVM,RISCV,1664,"Predict the next statement of this code snippet:
 <s> assert ( EEW == InstrInfo . SEW && <STR_LIT> ) ; if ( isUnknown ( ) || hasSEWLMULRatioOnly ( ) ) return false ; if ( ! hasSameAVL ( InstrInfo ) ) return false ;"
LLVM,RISCV,1665,"Predict the next statement of this code snippet:
 <s> bool isUnknown ( ) const {"
LLVM,RISCV,1666,"Predict the next statement of this code snippet:
 <s> bool isUnknown ( ) const {"
LLVM,RISCV,1667,"Predict the next statement of this code snippet:
 <s> bool isValid ( ) const {"
LLVM,RISCV,1668,"Predict the next statement of this code snippet:
 <s> if ( isCompatible ( Other , true ) ) return * this ; return Other ;"
LLVM,RISCV,1669,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo merge ( const VSETVLIInfo & Other ) const { assert ( isValid ( ) && <STR_LIT> ) ; if ( ! Other . isValid ( ) ) return * this ; if ( isCompatible ( Other , true ) ) return * this ; return Other ;"
LLVM,RISCV,1670,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InsertVSETVLI :: needVSETVLI ( const VSETVLIInfo & Require , const VSETVLIInfo & CurInfo ) { if ( CurInfo . isCompatible ( Require , false ) ) return false ; if ( ! CurInfo . isUnknown ( ) && Require . hasAVLReg ( ) && Require . getAVLReg ( ) . isVirtual ( ) && ! CurInfo . hasSEWLMULRatioOnly ( ) && Require . hasSameVTYPE ( CurInfo ) ) { if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) {"
LLVM,RISCV,1671,"Predict the next statement of this code snippet:
 <s> if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( DefInfo . hasSameAVL ( CurInfo ) && DefInfo . hasSameVTYPE ( CurInfo ) ) return false ; } } }"
LLVM,RISCV,1672,"Predict the next statement of this code snippet:
 <s> if ( DisableInsertVSETVLPHIOpt ) return true ; if ( ! Require . hasAVLReg ( ) ) return true ; Register AVLReg = Require . getAVLReg ( ) ; if ( ! AVLReg . isVirtual ( ) ) return true ; MachineInstr * PHI = MRI -> getVRegDef ( AVLReg ) ; if ( ! PHI || PHI -> getOpcode ( ) != <STR_LIT> || PHI -> getParent ( ) != & MBB ) return true ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = PHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register InReg = PHI -> getOperand ( PHIOp ) . getReg ( ) ; MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ;"
LLVM,RISCV,1673,"Predict the next statement of this code snippet:
 <s> initialize<ISA_LIT>InsertVSETVLIPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,RISCV,1674,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InsertVSETVLI ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>InsertVSETVLIPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,RISCV,1675,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasStdExtV ( ) ) return false ; TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; assert ( BlockInfo . empty ( ) && <STR_LIT> ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; bool HaveVectorOp = false ; for ( const MachineBasicBlock & MBB : MF ) HaveVectorOp |= computeVLVTYPEChanges ( MBB ) ; if ( HaveVectorOp ) { for ( const MachineBasicBlock & MBB : MF ) {"
LLVM,RISCV,1676,"Predict the next statement of this code snippet:
 <s> void setAVLImm ( unsigned Imm ) { AVLImm = Imm ;"
LLVM,RISCV,1677,"Predict the next statement of this code snippet:
 <s> AVLReg = Reg ;"
LLVM,RISCV,1678,"Predict the next statement of this code snippet:
 <s> void setAVLReg ( Register Reg ) {"
LLVM,RISCV,1679,"Predict the next statement of this code snippet:
 <s> void setUnknown ( ) { State = Unknown ;"
LLVM,RISCV,1680,"Predict the next statement of this code snippet:
 <s> void setVTYPE ( <STR_LIT> L , unsigned S , bool TA , bool MA , bool MRO , bool IsStore ) { assert ( isValid ( ) && ! isUnknown ( ) && <STR_LIT> ) ; VLMul = L ; SEW = S ; TailAgnostic = TA ; MaskAgnostic = MA ; MaskRegOp = MRO ; StoreOp = IsStore ;"
LLVM,RISCV,1681,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) , TailAgnostic ( false ) , MaskAgnostic ( false ) , MaskRegOp ( false ) , StoreOp ( false ) , SEWLMULRatioOnly ( false ) {"
LLVM,RISCV,1682,"Predict the next statement of this code snippet:
 <s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) , TailAgnostic ( false ) , MaskAgnostic ( false ) , MaskRegOp ( false ) , StoreOp ( false ) , SEWLMULRatioOnly ( false ) {"
LLVM,RISCV,1683,"Predict the next statement of this code snippet:
 <s> uint64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;"
LLVM,RISCV,1684,"Predict the next statement of this code snippet:
 <s> O << '(' ; O << getRegisterName ( Base ) << ')' ;"
LLVM,RISCV,1685,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printBDAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) {"
LLVM,RISCV,1686,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printBDXAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) {"
LLVM,RISCV,1687,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printBranchTarget ( const MCInst * MI , int opNum , raw_ostream & OS ) { if ( MI -> getOperand ( opNum ) . isImm ( ) ) { OS << <STR_LIT> ; } printOperand ( MI , opNum , OS ) ;"
LLVM,RISCV,1688,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printBranchTarget ( const MCInst * MI , int opNum , raw_ostream & OS ) { if ( MI -> getOperand ( opNum ) . isImm ( ) ) { OS << <STR_LIT> ;"
LLVM,RISCV,1689,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printCallOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printOperand ( MI , OpNum , O ) ;"
LLVM,RISCV,1690,"Predict the next statement of this code snippet:
 <s> static const char * const CondNames [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; uint64_t Imm = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( Imm > <NUM_LIT> && Imm < <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,1691,"Predict the next statement of this code snippet:
 <s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_Mips_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_Mips_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_Mips_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_Mips_TPREL_LO : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS << Offset ; } if ( Kind != MCSymbolRefExpr :: VK_None ) OS << ')' ;"
LLVM,RISCV,1692,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ;"
LLVM,RISCV,1693,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ;"
LLVM,RISCV,1694,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & OS ) { printOperand ( MI , opNum , OS ) ; OS << <STR_LIT> ; OS << getRegisterName ( MI -> getOperand ( opNum + <NUM_LIT> ) . getReg ( ) ) ; OS << <STR_LIT> ;"
LLVM,RISCV,1695,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ; OS << <STR_LIT> ; OS << getRegisterName ( MI -> getOperand ( opNum ) . getReg ( ) ) ;"
LLVM,RISCV,1696,"Predict the next statement of this code snippet:
 <s> printOperand ( MI -> getOperand ( OpNum ) , O ) ;"
LLVM,RISCV,1697,"Predict the next statement of this code snippet:
 <s> printOperand ( MI -> getOperand ( OpNum ) , O ) ;"
LLVM,RISCV,1698,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const {"
LLVM,RISCV,1699,"Predict the next statement of this code snippet:
 <s> if ( MI -> getOperand ( OpNum ) . isImm ( ) ) {"
LLVM,RISCV,1700,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printS20ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ;"
LLVM,RISCV,1701,"Predict the next statement of this code snippet:
 <s> if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ; } else printOperand ( MI , OpNum , O ) ;"
LLVM,RISCV,1702,"Predict the next statement of this code snippet:
 <s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ;"
LLVM,RISCV,1703,"Predict the next statement of this code snippet:
 <s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ; } else printOperand ( MI , OpNum , O ) ;"
LLVM,RISCV,1704,"Predict the next statement of this code snippet:
 <s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;"
LLVM,RISCV,1705,"Predict the next statement of this code snippet:
 <s> assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ;"
LLVM,RISCV,1706,"Predict the next statement of this code snippet:
 <s> if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;"
LLVM,RISCV,1707,"Predict the next statement of this code snippet:
 <s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ;"
LLVM,RISCV,1708,"Predict the next statement of this code snippet:
 <s> if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;"
LLVM,RISCV,1709,"Predict the next statement of this code snippet:
 <s> assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MO . getReg ( ) ) ;"
LLVM,RISCV,1710,"Predict the next statement of this code snippet:
 <s> const MCOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> ;"
LLVM,RISCV,1711,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printFenceArg ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned FenceArg = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'o' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'r' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'w' ;"
LLVM,RISCV,1712,"Predict the next statement of this code snippet:
 <s> unsigned FenceArg = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ;"
LLVM,RISCV,1713,"Predict the next statement of this code snippet:
 <s> assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { printRegName ( O , MO . getReg ( ) ) ; return ; } if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return ;"
LLVM,RISCV,1714,"Predict the next statement of this code snippet:
 <s> assert ( MO . isImm ( ) && <STR_LIT> ) ;"
LLVM,RISCV,1715,"Predict the next statement of this code snippet:
 <s> const MCOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; O << MO . getImm ( ) + <NUM_LIT> ;"
LLVM,RISCV,1716,"Predict the next statement of this code snippet:
 <s> unsigned Lmul = Imm & <NUM_LIT> ; Lmul = <NUM_LIT> << Lmul ; Sew = <NUM_LIT> << ( Sew + <NUM_LIT> ) ; O << <STR_LIT> << Sew << <STR_LIT> << Lmul ;"
LLVM,RISCV,1717,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( NoAliases || ! printAliasInstr ( NewMI , STI , O ) ) printInstruction ( NewMI , STI , O ) ;"
LLVM,RISCV,1718,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> << Lmul ; } else { Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } bool TailAgnostic = Imm & <NUM_LIT> ; bool MaskedoffAgnostic = Imm & <NUM_LIT> ; if ( TailAgnostic ) O << <STR_LIT> ; else O << <STR_LIT> ;"
LLVM,RISCV,1719,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printSpecialCapRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ;"
LLVM,RISCV,1720,"Predict the next statement of this code snippet:
 <s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; auto SpecialCapReg = <STR_LIT> ( Imm ) ; if ( SpecialCapReg ) O << SpecialCapReg -> Name ;"
LLVM,RISCV,1721,"Predict the next statement of this code snippet:
 <s> if ( Opt == <STR_LIT> ) { NoAliases = true ; return true ; } if ( Opt == <STR_LIT> ) {"
LLVM,RISCV,1722,"Predict the next statement of this code snippet:
 <s> const MCOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ;"
LLVM,RISCV,1723,"Predict the next statement of this code snippet:
 <s> unsigned FenceArg = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( ( ( FenceArg >> <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'o' ;"
LLVM,RISCV,1724,"Predict the next statement of this code snippet:
 <s> if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( NoAliases || ! printAliasInstr ( NewMI , Address , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ; printAnnotation ( O , Annot ) ;"
LLVM,RISCV,1725,"Predict the next statement of this code snippet:
 <s> bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ;"
LLVM,RISCV,1726,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O , const char * Modifier ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { printRegName ( O , MO . getReg ( ) ) ; return ;"
LLVM,RISCV,1727,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printVTypeI ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ;"
LLVM,RISCV,1728,"Predict the next statement of this code snippet:
 <s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; <ISA_LIT>VType :: printVType ( Imm , O ) ;"
LLVM,RISCV,1729,"Predict the next statement of this code snippet:
 <s> if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ;"
LLVM,RISCV,1730,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MO . isReg ( ) && ( MO . getReg ( ) == <STR_LIT> ) ) { printRegName ( O , <STR_LIT> ) ; return ; } } } if ( MO . isReg ( ) ) {"
LLVM,RISCV,1731,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printVectorRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNo ) . getReg ( ) ; printRegName ( O , Reg ) ;"
LLVM,RISCV,1732,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printVTypeImm ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; unsigned Ediv = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Sew = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lmul = Imm & <NUM_LIT> ; Sew = <NUM_LIT> << ( Sew + <NUM_LIT> ) ; Lmul = <NUM_LIT> << Lmul ; Ediv = <NUM_LIT> << Ediv ; O << <STR_LIT> << Sew ; O << <STR_LIT> << Lmul ;"
LLVM,RISCV,1733,"Predict the next statement of this code snippet:
 <s> unsigned Lmul = Imm & <NUM_LIT> ; Sew = <NUM_LIT> << ( Sew + <NUM_LIT> ) ; Lmul = <NUM_LIT> << Lmul ; Ediv = <NUM_LIT> << Ediv ;"
LLVM,RISCV,1734,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printFRMArg ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { auto FRMArg = static_cast < <STR_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; O << <STR_LIT> ( FRMArg ) ;"
LLVM,RISCV,1735,"Predict the next statement of this code snippet:
 <s> if ( NoAliases || ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ;"
LLVM,RISCV,1736,"Predict the next statement of this code snippet:
 <s> if ( Fractional ) { Lmul = <NUM_LIT> - Lmul ; Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } else { Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } bool TailAgnostic = Imm & <NUM_LIT> ; bool MaskedoffAgnostic = Imm & <NUM_LIT> ; if ( TailAgnostic ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( MaskedoffAgnostic ) O << <STR_LIT> ;"
LLVM,RISCV,1737,"Predict the next statement of this code snippet:
 <s> if ( MC . isReg ( ) ) O << getRegisterName ( MC . getReg ( ) ) ; else if ( MC . isImm ( ) ) O << MC . getImm ( ) ;"
LLVM,RISCV,1738,"Predict the next statement of this code snippet:
 <s> if ( MC . isReg ( ) ) O << getRegisterName ( MC . getReg ( ) ) ; else if ( MC . isImm ( ) ) O << MC . getImm ( ) ; else if ( MC . isExpr ( ) ) MC . getExpr ( ) -> print ( O , & MAI , true ) ;"
LLVM,RISCV,1739,"Predict the next statement of this code snippet:
 <s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ;"
LLVM,RISCV,1740,"Predict the next statement of this code snippet:
 <s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ;"
LLVM,RISCV,1741,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printUimm32contig0Operand ( const MCInst * MI , int OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;"
LLVM,RISCV,1742,"Predict the next statement of this code snippet:
 <s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; O << Value ;"
LLVM,RISCV,1743,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printUimm32contig1endOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;"
LLVM,RISCV,1744,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printUimm32contig1endOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;"
LLVM,RISCV,1745,"Predict the next statement of this code snippet:
 <s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; O << Value ; } else printOperand ( MI , OpNum , O ) ;"
LLVM,RISCV,1746,"Predict the next statement of this code snippet:
 <s> if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'o' ;"
LLVM,RISCV,1747,"Predict the next statement of this code snippet:
 <s> if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'o' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'r' ;"
LLVM,RISCV,1748,"Predict the next statement of this code snippet:
 <s> bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ;"
LLVM,RISCV,1749,"Predict the next statement of this code snippet:
 <s> if ( NoAliases || ! printAliasInstr ( MI , STI , O ) ) printInstruction ( MI , STI , O ) ;"
LLVM,RISCV,1750,"Predict the next statement of this code snippet:
 <s> return true ; } if ( Opt == <STR_LIT> ) { ArchRegNames = true ;"
LLVM,RISCV,1751,"Predict the next statement of this code snippet:
 <s> return getRegisterName ( RegNo , ArchRegNames ? <STR_LIT> : <STR_LIT> ) ;"
LLVM,RISCV,1752,"Predict the next statement of this code snippet:
 <s> if ( ! MO . isImm ( ) ) return printOperand ( MI , OpNo , STI , O ) ; if ( PrintBranchImmAsAddress ) { uint64_t Target = Address + MO . getImm ( ) ; if ( ! STI . hasFeature ( <STR_LIT> ) ) Target &= <NUM_LIT> ; O << formatHex ( Target ) ; } else { O << MO . getImm ( ) ;"
LLVM,RISCV,1753,"Predict the next statement of this code snippet:
 <s> auto SysReg = <STR_LIT> ( Imm ) ;"
LLVM,RISCV,1754,"Predict the next statement of this code snippet:
 <s> auto SysReg = <STR_LIT> ( Imm ) ; if ( SysReg && SysReg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) O << SysReg -> Name ;"
LLVM,RISCV,1755,"Predict the next statement of this code snippet:
 <s> unsigned FenceArg = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( ( ( FenceArg >> <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'o' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'r' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'w' ;"
LLVM,RISCV,1756,"Predict the next statement of this code snippet:
 <s> assert ( ( ( FenceArg >> <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ;"
LLVM,RISCV,1757,"Predict the next statement of this code snippet:
 <s> auto FRMArg = static_cast < <STR_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ;"
LLVM,RISCV,1758,"Predict the next statement of this code snippet:
 <s> MCInst UncompressedMI ; if ( PrintAliases && ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ;"
LLVM,RISCV,1759,"Predict the next statement of this code snippet:
 <s> MCInst UncompressedMI ; if ( PrintAliases && ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ;"
LLVM,RISCV,1760,"Predict the next statement of this code snippet:
 <s> assert ( ( Modifier == nullptr || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { printRegName ( O , MO . getReg ( ) ) ; return ; } if ( MO . isImm ( ) ) {"
LLVM,RISCV,1761,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printZeroOffsetMemOp ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MO . getReg ( ) ) ; O << <STR_LIT> ;"
LLVM,RISCV,1762,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {"
LLVM,RISCV,1763,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {"
LLVM,RISCV,1764,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame -> getObjectSize ( FI ) , MFFrame -> getObjectAlignment ( FI ) ) ;"
LLVM,RISCV,1765,"Predict the next statement of this code snippet:
 <s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame -> getObjectSize ( FI ) , MFFrame -> getObjectAlignment ( FI ) ) ; return MIB . addImm ( Offset ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ;"
LLVM,RISCV,1766,"Predict the next statement of this code snippet:
 <s> if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame -> getObjectSize ( FI ) , MFFrame -> getObjectAlignment ( FI ) ) ; return MIB . addImm ( Offset ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ;"
LLVM,RISCV,1767,"Predict the next statement of this code snippet:
 <s> unsigned ADDI = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDI ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg ; loadImmediate ( MBB , I , & Reg , Amount ) ; BuildMI ( MBB , I , DL , get ( ADD ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ;"
LLVM,RISCV,1768,"Predict the next statement of this code snippet:
 <s> if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDI ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg ; loadImmediate ( MBB , I , & Reg , Amount ) ; BuildMI ( MBB , I , DL , get ( ADD ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ;"
LLVM,RISCV,1769,"Predict the next statement of this code snippet:
 <s> if ( ThisCond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ ) Cond . push_back ( I -> getOperand ( i ) ) ; continue ; } assert ( Cond . size ( ) <= <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != ThisTarget -> getMBB ( ) ) return true ;"
LLVM,RISCV,1770,"Predict the next statement of this code snippet:
 <s> } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ;"
LLVM,RISCV,1771,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) {"
LLVM,RISCV,1772,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const {"
LLVM,RISCV,1773,"Predict the next statement of this code snippet:
 <s> return ( STI . isRV64 ( ) || STI . isRV32 ( ) ) ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,1774,"Predict the next statement of this code snippet:
 <s> return ( STI . isRV64 ( ) || STI . isRV32 ( ) ) ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,1775,"Predict the next statement of this code snippet:
 <s> } if ( isInt < <NUM_LIT> > ( Offset ) && isInt < <NUM_LIT> > ( Offset2 ) ) { return Opcode ; }"
LLVM,RISCV,1776,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: getOpcodeForOffset ( unsigned Opcode , int64_t Offset ) const { int64_t Offset2 = Offset ; if ( isInt < <NUM_LIT> > ( Offset ) && isInt < <NUM_LIT> > ( Offset2 ) ) { return Opcode ; } if ( isInt < <NUM_LIT> > ( Offset ) && isInt < <NUM_LIT> > ( Offset2 ) ) { return Opcode ; }"
LLVM,RISCV,1777,"Predict the next statement of this code snippet:
 <s> unsigned count = InsertBranchAtInst ( MBB , MBB . end ( ) , TBB , Cond , DL ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; count ++ ; return count ;"
LLVM,RISCV,1778,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> | <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> | <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,RISCV,1779,"Predict the next statement of this code snippet:
 <s> case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> :"
LLVM,RISCV,1780,"Predict the next statement of this code snippet:
 <s> Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> | <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> | <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> | <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ;"
LLVM,RISCV,1781,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const {"
LLVM,RISCV,1782,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , <STR_LIT> ) ;"
LLVM,RISCV,1783,"Predict the next statement of this code snippet:
 <s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ( MCID . TSFlags & Flag ) && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;"
LLVM,RISCV,1784,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , <STR_LIT> ) ;"
LLVM,RISCV,1785,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned * Reg , int64_t Value ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned Opcode ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = STI . isRV64 ( ) ? & <STR_LIT> : & <STR_LIT> ; unsigned ZERO = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; * Reg = RegInfo . createVirtualRegister ( RC ) ; if ( isInt < <NUM_LIT> > ( Value ) ) { Opcode = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,1786,"Predict the next statement of this code snippet:
 <s> getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ;"
LLVM,RISCV,1787,"Predict the next statement of this code snippet:
 <s> const MachineOperand * Target ; if ( ! isBranch ( I , Cond , Target ) ) break ; if ( ! Target -> isMBB ( ) ) break ; I -> eraseFromParent ( ) ;"
LLVM,RISCV,1788,"Predict the next statement of this code snippet:
 <s> SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const MachineOperand * Target ; if ( ! isBranch ( I , Cond , Target ) ) break ; if ( ! Target -> isMBB ( ) ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ;"
LLVM,RISCV,1789,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & sti ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( sti ) , STI ( sti ) {"
LLVM,RISCV,1790,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & sti ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( sti ) , STI ( sti ) {"
LLVM,RISCV,1791,"Predict the next statement of this code snippet:
 <s> unsigned LoadOpcode , StoreOpcode ; getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( StoreOpcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ;"
LLVM,RISCV,1792,"Predict the next statement of this code snippet:
 <s> J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ;"
LLVM,RISCV,1793,"Predict the next statement of this code snippet:
 <s> if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ;"
LLVM,RISCV,1794,"Predict the next statement of this code snippet:
 <s> assert ( MIb . mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ;"
LLVM,RISCV,1795,"Predict the next statement of this code snippet:
 <s> MBB . addLiveIn ( <STR_LIT> ) ;"
LLVM,RISCV,1796,"Predict the next statement of this code snippet:
 <s> case CASE_VFMA_SPLATS ( FNMSUB ) : case CASE_VFMA_OPCODE_LMULS ( FMACC , VV ) : case CASE_VFMA_OPCODE_LMULS ( FMSAC , VV ) : case CASE_VFMA_OPCODE_LMULS ( FNMACC , VV ) : case CASE_VFMA_OPCODE_LMULS ( FNMSAC , VV ) : case CASE_VFMA_OPCODE_LMULS ( MADD , VX ) : case CASE_VFMA_OPCODE_LMULS ( NMSUB , VX ) : case CASE_VFMA_OPCODE_LMULS ( MACC , VX ) : case CASE_VFMA_OPCODE_LMULS ( NMSAC , VX ) : case CASE_VFMA_OPCODE_LMULS ( MACC , VV ) : case CASE_VFMA_OPCODE_LMULS ( NMSAC , VV ) : { assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Opc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMACC , FMADD ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMADD , FMACC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMSAC , FMSUB ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMSUB , FMSAC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMACC , FNMADD ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMADD , FNMACC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMSAC , FNMSUB ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMSUB , FNMSAC ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FMACC , FMADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FMSAC , FMSUB , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FNMACC , FNMADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FNMSAC , FNMSUB , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MACC , MADD , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MADD , MACC , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSAC , NMSUB , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSUB , NMSAC , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MACC , MADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSAC , NMSUB , VV ) } auto & WorkingMI = cloneIfNew ( MI ) ;"
LLVM,RISCV,1797,"Predict the next statement of this code snippet:
 <s> case CASE_WIDEOP_OPCODE_LMULS ( FWADD_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( FWSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WADD_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WADDU_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUBU_WV ) : { unsigned NewOpc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADDU_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUBU_WV ) } MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . copyImplicitOps ( MI ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } return MIB ; } } return nullptr ;"
LLVM,RISCV,1798,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADDU_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUBU_WV ) } MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . copyImplicitOps ( MI ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } return MIB ;"
LLVM,RISCV,1799,"Predict the next statement of this code snippet:
 <s> Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( IsScalableVector ) { if ( NF == <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( Opc ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; int I = <NUM_LIT> , End = NF , Incr = <NUM_LIT> ; unsigned SrcEncoding = TRI -> getEncodingValue ( SrcReg ) ; unsigned DstEncoding = TRI -> getEncodingValue ( DstReg ) ; if ( forwardCopyWillClobberTuple ( DstEncoding , SrcEncoding , NF * LMul ) ) {"
LLVM,RISCV,1800,"Predict the next statement of this code snippet:
 <s> const unsigned Mask = <STR_LIT> ; return std :: make_pair ( TF & Mask , TF & ~ Mask ) ;"
LLVM,RISCV,1801,"Predict the next statement of this code snippet:
 <s> return ( ( DstReg - SrcReg ) & <NUM_LIT> ) < NumRegs ;"
LLVM,RISCV,1802,"Predict the next statement of this code snippet:
 <s> int NumOp = MI . getNumExplicitOperands ( ) ;"
LLVM,RISCV,1803,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,1804,"Predict the next statement of this code snippet:
 <s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NF = isRVVSpillForZvlsseg ( Opcode ) -> first ;"
LLVM,RISCV,1805,"Predict the next statement of this code snippet:
 <s> if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; BaseReg = & LdSt . getOperand ( <NUM_LIT> ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ;"
LLVM,RISCV,1806,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) ) return false ;"
LLVM,RISCV,1807,"Predict the next statement of this code snippet:
 <s> return MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,1808,"Predict the next statement of this code snippet:
 <s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return MCInstBuilder ( <STR_LIT> ) ; return MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,1809,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,1810,"Predict the next statement of this code snippet:
 <s> auto CannotInsertCall = [ ] ( outliner :: Candidate & C ) { const TargetRegisterInfo * TRI = C . getMF ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; C . initLRU ( * TRI ) ; LiveRegUnits LRU = C . LRU ; return ! LRU . available ( <STR_LIT> ) ; } ; llvm :: erase_if ( RepeatedSequenceLocs , CannotInsertCall ) ;"
LLVM,RISCV,1811,"Predict the next statement of this code snippet:
 <s> return RI ;"
LLVM,RISCV,1812,"Predict the next statement of this code snippet:
 <s> ArrayRef < std :: pair < unsigned , const char * >> <ISA_LIT>InstrInfo :: getSerializableDirectMachineOperandTargetFlags ( ) const { using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = {"
LLVM,RISCV,1813,"Predict the next statement of this code snippet:
 <s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = {"
LLVM,RISCV,1814,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; int64_t NumOfVReg = Amount / <NUM_LIT> ; Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . setMIFlag ( Flag ) ; assert ( isInt < <NUM_LIT> > ( NumOfVReg ) && <STR_LIT> ) ; if ( isPowerOf2_32 ( NumOfVReg ) ) { uint32_t ShiftAmount = Log2_32 ( NumOfVReg ) ; if ( ShiftAmount == <NUM_LIT> ) return VL ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg - <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg - <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg + <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg + <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( NumOfVReg ) ) movImm ( MBB , II , DL , N , NumOfVReg ) ; else { BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , N ) . addReg ( <STR_LIT> ) . addImm ( NumOfVReg ) . setMIFlag ( Flag ) ; } if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtM ( ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addReg ( N , RegState :: Kill ) . setMIFlag ( Flag ) ; } return VL ;"
LLVM,RISCV,1815,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( NumOfVReg ) ) movImm ( MBB , II , DL , N , NumOfVReg ) ; else { BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , N ) . addReg ( <STR_LIT> ) . addImm ( NumOfVReg ) . setMIFlag ( Flag ) ; } if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtM ( ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addReg ( N , RegState :: Kill ) . setMIFlag ( Flag ) ; } return VL ;"
LLVM,RISCV,1816,"Predict the next statement of this code snippet:
 <s> auto CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , getBrCond ( CC ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; if ( ! FBB ) return <NUM_LIT> ;"
LLVM,RISCV,1817,"Predict the next statement of this code snippet:
 <s> if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto II = MBB . end ( ) ; MachineInstr & MI = * BuildMI ( MBB , II , DL , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define | RegState :: Dead ) . addMBB ( & DestBB , <STR_LIT> ) ; RS -> enterBasicBlockEnd ( MBB ) ; unsigned Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MI . getIterator ( ) , false , <NUM_LIT> ) ;"
LLVM,RISCV,1818,"Predict the next statement of this code snippet:
 <s> assert ( MBB . empty ( ) && <STR_LIT> ) ; assert ( MBB . pred_size ( ) == <NUM_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto II = MBB . end ( ) ; MachineInstr & MI = * BuildMI ( MBB , II , DL , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define | RegState :: Dead ) . addMBB ( & DestBB , <STR_LIT> ) ; RS -> enterBasicBlockEnd ( MBB ) ; unsigned Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MI . getIterator ( ) , false , <NUM_LIT> ) ; MRI . replaceRegWith ( ScratchReg , Scav ) ; MRI . clearVirtRegs ( ) ; RS -> setRegUsed ( Scav ) ; return <NUM_LIT> ;"
LLVM,RISCV,1819,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ;"
LLVM,RISCV,1820,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,1821,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> :"
LLVM,RISCV,1822,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: isBranchOffsetInRange ( unsigned BranchOp , int64_t BrOffset ) const { unsigned XLen = STI . getXLen ( ) ; switch ( BranchOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1823,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ; break ;"
LLVM,RISCV,1824,"Predict the next statement of this code snippet:
 <s> if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ; break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ;"
LLVM,RISCV,1825,"Predict the next statement of this code snippet:
 <s> if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ;"
LLVM,RISCV,1826,"Predict the next statement of this code snippet:
 <s> const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ;"
LLVM,RISCV,1827,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;"
LLVM,RISCV,1828,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB , unsigned & Flags ) const {"
LLVM,RISCV,1829,"Predict the next statement of this code snippet:
 <s> if ( ! <STR_LIT> ( Opcode ) && ! isRVVWholeLoadStore ( Opcode ) && ! isRVVSpillForZvlsseg ( Opcode ) ) return false ; return ! CheckFIs || any_of ( MI . operands ( ) , [ ] ( const MachineOperand & MO ) { return MO . isFI ( ) ; } ) ;"
LLVM,RISCV,1830,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: isRVVSpill ( const MachineInstr & MI , bool CheckFIs ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( ! <STR_LIT> ( Opcode ) && ! isRVVWholeLoadStore ( Opcode ) && ! isRVVSpillForZvlsseg ( Opcode ) ) return false ; return ! CheckFIs || any_of ( MI . operands ( ) , [ ] ( const MachineOperand & MO ) {"
LLVM,RISCV,1831,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1832,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1833,"Predict the next statement of this code snippet:
 <s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,1834,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;"
LLVM,RISCV,1835,"Predict the next statement of this code snippet:
 <s> bool IsZvlsseg = true ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( IsScalableVector ) { MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MemoryLocation :: UnknownSize , MFI . getObjectAlign ( FI ) ) ; MFI . setStackID ( FI , TargetStackID :: ScalableVector ) ;"
LLVM,RISCV,1836,"Predict the next statement of this code snippet:
 <s> IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( IsScalableVector ) { MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MemoryLocation :: UnknownSize , MFI . getObjectAlign ( FI ) ) ; MFI . setStackID ( FI , TargetStackID :: ScalableVector ) ; auto MIB = BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ; if ( IsZvlsseg ) { MIB . addReg ( <STR_LIT> ) ; } } else { MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; }"
LLVM,RISCV,1837,"Predict the next statement of this code snippet:
 <s> unsigned Num = <NUM_LIT> ; if ( ! STI . is64Bit ( ) && ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; <STR_LIT> Seq = <STR_LIT> ( Val , STI . getFeatureBits ( ) ) ; assert ( ! Seq . empty ( ) ) ; for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ; if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( SrcReg , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,1838,"Predict the next statement of this code snippet:
 <s> unsigned Num = <NUM_LIT> ; if ( ! STI . is64Bit ( ) && ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; <STR_LIT> Seq = <STR_LIT> ( Val , STI . getFeatureBits ( ) ) ; assert ( ! Seq . empty ( ) ) ; for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ; if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( SrcReg , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } SrcReg = Result ; }"
LLVM,RISCV,1839,"Predict the next statement of this code snippet:
 <s> static void parseCondBranch ( MachineInstr & LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) {"
LLVM,RISCV,1840,"Predict the next statement of this code snippet:
 <s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; return <NUM_LIT> ;"
LLVM,RISCV,1841,"Predict the next statement of this code snippet:
 <s> I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ;"
LLVM,RISCV,1842,"Predict the next statement of this code snippet:
 <s> auto CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;"
LLVM,RISCV,1843,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , STI ( STI ) {"
LLVM,RISCV,1844,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , STI ( STI ) {"
LLVM,RISCV,1845,"Predict the next statement of this code snippet:
 <s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; unsigned Opcode ; bool IsScalableVector = true ; bool IsZvlsseg = true ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {"
LLVM,RISCV,1846,"Predict the next statement of this code snippet:
 <s> Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : if ( STI . getTargetTriple ( ) . isArch64Bit ( ) ) Ok = isUInt < <NUM_LIT> > ( Imm ) ; else Ok = isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,1847,"Predict the next statement of this code snippet:
 <s> Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,1848,"Predict the next statement of this code snippet:
 <s> unsigned Opc ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( Opc ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,RISCV,1849,"Predict the next statement of this code snippet:
 <s> default : { if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return <NUM_LIT> ; } return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1850,"Predict the next statement of this code snippet:
 <s> for ( ; I != E ; ++ I ) SequenceSize += getInstSizeInBytes ( * I ) ; unsigned CallOverhead = <NUM_LIT> ; for ( auto & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerDefault , CallOverhead ) ; unsigned FrameOverhead = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . getMF ( ) -> getSubtarget ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) FrameOverhead = <NUM_LIT> ;"
LLVM,RISCV,1851,"Predict the next statement of this code snippet:
 <s> if ( MI . isPosition ( ) ) { if ( MI . isCFIInstruction ( ) ) return outliner :: InstrType :: Invisible ; return outliner :: InstrType :: Illegal ; } if ( MI . isInlineAsm ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) && ! MBB -> succ_empty ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isReturn ( ) ) return outliner :: InstrType :: Illegal ;"
LLVM,RISCV,1852,"Predict the next statement of this code snippet:
 <s> unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; if ( ! FBB ) return <NUM_LIT> ; MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ;"
LLVM,RISCV,1853,"Predict the next statement of this code snippet:
 <s> MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ;"
LLVM,RISCV,1854,"Predict the next statement of this code snippet:
 <s> MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; if ( TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;"
LLVM,RISCV,1855,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; }"
LLVM,RISCV,1856,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;"
LLVM,RISCV,1857,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }"
LLVM,RISCV,1858,"Predict the next statement of this code snippet:
 <s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,1859,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ;"
LLVM,RISCV,1860,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: movImm ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsRV64 = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; Register SrcReg = <STR_LIT> ; Register Result = MRI . createVirtualRegister ( & <STR_LIT> ) ;"
LLVM,RISCV,1861,"Predict the next statement of this code snippet:
 <s> Register SrcReg = <STR_LIT> ; Register Result = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Num = <NUM_LIT> ; if ( ! IsRV64 && ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; <STR_LIT> Seq ; <STR_LIT> ( Val , IsRV64 , Seq ) ; assert ( Seq . size ( ) > <NUM_LIT> ) ; for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ;"
LLVM,RISCV,1862,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ;"
LLVM,RISCV,1863,"Predict the next statement of this code snippet:
 <s> case CASE_WIDEOP_OPCODE_LMULS ( WADDU_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUBU_WV ) : { unsigned NewOpc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADDU_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUBU_WV ) } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,1864,"Predict the next statement of this code snippet:
 <s> MachineInstr * <ISA_LIT>InstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MBB , MachineInstr & MI , LiveVariables * LV ) const { switch ( MI . getOpcode ( ) ) { default : break ; case CASE_WIDEOP_OPCODE_LMULS ( FWADD_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( FWSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WADD_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WADDU_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUBU_WV ) : { unsigned NewOpc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADDU_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUBU_WV ) } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . copyImplicitOps ( MI ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } return MIB ;"
LLVM,RISCV,1865,"Predict the next statement of this code snippet:
 <s> MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register SrcReg = <STR_LIT> ; Register Result = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Num = <NUM_LIT> ; if ( ! STI . is64Bit ( ) && ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; <STR_LIT> Seq = <STR_LIT> ( Val , STI . getFeatureBits ( ) ) ; assert ( ! Seq . empty ( ) ) ; for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ; if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> ) {"
LLVM,RISCV,1866,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } SrcReg = Result ; }"
LLVM,RISCV,1867,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : if ( STI . getTargetTriple ( ) . isArch64Bit ( ) ) Ok = isUInt < <NUM_LIT> > ( Imm ) ; else Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; } if ( ! Ok ) { ErrInfo = <STR_LIT> ;"
LLVM,RISCV,1868,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : if ( STI . getTargetTriple ( ) . isArch64Bit ( ) ) Ok = isUInt < <NUM_LIT> > ( Imm ) ; else Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; } if ( ! Ok ) { ErrInfo = <STR_LIT> ; return false ; }"
LLVM,RISCV,1869,"Predict the next statement of this code snippet:
 <s> return TargetInstrInfo :: isMBBSafeToOutlineFrom ( MBB , Flags ) ;"
LLVM,RISCV,1870,"Predict the next statement of this code snippet:
 <s> return TargetInstrInfo :: isMBBSafeToOutlineFrom ( MBB , Flags ) ;"
LLVM,RISCV,1871,"Predict the next statement of this code snippet:
 <s> case CASE_WIDEOP_OPCODE_LMULS ( FWSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WADD_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WADDU_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUBU_WV ) : { unsigned NewOpc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADDU_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUBU_WV ) } MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . copyImplicitOps ( MI ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ;"
LLVM,RISCV,1872,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . copyImplicitOps ( MI ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } if ( LIS ) {"
LLVM,RISCV,1873,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & DestBB , MachineBasicBlock & RestoreBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { assert ( RS && <STR_LIT> ) ; assert ( MBB . empty ( ) && <STR_LIT> ) ; assert ( MBB . pred_size ( ) == <NUM_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ;"
LLVM,RISCV,1874,"Predict the next statement of this code snippet:
 <s> if ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; if ( MBBI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; continue ; } unsigned VType = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( FirstVSetVLI ) { if ( <ISA_LIT>VType :: getSEW ( VType ) != FirstSEW ) return false ; } if ( ! <ISA_LIT>VType :: isTailAgnostic ( VType ) ) return false ; return LMul == <ISA_LIT>VType :: getVLMUL ( VType ) ; } else if ( MBBI -> isInlineAsm ( ) || MBBI -> isCall ( ) ) { return false ; } else if ( MBBI -> getNumDefs ( ) ) { if ( MBBI -> modifiesRegister ( <STR_LIT> ) ) return false ; for ( const MachineOperand & MO : MBBI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; if ( ! FoundDef && TRI -> isSubRegisterEq ( MO . getReg ( ) , SrcReg ) ) { if ( MO . getReg ( ) != SrcReg ) return false ; uint64_t TSFlags = MBBI -> getDesc ( ) . TSFlags ; if ( <STR_LIT> ( TSFlags ) ) return false ; FoundDef = true ; DefMBBI = MBBI ; if ( ! <STR_LIT> ( TSFlags ) ) return false ; break ; } }"
LLVM,RISCV,1875,"Predict the next statement of this code snippet:
 <s> MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const auto & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( TM . isPositionIndependent ( ) || STI . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ; unsigned ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto II = MBB . end ( ) ;"
LLVM,RISCV,1876,"Predict the next statement of this code snippet:
 <s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const auto & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( TM . isPositionIndependent ( ) || STI . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ; unsigned ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto II = MBB . end ( ) ; MachineInstr & LuiMI = * BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScratchReg ) . addMBB ( & DestBB , <STR_LIT> ) ;"
LLVM,RISCV,1877,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,1878,"Predict the next statement of this code snippet:
 <s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,1879,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,1880,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,1881,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , unsigned SrcReg , bool KillSrc ) const { assert ( <STR_LIT> . contains ( DstReg , SrcReg ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,1882,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , unsigned SrcReg , bool KillSrc ) const { assert ( <STR_LIT> . contains ( DstReg , SrcReg ) && <STR_LIT> ) ;"
LLVM,RISCV,1883,"Predict the next statement of this code snippet:
 <s> case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;"
LLVM,RISCV,1884,"Predict the next statement of this code snippet:
 <s> const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; }"
LLVM,RISCV,1885,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {"
LLVM,RISCV,1886,"Predict the next statement of this code snippet:
 <s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;"
LLVM,RISCV,1887,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ;"
LLVM,RISCV,1888,"Predict the next statement of this code snippet:
 <s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ;"
LLVM,RISCV,1889,"Predict the next statement of this code snippet:
 <s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ;"
LLVM,RISCV,1890,"Predict the next statement of this code snippet:
 <s> static bool forwardCopyWillClobberTuple ( unsigned DstReg , unsigned SrcReg , unsigned NumRegs ) { return DstReg > SrcReg && ( DstReg - SrcReg ) < NumRegs ;"
LLVM,RISCV,1891,"Predict the next statement of this code snippet:
 <s> return DstReg > SrcReg && ( DstReg - SrcReg ) < NumRegs ;"
LLVM,RISCV,1892,"Predict the next statement of this code snippet:
 <s> return TargetInstrInfo :: commuteInstructionImpl ( WorkingMI , false , OpIdx1 , OpIdx2 ) ; } case CASE_VFMA_OPCODE_LMULS ( FMADD , VV ) : case CASE_VFMA_OPCODE_LMULS ( FMSUB , VV ) : case CASE_VFMA_OPCODE_LMULS ( FNMADD , VV ) : case CASE_VFMA_OPCODE_LMULS ( FNMSUB , VV ) : { assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; if ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) { unsigned Opc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_VFMA_CHANGE_OPCODE_LMULS ( FMADD , FMACC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FMSUB , FMSAC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FNMADD , FNMACC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FNMSUB , FNMSAC , VV ) } auto & WorkingMI = cloneIfNew ( MI ) ; WorkingMI . setDesc ( get ( Opc ) ) ; return TargetInstrInfo :: commuteInstructionImpl ( WorkingMI , false , OpIdx1 , OpIdx2 ) ; } break ;"
LLVM,RISCV,1893,"Predict the next statement of this code snippet:
 <s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; int64_t NumOfVReg = Amount / <NUM_LIT> ; Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) ; assert ( isInt < <NUM_LIT> > ( NumOfVReg ) && <STR_LIT> ) ; if ( isPowerOf2_32 ( NumOfVReg ) ) { uint32_t ShiftAmount = Log2_32 ( NumOfVReg ) ; if ( ShiftAmount == <NUM_LIT> ) return VL ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addImm ( ShiftAmount ) ; } else if ( isPowerOf2_32 ( NumOfVReg - <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg - <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) ;"
LLVM,RISCV,1894,"Predict the next statement of this code snippet:
 <s> for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ; if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } SrcReg = Result ; }"
LLVM,RISCV,1895,"Predict the next statement of this code snippet:
 <s> case CASE_VFMA_OPCODE_LMULS ( MACC , VV ) : case CASE_VFMA_OPCODE_LMULS ( NMSAC , VV ) : { assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Opc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMACC , FMADD ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMADD , FMACC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMSAC , FMSUB ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMSUB , FMSAC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMACC , FNMADD ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMADD , FNMACC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMSAC , FNMSUB ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMSUB , FNMSAC ) CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 ( FMACC , FMADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 ( FMSAC , FMSUB , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 ( FNMACC , FNMADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 ( FNMSAC , FNMSUB , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MACC , MADD , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MADD , MACC , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSAC , NMSUB , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSUB , NMSAC , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MACC , MADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSAC , NMSUB , VV ) } auto & WorkingMI = cloneIfNew ( MI ) ; WorkingMI . setDesc ( get ( Opc ) ) ; return TargetInstrInfo :: commuteInstructionImpl ( WorkingMI , false , OpIdx1 , OpIdx2 ) ; } case CASE_VFMA_OPCODE_LMULS_MF4 ( FMADD , VV ) : case CASE_VFMA_OPCODE_LMULS_MF4 ( FMSUB , VV ) : case CASE_VFMA_OPCODE_LMULS_MF4 ( FNMADD , VV ) : case CASE_VFMA_OPCODE_LMULS_MF4 ( FNMSUB , VV ) : case CASE_VFMA_OPCODE_LMULS ( MADD , VV ) : case CASE_VFMA_OPCODE_LMULS ( NMSUB , VV ) : { assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; if ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) { unsigned Opc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 ( FMADD , FMACC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 ( FMSUB , FMSAC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 ( FNMADD , FNMACC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 ( FNMSUB , FNMSAC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MADD , MACC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSUB , NMSAC , VV ) } auto & WorkingMI = cloneIfNew ( MI ) ; WorkingMI . setDesc ( get ( Opc ) ) ; return TargetInstrInfo :: commuteInstructionImpl ( WorkingMI , false , OpIdx1 , OpIdx2 ) ; } break ; }"
LLVM,RISCV,1896,"Predict the next statement of this code snippet:
 <s> for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } if ( LIS ) { SlotIndex Idx = LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ; if ( MI . getOperand ( <NUM_LIT> ) . isEarlyClobber ( ) ) { LiveInterval & LI = LIS -> getInterval ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LiveRange :: Segment * S = LI . getSegmentContaining ( Idx ) ; if ( S -> end == Idx . getRegSlot ( true ) ) S -> end = Idx . getRegSlot ( ) ; }"
LLVM,RISCV,1897,"Predict the next statement of this code snippet:
 <s> if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return <NUM_LIT> ; } return get ( Opcode ) . getSize ( ) ;"
LLVM,RISCV,1898,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & DestBB , MachineBasicBlock & RestoreBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { assert ( RS && <STR_LIT> ) ; assert ( MBB . empty ( ) && <STR_LIT> ) ; assert ( MBB . pred_size ( ) == <NUM_LIT> ) ;"
LLVM,RISCV,1899,"Predict the next statement of this code snippet:
 <s> It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) , <NUM_LIT> , <STR_LIT> ) ) ; return It ;"
LLVM,RISCV,1900,"Predict the next statement of this code snippet:
 <s> It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) , <NUM_LIT> , <STR_LIT> ) ) ; return It ;"
LLVM,RISCV,1901,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; bool FoundDef = false ; bool FirstVSetVLI = false ; unsigned FirstSEW = <NUM_LIT> ; while ( MBBI != MBB . begin ( ) ) { -- MBBI ; if ( MBBI -> isMetaInstruction ( ) ) continue ; if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { if ( ! FoundDef ) { if ( ! FirstVSetVLI ) { FirstVSetVLI = true ; unsigned FirstVType = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> FirstLMul = <ISA_LIT>VType :: getVLMUL ( FirstVType ) ; FirstSEW = <ISA_LIT>VType :: getSEW ( FirstVType ) ; if ( FirstLMul != LMul ) return false ; } if ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; if ( MBBI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; continue ;"
LLVM,RISCV,1902,"Predict the next statement of this code snippet:
 <s> if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ; break ;"
LLVM,RISCV,1903,"Predict the next statement of this code snippet:
 <s> for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( SrcReg , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } SrcReg = DstReg ; }"
LLVM,RISCV,1904,"Predict the next statement of this code snippet:
 <s> } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( SrcReg , RegState :: Kill ) . setMIFlag ( Flag ) ; } else {"
LLVM,RISCV,1905,"Predict the next statement of this code snippet:
 <s> } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( IsScalableVector ) { bool UseVMV_V_V = false ; MachineBasicBlock :: const_iterator DefMBBI ; unsigned DefExplicitOpNum ; unsigned VIOpc ; if ( isConvertibleToVMV_V_V ( STI , MBB , MBBI , DefMBBI , LMul ) ) { UseVMV_V_V = true ; DefExplicitOpNum = DefMBBI -> getNumExplicitOperands ( ) ; switch ( LMul ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; VIOpc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; VIOpc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; VIOpc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; VIOpc = <STR_LIT> ; break ; } } bool UseVMV_V_I = false ; if ( UseVMV_V_V && ( DefMBBI -> getOpcode ( ) == VIOpc ) ) { UseVMV_V_I = true ; Opc = VIOpc ; } if ( NF == <NUM_LIT> ) {"
LLVM,RISCV,1906,"Predict the next statement of this code snippet:
 <s> unsigned Imm = MI . getOperand ( OpIdx ) . getImm ( ) ; <ISA_LIT>VType :: printVType ( Imm , OS ) ; } else if ( <STR_LIT> ( TSFlags ) ) { unsigned NumOperands = MI . getNumExplicitOperands ( ) ; bool HasPolicy = <STR_LIT> ( TSFlags ) ; if ( OpIdx != NumOperands - HasPolicy - <NUM_LIT> ) return std :: string ( ) ; unsigned Log2SEW = MI . getOperand ( OpIdx ) . getImm ( ) ;"
LLVM,RISCV,1907,"Predict the next statement of this code snippet:
 <s> } if ( MI . isInlineAsm ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) && ! MBB -> succ_empty ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isReturn ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; for ( const auto & MO : MI . operands ( ) ) if ( MO . isMBB ( ) || MO . isBlockAddress ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return outliner :: InstrType :: Illegal ;"
LLVM,RISCV,1908,"Predict the next statement of this code snippet:
 <s> if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; for ( const auto & MO : MI . operands ( ) ) if ( MO . isMBB ( ) || MO . isBlockAddress ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return outliner :: InstrType :: Illegal ;"
LLVM,RISCV,1909,"Predict the next statement of this code snippet:
 <s> uint32_t ShiftAmount = Log2_32 ( NumOfVReg - <NUM_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg + <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg + <NUM_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; movImm ( MBB , II , DL , N , NumOfVReg , Flag ) ; if ( ! STI . hasStdExtM ( ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addReg ( N , RegState :: Kill ) . setMIFlag ( Flag ) ; }"
LLVM,RISCV,1910,"Predict the next statement of this code snippet:
 <s> } BuildMI ( MBB , II , DL , get ( Opc ) , VL ) . addReg ( VL , RegState :: Kill ) . addReg ( VL ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg - <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg - <NUM_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg + <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg + <NUM_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; movImm ( MBB , II , DL , N , NumOfVReg , Flag ) ; if ( ! STI . hasStdExtM ( ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported {"
LLVM,RISCV,1911,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: movImm ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { Register SrcReg = <STR_LIT> ; if ( ! STI . is64Bit ( ) && ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; <STR_LIT> Seq = <STR_LIT> ( Val , STI . getFeatureBits ( ) ) ; assert ( ! Seq . empty ( ) ) ; for ( <STR_LIT> & Inst : Seq ) { switch ( Inst . getOpndKind ( ) ) { case <STR_LIT> : BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , DstReg ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,1912,"Predict the next statement of this code snippet:
 <s> for ( <STR_LIT> & Inst : Seq ) { switch ( Inst . getOpndKind ( ) ) { case <STR_LIT> : BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , DstReg ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; break ; case <STR_LIT> : BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ; break ; case <STR_LIT> : BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( SrcReg , RegState :: Kill ) . setMIFlag ( Flag ) ; break ; case <STR_LIT> : BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; break ; } SrcReg = DstReg ; }"
LLVM,RISCV,1913,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const {"
LLVM,RISCV,1914,"Predict the next statement of this code snippet:
 <s> is<ISA_LIT>Vector = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; is<ISA_LIT>Vector = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; is<ISA_LIT>Vector = true ; } else llvm_unreachable ( <STR_LIT> ) ; if ( is<ISA_LIT>Vector ) { RVFI -> setHasSpillVRs ( ) ; MFI . setStackID ( FI , TargetStackID :: <ISA_LIT>Vector ) ; BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) ; } else {"
LLVM,RISCV,1915,"Predict the next statement of this code snippet:
 <s> MachineFunction * MF = MBB . getParent ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; bool is<ISA_LIT>Vector = false ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; is<ISA_LIT>Vector = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ;"
LLVM,RISCV,1916,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( Flag ) ; return ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . setMIFlag ( Flag ) ; return ; } unsigned Opc ; bool IsScalableVector = true ; unsigned NF = <NUM_LIT> ; unsigned LMul = <NUM_LIT> ; unsigned SubRegIdx = <STR_LIT> ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ;"
LLVM,RISCV,1917,"Predict the next statement of this code snippet:
 <s> Optional < int64_t > <ISA_LIT>InstrInfo :: getAsIntImmediate ( const MachineOperand & Op , const MachineRegisterInfo & MRI ) const { if ( Op . isImm ( ) ) return Op . getImm ( ) ; if ( Op . isReg ( ) ) { Register Reg = Op . getReg ( ) ; if ( Reg == <STR_LIT> ) return <NUM_LIT> ; if ( Reg . isVirtual ( ) ) { auto * Def = MRI . getUniqueVRegDef ( Reg ) ; switch ( Def -> getOpcode ( ) ) { default : return None ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1918,"Predict the next statement of this code snippet:
 <s> if ( Reg == <STR_LIT> ) return <NUM_LIT> ; if ( Reg . isVirtual ( ) ) { auto * Def = MRI . getUniqueVRegDef ( Reg ) ; switch ( Def -> getOpcode ( ) ) { default : return None ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1919,"Predict the next statement of this code snippet:
 <s> { MO_CALL , <STR_LIT> } , { MO_PLT , <STR_LIT> } , { MO_LO , <STR_LIT> } , { MO_HI , <STR_LIT> } , { MO_PCREL_LO , <STR_LIT> } , { MO_PCREL_HI , <STR_LIT> } , { MO_GOT_HI , <STR_LIT> } , { MO_TPREL_LO , <STR_LIT> } , { MO_TPREL_HI , <STR_LIT> } , { MO_TPREL_ADD , <STR_LIT> } , { MO_TLS_GOT_HI , <STR_LIT> } , { MO_TLS_GD_HI , <STR_LIT> } , { MO_CAPTAB_PCREL_HI , <STR_LIT> } , { MO_TPREL_CINCOFFSET , <STR_LIT> } , { MO_TLS_IE_CAPTAB_PCREL_HI , <STR_LIT> } , { MO_TLS_GD_CAPTAB_PCREL_HI , <STR_LIT> } , { MO_CCALL , <STR_LIT> } } ;"
LLVM,RISCV,1920,"Predict the next statement of this code snippet:
 <s> ArrayRef < std :: pair < unsigned , const char * >> <ISA_LIT>InstrInfo :: getSerializableDirectMachineOperandTargetFlags ( ) const { using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_CALL , <STR_LIT> } , { MO_PLT , <STR_LIT> } , { MO_LO , <STR_LIT> } , { MO_HI , <STR_LIT> } , { MO_PCREL_LO , <STR_LIT> } , { MO_PCREL_HI , <STR_LIT> } , { MO_GOT_HI , <STR_LIT> } , { MO_TPREL_LO , <STR_LIT> } , { MO_TPREL_HI , <STR_LIT> } , { MO_TPREL_ADD , <STR_LIT> } , { MO_TLS_GOT_HI , <STR_LIT> } , { MO_TLS_GD_HI , <STR_LIT> } , { MO_CAPTAB_PCREL_HI , <STR_LIT> } , { MO_TPREL_CINCOFFSET , <STR_LIT> } , { MO_TLS_IE_CAPTAB_PCREL_HI , <STR_LIT> } , { MO_TLS_GD_CAPTAB_PCREL_HI , <STR_LIT> } , { MO_CCALL , <STR_LIT> } } ;"
LLVM,RISCV,1921,"Predict the next statement of this code snippet:
 <s> if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned PseudoOpcode ; if ( <STR_LIT> ( ST . getTargetABI ( ) ) ) PseudoOpcode = <STR_LIT> ; else PseudoOpcode = <STR_LIT> ; if ( Cond . empty ( ) ) { MachineInstr & MI = * BuildMI ( & MBB , DL , get ( PseudoOpcode ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ;"
LLVM,RISCV,1922,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned PseudoOpcode ; if ( <STR_LIT> ( ST . getTargetABI ( ) ) ) PseudoOpcode = <STR_LIT> ; else PseudoOpcode = <STR_LIT> ; if ( Cond . empty ( ) ) {"
LLVM,RISCV,1923,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * RC ; unsigned PseudoOpcode ; if ( <STR_LIT> ( ST . getTargetABI ( ) ) ) { RC = & <STR_LIT> ; PseudoOpcode = <STR_LIT> ; } else { RC = & <STR_LIT> ; PseudoOpcode = <STR_LIT> ; } Register ScratchReg = MRI . createVirtualRegister ( RC ) ; auto II = MBB . end ( ) ; MachineInstr & MI = * BuildMI ( MBB , II , DL , get ( PseudoOpcode ) ) . addReg ( ScratchReg , RegState :: Define | RegState :: Dead ) . addMBB ( & DestBB , <STR_LIT> ) ; RS -> enterBasicBlockEnd ( MBB ) ; unsigned Scav = RS -> scavengeRegisterBackwards ( * RC , MI . getIterator ( ) , false , <NUM_LIT> ) ; MRI . replaceRegWith ( ScratchReg , Scav ) ; MRI . clearVirtRegs ( ) ;"
LLVM,RISCV,1924,"Predict the next statement of this code snippet:
 <s> return true ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1925,"Predict the next statement of this code snippet:
 <s> switch ( Opcode ) { default : break ; case <STR_LIT> : return true ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1926,"Predict the next statement of this code snippet:
 <s> switch ( BranchOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1927,"Predict the next statement of this code snippet:
 <s> switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1928,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Base = & I . getOperand ( <NUM_LIT> ) ; Size = & I . getOperand ( <NUM_LIT> ) ; return true ;"
LLVM,RISCV,1929,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,1930,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {"
LLVM,RISCV,1931,"Predict the next statement of this code snippet:
 <s> IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ;"
LLVM,RISCV,1932,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> ( STI . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> , <STR_LIT> ( STI . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> ) , STI ( STI ) {"
LLVM,RISCV,1933,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> ( STI . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> , <STR_LIT> ( STI . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> ) , STI ( STI ) {"
LLVM,RISCV,1934,"Predict the next statement of this code snippet:
 <s> Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } if ( IsScalableVector ) { MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MemoryLocation :: UnknownSize , MFI . getObjectAlign ( FI ) ) ; MFI . setStackID ( FI , TargetStackID :: ScalableVector ) ; auto MIB = BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ; if ( IsZvlsseg ) { MIB . addReg ( <STR_LIT> ) ; } } else { MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;"
LLVM,RISCV,1935,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget & ST = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; unsigned Opcode ; bool IsScalableVector = true ; bool IsZvlsseg = true ; if ( <STR_LIT> ( ST . getTargetABI ( ) ) ) { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {"
LLVM,RISCV,1936,"Predict the next statement of this code snippet:
 <s> switch ( Opcode ) { default : { if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return <NUM_LIT> ; } return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> :"
LLVM,RISCV,1937,"Predict the next statement of this code snippet:
 <s> int NumTerminators = <NUM_LIT> ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ;"
LLVM,RISCV,1938,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = <NUM_LIT> ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == <NUM_LIT> && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = getBranchDestBlock ( * I ) ;"
LLVM,RISCV,1939,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> :"
LLVM,RISCV,1940,"Predict the next statement of this code snippet:
 <s> return true ; } assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false ;"
LLVM,RISCV,1941,"Predict the next statement of this code snippet:
 <s> Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ;"
LLVM,RISCV,1942,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : Ok = isInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : if ( STI . getTargetTriple ( ) . isArch64Bit ( ) ) Ok = isUInt < <NUM_LIT> > ( Imm ) ; else Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ;"
LLVM,RISCV,1943,"Predict the next statement of this code snippet:
 <s> auto E = MBB . end ( ) ; for ( ; I != E ; ++ I ) { if ( I -> isCFIInstruction ( ) ) { I -> removeFromParent ( ) ; Changed = true ; break ; }"
LLVM,RISCV,1944,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || ( <STR_LIT> . contains ( DstReg ) && <STR_LIT> . contains ( SrcReg ) ) ) { Opc = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opc ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; }"
LLVM,RISCV,1945,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || ( <STR_LIT> . contains ( DstReg ) && <STR_LIT> . contains ( SrcReg ) ) ) { Opc = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opc ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; }"
LLVM,RISCV,1946,"Predict the next statement of this code snippet:
 <s> return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; }"
LLVM,RISCV,1947,"Predict the next statement of this code snippet:
 <s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;"
LLVM,RISCV,1948,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;"
LLVM,RISCV,1949,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : break ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } return <NUM_LIT> ;"
LLVM,RISCV,1950,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;"
LLVM,RISCV,1951,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) ; } else {"
LLVM,RISCV,1952,"Predict the next statement of this code snippet:
 <s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,1953,"Predict the next statement of this code snippet:
 <s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,1954,"Predict the next statement of this code snippet:
 <s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;"
LLVM,RISCV,1955,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ;"
LLVM,RISCV,1956,"Predict the next statement of this code snippet:
 <s> case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; }"
LLVM,RISCV,1957,"Predict the next statement of this code snippet:
 <s> case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;"
LLVM,RISCV,1958,"Predict the next statement of this code snippet:
 <s> unsigned ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto II = MBB . end ( ) ; MachineInstr & LuiMI = * BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScratchReg ) . addMBB ( & DestBB , <STR_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) . addMBB ( & DestBB , <STR_LIT> ) ; RS -> enterBasicBlockEnd ( MBB ) ;"
LLVM,RISCV,1959,"Predict the next statement of this code snippet:
 <s> if ( ShiftAmount == <NUM_LIT> ) return VL ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addImm ( ShiftAmount ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , N ) . addReg ( <STR_LIT> ) . addImm ( NumOfVReg ) ;"
LLVM,RISCV,1960,"Predict the next statement of this code snippet:
 <s> int64_t NumOfVReg = Amount / <NUM_LIT> ; Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) ; assert ( isInt < <NUM_LIT> > ( NumOfVReg ) && <STR_LIT> ) ; if ( isPowerOf2_32 ( NumOfVReg ) ) { uint32_t ShiftAmount = Log2_32 ( NumOfVReg ) ; if ( ShiftAmount == <NUM_LIT> ) return VL ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addImm ( ShiftAmount ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , N ) . addReg ( <STR_LIT> ) . addImm ( NumOfVReg ) ;"
LLVM,RISCV,1961,"Predict the next statement of this code snippet:
 <s> Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; BaseReg = & LdSt . getOperand ( <NUM_LIT> ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ;"
LLVM,RISCV,1962,"Predict the next statement of this code snippet:
 <s> if ( LdSt . getNumExplicitOperands ( ) != <NUM_LIT> ) return false ; if ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) || ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; BaseReg = & LdSt . getOperand ( <NUM_LIT> ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ;"
LLVM,RISCV,1963,"Predict the next statement of this code snippet:
 <s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( IsScalableVector ) { MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MemoryLocation :: UnknownSize , MFI . getObjectAlign ( FI ) ) ; MFI . setStackID ( FI , TargetStackID :: ScalableVector ) ; auto MIB = BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) ; if ( IsZvlsseg ) { Register AddrInc = MF -> getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( AddrInc , RegState :: Define ) ; } MIB . addFrameIndex ( FI ) . addMemOperand ( MMO ) ; if ( IsZvlsseg ) { MIB . addReg ( <STR_LIT> ) ; } } else { MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;"
LLVM,RISCV,1964,"Predict the next statement of this code snippet:
 <s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ;"
LLVM,RISCV,1965,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , unsigned SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ;"
LLVM,RISCV,1966,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,1967,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,1968,"Predict the next statement of this code snippet:
 <s> unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,1969,"Predict the next statement of this code snippet:
 <s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,1970,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ;"
LLVM,RISCV,1971,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( SrcReg , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; }"
LLVM,RISCV,1972,"Predict the next statement of this code snippet:
 <s> unsigned Num = <NUM_LIT> ; if ( ! STI . is64Bit ( ) && ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; <STR_LIT> Seq = <STR_LIT> ( Val , STI . getFeatureBits ( ) ) ; assert ( ! Seq . empty ( ) ) ; for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ; if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> ) {"
LLVM,RISCV,1973,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } }"
LLVM,RISCV,1974,"Predict the next statement of this code snippet:
 <s> } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;"
LLVM,RISCV,1975,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ; break ; } return None ;"
LLVM,RISCV,1976,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ; break ; } return None ;"
LLVM,RISCV,1977,"Predict the next statement of this code snippet:
 <s> TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ ) Cond . push_back ( I -> getOperand ( i ) ) ; continue ; } assert ( Cond . size ( ) <= <NUM_LIT> ) ; assert ( TBB ) ;"
LLVM,RISCV,1978,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; SmallVector < MachineOperand , <NUM_LIT> > ThisCond ; ThisCond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const MachineOperand * ThisTarget ; if ( ! isBranch ( I , ThisCond , ThisTarget ) ) return true ; if ( ! ThisTarget -> isMBB ( ) ) return true ; if ( ThisCond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ;"
LLVM,RISCV,1979,"Predict the next statement of this code snippet:
 <s> else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { Opcode = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,RISCV,1980,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default :"
LLVM,RISCV,1981,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL ) const { if ( FBB ) { unsigned count = InsertBranchAtInst ( MBB , MBB . end ( ) , TBB , Cond , DL ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;"
LLVM,RISCV,1982,"Predict the next statement of this code snippet:
 <s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; count ++ ; return count ; }"
LLVM,RISCV,1983,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> | <STR_LIT> :"
LLVM,RISCV,1984,"Predict the next statement of this code snippet:
 <s> break ; case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> | <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> | <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,RISCV,1985,"Predict the next statement of this code snippet:
 <s> return isSimpleMove ( MI , FrameIndex , <STR_LIT> ) ;"
LLVM,RISCV,1986,"Predict the next statement of this code snippet:
 <s> static int isSimpleMove ( const MachineInstr & MI , int & FrameIndex , int Flag ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( ( MCID . TSFlags & Flag ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,1987,"Predict the next statement of this code snippet:
 <s> const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( ( MCID . TSFlags & Flag ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,1988,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const {"
LLVM,RISCV,1989,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,1990,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : return true ; }"
LLVM,RISCV,1991,"Predict the next statement of this code snippet:
 <s> assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) return true ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false ;"
LLVM,RISCV,1992,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Hi20 ) . setMIFlag ( Flag ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addImm ( Lo12 ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,1993,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: movImm32 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { assert ( isInt < <NUM_LIT> > ( Val ) && <STR_LIT> ) ; uint64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Hi20 ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,1994,"Predict the next statement of this code snippet:
 <s> const MachineOperand * ThisTarget ; if ( ! isBranch ( I , ThisCond , ThisTarget ) ) return true ; if ( ! ThisTarget -> isMBB ( ) ) return true ; if ( ThisCond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ ) Cond . push_back ( I -> getOperand ( i ) ) ; continue ; } assert ( Cond . size ( ) <= <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != ThisTarget -> getMBB ( ) ) return true ; unsigned OldCond = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldCond == ThisCond [ <NUM_LIT> ] . getImm ( ) ) continue ; }"
LLVM,RISCV,1995,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ;"
LLVM,RISCV,1996,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,1997,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & Subtarget ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( Subtarget ) {"
LLVM,RISCV,1998,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & Subtarget ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( Subtarget ) {"
LLVM,RISCV,1999,"Predict the next statement of this code snippet:
 <s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,2000,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , MaxVL ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addDef ( <STR_LIT> ) . addReg ( MaxVL , getKillRegState ( true ) ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addDef ( <STR_LIT> ) . addReg ( SavedVL , getKillRegState ( true ) ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ;"
LLVM,RISCV,2001,"Predict the next statement of this code snippet:
 <s> case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : {"
LLVM,RISCV,2002,"Predict the next statement of this code snippet:
 <s> } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;"
LLVM,RISCV,2003,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , unsigned SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ;"
LLVM,RISCV,2004,"Predict the next statement of this code snippet:
 <s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; }"
LLVM,RISCV,2005,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,2006,"Predict the next statement of this code snippet:
 <s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ;"
LLVM,RISCV,2007,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } return <NUM_LIT> ;"
LLVM,RISCV,2008,"Predict the next statement of this code snippet:
 <s> } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } return <NUM_LIT> ;"
LLVM,RISCV,2009,"Predict the next statement of this code snippet:
 <s> switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }"
LLVM,RISCV,2010,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {"
LLVM,RISCV,2011,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,2012,"Predict the next statement of this code snippet:
 <s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,2013,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: movImm32 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { assert ( isInt < <NUM_LIT> > ( Val ) && <STR_LIT> ) ; uint64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Hi20 ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,2014,"Predict the next statement of this code snippet:
 <s> Target = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ;"
LLVM,RISCV,2015,"Predict the next statement of this code snippet:
 <s> Target = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ; Cond . push_back ( LastInst . getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst . getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2016,"Predict the next statement of this code snippet:
 <s> I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ;"
LLVM,RISCV,2017,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ;"
LLVM,RISCV,2018,"Predict the next statement of this code snippet:
 <s> assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ;"
LLVM,RISCV,2019,"Predict the next statement of this code snippet:
 <s> Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ;"
LLVM,RISCV,2020,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) {"
LLVM,RISCV,2021,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) {"
LLVM,RISCV,2022,"Predict the next statement of this code snippet:
 <s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,2023,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,2024,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , {"
LLVM,RISCV,2025,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , {"
LLVM,RISCV,2026,"Predict the next statement of this code snippet:
 <s> InstructionSelector * create<ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , <ISA_LIT>Subtarget & Subtarget , <ISA_LIT>RegisterBankInfo & RBI ) {"
LLVM,RISCV,2027,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>InstructionSelector ( TM , Subtarget , RBI ) ;"
LLVM,RISCV,2028,"Predict the next statement of this code snippet:
 <s> static const char * getName ( ) {"
LLVM,RISCV,2029,"Predict the next statement of this code snippet:
 <s> static const char * getName ( ) { return DEBUG_TYPE ;"
LLVM,RISCV,2030,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , {"
LLVM,RISCV,2031,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , {"
LLVM,RISCV,2032,"Predict the next statement of this code snippet:
 <s> return true ; }"
LLVM,RISCV,2033,"Predict the next statement of this code snippet:
 <s> return true ; } if ( selectImpl ( I , * CoverageInfo ) ) return true ; return false ;"
LLVM,RISCV,2034,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;"
LLVM,RISCV,2035,"Predict the next statement of this code snippet:
 <s> void dump ( ) { errs ( ) << <STR_LIT> << this << '\n' ; errs ( ) << <STR_LIT> ;"
LLVM,RISCV,2036,"Predict the next statement of this code snippet:
 <s> } if ( Opcode == <STR_LIT> || CurDAG -> isBaseWithConstantOffset ( N ) ) { SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N . getOperand ( <NUM_LIT> ) ; unsigned Op0Code = Op0 -> getOpcode ( ) ; unsigned Op1Code = Op1 -> getOpcode ( ) ; if ( Op0Code == <STR_LIT> ) return expandOffset ( AM , IsBase , Op1 , cast < ConstantSDNode > ( Op0 ) ) ;"
LLVM,RISCV,2037,"Predict the next statement of this code snippet:
 <s> static bool expandOffset ( <ISA_LIT>AddressingMode & AM , bool IsBase , SDValue Op0 , ConstantSDNode * Op1 ) { int64_t TestOffset = AM . Offset + Op1 -> getSExtValue ( ) ; if ( selectOffset ( AM . OffR , TestOffset ) ) { AM . Base = Op0 ;"
LLVM,RISCV,2038,"Predict the next statement of this code snippet:
 <s> Base = AM . Base ; if ( ! Base . getNode ( ) ) Base = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( Base . getOpcode ( ) == <STR_LIT> ) { int64_t FrameIndex = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Offset = CurDAG -> getTargetFrameIndex ( FrameIndex , VT ) ; Base = CurDAG -> getTargetConstant ( AM . Offset , SDLoc ( Base ) , VT ) ; return ; } else if ( Base . getValueType ( ) != VT ) { assert ( VT == <STR_LIT> && Base . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Base ) ; SDValue Trunc = CurDAG -> getNode ( <STR_LIT> , DL , VT , Base ) ; insertDAGNode ( CurDAG , Base . getNode ( ) , Trunc ) ; Base = Trunc ; }"
LLVM,RISCV,2039,"Predict the next statement of this code snippet:
 <s> inline SDValue getImm ( const SDNode * Node , uint64_t Imm ) { return CurDAG -> getTargetConstant ( Imm , SDLoc ( Node ) , Node -> getValueType ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2040,"Predict the next statement of this code snippet:
 <s> return CurDAG -> getTargetConstant ( Imm , SDLoc ( Node ) , Node -> getValueType ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2041,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,RISCV,2042,"Predict the next statement of this code snippet:
 <s> DAG -> RepositionNode ( Pos -> getIterator ( ) , N . getNode ( ) ) ; N . getNode ( ) -> setNodeId ( Pos -> getNodeId ( ) ) ; }"
LLVM,RISCV,2043,"Predict the next statement of this code snippet:
 <s> static bool isValidOffset ( <STR_LIT> OffR , int64_t Val ) {"
LLVM,RISCV,2044,"Predict the next statement of this code snippet:
 <s> for ( auto & MBB : MF ) for ( auto & I : MBB ) {"
LLVM,RISCV,2045,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AddressingMode ( AddrForm form , OffRange offr ) : Form ( form ) , OffR ( offr ) , Base ( ) , Offset ( <NUM_LIT> ) {"
LLVM,RISCV,2046,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AddressingMode ( AddrForm form , OffRange offr ) : Form ( form ) , OffR ( offr ) , Base ( ) , Offset ( <NUM_LIT> ) {"
LLVM,RISCV,2047,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Lowering ( * TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {"
LLVM,RISCV,2048,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Lowering ( * TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {"
LLVM,RISCV,2049,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { bool ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ;"
LLVM,RISCV,2050,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) {"
LLVM,RISCV,2051,"Predict the next statement of this code snippet:
 <s> switch ( Opcode ) { case <STR_LIT> : { SDValue imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; unsigned Opc = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; EVT VT = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , imm ) ; return CurDAG -> getMachineNode ( Opc , DL , VT , TFI , imm ) ; } } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ; if ( ResNode == NULL || ResNode == Node ) Node -> dump ( CurDAG ) ; else ResNode -> dump ( CurDAG ) ;"
LLVM,RISCV,2052,"Predict the next statement of this code snippet:
 <s> selectMemRegAddr ( Op , Base , Offset ) ; OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ;"
LLVM,RISCV,2053,"Predict the next statement of this code snippet:
 <s> } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( Addr ) , ValTy ) ; return true ; } }"
LLVM,RISCV,2054,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> :"
LLVM,RISCV,2055,"Predict the next statement of this code snippet:
 <s> if ( Addr . getOpcode ( ) == <STR_LIT> ) { Target = Addr . getOperand ( <NUM_LIT> ) ; return true ; } return false ;"
LLVM,RISCV,2056,"Predict the next statement of this code snippet:
 <s> bool selectRegAddr ( SDValue Addr , SDValue & Base ) { Base = Addr ; return true ;"
LLVM,RISCV,2057,"Predict the next statement of this code snippet:
 <s> bool selectRegAddr ( SDValue Addr , SDValue & Base ) {"
LLVM,RISCV,2058,"Predict the next statement of this code snippet:
 <s> SDValue Upper = CurDAG -> getConstant ( UpperVal , DL , VT ) ; if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ;"
LLVM,RISCV,2059,"Predict the next statement of this code snippet:
 <s> } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && VT == XLenVT ) { auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } if ( Opcode == <STR_LIT> ) { SDLoc DL ( Node ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ;"
LLVM,RISCV,2060,"Predict the next statement of this code snippet:
 <s> ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } if ( Opcode == <STR_LIT> ) { SDLoc DL ( Node ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; }"
LLVM,RISCV,2061,"Predict the next statement of this code snippet:
 <s> case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; default :"
LLVM,RISCV,2062,"Predict the next statement of this code snippet:
 <s> return selectRVVSimm5 ( N , Width , Imm ) ;"
LLVM,RISCV,2063,"Predict the next statement of this code snippet:
 <s> bool selectShiftMask32 ( SDValue N , SDValue & ShAmt ) {"
LLVM,RISCV,2064,"Predict the next statement of this code snippet:
 <s> return selectShiftMask ( N , Subtarget -> getXLen ( ) , ShAmt ) ;"
LLVM,RISCV,2065,"Predict the next statement of this code snippet:
 <s> return selectShiftMask ( N , Subtarget -> getXLen ( ) , ShAmt ) ;"
LLVM,RISCV,2066,"Predict the next statement of this code snippet:
 <s> if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; int OffsetOpIdx ; int BaseOpIdx ; switch ( N -> getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) || N -> getConstantOperandVal ( OffsetOpIdx ) != <NUM_LIT> ) continue ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; if ( auto Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstant ( Const -> getSExtValue ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , GA -> getOffset ( ) , GA -> getTargetFlags ( ) ) ; } else { continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Base -> dump ( CurDAG ) ) ;"
LLVM,RISCV,2067,"Predict the next statement of this code snippet:
 <s> switch ( ConstraintID ) { case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; case InlineAsm :: Constraint_A : OutOps . push_back ( Op ) ; return false ; default : break ; }"
LLVM,RISCV,2068,"Predict the next statement of this code snippet:
 <s> return false ; case InlineAsm :: Constraint_A : OutOps . push_back ( Op ) ; return false ; default :"
LLVM,RISCV,2069,"Predict the next statement of this code snippet:
 <s> if ( ! I ) return false ; unsigned MaskOpIdx = I -> MaskOpIdx ; if ( ! isa < RegisterSDNode > ( N -> getOperand ( MaskOpIdx ) ) || cast < RegisterSDNode > ( N -> getOperand ( MaskOpIdx ) ) -> getReg ( ) != <STR_LIT> ) return false ; const auto * Glued = N -> getGluedNode ( ) ; if ( ! Glued || Glued -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! isa < RegisterSDNode > ( Glued -> getOperand ( <NUM_LIT> ) ) || cast < RegisterSDNode > ( Glued -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; SDValue MaskSetter = Glued -> getOperand ( <NUM_LIT> ) ; const auto IsVMSet = [ ] ( unsigned Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; } ; if ( ! MaskSetter -> isMachineOpcode ( ) || ! IsVMSet ( MaskSetter . getMachineOpcode ( ) ) ) return false ; Optional < unsigned > TailPolicyOpIdx ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( CurDAG -> getSubtarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MaskedMCID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( <STR_LIT> ( MaskedMCID . TSFlags ) ) { TailPolicyOpIdx = N -> getNumOperands ( ) - <NUM_LIT> ; if ( N -> getOperand ( * TailPolicyOpIdx ) . getValueType ( ) == <STR_LIT> ) ( * TailPolicyOpIdx ) -- ; if ( N -> getOperand ( * TailPolicyOpIdx ) . getValueType ( ) == <STR_LIT> ) ( * TailPolicyOpIdx ) -- ; if ( N -> getConstantOperandVal ( * TailPolicyOpIdx ) != <STR_LIT> ) return false ; } const MCInstrDesc & UnmaskedMCID = TII -> get ( I -> UnmaskedPseudo ) ; assert ( ! <STR_LIT> ( UnmaskedMCID . TSFlags ) && <STR_LIT> ( UnmaskedMCID . TSFlags ) && ! <STR_LIT> ( UnmaskedMCID . TSFlags ) && <STR_LIT> ) ; ( void ) UnmaskedMCID ; SmallVector < SDValue , <NUM_LIT> > Ops ;"
LLVM,RISCV,2070,"Predict the next statement of this code snippet:
 <s> return hasAllNBitUsers ( Node , <NUM_LIT> ) ;"
LLVM,RISCV,2071,"Predict the next statement of this code snippet:
 <s> bool hasAllWUsers ( SDNode * Node ) const {"
LLVM,RISCV,2072,"Predict the next statement of this code snippet:
 <s> return hasAllNBitUsers ( Node , <NUM_LIT> ) ;"
LLVM,RISCV,2073,"Predict the next statement of this code snippet:
 <s> HandleSDNode Dummy ( CurDAG -> getRoot ( ) ) ; SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_end ( ) ; bool MadeChange = false ; while ( Position != CurDAG -> allnodes_begin ( ) ) {"
LLVM,RISCV,2074,"Predict the next statement of this code snippet:
 <s> SDValue StackSlot = CurDAG -> getFrameIndex ( FI , TLI . getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; SDValue Chain = CurDAG -> getEntryNode ( ) ; Lo = CurDAG -> getStore ( Chain , DL , Lo , StackSlot , MPI , Align ( <NUM_LIT> ) ) ; SDValue OffsetSlot = CurDAG -> getMemBasePlusOffset ( StackSlot , TypeSize :: Fixed ( <NUM_LIT> ) , DL ) ; Hi = CurDAG -> getStore ( Chain , DL , Hi , OffsetSlot , MPI . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; Chain = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDVTList VTs = CurDAG -> getVTList ( { VT , <STR_LIT> } ) ; SDValue IntID = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , IntID , Passthru , StackSlot , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) , VL } ; SDValue Result = CurDAG -> getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , <STR_LIT> , MPI , Align ( <NUM_LIT> ) , MachineMemOperand :: MOLoad ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Result ) ;"
LLVM,RISCV,2075,"Predict the next statement of this code snippet:
 <s> if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SrcReg , CurDAG -> getRegister ( <STR_LIT> , XLenVT ) ) ; else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SrcReg ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; SrcReg = SDValue ( Result , <NUM_LIT> ) ; } return Result ;"
LLVM,RISCV,2076,"Predict the next statement of this code snippet:
 <s> SDNode * Load = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Addr , Offset , CurDAG -> getEntryNode ( ) ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; MachineMemOperand * MemOp = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , LLT ( VT ) , CP -> getAlign ( ) ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Load ) , { MemOp } ) ; return Load ;"
LLVM,RISCV,2077,"Predict the next statement of this code snippet:
 <s> if ( N . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { const APInt & AndMask = N -> getConstantOperandAPInt ( <NUM_LIT> ) ; assert ( isPowerOf2_32 ( ShiftWidth ) && <STR_LIT> ) ; APInt ShMask ( AndMask . getBitWidth ( ) , ShiftWidth - <NUM_LIT> ) ; if ( ShMask . isSubsetOf ( AndMask ) ) { ShAmt = N . getOperand ( <NUM_LIT> ) ; return true ; } KnownBits Known = CurDAG -> computeKnownBits ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ShMask . isSubsetOf ( AndMask | Known . Zero ) ) { ShAmt = N . getOperand ( <NUM_LIT> ) ; return true ;"
LLVM,RISCV,2078,"Predict the next statement of this code snippet:
 <s> VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } else if ( C && C -> isAllOnesValue ( ) ) { VL = CurDAG -> getTargetConstant ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } else if ( isa < RegisterSDNode > ( N ) && cast < RegisterSDNode > ( N ) -> getReg ( ) == <STR_LIT> ) { VL = CurDAG -> getTargetConstant ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } else { VL = N ; }"
LLVM,RISCV,2079,"Predict the next statement of this code snippet:
 <s> if ( C && isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2080,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Node ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , true , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; if ( IndexLog2EEW == <NUM_LIT> && ! Subtarget -> is64Bit ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ;"
LLVM,RISCV,2081,"Predict the next statement of this code snippet:
 <s> assert ( ( IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> ) && <STR_LIT> ) ; bool VLMax = IntNo == <STR_LIT> || IntNo == <STR_LIT> ; unsigned Offset = IntNoOffset + ( VLMax ? <NUM_LIT> : <NUM_LIT> ) ; assert ( Node -> getNumOperands ( ) == Offset + <NUM_LIT> && <STR_LIT> ) ; unsigned SEW = <ISA_LIT>VType :: decodeVSEW ( Node -> getConstantOperandVal ( Offset ) & <NUM_LIT> ) ; <STR_LIT> VLMul = static_cast < <STR_LIT> > ( Node -> getConstantOperandVal ( Offset + <NUM_LIT> ) & <NUM_LIT> ) ; unsigned VTypeI = <ISA_LIT>VType :: encodeVTYPE ( VLMul , SEW , true , false ) ; SDValue VTypeIOp = CurDAG -> getTargetConstant ( VTypeI , DL , XLenVT ) ; SmallVector < EVT , <NUM_LIT> > VTs = { XLenVT } ; if ( HasChain ) VTs . push_back ( <STR_LIT> ) ; SDValue VLOperand ; unsigned Opcode = <STR_LIT> ; if ( VLMax ) {"
LLVM,RISCV,2082,"Predict the next statement of this code snippet:
 <s> if ( N . getOpcode ( ) != <STR_LIT> || ! N . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return false ;"
LLVM,RISCV,2083,"Predict the next statement of this code snippet:
 <s> assert ( XLenVT == N . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) && <STR_LIT> ) ; MVT EltVT = N . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( EltVT . bitsLT ( XLenVT ) ) SplatImm = SignExtend64 ( SplatImm , EltVT . getSizeInBits ( ) ) ; if ( ! ValidateImm ( SplatImm ) ) return false ; SplatVal = DAG . getTargetConstant ( SplatImm , SDLoc ( N ) , XLenVT ) ; return true ;"
LLVM,RISCV,2084,"Predict the next statement of this code snippet:
 <s> int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > ( SplatImm ) ) return false ; SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc ( N ) , Subtarget -> getXLenVT ( ) ) ;"
LLVM,RISCV,2085,"Predict the next statement of this code snippet:
 <s> int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > ( SplatImm ) ) return false ; SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc ( N ) , Subtarget -> getXLenVT ( ) ) ;"
LLVM,RISCV,2086,"Predict the next statement of this code snippet:
 <s> report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Store , { MemOp -> getMemOperand ( ) } ) ; ReplaceNode ( Node , Store ) ;"
LLVM,RISCV,2087,"Predict the next statement of this code snippet:
 <s> Operands . push_back ( Base ) ; if ( IsStridedOrIndexed ) { Operands . push_back ( Node -> getOperand ( CurOp ++ ) ) ; if ( IndexVT ) * IndexVT = Operands . back ( ) -> getSimpleValueType ( <NUM_LIT> ) ; } if ( IsMasked ) { SDValue Mask = Node -> getOperand ( CurOp ++ ) ; Chain = CurDAG -> getCopyToReg ( Chain , DL , <STR_LIT> , Mask , SDValue ( ) ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; Operands . push_back ( CurDAG -> getRegister ( <STR_LIT> , Mask . getValueType ( ) ) ) ;"
LLVM,RISCV,2088,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; } }"
LLVM,RISCV,2089,"Predict the next statement of this code snippet:
 <s> SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ; if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SrcReg , CurDAG -> getRegister ( <STR_LIT> , XLenVT ) ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; SrcReg = SDValue ( Result , <NUM_LIT> ) ;"
LLVM,RISCV,2090,"Predict the next statement of this code snippet:
 <s> MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { unsigned SubRegIdx = <ISA_LIT>TargetLowering :: getSubregIndexByMVT ( VT , I ) ; ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx , DL , VT , SuperReg ) ) ; } ReplaceUses ( SDValue ( Node , NF ) , SDValue ( Load , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( Node ) ;"
LLVM,RISCV,2091,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Node ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , false , Operands ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , false , true , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDValue ( Load , <NUM_LIT> ) ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ;"
LLVM,RISCV,2092,"Predict the next statement of this code snippet:
 <s> if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , false , Operands ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , false , true , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDValue ( Load , <NUM_LIT> ) ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ;"
LLVM,RISCV,2093,"Predict the next statement of this code snippet:
 <s> SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ;"
LLVM,RISCV,2094,"Predict the next statement of this code snippet:
 <s> MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { unsigned SubRegIdx = <ISA_LIT>TargetLowering :: getSubregIndexByMVT ( VT , I ) ; ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx , DL , VT , SuperReg ) ) ;"
LLVM,RISCV,2095,"Predict the next statement of this code snippet:
 <s> unsigned NF = Node -> getNumOperands ( ) - <NUM_LIT> ; if ( IsMasked ) -- NF ; MVT VT = Node -> getOperand ( <NUM_LIT> ) -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; unsigned CurOp = <NUM_LIT> + NF ; MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Store , { MemOp -> getMemOperand ( ) } ) ;"
LLVM,RISCV,2096,"Predict the next statement of this code snippet:
 <s> MVT VT = Node -> getOperand ( <NUM_LIT> ) -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; unsigned CurOp = <NUM_LIT> + NF ; MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ;"
LLVM,RISCV,2097,"Predict the next statement of this code snippet:
 <s> SDValue Add ; unsigned AddBaseIdx ; if ( Base . getMachineOpcode ( ) == <STR_LIT> && Base . hasOneUse ( ) ) { Add = Base ; SDValue Op0 = Base . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Base . getOperand ( <NUM_LIT> ) ; if ( Op0 . isMachineOpcode ( ) && Op0 . getMachineOpcode ( ) == <STR_LIT> && ! isa < FrameIndexSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) { AddBaseIdx = <NUM_LIT> ; Base = Op0 ; } else if ( Op1 . isMachineOpcode ( ) && Op1 . getMachineOpcode ( ) == <STR_LIT> && ! isa < FrameIndexSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { AddBaseIdx = <NUM_LIT> ; Base = Op1 ; } else if ( Op1 . isMachineOpcode ( ) && Op1 . getMachineOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) && Op1 . getOperand ( <NUM_LIT> ) . isMachineOpcode ( ) && Op1 . getOperand ( <NUM_LIT> ) . getMachineOpcode ( ) == <STR_LIT> ) { uint64_t Imm = Op1 . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; Imm <<= <NUM_LIT> ; Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; uint64_t LoImm = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; Imm += LoImm ; if ( ! isInt < <NUM_LIT> > ( Imm ) ) return false ; AddBaseIdx = <NUM_LIT> ; Base = Op1 ; } else return false ;"
LLVM,RISCV,2098,"Predict the next statement of this code snippet:
 <s> unsigned MaskOpIdx = I -> MaskOpIdx ; if ( ! isa < RegisterSDNode > ( N -> getOperand ( MaskOpIdx ) ) || cast < RegisterSDNode > ( N -> getOperand ( MaskOpIdx ) ) -> getReg ( ) != <STR_LIT> ) return false ; const auto * Glued = N -> getGluedNode ( ) ; if ( ! Glued || Glued -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! isa < RegisterSDNode > ( Glued -> getOperand ( <NUM_LIT> ) ) || cast < RegisterSDNode > ( Glued -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; SDValue MaskSetter = Glued -> getOperand ( <NUM_LIT> ) ; const auto IsVMSet = [ ] ( unsigned Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; } ; if ( ! MaskSetter -> isMachineOpcode ( ) || ! IsVMSet ( MaskSetter . getMachineOpcode ( ) ) ) return false ; Optional < unsigned > TailPolicyOpIdx ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( CurDAG -> getSubtarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MaskedMCID = TII -> get ( N -> getMachineOpcode ( ) ) ; bool IsTA = true ; if ( <STR_LIT> ( MaskedMCID . TSFlags ) ) { TailPolicyOpIdx = N -> getNumOperands ( ) - <NUM_LIT> ; if ( N -> getOperand ( * TailPolicyOpIdx ) . getValueType ( ) == <STR_LIT> ) ( * TailPolicyOpIdx ) -- ; if ( N -> getOperand ( * TailPolicyOpIdx ) . getValueType ( ) == <STR_LIT> ) ( * TailPolicyOpIdx ) -- ; if ( ! ( N -> getConstantOperandVal ( * TailPolicyOpIdx ) & <STR_LIT> ) ) { if ( I -> UnmaskedTUPseudo == I -> MaskedPseudo && ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return false ; if ( ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) IsTA = false ; } } if ( IsTA ) { uint64_t TSFlags = TII -> get ( I -> UnmaskedPseudo ) . TSFlags ;"
LLVM,RISCV,2099,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getMachineOpcode ( ) == <STR_LIT> && ! isUInt < <NUM_LIT> > ( cast < ConstantSDNode > ( N01 ) -> getSExtValue ( ) ) ) break ; SDNode * Result = CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N00 , N01 ) ; ReplaceUses ( N , Result ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ReplaceUses ( N , N0 . getNode ( ) ) ; return true ;"
LLVM,RISCV,2100,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ; break ; case <STR_LIT> : if ( Bits < ( <NUM_LIT> - countLeadingZeros ( User -> getConstantOperandVal ( <NUM_LIT> ) ) ) ) return false ; break ; case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; } } return true ;"
LLVM,RISCV,2101,"Predict the next statement of this code snippet:
 <s> static bool isAllUndef ( ArrayRef < SDValue > Values ) { return llvm :: all_of ( Values , [ ] ( SDValue V ) { return V -> isUndef ( ) ; } ) ;"
LLVM,RISCV,2102,"Predict the next statement of this code snippet:
 <s> SDNode * Result = nullptr ; SDValue SrcReg = CurDAG -> getRegister ( <STR_LIT> , XLenVT ) ; for ( <STR_LIT> & Inst : Seq ) { SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ; switch ( Inst . getOpndKind ( ) ) { case <STR_LIT> : Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SDImm ) ; break ; case <STR_LIT> : Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , CurDAG -> getRegister ( <STR_LIT> , XLenVT ) ) ; break ; case <STR_LIT> : Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SrcReg ) ; break ; case <STR_LIT> : Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; break ; }"
LLVM,RISCV,2103,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; bool IsTU = IsMasked || ! isAllUndef ( Regs ) ; if ( IsTU ) { SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; } CurOp += NF ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , false , Operands , true ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsTU , false , true , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; bool TailAgnostic = true ; bool MaskAgnostic = false ; if ( IsMasked ) { uint64_t Policy = Node -> getConstantOperandVal ( Node -> getNumOperands ( ) - <NUM_LIT> ) ; TailAgnostic = Policy & <STR_LIT> ; MaskAgnostic = Policy & <STR_LIT> ; } unsigned VType = <ISA_LIT>VType :: encodeVTYPE ( LMUL , SEW , TailAgnostic , MaskAgnostic ) ; SDValue VTypeOp = CurDAG -> getTargetConstant ( VType , DL , XLenVT ) ;"
LLVM,RISCV,2104,"Predict the next statement of this code snippet:
 <s> bool MaskAgnostic = false ; if ( IsMasked ) { uint64_t Policy = Node -> getConstantOperandVal ( Node -> getNumOperands ( ) - <NUM_LIT> ) ; TailAgnostic = Policy & <STR_LIT> ; MaskAgnostic = Policy & <STR_LIT> ; } unsigned VType = <ISA_LIT>VType :: encodeVTYPE ( LMUL , SEW , TailAgnostic , MaskAgnostic ) ; SDValue VTypeOp = CurDAG -> getTargetConstant ( VType , DL , XLenVT ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , VTypeOp , SDValue ( Load , <NUM_LIT> ) ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { unsigned SubRegIdx = <ISA_LIT>TargetLowering :: getSubregIndexByMVT ( VT , I ) ; ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx , DL , VT , SuperReg ) ) ; } ReplaceUses ( SDValue ( Node , NF ) , SDValue ( ReadVL , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , NF + <NUM_LIT> ) , SDValue ( Load , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( Node ) ;"
LLVM,RISCV,2105,"Predict the next statement of this code snippet:
 <s> Operands . push_back ( Node -> getOperand ( CurOp ++ ) ) ; if ( IndexVT ) * IndexVT = Operands . back ( ) -> getSimpleValueType ( <NUM_LIT> ) ; } if ( IsMasked ) { SDValue Mask = Node -> getOperand ( CurOp ++ ) ; Chain = CurDAG -> getCopyToReg ( Chain , DL , <STR_LIT> , Mask , SDValue ( ) ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; Operands . push_back ( CurDAG -> getRegister ( <STR_LIT> , Mask . getValueType ( ) ) ) ; } SDValue VL ; selectVLOp ( Node -> getOperand ( CurOp ++ ) , VL ) ; Operands . push_back ( VL ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; SDValue SEWOp = CurDAG -> getTargetConstant ( Log2_32 ( SEW ) , DL , XLenVT ) ; Operands . push_back ( SEWOp ) ; Operands . push_back ( Chain ) ;"
LLVM,RISCV,2106,"Predict the next statement of this code snippet:
 <s> SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset2 = N -> getConstantOperandVal ( OffsetOpIdx ) ; if ( auto * Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { int64_t Offset1 = Const -> getSExtValue ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; if ( ! isInt < <NUM_LIT> > ( CombinedOffset ) ) continue ; ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto * GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { const DataLayout & DL = CurDAG -> getDataLayout ( ) ; Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = GA -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , CombinedOffset , GA -> getTargetFlags ( ) ) ; } else if ( auto * CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { Align Alignment = CP -> getAlign ( ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = CP -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ;"
LLVM,RISCV,2107,"Predict the next statement of this code snippet:
 <s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ;"
LLVM,RISCV,2108,"Predict the next statement of this code snippet:
 <s> if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ;"
LLVM,RISCV,2109,"Predict the next statement of this code snippet:
 <s> SDNode * Result = nullptr ; SDValue SrcReg = CurDAG -> getRegister ( <STR_LIT> , XLenVT ) ; for ( <STR_LIT> & Inst : Seq ) { SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ;"
LLVM,RISCV,2110,"Predict the next statement of this code snippet:
 <s> if ( N . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> ) { Val = N . getOperand ( <NUM_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . bitsLE ( <STR_LIT> ) ) { Val = N ;"
LLVM,RISCV,2111,"Predict the next statement of this code snippet:
 <s> return true ; } if ( N . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . bitsLE ( <STR_LIT> ) ) { Val = N ; return true ; }"
LLVM,RISCV,2112,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget -> getXLenVT ( ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } addVectorLoadStoreOperands ( Node , ScalarSize , DL , CurOp , IsMasked , false , Operands ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , false , true , ScalarSize , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDValue ( Load , <NUM_LIT> ) ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { unsigned SubRegIdx = <ISA_LIT>TargetLowering :: getSubregIndexByMVT ( VT , I ) ; ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx , DL , VT , SuperReg ) ) ;"
LLVM,RISCV,2113,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: selectVLSEGFF ( SDNode * Node , bool IsMasked ) { SDLoc DL ( Node ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ;"
LLVM,RISCV,2114,"Predict the next statement of this code snippet:
 <s> <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } MVT IndexVT ; addVectorLoadStoreOperands ( Node , ScalarSize , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ;"
LLVM,RISCV,2115,"Predict the next statement of this code snippet:
 <s> if ( IsStrided ) NF -- ; if ( IsMasked ) NF -- ; MVT VT = Node -> getOperand ( <NUM_LIT> ) -> getSimpleValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ;"
LLVM,RISCV,2116,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; unsigned CurOp = <NUM_LIT> + NF ; addVectorLoadStoreOperands ( Node , ScalarSize , DL , CurOp , IsMasked , IsStrided , Operands ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsStrided , ScalarSize , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Store , { MemOp -> getMemOperand ( ) } ) ; ReplaceNode ( Node , Store ) ;"
LLVM,RISCV,2117,"Predict the next statement of this code snippet:
 <s> SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; unsigned CurOp = <NUM_LIT> + NF ; MVT IndexVT ; addVectorLoadStoreOperands ( Node , ScalarSize , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Store , { MemOp -> getMemOperand ( ) } ) ;"
LLVM,RISCV,2118,"Predict the next statement of this code snippet:
 <s> <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; unsigned CurOp = <NUM_LIT> + NF ; MVT IndexVT ;"
LLVM,RISCV,2119,"Predict the next statement of this code snippet:
 <s> if ( N . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . bitsLE ( <STR_LIT> ) ) { Val = N ; return true ;"
LLVM,RISCV,2120,"Predict the next statement of this code snippet:
 <s> auto * C = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getZExtValue ( ) == UINT64_C ( <NUM_LIT> ) ) { Val = N . getOperand ( <NUM_LIT> ) ; return true ; } } if ( N . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . bitsLE ( <STR_LIT> ) ) { Val = N ; return true ; } return false ;"
LLVM,RISCV,2121,"Predict the next statement of this code snippet:
 <s> BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) || N -> getConstantOperandVal ( OffsetOpIdx ) != <NUM_LIT> ) continue ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; if ( auto Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstant ( Const -> getSExtValue ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , GA -> getOffset ( ) , GA -> getTargetFlags ( ) ) ; } else if ( auto CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CP -> getOffset ( ) , CP -> getTargetFlags ( ) ) ; } else { continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Base -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;"
LLVM,RISCV,2122,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) || N -> getConstantOperandVal ( OffsetOpIdx ) != <NUM_LIT> ) continue ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; if ( auto Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstant ( Const -> getSExtValue ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , GA -> getOffset ( ) , GA -> getTargetFlags ( ) ) ; } else if ( auto CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CP -> getOffset ( ) , CP -> getTargetFlags ( ) ) ; } else { continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Base -> dump ( CurDAG ) ) ;"
LLVM,RISCV,2123,"Predict the next statement of this code snippet:
 <s> static bool isConstantMask ( SDNode * Node , uint64_t & Mask ) { if ( Node -> getOpcode ( ) == <STR_LIT> && Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Mask = cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; return true ; }"
LLVM,RISCV,2124,"Predict the next statement of this code snippet:
 <s> doPeepholeLoadStoreADDI ( ) ;"
LLVM,RISCV,2125,"Predict the next statement of this code snippet:
 <s> EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; uint64_t Mask ; if ( Op1 . getOpcode ( ) == <STR_LIT> && isConstantMask ( Op0 . getNode ( ) , Mask ) ) { uint64_t ShAmt = cast < ConstantSDNode > ( Op1 . getNode ( ) ) -> getZExtValue ( ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) { SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( Node ) , XLenVT ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , XLenVT , Op0 . getOperand ( <NUM_LIT> ) , ShAmtVal ) ; return ;"
LLVM,RISCV,2126,"Predict the next statement of this code snippet:
 <s> return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; uint64_t Mask ; if ( Op1 . getOpcode ( ) == <STR_LIT> && isConstantMask ( Op0 . getNode ( ) , Mask ) ) { uint64_t ShAmt = cast < ConstantSDNode > ( Op1 . getNode ( ) ) -> getZExtValue ( ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) { SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( Node ) , XLenVT ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , XLenVT , Op0 . getOperand ( <NUM_LIT> ) , ShAmtVal ) ; return ; } } break ; } case <STR_LIT> : assert ( ! Subtarget -> is64Bit ( ) && <STR_LIT> ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) ) ) ; return ; } SelectCode ( Node ) ;"
LLVM,RISCV,2127,"Predict the next statement of this code snippet:
 <s> static SDNode * selectImm ( SelectionDAG * CurDAG , const SDLoc & DL , int64_t Imm , MVT XLenVT ) { <STR_LIT> Seq ; <STR_LIT> ( Imm , XLenVT == <STR_LIT> , Seq ) ; SDNode * Result = nullptr ; SDValue SrcReg = CurDAG -> getRegister ( <STR_LIT> , XLenVT ) ; for ( <STR_LIT> & Inst : Seq ) { SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ; if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; SrcReg = SDValue ( Result , <NUM_LIT> ) ;"
LLVM,RISCV,2128,"Predict the next statement of this code snippet:
 <s> SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ; if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; SrcReg = SDValue ( Result , <NUM_LIT> ) ;"
LLVM,RISCV,2129,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , DL , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDNode * Op0 = Node -> getOperand ( <NUM_LIT> ) . getNode ( ) ; uint64_t Mask ; if ( isa < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) && isConstantMask ( Op0 , Mask ) ) {"
LLVM,RISCV,2130,"Predict the next statement of this code snippet:
 <s> uint64_t VC2 = Shl . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC2 < <NUM_LIT> && VC1 == ( ( uint64_t ) <NUM_LIT> << VC2 ) ) { RS1 = Shl . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2131,"Predict the next statement of this code snippet:
 <s> if ( N . getOpcode ( ) != <STR_LIT> || cast < VTSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getVT ( ) != <STR_LIT> ) return false ; SDValue Or = N . getOperand ( <NUM_LIT> ) ; if ( Or . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Or . getOperand ( <NUM_LIT> ) ) ) return false ; SDValue Shl = Or . getOperand ( <NUM_LIT> ) ; if ( Shl . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) ) return false ; uint64_t VC1 = Or . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t VC2 = Shl . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC2 >= <NUM_LIT> || VC1 != maskTrailingOnes < uint64_t > ( VC2 ) ) return false ; RS1 = Shl . getOperand ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( VC2 , SDLoc ( N ) , Shl . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; return true ;"
LLVM,RISCV,2132,"Predict the next statement of this code snippet:
 <s> return true ; } } if ( XLenVT == <STR_LIT> ) { uint32_t VC1 = Or . getConstantOperandVal ( <NUM_LIT> ) ; uint32_t VC2 = Srl . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC1 == maskLeadingOnes < uint32_t > ( VC2 ) ) { RS1 = Srl . getOperand ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( VC2 , SDLoc ( N ) , Srl . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; return true ; } } } }"
LLVM,RISCV,2133,"Predict the next statement of this code snippet:
 <s> assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; if ( N . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) return false ; SDValue Srl = N . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) return false ; uint64_t VC1 = N . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t VC2 = Srl . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC2 >= <NUM_LIT> || VC1 != maskTrailingZeros < uint64_t > ( <NUM_LIT> - VC2 ) ) return false ;"
LLVM,RISCV,2134,"Predict the next statement of this code snippet:
 <s> return ; } unsigned Opcode = Node -> getOpcode ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : {"
LLVM,RISCV,2135,"Predict the next statement of this code snippet:
 <s> SDNode * Result ; SDValue SrcReg = CurDAG -> getRegister ( <STR_LIT> , XLenVT ) ; for ( <STR_LIT> & Inst : Seq ) { SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ; if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; SrcReg = SDValue ( Result , <NUM_LIT> ) ;"
LLVM,RISCV,2136,"Predict the next statement of this code snippet:
 <s> if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; SrcReg = SDValue ( Result , <NUM_LIT> ) ; } return Result ;"
LLVM,RISCV,2137,"Predict the next statement of this code snippet:
 <s> const SDValue ImmOp0 = CurDAG -> getTargetConstant ( Imm - Imm / <NUM_LIT> , DL , VT ) ; const SDValue ImmOp1 = CurDAG -> getTargetConstant ( Imm / <NUM_LIT> , DL , VT ) ; auto * NodeAddi0 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Node -> getOperand ( <NUM_LIT> ) , ImmOp0 ) ; auto * NodeAddi1 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( NodeAddi0 , <NUM_LIT> ) , ImmOp1 ) ; ReplaceNode ( Node , NodeAddi1 ) ; return ; } break ; } case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; uint64_t Mask ; if ( Op1 . getOpcode ( ) == <STR_LIT> && isConstantMask ( Op0 . getNode ( ) , Mask ) ) { uint64_t ShAmt = cast < ConstantSDNode > ( Op1 . getNode ( ) ) -> getZExtValue ( ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) { SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( Node ) , XLenVT ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , XLenVT , Op0 . getOperand ( <NUM_LIT> ) , ShAmtVal ) ; return ; } } break ; } case <STR_LIT> : {"
LLVM,RISCV,2138,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectRORI ( SDValue N , SDValue & RS1 , SDValue & Shamt ) { MVT XLenVT = Subtarget -> getXLenVT ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( XLenVT == <STR_LIT> ) { uint64_t VC = N . getConstantOperandVal ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( ( <NUM_LIT> - VC ) , SDLoc ( N ) , N . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; RS1 = N . getOperand ( <NUM_LIT> ) ; return true ; } if ( XLenVT == <STR_LIT> ) { uint32_t VC = N . getConstantOperandVal ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( ( <NUM_LIT> - VC ) , SDLoc ( N ) , N . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; RS1 = N . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2139,"Predict the next statement of this code snippet:
 <s> if ( N . getOpcode ( ) == <STR_LIT> && Subtarget -> getXLenVT ( ) == <STR_LIT> && cast < VTSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> ) { if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Or = N . getOperand ( <NUM_LIT> ) ; if ( Or . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Or . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Shl = Or . getOperand ( <NUM_LIT> ) ; SDValue Srl = Or . getOperand ( <NUM_LIT> ) ; if ( Srl . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue And = Srl . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( And . getOperand ( <NUM_LIT> ) ) ) { uint32_t VC1 = Srl . getConstantOperandVal ( <NUM_LIT> ) ; uint32_t VC2 = Shl . getConstantOperandVal ( <NUM_LIT> ) ; uint32_t VC3 = And . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC2 == ( <NUM_LIT> - VC1 ) && VC3 == maskLeadingOnes < uint32_t > ( VC2 ) ) { RS1 = Shl . getOperand ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( VC1 , SDLoc ( N ) , Srl . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; return true ; } } } } } } return false ;"
LLVM,RISCV,2140,"Predict the next statement of this code snippet:
 <s> SDValue Or = N . getOperand ( <NUM_LIT> ) ; if ( Or . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Or . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Shl = Or . getOperand ( <NUM_LIT> ) ; SDValue Srl = Or . getOperand ( <NUM_LIT> ) ; if ( Srl . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue And = Srl . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( And . getOperand ( <NUM_LIT> ) ) ) { uint32_t VC1 = Srl . getConstantOperandVal ( <NUM_LIT> ) ; uint32_t VC2 = Shl . getConstantOperandVal ( <NUM_LIT> ) ; uint32_t VC3 = And . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC2 == ( <NUM_LIT> - VC1 ) && VC3 == maskLeadingOnes < uint32_t > ( VC2 ) ) { RS1 = Shl . getOperand ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( VC1 , SDLoc ( N ) , Srl . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; return true ; } } }"
LLVM,RISCV,2141,"Predict the next statement of this code snippet:
 <s> SDValue Or = N ; if ( Or . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Srl = Or . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Or . getOperand ( <NUM_LIT> ) ) ) {"
LLVM,RISCV,2142,"Predict the next statement of this code snippet:
 <s> if ( isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Or . getOperand ( <NUM_LIT> ) ) ) { uint32_t VC1 = Or . getConstantOperandVal ( <NUM_LIT> ) ; uint32_t VC2 = Srl . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC1 == maskLeadingOnes < uint32_t > ( VC2 ) ) { RS1 = Srl . getOperand ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( VC2 , SDLoc ( N ) , Srl . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; return true ; } } } } return false ;"
LLVM,RISCV,2143,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; OffsettingOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; OffsettingOpcode = <STR_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) ) continue ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != OffsettingOpcode ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset2 = N -> getConstantOperandVal ( OffsetOpIdx ) ; if ( auto * Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { int64_t Offset1 = Const -> getSExtValue ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; if ( ! isInt < <NUM_LIT> > ( CombinedOffset ) ) continue ; ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto * GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { const DataLayout & DL = CurDAG -> getDataLayout ( ) ; Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ;"
LLVM,RISCV,2144,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: PostprocessISelDAG ( ) { doPeepholeLoadStoreOffset ( ) ;"
LLVM,RISCV,2145,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: PostprocessISelDAG ( ) {"
LLVM,RISCV,2146,"Predict the next statement of this code snippet:
 <s> I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) != <STR_LIT> ) continue ; assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDValue Lo = N -> getOperand ( <NUM_LIT> ) ; SDValue Hi = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && VT . isScalableVector ( ) && Lo . getValueType ( ) == <STR_LIT> && Hi . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( N ) ; int FI = FuncInfo -> getMoveF64FrameIndex ( MF ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ;"
LLVM,RISCV,2147,"Predict the next statement of this code snippet:
 <s> I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) != <STR_LIT> ) continue ; assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDValue Lo = N -> getOperand ( <NUM_LIT> ) ; SDValue Hi = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && VT . isScalableVector ( ) && Lo . getValueType ( ) == <STR_LIT> && Hi . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( N ) ; int FI = FuncInfo -> getMoveF64FrameIndex ( MF ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ;"
LLVM,RISCV,2148,"Predict the next statement of this code snippet:
 <s> if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { if ( Addr . getValueType ( ) . isScalarInteger ( ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ; return true ; } }"
LLVM,RISCV,2149,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrFI ( SDValue Addr , SDValue & Base ) { if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { if ( Addr . getValueType ( ) . isScalarInteger ( ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ; return true ; }"
LLVM,RISCV,2150,"Predict the next statement of this code snippet:
 <s> if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ;"
LLVM,RISCV,2151,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectBaseAddr ( SDValue Addr , SDValue & Base ) { if ( Addr . getValueType ( ) . isFatPointer ( ) ) return false ; assert ( Addr . getValueType ( ) . isInteger ( ) || Addr . getValueType ( ) == <STR_LIT> ) ; if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ; else Base = Addr ;"
LLVM,RISCV,2152,"Predict the next statement of this code snippet:
 <s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> typeForCapabilities ( ) ) ; return true ; } }"
LLVM,RISCV,2153,"Predict the next statement of this code snippet:
 <s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> typeForCapabilities ( ) ) ; return true ;"
LLVM,RISCV,2154,"Predict the next statement of this code snippet:
 <s> for ( auto UI = Node -> use_begin ( ) , UE = Node -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( ! User -> isMachineOpcode ( ) ) return false ; switch ( User -> getMachineOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ;"
LLVM,RISCV,2155,"Predict the next statement of this code snippet:
 <s> bool SelectAddr ( SDValue N , SDValue & Base ) { Base = N ;"
LLVM,RISCV,2156,"Predict the next statement of this code snippet:
 <s> Base = N ; return true ;"
LLVM,RISCV,2157,"Predict the next statement of this code snippet:
 <s> Node -> setNodeId ( - <NUM_LIT> ) ; return ; } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && VT == XLenVT ) { auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } SelectCode ( Node ) ;"
LLVM,RISCV,2158,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return createM1Tuple ( CurDAG , Regs , NF ) ; case <STR_LIT> : return createM2Tuple ( CurDAG , Regs , NF ) ; case <STR_LIT> :"
LLVM,RISCV,2159,"Predict the next statement of this code snippet:
 <s> return createM1Tuple ( CurDAG , Regs , NF ) ; case <STR_LIT> : return createM2Tuple ( CurDAG , Regs , NF ) ; case <STR_LIT> : return createM4Tuple ( CurDAG , Regs , NF ) ;"
LLVM,RISCV,2160,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) ) continue ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset2 = N -> getConstantOperandVal ( OffsetOpIdx ) ; if ( auto Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { int64_t Offset1 = Const -> getSExtValue ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; if ( ! isInt < <NUM_LIT> > ( CombinedOffset ) ) continue ; ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { const DataLayout & DL = CurDAG -> getDataLayout ( ) ; Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = GA -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , CombinedOffset , GA -> getTargetFlags ( ) ) ; } else if ( auto CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { Align Alignment = CP -> getAlign ( ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = CP -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CombinedOffset , CP -> getTargetFlags ( ) ) ; } else { continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Base -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ;"
LLVM,RISCV,2161,"Predict the next statement of this code snippet:
 <s> Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = GA -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , CombinedOffset , GA -> getTargetFlags ( ) ) ; } else if ( auto CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { Align Alignment = CP -> getAlign ( ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = CP -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CombinedOffset , CP -> getTargetFlags ( ) ) ; } else { continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Base -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( BaseOpIdx == <NUM_LIT> ) CurDAG -> UpdateNodeOperands ( N , Base . getOperand ( <NUM_LIT> ) , ImmOperand , N -> getOperand ( <NUM_LIT> ) ) ; else CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , Base . getOperand ( <NUM_LIT> ) , ImmOperand , N -> getOperand ( <NUM_LIT> ) ) ; if ( Base . getNode ( ) -> use_empty ( ) ) CurDAG -> RemoveDeadNode ( Base . getNode ( ) ) ; }"
LLVM,RISCV,2162,"Predict the next statement of this code snippet:
 <s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;"
LLVM,RISCV,2163,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> + Index ; } else if ( LMUL == <STR_LIT> ) { static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; return <STR_LIT> + Index ; } else if ( LMUL == <STR_LIT> ) { static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; return <STR_LIT> + Index ; }"
LLVM,RISCV,2164,"Predict the next statement of this code snippet:
 <s> assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) ; SDValue Shl = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> is64Bit ( ) ) {"
LLVM,RISCV,2165,"Predict the next statement of this code snippet:
 <s> assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) ; SDValue Srl = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> is64Bit ( ) ) { uint64_t VC1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; uint64_t VC2 = Srl . getConstantOperandVal ( <NUM_LIT> ) ; return VC1 == maskLeadingOnes < uint64_t > ( VC2 ) ; } uint32_t VC1 = N -> getConstantOperandVal ( <NUM_LIT> ) ;"
LLVM,RISCV,2166,"Predict the next statement of this code snippet:
 <s> assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ;"
LLVM,RISCV,2167,"Predict the next statement of this code snippet:
 <s> Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( Node , NF ) , SDValue ( Load , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( Node ) ;"
LLVM,RISCV,2168,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ;"
LLVM,RISCV,2169,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: selectVLSEGFFMask ( SDNode * Node ) { SDLoc DL ( Node ) ; unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ;"
LLVM,RISCV,2170,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( MaskedOff ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( Node , NF ) , SDValue ( Load , <NUM_LIT> ) ) ;"
LLVM,RISCV,2171,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: selectVLSEGMask ( SDNode * Node , unsigned IntNo , bool IsStrided ) { SDLoc DL ( Node ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( MaskedOff ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; } else { Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; } Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ;"
LLVM,RISCV,2172,"Predict the next statement of this code snippet:
 <s> if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; } else { Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; } Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ;"
LLVM,RISCV,2173,"Predict the next statement of this code snippet:
 <s> unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ;"
LLVM,RISCV,2174,"Predict the next statement of this code snippet:
 <s> EVT IndexVT = Node -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( Node , NF ) , SDValue ( Load , <NUM_LIT> ) ) ;"
LLVM,RISCV,2175,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = { MaskedOff , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( NF + <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ;"
LLVM,RISCV,2176,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) { if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> ) return false ;"
LLVM,RISCV,2177,"Predict the next statement of this code snippet:
 <s> assert ( XLenVT == N . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) && <STR_LIT> ) ; auto EltVT = N . getValueType ( ) . getVectorElementType ( ) ; if ( EltVT . bitsLT ( XLenVT ) ) { SplatImm = SignExtend64 ( SplatImm , EltVT . getSizeInBits ( ) ) ; } if ( ! isInt < <NUM_LIT> > ( SplatImm ) ) return false ;"
LLVM,RISCV,2178,"Predict the next statement of this code snippet:
 <s> int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > ( SplatImm ) ) return false ;"
LLVM,RISCV,2179,"Predict the next statement of this code snippet:
 <s> int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > ( SplatImm ) ) return false ;"
LLVM,RISCV,2180,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; } else { Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; } Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ;"
LLVM,RISCV,2181,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; } else {"
LLVM,RISCV,2182,"Predict the next statement of this code snippet:
 <s> } else { Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; } Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; ReplaceNode ( Node , Store ) ;"
LLVM,RISCV,2183,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = { StoreVal , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( <NUM_LIT> + NF ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ;"
LLVM,RISCV,2184,"Predict the next statement of this code snippet:
 <s> unsigned NF = Node -> getNumOperands ( ) - <NUM_LIT> ; EVT VT = Node -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = { StoreVal , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( <NUM_LIT> + NF ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ;"
LLVM,RISCV,2185,"Predict the next statement of this code snippet:
 <s> SDValue Operands [ ] = { StoreVal , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( <NUM_LIT> + NF ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ;"
LLVM,RISCV,2186,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = { StoreVal , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( <NUM_LIT> + NF ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; ReplaceNode ( Node , Store ) ;"
LLVM,RISCV,2187,"Predict the next statement of this code snippet:
 <s> SDNode * User = * UI ; if ( ! User -> isMachineOpcode ( ) ) return false ; switch ( User -> getMachineOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ;"
LLVM,RISCV,2188,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: hasAllNBitUsers ( SDNode * Node , unsigned Bits ) const { assert ( ( Node -> getOpcode ( ) == <STR_LIT> || Node -> getOpcode ( ) == <STR_LIT> || Node -> getOpcode ( ) == <STR_LIT> || Node -> getOpcode ( ) == <STR_LIT> || Node -> getOpcode ( ) == <STR_LIT> || Node -> getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Node ) ) && <STR_LIT> ) ; for ( auto UI = Node -> use_begin ( ) , UE = Node -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( ! User -> isMachineOpcode ( ) ) return false ;"
LLVM,RISCV,2189,"Predict the next statement of this code snippet:
 <s> if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; if ( auto Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstant ( Const -> getSExtValue ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , GA -> getOffset ( ) , GA -> getTargetFlags ( ) ) ; } else { continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Base -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ;"
LLVM,RISCV,2190,"Predict the next statement of this code snippet:
 <s> } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && VT == XLenVT ) { auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } if ( Opcode == <STR_LIT> ) { SDLoc DL ( Node ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ;"
LLVM,RISCV,2191,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( F64Val -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue From [ ] = { SDValue ( N , <NUM_LIT> ) , SDValue ( N , <NUM_LIT> ) } ; SDValue To [ ] = { F64Val . getOperand ( <NUM_LIT> ) , F64Val . getOperand ( <NUM_LIT> ) } ; CurDAG -> ReplaceAllUsesOfValuesWith ( From , To , <NUM_LIT> ) ; } }"
LLVM,RISCV,2192,"Predict the next statement of this code snippet:
 <s> SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; ++ Position ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) || ! ( N -> getMachineOpcode ( ) == <STR_LIT> ) ) continue ; SDValue F64Val = N -> getOperand ( <NUM_LIT> ) ; if ( F64Val . isMachineOpcode ( ) && F64Val . getMachineOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;"
LLVM,RISCV,2193,"Predict the next statement of this code snippet:
 <s> doPeepholeLoadStoreADDI ( ) ;"
LLVM,RISCV,2194,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: PostprocessISelDAG ( ) { doPeepholeLoadStoreADDI ( ) ; doPeepholeBuildPairF64SplitF64 ( ) ;"
LLVM,RISCV,2195,"Predict the next statement of this code snippet:
 <s> auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } if ( Opcode == <STR_LIT> ) { SDLoc DL ( Node ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;"
LLVM,RISCV,2196,"Predict the next statement of this code snippet:
 <s> if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && VT == XLenVT ) { auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } }"
LLVM,RISCV,2197,"Predict the next statement of this code snippet:
 <s> for ( auto UI = Node -> use_begin ( ) , UE = Node -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( ! User -> isMachineOpcode ( ) ) return false ; switch ( User -> getMachineOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ; break ; case <STR_LIT> : if ( Bits < ( <NUM_LIT> - countLeadingZeros ( User -> getConstantOperandVal ( <NUM_LIT> ) ) ) ) return false ; break ; case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> :"
LLVM,RISCV,2198,"Predict the next statement of this code snippet:
 <s> assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDValue Lo = N -> getOperand ( <NUM_LIT> ) ; SDValue Hi = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && VT . isScalableVector ( ) && Lo . getValueType ( ) == <STR_LIT> && Hi . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( N ) ; int FI = FuncInfo -> getMoveF64FrameIndex ( MF ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ; SDValue StackSlot = CurDAG -> getFrameIndex ( FI , TLI . getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; SDValue Chain = CurDAG -> getEntryNode ( ) ; Lo = CurDAG -> getStore ( Chain , DL , Lo , StackSlot , MPI , Align ( <NUM_LIT> ) ) ; SDValue OffsetSlot = CurDAG -> getMemBasePlusOffset ( StackSlot , TypeSize :: Fixed ( <NUM_LIT> ) , DL ) ; Hi = CurDAG -> getStore ( Chain , DL , Hi , OffsetSlot , MPI . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; Chain = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDVTList VTs = CurDAG -> getVTList ( { VT , <STR_LIT> } ) ; SDValue IntID = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , IntID , CurDAG -> getUNDEF ( VT ) , StackSlot , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) , VL } ; SDValue Result = CurDAG -> getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , <STR_LIT> , MPI , Align ( <NUM_LIT> ) , MachineMemOperand :: MOLoad ) ; -- I ;"
LLVM,RISCV,2199,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: selectVLOp ( SDValue N , SDValue & VL ) { auto * C = dyn_cast < ConstantSDNode > ( N ) ; if ( C && ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) || C -> getSExtValue ( ) == <STR_LIT> ) ) VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; else VL = N ;"
LLVM,RISCV,2200,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; uint64_t Mask ; if ( Op1 . getOpcode ( ) == <STR_LIT> && isConstantMask ( Op0 . getNode ( ) , Mask ) ) { uint64_t ShAmt = cast < ConstantSDNode > ( Op1 . getNode ( ) ) -> getZExtValue ( ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) {"
LLVM,RISCV,2201,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } unsigned Opcode = Node -> getOpcode ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; uint64_t Mask ; if ( Op1 . getOpcode ( ) == <STR_LIT> && isConstantMask ( Op0 . getNode ( ) , Mask ) ) { uint64_t ShAmt = cast < ConstantSDNode > ( Op1 . getNode ( ) ) -> getZExtValue ( ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) {"
LLVM,RISCV,2202,"Predict the next statement of this code snippet:
 <s> if ( C && C -> isNullValue ( ) ) VL = SDValue ( selectImm ( CurDAG , SDLoc ( N ) , <NUM_LIT> , Subtarget -> getXLenVT ( ) ) , <NUM_LIT> ) ; else VL = N ;"
LLVM,RISCV,2203,"Predict the next statement of this code snippet:
 <s> auto * C = dyn_cast < ConstantSDNode > ( N ) ; if ( C && C -> isNullValue ( ) ) VL = SDValue ( selectImm ( CurDAG , SDLoc ( N ) , <NUM_LIT> , Subtarget -> getXLenVT ( ) ) , <NUM_LIT> ) ; else VL = N ;"
LLVM,RISCV,2204,"Predict the next statement of this code snippet:
 <s> if ( simm12 && signExtend ) Opcode = <STR_LIT> ; else if ( simm12 && ! signExtend ) Opcode = <STR_LIT> ; else if ( ! simm12 && signExtend ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; break ; case <STR_LIT> : if ( simm12 ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; default : break ; } if ( ! Opcode ) break ; ReplaceNode ( Node , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Chain . getSimpleValueType ( ) , Base , Offset , Chain ) ) ; return ; } case <STR_LIT> : { ShuffleVectorSDNode * Shuffle = cast < ShuffleVectorSDNode > ( Node ) ; SDValue Vec0 = Shuffle -> getOperand ( <NUM_LIT> ) ; SDValue Vec1 = Shuffle -> getOperand ( <NUM_LIT> ) ; unsigned Opcode ; int imm ; if ( Vec1 -> getOpcode ( ) == <STR_LIT> ) { if ( VT == <STR_LIT> ) { Opcode = <STR_LIT> ; imm = ( Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; imm |= Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ; } else { switch ( Shuffle -> getMaskElt ( <NUM_LIT> ) ) { default : case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } imm = ( Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; imm |= ( Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; imm |= Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ; } SDValue Imm = CurDAG -> getTargetConstant ( imm , SDLoc ( Node ) , <STR_LIT> ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( Opcode , DL , VT , Vec0 , Imm ) ) ; return ; } if ( VT == <STR_LIT> ) { Opcode = <STR_LIT> ; imm = ( Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; imm |= Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ; } else { Opcode = <STR_LIT> ; imm = ( Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; imm |= ( Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; imm |= ( Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; imm |= Shuffle -> getMaskElt ( <NUM_LIT> ) & <NUM_LIT> ; } SDValue Imm = SDValue ( selectImm ( CurDAG , DL , imm , <STR_LIT> ) , <NUM_LIT> ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( Opcode , DL , VT , Vec0 , Vec1 , Imm ) ) ; return ;"
LLVM,RISCV,2205,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectPCLIP ( SDValue Dest , SDValue & SRC1 , SDValue & SRC2 ) {"
LLVM,RISCV,2206,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectPCLIPU ( SDValue Dest , SDValue & SRC1 , SDValue & SRC2 ) {"
LLVM,RISCV,2207,"Predict the next statement of this code snippet:
 <s> SDValue Upper = CurDAG -> getConstant ( UpperVal , DL , VT ) ; if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; { HandleSDNode Handle ( Upper ) ; SelectCode ( Upper . getNode ( ) ) ; Upper = Handle . getValue ( ) ; } SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL , VT , Upper , Lower ) ; ReplaceUses ( Node , Or . getNode ( ) ) ; CurDAG -> RemoveDeadNode ( Node ) ;"
LLVM,RISCV,2208,"Predict the next statement of this code snippet:
 <s> { HandleSDNode Handle ( Upper ) ; SelectCode ( Upper . getNode ( ) ) ; Upper = Handle . getValue ( ) ; } SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL , VT , Upper , Lower ) ; ReplaceUses ( Node , Or . getNode ( ) ) ; CurDAG -> RemoveDeadNode ( Node ) ;"
LLVM,RISCV,2209,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget -> getXLenVT ( ) ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } break ; } case <STR_LIT> : {"
LLVM,RISCV,2210,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { if ( auto * ConstOp = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { if ( ! ( ConstOp -> hasOneUse ( ) ) ) break ; int64_t Imm = ConstOp -> getSExtValue ( ) ; if ( ! ( - <NUM_LIT> <= Imm && Imm <= - <NUM_LIT> ) && ! ( <NUM_LIT> <= Imm && Imm <= <NUM_LIT> ) ) break ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; const SDValue ImmOp0 = CurDAG -> getTargetConstant ( Imm - Imm / <NUM_LIT> , DL , VT ) ; const SDValue ImmOp1 = CurDAG -> getTargetConstant ( Imm / <NUM_LIT> , DL , VT ) ; auto * NodeAddi0 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Node -> getOperand ( <NUM_LIT> ) , ImmOp0 ) ; auto * NodeAddi1 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( NodeAddi0 , <NUM_LIT> ) , ImmOp1 ) ; ReplaceNode ( Node , NodeAddi1 ) ; return ; } break ; } case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) {"
LLVM,RISCV,2211,"Predict the next statement of this code snippet:
 <s> return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; uint64_t Mask ; if ( Op1 . getOpcode ( ) == <STR_LIT> && isConstantMask ( Op0 . getNode ( ) , Mask ) ) { uint64_t ShAmt = cast < ConstantSDNode > ( Op1 . getNode ( ) ) -> getZExtValue ( ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) { SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( Node ) , XLenVT ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , XLenVT , Op0 . getOperand ( <NUM_LIT> ) , ShAmtVal ) ; return ; } } break ; } case <STR_LIT> : assert ( ! Subtarget -> is64Bit ( ) && <STR_LIT> ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) ) ) ;"
LLVM,RISCV,2212,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: MatchSLLIUW ( SDNode * N ) const { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) ; if ( ! Subtarget -> is64Bit ( ) ) return false ; SDValue Shl = N -> getOperand ( <NUM_LIT> ) ; uint64_t VC1 = N -> getConstantOperandVal ( <NUM_LIT> ) ;"
LLVM,RISCV,2213,"Predict the next statement of this code snippet:
 <s> assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ;"
LLVM,RISCV,2214,"Predict the next statement of this code snippet:
 <s> return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDNode * Op0 = Node -> getOperand ( <NUM_LIT> ) . getNode ( ) ; uint64_t Mask ; if ( isa < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) && isConstantMask ( Op0 , Mask ) ) { uint64_t ShAmt = Node -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) { SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( Node ) , XLenVT ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , XLenVT , Op0 -> getOperand ( <NUM_LIT> ) , ShAmtVal ) ; return ; } } break ; } case <STR_LIT> : assert ( ! Subtarget -> is64Bit ( ) && <STR_LIT> ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) ) ) ; return ; case <STR_LIT> : { LoadSDNode * Load = cast < LoadSDNode > ( Node ) ; if ( Load -> getAddressingMode ( ) != <STR_LIT> ) break ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue Base = Node -> getOperand ( <NUM_LIT> ) ; SDValue Offset = Node -> getOperand ( <NUM_LIT> ) ; bool simm12 = false ; bool signExtend = Load -> getExtensionType ( ) == <STR_LIT> ; if ( auto ConstantOffset = dyn_cast < ConstantSDNode > ( Offset ) ) { int ConstantVal = ConstantOffset -> getSExtValue ( ) ; simm12 = isInt < <NUM_LIT> > ( ConstantVal ) ; if ( simm12 ) Offset = CurDAG -> getTargetConstant ( ConstantVal , SDLoc ( Offset ) , Offset . getValueType ( ) ) ; } unsigned Opcode = <NUM_LIT> ; switch ( Load -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : if ( simm12 && signExtend ) Opcode = <STR_LIT> ; else if ( simm12 && ! signExtend ) Opcode = <STR_LIT> ; else if ( ! simm12 && signExtend ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; break ; case <STR_LIT> : if ( simm12 && signExtend ) Opcode = <STR_LIT> ;"
LLVM,RISCV,2215,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectLoopDecrement ( SDValue LoopDecrement ) {"
LLVM,RISCV,2216,"Predict the next statement of this code snippet:
 <s> if ( And . getOperand ( <NUM_LIT> ) == Shl . getOperand ( <NUM_LIT> ) && isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( And . getOperand ( <NUM_LIT> ) ) ) { uint64_t VC1 = Srl . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t VC2 = Shl . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t VC3 = And . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC2 == ( <NUM_LIT> - VC1 ) && ( VC3 | maskTrailingOnes < uint64_t > ( VC1 ) ) == <NUM_LIT> ) { RS1 = Shl . getOperand ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( VC1 , SDLoc ( N ) , Srl . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; return true ;"
LLVM,RISCV,2217,"Predict the next statement of this code snippet:
 <s> SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; ++ Position ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) || ! ( N -> getMachineOpcode ( ) == <STR_LIT> ) ) continue ; SDValue F64Val = N -> getOperand ( <NUM_LIT> ) ; if ( F64Val . isMachineOpcode ( ) && F64Val . getMachineOpcode ( ) == <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( F64Val -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue From [ ] = { SDValue ( N , <NUM_LIT> ) , SDValue ( N , <NUM_LIT> ) } ; SDValue To [ ] = { F64Val . getOperand ( <NUM_LIT> ) , F64Val . getOperand ( <NUM_LIT> ) } ; CurDAG -> ReplaceAllUsesOfValuesWith ( From , To , <NUM_LIT> ) ; }"
LLVM,RISCV,2218,"Predict the next statement of this code snippet:
 <s> DEBUG ( F64Val -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue From [ ] = { SDValue ( N , <NUM_LIT> ) , SDValue ( N , <NUM_LIT> ) } ; SDValue To [ ] = { F64Val . getOperand ( <NUM_LIT> ) , F64Val . getOperand ( <NUM_LIT> ) } ; CurDAG -> ReplaceAllUsesOfValuesWith ( From , To , <NUM_LIT> ) ; } }"
LLVM,RISCV,2219,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TargetMachine , OptLevel ) {"
LLVM,RISCV,2220,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TargetMachine , OptLevel ) {"
LLVM,RISCV,2221,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } unsigned Opcode = Node -> getOpcode ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { if ( auto * ConstOp = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { if ( ! ( ConstOp -> hasOneUse ( ) ) ) break ; int64_t Imm = ConstOp -> getSExtValue ( ) ; if ( ! ( - <NUM_LIT> <= Imm && Imm <= - <NUM_LIT> ) && ! ( <NUM_LIT> <= Imm && Imm <= <NUM_LIT> ) ) break ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; const SDValue ImmOp0 = CurDAG -> getTargetConstant ( Imm - Imm / <NUM_LIT> , DL , VT ) ; const SDValue ImmOp1 = CurDAG -> getTargetConstant ( Imm / <NUM_LIT> , DL , VT ) ; auto * NodeAddi0 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Node -> getOperand ( <NUM_LIT> ) , ImmOp0 ) ; auto * NodeAddi1 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( NodeAddi0 , <NUM_LIT> ) , ImmOp1 ) ; ReplaceNode ( Node , NodeAddi1 ) ; return ; } break ; } case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ;"
LLVM,RISCV,2222,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: addVectorLoadStoreOperands ( SDNode * Node , unsigned Log2SEW , const SDLoc & DL , unsigned CurOp , bool IsMasked , bool IsStridedOrIndexed , SmallVectorImpl < SDValue > & Operands , bool IsLoad , MVT * IndexVT ) { SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue Glue ; SDValue Base ; SelectBaseAddr ( Node -> getOperand ( CurOp ++ ) , Base ) ; Operands . push_back ( Base ) ; if ( IsStridedOrIndexed ) { Operands . push_back ( Node -> getOperand ( CurOp ++ ) ) ; if ( IndexVT ) * IndexVT = Operands . back ( ) -> getSimpleValueType ( <NUM_LIT> ) ; } if ( IsMasked ) { SDValue Mask = Node -> getOperand ( CurOp ++ ) ; Chain = CurDAG -> getCopyToReg ( Chain , DL , <STR_LIT> , Mask , SDValue ( ) ) ; Glue = Chain . getValue ( <NUM_LIT> ) ;"
LLVM,RISCV,2223,"Predict the next statement of this code snippet:
 <s> static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;"
LLVM,RISCV,2224,"Predict the next statement of this code snippet:
 <s> static SDValue createM1Tuple ( SelectionDAG & CurDAG , ArrayRef < SDValue > Regs , unsigned NF ) { static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return createTupleImpl ( CurDAG , Regs , RegClassIDs [ NF - <NUM_LIT> ] , <STR_LIT> ) ;"
LLVM,RISCV,2225,"Predict the next statement of this code snippet:
 <s> return createTupleImpl ( CurDAG , Regs , RegClassIDs [ NF - <NUM_LIT> ] , <STR_LIT> ) ;"
LLVM,RISCV,2226,"Predict the next statement of this code snippet:
 <s> static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return createTupleImpl ( CurDAG , Regs , RegClassIDs [ NF - <NUM_LIT> ] , <STR_LIT> ) ;"
LLVM,RISCV,2227,"Predict the next statement of this code snippet:
 <s> return createTupleImpl ( CurDAG , Regs , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,2228,"Predict the next statement of this code snippet:
 <s> static SDValue createM4Tuple ( SelectionDAG & CurDAG , ArrayRef < SDValue > Regs , unsigned NF ) { return createTupleImpl ( CurDAG , Regs , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,2229,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel ( TM ) ;"
LLVM,RISCV,2230,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :: LMUL_F8 : case <STR_LIT> :: LMUL_F4 : case <STR_LIT> :: LMUL_F2 : case <STR_LIT> :: LMUL_1 :"
LLVM,RISCV,2231,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Regs [ <NUM_LIT> ] ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( CurDAG . getTargetConstant ( RegClassID , DL , <STR_LIT> ) ) ; for ( unsigned I = <NUM_LIT> ; I < Regs . size ( ) ; ++ I ) { Ops . push_back ( Regs [ I ] ) ; Ops . push_back ( CurDAG . getTargetConstant ( SubReg0 + I , DL , <STR_LIT> ) ) ;"
LLVM,RISCV,2232,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) ) return false ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) return false ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset2 = N -> getConstantOperandVal ( OffsetOpIdx ) ; if ( auto * Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { int64_t Offset1 = Const -> getSExtValue ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; if ( ! isInt < <NUM_LIT> > ( CombinedOffset ) ) return false ; ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto * GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { const DataLayout & DL = CurDAG -> getDataLayout ( ) ; Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) return false ; int64_t Offset1 = GA -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , CombinedOffset , GA -> getTargetFlags ( ) ) ; } else if ( auto * CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { Align Alignment = CP -> getAlign ( ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) return false ; int64_t Offset1 = CP -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CombinedOffset , CP -> getTargetFlags ( ) ) ; } else {"
LLVM,RISCV,2233,"Predict the next statement of this code snippet:
 <s> unsigned Opc ; switch ( N0 . getMachineOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getMachineOpcode ( ) == <STR_LIT> && ! isUInt < <NUM_LIT> > ( cast < ConstantSDNode > ( N01 ) -> getSExtValue ( ) ) ) break ; SDNode * Result = CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N00 , N01 ) ; ReplaceUses ( N , Result ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ReplaceUses ( N , N0 . getNode ( ) ) ;"
LLVM,RISCV,2234,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( N0 . getMachineOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2235,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,RISCV,2236,"Predict the next statement of this code snippet:
 <s> MadeChange |= doPeepholeSExtW ( N ) ; MadeChange |= doPeepholeLoadStoreADDI ( N ) ; } if ( MadeChange ) CurDAG -> RemoveDeadNodes ( ) ;"
LLVM,RISCV,2237,"Predict the next statement of this code snippet:
 <s> SDValue VL = N -> getOperand ( <NUM_LIT> ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && VT . isScalableVector ( ) && Lo . getValueType ( ) == <STR_LIT> && Hi . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( N ) ; int FI = FuncInfo -> getMoveF64FrameIndex ( MF ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ; SDValue StackSlot = CurDAG -> getFrameIndex ( FI , TLI . getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; SDValue Chain = CurDAG -> getEntryNode ( ) ; Lo = CurDAG -> getStore ( Chain , DL , Lo , StackSlot , MPI , Align ( <NUM_LIT> ) ) ; SDValue OffsetSlot = CurDAG -> getMemBasePlusOffset ( StackSlot , TypeSize :: Fixed ( <NUM_LIT> ) , DL ) ; Hi = CurDAG -> getStore ( Chain , DL , Hi , OffsetSlot , MPI . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; Chain = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDVTList VTs = CurDAG -> getVTList ( { VT , <STR_LIT> } ) ; SDValue IntID = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , IntID , StackSlot , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) , VL } ; SDValue Result = CurDAG -> getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , <STR_LIT> , MPI , Align ( <NUM_LIT> ) , MachineMemOperand :: MOLoad ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; }"
LLVM,RISCV,2238,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) {"
LLVM,RISCV,2239,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) {"
LLVM,RISCV,2240,"Predict the next statement of this code snippet:
 <s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;"
LLVM,RISCV,2241,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrFI ( SDValue Addr , SDValue & Base ) { if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) {"
LLVM,RISCV,2242,"Predict the next statement of this code snippet:
 <s> if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ; else Base = Addr ; return true ;"
LLVM,RISCV,2243,"Predict the next statement of this code snippet:
 <s> SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ; if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SrcReg , CurDAG -> getRegister ( <STR_LIT> , XLenVT ) ) ; else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SrcReg ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; SrcReg = SDValue ( Result , <NUM_LIT> ) ; }"
LLVM,RISCV,2244,"Predict the next statement of this code snippet:
 <s> switch ( ConstraintID ) { case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; case InlineAsm :: Constraint_A : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ;"
LLVM,RISCV,2245,"Predict the next statement of this code snippet:
 <s> if ( auto * C = dyn_cast < ConstantSDNode > ( N ) ) {"
LLVM,RISCV,2246,"Predict the next statement of this code snippet:
 <s> } MVT VT = N . getSimpleValueType ( ) ; if ( CurDAG -> ComputeNumSignBits ( N ) > ( VT . getSizeInBits ( ) - <NUM_LIT> ) ) { Val = N ; return true ; }"
LLVM,RISCV,2247,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: selectShiftMask ( SDValue N , unsigned ShiftWidth , SDValue & ShAmt ) { if ( N . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { const APInt & AndMask = N -> getConstantOperandAPInt ( <NUM_LIT> ) ;"
LLVM,RISCV,2248,"Predict the next statement of this code snippet:
 <s> if ( C && isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2249,"Predict the next statement of this code snippet:
 <s> MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , IsStrided , Operands , true ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsStrided , false , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ;"
LLVM,RISCV,2250,"Predict the next statement of this code snippet:
 <s> MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , IsStrided , Operands , true ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsStrided , false , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ;"
LLVM,RISCV,2251,"Predict the next statement of this code snippet:
 <s> addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , false , Operands , true ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , false , true , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDValue ( Load , <NUM_LIT> ) ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ;"
LLVM,RISCV,2252,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , true , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ;"
LLVM,RISCV,2253,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) { if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> ) return false ; SplatVal = N . getOperand ( <NUM_LIT> ) ; return true ;"
LLVM,RISCV,2254,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) {"
LLVM,RISCV,2255,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) { return selectVSplatSimmHelper ( N , SplatVal , * CurDAG , * Subtarget , [ ] ( int64_t Imm ) { return isInt < <NUM_LIT> > ( Imm ) ; } ) ;"
LLVM,RISCV,2256,"Predict the next statement of this code snippet:
 <s> return selectVSplatSimmHelper ( N , SplatVal , * CurDAG , * Subtarget , [ ] ( int64_t Imm ) { return ( isInt < <NUM_LIT> > ( Imm ) && Imm != - <NUM_LIT> ) || Imm == <NUM_LIT> ; } ) ;"
LLVM,RISCV,2257,"Predict the next statement of this code snippet:
 <s> return selectVSplatSimmHelper ( N , SplatVal , * CurDAG , * Subtarget , [ ] ( int64_t Imm ) { return ( isInt < <NUM_LIT> > ( Imm ) && Imm != - <NUM_LIT> ) || Imm == <NUM_LIT> ; } ) ;"
LLVM,RISCV,2258,"Predict the next statement of this code snippet:
 <s> return Imm != <NUM_LIT> && ( ( isInt < <NUM_LIT> > ( Imm ) && Imm != - <NUM_LIT> ) || Imm == <NUM_LIT> ) ; } ) ;"
LLVM,RISCV,2259,"Predict the next statement of this code snippet:
 <s> return selectVSplatSimmHelper ( N , SplatVal , * CurDAG , * Subtarget , [ ] ( int64_t Imm ) { return Imm != <NUM_LIT> && ( ( isInt < <NUM_LIT> > ( Imm ) && Imm != - <NUM_LIT> ) || Imm == <NUM_LIT> ) ; } ) ;"
LLVM,RISCV,2260,"Predict the next statement of this code snippet:
 <s> assert ( XLenVT == N . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) && <STR_LIT> ) ; MVT EltVT = N . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( EltVT . bitsLT ( XLenVT ) ) SplatImm = SignExtend64 ( SplatImm , EltVT . getSizeInBits ( ) ) ; if ( ! ValidateImm ( SplatImm ) ) return false ;"
LLVM,RISCV,2261,"Predict the next statement of this code snippet:
 <s> assert ( XLenVT == N . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) && <STR_LIT> ) ; MVT EltVT = N . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( EltVT . bitsLT ( XLenVT ) ) SplatImm = SignExtend64 ( SplatImm , EltVT . getSizeInBits ( ) ) ;"
LLVM,RISCV,2262,"Predict the next statement of this code snippet:
 <s> if ( ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> ) || ! isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) return false ; int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ;"
LLVM,RISCV,2263,"Predict the next statement of this code snippet:
 <s> if ( ! isUInt < <NUM_LIT> > ( SplatImm ) ) return false ; SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc ( N ) , Subtarget -> getXLenVT ( ) ) ; return true ;"
LLVM,RISCV,2264,"Predict the next statement of this code snippet:
 <s> ByValArgInfo ( ) : FirstIdx ( <NUM_LIT> ) , NumRegs ( <NUM_LIT> ) , Address ( <NUM_LIT> ) {"
LLVM,RISCV,2265,"Predict the next statement of this code snippet:
 <s> ByValArgInfo ( ) : FirstIdx ( <NUM_LIT> ) , NumRegs ( <NUM_LIT> ) , Address ( <NUM_LIT> ) {"
LLVM,RISCV,2266,"Predict the next statement of this code snippet:
 <s> EVT getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const override { return <STR_LIT> ;"
LLVM,RISCV,2267,"Predict the next statement of this code snippet:
 <s> bool isFMAFasterThanFMulAndFAdd ( EVT ) const override {"
LLVM,RISCV,2268,"Predict the next statement of this code snippet:
 <s> bool isFMAFasterThanFMulAndFAdd ( EVT ) const override {"
LLVM,RISCV,2269,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ;"
LLVM,RISCV,2270,"Predict the next statement of this code snippet:
 <s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ;"
LLVM,RISCV,2271,"Predict the next statement of this code snippet:
 <s> if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Value ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) Value = DAG . getLoad ( VA . getValVT ( ) , DL , Chain , Value , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; else assert ( VA . getLocInfo ( ) == CCValAssign :: Full && <STR_LIT> ) ;"
LLVM,RISCV,2272,"Predict the next statement of this code snippet:
 <s> static SDValue convertLocVTToValVT ( SelectionDAG & DAG , SDLoc DL , CCValAssign & VA , SDValue Chain , SDValue Value ) { if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Value ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) Value = DAG . getLoad ( VA . getValVT ( ) , DL , Chain , Value , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;"
LLVM,RISCV,2273,"Predict the next statement of this code snippet:
 <s> switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : return DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value ) ; case CCValAssign :: ZExt : return DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value ) ;"
LLVM,RISCV,2274,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : jump = <STR_LIT> ; RA = <STR_LIT> ; break ; case <STR_LIT> : jump = <STR_LIT> ; RA = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MachineInstrBuilder jumpMI = BuildMI ( * BB , MI , DL , TII -> get ( jump ) , RA ) ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; i ++ ) { jumpMI . addOperand ( MI -> getOperand ( i ) ) ; } MI -> eraseFromParent ( ) ; return BB ;"
LLVM,RISCV,2275,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitCALL ( MI , MBB ) ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,RISCV,2276,"Predict the next statement of this code snippet:
 <s> SDValue Hi = getTargetNode ( Op , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( Op , DAG , <STR_LIT> ) ; SDValue ResHi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) ; SDValue ResLo = DAG . getNode ( <STR_LIT> , DL , Ty , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , ResHi , ResLo ) ;"
LLVM,RISCV,2277,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; EVT Ty = Op . getValueType ( ) ;"
LLVM,RISCV,2278,"Predict the next statement of this code snippet:
 <s> case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ;"
LLVM,RISCV,2279,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . isRV64 ( ) ) return <STR_LIT> ; else return <STR_LIT> ;"
LLVM,RISCV,2280,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { if ( Subtarget . isRV64 ( ) ) return <STR_LIT> ;"
LLVM,RISCV,2281,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . isRV64 ( ) ) return <STR_LIT> ;"
LLVM,RISCV,2282,"Predict the next statement of this code snippet:
 <s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'd' : case 'r' : if ( Subtarget . isRV64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( Subtarget . hasD ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( Subtarget . hasF ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( Subtarget . isRV64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,RISCV,2283,"Predict the next statement of this code snippet:
 <s> Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ;"
LLVM,RISCV,2284,"Predict the next statement of this code snippet:
 <s> EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( GlobalAddressSDNode * N = dyn_cast < GlobalAddressSDNode > ( Op ) ) return DAG . getTargetGlobalAddress ( N -> getGlobal ( ) , SDLoc ( Op ) , Ty , <NUM_LIT> , Flag ) ; if ( ExternalSymbolSDNode * N = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( N -> getSymbol ( ) , Ty , Flag ) ; if ( BlockAddressSDNode * N = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , <NUM_LIT> , Flag ) ; if ( JumpTableSDNode * N = dyn_cast < JumpTableSDNode > ( Op ) ) return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ;"
LLVM,RISCV,2285,"Predict the next statement of this code snippet:
 <s> OPCODE ( Lo ) ; OPCODE ( FENCE ) ; OPCODE ( SELECT_CC ) ; }"
LLVM,RISCV,2286,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ;"
LLVM,RISCV,2287,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return Imm . isPosZero ( ) ;"
LLVM,RISCV,2288,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ;"
LLVM,RISCV,2289,"Predict the next statement of this code snippet:
 <s> return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'M' :"
LLVM,RISCV,2290,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; unsigned PI , PO , PR , PW , SI , SO , SR , SW ; switch ( Op . getConstantOperandVal ( <NUM_LIT> ) ) { case NotAtomic : case Unordered : case Monotonic : case Acquire : case Release : case AcquireRelease : case SequentiallyConsistent : PI = <NUM_LIT> << <NUM_LIT> ; PO = <NUM_LIT> << <NUM_LIT> ; PR = <NUM_LIT> << <NUM_LIT> ; PW = <NUM_LIT> << <NUM_LIT> ; } switch ( Op . getConstantOperandVal ( <NUM_LIT> ) ) {"
LLVM,RISCV,2291,"Predict the next statement of this code snippet:
 <s> int64_t Offset = Node -> getOffset ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;"
LLVM,RISCV,2292,"Predict the next statement of this code snippet:
 <s> const BlockAddress * BA = Node -> getBlockAddress ( ) ; int64_t Offset = Node -> getOffset ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset ) ; return Result ;"
LLVM,RISCV,2293,"Predict the next statement of this code snippet:
 <s> SDValue Result ; if ( CP -> isMachineConstantPoolEntry ( ) ) Result = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; else Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) ) ;"
LLVM,RISCV,2294,"Predict the next statement of this code snippet:
 <s> if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT ValVT = VA . getValVT ( ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; InVals . push_back ( DAG . getLoad ( ValVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( IsVarArg ) { auto ArgRegs = IsRV32 ? RV32IntRegs : RV64IntRegs ; unsigned NumRegs = llvm :: <STR_LIT> ; unsigned Idx = CCInfo . getFirstUnallocated ( ArrayRef < MCPhysReg > ( ArgRegs , <NUM_LIT> ) ) ; unsigned RegSize = IsRV32 ? <NUM_LIT> : <NUM_LIT> ; MVT RegTy = <STR_LIT> ( RegSize * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; int VaArgOffset ; if ( NumRegs == Idx ) VaArgOffset = RoundUpToAlignment ( CCInfo . getNextStackOffset ( ) , RegSize ) ; else VaArgOffset = - ( int ) ( RegSize * ( NumRegs - Idx ) ) ; int FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < NumRegs ; ++ I , VaArgOffset += RegSize ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ;"
LLVM,RISCV,2295,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const {"
LLVM,RISCV,2296,"Predict the next statement of this code snippet:
 <s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Op ) ) { Op = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , SDLoc ( Op ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return getAddrPIC ( Op , DAG ) ;"
LLVM,RISCV,2297,"Predict the next statement of this code snippet:
 <s> Op = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , SDLoc ( Op ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return getAddrPIC ( Op , DAG ) ; }"
LLVM,RISCV,2298,"Predict the next statement of this code snippet:
 <s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,RISCV,2299,"Predict the next statement of this code snippet:
 <s> assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ;"
LLVM,RISCV,2300,"Predict the next statement of this code snippet:
 <s> SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ;"
LLVM,RISCV,2301,"Predict the next statement of this code snippet:
 <s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( cast < BlockAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerJumpTable ( cast < JumpTableSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ;"
LLVM,RISCV,2302,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return lowerGlobalTLSAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( cast < BlockAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerJumpTable ( cast < JumpTableSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVAARG ( Op , DAG ) ;"
LLVM,RISCV,2303,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . isRV64 ( ) ) RetCCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64 ) ; else RetCCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Glue ; if ( RetLocs . empty ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned I = <NUM_LIT> , E = RetLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = RetLocs [ I ] ; SDValue RetValue = OutVals [ I ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetValue = convertValVTToLocVT ( DAG , DL , VA , RetValue ) ; unsigned Reg = VA . getLocReg ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , Reg , RetValue , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( Reg , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) RetOps . push_back ( Glue ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps ) ;"
LLVM,RISCV,2304,"Predict the next statement of this code snippet:
 <s> MVT VT = Op . getSimpleValueType ( ) ; unsigned RA = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; MFI -> setReturnAddressIsTaken ( true ) ;"
LLVM,RISCV,2305,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ;"
LLVM,RISCV,2306,"Predict the next statement of this code snippet:
 <s> SDValue Cond = DAG . getNode ( <STR_LIT> , DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , Ty ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2307,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerSTACKRESTORE ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setManipulatesSP ( true ) ; unsigned sp = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,2308,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerSTACKSAVE ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setManipulatesSP ( true ) ;"
LLVM,RISCV,2309,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setManipulatesSP ( true ) ; unsigned sp = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , sp , Op . getValueType ( ) ) ;"
LLVM,RISCV,2310,"Predict the next statement of this code snippet:
 <s> InChain = DAG . getStore ( VAList . getValue ( <NUM_LIT> ) , DL , NextPtr , VAListPtr , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; return DAG . getLoad ( VT , DL , InChain , VAList , MachinePointerInfo ( ) , false , false , false , std :: min ( PtrVT . getSizeInBits ( ) , VT . getSizeInBits ( ) ) / <NUM_LIT> ) ;"
LLVM,RISCV,2311,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2312,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ;"
LLVM,RISCV,2313,"Predict the next statement of this code snippet:
 <s> if ( IsRet ) ArgTy = FType -> getReturnType ( ) ; else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ;"
LLVM,RISCV,2314,"Predict the next statement of this code snippet:
 <s> if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy ) ) {"
LLVM,RISCV,2315,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> ; i != NumArgs ; i ++ ) { MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ;"
LLVM,RISCV,2316,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; EVT Ty = Op . getValueType ( ) ; BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; const BlockAddress * BA = N -> getBlockAddress ( ) ; int64_t Offset = N -> getOffset ( ) ; if ( isPositionIndependent ( ) || Subtarget . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue BAHi = DAG . getTargetBlockAddress ( BA , Ty , Offset , <STR_LIT> ) ;"
LLVM,RISCV,2317,"Predict the next statement of this code snippet:
 <s> const char * Sym = N -> getSymbol ( ) ; if ( isPositionIndependent ( ) || Subtarget . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue GAHi = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue GALo = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , GAHi ) , <NUM_LIT> ) ; SDValue MNLo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , GALo ) , <NUM_LIT> ) ;"
LLVM,RISCV,2318,"Predict the next statement of this code snippet:
 <s> SDValue GAHi = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue GALo = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ;"
LLVM,RISCV,2319,"Predict the next statement of this code snippet:
 <s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - ( XLenInBytes * <NUM_LIT> ) ;"
LLVM,RISCV,2320,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; unsigned FrameReg = RI . getFrameRegister ( MF ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - ( XLenInBytes * <NUM_LIT> ) ;"
LLVM,RISCV,2321,"Predict the next statement of this code snippet:
 <s> const GlobalValue * GV = N -> getGlobal ( ) ; int64_t Offset = N -> getOffset ( ) ; if ( isPositionIndependent ( ) || Subtarget . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , Offset , <STR_LIT> ) ;"
LLVM,RISCV,2322,"Predict the next statement of this code snippet:
 <s> return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ;"
LLVM,RISCV,2323,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ;"
LLVM,RISCV,2324,"Predict the next statement of this code snippet:
 <s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; unsigned RegLo = VA . getLocReg ( ) ; unsigned RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = packIntoRegLoc ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) { RetOps . push_back ( Glue ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps ) ;"
LLVM,RISCV,2325,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { int Off = - XLenInBytes ; SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( Off , DL , VT ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( RI . getRARegister ( ) , getRegClassFor ( XLenVT ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , XLenVT ) ;"
LLVM,RISCV,2326,"Predict the next statement of this code snippet:
 <s> break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ; break ; }"
LLVM,RISCV,2327,"Predict the next statement of this code snippet:
 <s> EVT LocVT = VA . getLocVT ( ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ;"
LLVM,RISCV,2328,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,RISCV,2329,"Predict the next statement of this code snippet:
 <s> EVT ValVT = VA . getValVT ( ) ; SDValue Val ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , ValVT , Val ) ; break ; }"
LLVM,RISCV,2330,"Predict the next statement of this code snippet:
 <s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; EVT ValVT = VA . getValVT ( ) ; SDValue Val ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ;"
LLVM,RISCV,2331,"Predict the next statement of this code snippet:
 <s> else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ;"
LLVM,RISCV,2332,"Predict the next statement of this code snippet:
 <s> MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; Type * OrigTy = CLI ? CLI -> getArgs ( ) [ Outs [ i ] . OrigArgIndex ] . Ty : nullptr ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ;"
LLVM,RISCV,2333,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr ) ) return false ; } return true ;"
LLVM,RISCV,2334,"Predict the next statement of this code snippet:
 <s> State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , XLenInBytes ) , LocVT2 , CCValAssign :: Full ) ) ; return false ; } if ( Register Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo2 , ValVT2 , Reg , LocVT2 , CCValAssign :: Full ) ) ; } else {"
LLVM,RISCV,2335,"Predict the next statement of this code snippet:
 <s> if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset4 = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset4 , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset5 = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset5 , LocVT , LocInfo ) ) ; return false ; } return true ;"
LLVM,RISCV,2336,"Predict the next statement of this code snippet:
 <s> if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset4 = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset4 , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) {"
LLVM,RISCV,2337,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,2338,"Predict the next statement of this code snippet:
 <s> switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ;"
LLVM,RISCV,2339,"Predict the next statement of this code snippet:
 <s> case CCValAssign :: Full : break ; case CCValAssign :: BCvt : if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ; break ;"
LLVM,RISCV,2340,"Predict the next statement of this code snippet:
 <s> SDValue NewOp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2341,"Predict the next statement of this code snippet:
 <s> SDValue NewOp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2342,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( LoReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( HiReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; TII . loadRegFromStackSlot ( * BB , MI , DstReg , FI , DstRC , RI ) ; MI . eraseFromParent ( ) ;"
LLVM,RISCV,2343,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB ) ; case <STR_LIT> : return emitBuildPairF64Pseudo ( MI , BB ) ; case <STR_LIT> : return emitSplitF64Pseudo ( MI , BB ) ; }"
LLVM,RISCV,2344,"Predict the next statement of this code snippet:
 <s> } ) ) break ; } } const TargetInstrInfo & TII = * BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; for ( MachineInstr * DebugInstr : SelectDebugValues ) { TailMBB -> push_back ( DebugInstr -> removeFromParent ( ) ) ; } TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; unsigned Opcode = getBranchOpcodeForIntCondCode ( CC ) ; BuildMI ( HeadMBB , DL , TII . get ( Opcode ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( TailMBB ) ; IfFalseMBB -> addSuccessor ( TailMBB ) ; auto SelectMBBI = MI . getIterator ( ) ; auto SelectEnd = std :: next ( LastSelectPseudo -> getIterator ( ) ) ; auto InsertionPoint = TailMBB -> begin ( ) ; while ( SelectMBBI != SelectEnd ) { auto Next = std :: next ( SelectMBBI ) ; if ( isSelectPseudo ( * SelectMBBI ) ) { BuildMI ( * TailMBB , InsertionPoint , SelectMBBI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( HeadMBB ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( IfFalseMBB ) ; SelectMBBI -> eraseFromParent ( ) ;"
LLVM,RISCV,2345,"Predict the next statement of this code snippet:
 <s> Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto CC = static_cast < <STR_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; SmallVector < MachineInstr * , <NUM_LIT> > SelectDebugValues ; SmallSet < Register , <NUM_LIT> > SelectDests ; SelectDests . insert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * LastSelectPseudo = & MI ; for ( auto E = BB -> end ( ) , SequenceMBBI = MachineBasicBlock :: iterator ( MI ) ; SequenceMBBI != E ; ++ SequenceMBBI ) { if ( SequenceMBBI -> isDebugInstr ( ) ) continue ; else if ( isSelectPseudo ( * SequenceMBBI ) ) { if ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != LHS || SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != RHS || SequenceMBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) != CC || SelectDests . count ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) || SelectDests . count ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) break ; LastSelectPseudo = & * SequenceMBBI ;"
LLVM,RISCV,2346,"Predict the next statement of this code snippet:
 <s> static MachineBasicBlock * emitSplitF64Pseudo ( MachineInstr & MI , MachineBasicBlock * BB ) { assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = * BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ;"
LLVM,RISCV,2347,"Predict the next statement of this code snippet:
 <s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'f' : return C_RegisterClass ; case 'I' : case 'J' : case 'K' : return C_Immediate ; case 'A' :"
LLVM,RISCV,2348,"Predict the next statement of this code snippet:
 <s> case 'K' : return C_Immediate ; case 'A' : return C_Memory ; } }"
LLVM,RISCV,2349,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const {"
LLVM,RISCV,2350,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return <STR_LIT> ;"
LLVM,RISCV,2351,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,2352,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,2353,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }"
LLVM,RISCV,2354,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ;"
LLVM,RISCV,2355,"Predict the next statement of this code snippet:
 <s> return ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) ) || ( VT == <STR_LIT> && Subtarget . hasStdExtD ( ) ) ;"
LLVM,RISCV,2356,"Predict the next statement of this code snippet:
 <s> APInt ShiftedC1Int = C1Int << C2 -> getAPIntValue ( ) ; if ( ShiftedC1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( C1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ;"
LLVM,RISCV,2357,"Predict the next statement of this code snippet:
 <s> if ( Constraint . length ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'I' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { uint64_t CVal = C -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( CVal ) ) Ops . push_back ( DAG . getTargetConstant ( CVal , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ;"
LLVM,RISCV,2358,"Predict the next statement of this code snippet:
 <s> continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes ; } for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const Register Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store ) ; } RVFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ;"
LLVM,RISCV,2359,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget . getXLenVT ( ) ; TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( N -> getGlobal ( ) ) ; SDValue Addr ; switch ( Model ) { case TLSModel :: LocalExec : Addr = getStaticTLSAddr ( N , DAG , false ) ; break ; case TLSModel :: InitialExec :"
LLVM,RISCV,2360,"Predict the next statement of this code snippet:
 <s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; if ( STI . isRegisterReservedByUser ( RegLo ) || STI . isRegisterReservedByUser ( RegHi ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ;"
LLVM,RISCV,2361,"Predict the next statement of this code snippet:
 <s> if ( STI . isRegisterReservedByUser ( RegLo ) || STI . isRegisterReservedByUser ( RegHi ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; if ( STI . isRegisterReservedByUser ( VA . getLocReg ( ) ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) { RetOps . push_back ( Glue ) ; } const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { if ( ! Func . getReturnType ( ) -> isVoidTy ( ) ) report_fatal_error ( <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; StringRef Kind = MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned RetOpc ; if ( Kind == <STR_LIT> ) RetOpc = <STR_LIT> ;"
LLVM,RISCV,2362,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ; break ; }"
LLVM,RISCV,2363,"Predict the next statement of this code snippet:
 <s> int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,2364,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ; const TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } Register VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return Val ; return convertLocVTToValVT ( DAG , Val , VA , DL ) ;"
LLVM,RISCV,2365,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } Register VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return Val ; return convertLocVTToValVT ( DAG , Val , VA , DL ) ;"
LLVM,RISCV,2366,"Predict the next statement of this code snippet:
 <s> const Function & F = MF . getFunction ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( std :: any_of ( std :: begin ( Regs ) , std :: end ( Regs ) , [ & STI ] ( auto Reg ) {"
LLVM,RISCV,2367,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( std :: any_of ( std :: begin ( Regs ) , std :: end ( Regs ) , [ & STI ] ( auto Reg ) { return STI . isRegisterReservedByUser ( Reg . first ) ; } ) ) F . getContext ( ) . diagnose ( DiagnosticInfoUnsupported {"
LLVM,RISCV,2368,"Predict the next statement of this code snippet:
 <s> LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return false ; } assert ( LocVT == XLenVT && <STR_LIT> ) ; if ( Reg ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; } else {"
LLVM,RISCV,2369,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget & getSubtarget ( ) const { return Subtarget ;"
LLVM,RISCV,2370,"Predict the next statement of this code snippet:
 <s> return Subtarget ;"
LLVM,RISCV,2371,"Predict the next statement of this code snippet:
 <s> unsigned XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . getLocVT ( ) == XLenVT && <STR_LIT> ) ; SDValue ArgValue ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) ArgValue = unpackF64OnRV32DSoftABI ( DAG , Chain , VA , DL ) ; else if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; assert ( Ins [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ;"
LLVM,RISCV,2372,"Predict the next statement of this code snippet:
 <s> const GlobalValue * GV = N -> getGlobal ( ) ; int64_t Offset = N -> getOffset ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( isPositionIndependent ( ) || Subtarget . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ;"
LLVM,RISCV,2373,"Predict the next statement of this code snippet:
 <s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; unsigned RegLo = VA . getLocReg ( ) ; unsigned RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ;"
LLVM,RISCV,2374,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,RISCV,2375,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,RISCV,2376,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = * BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( LoReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( HiReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;"
LLVM,RISCV,2377,"Predict the next statement of this code snippet:
 <s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ;"
LLVM,RISCV,2378,"Predict the next statement of this code snippet:
 <s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; TII . storeRegToStackSlot ( * BB , MI , SrcReg , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , FI , SrcRC , RI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ; return BB ;"
LLVM,RISCV,2379,"Predict the next statement of this code snippet:
 <s> int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; TII . storeRegToStackSlot ( * BB , MI , SrcReg , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , FI , SrcRC , RI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;"
LLVM,RISCV,2380,"Predict the next statement of this code snippet:
 <s> if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ;"
LLVM,RISCV,2381,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtD ( ) ) return false ;"
LLVM,RISCV,2382,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc DL ( Op ) ;"
LLVM,RISCV,2383,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;"
LLVM,RISCV,2384,"Predict the next statement of this code snippet:
 <s> assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; }"
LLVM,RISCV,2385,"Predict the next statement of this code snippet:
 <s> SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ;"
LLVM,RISCV,2386,"Predict the next statement of this code snippet:
 <s> if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal ( ) ) return false ; return true ;"
LLVM,RISCV,2387,"Predict the next statement of this code snippet:
 <s> if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) {"
LLVM,RISCV,2388,"Predict the next statement of this code snippet:
 <s> break ; case TLSModel :: LocalDynamic : case TLSModel :: GeneralDynamic : Addr = getDynamicTLSAddr ( N , DAG ) ; break ; } if ( Offset != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Ty , Addr , DAG . getConstant ( Offset , DL , XLenVT ) ) ; return Addr ;"
LLVM,RISCV,2389,"Predict the next statement of this code snippet:
 <s> } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ;"
LLVM,RISCV,2390,"Predict the next statement of this code snippet:
 <s> if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg ; if ( ValVT == <STR_LIT> && ! UseGPRForF32 ) Reg = State . AllocateReg ( ArgFPR32s , ArgFPR64s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s , ArgFPR32s ) ; else Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( ) ;"
LLVM,RISCV,2391,"Predict the next statement of this code snippet:
 <s> BB -> addSuccessor ( LoopMBB ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned ReadAgainReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , HiReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ;"
LLVM,RISCV,2392,"Predict the next statement of this code snippet:
 <s> TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; unsigned Opcode = getBranchOpcodeForIntCondCode ( CC ) ; BuildMI ( HeadMBB , DL , TII . get ( Opcode ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( TailMBB ) ; IfFalseMBB -> addSuccessor ( TailMBB ) ; auto SelectMBBI = MI . getIterator ( ) ; auto SelectEnd = std :: next ( LastSelectPseudo -> getIterator ( ) ) ; auto InsertionPoint = TailMBB -> begin ( ) ; while ( SelectMBBI != SelectEnd ) { auto Next = std :: next ( SelectMBBI ) ; if ( isSelectPseudo ( * SelectMBBI ) ) { BuildMI ( * TailMBB , InsertionPoint , SelectMBBI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( HeadMBB ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( IfFalseMBB ) ; SelectMBBI -> eraseFromParent ( ) ;"
LLVM,RISCV,2393,"Predict the next statement of this code snippet:
 <s> if ( isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = <STR_LIT> ( ShiftedC1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ;"
LLVM,RISCV,2394,"Predict the next statement of this code snippet:
 <s> auto CalleeCC = CLI . CallConv ; auto IsVarArg = CLI . IsVarArg ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) return false ; if ( Caller . hasFnAttribute ( <STR_LIT> ) ) return false ; if ( IsVarArg ) return false ; if ( CCInfo . getNextStackOffset ( ) != <NUM_LIT> ) return false ; for ( auto & VA : ArgLocs ) if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ;"
LLVM,RISCV,2395,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RCW ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2396,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RCW ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ;"
LLVM,RISCV,2397,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( RC ) ;"
LLVM,RISCV,2398,"Predict the next statement of this code snippet:
 <s> static SDValue unpackFromRegLoc ( SelectionDAG & DAG , SDValue Chain , const CCValAssign & VA , const SDLoc & DL ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ; const TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return Val ; return convertLocVTToValVT ( DAG , Val , VA , DL ) ;"
LLVM,RISCV,2399,"Predict the next statement of this code snippet:
 <s> } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; }"
LLVM,RISCV,2400,"Predict the next statement of this code snippet:
 <s> unsigned TwoXLenInBytes = ( <NUM_LIT> * XLen ) / <NUM_LIT> ; if ( ! IsFixed && ArgFlags . getOrigAlign ( ) == TwoXLenInBytes && DL . getTypeAllocSize ( OrigTy ) == TwoXLenInBytes ) { unsigned RegIdx = State . getFirstUnallocated ( ArgGPRs ) ; if ( RegIdx != array_lengthof ( ArgGPRs ) && RegIdx % <NUM_LIT> == <NUM_LIT> ) State . AllocateReg ( ArgGPRs ) ; } SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( ) ;"
LLVM,RISCV,2401,"Predict the next statement of this code snippet:
 <s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; TailMBB -> splice ( TailMBB -> begin ( ) , HeadMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ;"
LLVM,RISCV,2402,"Predict the next statement of this code snippet:
 <s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ;"
LLVM,RISCV,2403,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }"
LLVM,RISCV,2404,"Predict the next statement of this code snippet:
 <s> CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: Indirect : { SDValue SpillSlot = DAG . CreateStackTemporary ( Outs [ i ] . ArgVT ) ; int FI = cast < FrameIndexSDNode > ( SpillSlot ) -> getIndex ( ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , SpillSlot , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; unsigned ArgIndex = Outs [ i ] . OrigArgIndex ; assert ( Outs [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Outs [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { SDValue PartValue = OutVals [ i + <NUM_LIT> ] ; unsigned PartOffset = Outs [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , SpillSlot , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , PartValue , Address , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; ++ i ; } ArgValue = SpillSlot ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( Flags . isByVal ( ) ) ArgValue = ByValArgs [ j ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ) ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , Address , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; SDValue Glue ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , Glue ) ;"
LLVM,RISCV,2405,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget . getXLenVT ( ) ; unsigned XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . getLocVT ( ) == XLenVT && <STR_LIT> ) ; SDValue ArgValue ; if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; assert ( Ins [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ;"
LLVM,RISCV,2406,"Predict the next statement of this code snippet:
 <s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; assert ( VA . getLocInfo ( ) == CCValAssign :: Full && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;"
LLVM,RISCV,2407,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ;"
LLVM,RISCV,2408,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setMinFunctionAlignment ( <NUM_LIT> ) ; setPrefFunctionAlignment ( <NUM_LIT> ) ;"
LLVM,RISCV,2409,"Predict the next statement of this code snippet:
 <s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; switch ( VA . getLocInfo ( ) ) {"
LLVM,RISCV,2410,"Predict the next statement of this code snippet:
 <s> unsigned NumArgs = Ins . size ( ) ; FunctionType * FType = MF . getFunction ( ) . getFunctionType ( ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasVInstructions ( ) ) FirstMaskArgument = preAssignMask ( Ins ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ArgVT = Ins [ i ] . VT ;"
LLVM,RISCV,2411,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . hasVInstructions ( ) ) FirstMaskArgument = preAssignMask ( Ins ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ArgVT = Ins [ i ] . VT ; <STR_LIT> ArgFlags = Ins [ i ] . Flags ; Type * ArgTy = nullptr ; if ( IsRet ) ArgTy = FType -> getReturnType ( ) ; else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( Fn ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet , ArgTy , * this , FirstMaskArgument ) ) {"
LLVM,RISCV,2412,"Predict the next statement of this code snippet:
 <s> if ( Fn ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr ) ;"
LLVM,RISCV,2413,"Predict the next statement of this code snippet:
 <s> Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasVInstructions ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr , * this , FirstMaskArgument ) ) return false ;"
LLVM,RISCV,2414,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasVInstructions ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) {"
LLVM,RISCV,2415,"Predict the next statement of this code snippet:
 <s> LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } unsigned TwoXLenInBytes = ( <NUM_LIT> * XLen ) / <NUM_LIT> ; if ( ! IsFixed && ArgFlags . getNonZeroOrigAlign ( ) == TwoXLenInBytes && DL . getTypeAllocSize ( OrigTy ) == TwoXLenInBytes ) { unsigned RegIdx = State . getFirstUnallocated ( ArgGPRs ) ; if ( RegIdx != array_lengthof ( ArgGPRs ) && RegIdx % <NUM_LIT> == <NUM_LIT> ) State . AllocateReg ( ArgGPRs ) ; } SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( UseGPRForF64 && XLen == <NUM_LIT> && ValVT == <STR_LIT> ) { assert ( ! ArgFlags . isSplit ( ) && PendingLocs . empty ( ) && <STR_LIT> ) ; Register Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ValVT . isFixedLengthVector ( ) ) LocVT = TLI . getContainerForFixedLengthVector ( LocVT ) ; if ( ValVT . isScalarInteger ( ) && ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ValVT . isScalarInteger ( ) && ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; }"
LLVM,RISCV,2416,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const {"
LLVM,RISCV,2417,"Predict the next statement of this code snippet:
 <s> if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfhmin ( ) ) return <STR_LIT> ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ;"
LLVM,RISCV,2418,"Predict the next statement of this code snippet:
 <s> if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfhmin ( ) ) return <STR_LIT> ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ;"
LLVM,RISCV,2419,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . hasVInstructions ( ) && ( VT . isScalableVector ( ) || Subtarget . useRVVForFixedLengthVectors ( ) ) ) return EVT :: getVectorVT ( Context , <STR_LIT> , VT . getVectorElementCount ( ) ) ;"
LLVM,RISCV,2420,"Predict the next statement of this code snippet:
 <s> return Subtarget . hasStdExtZbb ( ) && ! isa < ConstantSDNode > ( Y ) ;"
LLVM,RISCV,2421,"Predict the next statement of this code snippet:
 <s> if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ;"
LLVM,RISCV,2422,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isLegalElementTypeForRVV ( Type * ScalarTy ) const { if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) ) return true ; if ( ScalarTy -> isIntegerTy ( <NUM_LIT> ) ) return Subtarget . hasVInstructionsI64 ( ) ; if ( ScalarTy -> isHalfTy ( ) ) return Subtarget . hasVInstructionsF16 ( ) ; if ( ScalarTy -> isFloatTy ( ) ) return Subtarget . hasVInstructionsF32 ( ) ;"
LLVM,RISCV,2423,"Predict the next statement of this code snippet:
 <s> if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) ) return true ; if ( ScalarTy -> isIntegerTy ( <NUM_LIT> ) ) return Subtarget . hasVInstructionsI64 ( ) ; if ( ScalarTy -> isHalfTy ( ) ) return Subtarget . hasVInstructionsF16 ( ) ; if ( ScalarTy -> isFloatTy ( ) ) return Subtarget . hasVInstructionsF32 ( ) ; if ( ScalarTy -> isDoubleTy ( ) ) return Subtarget . hasVInstructionsF64 ( ) ; return false ;"
LLVM,RISCV,2424,"Predict the next statement of this code snippet:
 <s> MVT VT = Op . getSimpleValueType ( ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; MVT FloatEltVT = EltSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MVT FloatVT = <STR_LIT> ( FloatEltVT , VT . getVectorElementCount ( ) ) ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( FloatVT ) && <STR_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Src ) ; Src = DAG . getNode ( <STR_LIT> , DL , VT , Src , Neg ) ; } SDValue FloatVal = DAG . getNode ( <STR_LIT> , DL , FloatVT , Src ) ; EVT IntVT = FloatVT . changeVectorElementTypeToInteger ( ) ; SDValue Bitcast = DAG . getBitcast ( IntVT , FloatVal ) ; unsigned ShiftAmt = FloatEltVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , IntVT , Bitcast , DAG . getConstant ( ShiftAmt , DL , IntVT ) ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , VT , Shift ) ; unsigned ExponentBias = FloatEltVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , Trunc , DAG . getConstant ( ExponentBias , DL , VT ) ) ; unsigned Adjust = ExponentBias + ( EltSize - <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Adjust , DL , VT ) , Trunc ) ;"
LLVM,RISCV,2425,"Predict the next statement of this code snippet:
 <s> MVT FloatVT = <STR_LIT> ( FloatEltVT , VT . getVectorElementCount ( ) ) ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( FloatVT ) && <STR_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Src ) ; Src = DAG . getNode ( <STR_LIT> , DL , VT , Src , Neg ) ; } SDValue FloatVal = DAG . getNode ( <STR_LIT> , DL , FloatVT , Src ) ; EVT IntVT = FloatVT . changeVectorElementTypeToInteger ( ) ; SDValue Bitcast = DAG . getBitcast ( IntVT , FloatVal ) ;"
LLVM,RISCV,2426,"Predict the next statement of this code snippet:
 <s> static const int Table = ( int ( RoundingMode :: NearestTiesToEven ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardZero ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardNegative ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardPositive ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: NearestTiesToAway ) << <NUM_LIT> * <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RM , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;"
LLVM,RISCV,2427,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; SDValue Chain = Op -> getOperand ( <NUM_LIT> ) ; SDValue SysRegNo = DAG . getTargetConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; SDVTList VTs = DAG . getVTList ( XLenVT , <STR_LIT> ) ; SDValue RM = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , SysRegNo ) ;"
LLVM,RISCV,2428,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( BasePtr ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; if ( ! IsUnmasked ) Ops . push_back ( DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ) ;"
LLVM,RISCV,2429,"Predict the next statement of this code snippet:
 <s> SDValue SysRegNo = DAG . getTargetConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; static const unsigned Table = ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToEven ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardZero ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardNegative ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardPositive ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToAway ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;"
LLVM,RISCV,2430,"Predict the next statement of this code snippet:
 <s> SDValue RMValue = Op -> getOperand ( <NUM_LIT> ) ; SDValue SysRegNo = DAG . getTargetConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; static const unsigned Table = ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToEven ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardZero ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardNegative ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardPositive ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToAway ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ;"
LLVM,RISCV,2431,"Predict the next statement of this code snippet:
 <s> MVT OpVT = ScalarOp . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( ! OpVT . isScalarInteger ( ) || OpVT == XLenVT ) return SDValue ( ) ; if ( OpVT . bitsLT ( XLenVT ) ) { unsigned ExtOpc = isa < ConstantSDNode > ( ScalarOp ) ? <STR_LIT> : <STR_LIT> ; ScalarOp = DAG . getNode ( ExtOpc , DL , XLenVT , ScalarOp ) ; return DAG . getNode ( Op -> getOpcode ( ) , DL , Op -> getVTList ( ) , Operands ) ; } assert ( II -> SplatOperand > <NUM_LIT> && <STR_LIT> ) ; MVT VT = Op . getOperand ( SplatOp - <NUM_LIT> ) . getSimpleValueType ( ) ;"
LLVM,RISCV,2432,"Predict the next statement of this code snippet:
 <s> if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Op -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & OpIdx . value ( ) ) ;"
LLVM,RISCV,2433,"Predict the next statement of this code snippet:
 <s> if ( ! N0 -> hasOneUse ( ) || N0 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * N0C = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; auto * N1C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! N0C || ! N1C ) return SDValue ( ) ; int64_t C0 = N0C -> getSExtValue ( ) ; int64_t C1 = N1C -> getSExtValue ( ) ; int64_t CA , CB ; if ( C0 == - <NUM_LIT> || C0 == <NUM_LIT> || C0 == <NUM_LIT> || isInt < <NUM_LIT> > ( C1 ) ) return SDValue ( ) ; if ( ( C1 / C0 ) != <NUM_LIT> && isInt < <NUM_LIT> > ( C1 / C0 ) && isInt < <NUM_LIT> > ( C1 % C0 ) && ! isInt < <NUM_LIT> > ( C0 * ( C1 / C0 ) ) ) { CA = C1 / C0 ; CB = C1 % C0 ; } else if ( ( C1 / C0 + <NUM_LIT> ) != <NUM_LIT> && isInt < <NUM_LIT> > ( C1 / C0 + <NUM_LIT> ) && isInt < <NUM_LIT> > ( C1 % C0 - C0 ) && ! isInt < <NUM_LIT> > ( C0 * ( C1 / C0 + <NUM_LIT> ) ) ) { CA = C1 / C0 + <NUM_LIT> ; CB = C1 % C0 - C0 ; } else if ( ( C1 / C0 - <NUM_LIT> ) != <NUM_LIT> && isInt < <NUM_LIT> > ( C1 / C0 - <NUM_LIT> ) && isInt < <NUM_LIT> > ( C1 % C0 + C0 ) && ! isInt < <NUM_LIT> > ( C0 * ( C1 / C0 - <NUM_LIT> ) ) ) { CA = C1 / C0 - <NUM_LIT> ; CB = C1 % C0 + C0 ; } else return SDValue ( ) ;"
LLVM,RISCV,2434,"Predict the next statement of this code snippet:
 <s> if ( ! Subtarget . hasVInstructionsF16 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF32 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF64 ( ) ) return false ; break ; } if ( EltVT . getSizeInBits ( ) > Subtarget . getMaxELENForFixedLengthVectors ( ) ) return false ; unsigned LMul = divideCeil ( VT . getSizeInBits ( ) , MinVLen ) ;"
LLVM,RISCV,2435,"Predict the next statement of this code snippet:
 <s> if ( ! Subtarget . hasVInstructionsI64 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF16 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF32 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF64 ( ) ) return false ; break ; } if ( EltVT . getSizeInBits ( ) > Subtarget . getMaxELENForFixedLengthVectors ( ) ) return false ;"
LLVM,RISCV,2436,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ;"
LLVM,RISCV,2437,"Predict the next statement of this code snippet:
 <s> if ( RC == & <STR_LIT> ) { if ( FirstMaskArgument . hasValue ( ) && ValNo == FirstMaskArgument . getValue ( ) ) return State . AllocateReg ( <STR_LIT> ) ; return State . AllocateReg ( ArgVRs ) ; } if ( RC == & <STR_LIT> ) return State . AllocateReg ( ArgVRM2s ) ;"
LLVM,RISCV,2438,"Predict the next statement of this code snippet:
 <s> Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) FirstMaskArgument = preAssignMask ( Ins ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ArgVT = Ins [ i ] . VT ; <STR_LIT> ArgFlags = Ins [ i ] . Flags ; Type * ArgTy = nullptr ; if ( IsRet ) ArgTy = FType -> getReturnType ( ) ; else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ;"
LLVM,RISCV,2439,"Predict the next statement of this code snippet:
 <s> MVT ArgVT = Ins [ i ] . VT ; <STR_LIT> ArgFlags = Ins [ i ] . Flags ; Type * ArgTy = nullptr ; if ( IsRet ) ArgTy = FType -> getReturnType ( ) ; else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( Fn ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet , ArgTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << '\n' ) ; llvm_unreachable ( nullptr ) ; } }"
LLVM,RISCV,2440,"Predict the next statement of this code snippet:
 <s> MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; Type * OrigTy = CLI ? CLI -> getArgs ( ) [ Outs [ i ] . OrigArgIndex ] . Ty : nullptr ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( Fn ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy , * this , FirstMaskArgument ) ) {"
LLVM,RISCV,2441,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . hasStdExtV ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr , * this , FirstMaskArgument ) ) return false ; } return true ;"
LLVM,RISCV,2442,"Predict the next statement of this code snippet:
 <s> CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ;"
LLVM,RISCV,2443,"Predict the next statement of this code snippet:
 <s> PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } Register Reg ; unsigned StoreSizeBytes = XLen / <NUM_LIT> ; Align StackAlign = Align ( XLen / <NUM_LIT> ) ; if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR16s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR32s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s ) ; else if ( ValVT . isVector ( ) ) { Reg = allocateRVVReg ( ValVT , ValNo , FirstMaskArgument , State , TLI ) ; if ( ! Reg ) { if ( IsRet ) return true ; if ( ( Reg = State . AllocateReg ( ArgGPRs ) ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; } else if ( ValVT . isScalableVector ( ) ) { report_fatal_error ( <STR_LIT> ) ; } else { LocVT = ValVT ; StoreSizeBytes = ValVT . getStoreSize ( ) ; StackAlign = MaybeAlign ( ValVT . getScalarSizeInBits ( ) / <NUM_LIT> ) . valueOrOne ( ) ; } } } else { Reg = State . AllocateReg ( ArgGPRs ) ; } unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( StoreSizeBytes , StackAlign ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return false ; } assert ( ( ! UseGPRForF16_F32 || ! UseGPRForF64 || LocVT == XLenVT || ( TLI . getSubtarget ( ) . hasStdExtV ( ) && ValVT . isVector ( ) ) ) && <STR_LIT> ) ; if ( Reg ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ValVT . isFloatingPoint ( ) ) { LocVT = ValVT ; LocInfo = CCValAssign :: Full ;"
LLVM,RISCV,2444,"Predict the next statement of this code snippet:
 <s> State . addLoc ( CCValAssign :: getMem ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , State . AllocateStack ( XLenInBytes , StackAlign ) , VA1 . getLocVT ( ) , CCValAssign :: Full ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , Align ( XLenInBytes ) ) , LocVT2 , CCValAssign :: Full ) ) ; return false ; } if ( Register Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo2 , ValVT2 , Reg , LocVT2 , CCValAssign :: Full ) ) ; } else { State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , Align ( XLenInBytes ) ) , LocVT2 , CCValAssign :: Full ) ) ;"
LLVM,RISCV,2445,"Predict the next statement of this code snippet:
 <s> static const MCPhysReg GPRList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( GPRList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR16List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR16List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ;"
LLVM,RISCV,2446,"Predict the next statement of this code snippet:
 <s> static const MCPhysReg GPRList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( GPRList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) {"
LLVM,RISCV,2447,"Predict the next statement of this code snippet:
 <s> } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ;"
LLVM,RISCV,2448,"Predict the next statement of this code snippet:
 <s> if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; unsigned CombinedShAmt ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) CombinedShAmt = ShAmt1 | ShAmt2 ; else CombinedShAmt = ShAmt1 ^ ShAmt2 ; if ( CombinedShAmt == <NUM_LIT> ) return Src ; SDLoc DL ( N ) ; return DAG . getNode ( N -> getOpcode ( ) , DL , N -> getValueType ( <NUM_LIT> ) , Src , DAG . getConstant ( CombinedShAmt , DL , N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) ;"
LLVM,RISCV,2449,"Predict the next statement of this code snippet:
 <s> if ( Src . getOpcode ( ) != N -> getOpcode ( ) ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2450,"Predict the next statement of this code snippet:
 <s> SDValue VL = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOperand ( <NUM_LIT> ) != Mask || Op0 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDLoc DL ( N ) ; if ( Op0 . getOpcode ( ) == Op1 . getOpcode ( ) ) { if ( ! Op1 . hasOneUse ( ) ) return SDValue ( ) ; if ( Op1 . getOperand ( <NUM_LIT> ) != Mask || Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) {"
LLVM,RISCV,2451,"Predict the next statement of this code snippet:
 <s> if ( Op0 . getOpcode ( ) == Op1 . getOpcode ( ) ) { if ( ! Op1 . hasOneUse ( ) ) return SDValue ( ) ; if ( Op1 . getOperand ( <NUM_LIT> ) != Mask || Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) { if ( DAG . ComputeNumSignBits ( Op1 ) <= ( ScalarBits - NarrowSize ) ) return SDValue ( ) ; } else { APInt Mask = APInt :: getBitsSetFrom ( ScalarBits , NarrowSize ) ; if ( ! DAG . MaskedValueIsZero ( Op1 , Mask ) ) return SDValue ( ) ; } Op1 = DAG . getNode ( <STR_LIT> , DL , NarrowVT , Op1 , VL ) ; } else return SDValue ( ) ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ; unsigned ExtOpc = IsSignExt ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,2452,"Predict the next statement of this code snippet:
 <s> EVT VT = Op . getValueType ( ) ; if ( VT == Subtarget . getXLenVT ( ) || ( Subtarget . is64Bit ( ) && VT == <STR_LIT> ) ) { SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; auto MatchOROfReverse = [ & ] ( SDValue Reverse , SDValue X ) { if ( Reverse . getOpcode ( ) == <STR_LIT> && Reverse . getOperand ( <NUM_LIT> ) == X && isa < ConstantSDNode > ( Reverse . getOperand ( <NUM_LIT> ) ) && isPowerOf2_32 ( Reverse . getConstantOperandVal ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , X , Reverse . getOperand ( <NUM_LIT> ) ) ; if ( ( Reverse . getOpcode ( ) == <STR_LIT> || Reverse . getOpcode ( ) == <STR_LIT> ) && Reverse . getOperand ( <NUM_LIT> ) == X && isa < ConstantSDNode > ( Reverse . getOperand ( <NUM_LIT> ) ) ) { uint64_t RotAmt = Reverse . getConstantOperandVal ( <NUM_LIT> ) ; if ( RotAmt == ( VT . getSizeInBits ( ) / <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( RotAmt , DL , VT ) ) ; } return SDValue ( ) ; } ; if ( SDValue V = MatchOROfReverse ( Op0 , Op1 ) ) return V ; if ( SDValue V = MatchOROfReverse ( Op1 , Op0 ) ) return V ; if ( Op0 . getOpcode ( ) != <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue OrOp0 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue OrOp1 = Op0 . getOperand ( <NUM_LIT> ) ; auto LHS = matchGREVIPat ( OrOp0 ) ; if ( ! LHS ) { std :: swap ( OrOp0 , OrOp1 ) ; LHS = matchGREVIPat ( OrOp0 ) ; } auto RHS = matchGREVIPat ( Op1 ) ; if ( LHS && RHS && LHS -> formsPairWith ( * RHS ) && LHS -> Op == OrOp1 ) {"
LLVM,RISCV,2453,"Predict the next statement of this code snippet:
 <s> auto LHS = matchGREVIPat ( Op . getOperand ( <NUM_LIT> ) ) ; auto RHS = matchGREVIPat ( Op . getOperand ( <NUM_LIT> ) ) ; if ( LHS && RHS && LHS -> formsPairWith ( * RHS ) ) { SDLoc DL ( Op ) ;"
LLVM,RISCV,2454,"Predict the next statement of this code snippet:
 <s> if ( ( Slct . getOpcode ( ) != <STR_LIT> && Slct . getOpcode ( ) != <STR_LIT> ) || ! Slct . hasOneUse ( ) ) return SDValue ( ) ; auto isZeroOrAllOnes = [ ] ( SDValue N , bool AllOnes ) { return AllOnes ? isAllOnesConstant ( N ) : isNullConstant ( N ) ; } ; bool SwapSelectOps ; unsigned OpOffset = Slct . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue TrueVal = Slct . getOperand ( <NUM_LIT> + OpOffset ) ; SDValue FalseVal = Slct . getOperand ( <NUM_LIT> + OpOffset ) ; SDValue NonConstantVal ; if ( isZeroOrAllOnes ( TrueVal , AllOnes ) ) { SwapSelectOps = false ; NonConstantVal = FalseVal ; } else if ( isZeroOrAllOnes ( FalseVal , AllOnes ) ) { SwapSelectOps = true ; NonConstantVal = TrueVal ;"
LLVM,RISCV,2455,"Predict the next statement of this code snippet:
 <s> static SDValue combineSelectAndUseCommutative ( SDNode * N , SelectionDAG & DAG , bool AllOnes ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2456,"Predict the next statement of this code snippet:
 <s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue Result = combineSelectAndUse ( N , N0 , N1 , DAG , AllOnes ) ) return Result ;"
LLVM,RISCV,2457,"Predict the next statement of this code snippet:
 <s> if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ;"
LLVM,RISCV,2458,"Predict the next statement of this code snippet:
 <s> if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ;"
LLVM,RISCV,2459,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: udiv ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleTZ = Known2 . trunc ( <NUM_LIT> ) . countMaxTrailingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleTZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleLZ = Known2 . trunc ( <NUM_LIT> ) . countMaxLeadingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleLZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( auto * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Opc == <STR_LIT> ) Known = Known . trunc ( <NUM_LIT> ) ; unsigned ShAmt = C -> getZExtValue ( ) ; computeGREV ( Known . Zero , ShAmt ) ; computeGREV ( Known . One , ShAmt ) ;"
LLVM,RISCV,2460,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : { if ( Op . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && ( Op . getConstantOperandVal ( <NUM_LIT> ) & <NUM_LIT> ) == <NUM_LIT> ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp > <NUM_LIT> ) return <NUM_LIT> ; } break ; } case <STR_LIT> : if ( Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) > Subtarget . getXLen ( ) ) return <NUM_LIT> ; return Subtarget . getXLen ( ) - Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) + <NUM_LIT> ;"
LLVM,RISCV,2461,"Predict the next statement of this code snippet:
 <s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; assert ( V . getValueType ( ) . isScalableVector ( ) && <STR_LIT> ) ;"
LLVM,RISCV,2462,"Predict the next statement of this code snippet:
 <s> case CCValAssign :: Full : if ( VA . getValVT ( ) . isFixedLengthVector ( ) && VA . getLocVT ( ) . isScalableVector ( ) ) Val = convertFromScalableVector ( VA . getValVT ( ) , Val , DAG , Subtarget ) ; break ; case CCValAssign :: BCvt : if ( VA . getLocVT ( ) . isInteger ( ) && VA . getValVT ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; else if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; else Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ;"
LLVM,RISCV,2463,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,RISCV,2464,"Predict the next statement of this code snippet:
 <s> bool convertSelectOfConstantsToMath ( EVT VT ) const override { return true ;"
LLVM,RISCV,2465,"Predict the next statement of this code snippet:
 <s> assert ( V . getValueType ( ) . isFixedLengthVector ( ) && <STR_LIT> ) ; SDLoc DL ( V ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , V , Zero ) ;"
LLVM,RISCV,2466,"Predict the next statement of this code snippet:
 <s> assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; assert ( V . getValueType ( ) . isFixedLengthVector ( ) && <STR_LIT> ) ;"
LLVM,RISCV,2467,"Predict the next statement of this code snippet:
 <s> static SDValue convertValVTToLocVT ( SelectionDAG & DAG , SDValue Val , const CCValAssign & VA , const SDLoc & DL , const <ISA_LIT>Subtarget & Subtarget ) { EVT LocVT = VA . getLocVT ( ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( VA . getValVT ( ) . isFixedLengthVector ( ) && LocVT . isScalableVector ( ) ) Val = convertToScalableVector ( LocVT , Val , DAG , Subtarget ) ; break ; case CCValAssign :: BCvt :"
LLVM,RISCV,2468,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( N ) ; <STR_LIT> WOpcode = get<ISA_LIT>WOpcode ( N -> getOpcode ( ) ) ; SDValue NewOp0 = DAG . getNode ( ExtOpc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewOp1 = DAG . getNode ( ExtOpc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewRes = DAG . getNode ( WOpcode , DL , <STR_LIT> , NewOp0 , NewOp1 ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , NewRes ) ;"
LLVM,RISCV,2469,"Predict the next statement of this code snippet:
 <s> SDValue NewOp0 = DAG . getNode ( ExtOpc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewOp1 = DAG . getNode ( ExtOpc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewRes = DAG . getNode ( WOpcode , DL , <STR_LIT> , NewOp0 , NewOp1 ) ;"
LLVM,RISCV,2470,"Predict the next statement of this code snippet:
 <s> SDValue NewWOp = DAG . getNode ( N -> getOpcode ( ) , DL , <STR_LIT> , NewOp0 , NewOp1 ) ;"
LLVM,RISCV,2471,"Predict the next statement of this code snippet:
 <s> SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewOp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewWOp = DAG . getNode ( N -> getOpcode ( ) , DL , <STR_LIT> , NewOp0 , NewOp1 ) ;"
LLVM,RISCV,2472,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . hasStdExtZba ( ) && ! Imm . isSignedIntN ( <NUM_LIT> ) && ( ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( <NUM_LIT> ) && Imm . countTrailingZeros ( ) < <NUM_LIT> ) { APInt ImmS = Imm . ashr ( Imm . countTrailingZeros ( ) ) ; if ( ( ImmS + <NUM_LIT> ) . isPowerOf2 ( ) || ( ImmS - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - ImmS ) . isPowerOf2 ( ) ) return true ; } }"
LLVM,RISCV,2473,"Predict the next statement of this code snippet:
 <s> if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) { const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - Imm ) . isPowerOf2 ( ) || ( - <NUM_LIT> - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtZba ( ) && ! Imm . isSignedIntN ( <NUM_LIT> ) && ( ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( <NUM_LIT> ) && Imm . countTrailingZeros ( ) < <NUM_LIT> ) { APInt ImmS = Imm . ashr ( Imm . countTrailingZeros ( ) ) ; if ( ( ImmS + <NUM_LIT> ) . isPowerOf2 ( ) || ( ImmS - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - ImmS ) . isPowerOf2 ( ) ) return true ; } } } return false ;"
LLVM,RISCV,2474,"Predict the next statement of this code snippet:
 <s> unsigned SubRegClassID = getRegClassIDForVecVT ( SubVecVT ) ; unsigned SubRegIdx = <STR_LIT> ; for ( const unsigned RCID : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( VecRegClassID > RCID && SubRegClassID <= RCID ) { VecVT = VecVT . getHalfNumVectorElementsVT ( ) ;"
LLVM,RISCV,2475,"Predict the next statement of this code snippet:
 <s> std :: pair < unsigned , unsigned > <ISA_LIT>TargetLowering :: decomposeSubvectorInsertExtractToSubRegs ( MVT VecVT , MVT SubVecVT , unsigned InsertExtractIdx , const <ISA_LIT>RegisterInfo * TRI ) { static_assert ( ( <STR_LIT> > <STR_LIT> && <STR_LIT> > <STR_LIT> && <STR_LIT> > <STR_LIT> ) , <STR_LIT> ) ;"
LLVM,RISCV,2476,"Predict the next statement of this code snippet:
 <s> Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( MF ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMOLo = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; MachineMemOperand * MMOHi = MF . getMachineMemOperand ( MPI . getWithOffset ( <NUM_LIT> ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2477,"Predict the next statement of this code snippet:
 <s> if ( isa < LoadInst > ( Inst ) && Ord == AtomicOrdering :: SequentiallyConsistent ) return Builder . CreateFence ( Ord ) ; if ( isa < StoreInst > ( Inst ) && isReleaseOrStronger ( Ord ) ) return Builder . CreateFence ( AtomicOrdering :: Release ) ; return nullptr ;"
LLVM,RISCV,2478,"Predict the next statement of this code snippet:
 <s> Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ;"
LLVM,RISCV,2479,"Predict the next statement of this code snippet:
 <s> Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; <STR_LIT> CmpXchgIntrID = <STR_LIT> ; if ( XLen == <NUM_LIT> ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = <STR_LIT> ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ;"
LLVM,RISCV,2480,"Predict the next statement of this code snippet:
 <s> Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , HiReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , LoReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ReadAgainReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( HiReg ) . addReg ( ReadAgainReg ) . addMBB ( LoopMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; MI . eraseFromParent ( ) ; return DoneMBB ;"
LLVM,RISCV,2481,"Predict the next statement of this code snippet:
 <s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * LoopMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MF . insert ( It , LoopMBB ) ; MachineBasicBlock * DoneMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MF . insert ( It , DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; DoneMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopMBB ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; Register ReadAgainReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ;"
LLVM,RISCV,2482,"Predict the next statement of this code snippet:
 <s> SequenceMBBI != E ; ++ SequenceMBBI ) { if ( SequenceMBBI -> isDebugInstr ( ) ) continue ; else if ( isSelectPseudo ( * SequenceMBBI ) ) { if ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != LHS || SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != RHS || SequenceMBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) != CC || SelectDests . count ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) || SelectDests . count ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) break ; LastSelectPseudo = & * SequenceMBBI ; SequenceMBBI -> collectDebugValues ( SelectDebugValues ) ; SelectDests . insert ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else { if ( SequenceMBBI -> hasUnmodeledSideEffects ( ) || SequenceMBBI -> mayLoadOrStore ( ) ) break ; if ( llvm :: any_of ( SequenceMBBI -> operands ( ) , [ & ] ( MachineOperand & MO ) { return MO . isReg ( ) && MO . isUse ( ) && SelectDests . count ( MO . getReg ( ) ) ; } ) ) break ; } } const <ISA_LIT>InstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; for ( MachineInstr * DebugInstr : SelectDebugValues ) { TailMBB -> push_back ( DebugInstr -> removeFromParent ( ) ) ; } TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; BuildMI ( HeadMBB , DL , TII . getBrCond ( CC ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( TailMBB ) ; IfFalseMBB -> addSuccessor ( TailMBB ) ; auto SelectMBBI = MI . getIterator ( ) ; auto SelectEnd = std :: next ( LastSelectPseudo -> getIterator ( ) ) ; auto InsertionPoint = TailMBB -> begin ( ) ; while ( SelectMBBI != SelectEnd ) { auto Next = std :: next ( SelectMBBI ) ;"
LLVM,RISCV,2483,"Predict the next statement of this code snippet:
 <s> MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMOLo = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; MachineMemOperand * MMOHi = MF . getMachineMemOperand ( MPI . getWithOffset ( <NUM_LIT> ) , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOLo ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOHi ) ; MI . eraseFromParent ( ) ;"
LLVM,RISCV,2484,"Predict the next statement of this code snippet:
 <s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( MF ) ;"
LLVM,RISCV,2485,"Predict the next statement of this code snippet:
 <s> if ( isa < LoadInst > ( Inst ) && isAcquireOrStronger ( Ord ) ) return Builder . CreateFence ( AtomicOrdering :: Acquire ) ; return nullptr ;"
LLVM,RISCV,2486,"Predict the next statement of this code snippet:
 <s> Instruction * <ISA_LIT>TargetLowering :: emitTrailingFence ( IRBuilderBase & Builder , Instruction * Inst , AtomicOrdering Ord ) const {"
LLVM,RISCV,2487,"Predict the next statement of this code snippet:
 <s> SDValue L = DAG . getLoad ( NewVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getPointerInfo ( ) , Load -> getOriginalAlign ( ) , Load -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getMergeValues ( { DAG . getBitcast ( VT , L ) , L . getValue ( <NUM_LIT> ) } , DL ) ;"
LLVM,RISCV,2488,"Predict the next statement of this code snippet:
 <s> MVT NewVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * ( EltSizeBits / <NUM_LIT> ) ) ; assert ( NewVT . isValid ( ) && <STR_LIT> ) ; SDValue L = DAG . getLoad ( NewVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getPointerInfo ( ) , Load -> getOriginalAlign ( ) , Load -> getMemOperand ( ) -> getFlags ( ) ) ;"
LLVM,RISCV,2489,"Predict the next statement of this code snippet:
 <s> assert ( Store && Store -> getValue ( ) . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; if ( allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , Store -> getMemoryVT ( ) , * Store -> getMemOperand ( ) ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue StoredVal = Store -> getValue ( ) ; MVT VT = StoredVal . getSimpleValueType ( ) ; unsigned EltSizeBits = VT . getScalarSizeInBits ( ) ; assert ( ( EltSizeBits == <NUM_LIT> || EltSizeBits == <NUM_LIT> || EltSizeBits == <NUM_LIT> ) && <STR_LIT> ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * ( EltSizeBits / <NUM_LIT> ) ) ; assert ( NewVT . isValid ( ) && <STR_LIT> ) ; StoredVal = DAG . getBitcast ( NewVT , StoredVal ) ;"
LLVM,RISCV,2490,"Predict the next statement of this code snippet:
 <s> SDValue Addr = getTargetNode ( N , DL , Ty , DAG , <NUM_LIT> ) ; if ( IsLocal ) return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; } switch ( getTargetMachine ( ) . getCodeModel ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case CodeModel :: Small : { SDValue AddrHi = getTargetNode ( N , DL , Ty , DAG , <STR_LIT> ) ; SDValue AddrLo = getTargetNode ( N , DL , Ty , DAG , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , AddrLo ) , <NUM_LIT> ) ; } case CodeModel :: Medium : { SDValue Addr = getTargetNode ( N , DL , Ty , DAG , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ;"
LLVM,RISCV,2491,"Predict the next statement of this code snippet:
 <s> case 'I' : case 'J' : case 'K' : return C_Immediate ; case 'A' : return C_Memory ; case 'S' : return C_Other ; } } else { if ( Constraint == <STR_LIT> || Constraint == <STR_LIT> ) return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ;"
LLVM,RISCV,2492,"Predict the next statement of this code snippet:
 <s> assert ( VecVT . isScalableVector ( ) && <STR_LIT> ) ; return getDefaultVLOps ( VecVT , VecVT , DL , DAG , Subtarget ) ;"
LLVM,RISCV,2493,"Predict the next statement of this code snippet:
 <s> static std :: pair < SDValue , SDValue > getDefaultScalableVLOps ( MVT VecVT , SDLoc DL , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( VecVT . isScalableVector ( ) && <STR_LIT> ) ; return getDefaultVLOps ( VecVT , VecVT , DL , DAG , Subtarget ) ;"
LLVM,RISCV,2494,"Predict the next statement of this code snippet:
 <s> assert ( ContainerVT . isScalableVector ( ) && <STR_LIT> ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ;"
LLVM,RISCV,2495,"Predict the next statement of this code snippet:
 <s> Entry . Ty = CallTy ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ;"
LLVM,RISCV,2496,"Predict the next statement of this code snippet:
 <s> const GlobalValue * GV = N -> getGlobal ( ) ; SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Load ; Entry . Ty = CallTy ; Args . push_back ( Entry ) ;"
LLVM,RISCV,2497,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const {"
LLVM,RISCV,2498,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return <STR_LIT> ;"
LLVM,RISCV,2499,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const {"
LLVM,RISCV,2500,"Predict the next statement of this code snippet:
 <s> <STR_LIT> getExtendForAtomicCmpSwapArg ( ) const override { return <STR_LIT> ;"
LLVM,RISCV,2501,"Predict the next statement of this code snippet:
 <s> <STR_LIT> getExtendForAtomicOps ( ) const override {"
LLVM,RISCV,2502,"Predict the next statement of this code snippet:
 <s> <STR_LIT> getExtendForAtomicOps ( ) const override {"
LLVM,RISCV,2503,"Predict the next statement of this code snippet:
 <s> if ( ConstraintCode . size ( ) == <NUM_LIT> ) { switch ( ConstraintCode [ <NUM_LIT> ] ) {"
LLVM,RISCV,2504,"Predict the next statement of this code snippet:
 <s> unsigned KnownSize = VT . getSizeInBits ( ) . getKnownMinValue ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) KnownSize *= <NUM_LIT> ; switch ( KnownSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return <STR_LIT> :: LMUL_F8 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_F4 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_F2 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_1 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_2 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_4 ; case <NUM_LIT> :"
LLVM,RISCV,2505,"Predict the next statement of this code snippet:
 <s> assert ( VT . getVectorElementType ( ) . getSizeInBits ( ) <= <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,2506,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const {"
LLVM,RISCV,2507,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :: LMUL_F8 : case <STR_LIT> :: LMUL_F4 : case <STR_LIT> :: LMUL_F2 : case <STR_LIT> :: LMUL_1 : return <STR_LIT> ; case <STR_LIT> :: LMUL_2 : return <STR_LIT> ; case <STR_LIT> :: LMUL_4 : return <STR_LIT> ; case <STR_LIT> :: LMUL_8 : return <STR_LIT> ;"
LLVM,RISCV,2508,"Predict the next statement of this code snippet:
 <s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return <STR_LIT> ; return getRegClassIDForLMUL ( getLMUL ( VT ) ) ;"
LLVM,RISCV,2509,"Predict the next statement of this code snippet:
 <s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return <STR_LIT> ;"
LLVM,RISCV,2510,"Predict the next statement of this code snippet:
 <s> if ( Reg == <STR_LIT> ) Reg = MatchRegisterName ( RegName ) ; if ( Reg == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ;"
LLVM,RISCV,2511,"Predict the next statement of this code snippet:
 <s> if ( ! ReservedRegs . test ( Reg ) && ! Subtarget . isRegisterReservedByUser ( Reg ) ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; return Reg ;"
LLVM,RISCV,2512,"Predict the next statement of this code snippet:
 <s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const {"
LLVM,RISCV,2513,"Predict the next statement of this code snippet:
 <s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfh ( ) ) return <STR_LIT> ;"
LLVM,RISCV,2514,"Predict the next statement of this code snippet:
 <s> static SDValue getRVVFPExtendOrRound ( SDValue Op , MVT VT , MVT ContainerVT , SDLoc DL , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( VT . isScalableVector ( ) ) return DAG . getFPExtendOrRound ( Op , DL , VT ) ; assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; SDValue Mask , VL ;"
LLVM,RISCV,2515,"Predict the next statement of this code snippet:
 <s> switch ( ISDOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,2516,"Predict the next statement of this code snippet:
 <s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ;"
LLVM,RISCV,2517,"Predict the next statement of this code snippet:
 <s> } SDValue AddrHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrAdd = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrLo = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ;"
LLVM,RISCV,2518,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; const GlobalValue * GV = N -> getGlobal ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( UseGOT ) { SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load , TPReg ) ; } SDValue AddrHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrAdd = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrLo = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ;"
LLVM,RISCV,2519,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>TargetLowering :: getSubregIndexByMVT ( MVT VT , unsigned Index ) { <STR_LIT> LMUL = getLMUL ( VT ) ; if ( LMUL == <STR_LIT> :: LMUL_F8 || LMUL == <STR_LIT> :: LMUL_F4 || LMUL == <STR_LIT> :: LMUL_F2 || LMUL == <STR_LIT> :: LMUL_1 ) { static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,2520,"Predict the next statement of this code snippet:
 <s> static SDValue getTargetNode ( JumpTableSDNode * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned Flags ) {"
LLVM,RISCV,2521,"Predict the next statement of this code snippet:
 <s> Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = getValueType ( DL , I . getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOStore ;"
LLVM,RISCV,2522,"Predict the next statement of this code snippet:
 <s> return Subtarget . getXLenVT ( ) ;"
LLVM,RISCV,2523,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: hasBitPreservingFPLogic ( EVT VT ) const { return ( VT == <STR_LIT> && Subtarget . hasStdExtZfh ( ) ) || ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) ) || ( VT == <STR_LIT> && Subtarget . hasStdExtD ( ) ) ;"
LLVM,RISCV,2524,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz ( ) const {"
LLVM,RISCV,2525,"Predict the next statement of this code snippet:
 <s> return Subtarget . hasStdExtZbb ( ) ;"
LLVM,RISCV,2526,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCttz ( ) const {"
LLVM,RISCV,2527,"Predict the next statement of this code snippet:
 <s> APInt ShiftedC1Int = C1Int << C2 -> getAPIntValue ( ) ; if ( ShiftedC1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( C1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . getFeatureBits ( ) , true ) ; int ShiftedC1Cost = <STR_LIT> ( ShiftedC1Int , Ty . getSizeInBits ( ) , Subtarget . getFeatureBits ( ) , true ) ; if ( C1Cost < ShiftedC1Cost ) return false ; } } return true ;"
LLVM,RISCV,2528,"Predict the next statement of this code snippet:
 <s> auto * C2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( C1 && C2 ) { const APInt & C1Int = C1 -> getAPIntValue ( ) ; APInt ShiftedC1Int = C1Int << C2 -> getAPIntValue ( ) ; if ( ShiftedC1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ;"
LLVM,RISCV,2529,"Predict the next statement of this code snippet:
 <s> auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; }"
LLVM,RISCV,2530,"Predict the next statement of this code snippet:
 <s> auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ;"
LLVM,RISCV,2531,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return Subtarget . hasStdExtZfh ( ) ; case <STR_LIT> : return Subtarget . hasStdExtF ( ) ; case <STR_LIT> : return Subtarget . hasStdExtD ( ) ;"
LLVM,RISCV,2532,"Predict the next statement of this code snippet:
 <s> if ( VT == <STR_LIT> && ! Subtarget . hasStdExtZfh ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ;"
LLVM,RISCV,2533,"Predict the next statement of this code snippet:
 <s> if ( ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) ) return true ; if ( ScalarTy -> isHalfTy ( ) ) return Subtarget . hasStdExtZfh ( ) ; if ( ScalarTy -> isFloatTy ( ) ) return Subtarget . hasStdExtF ( ) ; if ( ScalarTy -> isDoubleTy ( ) ) return Subtarget . hasStdExtD ( ) ;"
LLVM,RISCV,2534,"Predict the next statement of this code snippet:
 <s> if ( VT . getScalarSizeInBits ( ) > Subtarget . getXLen ( ) ) return true ; ConstantSDNode * C1Node = cast < ConstantSDNode > ( AddNode . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * C2Node = cast < ConstantSDNode > ( ConstNode ) ; const APInt & C1 = C1Node -> getAPIntValue ( ) ; const APInt & C2 = C2Node -> getAPIntValue ( ) ; if ( C1 . isSignedIntN ( <NUM_LIT> ) && ! ( C1 * C2 ) . isSignedIntN ( <NUM_LIT> ) ) return false ;"
LLVM,RISCV,2535,"Predict the next statement of this code snippet:
 <s> if ( ShuffleVectorSDNode :: isSplatMask ( M . data ( ) , VT ) ) return true ;"
LLVM,RISCV,2536,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( ShuffleVectorSDNode :: isSplatMask ( M . data ( ) , VT ) ) return true ;"
LLVM,RISCV,2537,"Predict the next statement of this code snippet:
 <s> if ( ! SeqStepNum ) SeqStepNum = ValDiff ; else if ( ValDiff != SeqStepNum ) return None ; if ( ! SeqStepDenom ) SeqStepDenom = IdxDiff ; else if ( IdxDiff != * SeqStepDenom ) return None ; } } if ( SeqStepNum && SeqStepDenom ) { uint64_t ExpectedVal = ( int64_t ) ( Idx * ( uint64_t ) * SeqStepNum ) / * SeqStepDenom ; int64_t Addend = SignExtend64 ( Val - ExpectedVal , EltSizeInBits ) ; if ( ! SeqAddend ) SeqAddend = Addend ; else if ( SeqAddend != Addend ) return None ; }"
LLVM,RISCV,2538,"Predict the next statement of this code snippet:
 <s> if ( IsABIRegCopy && ValueVT == <STR_LIT> && PartVT == <STR_LIT> ) { SDValue Val = Parts [ <NUM_LIT> ] ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; return Val ; } if ( ValueVT . isScalableVector ( ) && PartVT . isScalableVector ( ) ) { LLVMContext & Context = * DAG . getContext ( ) ; SDValue Val = Parts [ <NUM_LIT> ] ; EVT ValueEltVT = ValueVT . getVectorElementType ( ) ; EVT PartEltVT = PartVT . getVectorElementType ( ) ; unsigned ValueVTBitSize = ValueVT . getSizeInBits ( ) . getKnownMinSize ( ) ; unsigned PartVTBitSize = PartVT . getSizeInBits ( ) . getKnownMinSize ( ) ; if ( PartVTBitSize % ValueVTBitSize == <NUM_LIT> ) { EVT SameEltTypeVT = ValueVT ; if ( ValueEltVT != PartEltVT ) { unsigned Count = ValueVTBitSize / PartEltVT . getSizeInBits ( ) ; assert ( Count != <NUM_LIT> && <STR_LIT> ) ; SameEltTypeVT = EVT :: getVectorVT ( Context , PartEltVT , Count , true ) ; } Val = DAG . getNode ( <STR_LIT> , DL , SameEltTypeVT , Val , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; if ( ValueEltVT != PartEltVT ) Val = DAG . getNode ( <STR_LIT> , DL , ValueVT , Val ) ; return Val ;"
LLVM,RISCV,2539,"Predict the next statement of this code snippet:
 <s> SDValue SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; SDValue NegX = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatZero , X , Mask , VL ) ; SDValue Max = DAG . getNode ( <STR_LIT> , DL , ContainerVT , X , NegX , Mask , VL ) ; return convertFromScalableVector ( VT , Max , DAG , Subtarget ) ;"
LLVM,RISCV,2540,"Predict the next statement of this code snippet:
 <s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; X = convertToScalableVector ( ContainerVT , X , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; SDValue NegX = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatZero , X , Mask , VL ) ;"
LLVM,RISCV,2541,"Predict the next statement of this code snippet:
 <s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ;"
LLVM,RISCV,2542,"Predict the next statement of this code snippet:
 <s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ;"
LLVM,RISCV,2543,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ;"
LLVM,RISCV,2544,"Predict the next statement of this code snippet:
 <s> MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } SDValue Mask = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) . first ; SDValue VL = DAG . getConstant ( SubVecVT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue SlidedownAmt = DAG . getConstant ( OrigIdx , DL , XLenVT ) ; SDValue Slidedown = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Vec , SlidedownAmt , Mask , VL ) ; Slidedown = DAG . getNode ( <STR_LIT> , DL , SubVecVT , Slidedown , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; return DAG . getBitcast ( Op . getValueType ( ) , Slidedown ) ; } unsigned SubRegIdx , RemIdx ; std :: tie ( SubRegIdx , RemIdx ) = <ISA_LIT>TargetLowering :: decomposeSubvectorInsertExtractToSubRegs ( VecVT , SubVecVT , OrigIdx , TRI ) ; if ( RemIdx == <NUM_LIT> ) return Op ; MVT InterSubVT = VecVT ; if ( VecVT . bitsGT ( getLMUL1VT ( VecVT ) ) ) { InterSubVT = getLMUL1VT ( VecVT ) ; Vec = DAG . getNode ( <STR_LIT> , DL , InterSubVT , Vec , DAG . getConstant ( OrigIdx - RemIdx , DL , XLenVT ) ) ; } SDValue SlidedownAmt = DAG . getConstant ( RemIdx , DL , XLenVT ) ; SlidedownAmt = DAG . getNode ( <STR_LIT> , DL , XLenVT , SlidedownAmt ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultScalableVLOps ( InterSubVT , DL , DAG , Subtarget ) ; SDValue Slidedown = DAG . getNode ( <STR_LIT> , DL , InterSubVT , DAG . getUNDEF ( InterSubVT ) , Vec , SlidedownAmt , Mask , VL ) ;"
LLVM,RISCV,2545,"Predict the next statement of this code snippet:
 <s> SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT EltVT = Op . getValueType ( ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( VecVT . getVectorElementType ( ) == <STR_LIT> ) { MVT WideVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; return DAG . getNode ( <STR_LIT> , DL , EltVT , Vec , Idx ) ;"
LLVM,RISCV,2546,"Predict the next statement of this code snippet:
 <s> SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Ext = DAG . getNode ( ExtendOpc , DL , ContainerExtVT , Op1 , Mask , VL ) ; return convertFromScalableVector ( ExtVT , Ext , DAG , Subtarget ) ;"
LLVM,RISCV,2547,"Predict the next statement of this code snippet:
 <s> MVT ExtVT = Op . getSimpleValueType ( ) ; if ( ! ExtVT . isFixedLengthVector ( ) ) return Op ; MVT VT = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT ContainerExtVT = getContainerForFixedLengthVector ( ExtVT ) ; MVT ContainerVT = <STR_LIT> ( VT . getVectorElementType ( ) , ContainerExtVT . getVectorElementCount ( ) ) ; SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ;"
LLVM,RISCV,2548,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorFCOPYSIGNToRVV ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue Mag = Op . getOperand ( <NUM_LIT> ) ; SDValue Sign = Op . getOperand ( <NUM_LIT> ) ; assert ( Mag . getValueType ( ) == Sign . getValueType ( ) && <STR_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; Mag = convertToScalableVector ( ContainerVT , Mag , DAG , Subtarget ) ; Sign = convertToScalableVector ( ContainerVT , Sign , DAG , Subtarget ) ;"
LLVM,RISCV,2549,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorLoadToRVV ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; auto * Load = cast < LoadSDNode > ( Op ) ; assert ( allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , Load -> getMemoryVT ( ) , * Load -> getMemOperand ( ) ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue NewLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , { Load -> getChain ( ) , Load -> getBasePtr ( ) , VL } , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Result = convertFromScalableVector ( VT , NewLoad , DAG , Subtarget ) ;"
LLVM,RISCV,2550,"Predict the next statement of this code snippet:
 <s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return lowerToScalableOp ( Op , DAG , MaskOpc , false ) ;"
LLVM,RISCV,2551,"Predict the next statement of this code snippet:
 <s> SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDValue Op2 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Select = DAG . getNode ( <STR_LIT> , DL , ContainerVT , CC , Op1 , Op2 , VL ) ;"
LLVM,RISCV,2552,"Predict the next statement of this code snippet:
 <s> SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDValue Op2 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ;"
LLVM,RISCV,2553,"Predict the next statement of this code snippet:
 <s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , VL ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , MaskVT , Op1 , Op2 , Op . getOperand ( <NUM_LIT> ) , Mask , VL ) ;"
LLVM,RISCV,2554,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorShiftToRVV ( SDValue Op , SelectionDAG & DAG ) const { unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ;"
LLVM,RISCV,2555,"Predict the next statement of this code snippet:
 <s> } MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDValue NewValue = convertToScalableVector ( ContainerVT , StoreVal , DAG , Subtarget ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , { Store -> getChain ( ) , NewValue , Store -> getBasePtr ( ) , VL } , Store -> getMemoryVT ( ) , Store -> getMemOperand ( ) ) ;"
LLVM,RISCV,2556,"Predict the next statement of this code snippet:
 <s> SDValue StoreVal = Store -> getValue ( ) ; MVT VT = StoreVal . getSimpleValueType ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && VT . getVectorNumElements ( ) < <NUM_LIT> ) { VT = <STR_LIT> ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , StoreVal , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDValue NewValue = convertToScalableVector ( ContainerVT , StoreVal , DAG , Subtarget ) ;"
LLVM,RISCV,2557,"Predict the next statement of this code snippet:
 <s> default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : break ; case CallingConv :: GHC : if ( ! MF . getSubtarget ( ) . getFeatureBits ( ) [ <STR_LIT> ] || ! MF . getSubtarget ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) report_fatal_error ( <STR_LIT> ) ; } const Function & Func = MF . getFunction ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { if ( ! Func . arg_empty ( ) ) report_fatal_error ( <STR_LIT> ) ; StringRef Kind = MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( ! ( Kind == <STR_LIT> || Kind == <STR_LIT> || Kind == <STR_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; } EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; unsigned XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; if ( CallConv == CallingConv :: GHC ) CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_GHC ) ; else analyzeInputArgs ( MF , CCInfo , Ins , false , CallConv == CallingConv :: Fast ? CC_<ISA_LIT>_FastCC : CC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) ArgValue = unpackF64OnRV32DSoftABI ( DAG , Chain , VA , DL ) ; else if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL , * this ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; unsigned ArgPartOffset = Ins [ i ] . PartOffset ; assert ( VA . getValVT ( ) . isVector ( ) || ArgPartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset - ArgPartOffset ; SDValue Offset = DAG . getIntPtrConstant ( PartOffset , DL ) ; if ( PartVA . getValVT ( ) . isScalableVector ( ) ) Offset = DAG . getNode ( <STR_LIT> , DL , XLenVT , Offset ) ;"
LLVM,RISCV,2558,"Predict the next statement of this code snippet:
 <s> MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; VectorVal = convertToScalableVector ( ContainerVT , VectorVal , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( VectorVal . getSimpleValueType ( ) ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ScalarSplat = DAG . getSplatVector ( M1VT , DL , ScalarVal ) ;"
LLVM,RISCV,2559,"Predict the next statement of this code snippet:
 <s> else return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue FpToInt = DAG . getNode ( Opc , DL , DstVT , Src ) ; SDValue ZeroInt = DAG . getConstant ( <NUM_LIT> , DL , DstVT ) ;"
LLVM,RISCV,2560,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; Register FrameReg = RI . getFrameRegister ( MF ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ;"
LLVM,RISCV,2561,"Predict the next statement of this code snippet:
 <s> static const int Table = ( int ( RoundingMode :: NearestTiesToEven ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardZero ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardNegative ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardPositive ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: NearestTiesToAway ) << <NUM_LIT> * <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RM , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;"
LLVM,RISCV,2562,"Predict the next statement of this code snippet:
 <s> static const int Table = ( int ( RoundingMode :: NearestTiesToEven ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardZero ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardNegative ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardPositive ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: NearestTiesToAway ) << <NUM_LIT> * <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RM , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ; SDValue Masked = DAG . getNode ( <STR_LIT> , DL , XLenVT , Shifted , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; return DAG . getMergeValues ( { Masked , Chain } , DL ) ;"
LLVM,RISCV,2563,"Predict the next statement of this code snippet:
 <s> break ; case TLSModel :: InitialExec : Addr = getStaticTLSAddr ( N , DAG , true ) ; break ; case TLSModel :: LocalDynamic : case TLSModel :: GeneralDynamic : Addr = getDynamicTLSAddr ( N , DAG ) ; break ; } if ( Offset != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Ty , Addr , DAG . getConstant ( Offset , DL , XLenVT ) ) ;"
LLVM,RISCV,2564,"Predict the next statement of this code snippet:
 <s> ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; bool IsLegalInsert = Subtarget . is64Bit ( ) || Val . getValueType ( ) != <STR_LIT> ; if ( ! IsLegalInsert && isa < ConstantSDNode > ( Val ) ) { const auto * CVal = cast < ConstantSDNode > ( Val ) ; if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) { IsLegalInsert = true ; Val = DAG . getConstant ( CVal -> getSExtValue ( ) , DL , <STR_LIT> ) ; } } SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ValInVec ; if ( IsLegalInsert ) { unsigned Opc = VecVT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; if ( isNullConstant ( Idx ) ) { Vec = DAG . getNode ( Opc , DL , ContainerVT , Vec , Val , VL ) ; if ( ! VecVT . isFixedLengthVector ( ) ) return Vec ; return convertFromScalableVector ( VecVT , Vec , DAG , Subtarget ) ; } ValInVec = DAG . getNode ( Opc , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Val , VL ) ; } else { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ValLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , Zero ) ; SDValue ValHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , One ) ; MVT I32ContainerVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue I32Mask = getDefaultScalableVLOps ( I32ContainerVT , DL , DAG , Subtarget ) . first ; SDValue InsertI64VL = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; ValInVec = DAG . getNode ( <STR_LIT> , DL , I32ContainerVT , Zero , InsertI64VL ) ; ValInVec = DAG . getNode ( <STR_LIT> , DL , I32ContainerVT , ValInVec , ValHi , I32Mask , InsertI64VL ) ; ValInVec = DAG . getNode ( <STR_LIT> , DL , I32ContainerVT , ValInVec , ValLo , I32Mask , InsertI64VL ) ; ValInVec = DAG . getBitcast ( ContainerVT , ValInVec ) ;"
LLVM,RISCV,2565,"Predict the next statement of this code snippet:
 <s> Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Store = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Store -> getChain ( ) , IntID } ; Ops . push_back ( Val ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Store -> getVTList ( ) , Ops , Store -> getMemoryVT ( ) , Store -> getMemOperand ( ) ) ; } }"
LLVM,RISCV,2566,"Predict the next statement of this code snippet:
 <s> MVT VT = Op . getSimpleValueType ( ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; SDValue SplattedVal = splatSplitI64WithVL ( DL , VT , Scalar , VL , DAG ) ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , VL ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , VL ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; SDValue SelectCond = DAG . getNode ( <STR_LIT> , DL , MaskVT , VID , SplattedIdx , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectCond , SplattedVal , Vec , VL ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = Op . getNumOperands ( ) ; bool IsMasked = NumOps == <NUM_LIT> ; unsigned OpOffset = IsMasked ? <NUM_LIT> : <NUM_LIT> ; SDValue Scalar = Op . getOperand ( <NUM_LIT> + OpOffset ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) break ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( Scalar ) ) if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) break ; MVT VT = Op . getSimpleValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT I32VT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue Vec = DAG . getBitcast ( I32VT , Op . getOperand ( <NUM_LIT> + OpOffset ) ) ; SDValue ScalarLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue ScalarHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;"
LLVM,RISCV,2567,"Predict the next statement of this code snippet:
 <s> unsigned OpOffset = IsMasked ? <NUM_LIT> : <NUM_LIT> ; SDValue Scalar = Op . getOperand ( <NUM_LIT> + OpOffset ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) break ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( Scalar ) ) if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) break ; MVT VT = Op . getSimpleValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT I32VT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue Vec = DAG . getBitcast ( I32VT , Op . getOperand ( <NUM_LIT> + OpOffset ) ) ; SDValue ScalarLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue ScalarHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue VL = Op . getOperand ( NumOps - ( <NUM_LIT> + OpOffset ) ) ; SDValue I32VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , VL , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; MVT I32MaskVT = <STR_LIT> ( <STR_LIT> , I32VT . getVectorElementCount ( ) ) ; SDValue I32Mask = DAG . getNode ( <STR_LIT> , DL , I32MaskVT , VL ) ; if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec , ScalarHi , I32Mask , I32VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec , ScalarLo , I32Mask , I32VL ) ; } else { Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec , ScalarLo , I32Mask , I32VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec , ScalarHi , I32Mask , I32VL ) ; } Vec = DAG . getBitcast ( VT , Vec ) ; if ( ! IsMasked ) return Vec ; SDValue Mask = Op . getOperand ( NumOps - <NUM_LIT> ) ; SDValue MaskedOff = Op . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Mask , Vec , MaskedOff , VL ) ; } } return lowerVectorIntrinsicSplats ( Op , DAG , Subtarget ) ;"
LLVM,RISCV,2568,"Predict the next statement of this code snippet:
 <s> } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Load = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; if ( ! IsUnmasked ) { SDValue Policy = DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ; Ops . push_back ( Policy ) ; } SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; Result = convertFromScalableVector ( VT , Result , DAG , Subtarget ) ; return DAG . getMergeValues ( { Result , Chain } , DL ) ; } }"
LLVM,RISCV,2569,"Predict the next statement of this code snippet:
 <s> JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; return getAddr ( N , DAG ) ;"
LLVM,RISCV,2570,"Predict the next statement of this code snippet:
 <s> JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ;"
LLVM,RISCV,2571,"Predict the next statement of this code snippet:
 <s> bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( ContainerVT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ;"
LLVM,RISCV,2572,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue IntID = DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ;"
LLVM,RISCV,2573,"Predict the next statement of this code snippet:
 <s> SDValue BasePtr = MemSD -> getBasePtr ( ) ; bool IsTruncatingStore = false ; SDValue Index , Mask , Val , VL ; if ( auto * VPSN = dyn_cast < VPScatterSDNode > ( Op . getNode ( ) ) ) { Index = VPSN -> getIndex ( ) ; Mask = VPSN -> getMask ( ) ; Val = VPSN -> getValue ( ) ; VL = VPSN -> getVectorLength ( ) ; IsTruncatingStore = false ; } else { auto * MSN = cast < MaskedScatterSDNode > ( Op . getNode ( ) ) ; Index = MSN -> getIndex ( ) ; Mask = MSN -> getMask ( ) ; Val = MSN -> getValue ( ) ; IsTruncatingStore = MSN -> isTruncatingStore ( ) ; } MVT VT = Val . getSimpleValueType ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( ! IsTruncatingStore && <STR_LIT> ) ;"
LLVM,RISCV,2574,"Predict the next statement of this code snippet:
 <s> MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( ! IsTruncatingStore && <STR_LIT> ) ; ( void ) IsTruncatingStore ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( VT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ;"
LLVM,RISCV,2575,"Predict the next statement of this code snippet:
 <s> Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; Ops . push_back ( Val ) ; Ops . push_back ( BasePtr ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ;"
LLVM,RISCV,2576,"Predict the next statement of this code snippet:
 <s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; Ops . push_back ( Val ) ; Ops . push_back ( BasePtr ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ;"
LLVM,RISCV,2577,"Predict the next statement of this code snippet:
 <s> Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL , Subtarget ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; if ( STI . isRegisterReservedByUser ( VA . getLocReg ( ) ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) { RetOps . push_back ( Glue ) ; } unsigned RetOpc = <STR_LIT> ; const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { if ( ! Func . getReturnType ( ) -> isVoidTy ( ) ) report_fatal_error ( <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; StringRef Kind = MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ;"
LLVM,RISCV,2578,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ;"
LLVM,RISCV,2579,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) { unsigned ExtOpc = isa < ConstantSDNode > ( Scalar ) ? <STR_LIT> : <STR_LIT> ; Scalar = DAG . getNode ( ExtOpc , DL , XLenVT , Scalar ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Scalar , VL ) ; } assert ( XLenVT == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; return splatSplitI64WithVL ( DL , VT , Scalar , VL , DAG ) ;"
LLVM,RISCV,2580,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( VT . isVector ( ) ) { MVT SplatCondVT = VT . changeVectorElementType ( <STR_LIT> ) ; SDValue CondSplat = VT . isScalableVector ( ) ? DAG . getSplatVector ( SplatCondVT , DL , CondV ) : DAG . getSplatBuildVector ( SplatCondVT , DL , CondV ) ; return DAG . getNode ( <STR_LIT> , DL , VT , CondSplat , TrueV , FalseV ) ; } if ( VT == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; const auto * CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; if ( isa < ConstantSDNode > ( TrueV ) && isa < ConstantSDNode > ( FalseV ) && CCVal == <STR_LIT> ) { const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ;"
LLVM,RISCV,2581,"Predict the next statement of this code snippet:
 <s> if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; SDValue TargetCC = DAG . getCondCode ( CCVal ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ; } SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SetNE = DAG . getCondCode ( <STR_LIT> ) ;"
LLVM,RISCV,2582,"Predict the next statement of this code snippet:
 <s> SDValue Chain = Op -> getOperand ( <NUM_LIT> ) ; SDValue RMValue = Op -> getOperand ( <NUM_LIT> ) ; SDValue SysRegNo = DAG . getConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; static const unsigned Table = ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToEven ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardZero ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardNegative ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardPositive ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToAway ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ; RMValue = DAG . getNode ( <STR_LIT> , DL , XLenVT , Shifted , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;"
LLVM,RISCV,2583,"Predict the next statement of this code snippet:
 <s> SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ; RMValue = DAG . getNode ( <STR_LIT> , DL , XLenVT , Shifted , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;"
LLVM,RISCV,2584,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerShiftLeftParts ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , XLenMinus1 , Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , One ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRight1Lo , XLenMinus1Shamt ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue HiTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue HiFalse = DAG . getNode ( <STR_LIT> , DL , VT , Lo , ShamtMinusXLen ) ; SDValue CC = DAG . getSetCC ( DL , VT , ShamtMinusXLen , Zero , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , CC , LoTrue , Zero ) ;"
LLVM,RISCV,2585,"Predict the next statement of this code snippet:
 <s> SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , XLenMinus1 , Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , One ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRight1Lo , XLenMinus1Shamt ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue HiTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ;"
LLVM,RISCV,2586,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; unsigned ShiftRightOp = IsSRA ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , XLenMinus1 , Shamt ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftLeftHi1 = DAG . getNode ( <STR_LIT> , DL , VT , Hi , One ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi1 , XLenMinus1Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRightLo , ShiftLeftHi ) ; SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ; SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusXLen ) ; SDValue HiFalse = IsSRA ? DAG . getNode ( <STR_LIT> , DL , VT , Hi , XLenMinus1 ) : Zero ; SDValue CC = DAG . getSetCC ( DL , VT , ShamtMinusXLen , Zero , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , CC , LoTrue , LoFalse ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , CC , HiTrue , HiFalse ) ; SDValue Parts [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Parts , DL ) ;"
LLVM,RISCV,2587,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; unsigned ShiftRightOp = IsSRA ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , XLenMinus1 , Shamt ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftLeftHi1 = DAG . getNode ( <STR_LIT> , DL , VT , Hi , One ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi1 , XLenMinus1Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRightLo , ShiftLeftHi ) ; SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ; SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusXLen ) ; SDValue HiFalse = IsSRA ? DAG . getNode ( <STR_LIT> , DL , VT , Hi , XLenMinus1 ) : Zero ; SDValue CC = DAG . getSetCC ( DL , VT , ShamtMinusXLen , Zero , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , CC , LoTrue , LoFalse ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , CC , HiTrue , HiFalse ) ; SDValue Parts [ <NUM_LIT> ] = { Lo , Hi } ;"
LLVM,RISCV,2588,"Predict the next statement of this code snippet:
 <s> MVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT , Subtarget ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ;"
LLVM,RISCV,2589,"Predict the next statement of this code snippet:
 <s> if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; } if ( Hi . getOpcode ( ) == <STR_LIT> && Hi . getOperand ( <NUM_LIT> ) == Lo && isa < ConstantSDNode > ( Hi . getOperand ( <NUM_LIT> ) ) && Hi . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , Hi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ;"
LLVM,RISCV,2590,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerToScalableOp ( SDValue Op , SelectionDAG & DAG , unsigned NewOpc , bool HasMask ) const { MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( const SDValue & V : Op -> op_values ( ) ) { assert ( ! isa < VTSDNode > ( V ) && <STR_LIT> ) ; if ( ! V . getValueType ( ) . isVector ( ) ) { Ops . push_back ( V ) ; continue ; } assert ( useRVVForFixedLengthVectorVT ( V . getSimpleValueType ( ) ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; } SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ;"
LLVM,RISCV,2591,"Predict the next statement of this code snippet:
 <s> Ops . push_back ( V ) ; continue ; } assert ( useRVVForFixedLengthVectorVT ( V . getSimpleValueType ( ) ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; } SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; if ( HasMask ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; SDValue ScalableRes = DAG . getNode ( NewOpc , DL , ContainerVT , Ops ) ; return convertFromScalableVector ( VT , ScalableRes , DAG , Subtarget ) ;"
LLVM,RISCV,2592,"Predict the next statement of this code snippet:
 <s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT VecEVT = Vec . getValueType ( ) ; unsigned BaseOpc = <STR_LIT> ( Op . getOpcode ( ) ) ; while ( getTypeAction ( * DAG . getContext ( ) , VecEVT ) == TargetLowering :: TypeSplitVector ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Vec , DL ) ; VecEVT = Lo . getValueType ( ) ; Vec = DAG . getNode ( BaseOpc , DL , VecEVT , Lo , Hi ) ; } if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ;"
LLVM,RISCV,2593,"Predict the next statement of this code snippet:
 <s> unsigned IntNo = Op . getConstantOperandVal ( HasChain ? <NUM_LIT> : <NUM_LIT> ) ; SDLoc DL ( Op ) ; const <STR_LIT> * II = <STR_LIT> ( IntNo ) ; if ( ! II || ! II -> SplatOperand ) return SDValue ( ) ; unsigned SplatOp = II -> SplatOperand + HasChain ; assert ( SplatOp < Op . getNumOperands ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [ SplatOp ] ; MVT OpVT = ScalarOp . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( ! OpVT . isScalarInteger ( ) || OpVT == XLenVT ) return SDValue ( ) ; if ( OpVT . bitsLT ( XLenVT ) ) { unsigned ExtOpc = isa < ConstantSDNode > ( ScalarOp ) ? <STR_LIT> : <STR_LIT> ; ScalarOp = DAG . getNode ( ExtOpc , DL , XLenVT , ScalarOp ) ; return DAG . getNode ( Op -> getOpcode ( ) , DL , Op -> getVTList ( ) , Operands ) ; } assert ( II -> SplatOperand > <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,2594,"Predict the next statement of this code snippet:
 <s> MVT VecVT = Op . getSimpleValueType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; assert ( Src . getValueType ( ) . isVector ( ) && Src . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SplatTrueVal = DAG . getConstant ( ExtTrueVal , DL , XLenVT ) ; if ( VecVT . isScalableVector ( ) ) { bool IsRV32E64 = ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> ; if ( ! IsRV32E64 ) { SplatZero = DAG . getSplatVector ( VecVT , DL , SplatZero ) ; SplatTrueVal = DAG . getSplatVector ( VecVT , DL , SplatTrueVal ) ; } else { SplatZero = DAG . getNode ( <STR_LIT> , DL , VecVT , SplatZero ) ; SplatTrueVal = DAG . getNode ( <STR_LIT> , DL , VecVT , SplatTrueVal ) ; } return DAG . getNode ( <STR_LIT> , DL , VecVT , Src , SplatTrueVal , SplatZero ) ; } MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; MVT I1ContainerVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; SDValue CC = convertToScalableVector ( I1ContainerVT , Src , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ;"
LLVM,RISCV,2595,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue VL = getDefaultScalableVLOps ( VT , DL , DAG , Subtarget ) . second ; return DAG . getNode ( <STR_LIT> , DL , VT , VL ) ; } if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue VL = getDefaultScalableVLOps ( VT , DL , DAG , Subtarget ) . second ; return DAG . getNode ( <STR_LIT> , DL , VT , VL ) ;"
LLVM,RISCV,2596,"Predict the next statement of this code snippet:
 <s> MVT VT = Op . getSimpleValueType ( ) ; SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue VL = getDefaultScalableVLOps ( VT , DL , DAG , Subtarget ) . second ; return DAG . getNode ( <STR_LIT> , DL , VT , VL ) ; } if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue VL = getDefaultScalableVLOps ( VT , DL , DAG , Subtarget ) . second ; return DAG . getNode ( <STR_LIT> , DL , VT , VL ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( SplatVal . getValueType ( ) == XLenVT && <STR_LIT> ) ; MVT InterVT = VT . changeVectorElementType ( <STR_LIT> ) ;"
LLVM,RISCV,2597,"Predict the next statement of this code snippet:
 <s> MVT VecVT = Src . getSimpleValueType ( ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SplatOne = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatOne ) ;"
LLVM,RISCV,2598,"Predict the next statement of this code snippet:
 <s> if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SplatOne = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatOne ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatZero ) ; if ( VecVT . isScalableVector ( ) ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Src , SplatOne ) ;"
LLVM,RISCV,2599,"Predict the next statement of this code snippet:
 <s> std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; } unsigned BaseOpc ; <STR_LIT> CC ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : { SDValue TrueMask = DAG . getNode ( <STR_LIT> , DL , ContainerVT , VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Vec , TrueMask , VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , Mask , VL ) ; CC = <STR_LIT> ; BaseOpc = <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , Mask , VL ) ; CC = <STR_LIT> ; BaseOpc = <STR_LIT> ; break ;"
LLVM,RISCV,2600,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( const auto & OpIdx : enumerate ( Op -> ops ( ) ) ) { SDValue V = OpIdx . value ( ) ; assert ( ! isa < VTSDNode > ( V ) && <STR_LIT> ) ; if ( ! V . getValueType ( ) . isFixedLengthVector ( ) ) { Ops . push_back ( V ) ; continue ; } MVT OpVT = V . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( OpVT ) ; assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; }"
LLVM,RISCV,2601,"Predict the next statement of this code snippet:
 <s> assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; } if ( ! VT . isFixedLengthVector ( ) ) return DAG . getNode ( <ISA_LIT>ISDOpc , DL , VT , Ops ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ;"
LLVM,RISCV,2602,"Predict the next statement of this code snippet:
 <s> EVT VecEVT = Vec . getValueType ( ) ; if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVVPReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ;"
LLVM,RISCV,2603,"Predict the next statement of this code snippet:
 <s> <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return match<ISA_LIT>BitmanipPat ( Op , BitmanipMasks ) ;"
LLVM,RISCV,2604,"Predict the next statement of this code snippet:
 <s> if ( Op . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Mask = Op . getConstantOperandVal ( <NUM_LIT> ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return None ; bool IsSHL = Op . getOpcode ( ) == <STR_LIT> ; if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return None ; uint64_t ShAmt = Op . getConstantOperandVal ( <NUM_LIT> ) ; unsigned Width = Op . getValueType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ShAmt >= Width || ! isPowerOf2_64 ( ShAmt ) ) return None ; if ( BitmanipMasks . size ( ) == <NUM_LIT> && ShAmt >= ( Width / <NUM_LIT> ) ) return None ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; bool SHLExpMask = IsSHL ; if ( ! Mask ) { if ( Src . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) { Mask = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2605,"Predict the next statement of this code snippet:
 <s> Mask = Op . getConstantOperandVal ( <NUM_LIT> ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return None ; bool IsSHL = Op . getOpcode ( ) == <STR_LIT> ; if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return None ; uint64_t ShAmt = Op . getConstantOperandVal ( <NUM_LIT> ) ; unsigned Width = Op . getValueType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ShAmt >= Width || ! isPowerOf2_64 ( ShAmt ) ) return None ; if ( BitmanipMasks . size ( ) == <NUM_LIT> && ShAmt >= ( Width / <NUM_LIT> ) ) return None ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; bool SHLExpMask = IsSHL ;"
LLVM,RISCV,2606,"Predict the next statement of this code snippet:
 <s> static Optional < <ISA_LIT>BitmanipPat > matchSHFLPat ( SDValue Op ) { static const uint64_t BitmanipMasks [ ] = {"
LLVM,RISCV,2607,"Predict the next statement of this code snippet:
 <s> static Optional < <ISA_LIT>BitmanipPat > matchSHFLPat ( SDValue Op ) {"
LLVM,RISCV,2608,"Predict the next statement of this code snippet:
 <s> return CI -> isTailCall ( ) ;"
LLVM,RISCV,2609,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: mergeStoresAfterLegalization ( EVT VT ) const { return ! Subtarget . useRVVForFixedLengthVectors ( ) || ( VT . isFixedLengthVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> ) ;"
LLVM,RISCV,2610,"Predict the next statement of this code snippet:
 <s> if ( SDValue V = transformAddShlImm ( N , DAG , Subtarget ) ) return V ;"
LLVM,RISCV,2611,"Predict the next statement of this code snippet:
 <s> if ( SDValue V = transformAddShlImm ( N , DAG , Subtarget ) ) return V ; return combineSelectAndUseCommutative ( N , DAG , false ) ;"
LLVM,RISCV,2612,"Predict the next statement of this code snippet:
 <s> return combineSelectAndUseCommutative ( N , DAG , true ) ;"
LLVM,RISCV,2613,"Predict the next statement of this code snippet:
 <s> static SDValue performANDCombine ( SDNode * N , SelectionDAG & DAG ) { return combineSelectAndUseCommutative ( N , DAG , true ) ;"
LLVM,RISCV,2614,"Predict the next statement of this code snippet:
 <s> if ( ! Subtarget . is64Bit ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> || Src . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; switch ( Src . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : if ( ! Subtarget . hasStdExtM ( ) ) return SDValue ( ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : break ; } if ( none_of ( N -> uses ( ) , [ ] ( SDNode * User ) { return User -> getOpcode ( ) == <STR_LIT> ; } ) ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > SetCCs ; for ( SDNode :: use_iterator UI = Src . getNode ( ) -> use_begin ( ) , UE = Src . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User == N ) continue ; if ( UI . getUse ( ) . getResNo ( ) != Src . getResNo ( ) ) continue ; if ( User -> getOpcode ( ) == <STR_LIT> ) { SetCCs . push_back ( User ) ; continue ; } break ; } if ( SetCCs . empty ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; DCI . CombineTo ( N , SExt ) ;"
LLVM,RISCV,2615,"Predict the next statement of this code snippet:
 <s> if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ;"
LLVM,RISCV,2616,"Predict the next statement of this code snippet:
 <s> static SDValue performORCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( Subtarget . hasStdExtZbp ( ) ) { if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ; if ( auto GORC = combineORToGORC ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GORC ; if ( auto SHFL = combineORToSHFL ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return SHFL ; }"
LLVM,RISCV,2617,"Predict the next statement of this code snippet:
 <s> static SDValue performSUBCombine ( SDNode * N , SelectionDAG & DAG ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; return combineSelectAndUse ( N , N1 , N0 , DAG , false ) ;"
LLVM,RISCV,2618,"Predict the next statement of this code snippet:
 <s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; return combineSelectAndUse ( N , N1 , N0 , DAG , false ) ;"
LLVM,RISCV,2619,"Predict the next statement of this code snippet:
 <s> static SDValue performXORCombine ( SDNode * N , SelectionDAG & DAG ) {"
LLVM,RISCV,2620,"Predict the next statement of this code snippet:
 <s> for ( const auto & ArgIdx : enumerate ( Args ) ) { MVT ArgVT = ArgIdx . value ( ) . VT ; if ( ArgVT . isVector ( ) && ArgVT . getVectorElementType ( ) == <STR_LIT> ) return ArgIdx . index ( ) ;"
LLVM,RISCV,2621,"Predict the next statement of this code snippet:
 <s> MVT ArgVT = ArgIdx . value ( ) . VT ; if ( ArgVT . isVector ( ) && ArgVT . getVectorElementType ( ) == <STR_LIT> ) return ArgIdx . index ( ) ; } return None ;"
LLVM,RISCV,2622,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,RISCV,2623,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: shouldExpandBuildVectorWithShuffles ( EVT VT , unsigned DefinedValues ) const { return false ;"
LLVM,RISCV,2624,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: shouldExpandBuildVectorWithShuffles ( EVT VT , unsigned DefinedValues ) const { return false ;"
LLVM,RISCV,2625,"Predict the next statement of this code snippet:
 <s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override {"
LLVM,RISCV,2626,"Predict the next statement of this code snippet:
 <s> if ( ABI == <STR_LIT> && ( Type == <STR_LIT> ) ) return false ;"
LLVM,RISCV,2627,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( Subtarget . is64Bit ( ) && Type == <STR_LIT> ) return true ; return IsSigned ;"
LLVM,RISCV,2628,"Predict the next statement of this code snippet:
 <s> return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Op -> getOperandUse ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2629,"Predict the next statement of this code snippet:
 <s> return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ;"
LLVM,RISCV,2630,"Predict the next statement of this code snippet:
 <s> if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VT , Lo , VL ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi , VL ) ;"
LLVM,RISCV,2631,"Predict the next statement of this code snippet:
 <s> int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VT , Lo , VL ) ; }"
LLVM,RISCV,2632,"Predict the next statement of this code snippet:
 <s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;"
LLVM,RISCV,2633,"Predict the next statement of this code snippet:
 <s> Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Parts [ <NUM_LIT> ] = Val ; return true ; } if ( ValueVT . isScalableVector ( ) && PartVT . isScalableVector ( ) ) { LLVMContext & Context = * DAG . getContext ( ) ; EVT ValueEltVT = ValueVT . getVectorElementType ( ) ; EVT PartEltVT = PartVT . getVectorElementType ( ) ; unsigned ValueVTBitSize = ValueVT . getSizeInBits ( ) . getKnownMinSize ( ) ; unsigned PartVTBitSize = PartVT . getSizeInBits ( ) . getKnownMinSize ( ) ; if ( PartVTBitSize % ValueVTBitSize == <NUM_LIT> ) { if ( ValueEltVT != PartEltVT ) { unsigned Count = ValueVTBitSize / PartEltVT . getSizeInBits ( ) ; assert ( Count != <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,2634,"Predict the next statement of this code snippet:
 <s> if ( ! TLO . LegalOps ) return false ; EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( Op . getOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return false ; const APInt & Mask = C -> getAPIntValue ( ) ; APInt ShrunkMask = Mask & DemandedBits ; APInt ExpandedMask = Mask | ~ DemandedBits ; auto IsLegalMask = [ ShrunkMask , ExpandedMask ] ( const APInt & Mask ) -> bool { return ShrunkMask . isSubsetOf ( Mask ) && Mask . isSubsetOf ( ExpandedMask ) ; } ; auto UseMask = [ Mask , Op , VT , & TLO ] ( const APInt & NewMask ) -> bool { if ( NewMask == Mask ) return true ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( NewMask , DL , VT ) ;"
LLVM,RISCV,2635,"Predict the next statement of this code snippet:
 <s> auto UseMask = [ Mask , Op , VT , & TLO ] ( const APInt & NewMask ) -> bool { if ( NewMask == Mask ) return true ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( NewMask , DL , VT ) ; SDValue NewOp = TLO . DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , NewC ) ; return TLO . CombineTo ( Op , NewOp ) ; } ; if ( ShrunkMask . isSignedIntN ( <NUM_LIT> ) ) return false ; if ( Subtarget . hasStdExtZbb ( ) || Subtarget . hasStdExtZbp ( ) ) { APInt NewMask = APInt ( Mask . getBitWidth ( ) , <NUM_LIT> ) ; if ( IsLegalMask ( NewMask ) ) return UseMask ( NewMask ) ; } if ( VT == <STR_LIT> ) { APInt NewMask = APInt ( <NUM_LIT> , <NUM_LIT> ) ; if ( IsLegalMask ( NewMask ) ) return UseMask ( NewMask ) ; } if ( ! ExpandedMask . isNegative ( ) ) return false ; unsigned MinSignedBits = ExpandedMask . getMinSignedBits ( ) ; APInt NewMask = ShrunkMask ;"
LLVM,RISCV,2636,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( N ) ; SDValue New0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C1 / C0 , DL , VT ) ) ; SDValue New1 = DAG . getNode ( <STR_LIT> , DL , VT , New0 , DAG . getConstant ( C0 , DL , VT ) ) ; if ( ( C1 % C0 ) == <NUM_LIT> ) return New1 ;"
LLVM,RISCV,2637,"Predict the next statement of this code snippet:
 <s> if ( ! N0C || ! N1C ) return SDValue ( ) ; int64_t C0 = N0C -> getSExtValue ( ) ; int64_t C1 = N1C -> getSExtValue ( ) ; if ( C0 <= <NUM_LIT> || C1 <= <NUM_LIT> ) return SDValue ( ) ; int64_t Bits = std :: min ( C0 , C1 ) ; int64_t Diff = std :: abs ( C0 - C1 ) ; if ( Diff != <NUM_LIT> && Diff != <NUM_LIT> && Diff != <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue NS = ( C0 < C1 ) ? N0 -> getOperand ( <NUM_LIT> ) : N1 -> getOperand ( <NUM_LIT> ) ; SDValue NL = ( C0 > C1 ) ? N0 -> getOperand ( <NUM_LIT> ) : N1 -> getOperand ( <NUM_LIT> ) ; SDValue NA0 = DAG . getNode ( <STR_LIT> , DL , VT , NL , DAG . getConstant ( Diff , DL , VT ) ) ; SDValue NA1 = DAG . getNode ( <STR_LIT> , DL , VT , NA0 , NS ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NA1 , DAG . getConstant ( Bits , DL , VT ) ) ;"
LLVM,RISCV,2638,"Predict the next statement of this code snippet:
 <s> CC = <STR_LIT> ; return ; } if ( CC == <STR_LIT> && isOneConstant ( RHS ) ) { RHS = LHS ; LHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; CC = <STR_LIT> ; return ; } switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ( CC ) ; std :: swap ( LHS , RHS ) ; break ; }"
LLVM,RISCV,2639,"Predict the next statement of this code snippet:
 <s> assert ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; return DAG . getLoad ( <STR_LIT> , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Register LoVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , LoVReg ) ; SDValue Lo = DAG . getCopyFromReg ( Chain , DL , LoVReg , <STR_LIT> ) ; SDValue Hi ; if ( VA . getLocReg ( ) == <STR_LIT> ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ;"
LLVM,RISCV,2640,"Predict the next statement of this code snippet:
 <s> EVT ValVT = VA . getValVT ( ) ; EVT PtrVT = <STR_LIT> ( DAG . getDataLayout ( ) . getPointerSizeInBits ( <NUM_LIT> ) ) ; int FI = MFI . CreateFixedObject ( ValVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full :"
LLVM,RISCV,2641,"Predict the next statement of this code snippet:
 <s> static SDValue unpackFromRegLoc ( SelectionDAG & DAG , SDValue Chain , const CCValAssign & VA , const SDLoc & DL , const <ISA_LIT>TargetLowering & TLI ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ;"
LLVM,RISCV,2642,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: useRVVForFixedLengthVectorVT ( MVT VT ) const {"
LLVM,RISCV,2643,"Predict the next statement of this code snippet:
 <s> return :: useRVVForFixedLengthVectorVT ( VT , Subtarget ) ;"
LLVM,RISCV,2644,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( llvm :: any_of ( Regs , [ & STI ] ( auto Reg ) { return STI . isRegisterReservedByUser ( Reg . first ) ;"
LLVM,RISCV,2645,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( llvm :: any_of ( Regs , [ & STI ] ( auto Reg ) { return STI . isRegisterReservedByUser ( Reg . first ) ;"
LLVM,RISCV,2646,"Predict the next statement of this code snippet:
 <s> auto Idx = <STR_LIT> ( Opc , <STR_LIT> :: frm ) ; if ( Idx < <NUM_LIT> ) return ;"
LLVM,RISCV,2647,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( <NUM_LIT> ) , Attr ) ) return SDValue ( N , <NUM_LIT> ) ; assert ( ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) && <STR_LIT> ) ; if ( ! Subtarget . hasStdExtZbt ( ) ) return SDValue ( ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; if ( Lg2 == <NUM_LIT> || Lg2 >= <NUM_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && ! ( Subtarget . is64Bit ( ) && VT == <STR_LIT> ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue Cmp = DAG . getSetCC ( DL , VT , N0 , Zero , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue Sel = DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Add , N0 ) ; Created . push_back ( Cmp . getNode ( ) ) ;"
LLVM,RISCV,2648,"Predict the next statement of this code snippet:
 <s> SDValue VL = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOperand ( <NUM_LIT> ) != Mask || Op0 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDLoc DL ( N ) ; if ( IsVWMULSU || Op0 . getOpcode ( ) == Op1 . getOpcode ( ) ) { if ( ! Op1 . hasOneUse ( ) ) return SDValue ( ) ; if ( Op1 . getOperand ( <NUM_LIT> ) != Mask || Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ;"
LLVM,RISCV,2649,"Predict the next statement of this code snippet:
 <s> bool IsZeroExt = Op0 . getOpcode ( ) == <STR_LIT> ; bool IsVWMULSU = IsSignExt && Op1 . getOpcode ( ) == <STR_LIT> ; if ( ( ! IsSignExt && ! IsZeroExt ) || ! Op0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOperand ( <NUM_LIT> ) != Mask || Op0 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDLoc DL ( N ) ; if ( IsVWMULSU || Op0 . getOpcode ( ) == Op1 . getOpcode ( ) ) { if ( ! Op1 . hasOneUse ( ) ) return SDValue ( ) ; if ( Op1 . getOperand ( <NUM_LIT> ) != Mask || Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) { if ( DAG . ComputeNumSignBits ( Op1 ) <= ( ScalarBits - NarrowSize ) ) return SDValue ( ) ; } else { APInt Mask = APInt :: getBitsSetFrom ( ScalarBits , NarrowSize ) ; if ( ! DAG . MaskedValueIsZero ( Op1 , Mask ) ) return SDValue ( ) ; } Op1 = DAG . getNode ( <STR_LIT> , DL , NarrowVT , Op1 , VL ) ; } else return SDValue ( ) ;"
LLVM,RISCV,2650,"Predict the next statement of this code snippet:
 <s> unsigned BitWidth = Known . getBitWidth ( ) ; unsigned Opc = Op . getOpcode ( ) ; assert ( ( Opc >= <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; Known . resetAll ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) break ; KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known = KnownBits :: commonBits ( Known , Known2 ) ; break ; } case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: urem ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: udiv ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleTZ = Known2 . trunc ( <NUM_LIT> ) . countMaxTrailingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleTZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleLZ = Known2 . trunc ( <NUM_LIT> ) . countMaxLeadingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleLZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; }"
LLVM,RISCV,2651,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && ( Op . getConstantOperandVal ( <NUM_LIT> ) & <NUM_LIT> ) == <NUM_LIT> ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp > <NUM_LIT> ) return <NUM_LIT> ; }"
LLVM,RISCV,2652,"Predict the next statement of this code snippet:
 <s> SDValue NewOp2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewRes = DAG . getNode ( WOpcode , DL , <STR_LIT> , NewOp1 , NewOp2 ) ;"
LLVM,RISCV,2653,"Predict the next statement of this code snippet:
 <s> return emitSelectPseudo ( MI , BB , Subtarget ) ; case <STR_LIT> : return emitBuildPairF64Pseudo ( MI , BB ) ; case <STR_LIT> : return emitSplitF64Pseudo ( MI , BB ) ; case <STR_LIT> : return emitQuietFCMP ( MI , BB , <STR_LIT> , <STR_LIT> , Subtarget ) ; case <STR_LIT> : return emitQuietFCMP ( MI , BB , <STR_LIT> , <STR_LIT> , Subtarget ) ; case <STR_LIT> :"
LLVM,RISCV,2654,"Predict the next statement of this code snippet:
 <s> MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; Register SavedFFlags = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetInstrInfo & TII = * BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , SavedFFlags ) ; auto MIB = BuildMI ( * BB , MI , DL , TII . get ( RelOpcode ) , DstReg ) . addReg ( Src1Reg ) . addReg ( Src2Reg ) ; if ( MI . getFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ) MIB -> setFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( SavedFFlags , RegState :: Kill ) ; auto MIB2 = BuildMI ( * BB , MI , DL , TII . get ( EqOpcode ) , <STR_LIT> ) . addReg ( Src1Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( Src2Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; if ( MI . getFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ) MIB2 -> setFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ; MI . eraseFromParent ( ) ;"
LLVM,RISCV,2655,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const { if ( Subtarget . is64Bit ( ) && ! isPositionIndependent ( ) && getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) {"
LLVM,RISCV,2656,"Predict the next statement of this code snippet:
 <s> switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,2657,"Predict the next statement of this code snippet:
 <s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { SDValue Zero = DAG . getConstantFP ( Flags . hasNoSignedZeros ( ) ? <NUM_LIT> : - <NUM_LIT> , DL , EltVT ) ; return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Zero ) ; } case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getNeutralElement ( BaseOpcode , DL , EltVT , Flags ) ) ; case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getNeutralElement ( BaseOpcode , DL , EltVT , Flags ) ) ; }"
LLVM,RISCV,2658,"Predict the next statement of this code snippet:
 <s> Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ;"
LLVM,RISCV,2659,"Predict the next statement of this code snippet:
 <s> const <STR_LIT> * II = <STR_LIT> ( IntNo ) ; if ( ! II ) return SDValue ( ) ;"
LLVM,RISCV,2660,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: hasAndNotCompare ( SDValue Y ) const {"
LLVM,RISCV,2661,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == <STR_LIT> && ! Subtarget . hasStdExtZfh ( ) ) return false ;"
LLVM,RISCV,2662,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == <STR_LIT> && ! Subtarget . hasStdExtZfh ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ;"
LLVM,RISCV,2663,"Predict the next statement of this code snippet:
 <s> int Srcs [ ] = { - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i != Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; int Pol = i % <NUM_LIT> ; int Src = Mask [ i ] / Size ; if ( Srcs [ Pol ] < <NUM_LIT> ) Srcs [ Pol ] = Src ; if ( Srcs [ Pol ] != Src ) return false ; int Elt = Mask [ i ] % Size ; if ( Elt != i / <NUM_LIT> ) return false ; } if ( Srcs [ <NUM_LIT> ] < <NUM_LIT> || Srcs [ <NUM_LIT> ] < <NUM_LIT> || Srcs [ <NUM_LIT> ] == Srcs [ <NUM_LIT> ] ) return false ;"
LLVM,RISCV,2664,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( auto * LD = dyn_cast < LoadSDNode > ( Val ) ) {"
LLVM,RISCV,2665,"Predict the next statement of this code snippet:
 <s> SDValue Val = Parts [ <NUM_LIT> ] ; EVT ValueEltVT = ValueVT . getVectorElementType ( ) ; EVT PartEltVT = PartVT . getVectorElementType ( ) ; unsigned ValueVTBitSize = ValueVT . getSizeInBits ( ) . getKnownMinSize ( ) ; unsigned PartVTBitSize = PartVT . getSizeInBits ( ) . getKnownMinSize ( ) ; if ( PartVTBitSize % ValueVTBitSize == <NUM_LIT> ) { assert ( PartVTBitSize >= ValueVTBitSize ) ; EVT SameEltTypeVT = ValueVT ; if ( ValueEltVT != PartEltVT ) { unsigned Count = PartVTBitSize / ValueEltVT . getFixedSizeInBits ( ) ; assert ( Count != <NUM_LIT> && <STR_LIT> ) ; SameEltTypeVT = EVT :: getVectorVT ( Context , ValueEltVT , Count , true ) ; Val = DAG . getNode ( <STR_LIT> , DL , SameEltTypeVT , Val ) ; } Val = DAG . getNode ( <STR_LIT> , DL , ValueVT , Val , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ; return Val ; } }"
LLVM,RISCV,2666,"Predict the next statement of this code snippet:
 <s> const MCExpr * <ISA_LIT>TargetLowering :: LowerCustomJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB , unsigned uid , MCContext & Ctx ) const { assert ( Subtarget . is64Bit ( ) && ! isPositionIndependent ( ) && getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) ; return MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , Ctx ) ;"
LLVM,RISCV,2667,"Predict the next statement of this code snippet:
 <s> assert ( Subtarget . is64Bit ( ) && ! isPositionIndependent ( ) && getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) ; return MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , Ctx ) ;"
LLVM,RISCV,2668,"Predict the next statement of this code snippet:
 <s> if ( NumElts <= LargestEltVT . getSizeInBits ( ) ) { assert ( isPowerOf2_32 ( NumElts ) && <STR_LIT> ) ; WideEltVT = <STR_LIT> ( NumElts ) ; WidenVecLen = <NUM_LIT> ; ExtractElementIdx = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; ExtractBitIdx = Idx ; } else { WideEltVT = LargestEltVT ; WidenVecLen = NumElts / WideEltVT . getSizeInBits ( ) ; ExtractElementIdx = DAG . getNode ( <STR_LIT> , DL , XLenVT , Idx , DAG . getConstant ( Log2_64 ( WideEltVT . getSizeInBits ( ) ) , DL , XLenVT ) ) ; ExtractBitIdx = DAG . getNode ( <STR_LIT> , DL , XLenVT , Idx , DAG . getConstant ( WideEltVT . getSizeInBits ( ) - <NUM_LIT> , DL , XLenVT ) ) ; } MVT WideVT = <STR_LIT> ( WideEltVT , WidenVecLen ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; SDValue ExtractElt = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , ExtractElementIdx ) ; SDValue ShiftRight = DAG . getNode ( <STR_LIT> , DL , XLenVT , ExtractElt , ExtractBitIdx ) ; return DAG . getNode ( <STR_LIT> , DL , XLenVT , ShiftRight , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; } } MVT WideVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; return DAG . getNode ( <STR_LIT> , DL , EltVT , Vec , Idx ) ; }"
LLVM,RISCV,2669,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerFPVECREDUCE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; MVT VecEltVT = Op . getSimpleValueType ( ) ; unsigned RVVOpcode ; SDValue VectorVal , ScalarVal ; std :: tie ( RVVOpcode , VectorVal , ScalarVal ) = getRVVFPReductionOpAndOperands ( Op , DAG , VecEltVT ) ; MVT VecVT = VectorVal . getSimpleValueType ( ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; VectorVal = convertToScalableVector ( ContainerVT , VectorVal , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( VectorVal . getSimpleValueType ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ScalarSplat = lowerScalarSplat ( ScalarVal , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ;"
LLVM,RISCV,2670,"Predict the next statement of this code snippet:
 <s> if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; VectorVal = convertToScalableVector ( ContainerVT , VectorVal , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( VectorVal . getSimpleValueType ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ;"
LLVM,RISCV,2671,"Predict the next statement of this code snippet:
 <s> static SDValue lowerFP_TO_INT_SAT ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT DstVT = Op . getValueType ( ) ; EVT SatVT = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; bool IsSigned = Op . getOpcode ( ) == <STR_LIT> ; unsigned Opc ; if ( SatVT == DstVT ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstVT == <STR_LIT> && SatVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue FpToInt = DAG . getNode ( Opc , DL , DstVT , Src , DAG . getTargetConstant ( <STR_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ;"
LLVM,RISCV,2672,"Predict the next statement of this code snippet:
 <s> Truncated = DAG . getSelect ( DL , VT , NeedAdjust , Adjust , Truncated ) ; } Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , Src ) ; const fltSemantics & FltSem = DAG . EVTToAPFloatSemantics ( VT ) ; unsigned Precision = APFloat :: semanticsPrecision ( FltSem ) ; APFloat MaxVal = APFloat ( FltSem ) ; MaxVal . convertFromAPInt ( APInt :: getOneBitSet ( Precision , Precision - <NUM_LIT> ) , false , APFloat :: rmNearestTiesToEven ) ; SDValue MaxValNode = DAG . getConstantFP ( MaxVal , DL , VT ) ; SDValue Abs = DAG . getNode ( <STR_LIT> , DL , VT , Src ) ;"
LLVM,RISCV,2673,"Predict the next statement of this code snippet:
 <s> assert ( isPowerOf2_32 ( BitWidth ) && BitWidth >= <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( Opc , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( BitWidth / <NUM_LIT> ) - <NUM_LIT> , DL , XLenVT ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Opc = IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Opc = IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : assert ( Op . getValueType ( ) == XLenVT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return lowerScalarSplat ( Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getSimpleValueType ( ) , DL , DAG , Subtarget ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { SDValue Scalar = Op . getOperand ( <NUM_LIT> ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) { Scalar = DAG . getNode ( <STR_LIT> , DL , XLenVT , Scalar ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Scalar , Op . getOperand ( <NUM_LIT> ) ) ; } assert ( Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,2674,"Predict the next statement of this code snippet:
 <s> bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Load = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ; if ( IsUnmasked ) Ops . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; else Ops . push_back ( PassThru ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2675,"Predict the next statement of this code snippet:
 <s> unsigned IntNo = Op . getConstantOperandVal ( <NUM_LIT> ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : { SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Load = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ; if ( IsUnmasked ) Ops . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; else Ops . push_back ( PassThru ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; if ( ! IsUnmasked ) { SDValue Policy = DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ; Ops . push_back ( Policy ) ; } SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; Result = convertFromScalableVector ( VT , Result , DAG , Subtarget ) ; return DAG . getMergeValues ( { Result , Chain } , DL ) ;"
LLVM,RISCV,2676,"Predict the next statement of this code snippet:
 <s> ContainerVT = getContainerForFixedLengthVector ( VT ) ; Op1 = convertToScalableVector ( ContainerVT , Op1 , DAG , Subtarget ) ; Op2 = convertToScalableVector ( ContainerVT , Op2 , DAG , Subtarget ) ; } SDLoc DL ( Op ) ;"
LLVM,RISCV,2677,"Predict the next statement of this code snippet:
 <s> ContainerVT = getContainerForFixedLengthVector ( VT ) ; Op1 = convertToScalableVector ( ContainerVT , Op1 , DAG , Subtarget ) ; Op2 = convertToScalableVector ( ContainerVT , Op2 , DAG , Subtarget ) ; } SDLoc DL ( Op ) ; SDValue Val = DAG . getNode ( MaskOpc , DL , ContainerVT , Op1 , Op2 , VL ) ; if ( ! IsFixed ) return Val ;"
LLVM,RISCV,2678,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerMaskedGather ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; const auto * MemSD = cast < MemSDNode > ( Op . getNode ( ) ) ; EVT MemVT = MemSD -> getMemoryVT ( ) ; MachineMemOperand * MMO = MemSD -> getMemOperand ( ) ; SDValue Chain = MemSD -> getChain ( ) ; SDValue BasePtr = MemSD -> getBasePtr ( ) ; <STR_LIT> LoadExtType ; SDValue Index , Mask , PassThru , VL ; if ( auto * VPGN = dyn_cast < VPGatherSDNode > ( Op . getNode ( ) ) ) { Index = VPGN -> getIndex ( ) ; Mask = VPGN -> getMask ( ) ; PassThru = DAG . getUNDEF ( VT ) ; VL = VPGN -> getVectorLength ( ) ; LoadExtType = <STR_LIT> ; } else { auto * MGN = cast < MaskedGatherSDNode > ( Op . getNode ( ) ) ; Index = MGN -> getIndex ( ) ; Mask = MGN -> getMask ( ) ; PassThru = MGN -> getPassThru ( ) ; LoadExtType = MGN -> getExtensionType ( ) ; } MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( LoadExtType == <STR_LIT> && <STR_LIT> ) ; ( void ) LoadExtType ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( ContainerVT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; if ( XLenVT == <STR_LIT> && IndexVT . getVectorElementType ( ) . bitsGT ( XLenVT ) ) { IndexVT = IndexVT . changeVectorElementType ( XLenVT ) ; SDValue TrueMask = DAG . getNode ( <STR_LIT> , DL , Mask . getValueType ( ) , VL ) ; Index = DAG . getNode ( <STR_LIT> , DL , IndexVT , Index , TrueMask , VL ) ; }"
LLVM,RISCV,2679,"Predict the next statement of this code snippet:
 <s> MVT VT = Op . getSimpleValueType ( ) ; const auto * MemSD = cast < MemSDNode > ( Op ) ; EVT MemVT = MemSD -> getMemoryVT ( ) ; MachineMemOperand * MMO = MemSD -> getMemOperand ( ) ; SDValue Chain = MemSD -> getChain ( ) ; SDValue BasePtr = MemSD -> getBasePtr ( ) ; SDValue Mask , PassThru , VL ; if ( const auto * VPLoad = dyn_cast < VPLoadSDNode > ( Op ) ) { Mask = VPLoad -> getMask ( ) ; PassThru = DAG . getUNDEF ( VT ) ; VL = VPLoad -> getVectorLength ( ) ; } else { const auto * MLoad = cast < MaskedLoadSDNode > ( Op ) ; Mask = MLoad -> getMask ( ) ; PassThru = MLoad -> getPassThru ( ) ; } bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ;"
LLVM,RISCV,2680,"Predict the next statement of this code snippet:
 <s> } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; if ( XLenVT == <STR_LIT> && IndexVT . getVectorElementType ( ) . bitsGT ( XLenVT ) ) { IndexVT = IndexVT . changeVectorElementType ( XLenVT ) ; SDValue TrueMask = DAG . getNode ( <STR_LIT> , DL , Mask . getValueType ( ) , VL ) ; Index = DAG . getNode ( <STR_LIT> , DL , IndexVT , Index , TrueMask , VL ) ; } unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; Ops . push_back ( Val ) ; Ops . push_back ( BasePtr ) ; Ops . push_back ( Index ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ;"
LLVM,RISCV,2681,"Predict the next statement of this code snippet:
 <s> ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( Scalar ) ; if ( isOneConstant ( VL ) && ( ! Const || isNullConstant ( Scalar ) || ! isInt < <NUM_LIT> > ( Const -> getSExtValue ( ) ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Scalar , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Scalar , VL ) ; }"
LLVM,RISCV,2682,"Predict the next statement of this code snippet:
 <s> if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue NeutralElem = DAG . getNeutralElement ( BaseOpc , DL , VecEltVT , SDNodeFlags ( ) ) ;"
LLVM,RISCV,2683,"Predict the next statement of this code snippet:
 <s> std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue NeutralElem = DAG . getNeutralElement ( BaseOpc , DL , VecEltVT , SDNodeFlags ( ) ) ; SDValue IdentitySplat = lowerScalarSplat ( NeutralElem , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , DAG . getUNDEF ( M1VT ) , Vec , IdentitySplat , Mask , VL ) ; SDValue Elt0 = DAG . getNode ( <STR_LIT> , DL , VecEltVT , Reduction , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; return DAG . getSExtOrTrunc ( Elt0 , DL , Op . getValueType ( ) ) ;"
LLVM,RISCV,2684,"Predict the next statement of this code snippet:
 <s> assert ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! Subtarget . hasVInstructions ( ) ) return SDValue ( ) ; bool HasChain = Op . getOpcode ( ) == <STR_LIT> ; unsigned IntNo = Op . getConstantOperandVal ( HasChain ? <NUM_LIT> : <NUM_LIT> ) ; SDLoc DL ( Op ) ; const <STR_LIT> * II = <STR_LIT> ( IntNo ) ; if ( ! II || ! II -> hasSplatOperand ( ) ) return SDValue ( ) ; unsigned SplatOp = II -> SplatOperand + <NUM_LIT> + HasChain ; assert ( SplatOp < Op . getNumOperands ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [ SplatOp ] ; MVT OpVT = ScalarOp . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( ! OpVT . isScalarInteger ( ) || OpVT == XLenVT ) return SDValue ( ) ;"
LLVM,RISCV,2685,"Predict the next statement of this code snippet:
 <s> SDValue StartSplat = lowerScalarSplat ( Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , StartSplat , Vec , StartSplat , Mask , VL ) ; SDValue Elt0 = DAG . getNode ( <STR_LIT> , DL , ResVT , Reduction , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; if ( ! VecVT . isInteger ( ) ) return Elt0 ; return DAG . getSExtOrTrunc ( Elt0 , DL , Op . getValueType ( ) ) ;"
LLVM,RISCV,2686,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerVPREDUCE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT VecEVT = Vec . getValueType ( ) ; if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVVPReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } SDValue VL = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ;"
LLVM,RISCV,2687,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return <STR_LIT> ;"
LLVM,RISCV,2688,"Predict the next statement of this code snippet:
 <s> return true ; } ; auto MatchShift = [ & ] ( int Shift ) { for ( int i = <NUM_LIT> ; i != Size - Shift ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != Shift + i ) return false ; return true ; } ; for ( int Shift = <NUM_LIT> ; Shift != Size ; ++ Shift ) if ( CheckUndefs ( Shift ) && MatchShift ( Shift ) ) return Shift ;"
LLVM,RISCV,2689,"Predict the next statement of this code snippet:
 <s> unsigned Opc ; if ( VT == XLenVT ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( N ) ; SDValue FpToInt = DAG . getNode ( Opc , DL , XLenVT , Src . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( FRM , DL , XLenVT ) ) ;"
LLVM,RISCV,2690,"Predict the next statement of this code snippet:
 <s> if ( FRM == <STR_LIT> ) return SDValue ( ) ; bool IsSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc ; if ( SatVT == DstVT ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstVT == <STR_LIT> && SatVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else return SDValue ( ) ; Src = Src . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue FpToInt = DAG . getNode ( Opc , DL , XLenVT , Src , DAG . getTargetConstant ( FRM , DL , XLenVT ) ) ; SDValue ZeroInt = DAG . getConstant ( <NUM_LIT> , DL , DstVT ) ;"
LLVM,RISCV,2691,"Predict the next statement of this code snippet:
 <s> if ( DstVT != XLenVT ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( Src . getValueType ( ) ) ) return SDValue ( ) ; if ( Src . getValueType ( ) == <STR_LIT> && ! Subtarget . hasStdExtZfh ( ) ) return SDValue ( ) ; EVT SatVT = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; <STR_LIT> FRM = matchRoundingOp ( Src ) ; if ( FRM == <STR_LIT> ) return SDValue ( ) ; bool IsSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc ; if ( SatVT == DstVT ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstVT == <STR_LIT> && SatVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else return SDValue ( ) ; Src = Src . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2692,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return Subtarget . hasStdExtZfh ( ) ; case <STR_LIT> : return Subtarget . hasStdExtF ( ) ; case <STR_LIT> : return Subtarget . hasStdExtD ( ) ; default : return false ; }"
LLVM,RISCV,2693,"Predict the next statement of this code snippet:
 <s> switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Op -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & OpIdx . value ( ) ) ; } return true ;"
LLVM,RISCV,2694,"Predict the next statement of this code snippet:
 <s> MVT InterVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; auto InterVec = DAG . getNode ( <STR_LIT> , DL , InterVT , Lo , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , InterVec ) ; } }"
LLVM,RISCV,2695,"Predict the next statement of this code snippet:
 <s> EVT ValueVT = Val . getValueType ( ) ; if ( IsABIRegCopy && ValueVT == <STR_LIT> && PartVT == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Parts [ <NUM_LIT> ] = Val ; return true ; } if ( ValueVT . isScalableVector ( ) && PartVT . isScalableVector ( ) ) { LLVMContext & Context = * DAG . getContext ( ) ; EVT ValueEltVT = ValueVT . getVectorElementType ( ) ; EVT PartEltVT = PartVT . getVectorElementType ( ) ; unsigned ValueVTBitSize = ValueVT . getSizeInBits ( ) . getKnownMinSize ( ) ; unsigned PartVTBitSize = PartVT . getSizeInBits ( ) . getKnownMinSize ( ) ;"
LLVM,RISCV,2696,"Predict the next statement of this code snippet:
 <s> unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) { if ( DAG . ComputeNumSignBits ( Op1 ) <= ( ScalarBits - NarrowSize ) ) return SDValue ( ) ; } else { APInt Mask = APInt :: getBitsSetFrom ( ScalarBits , NarrowSize ) ; if ( ! DAG . MaskedValueIsZero ( Op1 , Mask ) ) return SDValue ( ) ; } Op1 = DAG . getNode ( <STR_LIT> , DL , NarrowVT , Op1 , VL ) ; } else return SDValue ( ) ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ; unsigned ExtOpc = IsSignExt ? <STR_LIT> : <STR_LIT> ; if ( Op0 . getValueType ( ) != NarrowVT ) Op0 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op0 , Mask , VL ) ; ExtOpc = IsVWMULSU ? <STR_LIT> : ExtOpc ; if ( Op1 . getValueType ( ) != NarrowVT ) Op1 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op1 , Mask , VL ) ; unsigned WMulOpc = <STR_LIT> ;"
LLVM,RISCV,2697,"Predict the next statement of this code snippet:
 <s> if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) { if ( DAG . ComputeNumSignBits ( Op1 ) <= ( ScalarBits - NarrowSize ) ) return SDValue ( ) ; } else { APInt Mask = APInt :: getBitsSetFrom ( ScalarBits , NarrowSize ) ; if ( ! DAG . MaskedValueIsZero ( Op1 , Mask ) ) return SDValue ( ) ; } Op1 = DAG . getNode ( <STR_LIT> , DL , NarrowVT , Op1 , VL ) ; } else return SDValue ( ) ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ; unsigned ExtOpc = IsSignExt ? <STR_LIT> : <STR_LIT> ; if ( Op0 . getValueType ( ) != NarrowVT ) Op0 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op0 , Mask , VL ) ; ExtOpc = IsVWMULSU ? <STR_LIT> : ExtOpc ;"
LLVM,RISCV,2698,"Predict the next statement of this code snippet:
 <s> IdxDiff = <NUM_LIT> ; } if ( ! SeqStepNum ) SeqStepNum = ValDiff ; else if ( ValDiff != SeqStepNum ) return None ; if ( ! SeqStepDenom ) SeqStepDenom = IdxDiff ; else if ( IdxDiff != * SeqStepDenom ) return None ; } if ( ! PrevElt || PrevElt -> first != Val ) PrevElt = std :: make_pair ( Val , Idx ) ; } if ( ! SeqStepNum || ! SeqStepDenom ) return None ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumElts ; Idx ++ ) { if ( Op . getOperand ( Idx ) . isUndef ( ) ) continue ; uint64_t Val = Op . getConstantOperandVal ( Idx ) & maskTrailingOnes < uint64_t > ( EltSizeInBits ) ; uint64_t ExpectedVal = ( int64_t ) ( Idx * ( uint64_t ) * SeqStepNum ) / * SeqStepDenom ; int64_t Addend = SignExtend64 ( Val - ExpectedVal , EltSizeInBits ) ; if ( ! SeqAddend ) SeqAddend = Addend ;"
LLVM,RISCV,2699,"Predict the next statement of this code snippet:
 <s> Value * <ISA_LIT>TargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilder < > & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const { Value * Ordering = Builder . getInt32 ( static_cast < uint32_t > ( AI -> getOrdering ( ) ) ) ; Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * LrwOpScwLoop = <STR_LIT> ( AI -> getModule ( ) , getIntrinsicForMaskedAtomicRMWBinOp32 ( AI -> getOperation ( ) ) , Tys ) ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getInt32 ( Subtarget . getXLen ( ) - ValWidth ) , ShiftAmt ) ; return Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ; } return Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , Ordering } ) ;"
LLVM,RISCV,2700,"Predict the next statement of this code snippet:
 <s> case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min :"
LLVM,RISCV,2701,"Predict the next statement of this code snippet:
 <s> case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min : return <STR_LIT> ; case AtomicRMWInst :: UMax : return <STR_LIT> ; case AtomicRMWInst :: UMin :"
LLVM,RISCV,2702,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ;"
LLVM,RISCV,2703,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ;"
LLVM,RISCV,2704,"Predict the next statement of this code snippet:
 <s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ;"
LLVM,RISCV,2705,"Predict the next statement of this code snippet:
 <s> if ( Size == <NUM_LIT> || Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ;"
LLVM,RISCV,2706,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,2707,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,2708,"Predict the next statement of this code snippet:
 <s> default : break ; case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) return DCI . CombineTo ( N , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; SDLoc DL ( N ) ; if ( ! ( Op0 . getOpcode ( ) == <STR_LIT> || Op0 . getOpcode ( ) == <STR_LIT> ) || ! Op0 . getNode ( ) -> hasOneUse ( ) ) break ; SDValue NewSplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; SDValue Lo = NewSplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = NewSplitF64 . getValue ( <NUM_LIT> ) ; APInt SignBit = APInt :: getSignMask ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } assert ( Op0 . getOpcode ( ) == <STR_LIT> ) ; SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( ~ SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; APInt LHSMask = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; APInt RHSMask = APInt :: getLowBitsSet ( RHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , LHSMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , RHSMask , DCI ) ) ) return SDValue ( ) ;"
LLVM,RISCV,2709,"Predict the next statement of this code snippet:
 <s> return DCI . CombineTo ( N , Lo , NewHi ) ; } assert ( Op0 . getOpcode ( ) == <STR_LIT> ) ; SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( ~ SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; APInt LHSMask = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; APInt RHSMask = APInt :: getLowBitsSet ( RHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , LHSMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , RHSMask , DCI ) ) ) return SDValue ( ) ; break ; }"
LLVM,RISCV,2710,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ;"
LLVM,RISCV,2711,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; if ( Subtarget . hasStdExtA ( ) ) { setMaxAtomicSizeInBitsSupported ( Subtarget . getXLen ( ) ) ; setMinCmpXchgSizeInBits ( <NUM_LIT> ) ; } else { setMaxAtomicSizeInBitsSupported ( <NUM_LIT> ) ; } setBooleanContents ( ZeroOrOneBooleanContent ) ;"
LLVM,RISCV,2712,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ;"
LLVM,RISCV,2713,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,RISCV,2714,"Predict the next statement of this code snippet:
 <s> Value * <ISA_LIT>TargetLowering :: emitMaskedAtomicCmpXchgIntrinsic ( IRBuilder < > & Builder , AtomicCmpXchgInst * CI , Value * AlignedAddr , Value * CmpVal , Value * NewVal , Value * Mask , AtomicOrdering Ord ) const { Value * Ordering = Builder . getInt32 ( static_cast < uint32_t > ( Ord ) ) ;"
LLVM,RISCV,2715,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) != <STR_LIT> ) break ; return DCI . CombineTo ( N , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2716,"Predict the next statement of this code snippet:
 <s> setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; for ( auto N : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setLoadExtAction ( N , XLenVT , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;"
LLVM,RISCV,2717,"Predict the next statement of this code snippet:
 <s> static bool CC_<ISA_LIT>Assign2XLen ( unsigned XLen , CCState & State , CCValAssign VA1 , <STR_LIT> ArgFlags1 , unsigned ValNo2 , MVT ValVT2 , MVT LocVT2 , <STR_LIT> ArgFlags2 ) { unsigned XLenInBytes = XLen / <NUM_LIT> ; if ( Register Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , Reg , VA1 . getLocVT ( ) , CCValAssign :: Full ) ) ; } else { unsigned StackAlign = std :: max ( XLenInBytes , ArgFlags1 . getOrigAlign ( ) ) ;"
LLVM,RISCV,2718,"Predict the next statement of this code snippet:
 <s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { static const MCPhysReg GPRList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( GPRList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ;"
LLVM,RISCV,2719,"Predict the next statement of this code snippet:
 <s> State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) {"
LLVM,RISCV,2720,"Predict the next statement of this code snippet:
 <s> return ( ( VectorBits / EltSize ) * MinSize ) / <STR_LIT> ;"
LLVM,RISCV,2721,"Predict the next statement of this code snippet:
 <s> bool hasVLOperand ( ) const { return VLOperand != <NUM_LIT> ;"
LLVM,RISCV,2722,"Predict the next statement of this code snippet:
 <s> RTLIB :: Libcall LC ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; else LC = RTLIB :: getFPTOUINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; MakeLibCallOptions CallOptions ; EVT OpVT = Op0 . getValueType ( ) ; CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; }"
LLVM,RISCV,2723,"Predict the next statement of this code snippet:
 <s> SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,2724,"Predict the next statement of this code snippet:
 <s> assert ( LocVT == XLenVT && <STR_LIT> ) ; if ( IsRet && ValNo > <NUM_LIT> ) return true ; unsigned TwoXLenInBytes = ( <NUM_LIT> * XLen ) / <NUM_LIT> ; if ( ! IsFixed && ArgFlags . getOrigAlign ( ) == TwoXLenInBytes && DL . getTypeAllocSize ( OrigTy ) == TwoXLenInBytes ) { unsigned RegIdx = State . getFirstUnallocated ( ArgGPRs ) ; if ( RegIdx != array_lengthof ( ArgGPRs ) && RegIdx % <NUM_LIT> == <NUM_LIT> ) State . AllocateReg ( ArgGPRs ) ; } SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ;"
LLVM,RISCV,2725,"Predict the next statement of this code snippet:
 <s> Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) { RetOps . push_back ( Flag ) ; }"
LLVM,RISCV,2726,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; }"
LLVM,RISCV,2727,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ;"
LLVM,RISCV,2728,"Predict the next statement of this code snippet:
 <s> SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ScalarSplat = DAG . getSplatVector ( M1VT , DL , ScalarVal ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , VectorVal , ScalarSplat , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VecEltVT , Reduction , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ;"
LLVM,RISCV,2729,"Predict the next statement of this code snippet:
 <s> SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ScalarSplat = DAG . getSplatVector ( M1VT , DL , ScalarVal ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , VectorVal , ScalarSplat , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VecEltVT , Reduction , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ;"
LLVM,RISCV,2730,"Predict the next statement of this code snippet:
 <s> MVT VT = Op . getSimpleValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT I32VT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue Vec = DAG . getBitcast ( I32VT , Op . getOperand ( <NUM_LIT> + OpOffset ) ) ; SDValue ScalarLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue ScalarHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue VL = Op . getOperand ( NumOps - <NUM_LIT> ) ; SDValue I32VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , VL , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; MVT I32MaskVT = <STR_LIT> ( <STR_LIT> , I32VT . getVectorElementCount ( ) ) ; SDValue I32Mask = DAG . getNode ( <STR_LIT> , DL , I32MaskVT , VL ) ; if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec , ScalarHi , I32Mask , I32VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec , ScalarLo , I32Mask , I32VL ) ; } else { Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec , ScalarLo , I32Mask , I32VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec , ScalarHi , I32Mask , I32VL ) ; } Vec = DAG . getBitcast ( VT , Vec ) ; if ( ! IsMasked ) return Vec ; SDValue Mask = Op . getOperand ( NumOps - <NUM_LIT> ) ; SDValue MaskedOff = Op . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Mask , Vec , MaskedOff , VL ) ; } } return lowerVectorIntrinsicSplats ( Op , DAG , Subtarget ) ;"
LLVM,RISCV,2731,"Predict the next statement of this code snippet:
 <s> unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { MGN -> getChain ( ) , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( MGN -> getBasePtr ( ) ) ; Ops . push_back ( Index ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , MGN -> getMemoryVT ( ) , MGN -> getMemOperand ( ) ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; if ( VT . isFixedLengthVector ( ) ) Result = convertFromScalableVector ( VT , Result , DAG , Subtarget ) ; return DAG . getMergeValues ( { Result , Chain } , DL ) ;"
LLVM,RISCV,2732,"Predict the next statement of this code snippet:
 <s> MVT VT = Op . getSimpleValueType ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( MGN -> getBasePtr ( ) . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( MGN -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; SDValue VL ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( ContainerVT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ;"
LLVM,RISCV,2733,"Predict the next statement of this code snippet:
 <s> SDValue VL ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ;"
LLVM,RISCV,2734,"Predict the next statement of this code snippet:
 <s> SDValue PassThru = Load -> getPassThru ( ) ; SDValue VL ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ;"
LLVM,RISCV,2735,"Predict the next statement of this code snippet:
 <s> SDValue Index = MSN -> getIndex ( ) ; SDValue Mask = MSN -> getMask ( ) ; SDValue Val = MSN -> getValue ( ) ; MVT VT = Val . getSimpleValueType ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( MSN -> getBasePtr ( ) . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( ! MSN -> isTruncatingStore ( ) && <STR_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; SDValue VL ; if ( VT . isFixedLengthVector ( ) ) { MVT ContainerVT ; if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( VT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { MSN -> getChain ( ) , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ;"
LLVM,RISCV,2736,"Predict the next statement of this code snippet:
 <s> Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ;"
LLVM,RISCV,2737,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; MVT VecVT = Op . getSimpleValueType ( ) ; assert ( ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; if ( VecVT . isFixedLengthVector ( ) ) { MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ;"
LLVM,RISCV,2738,"Predict the next statement of this code snippet:
 <s> while ( getTypeAction ( * DAG . getContext ( ) , VecEVT ) == TargetLowering :: TypeSplitVector ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Vec , DL ) ; VecEVT = Lo . getValueType ( ) ; Vec = DAG . getNode ( BaseOpc , DL , VecEVT , Lo , Hi ) ; } if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ;"
LLVM,RISCV,2739,"Predict the next statement of this code snippet:
 <s> MVT M1VT = getLMUL1VT ( ContainerVT ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue NeutralElem = DAG . getNeutralElement ( BaseOpc , DL , VecEltVT , SDNodeFlags ( ) ) ; SDValue IdentitySplat = DAG . getSplatVector ( M1VT , DL , NeutralElem ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , Vec , IdentitySplat , Mask , VL ) ; SDValue Elt0 = DAG . getNode ( <STR_LIT> , DL , VecEltVT , Reduction , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; return DAG . getSExtOrTrunc ( Elt0 , DL , Op . getValueType ( ) ) ;"
LLVM,RISCV,2740,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : Vec = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Vec , Mask , VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , Mask , VL ) ; return DAG . getSetCC ( DL , XLenVT , Vec , Zero , <STR_LIT> ) ; case <STR_LIT> : Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , Mask , VL ) ; return DAG . getSetCC ( DL , XLenVT , Vec , Zero , <STR_LIT> ) ; case <STR_LIT> : { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , Mask , VL ) ;"
LLVM,RISCV,2741,"Predict the next statement of this code snippet:
 <s> EVT ElemVT = VT . getVectorElementType ( ) ; if ( Alignment >= ElemVT . getStoreSize ( ) ) { if ( Fast ) * Fast = true ;"
LLVM,RISCV,2742,"Predict the next statement of this code snippet:
 <s> return V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == BinOpToRVVReduce ( Opc ) ; } ; unsigned Opc = N -> getOpcode ( ) ; unsigned ReduceIdx ; if ( IsReduction ( N -> getOperand ( <NUM_LIT> ) , Opc ) ) ReduceIdx = <NUM_LIT> ; else if ( IsReduction ( N -> getOperand ( <NUM_LIT> ) , Opc ) ) ReduceIdx = <NUM_LIT> ; else return SDValue ( ) ; if ( Opc == <STR_LIT> && ! N -> getFlags ( ) . hasAllowReassociation ( ) ) return SDValue ( ) ; SDValue Extract = N -> getOperand ( ReduceIdx ) ; SDValue Reduce = Extract . getOperand ( <NUM_LIT> ) ; if ( ! Reduce . hasOneUse ( ) ) return SDValue ( ) ; SDValue ScalarV = Reduce . getOperand ( <NUM_LIT> ) ; if ( ScalarV . getOpcode ( ) != <STR_LIT> && ScalarV . getOpcode ( ) != <STR_LIT> && ScalarV . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isOneConstant ( ScalarV . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; auto IsRVVNeutralElement = [ Opc , & DAG ] ( SDNode * N , SDValue V ) { if ( Opc == <STR_LIT> && N -> getFlags ( ) . hasNoSignedZeros ( ) && isNullFPConstant ( V ) ) return true ; return DAG . getNeutralElement ( Opc , SDLoc ( V ) , V . getSimpleValueType ( ) , N -> getFlags ( ) ) == V ;"
LLVM,RISCV,2743,"Predict the next statement of this code snippet:
 <s> } } ; auto IsReduction = [ & BinOpToRVVReduce ] ( SDValue V , unsigned Opc ) { return V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == BinOpToRVVReduce ( Opc ) ; } ; unsigned Opc = N -> getOpcode ( ) ; unsigned ReduceIdx ; if ( IsReduction ( N -> getOperand ( <NUM_LIT> ) , Opc ) ) ReduceIdx = <NUM_LIT> ; else if ( IsReduction ( N -> getOperand ( <NUM_LIT> ) , Opc ) ) ReduceIdx = <NUM_LIT> ; else return SDValue ( ) ; if ( Opc == <STR_LIT> && ! N -> getFlags ( ) . hasAllowReassociation ( ) ) return SDValue ( ) ; SDValue Extract = N -> getOperand ( ReduceIdx ) ; SDValue Reduce = Extract . getOperand ( <NUM_LIT> ) ; if ( ! Reduce . hasOneUse ( ) ) return SDValue ( ) ; SDValue ScalarV = Reduce . getOperand ( <NUM_LIT> ) ; if ( ScalarV . getOpcode ( ) != <STR_LIT> && ScalarV . getOpcode ( ) != <STR_LIT> && ScalarV . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isOneConstant ( ScalarV . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; auto IsRVVNeutralElement = [ Opc , & DAG ] ( SDNode * N , SDValue V ) { if ( Opc == <STR_LIT> && N -> getFlags ( ) . hasNoSignedZeros ( ) && isNullFPConstant ( V ) ) return true ;"
LLVM,RISCV,2744,"Predict the next statement of this code snippet:
 <s> <STR_LIT> WOpcode = get<ISA_LIT>WOpcodeByIntr ( IntNo ) ; SmallVector < SDValue , <NUM_LIT> > NewOps ; for ( SDValue Op : drop_begin ( N -> ops ( ) ) ) NewOps . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ) ; SDValue NewRes = DAG . getNode ( WOpcode , DL , <STR_LIT> , NewOps ) ;"
LLVM,RISCV,2745,"Predict the next statement of this code snippet:
 <s> MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; for ( MachineInstr * DebugInstr : SelectDebugValues ) { TailMBB -> push_back ( DebugInstr -> removeFromParent ( ) ) ; } TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; BuildMI ( HeadMBB , DL , TII . getBrCond ( CC ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( TailMBB ) ; IfFalseMBB -> addSuccessor ( TailMBB ) ; auto SelectMBBI = MI . getIterator ( ) ; auto SelectEnd = std :: next ( LastSelectPseudo -> getIterator ( ) ) ; auto InsertionPoint = TailMBB -> begin ( ) ; while ( SelectMBBI != SelectEnd ) { auto Next = std :: next ( SelectMBBI ) ; if ( isSelectPseudo ( * SelectMBBI ) ) { BuildMI ( * TailMBB , InsertionPoint , SelectMBBI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( HeadMBB ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( IfFalseMBB ) ; SelectMBBI -> eraseFromParent ( ) ; } SelectMBBI = Next ; }"
LLVM,RISCV,2746,"Predict the next statement of this code snippet:
 <s> if ( SequenceMBBI -> hasUnmodeledSideEffects ( ) || SequenceMBBI -> mayLoadOrStore ( ) ) break ; if ( llvm :: any_of ( SequenceMBBI -> operands ( ) , [ & ] ( MachineOperand & MO ) { return MO . isReg ( ) && MO . isUse ( ) && SelectDests . count ( MO . getReg ( ) ) ; } ) ) break ; } } const <ISA_LIT>InstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; for ( MachineInstr * DebugInstr : SelectDebugValues ) { TailMBB -> push_back ( DebugInstr -> removeFromParent ( ) ) ; } TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ;"
LLVM,RISCV,2747,"Predict the next statement of this code snippet:
 <s> static SDValue getAllOnesMask ( MVT VecVT , SDValue VL , SDLoc DL , SelectionDAG & DAG ) {"
LLVM,RISCV,2748,"Predict the next statement of this code snippet:
 <s> switch ( EltVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumElts = ( VT . getVectorNumElements ( ) * <STR_LIT> ) / MinVLen ; NumElts = std :: max ( NumElts , <STR_LIT> / MaxELen ) ; assert ( isPowerOf2_32 ( NumElts ) && <STR_LIT> ) ; return <STR_LIT> ( EltVT , NumElts ) ; }"
LLVM,RISCV,2749,"Predict the next statement of this code snippet:
 <s> unsigned MinVLen = Subtarget . getMinRVVVectorSizeInBits ( ) ; unsigned MaxELen = Subtarget . getELEN ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; switch ( EltVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,2750,"Predict the next statement of this code snippet:
 <s> SDValue VL = VecVT . isFixedLengthVector ( ) ? DAG . getConstant ( VecVT . getVectorNumElements ( ) , DL , XLenVT ) : DAG . getRegister ( <STR_LIT> , XLenVT ) ; SDValue Mask = getAllOnesMask ( ContainerVT , VL , DL , DAG ) ;"
LLVM,RISCV,2751,"Predict the next statement of this code snippet:
 <s> static MVT getMaskTypeFor ( EVT VecVT ) {"
LLVM,RISCV,2752,"Predict the next statement of this code snippet:
 <s> assert ( VecVT . isVector ( ) ) ; ElementCount EC = VecVT . getVectorElementCount ( ) ;"
LLVM,RISCV,2753,"Predict the next statement of this code snippet:
 <s> int Size = Mask . size ( ) ; assert ( Size == ( int ) VT . getVectorNumElements ( ) && <STR_LIT> ) ; int Srcs [ ] = { - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i != Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; int Pol = i % <NUM_LIT> ; int Src = Mask [ i ] / Size ; if ( Srcs [ Pol ] < <NUM_LIT> ) Srcs [ Pol ] = Src ; if ( Srcs [ Pol ] != Src ) return false ; int Elt = Mask [ i ] % Size ; if ( Elt != i / <NUM_LIT> ) return false ; } if ( Srcs [ <NUM_LIT> ] < <NUM_LIT> || Srcs [ <NUM_LIT> ] < <NUM_LIT> || Srcs [ <NUM_LIT> ] == Srcs [ <NUM_LIT> ] ) return false ;"
LLVM,RISCV,2754,"Predict the next statement of this code snippet:
 <s> if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( ! AM . HasBaseReg ) break ; return false ; default :"
LLVM,RISCV,2755,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {"
LLVM,RISCV,2756,"Predict the next statement of this code snippet:
 <s> } MVT WideVT = <STR_LIT> ( WideEltVT , WidenVecLen ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; SDValue ExtractElt = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , ExtractElementIdx ) ; SDValue ShiftRight = DAG . getNode ( <STR_LIT> , DL , XLenVT , ExtractElt , ExtractBitIdx ) ; return DAG . getNode ( <STR_LIT> , DL , XLenVT , ShiftRight , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; } } MVT WideVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; return DAG . getNode ( <STR_LIT> , DL , EltVT , Vec , Idx ) ; } MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } if ( ! isNullConstant ( Idx ) ) {"
LLVM,RISCV,2757,"Predict the next statement of this code snippet:
 <s> MVT ContainerVT = getContainerForFixedLengthVector ( InVT ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDValue Op2 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; MVT MaskVT = getMaskTypeFor ( ContainerVT ) ; SDValue Mask = getAllOnesMask ( ContainerVT , VL , DL , DAG ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , MaskVT , Op1 , Op2 , Op . getOperand ( <NUM_LIT> ) , Mask , VL ) ;"
LLVM,RISCV,2758,"Predict the next statement of this code snippet:
 <s> GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; assert ( N -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; const GlobalValue * GV = N -> getGlobal ( ) ; bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; return getAddr ( N , DAG , IsLocal ) ;"
LLVM,RISCV,2759,"Predict the next statement of this code snippet:
 <s> assert ( N -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; const GlobalValue * GV = N -> getGlobal ( ) ;"
LLVM,RISCV,2760,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; assert ( N -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( N -> getGlobal ( ) ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) report_fatal_error ( <STR_LIT> ) ; SDValue Addr ; switch ( Model ) { case TLSModel :: LocalExec : Addr = getStaticTLSAddr ( N , DAG , false ) ; break ; case TLSModel :: InitialExec : Addr = getStaticTLSAddr ( N , DAG , true ) ; break ;"
LLVM,RISCV,2761,"Predict the next statement of this code snippet:
 <s> bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Val . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = getMaskTypeFor ( ContainerVT ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Store = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Store -> getChain ( ) , IntID } ; Ops . push_back ( Val ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Store -> getVTList ( ) , Ops , Store -> getMemoryVT ( ) , Store -> getMemOperand ( ) ) ;"
LLVM,RISCV,2762,"Predict the next statement of this code snippet:
 <s> } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : assert ( Op . getValueType ( ) == XLenVT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return lowerScalarSplat ( Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getSimpleValueType ( ) , DL , DAG , Subtarget ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { SDValue Scalar = Op . getOperand ( <NUM_LIT> ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) { Scalar = DAG . getNode ( <STR_LIT> , DL , XLenVT , Scalar ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Scalar , Op . getOperand ( <NUM_LIT> ) ) ; } assert ( Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = getVLOperand ( Op ) ; SDValue SplattedVal = splatSplitI64WithVL ( DL , VT , SDValue ( ) , Scalar , VL , DAG ) ; if ( Op . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SplattedVal ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , VL ) ; MVT MaskVT = getMaskTypeFor ( VT ) ; SDValue Mask = getAllOnesMask ( VT , VL , DL , DAG ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; SDValue SelectCond = DAG . getNode ( <STR_LIT> , DL , MaskVT , VID , SplattedIdx , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectCond , SplattedVal , Vec , VL ) ; }"
LLVM,RISCV,2763,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : { SDLoc DL ( Op ) ; static const <STR_LIT> VlsegInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NF = Op -> getNumValues ( ) - <NUM_LIT> ; assert ( NF >= <NUM_LIT> && NF <= <NUM_LIT> && <STR_LIT> ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( VlsegInts [ NF - <NUM_LIT> ] , DL , XLenVT ) ; auto * Load = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < EVT , <NUM_LIT> > ContainerVTs ( NF , ContainerVT ) ; ContainerVTs . push_back ( <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( ContainerVTs ) ; SmallVector < SDValue , <NUM_LIT> > Ops = { Load -> getChain ( ) , IntID } ; Ops . insert ( Ops . end ( ) , NF , DAG . getUNDEF ( ContainerVT ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( VL ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Results ; for ( unsigned int RetIdx = <NUM_LIT> ; RetIdx < NF ; RetIdx ++ ) Results . push_back ( convertFromScalableVector ( VT , Result . getValue ( RetIdx ) , DAG , Subtarget ) ) ; Results . push_back ( Result . getValue ( NF ) ) ; return DAG . getMergeValues ( Results , DL ) ;"
LLVM,RISCV,2764,"Predict the next statement of this code snippet:
 <s> Index = VPGN -> getIndex ( ) ; Mask = VPGN -> getMask ( ) ; PassThru = DAG . getUNDEF ( VT ) ; VL = VPGN -> getVectorLength ( ) ; LoadExtType = <STR_LIT> ; } else { auto * MGN = cast < MaskedGatherSDNode > ( Op . getNode ( ) ) ; Index = MGN -> getIndex ( ) ; Mask = MGN -> getMask ( ) ; PassThru = MGN -> getPassThru ( ) ; LoadExtType = MGN -> getExtensionType ( ) ; } MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( LoadExtType == <STR_LIT> && <STR_LIT> ) ; ( void ) LoadExtType ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = getMaskTypeFor ( ContainerVT ) ;"
LLVM,RISCV,2765,"Predict the next statement of this code snippet:
 <s> SDValue Mask , PassThru , VL ; if ( const auto * VPLoad = dyn_cast < VPLoadSDNode > ( Op ) ) { Mask = VPLoad -> getMask ( ) ; PassThru = DAG . getUNDEF ( VT ) ; VL = VPLoad -> getVectorLength ( ) ; } else { const auto * MLoad = cast < MaskedLoadSDNode > ( Op ) ; Mask = MLoad -> getMask ( ) ; PassThru = MLoad -> getPassThru ( ) ; } bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = getMaskTypeFor ( ContainerVT ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; if ( IsUnmasked ) Ops . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; else Ops . push_back ( PassThru ) ; Ops . push_back ( BasePtr ) ;"
LLVM,RISCV,2766,"Predict the next statement of this code snippet:
 <s> IsTruncatingStore = MSN -> isTruncatingStore ( ) ; } MVT VT = Val . getSimpleValueType ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( ! IsTruncatingStore && <STR_LIT> ) ; ( void ) IsTruncatingStore ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = getMaskTypeFor ( ContainerVT ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; if ( XLenVT == <STR_LIT> && IndexVT . getVectorElementType ( ) . bitsGT ( XLenVT ) ) { IndexVT = IndexVT . changeVectorElementType ( XLenVT ) ; SDValue TrueMask = DAG . getNode ( <STR_LIT> , DL , Mask . getValueType ( ) , VL ) ; Index = DAG . getNode ( <STR_LIT> , DL , IndexVT , Index , TrueMask , VL ) ;"
LLVM,RISCV,2767,"Predict the next statement of this code snippet:
 <s> MachineMemOperand * MMO = MemSD -> getMemOperand ( ) ; SDValue Chain = MemSD -> getChain ( ) ; SDValue BasePtr = MemSD -> getBasePtr ( ) ; SDValue Val , Mask , VL ; if ( const auto * VPStore = dyn_cast < VPStoreSDNode > ( Op ) ) { Val = VPStore -> getValue ( ) ; Mask = VPStore -> getMask ( ) ; VL = VPStore -> getVectorLength ( ) ; } else { const auto * MStore = cast < MaskedStoreSDNode > ( Op ) ; Val = MStore -> getValue ( ) ; Mask = MStore -> getMask ( ) ; } bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Val . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ;"
LLVM,RISCV,2768,"Predict the next statement of this code snippet:
 <s> } if ( VT . isFixedLengthVector ( ) ) { MVT SrcContainerVT = getContainerForFixedLengthVector ( SrcVT ) ; ContainerVT = SrcContainerVT . changeVectorElementType ( VT . getVectorElementType ( ) ) ; Src = convertToScalableVector ( SrcContainerVT , Src , DAG , Subtarget ) ; if ( IsVP ) { MVT MaskVT = getMaskTypeFor ( ContainerVT ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! IsVP ) std :: tie ( Mask , VL ) = getDefaultVLOps ( SrcVT , ContainerVT , DL , DAG , Subtarget ) ; unsigned ConvOpc = IsExtend ? <STR_LIT> : <STR_LIT> ; if ( IsDirectConv ) { Src = DAG . getNode ( ConvOpc , DL , ContainerVT , Src , Mask , VL ) ; if ( VT . isFixedLengthVector ( ) ) Src = convertFromScalableVector ( VT , Src , DAG , Subtarget ) ; return Src ; } unsigned InterConvOpc = IsExtend ? <STR_LIT> : <STR_LIT> ; MVT InterVT = ContainerVT . changeVectorElementType ( <STR_LIT> ) ; SDValue IntermediateConv = DAG . getNode ( InterConvOpc , DL , InterVT , Src , Mask , VL ) ; SDValue Result = DAG . getNode ( ConvOpc , DL , ContainerVT , IntermediateConv , Mask , VL ) ; if ( VT . isFixedLengthVector ( ) ) return convertFromScalableVector ( VT , Result , DAG , Subtarget ) ;"
LLVM,RISCV,2769,"Predict the next statement of this code snippet:
 <s> } else if ( AVLInt >= <NUM_LIT> * MaxVLMAX ) { <STR_LIT> Lmul = <ISA_LIT>TargetLowering :: getLMUL ( I32VT ) ; SDValue LMUL = DAG . getConstant ( Lmul , DL , XLenVT ) ; unsigned Sew = <ISA_LIT>VType :: encodeSEW ( I32VT . getScalarSizeInBits ( ) ) ; SDValue SEW = DAG . getConstant ( Sew , DL , XLenVT ) ; SDValue SETVLMAX = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; I32VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , SETVLMAX , SEW , LMUL ) ; } else { } } if ( ! I32VL ) { <STR_LIT> Lmul = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; SDValue LMUL = DAG . getConstant ( Lmul , DL , XLenVT ) ; unsigned Sew = <ISA_LIT>VType :: encodeSEW ( VT . getScalarSizeInBits ( ) ) ; SDValue SEW = DAG . getConstant ( Sew , DL , XLenVT ) ; SDValue SETVL = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , SETVL , AVL , SEW , LMUL ) ; I32VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , VL , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; } SDValue I32Mask = getAllOnesMask ( I32VT , I32VL , DL , DAG ) ; SDValue Passthru ; if ( IsMasked ) Passthru = DAG . getUNDEF ( I32VT ) ; else Passthru = DAG . getBitcast ( I32VT , Operands [ <NUM_LIT> ] ) ; if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Passthru , Vec , ScalarHi , I32Mask , I32VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Passthru , Vec , ScalarLo , I32Mask , I32VL ) ; } else { Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Passthru , Vec , ScalarLo , I32Mask , I32VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Passthru , Vec , ScalarHi , I32Mask , I32VL ) ; } Vec = DAG . getBitcast ( VT , Vec ) ; if ( ! IsMasked ) return Vec ; SDValue Mask = Operands [ NumOps - <NUM_LIT> ] ;"
LLVM,RISCV,2770,"Predict the next statement of this code snippet:
 <s> Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; if ( IsVPTrunc ) { MVT MaskContainerVT = getContainerForFixedLengthVector ( Mask . getSimpleValueType ( ) ) ; Mask = convertToScalableVector ( MaskContainerVT , Mask , DAG , Subtarget ) ; } } if ( ! IsVPTrunc ) { std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ;"
LLVM,RISCV,2771,"Predict the next statement of this code snippet:
 <s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return lowerVectorMaskTruncLike ( Op , DAG ) ; MVT DstEltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT SrcEltVT = SrcVT . getVectorElementType ( ) ; assert ( DstEltVT . bitsLT ( SrcEltVT ) && isPowerOf2_64 ( DstEltVT . getSizeInBits ( ) ) && isPowerOf2_64 ( SrcEltVT . getSizeInBits ( ) ) && <STR_LIT> ) ; MVT ContainerVT = SrcVT ; SDValue Mask , VL ; if ( IsVPTrunc ) { Mask = Op . getOperand ( <NUM_LIT> ) ; VL = Op . getOperand ( <NUM_LIT> ) ; } if ( SrcVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( SrcVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; if ( IsVPTrunc ) { MVT MaskVT = getMaskTypeFor ( ContainerVT ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } SDValue Result = Src ; if ( ! IsVPTrunc ) { std :: tie ( Mask , VL ) = getDefaultVLOps ( SrcVT , ContainerVT , DL , DAG , Subtarget ) ;"
LLVM,RISCV,2772,"Predict the next statement of this code snippet:
 <s> ContainerVT = getContainerForFixedLengthVector ( SrcVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; if ( IsVPTrunc ) { MVT MaskVT = getMaskTypeFor ( ContainerVT ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } SDValue Result = Src ; if ( ! IsVPTrunc ) { std :: tie ( Mask , VL ) = getDefaultVLOps ( SrcVT , ContainerVT , DL , DAG , Subtarget ) ; } LLVMContext & Context = * DAG . getContext ( ) ; const ElementCount Count = ContainerVT . getVectorElementCount ( ) ; do { SrcEltVT = <STR_LIT> ( SrcEltVT . getSizeInBits ( ) / <NUM_LIT> ) ; EVT ResultVT = EVT :: getVectorVT ( Context , SrcEltVT , Count ) ; Result = DAG . getNode ( <STR_LIT> , DL , ResultVT , Result , Mask , VL ) ; } while ( SrcEltVT != DstEltVT ) ;"
LLVM,RISCV,2773,"Predict the next statement of this code snippet:
 <s> SDValue VLMax = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ; int64_t ImmValue = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; SDValue DownOffset , UpOffset ; if ( ImmValue >= <NUM_LIT> ) { DownOffset = DAG . getConstant ( ImmValue , DL , XLenVT ) ; UpOffset = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , DownOffset ) ; } else { UpOffset = DAG . getConstant ( - ImmValue , DL , XLenVT ) ; DownOffset = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , UpOffset ) ; }"
LLVM,RISCV,2774,"Predict the next statement of this code snippet:
 <s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT SrcVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Src = convertToScalableVector ( SrcVT , Src , DAG , Subtarget ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ;"
LLVM,RISCV,2775,"Predict the next statement of this code snippet:
 <s> MVT VT = Op . getSimpleValueType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT SrcVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Src = convertToScalableVector ( SrcVT , Src , DAG , Subtarget ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ZeroSplat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Zero , VL ) ; SDValue SplatValue = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> , DL , XLenVT ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatValue , VL ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , Splat , ZeroSplat , VL ) ; if ( ! VT . isFixedLengthVector ( ) ) return Result ; return convertFromScalableVector ( VT , Result , DAG , Subtarget ) ;"
LLVM,RISCV,2776,"Predict the next statement of this code snippet:
 <s> Ops . push_back ( V ) ; continue ; } MVT OpVT = V . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( OpVT ) ; assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; }"
LLVM,RISCV,2777,"Predict the next statement of this code snippet:
 <s> MVT ContainerVT = getContainerForFixedLengthVector ( OpVT ) ; assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; } if ( ! VT . isFixedLengthVector ( ) ) return DAG . getNode ( <ISA_LIT>ISDOpc , DL , VT , Ops , Op -> getFlags ( ) ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VPOp = DAG . getNode ( <ISA_LIT>ISDOpc , DL , ContainerVT , Ops , Op -> getFlags ( ) ) ; return convertFromScalableVector ( VT , VPOp , DAG , Subtarget ) ;"
LLVM,RISCV,2778,"Predict the next statement of this code snippet:
 <s> <STR_LIT> Condition = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; Op1 = convertToScalableVector ( ContainerVT , Op1 , DAG , Subtarget ) ; Op2 = convertToScalableVector ( ContainerVT , Op2 , DAG , Subtarget ) ; } SDValue Result ; SDValue AllOneMask = DAG . getNode ( <STR_LIT> , DL , ContainerVT , VL ) ; switch ( Condition ) { default : break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op1 , Op2 , VL ) ; break ; case <STR_LIT> : { SDValue Temp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op1 , Op2 , VL ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Temp , AllOneMask , VL ) ; break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Temp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op1 , AllOneMask , VL ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Temp , Op2 , VL ) ; break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Temp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op2 , AllOneMask , VL ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op1 , Temp , VL ) ; break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Temp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op1 , AllOneMask , VL ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Temp , Op2 , VL ) ; break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Temp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op2 , AllOneMask , VL ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Temp , Op1 , VL ) ;"
LLVM,RISCV,2779,"Predict the next statement of this code snippet:
 <s> if ( SDValue V = combineBinOpToReduce ( N , DAG ) ) return V ;"
LLVM,RISCV,2780,"Predict the next statement of this code snippet:
 <s> if ( SDValue V = combineBinOpToReduce ( N , DAG ) ) return V ;"
LLVM,RISCV,2781,"Predict the next statement of this code snippet:
 <s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtZbs ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && isOneConstant ( N -> getOperand ( <NUM_LIT> ) ) && N0 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDLoc DL ( N ) ; SDValue Op0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue Srl = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ;"
LLVM,RISCV,2782,"Predict the next statement of this code snippet:
 <s> static SDValue performORCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( Subtarget . hasStdExtZbp ( ) ) { if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ; if ( auto GORC = combineORToGORC ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GORC ; if ( auto SHFL = combineORToSHFL ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return SHFL ; } if ( SDValue V = combineBinOpToReduce ( N , DAG ) ) return V ; return combineSelectAndUseCommutative ( N , DAG , false ) ;"
LLVM,RISCV,2783,"Predict the next statement of this code snippet:
 <s> if ( auto GORC = combineORToGORC ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GORC ; if ( auto SHFL = combineORToSHFL ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return SHFL ;"
LLVM,RISCV,2784,"Predict the next statement of this code snippet:
 <s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N1 ) && isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) && TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( ~ <NUM_LIT> , DL , <STR_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ; }"
LLVM,RISCV,2785,"Predict the next statement of this code snippet:
 <s> shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd ( SDValue X , ConstantSDNode * XC , ConstantSDNode * CC , SDValue Y , unsigned OldShiftOpcode , unsigned NewShiftOpcode , SelectionDAG & DAG ) const { if ( XC && OldShiftOpcode == <STR_LIT> && XC -> isOne ( ) ) return false ;"
LLVM,RISCV,2786,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: shouldRemoveExtendFromGSIndex ( EVT IndexVT , EVT DataVT ) const { return false ;"
LLVM,RISCV,2787,"Predict the next statement of this code snippet:
 <s> return Subtarget . is64Bit ( ) && CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ;"
LLVM,RISCV,2788,"Predict the next statement of this code snippet:
 <s> if ( VT . getFixedSizeInBits ( ) > <NUM_LIT> * <NUM_LIT> ) return false ; unsigned MinVLen = Subtarget . getMinRVVVectorSizeInBits ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; switch ( EltVT . SimpleTy ) { default : return false ; case <STR_LIT> : if ( VT . getVectorNumElements ( ) > MinVLen ) return false ; MinVLen /= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsI64 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF16 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF32 ( ) ) return false ; break ;"
LLVM,RISCV,2789,"Predict the next statement of this code snippet:
 <s> if ( ! VT . isScalableVector ( ) ) return false ; EVT ElemVT = VT . getVectorElementType ( ) ; if ( Alignment >= ElemVT . getStoreSize ( ) ) { if ( Fast ) * Fast = true ; return true ; }"
LLVM,RISCV,2790,"Predict the next statement of this code snippet:
 <s> else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet , ArgTy , * this , FirstMaskArgument ) ) {"
LLVM,RISCV,2791,"Predict the next statement of this code snippet:
 <s> if ( IsRet ) ArgTy = FType -> getReturnType ( ) ; else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet , ArgTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << '\n' ) ; llvm_unreachable ( nullptr ) ; }"
LLVM,RISCV,2792,"Predict the next statement of this code snippet:
 <s> unsigned NumArgs = Outs . size ( ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; i ++ ) { MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; Type * OrigTy = CLI ? CLI -> getArgs ( ) [ Outs [ i ] . OrigArgIndex ] . Ty : nullptr ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr ) ;"
LLVM,RISCV,2793,"Predict the next statement of this code snippet:
 <s> } if ( ! LocVT . isVector ( ) && ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } Register Reg ; if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR16s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR32s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s ) ; else if ( ValVT . isVector ( ) ) { const TargetRegisterClass * RC = TLI . getRegClassFor ( ValVT ) ; if ( RC == & <STR_LIT> ) { if ( FirstMaskArgument . hasValue ( ) && ValNo == FirstMaskArgument . getValue ( ) ) { Reg = State . AllocateReg ( <STR_LIT> ) ; } else { Reg = State . AllocateReg ( ArgVRs ) ; } } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM2s ) ; } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM4s ) ; } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM8s ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ! Reg ) { if ( IsRet ) return true ; LocInfo = CCValAssign :: Indirect ; Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = XLenVT ; } } else Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , Align ( XLen / <NUM_LIT> ) ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ;"
LLVM,RISCV,2794,"Predict the next statement of this code snippet:
 <s> static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset4 = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset4 , LocVT , LocInfo ) ) ; return false ; }"
LLVM,RISCV,2795,"Predict the next statement of this code snippet:
 <s> if ( isZeroOrAllOnes ( TrueVal , AllOnes ) ) { SwapSelectOps = false ; NonConstantVal = FalseVal ; } else if ( isZeroOrAllOnes ( FalseVal , AllOnes ) ) { SwapSelectOps = true ; NonConstantVal = TrueVal ; } else return SDValue ( ) ; TrueVal = OtherOp ; FalseVal = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , VT , OtherOp , NonConstantVal ) ;"
LLVM,RISCV,2796,"Predict the next statement of this code snippet:
 <s> if ( SDValue Result = combineSelectCCAndUse ( N , N0 , N1 , DAG , AllOnes ) ) return Result ; if ( SDValue Result = combineSelectCCAndUse ( N , N1 , N0 , DAG , AllOnes ) ) return Result ;"
LLVM,RISCV,2797,"Predict the next statement of this code snippet:
 <s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue Result = combineSelectCCAndUse ( N , N0 , N1 , DAG , AllOnes ) ) return Result ; if ( SDValue Result = combineSelectCCAndUse ( N , N1 , N0 , DAG , AllOnes ) ) return Result ; return SDValue ( ) ;"
LLVM,RISCV,2798,"Predict the next statement of this code snippet:
 <s> KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: urem ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: udiv ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleTZ = Known2 . trunc ( <NUM_LIT> ) . countMaxTrailingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleTZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleLZ = Known2 . trunc ( <NUM_LIT> ) . countMaxLeadingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleLZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : Known . Zero . setLowBits ( <NUM_LIT> ) ; break ; case <STR_LIT> : { unsigned IntNo = Op . getConstantOperandVal ( <NUM_LIT> ) ; switch ( IntNo ) {"
LLVM,RISCV,2799,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && ( Op . getConstantOperandVal ( <NUM_LIT> ) & <NUM_LIT> ) == <NUM_LIT> ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp > <NUM_LIT> ) return <NUM_LIT> ;"
LLVM,RISCV,2800,"Predict the next statement of this code snippet:
 <s> const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - Imm ) . isPowerOf2 ( ) || ( - <NUM_LIT> - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( <NUM_LIT> ) && Imm . countTrailingZeros ( ) < <NUM_LIT> ) {"
LLVM,RISCV,2801,"Predict the next statement of this code snippet:
 <s> const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - Imm ) . isPowerOf2 ( ) || ( - <NUM_LIT> - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ;"
LLVM,RISCV,2802,"Predict the next statement of this code snippet:
 <s> case 'v' : return C_RegisterClass ; case 'I' : case 'J' : case 'K' : return C_Immediate ; case 'A' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ;"
LLVM,RISCV,2803,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstantFP ( <NUM_LIT> , DL , EltVT ) ) ; case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getNeutralElement ( BaseOpcode , DL , EltVT , Flags ) ) ; case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getNeutralElement ( BaseOpcode , DL , EltVT , Flags ) ) ; }"
LLVM,RISCV,2804,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : break ; NODE_NAME_CASE ( RET_FLAG ) NODE_NAME_CASE ( URET_FLAG ) NODE_NAME_CASE ( SRET_FLAG ) NODE_NAME_CASE ( MRET_FLAG ) NODE_NAME_CASE ( CALL ) NODE_NAME_CASE ( SELECT_CC ) NODE_NAME_CASE ( BR_CC ) NODE_NAME_CASE ( BuildPairF64 ) NODE_NAME_CASE ( SplitF64 ) NODE_NAME_CASE ( TAIL ) NODE_NAME_CASE ( MULHSU ) NODE_NAME_CASE ( SLLW ) NODE_NAME_CASE ( SRAW ) NODE_NAME_CASE ( SRLW ) NODE_NAME_CASE ( DIVW ) NODE_NAME_CASE ( DIVUW ) NODE_NAME_CASE ( REMUW ) NODE_NAME_CASE ( ROLW ) NODE_NAME_CASE ( RORW ) NODE_NAME_CASE ( CLZW ) NODE_NAME_CASE ( CTZW ) NODE_NAME_CASE ( FSLW ) NODE_NAME_CASE ( FSRW ) NODE_NAME_CASE ( FSL ) NODE_NAME_CASE ( FSR ) NODE_NAME_CASE ( FMV_H_X ) NODE_NAME_CASE ( FMV_X_ANYEXTH ) NODE_NAME_CASE ( FMV_W_X_RV64 ) NODE_NAME_CASE ( FMV_X_ANYEXTW_RV64 ) NODE_NAME_CASE ( READ_CYCLE_WIDE ) NODE_NAME_CASE ( GREV ) NODE_NAME_CASE ( GREVW ) NODE_NAME_CASE ( GORC ) NODE_NAME_CASE ( GORCW ) NODE_NAME_CASE ( SHFL ) NODE_NAME_CASE ( SHFLW ) NODE_NAME_CASE ( UNSHFL ) NODE_NAME_CASE ( UNSHFLW ) NODE_NAME_CASE ( BCOMPRESS ) NODE_NAME_CASE ( BCOMPRESSW ) NODE_NAME_CASE ( BDECOMPRESS ) NODE_NAME_CASE ( BDECOMPRESSW ) NODE_NAME_CASE ( VMV_V_X_VL ) NODE_NAME_CASE ( VFMV_V_F_VL ) NODE_NAME_CASE ( VMV_X_S ) NODE_NAME_CASE ( VMV_S_X_VL ) NODE_NAME_CASE ( VFMV_S_F_VL ) NODE_NAME_CASE ( SPLAT_VECTOR_I64 ) NODE_NAME_CASE ( SPLAT_VECTOR_SPLIT_I64_VL ) NODE_NAME_CASE ( READ_VLENB ) NODE_NAME_CASE ( TRUNCATE_VECTOR_VL ) NODE_NAME_CASE ( VSLIDEUP_VL ) NODE_NAME_CASE ( VSLIDE1UP_VL ) NODE_NAME_CASE ( VSLIDEDOWN_VL ) NODE_NAME_CASE ( VSLIDE1DOWN_VL ) NODE_NAME_CASE ( VID_VL ) NODE_NAME_CASE ( VFNCVT_ROD_VL ) NODE_NAME_CASE ( VECREDUCE_ADD_VL ) NODE_NAME_CASE ( VECREDUCE_UMAX_VL ) NODE_NAME_CASE ( VECREDUCE_SMAX_VL ) NODE_NAME_CASE ( VECREDUCE_UMIN_VL ) NODE_NAME_CASE ( VECREDUCE_SMIN_VL ) NODE_NAME_CASE ( VECREDUCE_AND_VL ) NODE_NAME_CASE ( VECREDUCE_OR_VL ) NODE_NAME_CASE ( VECREDUCE_XOR_VL ) NODE_NAME_CASE ( VECREDUCE_FADD_VL ) NODE_NAME_CASE ( VECREDUCE_SEQ_FADD_VL ) NODE_NAME_CASE ( VECREDUCE_FMIN_VL ) NODE_NAME_CASE ( VECREDUCE_FMAX_VL ) NODE_NAME_CASE ( ADD_VL ) NODE_NAME_CASE ( AND_VL ) NODE_NAME_CASE ( MUL_VL ) NODE_NAME_CASE ( OR_VL ) NODE_NAME_CASE ( SDIV_VL ) NODE_NAME_CASE ( SHL_VL ) NODE_NAME_CASE ( SREM_VL ) NODE_NAME_CASE ( SRA_VL ) NODE_NAME_CASE ( SRL_VL ) NODE_NAME_CASE ( SUB_VL ) NODE_NAME_CASE ( UDIV_VL ) NODE_NAME_CASE ( UREM_VL ) NODE_NAME_CASE ( XOR_VL ) NODE_NAME_CASE ( FADD_VL ) NODE_NAME_CASE ( FSUB_VL ) NODE_NAME_CASE ( FMUL_VL ) NODE_NAME_CASE ( FDIV_VL ) NODE_NAME_CASE ( FNEG_VL ) NODE_NAME_CASE ( FABS_VL ) NODE_NAME_CASE ( FSQRT_VL ) NODE_NAME_CASE ( FMA_VL ) NODE_NAME_CASE ( FCOPYSIGN_VL ) NODE_NAME_CASE ( SMIN_VL ) NODE_NAME_CASE ( SMAX_VL ) NODE_NAME_CASE ( UMIN_VL ) NODE_NAME_CASE ( UMAX_VL ) NODE_NAME_CASE ( FMINNUM_VL ) NODE_NAME_CASE ( FMAXNUM_VL ) NODE_NAME_CASE ( MULHS_VL ) NODE_NAME_CASE ( MULHU_VL ) NODE_NAME_CASE ( FP_TO_SINT_VL ) NODE_NAME_CASE ( FP_TO_UINT_VL ) NODE_NAME_CASE ( SINT_TO_FP_VL ) NODE_NAME_CASE ( UINT_TO_FP_VL ) NODE_NAME_CASE ( FP_EXTEND_VL ) NODE_NAME_CASE ( FP_ROUND_VL ) NODE_NAME_CASE ( SETCC_VL ) NODE_NAME_CASE ( VSELECT_VL ) NODE_NAME_CASE ( VMAND_VL ) NODE_NAME_CASE ( VMOR_VL ) NODE_NAME_CASE ( VMXOR_VL ) NODE_NAME_CASE ( VMCLR_VL ) NODE_NAME_CASE ( VMSET_VL ) NODE_NAME_CASE ( VRGATHER_VX_VL ) NODE_NAME_CASE ( VRGATHER_VV_VL ) NODE_NAME_CASE ( VRGATHEREI16_VV_VL ) NODE_NAME_CASE ( VSEXT_VL ) NODE_NAME_CASE ( VZEXT_VL ) NODE_NAME_CASE ( VPOPC_VL ) NODE_NAME_CASE ( VLE_VL ) NODE_NAME_CASE ( VSE_VL ) NODE_NAME_CASE ( READ_CSR ) NODE_NAME_CASE ( WRITE_CSR ) NODE_NAME_CASE ( SWAP_CSR ) }"
LLVM,RISCV,2805,"Predict the next statement of this code snippet:
 <s> if ( ShiftedC1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( C1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ;"
LLVM,RISCV,2806,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorLoadToRVV ( SDValue Op , SelectionDAG & DAG ) const { auto * Load = cast < LoadSDNode > ( Op ) ; SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue NewLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , { Load -> getChain ( ) , Load -> getBasePtr ( ) , VL } , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Result = convertFromScalableVector ( VT , NewLoad , DAG , Subtarget ) ;"
LLVM,RISCV,2807,"Predict the next statement of this code snippet:
 <s> auto * Load = cast < LoadSDNode > ( Op ) ; SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ;"
LLVM,RISCV,2808,"Predict the next statement of this code snippet:
 <s> MVT VT = StoreVal . getSimpleValueType ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && VT . getVectorNumElements ( ) < <NUM_LIT> ) { VT = <STR_LIT> ;"
LLVM,RISCV,2809,"Predict the next statement of this code snippet:
 <s> CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) ArgValue = unpackF64OnRV32DSoftABI ( DAG , Chain , VA , DL ) ; else if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL , * this ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; unsigned ArgPartOffset = Ins [ i ] . PartOffset ; assert ( VA . getValVT ( ) . isVector ( ) || ArgPartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset - ArgPartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else {"
LLVM,RISCV,2810,"Predict the next statement of this code snippet:
 <s> IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( ContainerVT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { MGN -> getChain ( ) , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( MGN -> getBasePtr ( ) ) ; Ops . push_back ( Index ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ;"
LLVM,RISCV,2811,"Predict the next statement of this code snippet:
 <s> assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( MGN -> getBasePtr ( ) . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( MGN -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; SDValue VL ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( ContainerVT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ;"
LLVM,RISCV,2812,"Predict the next statement of this code snippet:
 <s> SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( Op . getSimpleValueType ( ) == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; auto CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; if ( isa < ConstantSDNode > ( TrueV ) && isa < ConstantSDNode > ( FalseV ) && CCVal == <STR_LIT> ) { const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; SDValue TargetCC = DAG . getTargetConstant ( CCVal , DL , XLenVT ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ; }"
LLVM,RISCV,2813,"Predict the next statement of this code snippet:
 <s> SDValue StepVec = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; uint64_t StepValImm = Op . getConstantOperandVal ( <NUM_LIT> ) ; if ( StepValImm != <NUM_LIT> ) { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == XLenVT && <STR_LIT> ) ; if ( isPowerOf2_64 ( StepValImm ) ) { SDValue StepVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Log2_64 ( StepValImm ) , DL , XLenVT ) ) ; StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ;"
LLVM,RISCV,2814,"Predict the next statement of this code snippet:
 <s> SDValue StepVec = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; uint64_t StepValImm = Op . getConstantOperandVal ( <NUM_LIT> ) ; if ( StepValImm != <NUM_LIT> ) { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == XLenVT && <STR_LIT> ) ; if ( isPowerOf2_64 ( StepValImm ) ) { SDValue StepVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Log2_64 ( StepValImm ) , DL , XLenVT ) ) ; StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ; } else { SDValue StepVal = DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2815,"Predict the next statement of this code snippet:
 <s> } } bool IsSelect = all_of ( enumerate ( SVN -> getMask ( ) ) , [ & ] ( const auto & MaskIdx ) { int MaskIndex = MaskIdx . value ( ) ; return MaskIndex < <NUM_LIT> || MaskIdx . index ( ) == ( unsigned ) MaskIndex % NumElts ; } ) ; assert ( ! V1 . isUndef ( ) && <STR_LIT> ) ; SmallVector < SDValue > MaskVals ; SmallVector < SDValue > GatherIndicesLHS , GatherIndicesRHS ; bool SwapOps = DAG . isSplatValue ( V2 ) && ! DAG . isSplatValue ( V1 ) ; bool InvertMask = IsSelect == SwapOps ; for ( int MaskIndex : SVN -> getMask ( ) ) { bool SelectMaskVal = ( MaskIndex < ( int ) NumElts ) ^ InvertMask ; MaskVals . push_back ( DAG . getConstant ( SelectMaskVal , DL , XLenVT ) ) ; if ( ! IsSelect ) { bool IsLHS = MaskIndex < ( int ) NumElts ; GatherIndicesLHS . push_back ( DAG . getConstant ( IsLHS ? std :: max ( MaskIndex , <NUM_LIT> ) : <NUM_LIT> , DL , XLenVT ) ) ; GatherIndicesRHS . push_back ( DAG . getConstant ( IsLHS ? <NUM_LIT> : MaskIndex - NumElts , DL , XLenVT ) ) ; } } if ( SwapOps ) { std :: swap ( V1 , V2 ) ; std :: swap ( GatherIndicesLHS , GatherIndicesRHS ) ; } assert ( MaskVals . size ( ) == NumElts && <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue SelectMask = DAG . getBuildVector ( MaskVT , DL , MaskVals ) ; if ( IsSelect ) return DAG . getNode ( <STR_LIT> , DL , VT , SelectMask , V1 , V2 ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && VT . getVectorNumElements ( ) > <NUM_LIT> ) { return SDValue ( ) ; } unsigned GatherOpc = <STR_LIT> ; MVT IndexVT = VT . changeTypeToInteger ( ) ; if ( IndexVT . getScalarType ( ) . bitsGT ( XLenVT ) ) { GatherOpc = <STR_LIT> ; IndexVT = IndexVT . changeVectorElementType ( <STR_LIT> ) ; } MVT IndexContainerVT = ContainerVT . changeVectorElementType ( IndexVT . getScalarType ( ) ) ; SDValue Gather ; if ( SDValue SplatValue = DAG . getSplatValue ( V1 , true ) ) { Gather = lowerScalarSplat ( SplatValue , VL , ContainerVT , DL , DAG , Subtarget ) ; } else { SDValue LHSIndices = DAG . getBuildVector ( IndexVT , DL , GatherIndicesLHS ) ; LHSIndices = convertToScalableVector ( IndexContainerVT , LHSIndices , DAG , Subtarget ) ; V1 = convertToScalableVector ( ContainerVT , V1 , DAG , Subtarget ) ; Gather = DAG . getNode ( GatherOpc , DL , ContainerVT , V1 , LHSIndices , TrueMask , VL ) ; } if ( ! V2 . isUndef ( ) ) {"
LLVM,RISCV,2816,"Predict the next statement of this code snippet:
 <s> SDValue V = OpIdx . value ( ) ; if ( ( unsigned ) OpIdx . index ( ) == EVLIdx ) { Ops . push_back ( DAG . getZExtOrTrunc ( V , DL , XLenVT ) ) ; continue ; } assert ( ! isa < VTSDNode > ( V ) && <STR_LIT> ) ; if ( ! V . getValueType ( ) . isFixedLengthVector ( ) ) { Ops . push_back ( V ) ; continue ; } MVT OpVT = V . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( OpVT ) ;"
LLVM,RISCV,2817,"Predict the next statement of this code snippet:
 <s> unsigned Width = Op . getValueType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ShAmt >= Width && ! isPowerOf2_64 ( ShAmt ) ) return None ; if ( BitmanipMasks . size ( ) == <NUM_LIT> && ShAmt >= ( Width / <NUM_LIT> ) ) return None ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; bool SHLExpMask = IsSHL ; if ( ! Mask ) { if ( Src . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) { Mask = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; SHLExpMask = ! SHLExpMask ; } else { Mask = maskTrailingOnes < uint64_t > ( Width ) ; * Mask &= ( IsSHL ? * Mask << ShAmt : * Mask >> ShAmt ) ; }"
LLVM,RISCV,2818,"Predict the next statement of this code snippet:
 <s> SelectionDAG & DAG = DCI . DAG ; return combineSelectCCAndUseCommutative ( N , DAG , true ) ;"
LLVM,RISCV,2819,"Predict the next statement of this code snippet:
 <s> static SDValue performANDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SelectionDAG & DAG = DCI . DAG ; return combineSelectCCAndUseCommutative ( N , DAG , true ) ;"
LLVM,RISCV,2820,"Predict the next statement of this code snippet:
 <s> static SDValue performORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SelectionDAG & DAG = DCI . DAG ; if ( Subtarget . hasStdExtZbp ( ) ) { if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ; if ( auto GORC = combineORToGORC ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GORC ; if ( auto SHFL = combineORToSHFL ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return SHFL ;"
LLVM,RISCV,2821,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . hasStdExtZbp ( ) ) { if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ; if ( auto GORC = combineORToGORC ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GORC ;"
LLVM,RISCV,2822,"Predict the next statement of this code snippet:
 <s> static SDValue performXORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) {"
LLVM,RISCV,2823,"Predict the next statement of this code snippet:
 <s> static SDValue performXORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SelectionDAG & DAG = DCI . DAG ; return combineSelectCCAndUseCommutative ( N , DAG , false ) ;"
LLVM,RISCV,2824,"Predict the next statement of this code snippet:
 <s> return false ; case <STR_LIT> : if ( VT . getVectorNumElements ( ) > MinVLen ) return false ; MinVLen /= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget . hasStdExtZfh ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasStdExtF ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasStdExtD ( ) ) return false ; break ; } unsigned LMul = divideCeil ( VT . getSizeInBits ( ) , MinVLen ) ;"
LLVM,RISCV,2825,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && ( Op . getConstantOperandVal ( <NUM_LIT> ) & <NUM_LIT> ) == <NUM_LIT> ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp > <NUM_LIT> ) return <NUM_LIT> ; } break ; } case <STR_LIT> :"
LLVM,RISCV,2826,"Predict the next statement of this code snippet:
 <s> if ( ! isa < ConstantSDNode > ( Op . getOperand ( Idx ) ) ) return None ; uint64_t Val = Op . getConstantOperandVal ( Idx ) & maskTrailingOnes < uint64_t > ( EltSizeInBits ) ; if ( PrevElt ) { int64_t Diff = SignExtend64 ( Val - PrevElt -> first , EltSizeInBits ) ; if ( Diff % ( Idx - PrevElt -> second ) != <NUM_LIT> ) return None ; int64_t Step = Diff / ( Idx - PrevElt -> second ) ; if ( Step == <NUM_LIT> ) return None ; if ( ! SeqStep ) SeqStep = Step ; else if ( Step != SeqStep ) return None ;"
LLVM,RISCV,2827,"Predict the next statement of this code snippet:
 <s> if ( PrevElt ) { int64_t Diff = SignExtend64 ( Val - PrevElt -> first , EltSizeInBits ) ; if ( Diff % ( Idx - PrevElt -> second ) != <NUM_LIT> ) return None ; int64_t Step = Diff / ( Idx - PrevElt -> second ) ; if ( Step == <NUM_LIT> ) return None ; if ( ! SeqStep ) SeqStep = Step ; else if ( Step != SeqStep ) return None ; } if ( SeqStep ) { int64_t Addend = SignExtend64 ( Val - ( Idx * ( uint64_t ) * SeqStep ) , EltSizeInBits ) ; if ( ! SeqAddend ) SeqAddend = Addend ; else if ( SeqAddend != Addend ) return None ; }"
LLVM,RISCV,2828,"Predict the next statement of this code snippet:
 <s> MVT VT = Op . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( VT . isVector ( ) ) { MVT SplatCondVT = VT . changeVectorElementType ( <STR_LIT> ) ; SDValue CondSplat = VT . isScalableVector ( ) ? DAG . getSplatVector ( SplatCondVT , DL , CondV ) : DAG . getSplatBuildVector ( SplatCondVT , DL , CondV ) ; return DAG . getNode ( <STR_LIT> , DL , VT , CondSplat , TrueV , FalseV ) ; } if ( VT == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; const auto * CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; if ( isa < ConstantSDNode > ( TrueV ) && isa < ConstantSDNode > ( FalseV ) && CCVal == <STR_LIT> ) { const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; SDValue TargetCC = DAG . getTargetConstant ( CCVal , DL , XLenVT ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ;"
LLVM,RISCV,2829,"Predict the next statement of this code snippet:
 <s> V1 = convertToScalableVector ( ContainerVT , V1 , DAG , Subtarget ) ; assert ( Lane < ( int ) NumElts && <STR_LIT> ) ; SDValue Gather = DAG . getNode ( <STR_LIT> , DL , ContainerVT , V1 , DAG . getConstant ( Lane , DL , XLenVT ) , TrueMask , VL ) ; return convertFromScalableVector ( VT , Gather , DAG , Subtarget ) ; } } bool IsSelect = all_of ( enumerate ( SVN -> getMask ( ) ) , [ & ] ( const auto & MaskIdx ) { int MaskIndex = MaskIdx . value ( ) ; return MaskIndex < <NUM_LIT> || MaskIdx . index ( ) == ( unsigned ) MaskIndex % NumElts ; } ) ; assert ( ! V1 . isUndef ( ) && <STR_LIT> ) ; SmallVector < SDValue > MaskVals ; SmallVector < SDValue > GatherIndicesLHS , GatherIndicesRHS ; bool SwapOps = DAG . isSplatValue ( V2 ) && ! DAG . isSplatValue ( V1 ) ; bool InvertMask = IsSelect == SwapOps ; for ( int MaskIndex : SVN -> getMask ( ) ) { bool SelectMaskVal = ( MaskIndex < ( int ) NumElts ) ^ InvertMask ; MaskVals . push_back ( DAG . getConstant ( SelectMaskVal , DL , XLenVT ) ) ; if ( ! IsSelect ) { bool IsLHSOrUndefIndex = MaskIndex < ( int ) NumElts ; GatherIndicesLHS . push_back ( IsLHSOrUndefIndex && MaskIndex >= <NUM_LIT> ? DAG . getConstant ( MaskIndex , DL , XLenVT ) : DAG . getUNDEF ( XLenVT ) ) ; GatherIndicesRHS . push_back ( IsLHSOrUndefIndex ? DAG . getUNDEF ( XLenVT ) : DAG . getConstant ( MaskIndex - NumElts , DL , XLenVT ) ) ; } } if ( SwapOps ) { std :: swap ( V1 , V2 ) ; std :: swap ( GatherIndicesLHS , GatherIndicesRHS ) ; } assert ( MaskVals . size ( ) == NumElts && <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue SelectMask = DAG . getBuildVector ( MaskVT , DL , MaskVals ) ; if ( IsSelect ) return DAG . getNode ( <STR_LIT> , DL , VT , SelectMask , V1 , V2 ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && VT . getVectorNumElements ( ) > <NUM_LIT> ) { return SDValue ( ) ; } unsigned GatherOpc = <STR_LIT> ; MVT IndexVT = VT . changeTypeToInteger ( ) ; if ( IndexVT . getScalarType ( ) . bitsGT ( XLenVT ) ) { GatherOpc = <STR_LIT> ;"
LLVM,RISCV,2830,"Predict the next statement of this code snippet:
 <s> if ( ! Subtarget . useRVVForFixedLengthVectors ( ) ) return false ; if ( VT . getFixedSizeInBits ( ) > <NUM_LIT> * <NUM_LIT> ) return false ; unsigned MinVLen = Subtarget . getMinRVVVectorSizeInBits ( ) ; switch ( VT . getVectorElementType ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : if ( VT . getVectorNumElements ( ) > MinVLen ) return false ; MinVLen /= <NUM_LIT> ; break ; case <STR_LIT> :"
LLVM,RISCV,2831,"Predict the next statement of this code snippet:
 <s> return emitSelectPseudo ( MI , BB ) ; case <STR_LIT> : return emitBuildPairF64Pseudo ( MI , BB ) ; case <STR_LIT> : return emitSplitF64Pseudo ( MI , BB ) ; }"
LLVM,RISCV,2832,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,2833,"Predict the next statement of this code snippet:
 <s> if ( isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = <STR_LIT> ( ShiftedC1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; if ( C1Cost < ShiftedC1Cost ) return false ; } }"
LLVM,RISCV,2834,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2835,"Predict the next statement of this code snippet:
 <s> ExtractElementIdx = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; ExtractBitIdx = Idx ; } else { WideEltVT = LargestEltVT ; WidenVecLen = NumElts / WideEltVT . getSizeInBits ( ) ; ExtractElementIdx = DAG . getNode ( <STR_LIT> , DL , XLenVT , Idx , DAG . getConstant ( Log2_64 ( WideEltVT . getSizeInBits ( ) ) , DL , XLenVT ) ) ; ExtractBitIdx = DAG . getNode ( <STR_LIT> , DL , XLenVT , Idx , DAG . getConstant ( WideEltVT . getSizeInBits ( ) - <NUM_LIT> , DL , XLenVT ) ) ; } MVT WideVT = <STR_LIT> ( WideEltVT , WidenVecLen ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; SDValue ExtractElt = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , ExtractElementIdx ) ; SDValue ShiftRight = DAG . getNode ( <STR_LIT> , DL , XLenVT , ExtractElt , ExtractBitIdx ) ; return DAG . getNode ( <STR_LIT> , DL , XLenVT , ShiftRight , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; } } MVT WideVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; return DAG . getNode ( <STR_LIT> , DL , EltVT , Vec , Idx ) ;"
LLVM,RISCV,2836,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; EVT MaskVT = Op . getValueType ( ) ; assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Src . getSimpleValueType ( ) ; SDValue Mask , VL ; if ( IsVPTrunc ) { Mask = Op . getOperand ( <NUM_LIT> ) ; VL = Op . getOperand ( <NUM_LIT> ) ; } MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; if ( IsVPTrunc ) { MVT MaskContainerVT = getContainerForFixedLengthVector ( Mask . getSimpleValueType ( ) ) ; Mask = convertToScalableVector ( MaskContainerVT , Mask , DAG , Subtarget ) ; } } if ( ! IsVPTrunc ) {"
LLVM,RISCV,2837,"Predict the next statement of this code snippet:
 <s> assert ( VT . isVector ( ) && <STR_LIT> ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return lowerVectorMaskTruncLike ( Op , DAG ) ; MVT DstEltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT SrcEltVT = SrcVT . getVectorElementType ( ) ; assert ( DstEltVT . bitsLT ( SrcEltVT ) && isPowerOf2_64 ( DstEltVT . getSizeInBits ( ) ) && isPowerOf2_64 ( SrcEltVT . getSizeInBits ( ) ) && <STR_LIT> ) ; MVT ContainerVT = SrcVT ; SDValue Mask , VL ; if ( IsVPTrunc ) { Mask = Op . getOperand ( <NUM_LIT> ) ; VL = Op . getOperand ( <NUM_LIT> ) ; } if ( SrcVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( SrcVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; if ( IsVPTrunc ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } SDValue Result = Src ; if ( ! IsVPTrunc ) { std :: tie ( Mask , VL ) = getDefaultVLOps ( SrcVT , ContainerVT , DL , DAG , Subtarget ) ; } LLVMContext & Context = * DAG . getContext ( ) ; const ElementCount Count = ContainerVT . getVectorElementCount ( ) ;"
LLVM,RISCV,2838,"Predict the next statement of this code snippet:
 <s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT SrcVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Src = convertToScalableVector ( SrcVT , Src , DAG , Subtarget ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ZeroSplat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Zero , VL ) ; SDValue SplatValue = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> , DL , XLenVT ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatValue , VL ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , Splat , ZeroSplat , VL ) ;"
LLVM,RISCV,2839,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT SrcVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Src = convertToScalableVector ( SrcVT , Src , DAG , Subtarget ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ZeroSplat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Zero , VL ) ; SDValue SplatValue = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> , DL , XLenVT ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatValue , VL ) ;"
LLVM,RISCV,2840,"Predict the next statement of this code snippet:
 <s> if ( SrcVT . isInteger ( ) ) { assert ( DstVT . isFloatingPoint ( ) && <STR_LIT> ) ; MVT InterimFVT = DstVT ; if ( SrcEltSize > ( <NUM_LIT> * DstEltSize ) ) { assert ( SrcEltSize == ( <NUM_LIT> * DstEltSize ) && <STR_LIT> ) ; assert ( DstVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; InterimFVT = <STR_LIT> ( <STR_LIT> , DstVT . getVectorElementCount ( ) ) ; } Result = DAG . getNode ( <ISA_LIT>ISDOpc , DL , InterimFVT , Src , Mask , VL ) ; if ( InterimFVT != DstVT ) { Src = Result ; Result = DAG . getNode ( <STR_LIT> , DL , DstVT , Src , Mask , VL ) ; } } else { assert ( SrcVT . isFloatingPoint ( ) && DstVT . isInteger ( ) && <STR_LIT> ) ; if ( DstEltSize == <NUM_LIT> ) { assert ( SrcEltSize >= <NUM_LIT> && <STR_LIT> ) ; MVT InterimIVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize ) , DstVT . getVectorElementCount ( ) ) ; Result = DAG . getNode ( <ISA_LIT>ISDOpc , DL , InterimIVT , Src , Mask , VL ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , InterimIVT , DAG . getUNDEF ( InterimIVT ) , SplatZero ) ; Result = DAG . getNode ( <STR_LIT> , DL , DstVT , Result , SplatZero , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; } else { MVT InterimIVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize / <NUM_LIT> ) , DstVT . getVectorElementCount ( ) ) ; Result = DAG . getNode ( <ISA_LIT>ISDOpc , DL , InterimIVT , Src , Mask , VL ) ; while ( InterimIVT != DstVT ) { SrcEltSize /= <NUM_LIT> ; Src = Result ; InterimIVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize / <NUM_LIT> ) , DstVT . getVectorElementCount ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , InterimIVT , Src , Mask , VL ) ; } } } } MVT VT = Op . getSimpleValueType ( ) ; if ( ! VT . isFixedLengthVector ( ) ) return Result ;"
LLVM,RISCV,2841,"Predict the next statement of this code snippet:
 <s> assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; <ISA_LIT>VSEW ElementWidth = static_cast < <ISA_LIT>VSEW > ( Log2_32 ( SEW / <NUM_LIT> ) ) ; <ISA_LIT>VLMUL Multiplier = static_cast < <ISA_LIT>VLMUL > ( VLMul ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) ; if ( VLIndex >= <NUM_LIT> ) { Register DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( MI . getOperand ( VLIndex ) . getReg ( ) ) ; } else MIB . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MIB . addImm ( <ISA_LIT>VType :: encodeVTYPE ( Multiplier , ElementWidth , true , false ) ) ;"
LLVM,RISCV,2842,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ArgVT = Ins [ i ] . VT ; <STR_LIT> ArgFlags = Ins [ i ] . Flags ; Type * ArgTy = nullptr ; if ( IsRet ) ArgTy = FType -> getReturnType ( ) ; else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet , ArgTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << '\n' ) ; llvm_unreachable ( nullptr ) ;"
LLVM,RISCV,2843,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . hasStdExtV ( ) ) preAssignMask ( Outs , FirstMaskArgument , CCInfo ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; i ++ ) { MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; Type * OrigTy = CLI ? CLI -> getArgs ( ) [ Outs [ i ] . OrigArgIndex ] . Ty : nullptr ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ;"
LLVM,RISCV,2844,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) preAssignMask ( Outs , FirstMaskArgument , CCInfo ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ;"
LLVM,RISCV,2845,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr , * this , FirstMaskArgument ) ) return false ; }"
LLVM,RISCV,2846,"Predict the next statement of this code snippet:
 <s> LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } Register Reg ; if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR16s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR32s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s ) ; else if ( ValVT . isScalableVector ( ) ) { const TargetRegisterClass * RC = TLI . getRegClassFor ( ValVT ) ; if ( RC == & <STR_LIT> ) { if ( FirstMaskArgument . hasValue ( ) && ValNo == FirstMaskArgument . getValue ( ) ) { Reg = State . AllocateReg ( <STR_LIT> ) ; } else { Reg = State . AllocateReg ( ArgVRs ) ; } } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM2s ) ; } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM4s ) ; } else if ( RC == & <STR_LIT> ) {"
LLVM,RISCV,2847,"Predict the next statement of this code snippet:
 <s> static SDValue combineGREVI_GORCI ( SDNode * N , SelectionDAG & DAG ) { unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != N -> getOpcode ( ) ) return SDValue ( ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; unsigned CombinedShAmt ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) CombinedShAmt = ShAmt1 | ShAmt2 ;"
LLVM,RISCV,2848,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LHS -> Op , DAG . getTargetConstant ( LHS -> ShAmt , DL , Subtarget . getXLenVT ( ) ) ) ; } } return SDValue ( ) ;"
LLVM,RISCV,2849,"Predict the next statement of this code snippet:
 <s> if ( VA . getLocVT ( ) . isInteger ( ) && VA . getValVT ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ;"
LLVM,RISCV,2850,"Predict the next statement of this code snippet:
 <s> if ( VT . isScalarInteger ( ) ) { if ( ! Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) ) return false ; if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) {"
LLVM,RISCV,2851,"Predict the next statement of this code snippet:
 <s> return addVSetVL ( MI , BB , VLIndex , SEWIndex , RVV -> VLMul ) ; } switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,2852,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,2853,"Predict the next statement of this code snippet:
 <s> break ; NODE_NAME_CASE ( RET_FLAG ) NODE_NAME_CASE ( URET_FLAG ) NODE_NAME_CASE ( SRET_FLAG ) NODE_NAME_CASE ( MRET_FLAG ) NODE_NAME_CASE ( CALL ) NODE_NAME_CASE ( SELECT_CC ) NODE_NAME_CASE ( BuildPairF64 ) NODE_NAME_CASE ( SplitF64 ) NODE_NAME_CASE ( TAIL ) NODE_NAME_CASE ( SLLW ) NODE_NAME_CASE ( SRAW ) NODE_NAME_CASE ( SRLW ) NODE_NAME_CASE ( DIVW ) NODE_NAME_CASE ( DIVUW ) NODE_NAME_CASE ( REMUW ) NODE_NAME_CASE ( ROLW ) NODE_NAME_CASE ( RORW ) NODE_NAME_CASE ( FSLW ) NODE_NAME_CASE ( FSRW ) NODE_NAME_CASE ( FMV_H_X ) NODE_NAME_CASE ( FMV_X_ANYEXTH ) NODE_NAME_CASE ( FMV_W_X_RV64 ) NODE_NAME_CASE ( FMV_X_ANYEXTW_RV64 ) NODE_NAME_CASE ( READ_CYCLE_WIDE ) NODE_NAME_CASE ( GREVI ) NODE_NAME_CASE ( GREVIW ) NODE_NAME_CASE ( GORCI ) NODE_NAME_CASE ( GORCIW ) }"
LLVM,RISCV,2854,"Predict the next statement of this code snippet:
 <s> break ;"
LLVM,RISCV,2855,"Predict the next statement of this code snippet:
 <s> unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes ; } for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const Register Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store ) ; } RVFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ; } if ( ! OutChains . empty ( ) ) { OutChains . push_back ( Chain ) ;"
LLVM,RISCV,2856,"Predict the next statement of this code snippet:
 <s> assert ( II -> ExtendedOperand < Op . getNumOperands ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [ II -> ExtendedOperand ] ; if ( ScalarOp . getValueType ( ) == <STR_LIT> || ScalarOp . getValueType ( ) == <STR_LIT> || ScalarOp . getValueType ( ) == <STR_LIT> ) { ScalarOp = DAG . getNode ( <STR_LIT> , DL , Subtarget . getXLenVT ( ) , ScalarOp ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Operands ) ; } } } } switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;"
LLVM,RISCV,2857,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( ( ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) || Subtarget . hasStdExtZfh ( ) ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . hasStdExtZfh ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , Subtarget . getXLenVT ( ) , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } else if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } return SDValue ( ) ; } case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasStdExtZbp ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ;"
LLVM,RISCV,2858,"Predict the next statement of this code snippet:
 <s> return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( ( ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) || Subtarget . hasStdExtZfh ( ) ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . hasStdExtZfh ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , Subtarget . getXLenVT ( ) , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } else if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } return SDValue ( ) ; } case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasStdExtZbp ( ) && <STR_LIT> ) ;"
LLVM,RISCV,2859,"Predict the next statement of this code snippet:
 <s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; if ( CallConv == CallingConv :: GHC && ! RVLocs . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; if ( STI . isRegisterReservedByUser ( RegLo ) || STI . isRegisterReservedByUser ( RegHi ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; if ( STI . isRegisterReservedByUser ( VA . getLocReg ( ) ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ;"
LLVM,RISCV,2860,"Predict the next statement of this code snippet:
 <s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; if ( STI . isRegisterReservedByUser ( RegLo ) || STI . isRegisterReservedByUser ( RegHi ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; if ( STI . isRegisterReservedByUser ( VA . getLocReg ( ) ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) { RetOps . push_back ( Glue ) ; } const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { if ( ! Func . getReturnType ( ) -> isVoidTy ( ) ) report_fatal_error ( <STR_LIT> ) ;"
LLVM,RISCV,2861,"Predict the next statement of this code snippet:
 <s> auto CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; normaliseSetCC ( LHS , RHS , CCVal ) ; SDValue TargetCC = DAG . getConstant ( CCVal , DL , XLenVT ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ; } SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SetNE = DAG . getConstant ( <STR_LIT> , DL , XLenVT ) ; SDValue Ops [ ] = { CondV , Zero , SetNE , TrueV , FalseV } ;"
LLVM,RISCV,2862,"Predict the next statement of this code snippet:
 <s> unsigned MaskIdx = Log2_64 ( ShAmt ) ; if ( MaskIdx >= array_lengthof ( BitmanipMasks ) ) return None ; auto Src = Op . getOperand ( <NUM_LIT> ) ; unsigned Width = Op . getValueType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; auto ExpMask = BitmanipMasks [ MaskIdx ] & maskTrailingOnes < uint64_t > ( Width ) ; bool SHLExpMask = IsSHL ; if ( ! Mask ) { if ( Src . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) { Mask = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2863,"Predict the next statement of this code snippet:
 <s> return DCI . CombineTo ( N , Lo , Hi ) ; } if ( ! ( Op0 . getOpcode ( ) == <STR_LIT> || Op0 . getOpcode ( ) == <STR_LIT> ) || ! Op0 . getNode ( ) -> hasOneUse ( ) ) break ; SDValue NewSplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; SDValue Lo = NewSplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = NewSplitF64 . getValue ( <NUM_LIT> ) ; APInt SignBit = APInt :: getSignMask ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } assert ( Op0 . getOpcode ( ) == <STR_LIT> ) ; SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( ~ SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; APInt LHSMask = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; APInt RHSMask = APInt :: getLowBitsSet ( RHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , LHSMask , DCI ) || SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , RHSMask , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue ShAmt = N -> getOperand ( <NUM_LIT> ) ; APInt OpMask = APInt :: getLowBitsSet ( Op0 . getValueSizeInBits ( ) , <NUM_LIT> ) ; APInt ShAmtMask = APInt :: getLowBitsSet ( ShAmt . getValueSizeInBits ( ) , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( Op0 , OpMask , DCI ) || SimplifyDemandedBits ( Op1 , OpMask , DCI ) || SimplifyDemandedBits ( ShAmt , ShAmtMask , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ;"
LLVM,RISCV,2864,"Predict the next statement of this code snippet:
 <s> unsigned NumArgs = Args . size ( ) ; for ( unsigned I = <NUM_LIT> ; I != NumArgs ; ++ I ) { MVT ArgVT = Args [ I ] . VT ; if ( ! ArgVT . isScalableVector ( ) || ArgVT . getVectorElementType ( ) . SimpleTy != <STR_LIT> ) continue ; FirstMaskArgument = I ; break ;"
LLVM,RISCV,2865,"Predict the next statement of this code snippet:
 <s> static void preAssignMask ( const ArgTy & Args , Optional < unsigned > & FirstMaskArgument , CCState & CCInfo ) { unsigned NumArgs = Args . size ( ) ; for ( unsigned I = <NUM_LIT> ; I != NumArgs ; ++ I ) { MVT ArgVT = Args [ I ] . VT ; if ( ! ArgVT . isScalableVector ( ) || ArgVT . getVectorElementType ( ) . SimpleTy != <STR_LIT> ) continue ; FirstMaskArgument = I ; break ;"
LLVM,RISCV,2866,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ; const TargetRegisterClass * RC = TLI . getRegClassFor ( LocVT . getSimpleVT ( ) ) ;"
LLVM,RISCV,2867,"Predict the next statement of this code snippet:
 <s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ;"
LLVM,RISCV,2868,"Predict the next statement of this code snippet:
 <s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Commute ) std :: swap ( Op0 , Op1 ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> || Op1 . getOpcode ( ) == <STR_LIT> ) && Op1 . hasOneUse ( ) && Op1 . getOperand ( <NUM_LIT> ) == Mask && Op1 . getOperand ( <NUM_LIT> ) == VL ) { unsigned ExtOpc = Op1 . getOpcode ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getValueType ( ) != NarrowVT ) Op1 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op1 , Mask , VL ) ; unsigned WOpc ;"
LLVM,RISCV,2869,"Predict the next statement of this code snippet:
 <s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != N -> getOpcode ( ) ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ;"
LLVM,RISCV,2870,"Predict the next statement of this code snippet:
 <s> static SDValue combineGREVI_GORCI ( SDNode * N , SelectionDAG & DAG ) { bool IsGORC = N -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsGORC || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != N -> getOpcode ( ) ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; unsigned CombinedShAmt ;"
LLVM,RISCV,2871,"Predict the next statement of this code snippet:
 <s> } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( ! Op1 . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; if ( Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt && DAG . ComputeNumSignBits ( Op1 ) > ( ScalarBits - NarrowSize ) ) { } else { APInt Mask = APInt :: getBitsSetFrom ( ScalarBits , NarrowSize ) ; if ( DAG . MaskedValueIsZero ( Op1 , Mask ) ) IsVWMULSU = IsSignExt ; else return SDValue ( ) ; } Op1 = DAG . getNode ( <STR_LIT> , DL , NarrowVT , DAG . getUNDEF ( NarrowVT ) , Op1 , VL ) ; } else return SDValue ( ) ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2872,"Predict the next statement of this code snippet:
 <s> unsigned BitWidth = IsWInstruction ? <NUM_LIT> : VT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( BitWidth ) && <STR_LIT> ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; if ( BitWidth < <NUM_LIT> || ShAmt1 != ( BitWidth / <NUM_LIT> ) || ShAmt2 != ( BitWidth - <NUM_LIT> ) ) return SDValue ( ) ; Src = Src . getOperand ( <NUM_LIT> ) ; unsigned CombinedShAmt = ShAmt1 ^ ShAmt2 ; if ( CombinedShAmt == <NUM_LIT> ) return Src ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( CombinedShAmt , DL , N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) ; if ( ! IsWInstruction ) return Res ;"
LLVM,RISCV,2873,"Predict the next statement of this code snippet:
 <s> if ( ShAmt & Shift ) { uint64_t Mask = GREVMasks [ Stage ] ; uint64_t Res = ( ( x & Mask ) << Shift ) | ( ( x >> Shift ) & Mask ) ; if ( IsGORC ) Res |= x ; x = Res ; }"
LLVM,RISCV,2874,"Predict the next statement of this code snippet:
 <s> static const uint64_t GREVMasks [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned Stage = <NUM_LIT> ; Stage != <NUM_LIT> ; ++ Stage ) { unsigned Shift = <NUM_LIT> << Stage ; if ( ShAmt & Shift ) { uint64_t Mask = GREVMasks [ Stage ] ; uint64_t Res = ( ( x & Mask ) << Shift ) | ( ( x >> Shift ) & Mask ) ;"
LLVM,RISCV,2875,"Predict the next statement of this code snippet:
 <s> Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: urem ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: udiv ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleTZ = Known2 . trunc ( <NUM_LIT> ) . countMaxTrailingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleTZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleLZ = Known2 . trunc ( <NUM_LIT> ) . countMaxLeadingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleLZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( auto * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned ShAmt = C -> getZExtValue ( ) & ( Known . getBitWidth ( ) - <NUM_LIT> ) ; bool IsGORC = Op . getOpcode ( ) == <STR_LIT> ; Known . Zero = ~ computeGREVOrGORC ( ~ Known . Zero . getZExtValue ( ) , ShAmt , IsGORC ) ; Known . One = computeGREVOrGORC ( Known . One . getZExtValue ( ) , ShAmt , IsGORC ) ; } break ; } case <STR_LIT> : { unsigned MinVLenB = std :: min ( <NUM_LIT> , Subtarget . getMinVLen ( ) ) / <NUM_LIT> ; if ( MinVLenB > <NUM_LIT> ) Known . Zero . setLowBits ( Log2_32 ( MinVLenB ) ) ; Known . Zero . setBitsFrom ( <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = Op . getConstantOperandVal ( Opc == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; switch ( IntNo ) {"
LLVM,RISCV,2876,"Predict the next statement of this code snippet:
 <s> } switch ( getTargetMachine ( ) . getCodeModel ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case CodeModel :: Small : { SDValue AddrHi = getTargetNode ( N , DL , Ty , DAG , <STR_LIT> ) ; SDValue AddrLo = getTargetNode ( N , DL , Ty , DAG , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , AddrLo ) , <NUM_LIT> ) ; } case CodeModel :: Medium : { SDValue Addr = getTargetNode ( N , DL , Ty , DAG , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ;"
LLVM,RISCV,2877,"Predict the next statement of this code snippet:
 <s> assert ( ContainerVT . isScalableVector ( ) && <STR_LIT> ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue VL = VecVT . isFixedLengthVector ( ) ? DAG . getConstant ( VecVT . getVectorNumElements ( ) , DL , XLenVT ) : DAG . getRegister ( <STR_LIT> , XLenVT ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , VL ) ; return { Mask , VL } ;"
LLVM,RISCV,2878,"Predict the next statement of this code snippet:
 <s> if ( UseGOT ) { SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MemOp = MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , LLT ( Ty . getSimpleVT ( ) ) , Align ( Ty . getFixedSizeInBits ( ) / <NUM_LIT> ) ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load . getNode ( ) ) , { MemOp } ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load , TPReg ) ; } SDValue AddrHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrAdd = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrLo = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ;"
LLVM,RISCV,2879,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ;"
LLVM,RISCV,2880,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: hasBitTest ( SDValue X , SDValue Y ) const {"
LLVM,RISCV,2881,"Predict the next statement of this code snippet:
 <s> return C && C -> getAPIntValue ( ) . ule ( <NUM_LIT> ) ;"
LLVM,RISCV,2882,"Predict the next statement of this code snippet:
 <s> int StartIdx = i - ( M % Size ) ; if ( StartIdx == <NUM_LIT> ) return - <NUM_LIT> ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : Size - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return - <NUM_LIT> ; int MaskSrc = M < Size ? <NUM_LIT> : <NUM_LIT> ; int & TargetSrc = StartIdx < <NUM_LIT> ? HiSrc : LoSrc ;"
LLVM,RISCV,2883,"Predict the next statement of this code snippet:
 <s> if ( StartIdx == <NUM_LIT> ) return - <NUM_LIT> ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : Size - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return - <NUM_LIT> ; int MaskSrc = M < Size ? <NUM_LIT> : <NUM_LIT> ; int & TargetSrc = StartIdx < <NUM_LIT> ? HiSrc : LoSrc ; if ( TargetSrc < <NUM_LIT> ) TargetSrc = MaskSrc ; else if ( TargetSrc != MaskSrc ) return - <NUM_LIT> ; } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( LoSrc >= <NUM_LIT> || HiSrc >= <NUM_LIT> ) && <STR_LIT> ) ;"
LLVM,RISCV,2884,"Predict the next statement of this code snippet:
 <s> const APInt & C2 = C2Node -> getAPIntValue ( ) ; if ( C1 . isSignedIntN ( <NUM_LIT> ) && ! ( C1 * C2 ) . isSignedIntN ( <NUM_LIT> ) ) return false ; return true ;"
LLVM,RISCV,2885,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const {"
LLVM,RISCV,2886,"Predict the next statement of this code snippet:
 <s> int LoSrc , HiSrc ; return ( isElementRotate ( LoSrc , HiSrc , M ) > <NUM_LIT> ) || isInterleaveShuffle ( M , SVT , SwapSources , Subtarget ) ;"
LLVM,RISCV,2887,"Predict the next statement of this code snippet:
 <s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; X = convertToScalableVector ( ContainerVT , X , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ;"
LLVM,RISCV,2888,"Predict the next statement of this code snippet:
 <s> X = convertToScalableVector ( ContainerVT , X , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ;"
LLVM,RISCV,2889,"Predict the next statement of this code snippet:
 <s> auto * Load = cast < LoadSDNode > ( Op ) ; assert ( allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , Load -> getMemoryVT ( ) , * Load -> getMemOperand ( ) ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; bool IsMaskOp = VT . getVectorElementType ( ) == <STR_LIT> ; SDValue IntID = DAG . getTargetConstant ( IsMaskOp ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ;"
LLVM,RISCV,2890,"Predict the next statement of this code snippet:
 <s> StoreVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , StoreVal , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue NewValue = convertToScalableVector ( ContainerVT , StoreVal , DAG , Subtarget ) ; bool IsMaskOp = VT . getVectorElementType ( ) == <STR_LIT> ; SDValue IntID = DAG . getTargetConstant ( IsMaskOp ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ;"
LLVM,RISCV,2891,"Predict the next statement of this code snippet:
 <s> SDValue ScalarSplat = lowerScalarSplat ( SDValue ( ) , ScalarVal , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , DAG . getUNDEF ( M1VT ) , VectorVal , ScalarSplat , Mask , VL ) ;"
LLVM,RISCV,2892,"Predict the next statement of this code snippet:
 <s> MVT VecVT = VectorVal . getSimpleValueType ( ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; VectorVal = convertToScalableVector ( ContainerVT , VectorVal , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( VectorVal . getSimpleValueType ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ;"
LLVM,RISCV,2893,"Predict the next statement of this code snippet:
 <s> assert ( VT . isVector ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Src = DAG . getFreeze ( Op . getOperand ( <NUM_LIT> ) ) ; SDValue Abs = DAG . getNode ( <STR_LIT> , DL , VT , Src ) ; const fltSemantics & FltSem = DAG . EVTToAPFloatSemantics ( VT ) ; bool Ignored ; APFloat Point5Pred = APFloat ( <NUM_LIT> ) ; Point5Pred . convert ( FltSem , APFloat :: rmNearestTiesToEven , & Ignored ) ; Point5Pred . next ( true ) ; SDValue Adjust = DAG . getNode ( <STR_LIT> , DL , VT , Abs , DAG . getConstantFP ( Point5Pred , DL , VT ) ) ; MVT IntVT = VT . changeVectorElementTypeToInteger ( ) ; SDValue Truncated = DAG . getNode ( <STR_LIT> , DL , IntVT , Adjust ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , Src ) ;"
LLVM,RISCV,2894,"Predict the next statement of this code snippet:
 <s> SDValue Truncated = DAG . getNode ( <STR_LIT> , DL , IntVT , Adjust ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , Src ) ; unsigned Precision = APFloat :: semanticsPrecision ( FltSem ) ; APFloat MaxVal = APFloat ( FltSem ) ; MaxVal . convertFromAPInt ( APInt :: getOneBitSet ( Precision , Precision - <NUM_LIT> ) , false , APFloat :: rmNearestTiesToEven ) ;"
LLVM,RISCV,2895,"Predict the next statement of this code snippet:
 <s> SDValue Src = DAG . getFreeze ( Op . getOperand ( <NUM_LIT> ) ) ; MVT IntVT = VT . changeVectorElementTypeToInteger ( ) ; SDValue Truncated = DAG . getNode ( <STR_LIT> , DL , IntVT , Src ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated ) ; MVT SetccVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue Adjust = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ) ; SDValue NeedAdjust = DAG . getSetCC ( DL , SetccVT , Truncated , Src , <STR_LIT> ) ; Truncated = DAG . getSelect ( DL , VT , NeedAdjust , Adjust , Truncated ) ; } else if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue Adjust = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ) ; SDValue NeedAdjust = DAG . getSetCC ( DL , SetccVT , Truncated , Src , <STR_LIT> ) ; Truncated = DAG . getSelect ( DL , VT , NeedAdjust , Adjust , Truncated ) ; } Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , Src ) ; const fltSemantics & FltSem = DAG . EVTToAPFloatSemantics ( VT ) ; unsigned Precision = APFloat :: semanticsPrecision ( FltSem ) ; APFloat MaxVal = APFloat ( FltSem ) ; MaxVal . convertFromAPInt ( APInt :: getOneBitSet ( Precision , Precision - <NUM_LIT> ) , false , APFloat :: rmNearestTiesToEven ) ; SDValue MaxValNode = DAG . getConstantFP ( MaxVal , DL , VT ) ;"
LLVM,RISCV,2896,"Predict the next statement of this code snippet:
 <s> } } SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ValInVec ; if ( IsLegalInsert ) { unsigned Opc = VecVT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; if ( isNullConstant ( Idx ) ) { Vec = DAG . getNode ( Opc , DL , ContainerVT , Vec , Val , VL ) ; if ( ! VecVT . isFixedLengthVector ( ) ) return Vec ; return convertFromScalableVector ( VecVT , Vec , DAG , Subtarget ) ; } ValInVec = DAG . getNode ( Opc , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Val , VL ) ; } else { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ValLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , Zero ) ; SDValue ValHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , One ) ; MVT I32ContainerVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue I32Mask = getDefaultScalableVLOps ( I32ContainerVT , DL , DAG , Subtarget ) . first ; SDValue InsertI64VL = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; ValInVec = DAG . getNode ( <STR_LIT> , DL , I32ContainerVT , DAG . getUNDEF ( I32ContainerVT ) , Zero , InsertI64VL ) ; ValInVec = DAG . getNode ( <STR_LIT> , DL , I32ContainerVT , DAG . getUNDEF ( I32ContainerVT ) , ValInVec , ValHi , I32Mask , InsertI64VL ) ; ValInVec = DAG . getNode ( <STR_LIT> , DL , I32ContainerVT , DAG . getUNDEF ( I32ContainerVT ) , ValInVec , ValLo , I32Mask , InsertI64VL ) ; ValInVec = DAG . getBitcast ( ContainerVT , ValInVec ) ;"
LLVM,RISCV,2897,"Predict the next statement of this code snippet:
 <s> } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; bool IsLegalInsert = Subtarget . is64Bit ( ) || Val . getValueType ( ) != <STR_LIT> ; if ( ! IsLegalInsert && isa < ConstantSDNode > ( Val ) ) { const auto * CVal = cast < ConstantSDNode > ( Val ) ; if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) { IsLegalInsert = true ; Val = DAG . getConstant ( CVal -> getSExtValue ( ) , DL , <STR_LIT> ) ; } } SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ValInVec ; if ( IsLegalInsert ) { unsigned Opc = VecVT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; if ( isNullConstant ( Idx ) ) { Vec = DAG . getNode ( Opc , DL , ContainerVT , Vec , Val , VL ) ; if ( ! VecVT . isFixedLengthVector ( ) ) return Vec ; return convertFromScalableVector ( VecVT , Vec , DAG , Subtarget ) ; } ValInVec = DAG . getNode ( Opc , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Val , VL ) ; } else { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ;"
LLVM,RISCV,2898,"Predict the next statement of this code snippet:
 <s> bool HasPassthru = Passthru && ! Passthru . isUndef ( ) ; if ( ! HasPassthru && ! Passthru ) Passthru = DAG . getUNDEF ( VT ) ; if ( VT . isFloatingPoint ( ) ) { if ( isOneConstant ( VL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Passthru , Scalar , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Passthru , Scalar , VL ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ;"
LLVM,RISCV,2899,"Predict the next statement of this code snippet:
 <s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ;"
LLVM,RISCV,2900,"Predict the next statement of this code snippet:
 <s> SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , XLenMinus1 ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftLeftHi1 = DAG . getNode ( <STR_LIT> , DL , VT , Hi , One ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi1 , XLenMinus1Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRightLo , ShiftLeftHi ) ; SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ;"
LLVM,RISCV,2901,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerShiftRightParts ( SDValue Op , SelectionDAG & DAG , bool IsSRA ) const { SDLoc DL ( Op ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; unsigned ShiftRightOp = IsSRA ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ;"
LLVM,RISCV,2902,"Predict the next statement of this code snippet:
 <s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; if ( VecVT . isFixedLengthVector ( ) ) { MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Res = splatPartsI64WithVL ( DL , ContainerVT , SDValue ( ) , Lo , Hi , VL , DAG ) ; return convertFromScalableVector ( VecVT , Res , DAG , Subtarget ) ; } if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ;"
LLVM,RISCV,2903,"Predict the next statement of this code snippet:
 <s> if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Lo , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } if ( Hi . getOpcode ( ) == <STR_LIT> && Hi . getOperand ( <NUM_LIT> ) == Lo && isa < ConstantSDNode > ( Hi . getOperand ( <NUM_LIT> ) ) && Hi . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Lo , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ;"
LLVM,RISCV,2904,"Predict the next statement of this code snippet:
 <s> if ( isPowerOf2_64 ( StepValImm ) ) { SDValue StepVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , DAG . getConstant ( Log2_64 ( StepValImm ) , DL , XLenVT ) ) ; StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ; } else { SDValue StepVal = lowerScalarSplat ( SDValue ( ) , DAG . getConstant ( StepValImm , DL , VT . getVectorElementType ( ) ) , VL , VT , DL , DAG , Subtarget ) ; StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ; } }"
LLVM,RISCV,2905,"Predict the next statement of this code snippet:
 <s> StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ; } else { SDValue StepVal = lowerScalarSplat ( SDValue ( ) , DAG . getConstant ( StepValImm , DL , VT . getVectorElementType ( ) ) , VL , VT , DL , DAG , Subtarget ) ; StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ; } } return StepVec ;"
LLVM,RISCV,2906,"Predict the next statement of this code snippet:
 <s> if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ;"
LLVM,RISCV,2907,"Predict the next statement of this code snippet:
 <s> } MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; MVT I1ContainerVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; SDValue CC = convertToScalableVector ( I1ContainerVT , Src , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SplatTrueVal = DAG . getConstant ( ExtTrueVal , DL , XLenVT ) ;"
LLVM,RISCV,2908,"Predict the next statement of this code snippet:
 <s> std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SplatTrueVal = DAG . getConstant ( ExtTrueVal , DL , XLenVT ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatZero , VL ) ;"
LLVM,RISCV,2909,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerVectorMaskTrunc ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT MaskVT = Op . getValueType ( ) ; assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Src . getSimpleValueType ( ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SplatOne = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatOne ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatZero ) ; if ( VecVT . isScalableVector ( ) ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Src , SplatOne ) ; return DAG . getSetCC ( DL , MaskVT , Trunc , SplatZero , <STR_LIT> ) ; } SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; MVT MaskContainerVT = ContainerVT . changeVectorElementType ( <STR_LIT> ) ;"
LLVM,RISCV,2910,"Predict the next statement of this code snippet:
 <s> ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SplatOne = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatOne ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatZero ) ; if ( VecVT . isScalableVector ( ) ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Src , SplatOne ) ; return DAG . getSetCC ( DL , MaskVT , Trunc , SplatZero , <STR_LIT> ) ; } SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; MVT MaskContainerVT = ContainerVT . changeVectorElementType ( <STR_LIT> ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , SplatOne , Mask , VL ) ;"
LLVM,RISCV,2911,"Predict the next statement of this code snippet:
 <s> return DAG . getNode ( <STR_LIT> , DL , VecVT , Res , Lo , DAG . getIntPtrConstant ( LoVT . getVectorMinNumElements ( ) , DL ) ) ; } IntVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; GatherOpc = <STR_LIT> ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultScalableVLOps ( VecVT , DL , DAG , Subtarget ) ; unsigned MinElts = VecVT . getVectorMinNumElements ( ) ; SDValue VLMax = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ; SDValue VLMinus1 = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; bool IsRV32E64 = ! Subtarget . is64Bit ( ) && IntVT . getVectorElementType ( ) == <STR_LIT> ; SDValue SplatVL ; if ( ! IsRV32E64 ) SplatVL = DAG . getSplatVector ( IntVT , DL , VLMinus1 ) ; else SplatVL = DAG . getNode ( <STR_LIT> , DL , IntVT , DAG . getUNDEF ( IntVT ) , VLMinus1 , DAG . getRegister ( <STR_LIT> , XLenVT ) ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , IntVT , Mask , VL ) ;"
LLVM,RISCV,2912,"Predict the next statement of this code snippet:
 <s> MVT IntVT = VecVT . changeVectorElementTypeToInteger ( ) ; if ( ( MaxVLMAX == <NUM_LIT> || MaxVLMAX > <NUM_LIT> ) && EltSize == <NUM_LIT> ) { if ( MinSize == ( <NUM_LIT> * <STR_LIT> ) ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; EVT LoVT , HiVT ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VecVT ) ; Lo = DAG . getNode ( <STR_LIT> , DL , LoVT , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , HiVT , Hi ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Hi , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VecVT , Res , Lo , DAG . getIntPtrConstant ( LoVT . getVectorMinNumElements ( ) , DL ) ) ; } IntVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; GatherOpc = <STR_LIT> ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultScalableVLOps ( VecVT , DL , DAG , Subtarget ) ; unsigned MinElts = VecVT . getVectorMinNumElements ( ) ; SDValue VLMax = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ; SDValue VLMinus1 = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; bool IsRV32E64 = ! Subtarget . is64Bit ( ) && IntVT . getVectorElementType ( ) == <STR_LIT> ; SDValue SplatVL ; if ( ! IsRV32E64 ) SplatVL = DAG . getSplatVector ( IntVT , DL , VLMinus1 ) ;"
LLVM,RISCV,2913,"Predict the next statement of this code snippet:
 <s> SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT VecVT = Op . getSimpleValueType ( ) ; unsigned MinElts = VecVT . getVectorMinNumElements ( ) ; SDValue VLMax = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ; int64_t ImmValue = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; SDValue DownOffset , UpOffset ; if ( ImmValue >= <NUM_LIT> ) { DownOffset = DAG . getConstant ( ImmValue , DL , XLenVT ) ;"
LLVM,RISCV,2914,"Predict the next statement of this code snippet:
 <s> assert ( DstVT . isFloatingPoint ( ) && <STR_LIT> ) ; if ( SrcEltSize == <NUM_LIT> ) { MVT IntVT = DstVT . changeVectorElementTypeToInteger ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ZeroSplat = DAG . getNode ( <STR_LIT> , DL , IntVT , DAG . getUNDEF ( IntVT ) , Zero , VL ) ; SDValue One = DAG . getConstant ( <ISA_LIT>ISDExtOpc == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> , DL , XLenVT ) ; SDValue OneSplat = DAG . getNode ( <STR_LIT> , DL , IntVT , DAG . getUNDEF ( IntVT ) , One , VL ) ; Src = DAG . getNode ( <STR_LIT> , DL , IntVT , Src , OneSplat , ZeroSplat , VL ) ; } else if ( DstEltSize > ( <NUM_LIT> * SrcEltSize ) ) { MVT IntVT = <STR_LIT> ( <STR_LIT> ( DstEltSize / <NUM_LIT> ) , DstVT . getVectorElementCount ( ) ) ; Src = DAG . getNode ( <ISA_LIT>ISDExtOpc , DL , IntVT , { Src , Mask , VL } ) ; } Result = DAG . getNode ( <ISA_LIT>ISDOpc , DL , DstVT , { Src , Mask , VL } ) ; } else { assert ( SrcVT . isFloatingPoint ( ) && DstVT . isInteger ( ) && <STR_LIT> ) ; if ( DstEltSize > ( <NUM_LIT> * SrcEltSize ) ) { assert ( SrcVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT InterimFVT = <STR_LIT> ( <STR_LIT> , DstVT . getVectorElementCount ( ) ) ; Src = DAG . getNode ( <STR_LIT> , DL , InterimFVT , { Src , Mask , VL } ) ; } Result = DAG . getNode ( <ISA_LIT>ISDOpc , DL , DstVT , { Src , Mask , VL } ) ; } } else { if ( SrcVT . isInteger ( ) ) { assert ( DstVT . isFloatingPoint ( ) && <STR_LIT> ) ; MVT InterimFVT = DstVT ;"
LLVM,RISCV,2915,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT VecEVT = Vec . getValueType ( ) ; if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVVPReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } SDValue VL = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ResVT = ! VecVT . isInteger ( ) || VecEltVT . bitsGE ( XLenVT ) ? VecEltVT : XLenVT ; SDValue StartSplat = lowerScalarSplat ( SDValue ( ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , StartSplat , Vec , StartSplat , Mask , VL ) ;"
LLVM,RISCV,2916,"Predict the next statement of this code snippet:
 <s> if ( Vec . getValueType ( ) != VT ) return SDValue ( ) ; SDValue Idx = SplatVal . getOperand ( <NUM_LIT> ) ; if ( Idx . getValueType ( ) != Subtarget . getXLenVT ( ) ) return SDValue ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) {"
LLVM,RISCV,2917,"Predict the next statement of this code snippet:
 <s> SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Gather = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Vec , Idx , Mask , VL ) ; if ( ! VT . isFixedLengthVector ( ) ) return Gather ;"
LLVM,RISCV,2918,"Predict the next statement of this code snippet:
 <s> static SDValue performBITREVERSECombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( Subtarget . hasStdExtZbkb ( ) && <STR_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ;"
LLVM,RISCV,2919,"Predict the next statement of this code snippet:
 <s> assert ( Subtarget . hasStdExtZbkb ( ) && <STR_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isScalarInteger ( ) || VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) || ! isPowerOf2_32 ( VT . getSizeInBits ( ) ) ) return SDValue ( ) ;"
LLVM,RISCV,2920,"Predict the next statement of this code snippet:
 <s> if ( Src . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . bitsGE ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) ) ; if ( Subtarget . hasStdExtZbb ( ) && Subtarget . is64Bit ( ) && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && VT == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> && DAG . ComputeNumSignBits ( Src . getOperand ( <NUM_LIT> ) ) > <NUM_LIT> ) { SDLoc DL ( N ) ; SDValue Freeze = DAG . getFreeze ( Src . getOperand ( <NUM_LIT> ) ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Freeze ) ; Neg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Neg , DAG . getValueType ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Freeze , Neg ) ; } return SDValue ( ) ;"
LLVM,RISCV,2921,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( N ) ; SDValue Freeze = DAG . getFreeze ( Src . getOperand ( <NUM_LIT> ) ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Freeze ) ; Neg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Neg , DAG . getValueType ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Freeze , Neg ) ;"
LLVM,RISCV,2922,"Predict the next statement of this code snippet:
 <s> case Instruction :: Xor : case Instruction :: FAdd : case Instruction :: FSub : case Instruction :: FMul : case Instruction :: FDiv : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ;"
LLVM,RISCV,2923,"Predict the next statement of this code snippet:
 <s> int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VT , Passthru , Lo , VL ) ; auto * Const = dyn_cast < ConstantSDNode > ( VL ) ; if ( LoC == HiC && Const && Const -> isAllOnesValue ( ) ) { MVT InterVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; auto InterVec = DAG . getNode ( <STR_LIT> , DL , InterVT , DAG . getUNDEF ( InterVT ) , Lo , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , InterVec ) ; } } return DAG . getNode ( <STR_LIT> , DL , VT , Passthru , Lo , Hi , VL ) ;"
LLVM,RISCV,2924,"Predict the next statement of this code snippet:
 <s> if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ;"
LLVM,RISCV,2925,"Predict the next statement of this code snippet:
 <s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return splatPartsI64WithVL ( DL , VT , Passthru , Lo , Hi , VL , DAG ) ;"
LLVM,RISCV,2926,"Predict the next statement of this code snippet:
 <s> SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( UseGPRForF64 && XLen == <NUM_LIT> && ValVT == <STR_LIT> ) { assert ( ! ArgFlags . isSplit ( ) && PendingLocs . empty ( ) && <STR_LIT> ) ; Register Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } Register Reg ; if ( ValVT == <STR_LIT> && ! UseGPRForF32 ) Reg = State . AllocateReg ( ArgFPR32s , ArgFPR64s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF16 ) Reg = State . AllocateReg ( ArgFPR16s , ArgFPR64s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s , ArgFPR32s ) ; else if ( ValVT . isScalableVector ( ) ) { switch ( ValVT . getSizeInBits ( ) . getKnownMinSize ( ) ) { case <NUM_LIT> :"
LLVM,RISCV,2927,"Predict the next statement of this code snippet:
 <s> case CCValAssign :: BCvt : if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ;"
LLVM,RISCV,2928,"Predict the next statement of this code snippet:
 <s> Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; }"
LLVM,RISCV,2929,"Predict the next statement of this code snippet:
 <s> static SDValue convertValVTToLocVT ( SelectionDAG & DAG , SDValue Val , const CCValAssign & VA , const SDLoc & DL ) { EVT LocVT = VA . getLocVT ( ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ;"
LLVM,RISCV,2930,"Predict the next statement of this code snippet:
 <s> } if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ;"
LLVM,RISCV,2931,"Predict the next statement of this code snippet:
 <s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( MF ) ;"
LLVM,RISCV,2932,"Predict the next statement of this code snippet:
 <s> Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( MF ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( LoReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( HiReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; TII . loadRegFromStackSlot ( * BB , MI , DstReg , FI , DstRC , RI ) ; MI . eraseFromParent ( ) ; return BB ;"
LLVM,RISCV,2933,"Predict the next statement of this code snippet:
 <s> break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( vtypei ) ; return BB ; } switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :"
LLVM,RISCV,2934,"Predict the next statement of this code snippet:
 <s> static MachineBasicBlock * emitSplitF64Pseudo ( MachineInstr & MI , MachineBasicBlock * BB ) { assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = * BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,2935,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,2936,"Predict the next statement of this code snippet:
 <s> if ( isNullConstant ( Idx ) ) return Op ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT EltVT = Op . getValueType ( ) ; EVT VecVT = Vec . getValueType ( ) ;"
LLVM,RISCV,2937,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( Idx ) ) return Op ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT EltVT = Op . getValueType ( ) ; EVT VecVT = Vec . getValueType ( ) ; SDValue Slidedown = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Vec , Idx ) ;"
LLVM,RISCV,2938,"Predict the next statement of this code snippet:
 <s> SDValue Promote = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , scalar ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Promote , Op . getOperand ( <NUM_LIT> ) } ) ; } break ; } } if ( const <STR_LIT> * EII = <STR_LIT> ( IntNo ) ) { if ( EII -> ExtendedOperand ) { assert ( EII -> ExtendedOperand < Op . getNumOperands ( ) ) ; std :: vector < SDValue > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ;"
LLVM,RISCV,2939,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getRegister ( <STR_LIT> , PtrVT ) ; } case <STR_LIT> : { SDValue scalar = Op . getOperand ( <NUM_LIT> ) ; if ( scalar . getSimpleValueType ( ) == <STR_LIT> ) { SDValue Promote = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , scalar ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Promote , Op . getOperand ( <NUM_LIT> ) } ) ; } break ; } } if ( const <STR_LIT> * EII = <STR_LIT> ( IntNo ) ) { if ( EII -> ExtendedOperand ) { assert ( EII -> ExtendedOperand < Op . getNumOperands ( ) ) ; std :: vector < SDValue > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [ EII -> ExtendedOperand ] ;"
LLVM,RISCV,2940,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ;"
LLVM,RISCV,2941,"Predict the next statement of this code snippet:
 <s> return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> :"
LLVM,RISCV,2942,"Predict the next statement of this code snippet:
 <s> assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ; break ; } case <STR_LIT> : { SDNode & Op = * N ; unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) {"
LLVM,RISCV,2943,"Predict the next statement of this code snippet:
 <s> static SDValue unpackFromMemLoc ( SelectionDAG & DAG , SDValue Chain , const CCValAssign & VA , const SDLoc & DL ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; EVT ValVT = VA . getValVT ( ) ; EVT PtrVT = <STR_LIT> ( DAG . getDataLayout ( ) . getPointerSizeInBits ( <NUM_LIT> ) ) ; int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) . getKnownMinSize ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : if ( ValVT . isScalableVector ( ) ) {"
LLVM,RISCV,2944,"Predict the next statement of this code snippet:
 <s> SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : if ( ValVT . isScalableVector ( ) ) { return DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } case CCValAssign :: BCvt : ExtType = <STR_LIT> ;"
LLVM,RISCV,2945,"Predict the next statement of this code snippet:
 <s> Align StackAlign = std :: max ( Align ( XLenInBytes ) , ArgFlags1 . getNonZeroOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , State . AllocateStack ( XLenInBytes , StackAlign ) , VA1 . getLocVT ( ) , CCValAssign :: Full ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , Align ( XLenInBytes ) ) , LocVT2 , CCValAssign :: Full ) ) ; return false ; } if ( Register Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo2 , ValVT2 , Reg , LocVT2 , CCValAssign :: Full ) ) ;"
LLVM,RISCV,2946,"Predict the next statement of this code snippet:
 <s> return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR16List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR16List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset4 = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset4 , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset5 = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset5 , LocVT , LocInfo ) ) ; return false ; }"
LLVM,RISCV,2947,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB ) ; case <STR_LIT> : return emitBuildPairF64Pseudo ( MI , BB ) ; case <STR_LIT> : return emitSplitF64Pseudo ( MI , BB ) ;"
LLVM,RISCV,2948,"Predict the next statement of this code snippet:
 <s> assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB ) ; case <STR_LIT> : return emitBuildPairF64Pseudo ( MI , BB ) ; case <STR_LIT> :"
LLVM,RISCV,2949,"Predict the next statement of this code snippet:
 <s> assert ( ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) ; unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; <STR_LIT> CmpXchgIntrID = <STR_LIT> ; if ( XLen == <NUM_LIT> ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = <STR_LIT> ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ;"
LLVM,RISCV,2950,"Predict the next statement of this code snippet:
 <s> Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; <STR_LIT> CmpXchgIntrID = <STR_LIT> ; if ( XLen == <NUM_LIT> ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = <STR_LIT> ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ;"
LLVM,RISCV,2951,"Predict the next statement of this code snippet:
 <s> assert ( ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) ; unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( AI -> getOrdering ( ) ) ) ; Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * LrwOpScwLoop = <STR_LIT> ( AI -> getModule ( ) , getIntrinsicForMaskedAtomicRMWBinOp ( XLen , AI -> getOperation ( ) ) , Tys ) ; if ( XLen == <NUM_LIT> ) { Incr = Builder . CreateSExt ( Incr , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; ShiftAmt = Builder . CreateSExt ( ShiftAmt , Builder . getInt64Ty ( ) ) ; }"
LLVM,RISCV,2952,"Predict the next statement of this code snippet:
 <s> if ( XLen == <NUM_LIT> ) { Incr = Builder . CreateSExt ( Incr , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; ShiftAmt = Builder . CreateSExt ( ShiftAmt , Builder . getInt64Ty ( ) ) ; } Value * Result ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getIntN ( XLen , XLen - ValWidth ) , ShiftAmt ) ; Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ;"
LLVM,RISCV,2953,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( N ) ; if ( <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) { SDValue Addr = getTargetNode ( N , DL , Ty , DAG , <NUM_LIT> ) ; if ( IsLocal && CanDeriveFromPcc ) { return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; } SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MemOp = MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , LLT ( Ty . getSimpleVT ( ) ) , Align ( Ty . getFixedSizeInBits ( ) / <NUM_LIT> ) ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load . getNode ( ) ) , { MemOp } ) ; return Load ; } if ( isPositionIndependent ( ) ) { SDValue Addr = getTargetNode ( N , DL , Ty , DAG , <NUM_LIT> ) ; if ( IsLocal ) return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MemOp = MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , LLT ( Ty . getSimpleVT ( ) ) , Align ( Ty . getFixedSizeInBits ( ) / <NUM_LIT> ) ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load . getNode ( ) ) , { MemOp } ) ; return Load ; }"
LLVM,RISCV,2954,"Predict the next statement of this code snippet:
 <s> const GlobalValue * GV = N -> getGlobal ( ) ; unsigned Opcode = <STR_LIT> ( Subtarget . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( Opcode , DL , Ty , Addr ) , <NUM_LIT> ) ; ArgListTy Args ;"
LLVM,RISCV,2955,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ( Subtarget . getTargetABI ( ) ) ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,2956,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return <STR_LIT> ( Subtarget . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,2957,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return <STR_LIT> ( Subtarget . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,2958,"Predict the next statement of this code snippet:
 <s> unsigned CapSize = Subtarget . typeForCapabilities ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Op . size ( ) >= CapSize ) { Align CapAlign ( CapSize ) ; LLVM_DEBUG ( dbgs ( ) << __func__ << <STR_LIT> << Op . size ( ) << <STR_LIT> << ( Op . isFixedDstAlign ( ) ? Op . getDstAlign ( ) . value ( ) : <NUM_LIT> ) << <STR_LIT> << ( Op . isMemset ( ) ? <NUM_LIT> : Op . getSrcAlign ( ) . value ( ) ) << <STR_LIT> << CapSize << <STR_LIT> ) ; if ( Op . isAligned ( CapAlign ) ) { return CapType ; } else if ( ! Op . isMemset ( ) ) { return <STR_LIT> ; }"
LLVM,RISCV,2959,"Predict the next statement of this code snippet:
 <s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const {"
LLVM,RISCV,2960,"Predict the next statement of this code snippet:
 <s> SDValue MNAdd = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , TPReg , MNHi , AddrCIncOffset ) , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNAdd , AddrLo ) , <NUM_LIT> ) ; } if ( NotLocal ) { SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MemOp = MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , LLT ( Ty . getSimpleVT ( ) ) , Align ( Ty . getFixedSizeInBits ( ) / <NUM_LIT> ) ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load . getNode ( ) ) , { MemOp } ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load , TPReg ) ; } SDValue AddrHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrAdd = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrLo = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ; SDValue MNAdd = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , TPReg , AddrAdd ) , <NUM_LIT> ) ;"
LLVM,RISCV,2961,"Predict the next statement of this code snippet:
 <s> TailPaddingAmount <ISA_LIT>TargetLowering :: getTailPaddingForPreciseBounds ( uint64_t Size ) const { if ( ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) return TailPaddingAmount :: None ;"
LLVM,RISCV,2962,"Predict the next statement of this code snippet:
 <s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,2963,"Predict the next statement of this code snippet:
 <s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ;"
LLVM,RISCV,2964,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; return getAddr ( N , Ty , DAG , true , true ) ;"
LLVM,RISCV,2965,"Predict the next statement of this code snippet:
 <s> translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; if ( LHS . getValueType ( ) . isFatPointer ( ) ) { LHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , LHS ) ; RHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , RHS ) ; } SDValue TargetCC = DAG . getCondCode ( CCVal ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , LHS , RHS , TargetCC , Op . getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2966,"Predict the next statement of this code snippet:
 <s> ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ;"
LLVM,RISCV,2967,"Predict the next statement of this code snippet:
 <s> int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - ( XLenInBytes * <NUM_LIT> ) ; SDValue Ptr = DAG . getPointerAdd ( DL , FrameAddr , Offset ) ; FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ; } return FrameAddr ;"
LLVM,RISCV,2968,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; int64_t Offset = N -> getOffset ( ) ; const GlobalValue * GV = N -> getGlobal ( ) ; bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; SDValue Addr = getAddr ( N , Ty , DAG , IsLocal , false ) ; if ( Offset != <NUM_LIT> ) return DAG . getPointerAdd ( DL , Addr , Offset ) ; return Addr ;"
LLVM,RISCV,2969,"Predict the next statement of this code snippet:
 <s> GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; int64_t Offset = N -> getOffset ( ) ; const GlobalValue * GV = N -> getGlobal ( ) ; bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;"
LLVM,RISCV,2970,"Predict the next statement of this code snippet:
 <s> Addr = getStaticTLSAddr ( N , Ty , DAG , true ) ; break ; case TLSModel :: LocalDynamic : case TLSModel :: GeneralDynamic : Addr = getDynamicTLSAddr ( N , Ty , DAG ) ; break ; } if ( Offset != <NUM_LIT> ) return DAG . getPointerAdd ( DL , Addr , Offset ) ; return Addr ;"
LLVM,RISCV,2971,"Predict the next statement of this code snippet:
 <s> SDValue SplattedVal = splatSplitI64WithVL ( DL , VT , Scalar , VL , DAG ) ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , VL ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , VL ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; SDValue SelectCond = DAG . getNode ( <STR_LIT> , DL , MaskVT , VID , SplattedIdx , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectCond , SplattedVal , Vec , VL ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = Op . getNumOperands ( ) ; bool IsMasked = NumOps == <NUM_LIT> ; unsigned OpOffset = IsMasked ? <NUM_LIT> : <NUM_LIT> ; SDValue Scalar = Op . getOperand ( <NUM_LIT> + OpOffset ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) break ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( Scalar ) ) if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) break ; MVT VT = Op . getSimpleValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT I32VT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue Vec = DAG . getBitcast ( I32VT , Op . getOperand ( <NUM_LIT> + OpOffset ) ) ; SDValue ScalarLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue ScalarHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue VL = Op . getOperand ( NumOps - <NUM_LIT> ) ; SDValue I32VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , VL , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; MVT I32MaskVT = <STR_LIT> ( <STR_LIT> , I32VT . getVectorElementCount ( ) ) ; SDValue I32Mask = DAG . getNode ( <STR_LIT> , DL , I32MaskVT , VL ) ; if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> ) {"
LLVM,RISCV,2972,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const {"
LLVM,RISCV,2973,"Predict the next statement of this code snippet:
 <s> EVT Ty = Op . getValueType ( ) ; return getAddr ( N , Ty , DAG , true , true ) ;"
LLVM,RISCV,2974,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { int Off = - XLenInBytes ; SDValue FrameAddr = lowerFRAMEADDR ( Op , DAG ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getPointerAdd ( DL , FrameAddr , Off ) , MachinePointerInfo ( ) ) ;"
LLVM,RISCV,2975,"Predict the next statement of this code snippet:
 <s> const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; if ( LHS . getValueType ( ) . isFatPointer ( ) ) { LHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , LHS ) ; RHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , RHS ) ; } SDValue TargetCC = DAG . getTargetConstant ( CCVal , DL , XLenVT ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ; } SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SetNE = DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ;"
LLVM,RISCV,2976,"Predict the next statement of this code snippet:
 <s> } if ( VT == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && ( CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT || CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . isFatPointer ( ) ) ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; const auto * CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; if ( isa < ConstantSDNode > ( TrueV ) && isa < ConstantSDNode > ( FalseV ) && CCVal == <STR_LIT> ) { const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; if ( LHS . getValueType ( ) . isFatPointer ( ) ) { LHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , LHS ) ; RHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , RHS ) ; } SDValue TargetCC = DAG . getTargetConstant ( CCVal , DL , XLenVT ) ;"
LLVM,RISCV,2977,"Predict the next statement of this code snippet:
 <s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;"
LLVM,RISCV,2978,"Predict the next statement of this code snippet:
 <s> LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : break ; } SmallVector < SDNode * , <NUM_LIT> > SetCCs ; for ( SDNode :: use_iterator UI = Src . getNode ( ) -> use_begin ( ) , UE = Src . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User == N ) continue ; if ( UI . getUse ( ) . getResNo ( ) != Src . getResNo ( ) ) continue ; if ( User -> getOpcode ( ) == <STR_LIT> ) { SetCCs . push_back ( User ) ; continue ; } break ; } if ( SetCCs . empty ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; DCI . CombineTo ( N , SExt ) ; for ( SDNode * SetCC : SetCCs ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { SDValue SOp = SetCC -> getOperand ( j ) ; if ( SOp == Src ) Ops . push_back ( SExt ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SOp ) ) ; } Ops . push_back ( SetCC -> getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2979,"Predict the next statement of this code snippet:
 <s> unsigned Size = CI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind :: None ;"
LLVM,RISCV,2980,"Predict the next statement of this code snippet:
 <s> if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind :: None ;"
LLVM,RISCV,2981,"Predict the next statement of this code snippet:
 <s> if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ;"
LLVM,RISCV,2982,"Predict the next statement of this code snippet:
 <s> <STR_LIT> ABI = Subtarget . getTargetABI ( ) ;"
LLVM,RISCV,2983,"Predict the next statement of this code snippet:
 <s> if ( DL . isFatPointer ( PointerTy ) && ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) && ( isa < AtomicRMWInst > ( AI ) || isa < AtomicCmpXchgInst > ( AI ) ) ) return false ;"
LLVM,RISCV,2984,"Predict the next statement of this code snippet:
 <s> int FI = MFI . CreateFixedObject ( ValVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : case CCValAssign :: BCvt : ExtType = <STR_LIT> ; break ; }"
LLVM,RISCV,2985,"Predict the next statement of this code snippet:
 <s> bool hasSplatOperand ( ) const {"
LLVM,RISCV,2986,"Predict the next statement of this code snippet:
 <s> RTLIB :: Libcall LC ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; else LC = RTLIB :: getFPTOUINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; MakeLibCallOptions CallOptions ; EVT OpVT = Op0 . getValueType ( ) ; CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RCW ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ;"
LLVM,RISCV,2987,"Predict the next statement of this code snippet:
 <s> if ( Reg == <STR_LIT> ) Reg = MatchRegisterName ( RegName ) ; if ( Reg == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; BitVector ReservedRegs = Subtarget . getRegisterInfo ( ) -> getReservedRegs ( MF ) ; if ( ! ReservedRegs . test ( Reg ) && ! Subtarget . isRegisterReservedByUser ( Reg ) ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ;"
LLVM,RISCV,2988,"Predict the next statement of this code snippet:
 <s> if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ; if ( ! Value . getNode ( ) ) Value = V ; } if ( ! Value . getNode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return DAG . getUNDEF ( VT ) ;"
LLVM,RISCV,2989,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerBUILD_VECTOR ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; bool isConstant = true ; SDValue Value ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . isUndef ( ) ) continue ; if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ; if ( ! Value . getNode ( ) ) Value = V ; } if ( ! Value . getNode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return DAG . getUNDEF ( VT ) ; } if ( isConstant ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return SDValue ( ) ; }"
LLVM,RISCV,2990,"Predict the next statement of this code snippet:
 <s> else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2991,"Predict the next statement of this code snippet:
 <s> return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } }"
LLVM,RISCV,2992,"Predict the next statement of this code snippet:
 <s> F -> insert ( I , TailMBB ) ; for ( MachineInstr * DebugInstr : SelectDebugValues ) { TailMBB -> push_back ( DebugInstr -> removeFromParent ( ) ) ; } TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; unsigned Opcode = getBranchOpcodeForIntCondCode ( CC ) ; BuildMI ( HeadMBB , DL , TII . get ( Opcode ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( TailMBB ) ; IfFalseMBB -> addSuccessor ( TailMBB ) ; auto SelectMBBI = MI . getIterator ( ) ; auto SelectEnd = std :: next ( LastSelectPseudo -> getIterator ( ) ) ; auto InsertionPoint = TailMBB -> begin ( ) ; while ( SelectMBBI != SelectEnd ) { auto Next = std :: next ( SelectMBBI ) ; if ( isSelectPseudo ( * SelectMBBI ) ) { BuildMI ( * TailMBB , InsertionPoint , SelectMBBI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( HeadMBB ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( IfFalseMBB ) ; SelectMBBI -> eraseFromParent ( ) ; } SelectMBBI = Next ;"
LLVM,RISCV,2993,"Predict the next statement of this code snippet:
 <s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'f' : return C_RegisterClass ;"
LLVM,RISCV,2994,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState ArgCCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; ArgCCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>32 ) ; unsigned NumBytes = ArgCCInfo . getNextStackOffset ( ) ; for ( auto & Arg : Outs ) { if ( ! Arg . Flags . isByVal ( ) ) continue ; report_fatal_error ( <STR_LIT> ) ; } Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , CLI . DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SDValue StackPtr ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; SDValue ArgValue = OutVals [ I ] ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; report_fatal_error ( <STR_LIT> ) ; } } SDValue Glue ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; } if ( isa < GlobalAddressSDNode > ( Callee ) ) { Callee = lowerGlobalAddress ( Callee , DAG ) ; } else if ( isa < ExternalSymbolSDNode > ( Callee ) ) { Callee = lowerExternalSymbol ( Callee , DAG ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto & Reg : RegsToPass ) Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( Glue . getNode ( ) ) Ops . push_back ( Glue ) ;"
LLVM,RISCV,2995,"Predict the next statement of this code snippet:
 <s> report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ;"
LLVM,RISCV,2996,"Predict the next statement of this code snippet:
 <s> for ( auto N : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setLoadExtAction ( N , XLenVT , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ;"
LLVM,RISCV,2997,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ;"
LLVM,RISCV,2998,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>TargetLowering ( ) {"
LLVM,RISCV,2999,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>TargetLowering ( ) {"
LLVM,RISCV,3000,"Predict the next statement of this code snippet:
 <s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; Register RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else {"
LLVM,RISCV,3001,"Predict the next statement of this code snippet:
 <s> CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; Register RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else {"
LLVM,RISCV,3002,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ArgVT = Ins [ i ] . VT ; <STR_LIT> ArgFlags = Ins [ i ] . Flags ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << '\n' ) ; llvm_unreachable ( nullptr ) ; } }"
LLVM,RISCV,3003,"Predict the next statement of this code snippet:
 <s> if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << '\n' ) ; llvm_unreachable ( nullptr ) ; }"
LLVM,RISCV,3004,"Predict the next statement of this code snippet:
 <s> if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet ) ) {"
LLVM,RISCV,3005,"Predict the next statement of this code snippet:
 <s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true ) ) return false ; }"
LLVM,RISCV,3006,"Predict the next statement of this code snippet:
 <s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ;"
LLVM,RISCV,3007,"Predict the next statement of this code snippet:
 <s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( IsVarArg ) report_fatal_error ( <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . getLocVT ( ) == Subtarget . getXLenVT ( ) && <STR_LIT> ) ; SDValue ArgValue ; if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) {"
LLVM,RISCV,3008,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; assert ( VA . getLocInfo ( ) == CCValAssign :: Full && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;"
LLVM,RISCV,3009,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ;"
LLVM,RISCV,3010,"Predict the next statement of this code snippet:
 <s> SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , AddrLo ) , <NUM_LIT> ) ; } case CodeModel :: Medium : { SDValue Addr = getTargetNode ( N , DL , Ty , DAG , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; }"
LLVM,RISCV,3011,"Predict the next statement of this code snippet:
 <s> case CodeModel :: Small : { SDValue AddrHi = getTargetNode ( N , DL , Ty , DAG , <STR_LIT> ) ; SDValue AddrLo = getTargetNode ( N , DL , Ty , DAG , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , AddrLo ) , <NUM_LIT> ) ;"
LLVM,RISCV,3012,"Predict the next statement of this code snippet:
 <s> if ( isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ;"
LLVM,RISCV,3013,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ;"
LLVM,RISCV,3014,"Predict the next statement of this code snippet:
 <s> if ( isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ;"
LLVM,RISCV,3015,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; int64_t Offset = N -> getOffset ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue Addr = getAddr ( N , DAG ) ; if ( Offset != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Ty , Addr , DAG . getConstant ( Offset , DL , XLenVT ) ) ; return Addr ;"
LLVM,RISCV,3016,"Predict the next statement of this code snippet:
 <s> switch ( Op . getOpcode ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : {"
LLVM,RISCV,3017,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> :"
LLVM,RISCV,3018,"Predict the next statement of this code snippet:
 <s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto BuildVSETVLI = [ & ] ( ) { if ( VLIndex >= <NUM_LIT> ) { Register DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const MachineOperand & VLOp = MI . getOperand ( VLIndex ) ; if ( VLOp . isImm ( ) ) return BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addImm ( VLOp . getImm ( ) ) ; Register VLReg = MI . getOperand ( VLIndex ) . getReg ( ) ; return BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( VLReg ) ; } return BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } ; MachineInstrBuilder MIB = BuildVSETVLI ( ) ; bool TailAgnostic = true ; unsigned UseOpIdx ; if ( ! ForceTailAgnostic && MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) ) { TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI . getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ;"
LLVM,RISCV,3019,"Predict the next statement of this code snippet:
 <s> while ( true ) { if ( ! MI -> isFullCopy ( ) ) return MI ; if ( ! Register :: isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ; MI = MRI . getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;"
LLVM,RISCV,3020,"Predict the next statement of this code snippet:
 <s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB ) ;"
LLVM,RISCV,3021,"Predict the next statement of this code snippet:
 <s> if ( <STR_LIT> ( TSFlags ) ) { unsigned NumOperands = MI . getNumExplicitOperands ( ) ; int VLIndex = <STR_LIT> ( TSFlags ) ? NumOperands - <NUM_LIT> : - <NUM_LIT> ; unsigned SEWIndex = NumOperands - <NUM_LIT> ; bool ForceTailAgnostic = <STR_LIT> ( TSFlags ) ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; return addVSetVL ( MI , BB , VLIndex , SEWIndex , VLMul , ForceTailAgnostic ) ; } switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB ) ;"
LLVM,RISCV,3022,"Predict the next statement of this code snippet:
 <s> return convertFromScalableVector ( VecVT , Res , DAG , Subtarget ) ; } if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; } if ( Hi . getOpcode ( ) == <STR_LIT> && Hi . getOperand ( <NUM_LIT> ) == Lo && isa < ConstantSDNode > ( Hi . getOperand ( <NUM_LIT> ) ) && Hi . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ;"
LLVM,RISCV,3023,"Predict the next statement of this code snippet:
 <s> bool SelectMaskVal = ( MaskIndex < ( int ) NumElts ) ^ InvertMask ; MaskVals . push_back ( DAG . getConstant ( SelectMaskVal , DL , XLenVT ) ) ; if ( ! IsSelect ) { bool IsLHS = MaskIndex < ( int ) NumElts ; GatherIndicesLHS . push_back ( DAG . getConstant ( IsLHS ? std :: max ( MaskIndex , <NUM_LIT> ) : <NUM_LIT> , DL , XLenVT ) ) ; GatherIndicesRHS . push_back ( DAG . getConstant ( IsLHS ? <NUM_LIT> : MaskIndex - NumElts , DL , XLenVT ) ) ; } } if ( SwapOps ) { std :: swap ( V1 , V2 ) ; std :: swap ( GatherIndicesLHS , GatherIndicesRHS ) ; } assert ( MaskVals . size ( ) == NumElts && <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue SelectMask = DAG . getBuildVector ( MaskVT , DL , MaskVals ) ; if ( IsSelect ) return DAG . getNode ( <STR_LIT> , DL , VT , SelectMask , V1 , V2 ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && VT . getVectorNumElements ( ) > <NUM_LIT> ) { return SDValue ( ) ; } unsigned GatherOpc = <STR_LIT> ; MVT IndexVT = VT . changeTypeToInteger ( ) ; if ( IndexVT . getScalarType ( ) . bitsGT ( XLenVT ) ) { GatherOpc = <STR_LIT> ; IndexVT = IndexVT . changeVectorElementType ( <STR_LIT> ) ; } MVT IndexContainerVT = ContainerVT . changeVectorElementType ( IndexVT . getScalarType ( ) ) ; SDValue Gather ; if ( SDValue SplatValue = DAG . getSplatValue ( V1 ) ) { Gather = lowerScalarSplat ( SplatValue , VL , ContainerVT , DL , DAG , Subtarget ) ; } else { SDValue LHSIndices = DAG . getBuildVector ( IndexVT , DL , GatherIndicesLHS ) ; LHSIndices = convertToScalableVector ( IndexContainerVT , LHSIndices , DAG , Subtarget ) ; V1 = convertToScalableVector ( ContainerVT , V1 , DAG , Subtarget ) ; Gather = DAG . getNode ( GatherOpc , DL , ContainerVT , V1 , LHSIndices , TrueMask , VL ) ; } if ( ! V2 . isUndef ( ) ) { MVT MaskContainerVT = ContainerVT . changeVectorElementType ( <STR_LIT> ) ; SelectMask = convertToScalableVector ( MaskContainerVT , SelectMask , DAG , Subtarget ) ;"
LLVM,RISCV,3024,"Predict the next statement of this code snippet:
 <s> SDValue Chain = DAG . getEntryNode ( ) ; Lo = DAG . getStore ( Chain , DL , Lo , StackSlot , MPI , Align ( <NUM_LIT> ) ) ; SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , TypeSize :: Fixed ( <NUM_LIT> ) , DL ) ; Hi = DAG . getStore ( Chain , DL , Hi , OffsetSlot , MPI . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDVTList VTs = DAG . getVTList ( { VT , <STR_LIT> } ) ; SDValue IntID = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , IntID , StackSlot , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , VL } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , <STR_LIT> , MPI , Align ( <NUM_LIT> ) , MachineMemOperand :: MOLoad ) ;"
LLVM,RISCV,3025,"Predict the next statement of this code snippet:
 <s> int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VT , Lo , VL ) ;"
LLVM,RISCV,3026,"Predict the next statement of this code snippet:
 <s> static SDValue splatPartsI64WithVL ( const SDLoc & DL , MVT VT , SDValue Lo , SDValue Hi , SDValue VL , SelectionDAG & DAG ) { if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ;"
LLVM,RISCV,3027,"Predict the next statement of this code snippet:
 <s> LocInfo = CCValAssign :: BCvt ; } if ( IsRet && ValNo > <NUM_LIT> ) return true ; unsigned TwoXLenInBytes = ( <NUM_LIT> * XLen ) / <NUM_LIT> ; if ( ! IsFixed && ArgFlags . getOrigAlign ( ) == TwoXLenInBytes && DL . getTypeAllocSize ( OrigTy ) == TwoXLenInBytes ) { unsigned RegIdx = State . getFirstUnallocated ( ArgGPRs ) ; if ( RegIdx != array_lengthof ( ArgGPRs ) && RegIdx % <NUM_LIT> == <NUM_LIT> ) State . AllocateReg ( ArgGPRs ) ; } SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( XLen == <NUM_LIT> && ValVT == <STR_LIT> ) { assert ( ! ArgFlags . isSplit ( ) && PendingLocs . empty ( ) && <STR_LIT> ) ; unsigned Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ;"
LLVM,RISCV,3028,"Predict the next statement of this code snippet:
 <s> assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ;"
LLVM,RISCV,3029,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : { assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ;"
LLVM,RISCV,3030,"Predict the next statement of this code snippet:
 <s> default : break ; case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) return DCI . CombineTo ( N , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; SDLoc DL ( N ) ; if ( ! ( Op0 . getOpcode ( ) == <STR_LIT> || Op0 . getOpcode ( ) == <STR_LIT> ) || ! Op0 . getNode ( ) -> hasOneUse ( ) ) break ; SDValue NewSplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; SDValue Lo = NewSplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = NewSplitF64 . getValue ( <NUM_LIT> ) ; APInt SignBit = APInt :: getSignMask ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } assert ( Op0 . getOpcode ( ) == <STR_LIT> ) ; SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( ~ SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3031,"Predict the next statement of this code snippet:
 <s> APInt LHSMask = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; APInt RHSMask = APInt :: getLowBitsSet ( RHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , LHSMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , RHSMask , DCI ) ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { SDValue AExtOp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 . getOperand ( <NUM_LIT> ) ) ; return DCI . CombineTo ( N , AExtOp ) ; } if ( ! ( Op0 . getOpcode ( ) == <STR_LIT> || Op0 . getOpcode ( ) == <STR_LIT> ) || ! Op0 . getNode ( ) -> hasOneUse ( ) ) break ; SDValue NewFMV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 . getOperand ( <NUM_LIT> ) ) ; APInt SignBit = APInt :: getSignMask ( <NUM_LIT> ) . sext ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { return DCI . CombineTo ( N , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewFMV , DAG . getConstant ( SignBit , DL , <STR_LIT> ) ) ) ; } assert ( Op0 . getOpcode ( ) == <STR_LIT> ) ; return DCI . CombineTo ( N , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewFMV , DAG . getConstant ( ~ SignBit , DL , <STR_LIT> ) ) ) ;"
LLVM,RISCV,3032,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } if ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,RISCV,3033,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( Subtarget . is64Bit ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } if ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = {"
LLVM,RISCV,3034,"Predict the next statement of this code snippet:
 <s> } if ( Base == Op -> getOperand ( <NUM_LIT> ) ) { Offset = Op -> getOperand ( <NUM_LIT> ) ; } else if ( Base == Op -> getOperand ( <NUM_LIT> ) ) { Offset = Op -> getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,3035,"Predict the next statement of this code snippet:
 <s> if ( ! Subtarget . hasExtXCoreVMem ( ) ) return false ; if ( Op -> getOpcode ( ) != <STR_LIT> ) return false ; if ( LSBaseSDNode * LS = dyn_cast < LSBaseSDNode > ( N ) ) { Base = LS -> getBasePtr ( ) ; } else { return false ;"
LLVM,RISCV,3036,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> :"
LLVM,RISCV,3037,"Predict the next statement of this code snippet:
 <s> CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ; break ;"
LLVM,RISCV,3038,"Predict the next statement of this code snippet:
 <s> CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ;"
LLVM,RISCV,3039,"Predict the next statement of this code snippet:
 <s> Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOStore ; return true ; }"
LLVM,RISCV,3040,"Predict the next statement of this code snippet:
 <s> unsigned IntNo = Op . getConstantOperandVal ( <NUM_LIT> ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : { SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ;"
LLVM,RISCV,3041,"Predict the next statement of this code snippet:
 <s> switch ( IntNo ) { default : break ; case <STR_LIT> : { SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Load = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ;"
LLVM,RISCV,3042,"Predict the next statement of this code snippet:
 <s> const auto * MLoad = cast < MaskedLoadSDNode > ( Op ) ; Mask = MLoad -> getMask ( ) ; PassThru = MLoad -> getPassThru ( ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; }"
LLVM,RISCV,3043,"Predict the next statement of this code snippet:
 <s> SDValue BasePtr = MemSD -> getBasePtr ( ) ; SDValue Val , Mask , VL ; if ( const auto * VPStore = dyn_cast < VPStoreSDNode > ( Op ) ) { Val = VPStore -> getValue ( ) ; Mask = VPStore -> getMask ( ) ; VL = VPStore -> getVectorLength ( ) ; } else { const auto * MStore = cast < MaskedStoreSDNode > ( Op ) ; Val = MStore -> getValue ( ) ; Mask = MStore -> getMask ( ) ; } MVT VT = Val . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ;"
LLVM,RISCV,3044,"Predict the next statement of this code snippet:
 <s> if ( SDValue V = transformAddShlImm ( N , DAG , Subtarget ) ) return V ;"
LLVM,RISCV,3045,"Predict the next statement of this code snippet:
 <s> if ( SDValue V = transformAddShlImm ( N , DAG , Subtarget ) ) return V ; return combineSelectAndUseCommutative ( N , DAG , false ) ;"
LLVM,RISCV,3046,"Predict the next statement of this code snippet:
 <s> case Instruction :: FAdd : case Instruction :: FSub : case Instruction :: FMul : case Instruction :: FDiv : return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ;"
LLVM,RISCV,3047,"Predict the next statement of this code snippet:
 <s> } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ;"
LLVM,RISCV,3048,"Predict the next statement of this code snippet:
 <s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( Subtarget . hasStdExtF ( ) && VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( Subtarget . hasStdExtD ( ) && VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ;"
LLVM,RISCV,3049,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return nullptr ;"
LLVM,RISCV,3050,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,3051,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> :"
LLVM,RISCV,3052,"Predict the next statement of this code snippet:
 <s> return ; } assert ( ( N -> getNumValues ( ) == Res -> getNumValues ( ) ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = N -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ;"
LLVM,RISCV,3053,"Predict the next statement of this code snippet:
 <s> if ( ! Res . getNode ( ) ) return ; if ( N -> getNumValues ( ) == <NUM_LIT> ) { Results . push_back ( Res ) ; return ; } assert ( ( N -> getNumValues ( ) == Res -> getNumValues ( ) ) && <STR_LIT> ) ;"
LLVM,RISCV,3054,"Predict the next statement of this code snippet:
 <s> SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; EVT Ty = Op . getValueType ( ) ; assert ( Ty == <STR_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ;"
LLVM,RISCV,3055,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerVectorBuild ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; EVT Ty = Op . getValueType ( ) ; assert ( Ty == <STR_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,3056,"Predict the next statement of this code snippet:
 <s> rawResult = DAG . getNode ( <STR_LIT> , DL , RegTy , dummy , V1 ) ; } else { rawResult = DAG . getNode ( <STR_LIT> , DL , RegTy , dummy , V1 ) ; } signed_bit = DAG . getNode ( <STR_LIT> , DL , RegTy , DAG . getNode ( <STR_LIT> , DL , RegTy , rawResult , DAG . getConstant ( <NUM_LIT> , DL , RegTy ) ) , DAG . getConstant ( lowShift , DL , RegTy ) ) ; mask = DAG . getNode ( <STR_LIT> , DL , RegTy , signed_bit , DAG . getConstant ( lowShift - <NUM_LIT> , DL , RegTy ) ) ; SDValue finalResult = DAG . getNode ( <STR_LIT> , DL , RegTy , rawResult , mask ) ;"
LLVM,RISCV,3057,"Predict the next statement of this code snippet:
 <s> SDValue num = Op . getOperand ( <NUM_LIT> ) ; auto * index = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; APInt pos = index -> getAPIntValue ( ) ; EVT Ty = Op . getValueType ( ) ;"
LLVM,RISCV,3058,"Predict the next statement of this code snippet:
 <s> Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ; break ;"
LLVM,RISCV,3059,"Predict the next statement of this code snippet:
 <s> Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : {"
LLVM,RISCV,3060,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtP ( ) && Subtarget . is64Bit ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Subtarget . is64Bit ( ) ? Legal : Custom ) ; if ( Subtarget . hasStdExtA ( ) ) { setMaxAtomicSizeInBitsSupported ( Subtarget . getXLen ( ) ) ; setMinCmpXchgSizeInBits ( <NUM_LIT> ) ; } else { setMaxAtomicSizeInBitsSupported ( <NUM_LIT> ) ; } setBooleanContents ( ZeroOrOneBooleanContent ) ; unsigned FunctionAlignment = Subtarget . hasStdExtC ( ) ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,3061,"Predict the next statement of this code snippet:
 <s> } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtP ( ) && Subtarget . is64Bit ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; }"
LLVM,RISCV,3062,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ;"
LLVM,RISCV,3063,"Predict the next statement of this code snippet:
 <s> switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool IsStrict = N -> isStrictFPOpcode ( ) ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDValue Op0 = IsStrict ? N -> getOperand ( <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> ) ; RTLIB :: Libcall LC ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; else LC = RTLIB :: getFPTOUINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; MakeLibCallOptions CallOptions ; EVT OpVT = Op0 . getValueType ( ) ; CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3064,"Predict the next statement of this code snippet:
 <s> assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ;"
LLVM,RISCV,3065,"Predict the next statement of this code snippet:
 <s> assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; <ISA_LIT>VSEW ElementWidth = static_cast < <ISA_LIT>VSEW > ( Log2_32 ( SEW / <NUM_LIT> ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) ; if ( VLIndex >= <NUM_LIT> ) { Register DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( MI . getOperand ( VLIndex ) . getReg ( ) ) ; } else MIB . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) ; bool TailAgnostic = true ; unsigned UseOpIdx ; if ( MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) && ! WritesElement0 ) { TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI . getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } MIB . addImm ( <ISA_LIT>VType :: encodeVTYPE ( VLMul , ElementWidth , TailAgnostic , false ) ) ; MI . getOperand ( SEWIndex ) . setImm ( - <NUM_LIT> ) ; if ( VLIndex >= <NUM_LIT> ) {"
LLVM,RISCV,3066,"Predict the next statement of this code snippet:
 <s> if ( VLIndex >= <NUM_LIT> ) { Register DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( MI . getOperand ( VLIndex ) . getReg ( ) ) ; } else MIB . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) ; bool TailAgnostic = true ; unsigned UseOpIdx ; if ( MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) && ! WritesElement0 ) { TailAgnostic = false ;"
LLVM,RISCV,3067,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; unsigned Opc = Op . getOpcode ( ) ; assert ( ( Opc >= <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; Known . resetAll ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: urem ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ;"
LLVM,RISCV,3068,"Predict the next statement of this code snippet:
 <s> Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: udiv ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ;"
LLVM,RISCV,3069,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : if ( Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) > Subtarget . getXLen ( ) ) return <NUM_LIT> ; return Subtarget . getXLen ( ) - Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) + <NUM_LIT> ; } return <NUM_LIT> ;"
LLVM,RISCV,3070,"Predict the next statement of this code snippet:
 <s> bool WritesElement0 = TSFlags & <STR_LIT> ; <ISA_LIT>VLMUL VLMul = static_cast < <ISA_LIT>VLMUL > ( ( TSFlags & <STR_LIT> ) >> <STR_LIT> ) ; return addVSetVL ( MI , BB , VLIndex , SEWIndex , VLMul , WritesElement0 ) ; } switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3071,"Predict the next statement of this code snippet:
 <s> switch ( ( <STR_LIT> ) Opcode ) { case <STR_LIT> : break ; NODE_NAME_CASE ( RET_FLAG ) NODE_NAME_CASE ( URET_FLAG ) NODE_NAME_CASE ( SRET_FLAG ) NODE_NAME_CASE ( MRET_FLAG ) NODE_NAME_CASE ( CALL ) NODE_NAME_CASE ( SELECT_CC ) NODE_NAME_CASE ( BuildPairF64 ) NODE_NAME_CASE ( SplitF64 ) NODE_NAME_CASE ( TAIL ) NODE_NAME_CASE ( SLLW ) NODE_NAME_CASE ( SRAW ) NODE_NAME_CASE ( SRLW ) NODE_NAME_CASE ( DIVW ) NODE_NAME_CASE ( DIVUW ) NODE_NAME_CASE ( REMUW ) NODE_NAME_CASE ( ROLW ) NODE_NAME_CASE ( RORW ) NODE_NAME_CASE ( FSLW ) NODE_NAME_CASE ( FSRW ) NODE_NAME_CASE ( FMV_H_X ) NODE_NAME_CASE ( FMV_X_ANYEXTH ) NODE_NAME_CASE ( FMV_W_X_RV64 ) NODE_NAME_CASE ( FMV_X_ANYEXTW_RV64 ) NODE_NAME_CASE ( READ_CYCLE_WIDE ) NODE_NAME_CASE ( GREVI ) NODE_NAME_CASE ( GREVIW ) NODE_NAME_CASE ( GORCI ) NODE_NAME_CASE ( GORCIW ) NODE_NAME_CASE ( VMV_X_S ) NODE_NAME_CASE ( SPLAT_VECTOR_I64 ) NODE_NAME_CASE ( READ_VLENB ) NODE_NAME_CASE ( TRUNCATE_VECTOR ) NODE_NAME_CASE ( VLEFF ) NODE_NAME_CASE ( VLEFF_MASK ) NODE_NAME_CASE ( VLSEGFF ) NODE_NAME_CASE ( VLSEGFF_MASK ) NODE_NAME_CASE ( READ_VL ) NODE_NAME_CASE ( VSLIDEUP ) NODE_NAME_CASE ( VSLIDEDOWN ) NODE_NAME_CASE ( VID ) } return nullptr ;"
LLVM,RISCV,3072,"Predict the next statement of this code snippet:
 <s> SDValue Val = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . is64Bit ( ) || VecVT . getVectorElementType ( ) != <STR_LIT> ) { if ( isNullConstant ( Idx ) ) return Op ; SDValue Slidedown = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Vec , Idx ) ; SDValue InsertElt0 = DAG . getNode ( <STR_LIT> , DL , VecVT , Slidedown , Val , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , VecVT , Vec , InsertElt0 , Idx ) ; } SDValue SplattedVal = DAG . getSplatVector ( VecVT , DL , Val ) ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VecVT , Idx ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VecVT ) ; auto SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VecVT ) ;"
LLVM,RISCV,3073,"Predict the next statement of this code snippet:
 <s> } else if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } return SDValue ( ) ; } case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasStdExtZbp ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned Imm = VT . getSizeInBits ( ) - <NUM_LIT> ; if ( Op . getOpcode ( ) == <STR_LIT> ) Imm &= ~ <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Imm , DL , Subtarget . getXLenVT ( ) ) ) ; } case <STR_LIT> : { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ! VT . isVector ( ) ) return Op ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return lowerVectorMaskTrunc ( Op , DAG ) ; EVT DstEltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcEltVT = SrcVT . getVectorElementType ( ) ; assert ( DstEltVT . bitsLT ( SrcEltVT ) && isPowerOf2_64 ( DstEltVT . getSizeInBits ( ) ) && isPowerOf2_64 ( SrcEltVT . getSizeInBits ( ) ) && <STR_LIT> ) ; SDValue Result = Src ; LLVMContext & Context = * DAG . getContext ( ) ; const ElementCount Count = SrcVT . getVectorElementCount ( ) ; do { SrcEltVT = EVT :: getIntegerVT ( Context , SrcEltVT . getSizeInBits ( ) / <NUM_LIT> ) ; EVT ResultVT = EVT :: getVectorVT ( Context , SrcEltVT , Count ) ; Result = DAG . getNode ( <STR_LIT> , DL , ResultVT , Result ) ; } while ( SrcEltVT != DstEltVT ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return lowerVectorMaskExt ( Op , DAG , <NUM_LIT> ) ; case <STR_LIT> : return lowerVectorMaskExt ( Op , DAG , - <NUM_LIT> ) ; case <STR_LIT> : return lowerSPLATVECTOR ( Op , DAG ) ; case <STR_LIT> :"
LLVM,RISCV,3074,"Predict the next statement of this code snippet:
 <s> assert ( Subtarget . hasStdExtZbp ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned Imm = VT . getSizeInBits ( ) - <NUM_LIT> ; if ( Op . getOpcode ( ) == <STR_LIT> ) Imm &= ~ <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Imm , DL , Subtarget . getXLenVT ( ) ) ) ; } case <STR_LIT> : { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ! VT . isVector ( ) ) return Op ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return lowerVectorMaskTrunc ( Op , DAG ) ; EVT DstEltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcEltVT = SrcVT . getVectorElementType ( ) ; assert ( DstEltVT . bitsLT ( SrcEltVT ) && isPowerOf2_64 ( DstEltVT . getSizeInBits ( ) ) && isPowerOf2_64 ( SrcEltVT . getSizeInBits ( ) ) && <STR_LIT> ) ; SDValue Result = Src ; LLVMContext & Context = * DAG . getContext ( ) ; const ElementCount Count = SrcVT . getVectorElementCount ( ) ; do { SrcEltVT = EVT :: getIntegerVT ( Context , SrcEltVT . getSizeInBits ( ) / <NUM_LIT> ) ; EVT ResultVT = EVT :: getVectorVT ( Context , SrcEltVT , Count ) ; Result = DAG . getNode ( <STR_LIT> , DL , ResultVT , Result ) ; } while ( SrcEltVT != DstEltVT ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return lowerVectorMaskExt ( Op , DAG , <NUM_LIT> ) ;"
LLVM,RISCV,3075,"Predict the next statement of this code snippet:
 <s> } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue ThirtyTwoV = DAG . getConstant ( <NUM_LIT> , DL , VecVT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , Zero ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , One ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ;"
LLVM,RISCV,3076,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerSPLATVECTOR ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT VecVT = Op . getValueType ( ) ; assert ( ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( SplatVal ) ) { if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( CVal -> getSExtValue ( ) , DL , <STR_LIT> ) ) ; } if ( SplatVal . getOpcode ( ) == <STR_LIT> && SplatVal . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , DL , VecVT , SplatVal . getOperand ( <NUM_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue ThirtyTwoV = DAG . getConstant ( <NUM_LIT> , DL , VecVT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , Zero ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , One ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; if ( isNullConstant ( Hi ) ) return Lo ;"
LLVM,RISCV,3077,"Predict the next statement of this code snippet:
 <s> if ( ! Src . getValueType ( ) . isVector ( ) || Src . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) return Op ; bool IsRV32E64 = ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatTrueVal = DAG . getConstant ( ExtTrueVal , DL , Subtarget . getXLenVT ( ) ) ; if ( ! IsRV32E64 ) { SplatZero = DAG . getSplatVector ( VecVT , DL , SplatZero ) ; SplatTrueVal = DAG . getSplatVector ( VecVT , DL , SplatTrueVal ) ; } else {"
LLVM,RISCV,3078,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerVectorMaskTrunc ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT MaskVT = Op . getValueType ( ) ; assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Src . getValueType ( ) ; bool IsRV32E64 = ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> ; SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; if ( ! IsRV32E64 ) { SplatOne = DAG . getSplatVector ( VecVT , DL , SplatOne ) ; SplatZero = DAG . getSplatVector ( VecVT , DL , SplatZero ) ; } else {"
LLVM,RISCV,3079,"Predict the next statement of this code snippet:
 <s> EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( Op . getOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return false ; const APInt & Mask = C -> getAPIntValue ( ) ; APInt ShrunkMask = Mask & DemandedBits ; if ( ShrunkMask . isSignedIntN ( <NUM_LIT> ) ) return false ; APInt ExpandedMask = Mask | ~ DemandedBits ; if ( ! ExpandedMask . isNegative ( ) ) return false ; unsigned MinSignedBits = ExpandedMask . getMinSignedBits ( ) ; APInt NewMask = ShrunkMask ; if ( MinSignedBits <= <NUM_LIT> ) NewMask . setBitsFrom ( <NUM_LIT> ) ; else if ( MinSignedBits <= <NUM_LIT> && ! ShrunkMask . isSignedIntN ( <NUM_LIT> ) ) NewMask . setBitsFrom ( <NUM_LIT> ) ; else return false ; assert ( NewMask . isSubsetOf ( ExpandedMask ) ) ; if ( NewMask == Mask ) return true ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( NewMask , DL , VT ) ; SDValue NewOp = TLO . DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , NewC ) ; return TLO . CombineTo ( Op , NewOp ) ;"
LLVM,RISCV,3080,"Predict the next statement of this code snippet:
 <s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue NewRHS = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , RHS , DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ) ) ; return DCI . CombineTo ( N , DAG . getNode ( N -> getOpcode ( ) , DL , LHS . getValueType ( ) , LHS , NewRHS ) ) ; } case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,3081,"Predict the next statement of this code snippet:
 <s> if ( ! DCI . isBeforeLegalize ( ) ) break ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || RHS -> getOpcode ( ) == <STR_LIT> || ( RHS -> getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( RHS -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) <= <NUM_LIT> ) ) break ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue NewRHS = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , RHS , DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ) ) ; return DCI . CombineTo ( N , DAG . getNode ( N -> getOpcode ( ) , DL , LHS . getValueType ( ) , LHS , NewRHS ) ) ; } case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || Src . getValueType ( ) != <STR_LIT> ) break ; if ( ! isVariableShift ( Src ) && ! ( Subtarget . hasStdExtM ( ) && isVariableSDivUDivURem ( Src ) ) ) break ; SDLoc DL ( N ) ; return DCI . CombineTo ( N , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ) ; } case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) != <STR_LIT> ) break ;"
LLVM,RISCV,3082,"Predict the next statement of this code snippet:
 <s> if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Base = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Base = ST -> getBasePtr ( ) ; } else { return false ; } if ( Base == Op -> getOperand ( <NUM_LIT> ) ) { Offset = Op -> getOperand ( <NUM_LIT> ) ; } else if ( Base == Op -> getOperand ( <NUM_LIT> ) ) {"
LLVM,RISCV,3083,"Predict the next statement of this code snippet:
 <s> Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ; break ; } case <STR_LIT> : { switch ( N -> getConstantOperandVal ( <NUM_LIT> ) ) { default : break ; case <STR_LIT> : SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = N -> getOperand ( <NUM_LIT> ) ; EVT ValueVTs [ ] = { Subtarget . getXLenVT ( ) , N -> getValueType ( <NUM_LIT> ) } ;"
LLVM,RISCV,3084,"Predict the next statement of this code snippet:
 <s> unsigned RA ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : jump = <STR_LIT> ; RA = <STR_LIT> ; break ; case <STR_LIT> : jump = <STR_LIT> ; RA = <STR_LIT> ; break ; case <STR_LIT> : jump = <STR_LIT> ; RA = <STR_LIT> ; break ; case <STR_LIT> : jump = <STR_LIT> ; RA = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MachineInstrBuilder jumpMI = BuildMI ( * BB , MI , DL , TII -> get ( jump ) , RA ) ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) { jumpMI . addOperand ( MI . getOperand ( i ) ) ; } MI . eraseFromParent ( ) ; return BB ;"
LLVM,RISCV,3085,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : return emitCALL ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return emitPEXTRACT ( MI , MBB , false ) ; case <STR_LIT> : case <STR_LIT> : return emitPEXTRACT ( MI , MBB , true ) ; case <STR_LIT> : return emitPINSERT ( MI , MBB ) ; case <STR_LIT> : return emitPBCLRSET ( MI , MBB , false ) ; case <STR_LIT> : return emitPBCLRSET ( MI , MBB , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitPRN ( MI , MBB ) ; default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,3086,"Predict the next statement of this code snippet:
 <s> } else if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) { immediate = <NUM_LIT> ; registr = <NUM_LIT> ; } assert ( immediate != <NUM_LIT> && registr != <NUM_LIT> ) ; int n = MI . getOperand ( immediate ) . getImm ( ) ; unsigned int l_pos , r_pos ; if ( ! RI5CY_bitIntervalExtraction ( n , & l_pos , & r_pos , isset ) ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ; } assert ( r_pos <= l_pos ) ; unsigned opcode = isset ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder pbclrMI = BuildMI ( * BB , MI , DL , TII -> get ( opcode ) ) ; pbclrMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; pbclrMI . addOperand ( MI . getOperand ( registr ) ) ;"
LLVM,RISCV,3087,"Predict the next statement of this code snippet:
 <s> int n = MI . getOperand ( immediate ) . getImm ( ) ; unsigned int l_pos , r_pos ; if ( ! RI5CY_bitIntervalExtraction ( n , & l_pos , & r_pos , isset ) ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ; } assert ( r_pos <= l_pos ) ; unsigned opcode = isset ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder pbclrMI = BuildMI ( * BB , MI , DL , TII -> get ( opcode ) ) ; pbclrMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; pbclrMI . addOperand ( MI . getOperand ( registr ) ) ;"
LLVM,RISCV,3088,"Predict the next statement of this code snippet:
 <s> const TargetInstrInfo * TII = BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int imm2 = MI . getOperand ( imm2_pos ) . getImm ( ) ; int imm3 = MI . getOperand ( imm3_pos ) . getImm ( ) ; if ( imm2 + imm3 <= <NUM_LIT> ) { MachineInstrBuilder newMI = BuildMI ( * BB , MI , DL , TII -> get ( unsign ? <STR_LIT> : <STR_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( src1_pos ) ) ; newMI . addImm ( <NUM_LIT> - imm2 - imm3 ) ; newMI . addImm ( imm3 ) ; } else { MachineInstrBuilder newMI = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( src1_pos ) ) ; newMI . addImm ( <NUM_LIT> ) ; } MI . eraseFromParent ( ) ;"
LLVM,RISCV,3089,"Predict the next statement of this code snippet:
 <s> int imm3 = MI . getOperand ( imm3_pos ) . getImm ( ) ; if ( imm2 + imm3 <= <NUM_LIT> ) { MachineInstrBuilder newMI = BuildMI ( * BB , MI , DL , TII -> get ( unsign ? <STR_LIT> : <STR_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( src1_pos ) ) ; newMI . addImm ( <NUM_LIT> - imm2 - imm3 ) ; newMI . addImm ( imm3 ) ; } else { MachineInstrBuilder newMI = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ;"
LLVM,RISCV,3090,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitPINSERT ( MachineInstr & MI , MachineBasicBlock * BB ) const { const unsigned dst_pos = <NUM_LIT> ; const unsigned src_pos = <NUM_LIT> ; const unsigned imm2_pos = <NUM_LIT> ; const unsigned imm3_pos = <NUM_LIT> ; assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; assert ( MI . getOperand ( dst_pos ) . isReg ( ) ) ; assert ( MI . getOperand ( src_pos ) . isReg ( ) ) ; assert ( MI . getOperand ( imm2_pos ) . isImm ( ) ) ; assert ( MI . getOperand ( imm3_pos ) . isImm ( ) ) ; const TargetInstrInfo * TII = BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int n = MI . getOperand ( imm2_pos ) . getImm ( ) ; int shift_imm = MI . getOperand ( imm3_pos ) . getImm ( ) ; unsigned int l_pos , r_pos ; if ( ! RI5CY_bitIntervalExtraction ( n , & l_pos , & r_pos , true ) || r_pos != <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ; } assert ( isUInt < <NUM_LIT> > ( l_pos ) ) ; assert ( isUInt < <NUM_LIT> > ( shift_imm ) ) ; unsigned opcode = <STR_LIT> ; MachineInstrBuilder pinsertMI = BuildMI ( * BB , MI , DL , TII -> get ( opcode ) ) ; pinsertMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; pinsertMI . addOperand ( MI . getOperand ( dst_pos ) ) ; pinsertMI . addOperand ( MI . getOperand ( src_pos ) ) ; pinsertMI . addImm ( l_pos ) ; pinsertMI . addImm ( shift_imm ) ; MI . eraseFromParent ( ) ;"
LLVM,RISCV,3091,"Predict the next statement of this code snippet:
 <s> unsigned opcode = issub ? ( unsign ? <STR_LIT> : <STR_LIT> ) : ( unsign ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder paddrnMI = BuildMI ( * BB , MI , DL , TII -> get ( opcode ) ) ; paddrnMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; paddrnMI . addOperand ( MI . getOperand ( reg1 ) ) ; paddrnMI . addOperand ( MI . getOperand ( reg2 ) ) ; paddrnMI . addImm ( n2 ) ; } else { MachineInstrBuilder sra = BuildMI ( * BB , MI , DL , TII -> get ( unsign ? <STR_LIT> : <STR_LIT> ) ) ; sra . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; sra . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; sra . addImm ( n2 ) ; MachineInstrBuilder addsub = BuildMI ( * BB , sra . getInstr ( ) , DL , TII -> get ( <STR_LIT> ) ) ; addsub . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; addsub . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; addsub . addImm ( n1 ) ;"
LLVM,RISCV,3092,"Predict the next statement of this code snippet:
 <s> unsigned bne = RC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned zero = RC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( BB , DL , TII -> get ( bne ) ) . addMBB ( sinkMBB ) . addReg ( zero ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned VReg = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * copy0MBB , copy0MBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , VReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , VReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned VReg = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * copy0MBB , copy0MBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , VReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( VReg ) . addMBB ( copy0MBB ) ;"
LLVM,RISCV,3093,"Predict the next statement of this code snippet:
 <s> default : break ; case 'd' : case 'r' : if ( Subtarget . isRV64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( Subtarget . hasD ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( Subtarget . hasF ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( Subtarget . isRV64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,RISCV,3094,"Predict the next statement of this code snippet:
 <s> OPCODE ( Lo ) ; OPCODE ( FENCE ) ; OPCODE ( SELECT_CC ) ; OPCODE ( SMIN ) ; OPCODE ( UMIN ) ; OPCODE ( SMAX ) ; OPCODE ( UMAX ) ; } return NULL ;"
LLVM,RISCV,3095,"Predict the next statement of this code snippet:
 <s> OPCODE ( Hi ) ; OPCODE ( Lo ) ; OPCODE ( FENCE ) ; OPCODE ( SELECT_CC ) ; OPCODE ( SMIN ) ; OPCODE ( UMIN ) ; OPCODE ( SMAX ) ; OPCODE ( UMAX ) ; } return NULL ;"
LLVM,RISCV,3096,"Predict the next statement of this code snippet:
 <s> case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : case AtomicOrdering :: Monotonic : case AtomicOrdering :: Acquire : case AtomicOrdering :: Release : case AtomicOrdering :: AcquireRelease : case AtomicOrdering :: SequentiallyConsistent : PI = <NUM_LIT> << <NUM_LIT> ; PO = <NUM_LIT> << <NUM_LIT> ; PR = <NUM_LIT> << <NUM_LIT> ; PW = <NUM_LIT> << <NUM_LIT> ; } switch ( Op . getConstantOperandVal ( <NUM_LIT> ) ) { case SingleThread : case CrossThread : SI = <NUM_LIT> << <NUM_LIT> ; SO = <NUM_LIT> << <NUM_LIT> ;"
LLVM,RISCV,3097,"Predict the next statement of this code snippet:
 <s> SO = <NUM_LIT> << <NUM_LIT> ; SR = <NUM_LIT> << <NUM_LIT> ; SW = <NUM_LIT> << <NUM_LIT> ; } unsigned pred = PI | PO | PR | PW ; unsigned succ = SI | SO | SR | SW ;"
LLVM,RISCV,3098,"Predict the next statement of this code snippet:
 <s> int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; InVals . push_back ( DAG . getLoad ( ValVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( IsVarArg ) { auto ArgRegs = IsRV32 ? RV32IntRegs : RV64IntRegs ; unsigned NumRegs = llvm :: <STR_LIT> ; unsigned Idx = CCInfo . getFirstUnallocated ( ArrayRef < MCPhysReg > ( ArgRegs , <NUM_LIT> ) ) ; unsigned RegSize = IsRV32 ? <NUM_LIT> : <NUM_LIT> ; MVT RegTy = <STR_LIT> ( RegSize * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; int VaArgOffset ; if ( NumRegs == Idx ) VaArgOffset = alignTo ( CCInfo . getNextStackOffset ( ) , RegSize ) ; else VaArgOffset = - ( int ) ( RegSize * ( NumRegs - Idx ) ) ; int FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < NumRegs ; ++ I , VaArgOffset += RegSize ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store ) ; } } if ( ! OutChains . empty ( ) ) {"
LLVM,RISCV,3099,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RetLocs ; CCState RetCCInfo ( CallConv , IsVarArg , MF , RetLocs , * DAG . getContext ( ) ) ; if ( Subtarget . isRV64 ( ) ) RetCCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64 ) ; else RetCCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Glue ; if ( RetLocs . empty ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ;"
LLVM,RISCV,3100,"Predict the next statement of this code snippet:
 <s> lowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { return SDValue ( ) ;"
LLVM,RISCV,3101,"Predict the next statement of this code snippet:
 <s> lowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const {"
LLVM,RISCV,3102,"Predict the next statement of this code snippet:
 <s> if ( C . front ( ) != '{' || C . back ( ) != '}' ) return std :: make_pair ( false , false ) ; StringRef :: const_iterator I , B = C . begin ( ) + <NUM_LIT> , E = C . end ( ) - <NUM_LIT> ; I = std :: find_if ( B , E , isdigit ) ; Prefix = StringRef ( B , I - B ) ;"
LLVM,RISCV,3103,"Predict the next statement of this code snippet:
 <s> StringRef Prefix ; unsigned long long Reg ; std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget . hasD ( ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; } else {"
LLVM,RISCV,3104,"Predict the next statement of this code snippet:
 <s> std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget . hasD ( ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ;"
LLVM,RISCV,3105,"Predict the next statement of this code snippet:
 <s> DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known2 , Depth + <NUM_LIT> ) ; Known . Zero &= Known2 . Zero ; Known . One &= Known2 . One ;"
LLVM,RISCV,3106,"Predict the next statement of this code snippet:
 <s> KnownBits Known2 ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ;"
LLVM,RISCV,3107,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'A' : return C_Memory ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ;"
LLVM,RISCV,3108,"Predict the next statement of this code snippet:
 <s> default : return SDValue ( ) ; case <STR_LIT> : return lowerSETVL ( Op , DAG ) ; case <STR_LIT> :"
LLVM,RISCV,3109,"Predict the next statement of this code snippet:
 <s> default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; }"
LLVM,RISCV,3110,"Predict the next statement of this code snippet:
 <s> return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> :"
LLVM,RISCV,3111,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDVTList ResultVTs = DAG . getVTList ( XLenVT , XLenVT ) ;"
LLVM,RISCV,3112,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget . getXLenVT ( ) ; SDVTList ResultVTs = DAG . getVTList ( XLenVT , XLenVT ) ;"
LLVM,RISCV,3113,"Predict the next statement of this code snippet:
 <s> if ( ElemVT == <STR_LIT> ) { SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SplatVal ) ; } return SDValue ( ) ;"
LLVM,RISCV,3114,"Predict the next statement of this code snippet:
 <s> if ( ElemVT == <STR_LIT> ) { SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SplatVal ) ;"
LLVM,RISCV,3115,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>VSEW ElementWidth = static_cast < <ISA_LIT>VSEW > ( Log2_32 ( SEW / <NUM_LIT> ) ) ; <ISA_LIT>VLMUL Multiplier = static_cast < <ISA_LIT>VLMUL > ( VLMul ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) ; if ( VLIndex >= <NUM_LIT> ) { Register DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( MI . getOperand ( VLIndex ) . getReg ( ) ) ; } else MIB . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) ; bool TailAgnostic = true ; if ( MI . isRegTiedToUseOperand ( <NUM_LIT> ) && ! WritesElement0 ) TailAgnostic = false ; MIB . addImm ( <ISA_LIT>VType :: encodeVTYPE ( Multiplier , ElementWidth , TailAgnostic , false ) ) ; MI . getOperand ( SEWIndex ) . setImm ( - <NUM_LIT> ) ; if ( VLIndex >= <NUM_LIT> ) {"
LLVM,RISCV,3116,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = * BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; unsigned SEW = MI . getOperand ( SEWIndex ) . getImm ( ) ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; <ISA_LIT>VSEW ElementWidth = static_cast < <ISA_LIT>VSEW > ( Log2_32 ( SEW / <NUM_LIT> ) ) ; <ISA_LIT>VLMUL Multiplier = static_cast < <ISA_LIT>VLMUL > ( VLMul ) ;"
LLVM,RISCV,3117,"Predict the next statement of this code snippet:
 <s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3118,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { if ( const <STR_LIT> * RVV = <STR_LIT> ( MI . getOpcode ( ) ) ) { int VLIndex = RVV -> getVLIndex ( ) ; int SEWIndex = RVV -> getSEWIndex ( ) ; bool WritesElement0 = RVV -> writesElement0 ( ) ; assert ( SEWIndex >= <NUM_LIT> && <STR_LIT> ) ; return addVSetVL ( MI , BB , VLIndex , SEWIndex , RVV -> VLMul , WritesElement0 ) ;"
LLVM,RISCV,3119,"Predict the next statement of this code snippet:
 <s> if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget . hasStdExtV ( ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ;"
LLVM,RISCV,3120,"Predict the next statement of this code snippet:
 <s> if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget . hasStdExtV ( ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ;"
LLVM,RISCV,3121,"Predict the next statement of this code snippet:
 <s> unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc DL ( Op ) ; if ( Subtarget . hasStdExtV ( ) ) { if ( const <STR_LIT> * II = <STR_LIT> ( IntNo ) ) { if ( II -> ExtendedOperand ) { assert ( II -> ExtendedOperand < Op . getNumOperands ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [ II -> ExtendedOperand ] ; EVT OpVT = ScalarOp . getValueType ( ) ; if ( OpVT == <STR_LIT> || OpVT == <STR_LIT> || ( OpVT == <STR_LIT> && Subtarget . is64Bit ( ) ) ) { unsigned ExtOpc = isa < ConstantSDNode > ( ScalarOp ) ? <STR_LIT> : <STR_LIT> ; ScalarOp = DAG . getNode ( ExtOpc , DL , Subtarget . getXLenVT ( ) , ScalarOp ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Operands ) ; }"
LLVM,RISCV,3122,"Predict the next statement of this code snippet:
 <s> assert ( ExtendOp < Op . getNumOperands ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [ ExtendOp ] ; EVT OpVT = ScalarOp . getValueType ( ) ; if ( OpVT == <STR_LIT> || OpVT == <STR_LIT> || ( OpVT == <STR_LIT> && Subtarget . is64Bit ( ) ) ) { unsigned ExtOpc = isa < ConstantSDNode > ( ScalarOp ) ? <STR_LIT> : <STR_LIT> ; ScalarOp = DAG . getNode ( ExtOpc , DL , Subtarget . getXLenVT ( ) , ScalarOp ) ; return DAG . getNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Operands ) ; } } } } return SDValue ( ) ;"
LLVM,RISCV,3123,"Predict the next statement of this code snippet:
 <s> unsigned ExtendOp = II -> ExtendedOperand + <NUM_LIT> ; assert ( ExtendOp < Op . getNumOperands ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [ ExtendOp ] ; EVT OpVT = ScalarOp . getValueType ( ) ; if ( OpVT == <STR_LIT> || OpVT == <STR_LIT> || ( OpVT == <STR_LIT> && Subtarget . is64Bit ( ) ) ) { unsigned ExtOpc = isa < ConstantSDNode > ( ScalarOp ) ? <STR_LIT> : <STR_LIT> ; ScalarOp = DAG . getNode ( ExtOpc , DL , Subtarget . getXLenVT ( ) , ScalarOp ) ; return DAG . getNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Operands ) ; }"
LLVM,RISCV,3124,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( ( ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) || Subtarget . hasStdExtZfh ( ) ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . hasStdExtZfh ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , Subtarget . getXLenVT ( ) , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } else if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } return SDValue ( ) ; } case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> :"
LLVM,RISCV,3125,"Predict the next statement of this code snippet:
 <s> if ( auto * CVal = dyn_cast < ConstantSDNode > ( SplatVal ) ) { if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( CVal -> getSExtValue ( ) , DL , <STR_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue ThirtyTwoV = DAG . getConstant ( <NUM_LIT> , DL , VecVT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , Zero ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , One ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; if ( isNullConstant ( Hi ) ) return Lo ; Hi = DAG . getNode ( <STR_LIT> , DL , VecVT , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VecVT , Hi , ThirtyTwoV ) ;"
LLVM,RISCV,3126,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Op ) ; EVT VecVT = Op . getValueType ( ) ; assert ( ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( SplatVal ) ) { if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( CVal -> getSExtValue ( ) , DL , <STR_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue ThirtyTwoV = DAG . getConstant ( <NUM_LIT> , DL , VecVT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , Zero ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , One ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ;"
LLVM,RISCV,3127,"Predict the next statement of this code snippet:
 <s> if ( ArgVT . isScalableVector ( ) && ArgVT . getVectorElementType ( ) . SimpleTy == <STR_LIT> ) return ArgIdx . index ( ) ; }"
LLVM,RISCV,3128,"Predict the next statement of this code snippet:
 <s> for ( const auto & ArgIdx : enumerate ( Args ) ) { MVT ArgVT = ArgIdx . value ( ) . VT ;"
LLVM,RISCV,3129,"Predict the next statement of this code snippet:
 <s> unsigned Tmp2 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; return std :: min ( Tmp , Tmp2 ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && ( Op . getConstantOperandVal ( <NUM_LIT> ) & <NUM_LIT> ) == <NUM_LIT> ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp > <NUM_LIT> ) return <NUM_LIT> ; } break ; } case <STR_LIT> : if ( Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) > Subtarget . getXLen ( ) ) return <NUM_LIT> ; return Subtarget . getXLen ( ) - Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) + <NUM_LIT> ; }"
LLVM,RISCV,3130,"Predict the next statement of this code snippet:
 <s> if ( VT . isVector ( ) ) return false ; return Subtarget . hasStdExtZbb ( ) && ! isa < ConstantSDNode > ( Y ) ;"
LLVM,RISCV,3131,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: hasAndNotCompare ( SDValue Y ) const {"
LLVM,RISCV,3132,"Predict the next statement of this code snippet:
 <s> case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ;"
LLVM,RISCV,3133,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { using namespace llvm :: PatternMatch ; if ( ! I -> getType ( ) -> isVectorTy ( ) || ! Subtarget . hasVInstructions ( ) ) return false ; auto IsSinker = [ & ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: FAdd : case Instruction :: FSub : case Instruction :: FMul : case Instruction :: FDiv : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ;"
LLVM,RISCV,3134,"Predict the next statement of this code snippet:
 <s> if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Value ) ;"
LLVM,RISCV,3135,"Predict the next statement of this code snippet:
 <s> static SDValue convertLocVTToValVT ( SelectionDAG & DAG , SDLoc DL , CCValAssign & VA , SDValue Chain , SDValue Value ) { if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ;"
LLVM,RISCV,3136,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return emitSelectCC ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitCALL ( MI , MBB ) ;"
LLVM,RISCV,3137,"Predict the next statement of this code snippet:
 <s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectCC ( MI , MBB ) ;"
LLVM,RISCV,3138,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( <NUM_LIT> ) ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , IsRV32 ? IsVarArg ? CC_<ISA_LIT>32_VAR : CC_<ISA_LIT>32 : IsVarArg ? CC_<ISA_LIT>64_VAR : CC_<ISA_LIT>64 ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; if ( Subtarget . isRV64 ( ) ) RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { if ( Subtarget . isRV32 ( ) ) { RC = & <STR_LIT> ; } else { RC = & <STR_LIT> ; } } else if ( RegVT == <STR_LIT> ) { if ( Subtarget . hasD ( ) ) RC = & <STR_LIT> ; else if ( Subtarget . hasF ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { if ( Subtarget . hasD ( ) ) RC = & <STR_LIT> ; else if ( Subtarget . hasF ( ) ) RC = & <STR_LIT> ; else if ( Subtarget . isRV64 ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ;"
LLVM,RISCV,3139,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,3140,"Predict the next statement of this code snippet:
 <s> if ( IsRet ) ArgTy = FType -> getReturnType ( ) ; else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet , ArgTy ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << '\n' ) ; llvm_unreachable ( nullptr ) ; } }"
LLVM,RISCV,3141,"Predict the next statement of this code snippet:
 <s> if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr ) ;"
LLVM,RISCV,3142,"Predict the next statement of this code snippet:
 <s> unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return false ; } assert ( LocVT == XLenVT && <STR_LIT> ) ; if ( Reg ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ValVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ;"
LLVM,RISCV,3143,"Predict the next statement of this code snippet:
 <s> static bool CC_<ISA_LIT>Assign2XLen ( unsigned XLen , CCState & State , CCValAssign VA1 , <STR_LIT> ArgFlags1 , unsigned ValNo2 , MVT ValVT2 , MVT LocVT2 , <STR_LIT> ArgFlags2 ) { unsigned XLenInBytes = XLen / <NUM_LIT> ; if ( unsigned Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , Reg , VA1 . getLocVT ( ) , CCValAssign :: Full ) ) ; } else { unsigned StackAlign = std :: max ( XLenInBytes , ArgFlags1 . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , State . AllocateStack ( XLenInBytes , StackAlign ) , VA1 . getLocVT ( ) , CCValAssign :: Full ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , XLenInBytes ) , LocVT2 , CCValAssign :: Full ) ) ; return false ; } if ( unsigned Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo2 , ValVT2 , Reg , LocVT2 , CCValAssign :: Full ) ) ; } else {"
LLVM,RISCV,3144,"Predict the next statement of this code snippet:
 <s> case CCValAssign :: Full : break ; case CCValAssign :: BCvt :"
LLVM,RISCV,3145,"Predict the next statement of this code snippet:
 <s> case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ;"
LLVM,RISCV,3146,"Predict the next statement of this code snippet:
 <s> break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ; break ; }"
LLVM,RISCV,3147,"Predict the next statement of this code snippet:
 <s> if ( isa < LoadInst > ( Inst ) && Ord == AtomicOrdering :: SequentiallyConsistent ) return Builder . CreateFence ( Ord ) ;"
LLVM,RISCV,3148,"Predict the next statement of this code snippet:
 <s> Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ; if ( XLen == <NUM_LIT> ) Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ;"
LLVM,RISCV,3149,"Predict the next statement of this code snippet:
 <s> <STR_LIT> CmpXchgIntrID = <STR_LIT> ; if ( XLen == <NUM_LIT> ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = <STR_LIT> ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ;"
LLVM,RISCV,3150,"Predict the next statement of this code snippet:
 <s> if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getIntN ( XLen , XLen - ValWidth ) , ShiftAmt ) ; Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ; } else {"
LLVM,RISCV,3151,"Predict the next statement of this code snippet:
 <s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ; return BB ;"
LLVM,RISCV,3152,"Predict the next statement of this code snippet:
 <s> Instruction * <ISA_LIT>TargetLowering :: emitTrailingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( isa < LoadInst > ( Inst ) && isAcquireOrStronger ( Ord ) ) return Builder . CreateFence ( AtomicOrdering :: Acquire ) ; return nullptr ;"
LLVM,RISCV,3153,"Predict the next statement of this code snippet:
 <s> if ( isa < LoadInst > ( Inst ) && isAcquireOrStronger ( Ord ) ) return Builder . CreateFence ( AtomicOrdering :: Acquire ) ;"
LLVM,RISCV,3154,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min : return <STR_LIT> ; case AtomicRMWInst :: UMax : return <STR_LIT> ; case AtomicRMWInst :: UMin : return <STR_LIT> ; } } if ( XLen == <NUM_LIT> ) { switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ;"
LLVM,RISCV,3155,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min : return <STR_LIT> ; case AtomicRMWInst :: UMax : return <STR_LIT> ; case AtomicRMWInst :: UMin : return <STR_LIT> ; } } if ( XLen == <NUM_LIT> ) { switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min : return <STR_LIT> ; case AtomicRMWInst :: UMax : return <STR_LIT> ; case AtomicRMWInst :: UMin : return <STR_LIT> ; } } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,3156,"Predict the next statement of this code snippet:
 <s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; } }"
LLVM,RISCV,3157,"Predict the next statement of this code snippet:
 <s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; }"
LLVM,RISCV,3158,"Predict the next statement of this code snippet:
 <s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; return VT . changeVectorElementTypeToInteger ( ) ;"
LLVM,RISCV,3159,"Predict the next statement of this code snippet:
 <s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const {"
LLVM,RISCV,3160,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,3161,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,RISCV,3162,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ;"
LLVM,RISCV,3163,"Predict the next statement of this code snippet:
 <s> auto CalleeCC = CLI . CallConv ; auto IsVarArg = CLI . IsVarArg ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) return false ; if ( Caller . hasFnAttribute ( <STR_LIT> ) ) return false ; if ( IsVarArg ) return false ; if ( CCInfo . getNextStackOffset ( ) != <NUM_LIT> ) return false ; for ( auto & VA : ArgLocs ) if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ;"
LLVM,RISCV,3164,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( ! AM . HasBaseReg ) break ;"
LLVM,RISCV,3165,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> > ( Imm ) ;"
LLVM,RISCV,3166,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isSExtCheaperThanZExt ( EVT SrcVT , EVT DstVT ) const { return Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ;"
LLVM,RISCV,3167,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isSExtCheaperThanZExt ( EVT SrcVT , EVT DstVT ) const {"
LLVM,RISCV,3168,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . is64Bit ( ) || SrcVT . isVector ( ) || DstVT . isVector ( ) || ! SrcVT . isInteger ( ) || ! DstVT . isInteger ( ) ) return false ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; unsigned DestBits = DstVT . getSizeInBits ( ) ; return ( SrcBits == <NUM_LIT> && DestBits == <NUM_LIT> ) ;"
LLVM,RISCV,3169,"Predict the next statement of this code snippet:
 <s> static bool isVariableSDivUDivURem ( SDValue Val ) { switch ( Val . getOpcode ( ) ) { default : return false ; case <STR_LIT> :"
LLVM,RISCV,3170,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3171,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( auto * LD = dyn_cast < LoadSDNode > ( Val ) ) { EVT MemVT = LD -> getMemoryVT ( ) ; if ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || ( Subtarget . is64Bit ( ) && MemVT == <STR_LIT> ) ) && ( LD -> getExtensionType ( ) == <STR_LIT> || LD -> getExtensionType ( ) == <STR_LIT> ) ) return true ; }"
LLVM,RISCV,3172,"Predict the next statement of this code snippet:
 <s> if ( isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue BAHi = DAG . getTargetBlockAddress ( BA , Ty , Offset , <STR_LIT> ) ; SDValue BALo = DAG . getTargetBlockAddress ( BA , Ty , Offset , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , BAHi ) , <NUM_LIT> ) ;"
LLVM,RISCV,3173,"Predict the next statement of this code snippet:
 <s> InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes ; } for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ;"
LLVM,RISCV,3174,"Predict the next statement of this code snippet:
 <s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) ArgValue = unpackF64OnRV32DSoftABI ( DAG , Chain , VA , DL ) ; else if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; assert ( Ins [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes ; } for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) {"
LLVM,RISCV,3175,"Predict the next statement of this code snippet:
 <s> while ( Depth -- ) { int Offset = - ( XLenInBytes * <NUM_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ;"
LLVM,RISCV,3176,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; unsigned FrameReg = RI . getFrameRegister ( MF ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;"
LLVM,RISCV,3177,"Predict the next statement of this code snippet:
 <s> EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = N -> getGlobal ( ) ; int64_t Offset = N -> getOffset ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , GAHi ) , <NUM_LIT> ) ; SDValue MNLo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , GALo ) , <NUM_LIT> ) ; if ( Offset != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Ty , MNLo , DAG . getConstant ( Offset , DL , XLenVT ) ) ;"
LLVM,RISCV,3178,"Predict the next statement of this code snippet:
 <s> SDValue GALo = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , GAHi ) , <NUM_LIT> ) ; SDValue MNLo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , GALo ) , <NUM_LIT> ) ; if ( Offset != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Ty , MNLo , DAG . getConstant ( Offset , DL , XLenVT ) ) ; return MNLo ;"
LLVM,RISCV,3179,"Predict the next statement of this code snippet:
 <s> switch ( Op . getOpcode ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> :"
LLVM,RISCV,3180,"Predict the next statement of this code snippet:
 <s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { int Off = - XLenInBytes ; SDValue FrameAddr = lowerFRAMEADDR ( Op , DAG ) ;"
LLVM,RISCV,3181,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget . getXLenVT ( ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { int Off = - XLenInBytes ; SDValue FrameAddr = lowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( Off , DL , VT ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( RI . getRARegister ( ) , getRegClassFor ( XLenVT ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , XLenVT ) ;"
LLVM,RISCV,3182,"Predict the next statement of this code snippet:
 <s> MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( Op . getSimpleValueType ( ) == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; auto CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; normaliseSetCC ( LHS , RHS , CCVal ) ; SDValue TargetCC = DAG . getConstant ( CCVal , DL , XLenVT ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;"
LLVM,RISCV,3183,"Predict the next statement of this code snippet:
 <s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;"
LLVM,RISCV,3184,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: lowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;"
LLVM,RISCV,3185,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ( CC ) ; std :: swap ( LHS , RHS ) ; break ; }"
LLVM,RISCV,3186,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . getXLen ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! DCI . isBeforeLegalize ( ) ) break ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || RHS -> getOpcode ( ) == <STR_LIT> || ( RHS -> getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( RHS -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) <= <NUM_LIT> ) ) break ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue NewRHS = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , RHS , DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ) ) ; return DCI . CombineTo ( N , DAG . getNode ( N -> getOpcode ( ) , DL , LHS . getValueType ( ) , LHS , NewRHS ) ) ; } case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || Src . getValueType ( ) != <STR_LIT> ) break ; if ( ! isVariableShift ( Src ) && ! ( Subtarget . hasStdExtM ( ) && isVariableSDivUDivURem ( Src ) ) ) break ; SDLoc DL ( N ) ;"
LLVM,RISCV,3187,"Predict the next statement of this code snippet:
 <s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override {"
LLVM,RISCV,3188,"Predict the next statement of this code snippet:
 <s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ;"
LLVM,RISCV,3189,"Predict the next statement of this code snippet:
 <s> unsigned Size = CI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size == <NUM_LIT> || Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ;"
LLVM,RISCV,3190,"Predict the next statement of this code snippet:
 <s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * CI ) const {"
LLVM,RISCV,3191,"Predict the next statement of this code snippet:
 <s> if ( Size == <NUM_LIT> || Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ;"
LLVM,RISCV,3192,"Predict the next statement of this code snippet:
 <s> assert ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; return DAG . getLoad ( <STR_LIT> , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; unsigned LoVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , LoVReg ) ; SDValue Lo = DAG . getCopyFromReg ( Chain , DL , LoVReg , <STR_LIT> ) ; SDValue Hi ; if ( VA . getLocReg ( ) == <STR_LIT> ) {"
LLVM,RISCV,3193,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; EVT ValVT = VA . getValVT ( ) ; EVT PtrVT = <STR_LIT> ( DAG . getDataLayout ( ) . getPointerSizeInBits ( <NUM_LIT> ) ) ;"
LLVM,RISCV,3194,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : ExtType = <STR_LIT> ; break ; } Val = DAG . getExtLoad ( ExtType , DL , LocVT , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , ValVT ) ; return Val ;"
LLVM,RISCV,3195,"Predict the next statement of this code snippet:
 <s> computeTables ( ) ;"
LLVM,RISCV,3196,"Predict the next statement of this code snippet:
 <s> getLegacyLegalizerInfo ( ) . computeTables ( ) ;"
LLVM,RISCV,3197,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LegalizerInfo :: <ISA_LIT>LegalizerInfo ( const <ISA_LIT>Subtarget & ST ) {"
LLVM,RISCV,3198,"Predict the next statement of this code snippet:
 <s> unsigned getCalleeSavedStackSize ( ) const { return CalleeSavedStackSize ;"
LLVM,RISCV,3199,"Predict the next statement of this code snippet:
 <s> uint64_t getRVVPadding ( ) const {"
LLVM,RISCV,3200,"Predict the next statement of this code snippet:
 <s> uint64_t getRVVPadding ( ) const { return RVVPadding ;"
LLVM,RISCV,3201,"Predict the next statement of this code snippet:
 <s> return RVVStackAlign ;"
LLVM,RISCV,3202,"Predict the next statement of this code snippet:
 <s> uint64_t getRVVStackSize ( ) const {"
LLVM,RISCV,3203,"Predict the next statement of this code snippet:
 <s> static void mapping ( IO & YamlIO , <ISA_LIT>MachineFunctionInfo & MFI ) {"
LLVM,RISCV,3204,"Predict the next statement of this code snippet:
 <s> void setCalleeSavedStackSize ( unsigned Size ) { CalleeSavedStackSize = Size ;"
LLVM,RISCV,3205,"Predict the next statement of this code snippet:
 <s> void setRVVStackAlign ( Align StackAlign ) {"
LLVM,RISCV,3206,"Predict the next statement of this code snippet:
 <s> RVVStackSize = Size ;"
LLVM,RISCV,3207,"Predict the next statement of this code snippet:
 <s> bool useSaveRestoreLibCalls ( const MachineFunction & MF ) const { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . enableSaveRestore ( ) && VarArgsSaveSize == <NUM_LIT> && ! MF . getFrameInfo ( ) . hasTailCall ( ) && ! MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ;"
LLVM,RISCV,3208,"Predict the next statement of this code snippet:
 <s> bool useSaveRestoreLibCalls ( ) const { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . enableSaveRestore ( ) && VarArgsSaveSize == <NUM_LIT> && ! MF . getFrameInfo ( ) . hasTailCall ( ) ;"
LLVM,RISCV,3209,"Predict the next statement of this code snippet:
 <s> bool useSaveRestoreLibCalls ( ) const {"
LLVM,RISCV,3210,"Predict the next statement of this code snippet:
 <s> for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { const <ISA_LIT>Subtarget * ST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterClass * RC = ST -> isRV64 ( ) ? & <STR_LIT> : & <STR_LIT> ; EhDataRegFI [ I ] = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; }"
LLVM,RISCV,3211,"Predict the next statement of this code snippet:
 <s> EhDataRegFI [ I ] = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; }"
LLVM,RISCV,3212,"Predict the next statement of this code snippet:
 <s> unsigned getLibCallStackSize ( ) const { return LibCallStackSize ;"
LLVM,RISCV,3213,"Predict the next statement of this code snippet:
 <s> unsigned getLibCallStackSize ( ) const { return LibCallStackSize ;"
LLVM,RISCV,3214,"Predict the next statement of this code snippet:
 <s> int getMoveF64FrameIndex ( MachineFunction & MF ) {"
LLVM,RISCV,3215,"Predict the next statement of this code snippet:
 <s> return CallsEhReturn && ( FI == EhDataRegFI [ <NUM_LIT> ] || FI == EhDataRegFI [ <NUM_LIT> ] ) ;"
LLVM,RISCV,3216,"Predict the next statement of this code snippet:
 <s> return Res != HwlpBasicBlocks . end ( ) ;"
LLVM,RISCV,3217,"Predict the next statement of this code snippet:
 <s> return Res != HwlpBasicBlocks . end ( ) ;"
LLVM,RISCV,3218,"Predict the next statement of this code snippet:
 <s> HwlpBasicBlocks . insert ( BB ) ;"
LLVM,RISCV,3219,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MachineFunctionInfo ( const MachineFunction & MF ) {"
LLVM,RISCV,3220,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MachineFunctionInfo ( const MachineFunction & MF ) {"
LLVM,RISCV,3221,"Predict the next statement of this code snippet:
 <s> void setLibCallStackSize ( unsigned Size ) { LibCallStackSize = Size ;"
LLVM,RISCV,3222,"Predict the next statement of this code snippet:
 <s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . enableSaveRestore ( ) && VarArgsSaveSize == <NUM_LIT> && ! MF . getFrameInfo ( ) . hasTailCall ( ) ;"
LLVM,RISCV,3223,"Predict the next statement of this code snippet:
 <s> return CallsEhReturn ;"
LLVM,RISCV,3224,"Predict the next statement of this code snippet:
 <s> bool getManipulatesSP ( ) const {"
LLVM,RISCV,3225,"Predict the next statement of this code snippet:
 <s> return ManipulatesSP ;"
LLVM,RISCV,3226,"Predict the next statement of this code snippet:
 <s> return SavedGPRFrameSize ;"
LLVM,RISCV,3227,"Predict the next statement of this code snippet:
 <s> unsigned getVarArgsFirstFPR ( ) const { return VarArgsFirstFPR ;"
LLVM,RISCV,3228,"Predict the next statement of this code snippet:
 <s> return VarArgsFirstGPR ;"
LLVM,RISCV,3229,"Predict the next statement of this code snippet:
 <s> return VarArgsFrameIndex ;"
LLVM,RISCV,3230,"Predict the next statement of this code snippet:
 <s> return HasByvalArg ;"
LLVM,RISCV,3231,"Predict the next statement of this code snippet:
 <s> return HasByvalArg ;"
LLVM,RISCV,3232,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : MF ( MF ) , SavedGPRFrameSize ( <NUM_LIT> ) , LowSavedGPR ( <NUM_LIT> ) , HighSavedGPR ( <NUM_LIT> ) , VarArgsFirstGPR ( <NUM_LIT> ) , VarArgsFirstFPR ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , RegSaveFrameIndex ( <NUM_LIT> ) , ManipulatesSP ( false ) , CallsEhReturn ( false ) {"
LLVM,RISCV,3233,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : MF ( MF ) , SavedGPRFrameSize ( <NUM_LIT> ) , LowSavedGPR ( <NUM_LIT> ) , HighSavedGPR ( <NUM_LIT> ) , VarArgsFirstGPR ( <NUM_LIT> ) , VarArgsFirstFPR ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , RegSaveFrameIndex ( <NUM_LIT> ) , ManipulatesSP ( false ) , CallsEhReturn ( false ) {"
LLVM,RISCV,3234,"Predict the next statement of this code snippet:
 <s> CallsEhReturn = ceret ;"
LLVM,RISCV,3235,"Predict the next statement of this code snippet:
 <s> CallsEhReturn = ceret ;"
LLVM,RISCV,3236,"Predict the next statement of this code snippet:
 <s> void setFormalArgInfo ( unsigned Size , bool HasByval ) {"
LLVM,RISCV,3237,"Predict the next statement of this code snippet:
 <s> void setHighSavedGPR ( unsigned Reg ) { HighSavedGPR = Reg ;"
LLVM,RISCV,3238,"Predict the next statement of this code snippet:
 <s> void setLowSavedGPR ( unsigned Reg ) {"
LLVM,RISCV,3239,"Predict the next statement of this code snippet:
 <s> void setManipulatesSP ( bool MSP ) {"
LLVM,RISCV,3240,"Predict the next statement of this code snippet:
 <s> void setRegSaveFrameIndex ( unsigned FI ) { RegSaveFrameIndex = FI ;"
LLVM,RISCV,3241,"Predict the next statement of this code snippet:
 <s> void setSavedGPRFrameSize ( unsigned bytes ) {"
LLVM,RISCV,3242,"Predict the next statement of this code snippet:
 <s> SavedGPRFrameSize = bytes ;"
LLVM,RISCV,3243,"Predict the next statement of this code snippet:
 <s> void setVarArgsFirstFPR ( unsigned FPR ) {"
LLVM,RISCV,3244,"Predict the next statement of this code snippet:
 <s> VarArgsFirstGPR = GPR ;"
LLVM,RISCV,3245,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {"
LLVM,RISCV,3246,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {"
LLVM,RISCV,3247,"Predict the next statement of this code snippet:
 <s> if ( MoveF64FrameIndex == - <NUM_LIT> ) MoveF64FrameIndex = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ;"
LLVM,RISCV,3248,"Predict the next statement of this code snippet:
 <s> if ( MoveF64FrameIndex == - <NUM_LIT> ) MoveF64FrameIndex = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ;"
LLVM,RISCV,3249,"Predict the next statement of this code snippet:
 <s> return VarArgsFrameIndex ;"
LLVM,RISCV,3250,"Predict the next statement of this code snippet:
 <s> VarArgsFrameIndex = YamlMFI . VarArgsFrameIndex ;"
LLVM,RISCV,3251,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MachineFunctionInfo :: initializeBaseYamlFields ( const yaml :: <ISA_LIT>MachineFunctionInfo & YamlMFI ) { VarArgsFrameIndex = YamlMFI . VarArgsFrameIndex ; VarArgsSaveSize = YamlMFI . VarArgsSaveSize ;"
LLVM,RISCV,3252,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : MF ( MF ) {"
LLVM,RISCV,3253,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : MF ( MF ) {"
LLVM,RISCV,3254,"Predict the next statement of this code snippet:
 <s> VarArgsFrameIndex = Index ;"
LLVM,RISCV,3255,"Predict the next statement of this code snippet:
 <s> void setVarArgsSaveSize ( int Size ) { VarArgsSaveSize = Size ;"
LLVM,RISCV,3256,"Predict the next statement of this code snippet:
 <s> VarArgsSaveSize = Size ;"
LLVM,RISCV,3257,"Predict the next statement of this code snippet:
 <s> } if ( MIs . size ( ) < <NUM_LIT> || ( RegImm . Imm != <NUM_LIT> && MIs . size ( ) < <NUM_LIT> ) ) return <STR_LIT> ; const TargetRegisterClass * RCToScavenge ; if ( <STR_LIT> . contains ( RegImm . Reg ) ) RCToScavenge = & <STR_LIT> ; else if ( <STR_LIT> . contains ( RegImm . Reg ) ) RCToScavenge = & <STR_LIT> ; else if ( <STR_LIT> . contains ( RegImm . Reg ) ) RCToScavenge = & <STR_LIT> ;"
LLVM,RISCV,3258,"Predict the next statement of this code snippet:
 <s> static uint8_t compressedLDSTOffsetMask ( unsigned Opcode ) {"
LLVM,RISCV,3259,"Predict the next statement of this code snippet:
 <s> static uint8_t compressedLDSTOffsetMask ( unsigned Opcode ) {"
LLVM,RISCV,3260,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>MakeCompressibleOptPass ( ) { return new <ISA_LIT>MakeCompressibleOpt ( ) ;"
LLVM,RISCV,3261,"Predict the next statement of this code snippet:
 <s> static int64_t getBaseAdjustForCompression ( int64_t Offset , unsigned Opcode ) {"
LLVM,RISCV,3262,"Predict the next statement of this code snippet:
 <s> static int64_t getBaseAdjustForCompression ( int64_t Offset , unsigned Opcode ) {"
LLVM,RISCV,3263,"Predict the next statement of this code snippet:
 <s> return <ISA_LIT>_COMPRESS_INSTRS_NAME ;"
LLVM,RISCV,3264,"Predict the next statement of this code snippet:
 <s> const unsigned Opcode = MI . getOpcode ( ) ; if ( isCompressibleLoad ( MI ) || isCompressibleStore ( MI ) ) { const MachineOperand & MOImm = MI . getOperand ( <NUM_LIT> ) ; if ( ! MOImm . isImm ( ) ) return RegImmPair ( <STR_LIT> , <NUM_LIT> ) ; int64_t Offset = MOImm . getImm ( ) ; int64_t NewBaseAdjust = getBaseAdjustForCompression ( Offset , Opcode ) ; Register Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( Base ) ) { if ( ! compressibleSPOffset ( Offset , Opcode ) && NewBaseAdjust ) return RegImmPair ( Base , NewBaseAdjust ) ; } else { Register SrcDest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool SrcDestCompressed = isCompressedReg ( SrcDest ) ; bool BaseCompressed = isCompressedReg ( Base ) ; if ( ( ! BaseCompressed || NewBaseAdjust ) && SrcDestCompressed ) return RegImmPair ( Base , NewBaseAdjust ) ; if ( isCompressibleStore ( MI ) ) { if ( ! SrcDestCompressed && ( BaseCompressed || SrcDest == Base ) && ! NewBaseAdjust ) return RegImmPair ( SrcDest , NewBaseAdjust ) ; } }"
LLVM,RISCV,3265,"Predict the next statement of this code snippet:
 <s> static RegImmPair getRegImmPairPreventingCompression ( const MachineInstr & MI ) { const unsigned Opcode = MI . getOpcode ( ) ; if ( isCompressibleLoad ( MI ) || isCompressibleStore ( MI ) ) { const MachineOperand & MOImm = MI . getOperand ( <NUM_LIT> ) ; if ( ! MOImm . isImm ( ) ) return RegImmPair ( <STR_LIT> , <NUM_LIT> ) ; int64_t Offset = MOImm . getImm ( ) ; int64_t NewBaseAdjust = getBaseAdjustForCompression ( Offset , Opcode ) ; Register Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( Base ) ) { if ( ! compressibleSPOffset ( Offset , Opcode ) && NewBaseAdjust ) return RegImmPair ( Base , NewBaseAdjust ) ; } else { Register SrcDest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool SrcDestCompressed = isCompressedReg ( SrcDest ) ; bool BaseCompressed = isCompressedReg ( Base ) ; if ( ( ! BaseCompressed || NewBaseAdjust ) && SrcDestCompressed ) return RegImmPair ( Base , NewBaseAdjust ) ;"
LLVM,RISCV,3266,"Predict the next statement of this code snippet:
 <s> static bool isCompressedReg ( Register Reg ) {"
LLVM,RISCV,3267,"Predict the next statement of this code snippet:
 <s> static bool isCompressedReg ( Register Reg ) {"
LLVM,RISCV,3268,"Predict the next statement of this code snippet:
 <s> const unsigned Opcode = MI . getOpcode ( ) ;"
LLVM,RISCV,3269,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget & STI = MI . getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const unsigned Opcode = MI . getOpcode ( ) ;"
LLVM,RISCV,3270,"Predict the next statement of this code snippet:
 <s> return Opcode == <STR_LIT> || ( ! STI . is64Bit ( ) && Opcode == <STR_LIT> ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;"
LLVM,RISCV,3271,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3272,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MakeCompressibleOpt ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,3273,"Predict the next statement of this code snippet:
 <s> SmallVector < MachineInstr * , <NUM_LIT> > MIs ; Register NewReg = analyzeCompressibleUses ( MI , RegImm , MIs ) ; if ( ! NewReg ) continue ; if ( <STR_LIT> . contains ( RegImm . Reg ) ) { assert ( isInt < <NUM_LIT> > ( RegImm . Imm ) ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , NewReg ) . addReg ( RegImm . Reg ) . addImm ( RegImm . Imm ) ; } else { assert ( RegImm . Imm == <NUM_LIT> ) ; unsigned Opcode = <STR_LIT> . contains ( RegImm . Reg ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( Opcode ) , NewReg ) . addReg ( RegImm . Reg ) . addReg ( RegImm . Reg ) ; } for ( MachineInstr * UpdateMI : MIs ) updateOperands ( * UpdateMI , RegImm , NewReg ) ; } }"
LLVM,RISCV,3274,"Predict the next statement of this code snippet:
 <s> if ( MO . isDef ( ) ) { assert ( isCompressibleLoad ( MI ) ) ; continue ; } MO . setReg ( NewReg ) ; } MachineOperand & MOImm = MI . getOperand ( <NUM_LIT> ) ; int64_t NewOffset = MOImm . getImm ( ) & compressedLDSTOffsetMask ( Opcode ) ; MOImm . setImm ( NewOffset ) ;"
LLVM,RISCV,3275,"Predict the next statement of this code snippet:
 <s> Inst ( unsigned Opc , int64_t Imm ) : Opc ( Opc ) , Imm ( Imm ) {"
LLVM,RISCV,3276,"Predict the next statement of this code snippet:
 <s> Inst ( unsigned Opc , int64_t Imm ) : Opc ( Opc ) , Imm ( Imm ) {"
LLVM,RISCV,3277,"Predict the next statement of this code snippet:
 <s> int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; generateInstSeq ( Hi52 , Is64Bit , Res ) ; Res . push_back ( Inst ( <STR_LIT> , ShiftAmount ) ) ; if ( Lo12 ) Res . push_back ( Inst ( <STR_LIT> , Lo12 ) ) ;"
LLVM,RISCV,3278,"Predict the next statement of this code snippet:
 <s> unsigned AddiOpc = ( Is64Bit && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( Inst ( AddiOpc , Lo12 ) ) ; } return ; } assert ( Is64Bit && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; generateInstSeq ( Hi52 , Is64Bit , Res ) ; Res . push_back ( Inst ( <STR_LIT> , ShiftAmount ) ) ; if ( Lo12 ) Res . push_back ( Inst ( <STR_LIT> , Lo12 ) ) ;"
LLVM,RISCV,3279,"Predict the next statement of this code snippet:
 <s> generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; }"
LLVM,RISCV,3280,"Predict the next statement of this code snippet:
 <s> if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( <STR_LIT> ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( <STR_LIT> ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ;"
LLVM,RISCV,3281,"Predict the next statement of this code snippet:
 <s> InstSeq generateInstSeq ( int64_t Val , bool IsRV64 ) { <STR_LIT> Res ; generateInstSeqImpl ( Val , IsRV64 , Res ) ; if ( Val > <NUM_LIT> && Res . size ( ) > <NUM_LIT> ) { assert ( IsRV64 && <STR_LIT> ) ; unsigned ShiftAmount = countLeadingZeros ( ( uint64_t ) Val ) ; Val <<= ShiftAmount ; Val |= maskTrailingOnes < uint64_t > ( ShiftAmount ) ; <STR_LIT> TmpSeq ; generateInstSeqImpl ( Val , IsRV64 , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; Val &= maskTrailingZeros < uint64_t > ( ShiftAmount ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( Val , IsRV64 , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } return Res ;"
LLVM,RISCV,3282,"Predict the next statement of this code snippet:
 <s> TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; Val &= maskTrailingZeros < uint64_t > ( ShiftAmount ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( Val , IsRV64 , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; }"
LLVM,RISCV,3283,"Predict the next statement of this code snippet:
 <s> if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( <STR_LIT> ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) {"
LLVM,RISCV,3284,"Predict the next statement of this code snippet:
 <s> APInt Chunk = Val . ashr ( ShiftVal ) . sextOrTrunc ( PlatRegSize ) ; InstSeq MatSeq = generateInstSeq ( Chunk . getSExtValue ( ) , IsRV64 ) ;"
LLVM,RISCV,3285,"Predict the next statement of this code snippet:
 <s> for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < Size ; ShiftVal += PlatRegSize ) {"
LLVM,RISCV,3286,"Predict the next statement of this code snippet:
 <s> generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } ShiftedVal &= maskTrailingZeros < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ;"
LLVM,RISCV,3287,"Predict the next statement of this code snippet:
 <s> bool IsRV64 = ActiveFeatures [ <STR_LIT> ] ; if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( <STR_LIT> ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( <STR_LIT> ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( ( uint64_t ) Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; bool Unsigned = false ;"
LLVM,RISCV,3288,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Compressed = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Compressed = isInt < <NUM_LIT> > ( Instr . Imm ) ; break ; case <STR_LIT> : Compressed = false ; break ;"
LLVM,RISCV,3289,"Predict the next statement of this code snippet:
 <s> int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( ( uint64_t ) Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; generateInstSeq ( Hi52 , IsRV64 , Res ) ;"
LLVM,RISCV,3290,"Predict the next statement of this code snippet:
 <s> if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( Inst ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( Inst ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( ( uint64_t ) Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; generateInstSeq ( Hi52 , IsRV64 , Res ) ; Res . push_back ( Inst ( <STR_LIT> , ShiftAmount ) ) ;"
LLVM,RISCV,3291,"Predict the next statement of this code snippet:
 <s> generateInstSeq ( Chunk . getSExtValue ( ) , IsRV64 , MatSeq ) ; Cost += MatSeq . size ( ) ; }"
LLVM,RISCV,3292,"Predict the next statement of this code snippet:
 <s> int PlatRegSize = IsRV64 ? <NUM_LIT> : <NUM_LIT> ; int Cost = <NUM_LIT> ; for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < Size ; ShiftVal += PlatRegSize ) { APInt Chunk = Val . ashr ( ShiftVal ) . sextOrTrunc ( PlatRegSize ) ; InstSeq MatSeq ;"
LLVM,RISCV,3293,"Predict the next statement of this code snippet:
 <s> unsigned LowerLeadingOnes = countLeadingOnes ( Lo_32 ( Val ) ) ; if ( UpperTrailingOnes < <NUM_LIT> && ( UpperTrailingOnes + LowerLeadingOnes ) > ( <NUM_LIT> - <NUM_LIT> ) ) return <NUM_LIT> - UpperTrailingOnes ; return <NUM_LIT> ;"
LLVM,RISCV,3294,"Predict the next statement of this code snippet:
 <s> if ( TrailingOnes > <NUM_LIT> && TrailingOnes < <NUM_LIT> && ( LeadingOnes + TrailingOnes ) > ( <NUM_LIT> - <NUM_LIT> ) ) return <NUM_LIT> - TrailingOnes ; unsigned UpperTrailingOnes = countTrailingOnes ( Hi_32 ( Val ) ) ; unsigned LowerLeadingOnes = countLeadingOnes ( Lo_32 ( Val ) ) ; if ( UpperTrailingOnes < <NUM_LIT> && ( UpperTrailingOnes + LowerLeadingOnes ) > ( <NUM_LIT> - <NUM_LIT> ) ) return <NUM_LIT> - UpperTrailingOnes ; return <NUM_LIT> ;"
LLVM,RISCV,3295,"Predict the next statement of this code snippet:
 <s> if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t NewVal ; unsigned Opc ; if ( Val < <NUM_LIT> ) { Opc = <STR_LIT> ; NewVal = Val | <NUM_LIT> ; } else { Opc = <STR_LIT> ; NewVal = Val & ~ <NUM_LIT> ; } if ( isInt < <NUM_LIT> > ( NewVal ) ) { <STR_LIT> TmpSeq ; generateInstSeqImpl ( NewVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } int32_t Lo = Val ; uint32_t Hi = Val >> <NUM_LIT> ; Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ; generateInstSeqImpl ( Lo , ActiveFeatures , TmpSeq ) ; if ( Lo > <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; } else if ( Lo < <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( ~ Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; Hi = ~ Hi ; } if ( Opc > <NUM_LIT> ) { while ( Hi != <NUM_LIT> ) { unsigned Bit = countTrailingZeros ( Hi ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , Bit + <NUM_LIT> ) ) ; Hi &= ~ ( <NUM_LIT> << Bit ) ; } if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t Div = <NUM_LIT> ; unsigned Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ;"
LLVM,RISCV,3296,"Predict the next statement of this code snippet:
 <s> bool Unsigned = false ; if ( ShiftAmount > <NUM_LIT> && ! isInt < <NUM_LIT> > ( Hi52 ) ) { if ( isInt < <NUM_LIT> > ( ( uint64_t ) Hi52 << <NUM_LIT> ) ) { ShiftAmount -= <NUM_LIT> ; Hi52 = ( uint64_t ) Hi52 << <NUM_LIT> ; } else if ( isUInt < <NUM_LIT> > ( ( uint64_t ) Hi52 << <NUM_LIT> ) && ActiveFeatures [ <STR_LIT> ] ) { ShiftAmount -= <NUM_LIT> ; Hi52 = ( ( uint64_t ) Hi52 << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; Unsigned = true ; } } if ( isUInt < <NUM_LIT> > ( ( uint64_t ) Hi52 ) && ! isInt < <NUM_LIT> > ( ( uint64_t ) Hi52 ) && ActiveFeatures [ <STR_LIT> ] ) { Hi52 = ( ( uint64_t ) Hi52 ) | ( <NUM_LIT> << <NUM_LIT> ) ; Unsigned = true ; } generateInstSeqImpl ( Hi52 , ActiveFeatures , Res ) ; if ( Unsigned ) Res . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; else Res . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ;"
LLVM,RISCV,3297,"Predict the next statement of this code snippet:
 <s> bool Compressed ; switch ( Instr . Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Compressed = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Compressed = isInt < <NUM_LIT> > ( Instr . Imm ) ; break ; case <STR_LIT> : Compressed = false ; break ; } if ( ! Compressed ) Cost += <NUM_LIT> ; else Cost += <NUM_LIT> ; } return Cost ;"
LLVM,RISCV,3298,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : Compressed = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Compressed = isInt < <NUM_LIT> > ( Instr . Imm ) ; break ; case <STR_LIT> : Compressed = false ; break ; } if ( ! Compressed ) Cost += <NUM_LIT> ; else Cost += <NUM_LIT> ;"
LLVM,RISCV,3299,"Predict the next statement of this code snippet:
 <s> if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } ShiftedVal &= maskTrailingZeros < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t NewVal ; unsigned Opc ; if ( Val < <NUM_LIT> ) { Opc = <STR_LIT> ; NewVal = Val | <NUM_LIT> ; } else { Opc = <STR_LIT> ; NewVal = Val & ~ <NUM_LIT> ; } if ( isInt < <NUM_LIT> > ( NewVal ) ) { <STR_LIT> TmpSeq ; generateInstSeqImpl ( NewVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } int32_t Lo = Val ; uint32_t Hi = Val >> <NUM_LIT> ; Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ; generateInstSeqImpl ( Lo , ActiveFeatures , TmpSeq ) ; if ( Lo > <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; } else if ( Lo < <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( ~ Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; Hi = ~ Hi ; } if ( Opc > <NUM_LIT> ) { while ( Hi != <NUM_LIT> ) { unsigned Bit = countTrailingZeros ( Hi ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , Bit + <NUM_LIT> ) ) ; Hi &= ~ ( <NUM_LIT> << Bit ) ; }"
LLVM,RISCV,3300,"Predict the next statement of this code snippet:
 <s> if ( Hi20 ) Res . push_back ( Inst ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( Inst ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ;"
LLVM,RISCV,3301,"Predict the next statement of this code snippet:
 <s> if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } ShiftedVal &= maskTrailingZeros < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t NewVal ; unsigned Opc ; if ( Val < <NUM_LIT> ) { Opc = <STR_LIT> ; NewVal = Val | <NUM_LIT> ; } else { Opc = <STR_LIT> ; NewVal = Val & ~ <NUM_LIT> ; } if ( isInt < <NUM_LIT> > ( NewVal ) ) { <STR_LIT> TmpSeq ; generateInstSeqImpl ( NewVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } int32_t Lo = Val ; uint32_t Hi = Val >> <NUM_LIT> ; Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ; generateInstSeqImpl ( Lo , ActiveFeatures , TmpSeq ) ; if ( Lo > <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; } else if ( Lo < <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( ~ Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; Hi = ~ Hi ; } if ( Opc > <NUM_LIT> ) { while ( Hi != <NUM_LIT> ) { unsigned Bit = countTrailingZeros ( Hi ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , Bit + <NUM_LIT> ) ) ; Hi &= ~ ( <NUM_LIT> << Bit ) ; } if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t Div = <NUM_LIT> ; unsigned Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ;"
LLVM,RISCV,3302,"Predict the next statement of this code snippet:
 <s> bool Unsigned = false ; if ( ! isInt < <NUM_LIT> > ( Val ) ) { ShiftAmount = findFirstSet ( ( uint64_t ) Val ) ; Val >>= ShiftAmount ; if ( ShiftAmount > <NUM_LIT> && ! isInt < <NUM_LIT> > ( Val ) ) { if ( isInt < <NUM_LIT> > ( ( uint64_t ) Val << <NUM_LIT> ) ) { ShiftAmount -= <NUM_LIT> ; Val = ( uint64_t ) Val << <NUM_LIT> ; } else if ( isUInt < <NUM_LIT> > ( ( uint64_t ) Val << <NUM_LIT> ) && ActiveFeatures [ <STR_LIT> ] ) { ShiftAmount -= <NUM_LIT> ; Val = ( ( uint64_t ) Val << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; Unsigned = true ; } } if ( isUInt < <NUM_LIT> > ( ( uint64_t ) Val ) && ! isInt < <NUM_LIT> > ( ( uint64_t ) Val ) && ActiveFeatures [ <STR_LIT> ] ) { Val = ( ( uint64_t ) Val ) | ( <NUM_LIT> << <NUM_LIT> ) ; Unsigned = true ; } }"
LLVM,RISCV,3303,"Predict the next statement of this code snippet:
 <s> if ( ! HasRVC ) return Res . size ( ) ; int Cost = <NUM_LIT> ; for ( auto Instr : Res ) { bool Compressed = false ; switch ( Instr . Opc ) { case <STR_LIT> : case <STR_LIT> : Compressed = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Compressed = isInt < <NUM_LIT> > ( Instr . Imm ) ;"
LLVM,RISCV,3304,"Predict the next statement of this code snippet:
 <s> generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t NewVal ; unsigned Opc ; if ( Val < <NUM_LIT> ) { Opc = <STR_LIT> ; NewVal = Val | <NUM_LIT> ; } else { Opc = <STR_LIT> ; NewVal = Val & ~ <NUM_LIT> ; } if ( isInt < <NUM_LIT> > ( NewVal ) ) { <STR_LIT> TmpSeq ; generateInstSeqImpl ( NewVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } int32_t Lo = Val ; uint32_t Hi = Val >> <NUM_LIT> ; Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ; generateInstSeqImpl ( Lo , ActiveFeatures , TmpSeq ) ; if ( Lo > <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; } else if ( Lo < <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( ~ Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; Hi = ~ Hi ; } if ( Opc > <NUM_LIT> ) { while ( Hi != <NUM_LIT> ) { unsigned Bit = countTrailingZeros ( Hi ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , Bit + <NUM_LIT> ) ) ; Hi &= ~ ( <NUM_LIT> << Bit ) ; } if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t Div = <NUM_LIT> ;"
LLVM,RISCV,3305,"Predict the next statement of this code snippet:
 <s> if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( <STR_LIT> ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( <STR_LIT> ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( ( uint64_t ) Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; bool Unsigned = false ;"
LLVM,RISCV,3306,"Predict the next statement of this code snippet:
 <s> for ( auto Instr : Res ) { bool Compressed ; switch ( Instr . Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Compressed = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Compressed = isInt < <NUM_LIT> > ( Instr . Imm ) ; break ;"
LLVM,RISCV,3307,"Predict the next statement of this code snippet:
 <s> int PlatRegSize = IsRV64 ? <NUM_LIT> : <NUM_LIT> ; int Cost = <NUM_LIT> ; for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < Size ; ShiftVal += PlatRegSize ) { APInt Chunk = Val . ashr ( ShiftVal ) . sextOrTrunc ( PlatRegSize ) ; InstSeq MatSeq = generateInstSeq ( Chunk . getSExtValue ( ) , ActiveFeatures ) ; Cost += getInstSeqCost ( MatSeq , HasRVC ) ; } return std :: max ( <NUM_LIT> , Cost ) ;"
LLVM,RISCV,3308,"Predict the next statement of this code snippet:
 <s> for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < Size ; ShiftVal += PlatRegSize ) { APInt Chunk = Val . ashr ( ShiftVal ) . sextOrTrunc ( PlatRegSize ) ; InstSeq MatSeq = generateInstSeq ( Chunk . getSExtValue ( ) , ActiveFeatures ) ; Cost += getInstSeqCost ( MatSeq , HasRVC ) ; }"
LLVM,RISCV,3309,"Predict the next statement of this code snippet:
 <s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ;"
LLVM,RISCV,3310,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCAsmBackend :: relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { unsigned Opcode = getRelaxedOpcode ( Inst . getOpcode ( ) ) ;"
LLVM,RISCV,3311,"Predict the next statement of this code snippet:
 <s> MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU ) {"
LLVM,RISCV,3312,"Predict the next statement of this code snippet:
 <s> } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override ; bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override ; void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override ; bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ;"
LLVM,RISCV,3313,"Predict the next statement of this code snippet:
 <s> Value = extractBitsForFixup ( Fixup . getKind ( ) , Value ) ;"
LLVM,RISCV,3314,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>MCAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const { Value = extractBitsForFixup ( Fixup . getKind ( ) , Value ) ; return ( int16_t ) Value != ( int64_t ) Value ;"
LLVM,RISCV,3315,"Predict the next statement of this code snippet:
 <s> assert ( Opcode && <STR_LIT> ) ; Res = Inst ; Res . setOpcode ( Opcode ) ;"
LLVM,RISCV,3316,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) {"
LLVM,RISCV,3317,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) {"
LLVM,RISCV,3318,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>MCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OW -> write8 ( <NUM_LIT> ) ;"
LLVM,RISCV,3319,"Predict the next statement of this code snippet:
 <s> CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ;"
LLVM,RISCV,3320,"Predict the next statement of this code snippet:
 <s> const MCExpr * <ISA_LIT>MCAsmInfo :: getExprForFDESymbol ( const MCSymbol * Sym , unsigned Encoding , MCStreamer & Streamer ) const { if ( ! ( Encoding & dwarf :: DW_EH_PE_pcrel ) ) return MCAsmInfo :: getExprForFDESymbol ( Sym , Encoding , Streamer ) ;"
LLVM,RISCV,3321,"Predict the next statement of this code snippet:
 <s> CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ;"
LLVM,RISCV,3322,"Predict the next statement of this code snippet:
 <s> AlignmentIsInBytes = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ;"
LLVM,RISCV,3323,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {"
LLVM,RISCV,3324,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {"
LLVM,RISCV,3325,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ;"
LLVM,RISCV,3326,"Predict the next statement of this code snippet:
 <s> CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; Data16bitsDirective = <STR_LIT> ;"
LLVM,RISCV,3327,"Predict the next statement of this code snippet:
 <s> IsCheriPurecapABI = ABI != <STR_LIT> && <STR_LIT> ( ABI ) ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ;"
LLVM,RISCV,3328,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { PointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,3329,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) {"
LLVM,RISCV,3330,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ;"
LLVM,RISCV,3331,"Predict the next statement of this code snippet:
 <s> Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;"
LLVM,RISCV,3332,"Predict the next statement of this code snippet:
 <s> Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ; const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addExpr ( CallExpr ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,3333,"Predict the next statement of this code snippet:
 <s> if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax ) { if ( FixupKind == <STR_LIT> ) {"
LLVM,RISCV,3334,"Predict the next statement of this code snippet:
 <s> <STR_LIT> FixupKind = <STR_LIT> ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax ) { if ( FixupKind == <STR_LIT> ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ;"
LLVM,RISCV,3335,"Predict the next statement of this code snippet:
 <s> MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { expandVMSGE ( MI , OS , Fixups , STI ) ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; }"
LLVM,RISCV,3336,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } if ( MI . getNumOperands ( ) == <NUM_LIT> ) { TmpInst = MCInstBuilder ( Opcode ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; } else if ( MI . getNumOperands ( ) == <NUM_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; TmpInst = MCInstBuilder ( Opcode ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; } else if ( MI . getNumOperands ( ) == <NUM_LIT> ) {"
LLVM,RISCV,3337,"Predict the next statement of this code snippet:
 <s> expandFunctionCall ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandCIncOffsetTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : {"
LLVM,RISCV,3338,"Predict the next statement of this code snippet:
 <s> MCOperand DestReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand TPReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand SrcReg = MI . getOperand ( <NUM_LIT> ) ; assert ( TPReg . isReg ( ) && TPReg . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MCOperand SrcSymbol = MI . getOperand ( <NUM_LIT> ) ; assert ( SrcSymbol . isExpr ( ) && <STR_LIT> ) ; const <ISA_LIT>MCExpr * Expr = dyn_cast < <ISA_LIT>MCExpr > ( SrcSymbol . getExpr ( ) ) ; assert ( Expr && Expr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_CINCOFFSET && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ;"
LLVM,RISCV,3339,"Predict the next statement of this code snippet:
 <s> assert ( Expr && Expr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_CINCOFFSET && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; }"
LLVM,RISCV,3340,"Predict the next statement of this code snippet:
 <s> IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; IsCap = true ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = true ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; IsCap = true ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = true ; } uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ;"
LLVM,RISCV,3341,"Predict the next statement of this code snippet:
 <s> FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CAPTAB_PCREL_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_CINCOFFSET : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CCALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) FixupKind = <STR_LIT> ; else FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; }"
LLVM,RISCV,3342,"Predict the next statement of this code snippet:
 <s> Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ; const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;"
LLVM,RISCV,3343,"Predict the next statement of this code snippet:
 <s> unsigned Size = Desc . getSize ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { expandFunctionCall ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write ( OS , Bits , <STR_LIT> ) ; break ; } } ++ MCNumEmitted ;"
LLVM,RISCV,3344,"Predict the next statement of this code snippet:
 <s> } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write ( OS , Bits , <STR_LIT> ) ;"
LLVM,RISCV,3345,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCCodeEmitter :: expandFunctionCall ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { MCInst TmpInst ; MCOperand Func ; Register Ra ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;"
LLVM,RISCV,3346,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>MCCodeEmitter ( Ctx , MCII ) ;"
LLVM,RISCV,3347,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { expandFunctionCall ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; }"
LLVM,RISCV,3348,"Predict the next statement of this code snippet:
 <s> expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : {"
LLVM,RISCV,3349,"Predict the next statement of this code snippet:
 <s> MCOperand DestReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand SrcReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand TPReg = MI . getOperand ( <NUM_LIT> ) ; assert ( TPReg . isReg ( ) && TPReg . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MCOperand SrcSymbol = MI . getOperand ( <NUM_LIT> ) ; assert ( SrcSymbol . isExpr ( ) && <STR_LIT> ) ; const <ISA_LIT>MCExpr * Expr = dyn_cast < <ISA_LIT>MCExpr > ( SrcSymbol . getExpr ( ) ) ; assert ( Expr && Expr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ;"
LLVM,RISCV,3350,"Predict the next statement of this code snippet:
 <s> MCOperand DestReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand SrcReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand TPReg = MI . getOperand ( <NUM_LIT> ) ; assert ( TPReg . isReg ( ) && TPReg . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MCOperand SrcSymbol = MI . getOperand ( <NUM_LIT> ) ; assert ( SrcSymbol . isExpr ( ) && <STR_LIT> ) ; const <ISA_LIT>MCExpr * Expr = dyn_cast < <ISA_LIT>MCExpr > ( SrcSymbol . getExpr ( ) ) ;"
LLVM,RISCV,3351,"Predict the next statement of this code snippet:
 <s> Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ; const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;"
LLVM,RISCV,3352,"Predict the next statement of this code snippet:
 <s> TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,3353,"Predict the next statement of this code snippet:
 <s> switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) {"
LLVM,RISCV,3354,"Predict the next statement of this code snippet:
 <s> assert ( MO . isReg ( ) && <STR_LIT> ) ; switch ( MO . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; }"
LLVM,RISCV,3355,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write ( Bits ) ; ++ MCNumEmitted ;"
LLVM,RISCV,3356,"Predict the next statement of this code snippet:
 <s> uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write ( Bits ) ;"
LLVM,RISCV,3357,"Predict the next statement of this code snippet:
 <s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; <STR_LIT> FixupKind = <STR_LIT> ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = MIFrm == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) {"
LLVM,RISCV,3358,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCCodeEmitter ( MCContext & ctx ) : Ctx ( ctx ) {"
LLVM,RISCV,3359,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCCodeEmitter ( MCContext & ctx ) : Ctx ( ctx ) {"
LLVM,RISCV,3360,"Predict the next statement of this code snippet:
 <s> switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint16_t > ( Bits ) ; break ; } case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write ( Bits ) ; break ; } } ++ MCNumEmitted ;"
LLVM,RISCV,3361,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ;"
LLVM,RISCV,3362,"Predict the next statement of this code snippet:
 <s> unsigned Size = Desc . getSize ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { expandFunctionCall ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; }"
LLVM,RISCV,3363,"Predict the next statement of this code snippet:
 <s> if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { expandFunctionCall ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : {"
LLVM,RISCV,3364,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>MCCodeEmitter :: getImmOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; MCInstrDesc const & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned MIFrm = Desc . TSFlags & <STR_LIT> ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; <STR_LIT> FixupKind = <STR_LIT> ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = MIFrm == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ;"
LLVM,RISCV,3365,"Predict the next statement of this code snippet:
 <s> RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { if ( MI . getNumOperands ( ) == <NUM_LIT> ) { auto & MOCount = MI . getOperand ( <NUM_LIT> ) ; if ( MOCount . isReg ( ) ) FixupKind = <STR_LIT> ; else FixupKind = <STR_LIT> ; } else {"
LLVM,RISCV,3366,"Predict the next statement of this code snippet:
 <s> bool RelaxCandidate = false ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) {"
LLVM,RISCV,3367,"Predict the next statement of this code snippet:
 <s> case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ;"
LLVM,RISCV,3368,"Predict the next statement of this code snippet:
 <s> bool EnableRelax = STI . getFeatureBits ( ) [ <STR_LIT> ] ; const MCOperand & MO = MI . getOperand ( OpNo ) ; MCInstrDesc const & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned MIFrm = Desc . TSFlags & <STR_LIT> ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; <STR_LIT> FixupKind = <STR_LIT> ; bool RelaxCandidate = false ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ;"
LLVM,RISCV,3369,"Predict the next statement of this code snippet:
 <s> MCOperand Func ; unsigned Ra ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; } uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ; const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;"
LLVM,RISCV,3370,"Predict the next statement of this code snippet:
 <s> const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,3371,"Predict the next statement of this code snippet:
 <s> FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; } return <NUM_LIT> ;"
LLVM,RISCV,3372,"Predict the next statement of this code snippet:
 <s> FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FixupKind = <STR_LIT> ; break ; case <STR_LIT> : FixupKind = <STR_LIT> ; break ; default : break ; } } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ;"
LLVM,RISCV,3373,"Predict the next statement of this code snippet:
 <s> case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FixupKind = <STR_LIT> ; break ; case <STR_LIT> : FixupKind = <STR_LIT> ; break ; default : break ; } } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; } return <NUM_LIT> ;"
LLVM,RISCV,3374,"Predict the next statement of this code snippet:
 <s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) {"
LLVM,RISCV,3375,"Predict the next statement of this code snippet:
 <s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) {"
LLVM,RISCV,3376,"Predict the next statement of this code snippet:
 <s> unsigned ShiftValue = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) {"
LLVM,RISCV,3377,"Predict the next statement of this code snippet:
 <s> unsigned getBranchTargetEncoding ( const MCInst & MI , unsigned int OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) << <NUM_LIT> ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;"
LLVM,RISCV,3378,"Predict the next statement of this code snippet:
 <s> const MCOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) << <NUM_LIT> ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return <NUM_LIT> ;"
LLVM,RISCV,3379,"Predict the next statement of this code snippet:
 <s> unsigned getCallEncoding ( const MCInst & MI , unsigned int OpNum , SmallVectorImpl < MCFixup > & Fixups ) const {"
LLVM,RISCV,3380,"Predict the next statement of this code snippet:
 <s> const MCOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) << <NUM_LIT> ;"
LLVM,RISCV,3381,"Predict the next statement of this code snippet:
 <s> unsigned getJumpTargetEncoding ( const MCInst & MI , unsigned int OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNum ) ;"
LLVM,RISCV,3382,"Predict the next statement of this code snippet:
 <s> if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ;"
LLVM,RISCV,3383,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;"
LLVM,RISCV,3384,"Predict the next statement of this code snippet:
 <s> if ( MO . isImm ( ) ) return MO . getImm ( ) << <NUM_LIT> ;"
LLVM,RISCV,3385,"Predict the next statement of this code snippet:
 <s> if ( MO . isImm ( ) ) return MO . getImm ( ) << <NUM_LIT> ;"
LLVM,RISCV,3386,"Predict the next statement of this code snippet:
 <s> unsigned getPCImmEncoding ( const MCInst & MI , unsigned int OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNum ) ;"
LLVM,RISCV,3387,"Predict the next statement of this code snippet:
 <s> if ( MO . isImm ( ) ) return MO . getImm ( ) / <NUM_LIT> ; const MCExpr * Expr = MO . getExpr ( ) ; if ( Offset ) {"
LLVM,RISCV,3388,"Predict the next statement of this code snippet:
 <s> if ( MO . isImm ( ) ) return MO . getImm ( ) / <NUM_LIT> ; const MCExpr * Expr = MO . getExpr ( ) ; if ( Offset ) {"
LLVM,RISCV,3389,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , Ctx ( ctx ) {"
LLVM,RISCV,3390,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , Ctx ( ctx ) {"
LLVM,RISCV,3391,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>MCCodeEmitter ( ) {"
LLVM,RISCV,3392,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>MCCodeEmitter ( ) {"
LLVM,RISCV,3393,"Predict the next statement of this code snippet:
 <s> if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write ( OS , Bits , <STR_LIT> ) ; break ; } } ++ MCNumEmitted ;"
LLVM,RISCV,3394,"Predict the next statement of this code snippet:
 <s> const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,3395,"Predict the next statement of this code snippet:
 <s> break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; return <NUM_LIT> ;"
LLVM,RISCV,3396,"Predict the next statement of this code snippet:
 <s> case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ;"
LLVM,RISCV,3397,"Predict the next statement of this code snippet:
 <s> const MCExpr * CallExpr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL , Ctx ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,3398,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = MIFrm == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : FixupKind = MIFrm == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,3399,"Predict the next statement of this code snippet:
 <s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( Ctx , MCII ) ;"
LLVM,RISCV,3400,"Predict the next statement of this code snippet:
 <s> } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : {"
LLVM,RISCV,3401,"Predict the next statement of this code snippet:
 <s> if ( MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ;"
LLVM,RISCV,3402,"Predict the next statement of this code snippet:
 <s> unsigned Ra = ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = Func . getExpr ( ) ; const MCExpr * CallExpr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL , Ctx ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ;"
LLVM,RISCV,3403,"Predict the next statement of this code snippet:
 <s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; <STR_LIT> FixupKind = <STR_LIT> ; bool RelaxCandidate = false ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ;"
LLVM,RISCV,3404,"Predict the next statement of this code snippet:
 <s> bool RelaxCandidate = false ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) {"
LLVM,RISCV,3405,"Predict the next statement of this code snippet:
 <s> unsigned Res = MO . getImm ( ) ; assert ( ( Res & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,3406,"Predict the next statement of this code snippet:
 <s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,3407,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCCodeEmitter ( MCContext & ctx , MCInstrInfo const & MCII ) : Ctx ( ctx ) , MCII ( MCII ) {"
LLVM,RISCV,3408,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCCodeEmitter ( MCContext & ctx , MCInstrInfo const & MCII ) : Ctx ( ctx ) , MCII ( MCII ) {"
LLVM,RISCV,3409,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>MCCodeEmitter ( ) override {"
LLVM,RISCV,3410,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>MCCodeEmitter ( ) override {"
LLVM,RISCV,3411,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) {"
LLVM,RISCV,3412,"Predict the next statement of this code snippet:
 <s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ;"
LLVM,RISCV,3413,"Predict the next statement of this code snippet:
 <s> case VK_<ISA_LIT>_HI : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; }"
LLVM,RISCV,3414,"Predict the next statement of this code snippet:
 <s> if ( ! AUIPCSymbol ) return false ; const MCFixup * TargetFixup = getPCRelHiFixup ( ) ; if ( ! TargetFixup ) return false ; if ( ( unsigned ) TargetFixup -> getKind ( ) != <STR_LIT> ) return false ; MCValue Target ; if ( ! TargetFixup -> getValue ( ) -> evaluateAsValue ( Target , * Layout ) ) return false ; if ( ! Target . getSymA ( ) || ! Target . getSymA ( ) -> getSymbol ( ) . isInSection ( ) ) return false ; if ( & Target . getSymA ( ) -> getSymbol ( ) . getSection ( ) != findAssociatedFragment ( ) -> getParent ( ) ) return false ; uint64_t AUIPCOffset = AUIPCSymbol -> getOffset ( ) ; Res = MCValue :: get ( Target . getSymA ( ) , nullptr , Target . getConstant ( ) + ( Fixup -> getOffset ( ) - AUIPCOffset ) ) ; return true ;"
LLVM,RISCV,3415,"Predict the next statement of this code snippet:
 <s> const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE ) return nullptr ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSRE -> findAssociatedFragment ( ) ) ; if ( ! DF ) return nullptr ;"
LLVM,RISCV,3416,"Predict the next statement of this code snippet:
 <s> if ( ! DF ) return nullptr ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != AUIPCSymbol -> getOffset ( ) ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case <STR_LIT> : return & F ; } }"
LLVM,RISCV,3417,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind <ISA_LIT>MCExpr :: getVariantKindForName ( StringRef name ) { return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;"
LLVM,RISCV,3418,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : return <STR_LIT> ; case VK_<ISA_LIT>_HI : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_LO : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_HI : return <STR_LIT> ; }"
LLVM,RISCV,3419,"Predict the next statement of this code snippet:
 <s> if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ; if ( HasVariant ) OS << ')' ;"
LLVM,RISCV,3420,"Predict the next statement of this code snippet:
 <s> if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ; if ( HasVariant ) OS << ')' ;"
LLVM,RISCV,3421,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const {"
LLVM,RISCV,3422,"Predict the next statement of this code snippet:
 <s> Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;"
LLVM,RISCV,3423,"Predict the next statement of this code snippet:
 <s> MCValue Value ; if ( Kind == VK_<ISA_LIT>_PCREL_HI || Kind == VK_<ISA_LIT>_PCREL_LO || Kind == VK_<ISA_LIT>_GOT_HI || Kind == VK_<ISA_LIT>_TPREL_HI || Kind == VK_<ISA_LIT>_TPREL_LO || Kind == VK_<ISA_LIT>_TPREL_ADD || Kind == VK_<ISA_LIT>_TLS_GOT_HI || Kind == VK_<ISA_LIT>_TLS_GD_HI || Kind == VK_<ISA_LIT>_CALL || Kind == VK_<ISA_LIT>_CALL_PLT ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ;"
LLVM,RISCV,3424,"Predict the next statement of this code snippet:
 <s> MCValue Value ; if ( Kind == VK_<ISA_LIT>_PCREL_HI || Kind == VK_<ISA_LIT>_PCREL_LO || Kind == VK_<ISA_LIT>_GOT_HI || Kind == VK_<ISA_LIT>_TPREL_HI || Kind == VK_<ISA_LIT>_TPREL_LO || Kind == VK_<ISA_LIT>_TPREL_ADD || Kind == VK_<ISA_LIT>_TLS_GOT_HI || Kind == VK_<ISA_LIT>_TLS_GD_HI || Kind == VK_<ISA_LIT>_CALL || Kind == VK_<ISA_LIT>_CALL_PLT ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ;"
LLVM,RISCV,3425,"Predict the next statement of this code snippet:
 <s> Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) , getKind ( ) ) ;"
LLVM,RISCV,3426,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , nullptr , nullptr ) ) return false ; Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) , getKind ( ) ) ;"
LLVM,RISCV,3427,"Predict the next statement of this code snippet:
 <s> switch ( getKind ( ) ) { default : return ;"
LLVM,RISCV,3428,"Predict the next statement of this code snippet:
 <s> case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; break ; } case MCExpr :: Unary : fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;"
LLVM,RISCV,3429,"Predict the next statement of this code snippet:
 <s> case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; break ; }"
LLVM,RISCV,3430,"Predict the next statement of this code snippet:
 <s> DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = <NUM_LIT> ; } for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != Offset ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DFOut ) * DFOut = DF ; return & F ; } } return nullptr ;"
LLVM,RISCV,3431,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GOT_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_HI : return <STR_LIT> ; case VK_<ISA_LIT>_CALL : return <STR_LIT> ; case VK_<ISA_LIT>_CALL_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_32_PCREL : return <STR_LIT> ;"
LLVM,RISCV,3432,"Predict the next statement of this code snippet:
 <s> if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ; if ( Kind == VK_<ISA_LIT>_CALL_PLT ) OS << <STR_LIT> ;"
LLVM,RISCV,3433,"Predict the next statement of this code snippet:
 <s> VariantKind Kind = getKind ( ) ; bool HasVariant = ( ( Kind != VK_<ISA_LIT>_None ) && ( Kind != VK_<ISA_LIT>_CALL ) && ( Kind != VK_<ISA_LIT>_CALL_PLT ) ) ; if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ;"
LLVM,RISCV,3434,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>MCExpr :: evaluateAsConstant ( int64_t & Res ) const { MCValue Value ; if ( Kind == VK_<ISA_LIT>_PCREL_HI || Kind == VK_<ISA_LIT>_PCREL_LO || Kind == VK_<ISA_LIT>_GOT_HI || Kind == VK_<ISA_LIT>_TPREL_HI || Kind == VK_<ISA_LIT>_TPREL_LO || Kind == VK_<ISA_LIT>_TPREL_ADD || Kind == VK_<ISA_LIT>_TLS_GOT_HI || Kind == VK_<ISA_LIT>_TLS_GD_HI || Kind == VK_<ISA_LIT>_CALL || Kind == VK_<ISA_LIT>_CALL_PLT || Kind == VK_<ISA_LIT>_CAPTAB_PCREL_HI || Kind == VK_<ISA_LIT>_TPREL_CINCOFFSET || Kind == VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI || Kind == VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI || Kind == VK_<ISA_LIT>_CCALL ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ;"
LLVM,RISCV,3435,"Predict the next statement of this code snippet:
 <s> case VK_<ISA_LIT>_TLS_GD_HI : case VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI : case VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI : break ; } fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ;"
LLVM,RISCV,3436,"Predict the next statement of this code snippet:
 <s> const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE ) return nullptr ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSymbol -> getFragment ( ) ) ; if ( ! DF ) return nullptr ; uint64_t Offset = AUIPCSymbol -> getOffset ( ) ; if ( DF -> getContents ( ) . size ( ) == Offset ) { DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = <NUM_LIT> ; }"
LLVM,RISCV,3437,"Predict the next statement of this code snippet:
 <s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GOT_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_CAPTAB_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_CINCOFFSET ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;"
LLVM,RISCV,3438,"Predict the next statement of this code snippet:
 <s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GOT_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_CAPTAB_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_CINCOFFSET ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;"
LLVM,RISCV,3439,"Predict the next statement of this code snippet:
 <s> case VK_<ISA_LIT>_TPREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_ADD : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GOT_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_HI : return <STR_LIT> ; case VK_<ISA_LIT>_CAPTAB_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_CINCOFFSET : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_CALL : return <STR_LIT> ; case VK_<ISA_LIT>_CALL_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_CCALL : return <STR_LIT> ; case VK_<ISA_LIT>_32_PCREL : return <STR_LIT> ; }"
LLVM,RISCV,3440,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { VariantKind Kind = getKind ( ) ; bool HasVariant = ( ( Kind != VK_<ISA_LIT>_None ) && ( Kind != VK_<ISA_LIT>_CALL ) && ( Kind != VK_<ISA_LIT>_CALL_PLT ) && ( Kind != VK_<ISA_LIT>_CCALL ) ) ; if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ; if ( Kind == VK_<ISA_LIT>_CALL_PLT ) OS << <STR_LIT> ;"
LLVM,RISCV,3441,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>MCExpr :: evaluateAsConstant ( int64_t & Res ) const { MCValue Value ; if ( Kind == VK_<ISA_LIT>_PCREL_HI || Kind == VK_<ISA_LIT>_PCREL_LO || Kind == VK_<ISA_LIT>_GOT_HI || Kind == VK_<ISA_LIT>_CALL ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ;"
LLVM,RISCV,3442,"Predict the next statement of this code snippet:
 <s> MCValue Value ; if ( Kind == VK_<ISA_LIT>_PCREL_HI || Kind == VK_<ISA_LIT>_PCREL_LO || Kind == VK_<ISA_LIT>_GOT_HI || Kind == VK_<ISA_LIT>_CALL ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ;"
LLVM,RISCV,3443,"Predict the next statement of this code snippet:
 <s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ;"
LLVM,RISCV,3444,"Predict the next statement of this code snippet:
 <s> const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != AUIPCSymbol -> getOffset ( ) ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : return & F ; }"
LLVM,RISCV,3445,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : return <STR_LIT> ; case VK_<ISA_LIT>_HI : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_LO : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_GOT_HI : return <STR_LIT> ; }"
LLVM,RISCV,3446,"Predict the next statement of this code snippet:
 <s> StringRef <ISA_LIT>MCExpr :: getVariantKindName ( VariantKind Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : return <STR_LIT> ; case VK_<ISA_LIT>_HI : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_LO : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_GOT_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_LO : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_ADD : return <STR_LIT> ;"
LLVM,RISCV,3447,"Predict the next statement of this code snippet:
 <s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_LO : case VK_<ISA_LIT>_HI : case VK_<ISA_LIT>_PCREL_LO :"
LLVM,RISCV,3448,"Predict the next statement of this code snippet:
 <s> if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_LO : case VK_<ISA_LIT>_HI : case VK_<ISA_LIT>_PCREL_LO : case VK_<ISA_LIT>_PCREL_HI : return false ; } }"
LLVM,RISCV,3449,"Predict the next statement of this code snippet:
 <s> <STR_LIT> getFixupKind ( ) const {"
LLVM,RISCV,3450,"Predict the next statement of this code snippet:
 <s> if ( DF -> getContents ( ) . size ( ) == Offset ) { DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = <NUM_LIT> ; } for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != Offset ) continue ; switch ( ( unsigned ) F . getKind ( ) ) {"
LLVM,RISCV,3451,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {"
LLVM,RISCV,3452,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {"
LLVM,RISCV,3453,"Predict the next statement of this code snippet:
 <s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ;"
LLVM,RISCV,3454,"Predict the next statement of this code snippet:
 <s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr ) ;"
LLVM,RISCV,3455,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr ) ;"
LLVM,RISCV,3456,"Predict the next statement of this code snippet:
 <s> default : return ; case VK_<ISA_LIT>_TPREL_HI20 : case VK_<ISA_LIT>_TPREL_LO12 : break ; }"
LLVM,RISCV,3457,"Predict the next statement of this code snippet:
 <s> static void fixELFSymbolsInTLSFixupsImpl ( const MCExpr * Expr , MCAssembler & Asm ) { switch ( Expr -> getKind ( ) ) { case MCExpr :: Target : llvm_unreachable ( <STR_LIT> ) ; break ; case MCExpr :: Constant : break ; case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; break ;"
LLVM,RISCV,3458,"Predict the next statement of this code snippet:
 <s> case VK_<ISA_LIT>_LO12 : return <STR_LIT> ; case VK_<ISA_LIT>_HI20 : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_LO12 : return <STR_LIT> ;"
LLVM,RISCV,3459,"Predict the next statement of this code snippet:
 <s> case VK_<ISA_LIT>_HI20 : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_LO12 : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_HI20 : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_LO12 : return <STR_LIT> ;"
LLVM,RISCV,3460,"Predict the next statement of this code snippet:
 <s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO12 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI20 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_LO12 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI20 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_LO12 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_HI20 ) . Default ( VK_<ISA_LIT>_None ) ;"
LLVM,RISCV,3461,"Predict the next statement of this code snippet:
 <s> bool closeParen = printVariantKind ( OS , Kind ) ; const MCExpr * Expr = getSubExpr ( ) ;"
LLVM,RISCV,3462,"Predict the next statement of this code snippet:
 <s> case VK_<ISA_LIT>_None : closeParen = false ; break ; case VK_<ISA_LIT>_LO12 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HI20 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PCREL_LO12 : OS << <STR_LIT> ; break ;"
LLVM,RISCV,3463,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( Kind == VK_<ISA_LIT>_PCREL_LO && evaluatePCRelLo ( Res , Layout , Fixup ) ) return true ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_LO : case VK_<ISA_LIT>_HI : case VK_<ISA_LIT>_PCREL_LO :"
LLVM,RISCV,3464,"Predict the next statement of this code snippet:
 <s> MCValue Target ; if ( ! TargetFixup -> getValue ( ) -> evaluateAsValue ( Target , * Layout ) ) return false ; if ( ! Target . getSymA ( ) || ! Target . getSymA ( ) -> getSymbol ( ) . isInSection ( ) ) return false ; if ( & Target . getSymA ( ) -> getSymbol ( ) . getSection ( ) != findAssociatedFragment ( ) -> getParent ( ) ) return false ; uint64_t AUIPCOffset = AUIPCSymbol -> getOffset ( ) ; Res = MCValue :: get ( Target . getSymA ( ) , nullptr , Target . getConstant ( ) + ( Fixup -> getOffset ( ) - AUIPCOffset ) ) ;"
LLVM,RISCV,3465,"Predict the next statement of this code snippet:
 <s> auto & RAB = static_cast < <ISA_LIT>AsmBackend & > ( Layout -> getAssembler ( ) . getBackend ( ) ) ; if ( RAB . willForceRelocations ( ) ) return false ; MCValue AUIPCLoc ; if ( ! getSubExpr ( ) -> evaluateAsValue ( AUIPCLoc , * Layout ) ) return false ; const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE || findAssociatedFragment ( ) != AUIPCSRE -> findAssociatedFragment ( ) ) return false ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; if ( ! AUIPCSymbol ) return false ; const MCFixup * TargetFixup = getPCRelHiFixup ( ) ; if ( ! TargetFixup ) return false ; if ( ( unsigned ) TargetFixup -> getKind ( ) != <STR_LIT> ) return false ; MCValue Target ; if ( ! TargetFixup -> getValue ( ) -> evaluateAsValue ( Target , * Layout ) ) return false ; if ( ! Target . getSymA ( ) || ! Target . getSymA ( ) -> getSymbol ( ) . isInSection ( ) ) return false ; if ( & Target . getSymA ( ) -> getSymbol ( ) . getSection ( ) != findAssociatedFragment ( ) -> getParent ( ) ) return false ; uint64_t AUIPCOffset = AUIPCSymbol -> getOffset ( ) ;"
LLVM,RISCV,3466,"Predict the next statement of this code snippet:
 <s> const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSymbol -> getFragment ( ) ) ; if ( ! DF ) return nullptr ; uint64_t Offset = AUIPCSymbol -> getOffset ( ) ; if ( DF -> getContents ( ) . size ( ) == Offset ) { DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ;"
LLVM,RISCV,3467,"Predict the next statement of this code snippet:
 <s> DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = <NUM_LIT> ; } for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != Offset ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ;"
LLVM,RISCV,3468,"Predict the next statement of this code snippet:
 <s> auto & RAB = static_cast < <ISA_LIT>AsmBackend & > ( Layout -> getAssembler ( ) . getBackend ( ) ) ; if ( RAB . willForceRelocations ( ) ) return false ; MCValue AUIPCLoc ; if ( ! getSubExpr ( ) -> evaluateAsValue ( AUIPCLoc , * Layout ) ) return false ; const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE || findAssociatedFragment ( ) != AUIPCSRE -> findAssociatedFragment ( ) ) return false ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; if ( ! AUIPCSymbol ) return false ;"
LLVM,RISCV,3469,"Predict the next statement of this code snippet:
 <s> MCValue Value ; if ( Kind == VK_<ISA_LIT>_PCREL_HI ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ;"
LLVM,RISCV,3470,"Predict the next statement of this code snippet:
 <s> if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ;"
LLVM,RISCV,3471,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const {"
LLVM,RISCV,3472,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { return getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ;"
LLVM,RISCV,3473,"Predict the next statement of this code snippet:
 <s> return getSubExpr ( ) -> findAssociatedFragment ( ) ;"
LLVM,RISCV,3474,"Predict the next statement of this code snippet:
 <s> return getSubExpr ( ) -> findAssociatedFragment ( ) ;"
LLVM,RISCV,3475,"Predict the next statement of this code snippet:
 <s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {"
LLVM,RISCV,3476,"Predict the next statement of this code snippet:
 <s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {"
LLVM,RISCV,3477,"Predict the next statement of this code snippet:
 <s> return Kind ;"
LLVM,RISCV,3478,"Predict the next statement of this code snippet:
 <s> VariantKind getKind ( ) const { return Kind ;"
LLVM,RISCV,3479,"Predict the next statement of this code snippet:
 <s> return Expr ;"
LLVM,RISCV,3480,"Predict the next statement of this code snippet:
 <s> return Expr ;"
LLVM,RISCV,3481,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind <ISA_LIT>MCExpr :: getVariantKindForName ( StringRef name ) { return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;"
LLVM,RISCV,3482,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind <ISA_LIT>MCExpr :: getVariantKindForName ( StringRef name ) {"
LLVM,RISCV,3483,"Predict the next statement of this code snippet:
 <s> StringRef <ISA_LIT>MCExpr :: getVariantKindName ( VariantKind Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : return <STR_LIT> ; case VK_<ISA_LIT>_HI : return <STR_LIT> ;"
LLVM,RISCV,3484,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>MCExpr ( const MCExpr * Expr , VariantKind Kind ) : Expr ( Expr ) , Kind ( Kind ) {"
LLVM,RISCV,3485,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>MCExpr ( const MCExpr * Expr , VariantKind Kind ) : Expr ( Expr ) , Kind ( Kind ) {"
LLVM,RISCV,3486,"Predict the next statement of this code snippet:
 <s> static MCSymbolRefExpr :: VariantKind getVariantKind ( unsigned Flags ) {"
LLVM,RISCV,3487,"Predict the next statement of this code snippet:
 <s> OutMI . setOpcode ( Opcode ) ; for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; MCOperand MCOp = lowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ; }"
LLVM,RISCV,3488,"Predict the next statement of this code snippet:
 <s> MCOperand <ISA_LIT>MCInstLower :: lowerOperand ( const MachineOperand & MO ) const { switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return MCOperand ( ) ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_MachineBasicBlock : return lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , <NUM_LIT> ) ; case MachineOperand :: MO_GlobalAddress : return lowerSymbolOperand ( MO , AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , MO . getOffset ( ) ) ; case MachineOperand :: MO_ExternalSymbol : { StringRef Name = MO . getSymbolName ( ) ; return lowerSymbolOperand ( MO , AsmPrinter . GetExternalSymbolSymbol ( Name ) , MO . getOffset ( ) ) ; } case MachineOperand :: MO_JumpTableIndex : return lowerSymbolOperand ( MO , AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) , <NUM_LIT> ) ; case MachineOperand :: MO_ConstantPoolIndex : return lowerSymbolOperand ( MO , AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) , MO . getOffset ( ) ) ; case MachineOperand :: MO_BlockAddress : { const BlockAddress * BA = MO . getBlockAddress ( ) ; return lowerSymbolOperand ( MO , AsmPrinter . GetBlockAddressSymbol ( BA ) , MO . getOffset ( ) ) ; }"
LLVM,RISCV,3489,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_ABS_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_TPREL_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_TPREL_LO ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , Kind , Ctx ) ;"
LLVM,RISCV,3490,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_ABS_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_ABS_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_TPREL_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_TPREL_LO ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , Kind , Ctx ) ; if ( Offset ) { const MCExpr * OffsetExpr = MCConstantExpr :: create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: createAdd ( Expr , OffsetExpr , Ctx ) ;"
LLVM,RISCV,3491,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & ctx , <ISA_LIT>AsmPrinter & asmprinter ) : Ctx ( ctx ) , AsmPrinter ( asmprinter ) {"
LLVM,RISCV,3492,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & ctx , <ISA_LIT>AsmPrinter & asmprinter ) : Ctx ( ctx ) , AsmPrinter ( asmprinter ) {"
LLVM,RISCV,3493,"Predict the next statement of this code snippet:
 <s> if ( lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP ) ) OutMI . addOperand ( MCOp ) ; } switch ( OutMI . getOpcode ( ) ) { case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : { const Function & F = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return false ; AP . emitNops ( Num ) ; return true ; } break ; } case <STR_LIT> : OutMI . setOpcode ( <STR_LIT> ) ;"
LLVM,RISCV,3494,"Predict the next statement of this code snippet:
 <s> break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbolPreferLocal ( * MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = lowerSymbolOperand ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = lowerSymbolOperand ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ;"
LLVM,RISCV,3495,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI ; break ;"
LLVM,RISCV,3496,"Predict the next statement of this code snippet:
 <s> switch ( MO . getType ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ;"
LLVM,RISCV,3497,"Predict the next statement of this code snippet:
 <s> const MachineBasicBlock * MBB = MI -> getParent ( ) ; assert ( MBB && <STR_LIT> ) ; const MachineFunction * MF = MBB -> getParent ( ) ; assert ( MF && <STR_LIT> ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; assert ( TRI && <STR_LIT> ) ; uint64_t TSFlags = MI -> getDesc ( ) . TSFlags ; int NumOps = MI -> getNumExplicitOperands ( ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { int OpNo = ( int ) MI -> getOperandNo ( & MO ) ; assert ( OpNo >= <NUM_LIT> && <STR_LIT> ) ; if ( ( TSFlags & <STR_LIT> ) && OpNo == ( NumOps - <NUM_LIT> ) ) continue ; if ( ( TSFlags & <STR_LIT> ) && OpNo == ( NumOps - <NUM_LIT> ) ) continue ; if ( ( TSFlags & <STR_LIT> ) && OpNo == <NUM_LIT> ) {"
LLVM,RISCV,3498,"Predict the next statement of this code snippet:
 <s> if ( lower<ISA_LIT>VMachineInstrToMCInst ( MI , OutMI ) ) return false ; OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP ) ) OutMI . addOperand ( MCOp ) ; } switch ( OutMI . getOpcode ( ) ) { case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : { const Function & F = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return false ;"
LLVM,RISCV,3499,"Predict the next statement of this code snippet:
 <s> switch ( OutMI . getOpcode ( ) ) { case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : { const Function & F = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return false ; AP . emitNops ( Num ) ; return true ; } break ; } case <STR_LIT> : OutMI . setOpcode ( <STR_LIT> ) ;"
LLVM,RISCV,3500,"Predict the next statement of this code snippet:
 <s> MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = lowerSymbolOperand ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = lowerSymbolOperand ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; break ;"
LLVM,RISCV,3501,"Predict the next statement of this code snippet:
 <s> case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ;"
LLVM,RISCV,3502,"Predict the next statement of this code snippet:
 <s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; } const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ;"
LLVM,RISCV,3503,"Predict the next statement of this code snippet:
 <s> static MCOperand lowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym , const AsmPrinter & AP ) { MCContext & Ctx = AP . OutContext ; <ISA_LIT>MCExpr :: VariantKind Kind ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> :"
LLVM,RISCV,3504,"Predict the next statement of this code snippet:
 <s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ; break ;"
LLVM,RISCV,3505,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; }"
LLVM,RISCV,3506,"Predict the next statement of this code snippet:
 <s> if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ME = <ISA_LIT>MCExpr :: create ( ME , Kind , Ctx ) ; return MCOperand :: createExpr ( ME ) ;"
LLVM,RISCV,3507,"Predict the next statement of this code snippet:
 <s> MCContext & Ctx = AP . OutContext ; <ISA_LIT>MCExpr :: VariantKind Kind ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ; break ; } const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;"
LLVM,RISCV,3508,"Predict the next statement of this code snippet:
 <s> Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ; break ; } const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ME = <ISA_LIT>MCExpr :: create ( ME , Kind , Ctx ) ; return MCOperand :: createExpr ( ME ) ;"
LLVM,RISCV,3509,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : return MCSymbolRefExpr :: VK_TPREL ; } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,3510,"Predict the next statement of this code snippet:
 <s> switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI20 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO12 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI20 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO12 ; break ;"
LLVM,RISCV,3511,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCExpr :: VariantKind TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI20 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO12 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI20 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO12 ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , Kind , Ctx ) ; if ( Offset ) { const MCExpr * OffsetExpr = MCConstantExpr :: create ( Offset , Ctx ) ;"
LLVM,RISCV,3512,"Predict the next statement of this code snippet:
 <s> for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP ) ) OutMI . addOperand ( MCOp ) ;"
LLVM,RISCV,3513,"Predict the next statement of this code snippet:
 <s> bool llvm :: Lower<ISA_LIT>MachineOperandToMCOperand ( const MachineOperand & MO , MCOperand & MCOp , const AsmPrinter & AP ) { switch ( MO . getType ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ;"
LLVM,RISCV,3514,"Predict the next statement of this code snippet:
 <s> OutMI . setOpcode ( RVV -> BaseInstr ) ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; assert ( MBB && <STR_LIT> ) ; const MachineFunction * MF = MBB -> getParent ( ) ; assert ( MF && <STR_LIT> ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; assert ( TRI && <STR_LIT> ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { int OpNo = ( int ) MI -> getOperandNo ( & MO ) ; assert ( OpNo >= <NUM_LIT> && <STR_LIT> ) ; if ( OpNo == RVV -> getVLIndex ( ) || OpNo == RVV -> getSEWIndex ( ) || OpNo == RVV -> getMergeOpIndex ( ) ) continue ; MCOperand MCOp ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) {"
LLVM,RISCV,3515,"Predict the next statement of this code snippet:
 <s> switch ( MO . getType ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ;"
LLVM,RISCV,3516,"Predict the next statement of this code snippet:
 <s> for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP ) ) OutMI . addOperand ( MCOp ) ; }"
LLVM,RISCV,3517,"Predict the next statement of this code snippet:
 <s> MCOperand MCOp ;"
LLVM,RISCV,3518,"Predict the next statement of this code snippet:
 <s> if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = lowerSymbolOperand ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ;"
LLVM,RISCV,3519,"Predict the next statement of this code snippet:
 <s> MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ;"
LLVM,RISCV,3520,"Predict the next statement of this code snippet:
 <s> const MCSubtargetInfo * STI = getContext ( ) . getSubtargetInfo ( ) ;"
LLVM,RISCV,3521,"Predict the next statement of this code snippet:
 <s> unsigned <STR_LIT> ( ) const {"
LLVM,RISCV,3522,"Predict the next statement of this code snippet:
 <s> assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLEReloc ( Kind ) ; case MCSymbolRefExpr :: VK_GOT : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PLT : assert ( IsPCRel && <STR_LIT> ) ; return getPLTReloc ( Kind ) ;"
LLVM,RISCV,3523,"Predict the next statement of this code snippet:
 <s> MCSymbolRefExpr :: VariantKind Modifier = ( Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ) ; unsigned Kind = Fixup . getKind ( ) ; switch ( Modifier ) { case MCSymbolRefExpr :: VK_None : if ( IsPCRel ) return getPCRelReloc ( Kind ) ; return getAbsoluteReloc ( Kind ) ; case MCSymbolRefExpr :: VK_NTPOFF : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLEReloc ( Kind ) ; case MCSymbolRefExpr :: VK_GOT : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PLT : assert ( IsPCRel && <STR_LIT> ) ; return getPLTReloc ( Kind ) ;"
LLVM,RISCV,3524,"Predict the next statement of this code snippet:
 <s> case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ;"
LLVM,RISCV,3525,"Predict the next statement of this code snippet:
 <s> static unsigned getAbsoluteReloc ( unsigned Kind ) {"
LLVM,RISCV,3526,"Predict the next statement of this code snippet:
 <s> static unsigned getPCRelReloc ( unsigned Kind ) { switch ( Kind ) { case FK_Data_4 : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ;"
LLVM,RISCV,3527,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; }"
LLVM,RISCV,3528,"Predict the next statement of this code snippet:
 <s> unsigned Kind = Fixup . getKind ( ) ; switch ( Modifier ) { case MCSymbolRefExpr :: VK_None : if ( IsPCRel ) return getPCRelReloc ( Kind ) ; return getAbsoluteReloc ( Kind ) ; case MCSymbolRefExpr :: VK_NTPOFF : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLEReloc ( Kind ) ; case MCSymbolRefExpr :: VK_GOT :"
LLVM,RISCV,3529,"Predict the next statement of this code snippet:
 <s> case FK_Data_4 : return ELF :: R_<ISA_LIT>_TLS_TPREL32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_TLS_TPREL64 ; }"
LLVM,RISCV,3530,"Predict the next statement of this code snippet:
 <s> case FK_Data_4 : return ELF :: R_<ISA_LIT>_TLS_TPREL32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_TLS_TPREL64 ; } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,3531,"Predict the next statement of this code snippet:
 <s> <STR_LIT> ( uint8_t OSABI ) : MCELFObjectTargetWriter ( true , OSABI , ELF :: EM_<ISA_LIT> , true ) {"
LLVM,RISCV,3532,"Predict the next statement of this code snippet:
 <s> <STR_LIT> ( uint8_t OSABI ) : MCELFObjectTargetWriter ( true , OSABI , ELF :: EM_<ISA_LIT> , true ) {"
LLVM,RISCV,3533,"Predict the next statement of this code snippet:
 <s> <STR_LIT> <ISA_LIT>ObjectWriter ( ) {"
LLVM,RISCV,3534,"Predict the next statement of this code snippet:
 <s> <STR_LIT> <ISA_LIT>ObjectWriter ( ) {"
LLVM,RISCV,3535,"Predict the next statement of this code snippet:
 <s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;"
LLVM,RISCV,3536,"Predict the next statement of this code snippet:
 <s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;"
LLVM,RISCV,3537,"Predict the next statement of this code snippet:
 <s> if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; else if ( CM == CodeModel :: JITDefault ) CM = RM == Reloc :: PIC_ ? CodeModel :: Small : CodeModel :: Medium ; X -> initMCCodeGenInfo ( RM , CM , OL ) ; return X ;"
LLVM,RISCV,3538,"Predict the next statement of this code snippet:
 <s> if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; else if ( CM == CodeModel :: JITDefault ) CM = RM == Reloc :: PIC_ ? CodeModel :: Small : CodeModel :: Medium ; X -> initMCCodeGenInfo ( RM , CM , OL ) ;"
LLVM,RISCV,3539,"Predict the next statement of this code snippet:
 <s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {"
LLVM,RISCV,3540,"Predict the next statement of this code snippet:
 <s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;"
LLVM,RISCV,3541,"Predict the next statement of this code snippet:
 <s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ;"
LLVM,RISCV,3542,"Predict the next statement of this code snippet:
 <s> return createELFStreamer ( Ctx , MAB , OS , Emitter , RelaxAll ) ;"
LLVM,RISCV,3543,"Predict the next statement of this code snippet:
 <s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {"
LLVM,RISCV,3544,"Predict the next statement of this code snippet:
 <s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {"
LLVM,RISCV,3545,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>64Target , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , create<ISA_LIT>MCObjectStreamer ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>64Target , create<ISA_LIT>MCObjectStreamer ) ;"
LLVM,RISCV,3546,"Predict the next statement of this code snippet:
 <s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {"
LLVM,RISCV,3547,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ;"
LLVM,RISCV,3548,"Predict the next statement of this code snippet:
 <s> for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ;"
LLVM,RISCV,3549,"Predict the next statement of this code snippet:
 <s> if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S , STI ) ;"
LLVM,RISCV,3550,"Predict the next statement of this code snippet:
 <s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { const Triple & TT = STI . getTargetTriple ( ) ;"
LLVM,RISCV,3551,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ;"
LLVM,RISCV,3552,"Predict the next statement of this code snippet:
 <s> MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;"
LLVM,RISCV,3553,"Predict the next statement of this code snippet:
 <s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) {"
LLVM,RISCV,3554,"Predict the next statement of this code snippet:
 <s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; return MAI ;"
LLVM,RISCV,3555,"Predict the next statement of this code snippet:
 <s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ;"
LLVM,RISCV,3556,"Predict the next statement of this code snippet:
 <s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ;"
LLVM,RISCV,3557,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ;"
LLVM,RISCV,3558,"Predict the next statement of this code snippet:
 <s> for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ;"
LLVM,RISCV,3559,"Predict the next statement of this code snippet:
 <s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,3560,"Predict the next statement of this code snippet:
 <s> std :: string CPUName = std :: string ( CPU ) ;"
LLVM,RISCV,3561,"Predict the next statement of this code snippet:
 <s> if ( CPU == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> ) + ( TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ;"
LLVM,RISCV,3562,"Predict the next statement of this code snippet:
 <s> if ( CPU . empty ( ) ) CPU = TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,3563,"Predict the next statement of this code snippet:
 <s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; Register SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;"
LLVM,RISCV,3564,"Predict the next statement of this code snippet:
 <s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; Register SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;"
LLVM,RISCV,3565,"Predict the next statement of this code snippet:
 <s> MCStreamer * create<ISA_LIT>ELFStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && MOW , std :: unique_ptr < MCCodeEmitter > && MCE , bool RelaxAll ) {"
LLVM,RISCV,3566,"Predict the next statement of this code snippet:
 <s> return create<ISA_LIT>ELFStreamer ( Context , std :: move ( MAB ) , std :: move ( MOW ) , std :: move ( MCE ) , RelaxAll ) ;"
LLVM,RISCV,3567,"Predict the next statement of this code snippet:
 <s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCRegister SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , SP , <NUM_LIT> ) ;"
LLVM,RISCV,3568,"Predict the next statement of this code snippet:
 <s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ;"
LLVM,RISCV,3569,"Predict the next statement of this code snippet:
 <s> MOFI -> initMCObjectFileInfo ( Ctx , PIC , LargeCodeModel ) ;"
LLVM,RISCV,3570,"Predict the next statement of this code snippet:
 <s> MCObjectFileInfo * MOFI = new <ISA_LIT>MCObjectFileInfo ( ) ; MOFI -> initMCObjectFileInfo ( Ctx , PIC , LargeCodeModel ) ;"
LLVM,RISCV,3571,"Predict the next statement of this code snippet:
 <s> if ( CPU . empty ( ) || CPU == <STR_LIT> ) CPU = TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,3572,"Predict the next statement of this code snippet:
 <s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {"
LLVM,RISCV,3573,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>TargetStreamer ( S ) ;"
LLVM,RISCV,3574,"Predict the next statement of this code snippet:
 <s> if ( Size == <NUM_LIT> ) Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; else Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; Target = Addr + Imm ; return true ; } if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { Target = Addr + Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; }"
LLVM,RISCV,3575,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCObjectFileInfo ( * T , create<ISA_LIT>MCObjectFileInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>ELFStreamer ) ;"
LLVM,RISCV,3576,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>ELFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ;"
LLVM,RISCV,3577,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {"
LLVM,RISCV,3578,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {"
LLVM,RISCV,3579,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ;"
LLVM,RISCV,3580,"Predict the next statement of this code snippet:
 <s> MCRegister SP = MRI . getDwarfRegNum ( SPReg , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;"
LLVM,RISCV,3581,"Predict the next statement of this code snippet:
 <s> if ( ABI != <STR_LIT> && <STR_LIT> ( ABI ) ) RAReg = <STR_LIT> ; else RAReg = <STR_LIT> ;"
LLVM,RISCV,3582,"Predict the next statement of this code snippet:
 <s> for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>ELFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ;"
LLVM,RISCV,3583,"Predict the next statement of this code snippet:
 <s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ;"
LLVM,RISCV,3584,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; }"
LLVM,RISCV,3585,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ;"
LLVM,RISCV,3586,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;"
LLVM,RISCV,3587,"Predict the next statement of this code snippet:
 <s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ;"
LLVM,RISCV,3588,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ;"
LLVM,RISCV,3589,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfoImpl ) ; }"
LLVM,RISCV,3590,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ;"
LLVM,RISCV,3591,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;"
LLVM,RISCV,3592,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;"
LLVM,RISCV,3593,"Predict the next statement of this code snippet:
 <s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { return new <ISA_LIT>MCAsmInfo ( TT ) ;"
LLVM,RISCV,3594,"Predict the next statement of this code snippet:
 <s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;"
LLVM,RISCV,3595,"Predict the next statement of this code snippet:
 <s> const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S , STI ) ; return nullptr ;"
LLVM,RISCV,3596,"Predict the next statement of this code snippet:
 <s> const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S , STI ) ; return nullptr ;"
LLVM,RISCV,3597,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ;"
LLVM,RISCV,3598,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; }"
LLVM,RISCV,3599,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; unsigned BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . RemoveOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ; ImmOp . setOffset ( Offset ) ; Tail . addOperand ( ImmOp ) ; Tail . getOperand ( <NUM_LIT> ) . setReg ( HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DeadInstrs . insert ( & LoADDI ) ; return true ;"
LLVM,RISCV,3600,"Predict the next statement of this code snippet:
 <s> MachineInstr & Tail = * MRI -> use_begin ( DestReg ) -> getParent ( ) ; switch ( Tail . getOpcode ( ) ) { default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; return false ; case <STR_LIT> : { int64_t Offset = Tail . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ; case <STR_LIT> : { int64_t Offset ; if ( ! matchLargeOffset ( Tail , DestReg , Offset ) ) return false ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3601,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>MergeBaseOffsetOpt :: detectLuiAddiGlobal ( MachineInstr & HiLUI , MachineInstr * & LoADDI ) { if ( HiLUI . getOpcode ( ) != <STR_LIT> || HiLUI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> || HiLUI . getOperand ( <NUM_LIT> ) . getType ( ) != MachineOperand :: MO_GlobalAddress || HiLUI . getOperand ( <NUM_LIT> ) . getOffset ( ) != <NUM_LIT> || ! MRI -> hasOneUse ( HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; unsigned HiLuiDestReg = HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LoADDI = MRI -> use_begin ( HiLuiDestReg ) -> getParent ( ) ;"
LLVM,RISCV,3602,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>MergeBaseOffsetOpt :: detectLuiAddiGlobal ( MachineInstr & HiLUI , MachineInstr * & LoADDI ) { if ( HiLUI . getOpcode ( ) != <STR_LIT> || HiLUI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> || HiLUI . getOperand ( <NUM_LIT> ) . getType ( ) != MachineOperand :: MO_GlobalAddress || HiLUI . getOperand ( <NUM_LIT> ) . getOffset ( ) != <NUM_LIT> || ! MRI -> hasOneUse ( HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ;"
LLVM,RISCV,3603,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; Register BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . RemoveOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,3604,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; Register BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . RemoveOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ; ImmOp . setOffset ( Offset ) ; Tail . addOperand ( ImmOp ) ; Tail . getOperand ( <NUM_LIT> ) . setReg ( HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DeadInstrs . insert ( & LoADDI ) ; return true ;"
LLVM,RISCV,3605,"Predict the next statement of this code snippet:
 <s> default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; return false ; case <STR_LIT> : { int64_t Offset = Tail . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ; case <STR_LIT> : { int64_t Offset ; if ( ! matchLargeOffset ( Tail , DestReg , Offset ) ) return false ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; Register BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . RemoveOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ; ImmOp . setOffset ( Offset ) ; Tail . addOperand ( ImmOp ) ; Tail . getOperand ( <NUM_LIT> ) . setReg ( HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DeadInstrs . insert ( & LoADDI ) ; return true ; } break ; } return false ;"
LLVM,RISCV,3606,"Predict the next statement of this code snippet:
 <s> MRI = & Fn . getRegInfo ( ) ; for ( MachineBasicBlock & MBB : Fn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; for ( MachineInstr & HiLUI : MBB ) {"
LLVM,RISCV,3607,"Predict the next statement of this code snippet:
 <s> MRI = & Fn . getRegInfo ( ) ; for ( MachineBasicBlock & MBB : Fn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; for ( MachineInstr & HiLUI : MBB ) { MachineInstr * LoADDI = nullptr ; if ( ! detectLuiAddiGlobal ( HiLUI , LoADDI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * LoADDI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) << <STR_LIT> ) ; detectAndFoldOffset ( HiLUI , * LoADDI ) ; } } for ( auto * MI : DeadInstrs ) MI -> eraseFromParent ( ) ; return true ;"
LLVM,RISCV,3608,"Predict the next statement of this code snippet:
 <s> DeadInstrs . insert ( & Tail ) ; MRI -> replaceRegWith ( Tail . getOperand ( <NUM_LIT> ) . getReg ( ) , LoADDI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;"
LLVM,RISCV,3609,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MergeBaseOffsetOpt :: foldOffset ( MachineInstr & HiLUI , MachineInstr & LoADDI , MachineInstr & Tail , int64_t Offset ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ;"
LLVM,RISCV,3610,"Predict the next statement of this code snippet:
 <s> Register Rt = TailAdd . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg = Rs == GAReg ? Rt : Rs ; if ( ! MRI -> hasOneUse ( Reg ) ) return false ; MachineInstr & OffsetTail = * MRI -> getVRegDef ( Reg ) ; if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { MachineOperand & AddiImmOp = OffsetTail . getOperand ( <NUM_LIT> ) ; if ( AddiImmOp . getTargetFlags ( ) != <STR_LIT> ) return false ; int64_t OffLo = AddiImmOp . getImm ( ) ; MachineInstr & OffsetLui = * MRI -> getVRegDef ( OffsetTail . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineOperand & LuiImmOp = OffsetLui . getOperand ( <NUM_LIT> ) ; if ( OffsetLui . getOpcode ( ) != <STR_LIT> || LuiImmOp . getTargetFlags ( ) != <STR_LIT> || ! MRI -> hasOneUse ( OffsetLui . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Offset = SignExtend64 < <NUM_LIT> > ( LuiImmOp . getImm ( ) << <NUM_LIT> ) ; Offset += OffLo ; if ( ! ST -> is64Bit ( ) ) Offset = SignExtend64 < <NUM_LIT> > ( Offset ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << OffsetTail << <STR_LIT> << OffsetLui ) ; DeadInstrs . insert ( & OffsetTail ) ; DeadInstrs . insert ( & OffsetLui ) ; return true ; } else if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << OffsetTail ) ; Offset = SignExtend64 < <NUM_LIT> > ( OffsetTail . getOperand ( <NUM_LIT> ) . getImm ( ) << <NUM_LIT> ) ; DeadInstrs . insert ( & OffsetTail ) ;"
LLVM,RISCV,3611,"Predict the next statement of this code snippet:
 <s> if ( ! MRI -> hasOneUse ( Reg ) ) return false ; MachineInstr & OffsetTail = * MRI -> getVRegDef ( Reg ) ; if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { MachineOperand & AddiImmOp = OffsetTail . getOperand ( <NUM_LIT> ) ; if ( AddiImmOp . getTargetFlags ( ) != <STR_LIT> ) return false ; int64_t OffLo = AddiImmOp . getImm ( ) ; MachineInstr & OffsetLui = * MRI -> getVRegDef ( OffsetTail . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineOperand & LuiImmOp = OffsetLui . getOperand ( <NUM_LIT> ) ; if ( OffsetLui . getOpcode ( ) != <STR_LIT> || LuiImmOp . getTargetFlags ( ) != <STR_LIT> || ! MRI -> hasOneUse ( OffsetLui . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Offset = SignExtend64 < <NUM_LIT> > ( LuiImmOp . getImm ( ) << <NUM_LIT> ) ; Offset += OffLo ; if ( ! ST -> is64Bit ( ) ) Offset = SignExtend64 < <NUM_LIT> > ( Offset ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << OffsetTail << <STR_LIT> << OffsetLui ) ; DeadInstrs . insert ( & OffsetTail ) ; DeadInstrs . insert ( & OffsetLui ) ; return true ; } else if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << OffsetTail ) ; Offset = SignExtend64 < <NUM_LIT> > ( OffsetTail . getOperand ( <NUM_LIT> ) . getImm ( ) << <NUM_LIT> ) ;"
LLVM,RISCV,3612,"Predict the next statement of this code snippet:
 <s> MRI = & Fn . getRegInfo ( ) ; for ( MachineBasicBlock & MBB : Fn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; for ( MachineInstr & HiLUI : MBB ) { MachineInstr * LoADDI = nullptr ;"
LLVM,RISCV,3613,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : { int64_t Offset = Tail . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ; case <STR_LIT> : { int64_t Offset ; if ( ! matchLargeOffset ( Tail , DestReg , Offset ) ) return false ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; Register BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . RemoveOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ; ImmOp . setOffset ( Offset ) ; Tail . addOperand ( ImmOp ) ;"
LLVM,RISCV,3614,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; Register BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . removeOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ; ImmOp . setOffset ( Offset ) ; Tail . addOperand ( ImmOp ) ; Tail . getOperand ( <NUM_LIT> ) . setReg ( HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DeadInstrs . insert ( & LoADDI ) ; return true ; } } return false ;"
LLVM,RISCV,3615,"Predict the next statement of this code snippet:
 <s> if ( LoADDI -> getOpcode ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getType ( ) != MachineOperand :: MO_GlobalAddress || LoADDI -> getOperand ( <NUM_LIT> ) . getOffset ( ) != <NUM_LIT> || ! MRI -> hasOneUse ( LoADDI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; return true ;"
LLVM,RISCV,3616,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>MergeBaseOffsetOpt ( ) ;"
LLVM,RISCV,3617,"Predict the next statement of this code snippet:
 <s> MachineInstr & Tail = * MRI -> use_begin ( DestReg ) -> getParent ( ) ; switch ( Tail . getOpcode ( ) ) { default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; return false ; case <STR_LIT> : { int64_t Offset = Tail . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } case <STR_LIT> : { int64_t Offset ; if ( ! matchLargeOffset ( Tail , DestReg , Offset ) ) return false ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3618,"Predict the next statement of this code snippet:
 <s> return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; Register BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . removeOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,3619,"Predict the next statement of this code snippet:
 <s> Register HiLuiDestReg = HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LoADDI = MRI -> use_begin ( HiLuiDestReg ) -> getParent ( ) ; if ( LoADDI -> getOpcode ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getType ( ) != MachineOperand :: MO_GlobalAddress || LoADDI -> getOperand ( <NUM_LIT> ) . getOffset ( ) != <NUM_LIT> || ! MRI -> hasOneUse ( LoADDI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ;"
LLVM,RISCV,3620,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MergeBaseOffsetOpt :: foldOffset ( MachineInstr & HiLUI , MachineInstr & LoADDI , MachineInstr & Tail , int64_t Offset ) { HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; LoADDI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; DeadInstrs . insert ( & Tail ) ;"
LLVM,RISCV,3621,"Predict the next statement of this code snippet:
 <s> DeadInstrs . insert ( & Tail ) ;"
LLVM,RISCV,3622,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override {"
LLVM,RISCV,3623,"Predict the next statement of this code snippet:
 <s> Register Rs = TailAdd . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Rt = TailAdd . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg = Rs == GAReg ? Rt : Rs ; if ( ! MRI -> hasOneUse ( Reg ) ) return false ; MachineInstr & OffsetTail = * MRI -> getVRegDef ( Reg ) ; if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { MachineOperand & AddiImmOp = OffsetTail . getOperand ( <NUM_LIT> ) ; if ( AddiImmOp . getTargetFlags ( ) != <STR_LIT> ) return false ; int64_t OffLo = AddiImmOp . getImm ( ) ;"
LLVM,RISCV,3624,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MergeBaseOffsetOpt ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,3625,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MergeBaseOffsetOpt ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,3626,"Predict the next statement of this code snippet:
 <s> DeadInstrs . clear ( ) ; MRI = & Fn . getRegInfo ( ) ; for ( MachineBasicBlock & MBB : Fn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; for ( MachineInstr & HiLUI : MBB ) { MachineInstr * LoADDI = nullptr ; if ( ! detectLuiAddiGlobal ( HiLUI , LoADDI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * LoADDI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) << <STR_LIT> ) ; MadeChange |= detectAndFoldOffset ( HiLUI , * LoADDI ) ;"
LLVM,RISCV,3627,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; for ( MachineInstr & HiLUI : MBB ) { MachineInstr * LoADDI = nullptr ; if ( ! detectLuiAddiGlobal ( HiLUI , LoADDI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * LoADDI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) << <STR_LIT> ) ; MadeChange |= detectAndFoldOffset ( HiLUI , * LoADDI ) ; }"
LLVM,RISCV,3628,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <ISA_LIT>_OPTIMIZE_VSETVL_USES_NAME ;"
LLVM,RISCV,3629,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override {"
LLVM,RISCV,3630,"Predict the next statement of this code snippet:
 <s> bool isSameRegisterClass ( unsigned Reg1 , unsigned Reg2 ) { return <STR_LIT> . contains ( Reg1 , Reg2 ) || <STR_LIT> . contains ( Reg1 , Reg2 ) ;"
LLVM,RISCV,3631,"Predict the next statement of this code snippet:
 <s> bool isSameRegisterClass ( unsigned Reg1 , unsigned Reg2 ) { return <STR_LIT> . contains ( Reg1 , Reg2 ) || <STR_LIT> . contains ( Reg1 , Reg2 ) ;"
LLVM,RISCV,3632,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>OptimizeVSETVLUses ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,3633,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>OptimizeVSETVLUses ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,3634,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Fn . getFunction ( ) . getName ( ) << <STR_LIT> ) ; for ( MachineBasicBlock & MBB : Fn ) { for ( MachineInstr & Instr : MBB ) { if ( Instr . isCopy ( ) ) { const auto & CopyDest = Instr . getOperand ( <NUM_LIT> ) ; auto & CopySource = Instr . getOperand ( <NUM_LIT> ) ; const MachineInstr * MI = MRI . getVRegDef ( CopySource . getReg ( ) ) ; if ( ! MI ) { continue ; }"
LLVM,RISCV,3635,"Predict the next statement of this code snippet:
 <s> } if ( MI -> getOpcode ( ) == <STR_LIT> && ! isSameRegisterClass ( CopyDest . getReg ( ) , CopySource . getReg ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << <STR_LIT> ) ; LLVM_DEBUG ( Instr . dump ( ) ) ; const auto & VSETVLDefGPR = MI -> getOperand ( <NUM_LIT> ) ; const auto & VSETVLDefVLR = MI -> getOperand ( <NUM_LIT> ) ; const auto & Replacement = VSETVLDefGPR . getReg ( ) != CopySource . getReg ( ) ? VSETVLDefGPR : VSETVLDefVLR ; CopySource . setIsKill ( false ) ; CopySource . setReg ( Replacement . getReg ( ) ) ; MRI . clearKillFlags ( Replacement . getReg ( ) ) ; } } } } return true ;"
LLVM,RISCV,3636,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>PulpHWLoopsPass ( ) {"
LLVM,RISCV,3637,"Predict the next statement of this code snippet:
 <s> assert ( ! OuterLoopSetup && <STR_LIT> ) ; if ( LoopSetup ) { OuterLoopSetup = LoopSetup ; } LoopSetup = & MI ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { assert ( LoopSetup && <STR_LIT> ) ; Setups . push_back ( LoopSetup ) ; Branches . push_back ( & MI ) ;"
LLVM,RISCV,3638,"Predict the next statement of this code snippet:
 <s> AU . addRequired < MachineDominatorTree > ( ) ;"
LLVM,RISCV,3639,"Predict the next statement of this code snippet:
 <s> AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;"
LLVM,RISCV,3640,"Predict the next statement of this code snippet:
 <s> return PULP_HWLOOPS_NAME ;"
LLVM,RISCV,3641,"Predict the next statement of this code snippet:
 <s> LastInstr -> setPreInstrSymbol ( MF , LastInstrSymbol ) ; } int Offset = <NUM_LIT> , SetupOffset = <NUM_LIT> , FirstInstrOffset = <NUM_LIT> , LastInstrOffset = <NUM_LIT> ; for ( auto & BB : MF ) { for ( auto & MI : BB ) { if ( & MI == Setup ) { SetupOffset = Offset ; } else if ( & MI == FirstInstr ) { FirstInstrOffset = Offset ; } else if ( & MI == LastInstr ) { LastInstrOffset = Offset ; } Offset += TII -> getInstSizeInBytes ( MI ) ; } } assert ( isUInt < <NUM_LIT> > ( FirstInstrOffset - SetupOffset ) && isUInt < <NUM_LIT> > ( LastInstrOffset - SetupOffset ) && <STR_LIT> ) ; MachineBasicBlock * Preheader = Setup -> getParent ( ) ; if ( Setup -> getOpcode ( ) == <STR_LIT> ) { Register count = Setup -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( FirstInstrOffset - SetupOffset == <NUM_LIT> ) { BuildMI ( * Preheader , Setup , Setup -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addReg ( count ) . addSym ( LastInstrSymbol ) ; } else { BuildMI ( * Preheader , Setup , Setup -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addReg ( count ) ; BuildMI ( * Preheader , Setup , Setup -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addMBB ( LoopHeader ) ; BuildMI ( * Preheader , Setup , Setup -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addSym ( LastInstrSymbol ) ; } } else { int64_t count = Setup -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( FirstInstrOffset - SetupOffset == <NUM_LIT> && LastInstrOffset - SetupOffset < <NUM_LIT> ) { BuildMI ( * Preheader , Setup , Setup -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addImm ( count ) . addSym ( LastInstrSymbol ) ; } else { BuildMI ( * Preheader , Setup , Setup -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addImm ( count ) ; BuildMI ( * Preheader , Setup , Setup -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addMBB ( LoopHeader ) ; BuildMI ( * Preheader , Setup , Setup -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addSym ( LastInstrSymbol ) ; }"
LLVM,RISCV,3642,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PulpHWLoops ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,3643,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PulpHWLoops ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,3644,"Predict the next statement of this code snippet:
 <s> TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; FindInstrPairs ( MDT -> getRootNode ( ) , nullptr , nullptr ) ; assert ( Setups . size ( ) == Branches . size ( ) && Setups . size ( ) == LoopNums . size ( ) ) ; if ( Setups . empty ( ) ) return false ; while ( ! Setups . empty ( ) ) { ProcessHardwareLoop ( Setups . pop_back_val ( ) , Branches . pop_back_val ( ) , LoopNums . pop_back_val ( ) , MF ) ;"
LLVM,RISCV,3645,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>RedundantCopyEliminationPass ( ) {"
LLVM,RISCV,3646,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>RedundantCopyElimination ( ) ;"
LLVM,RISCV,3647,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <STR_LIT> ;"
LLVM,RISCV,3648,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,RISCV,3649,"Predict the next statement of this code snippet:
 <s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;"
LLVM,RISCV,3650,"Predict the next statement of this code snippet:
 <s> if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && & MBB != MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; return false ;"
LLVM,RISCV,3651,"Predict the next statement of this code snippet:
 <s> if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && & MBB == MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && & MBB != MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; return false ;"
LLVM,RISCV,3652,"Predict the next statement of this code snippet:
 <s> Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SrcReg == <STR_LIT> && ! MRI -> isReserved ( DefReg ) && TargetReg == DefReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> print ( dbgs ( ) ) ) ; MI -> eraseFromParent ( ) ; Changed = true ; LastChange = I ; ++ NumCopiesRemoved ; continue ; } } if ( MI -> modifiesRegister ( TargetReg , TRI ) ) break ; } if ( ! Changed ) return false ; CondBr -> clearRegisterKills ( TargetReg , TRI ) ; if ( ! MBB . isLiveIn ( TargetReg ) ) MBB . addLiveIn ( TargetReg ) ; for ( MachineInstr & MMI : make_range ( MBB . begin ( ) , LastChange ) ) MMI . clearRegisterKills ( TargetReg , TRI ) ; return true ;"
LLVM,RISCV,3653,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RedundantCopyElimination ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,3654,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( MBB ) ;"
LLVM,RISCV,3655,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterBankInfo :: <ISA_LIT>RegisterBankInfo ( const TargetRegisterInfo & TRI ) : <ISA_LIT>GenRegisterBankInfo ( ) {"
LLVM,RISCV,3656,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterBankInfo :: <ISA_LIT>RegisterBankInfo ( const TargetRegisterInfo & TRI ) : <ISA_LIT>GenRegisterBankInfo ( ) {"
LLVM,RISCV,3657,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterBankInfo :: <ISA_LIT>RegisterBankInfo ( const TargetRegisterInfo & TRI ) {"
LLVM,RISCV,3658,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterBankInfo :: <ISA_LIT>RegisterBankInfo ( const TargetRegisterInfo & TRI ) {"
LLVM,RISCV,3659,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = <NUM_LIT> ) const override {"
LLVM,RISCV,3660,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = <NUM_LIT> ) const override {"
LLVM,RISCV,3661,"Predict the next statement of this code snippet:
 <s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override {"
LLVM,RISCV,3662,"Predict the next statement of this code snippet:
 <s> int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ;"
LLVM,RISCV,3663,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_SaveList ; return CSR_Interrupt_SaveList ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32F_LP64F_SaveList ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3664,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_SaveList ; return CSR_Interrupt_SaveList ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ;"
LLVM,RISCV,3665,"Predict the next statement of this code snippet:
 <s> return CSR_Interrupt_RegMask ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32F_LP64F_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32D_LP64D_RegMask ;"
LLVM,RISCV,3666,"Predict the next statement of this code snippet:
 <s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_RegMask ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_RegMask ; return CSR_Interrupt_RegMask ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,3667,"Predict the next statement of this code snippet:
 <s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;"
LLVM,RISCV,3668,"Predict the next statement of this code snippet:
 <s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;"
LLVM,RISCV,3669,"Predict the next statement of this code snippet:
 <s> unsigned FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm32 ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill = true ;"
LLVM,RISCV,3670,"Predict the next statement of this code snippet:
 <s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ; if ( ! IsRVVSpill ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset . getFixed ( ) ) ; else { if ( Offset . getFixed ( ) ) { Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addImm ( Offset . getFixed ( ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } } } else { assert ( ScalableFactorRegister && <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> && ! Offset . getFixed ( ) ) { BuildMI ( MBB , II , DL , TII -> get ( ScalableAdjOpc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addReg ( ScalableFactorRegister , RegState :: Kill ) ; MI . eraseFromParent ( ) ; return ; } Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( ScalableAdjOpc ) , VL ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addReg ( ScalableFactorRegister , RegState :: Kill ) ; if ( IsRVVSpill && Offset . getFixed ( ) ) { BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL ) . addImm ( Offset . getFixed ( ) ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VL , false , false , true ) ; if ( ! IsRVVSpill ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset . getFixed ( ) ) ; } auto ZvlssegInfo = TII -> isRVVSpillForZvlsseg ( MI . getOpcode ( ) ) ; if ( ZvlssegInfo ) {"
LLVM,RISCV,3671,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & ) const { if ( RC == & <STR_LIT> ) return & <STR_LIT> ; return RC ;"
LLVM,RISCV,3672,"Predict the next statement of this code snippet:
 <s> if ( RC == & <STR_LIT> ) return & <STR_LIT> ; return RC ;"
LLVM,RISCV,3673,"Predict the next statement of this code snippet:
 <s> DIExpression :: appendOffset ( Ops , Offset . getFixed ( ) ) ; unsigned VLENB = getDwarfRegNum ( <STR_LIT> , true ) ; int64_t VLENBSized = Offset . getScalable ( ) / <NUM_LIT> ; if ( VLENBSized > <NUM_LIT> ) { Ops . push_back ( dwarf :: DW_OP_constu ) ; Ops . push_back ( VLENBSized ) ; Ops . append ( { dwarf :: DW_OP_bregx , VLENB , <NUM_LIT> } ) ; Ops . push_back ( dwarf :: DW_OP_mul ) ; Ops . push_back ( dwarf :: DW_OP_plus ) ; } else if ( VLENBSized < <NUM_LIT> ) { Ops . push_back ( dwarf :: DW_OP_constu ) ; Ops . push_back ( - VLENBSized ) ; Ops . append ( { dwarf :: DW_OP_bregx , VLENB , <NUM_LIT> } ) ; Ops . push_back ( dwarf :: DW_OP_mul ) ; Ops . push_back ( dwarf :: DW_OP_minus ) ; }"
LLVM,RISCV,3674,"Predict the next statement of this code snippet:
 <s> unsigned VLENB = getDwarfRegNum ( <STR_LIT> , true ) ; int64_t VLENBSized = Offset . getScalable ( ) / <NUM_LIT> ; if ( VLENBSized > <NUM_LIT> ) { Ops . push_back ( dwarf :: DW_OP_constu ) ; Ops . push_back ( VLENBSized ) ; Ops . append ( { dwarf :: DW_OP_bregx , VLENB , <NUM_LIT> } ) ; Ops . push_back ( dwarf :: DW_OP_mul ) ; Ops . push_back ( dwarf :: DW_OP_plus ) ; } else if ( VLENBSized < <NUM_LIT> ) { Ops . push_back ( dwarf :: DW_OP_constu ) ; Ops . push_back ( - VLENBSized ) ; Ops . append ( { dwarf :: DW_OP_bregx , VLENB , <NUM_LIT> } ) ; Ops . push_back ( dwarf :: DW_OP_mul ) ; Ops . push_back ( dwarf :: DW_OP_minus ) ; }"
LLVM,RISCV,3675,"Predict the next statement of this code snippet:
 <s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtC ( ) ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,3676,"Predict the next statement of this code snippet:
 <s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtC ( ) ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,3677,"Predict the next statement of this code snippet:
 <s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ;"
LLVM,RISCV,3678,"Predict the next statement of this code snippet:
 <s> } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ;"
LLVM,RISCV,3679,"Predict the next statement of this code snippet:
 <s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return false ; const auto * FII = llvm :: find_if ( FixedCSRFIMap , [ & ] ( auto P ) { return P . first == Reg ; } ) ; if ( FII == std :: end ( FixedCSRFIMap ) ) return false ; FrameIdx = FII -> second ; return true ;"
LLVM,RISCV,3680,"Predict the next statement of this code snippet:
 <s> BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = <NUM_LIT> ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ;"
LLVM,RISCV,3681,"Predict the next statement of this code snippet:
 <s> return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isRegisterReservedByUser ( PhysReg ) ;"
LLVM,RISCV,3682,"Predict the next statement of this code snippet:
 <s> if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ;"
LLVM,RISCV,3683,"Predict the next statement of this code snippet:
 <s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;"
LLVM,RISCV,3684,"Predict the next statement of this code snippet:
 <s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( MFI . getStackID ( FrameIndex ) == TargetStackID :: <ISA_LIT>Vector ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { MachineOperand StackSlot = MI . getOperand ( FIOperandNum ) ; unsigned Opcode = getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * StoreAddr = BuildMI ( MBB , II , DL , TII -> get ( Opcode ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( StackSlot ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return eliminateFrameIndex ( StoreAddr , <NUM_LIT> , <NUM_LIT> , RS ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand StackSlot = MI . getOperand ( FIOperandNum ) ; unsigned Opcode = getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Register addr = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * StoreAddr = BuildMI ( MBB , II , DL , TII -> get ( Opcode ) , addr ) . add ( StackSlot ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( addr , false , false , false ) ; return eliminateFrameIndex ( StoreAddr , <NUM_LIT> , <NUM_LIT> , RS ) ; } default :"
LLVM,RISCV,3685,"Predict the next statement of this code snippet:
 <s> switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32F_LP64F_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32D_LP64D_RegMask ;"
LLVM,RISCV,3686,"Predict the next statement of this code snippet:
 <s> BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = <NUM_LIT> ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ;"
LLVM,RISCV,3687,"Predict the next statement of this code snippet:
 <s> else { if ( Offset . getFixed ( ) ) { Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addImm ( Offset . getFixed ( ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } } } else { assert ( ! <STR_LIT> ( STI . getTargetABI ( ) ) && <STR_LIT> ) ; assert ( ScalableFactorRegister && <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> && ! Offset . getFixed ( ) ) { BuildMI ( MBB , II , DL , TII -> get ( ScalableAdjOpc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addReg ( ScalableFactorRegister , RegState :: Kill ) ; MI . eraseFromParent ( ) ; return ; } Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( ScalableAdjOpc ) , VL ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addReg ( ScalableFactorRegister , RegState :: Kill ) ; if ( IsRVVSpill && Offset . getFixed ( ) ) { BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL ) . addImm ( Offset . getFixed ( ) ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VL , false , false , true ) ; if ( ! IsRVVSpill ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset . getFixed ( ) ) ; } auto ZvlssegInfo = TII -> isRVVSpillForZvlsseg ( MI . getOpcode ( ) ) ; if ( ZvlssegInfo ) { Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) ; uint32_t ShiftAmount = Log2_32 ( ZvlssegInfo -> second ) ; if ( ShiftAmount != <NUM_LIT> ) BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL ) . addImm ( ShiftAmount ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( VL , false ) ; }"
LLVM,RISCV,3688,"Predict the next statement of this code snippet:
 <s> } if ( ! isInt < <NUM_LIT> > ( Offset . getFixed ( ) ) ) { unsigned Opc ; unsigned ImmOpc ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( <STR_LIT> ( STI . getTargetABI ( ) ) ) { Opc = <STR_LIT> ; ImmOpc = <STR_LIT> ; } else { Opc = <STR_LIT> ; ImmOpc = <STR_LIT> ; } TII -> movImm ( MBB , II , DL , ScratchReg , Offset . getFixed ( ) ) ; if ( MI . getOpcode ( ) == ImmOpc && ! Offset . getScalable ( ) ) { BuildMI ( MBB , II , DL , TII -> get ( Opc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; MI . eraseFromParent ( ) ; return ; } Register DestReg = ScratchReg ; if ( <STR_LIT> ( STI . getTargetABI ( ) ) ) { DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; } BuildMI ( MBB , II , DL , TII -> get ( Opc ) , DestReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = StackOffset :: get ( <NUM_LIT> , Offset . getScalable ( ) ) ; FrameReg = DestReg ; FrameRegIsKill = true ; } if ( ! Offset . getScalable ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ; if ( ! IsRVVSpill ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset . getFixed ( ) ) ; else { if ( Offset . getFixed ( ) ) {"
LLVM,RISCV,3689,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . hasStdExtD ( ) ) return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_F64_Interrupt_SaveList : CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_F32_Interrupt_SaveList : CSR_XLEN_F32_Interrupt_SaveList ; return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_Interrupt_SaveList : CSR_Interrupt_SaveList ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3690,"Predict the next statement of this code snippet:
 <s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_IL32PC64_L64PC128_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32F_LP64F_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_IL32PC64F_L64PC128F_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32D_LP64D_RegMask ; case <STR_LIT> :"
LLVM,RISCV,3691,"Predict the next statement of this code snippet:
 <s> return TFI -> hasFP ( MF ) ? TFI -> getFPReg ( ) : TFI -> getSPReg ( ) ;"
LLVM,RISCV,3692,"Predict the next statement of this code snippet:
 <s> BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = <NUM_LIT> ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( STI . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ;"
LLVM,RISCV,3693,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ( STI . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , STI . getHwMode ( ) ) {"
LLVM,RISCV,3694,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ( STI . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , STI . getHwMode ( ) ) {"
LLVM,RISCV,3695,"Predict the next statement of this code snippet:
 <s> if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII -> second ;"
LLVM,RISCV,3696,"Predict the next statement of this code snippet:
 <s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;"
LLVM,RISCV,3697,"Predict the next statement of this code snippet:
 <s> if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ;"
LLVM,RISCV,3698,"Predict the next statement of this code snippet:
 <s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ;"
LLVM,RISCV,3699,"Predict the next statement of this code snippet:
 <s> if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII -> second ; return true ;"
LLVM,RISCV,3700,"Predict the next statement of this code snippet:
 <s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII -> second ; return true ;"
LLVM,RISCV,3701,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill = true ; }"
LLVM,RISCV,3702,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) . getFixed ( ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill = true ; }"
LLVM,RISCV,3703,"Predict the next statement of this code snippet:
 <s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,3704,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,3705,"Predict the next statement of this code snippet:
 <s> if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;"
LLVM,RISCV,3706,"Predict the next statement of this code snippet:
 <s> if ( ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ;"
LLVM,RISCV,3707,"Predict the next statement of this code snippet:
 <s> auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ;"
LLVM,RISCV,3708,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const {"
LLVM,RISCV,3709,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const {"
LLVM,RISCV,3710,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg == <STR_LIT> ;"
LLVM,RISCV,3711,"Predict the next statement of this code snippet:
 <s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; } else Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ;"
LLVM,RISCV,3712,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . hasStdExtV ( ) ) return CSR_XLEN_F32_VEC_Interrupt_SaveList ; return CSR_Interrupt_SaveList ; } if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtV ( ) ) return CSR_ILP32F_LP64F_VEC_SaveList ; switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32F_LP64F_SaveList ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32D_LP64D_SaveList ;"
LLVM,RISCV,3713,"Predict the next statement of this code snippet:
 <s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { auto & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_SaveList ; return CSR_Interrupt_SaveList ; if ( Subtarget . hasStdExtV ( ) ) return CSR_XLEN_F32_VEC_Interrupt_SaveList ; return CSR_Interrupt_SaveList ; } if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtV ( ) ) return CSR_ILP32F_LP64F_VEC_SaveList ; switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32F_LP64F_SaveList ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3714,"Predict the next statement of this code snippet:
 <s> } if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtV ( ) ) return CSR_ILP32F_LP64F_VEC_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) return CSR_ILP32F_LP64F_RegMask ; switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3715,"Predict the next statement of this code snippet:
 <s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;"
LLVM,RISCV,3716,"Predict the next statement of this code snippet:
 <s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; assert ( TFI -> hasFP ( MF ) && <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;"
LLVM,RISCV,3717,"Predict the next statement of this code snippet:
 <s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {"
LLVM,RISCV,3718,"Predict the next statement of this code snippet:
 <s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ;"
LLVM,RISCV,3719,"Predict the next statement of this code snippet:
 <s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = <NUM_LIT> ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;"
LLVM,RISCV,3720,"Predict the next statement of this code snippet:
 <s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { auto & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_SaveList ;"
LLVM,RISCV,3721,"Predict the next statement of this code snippet:
 <s> auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_RegMask ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_RegMask ; return CSR_Interrupt_RegMask ;"
LLVM,RISCV,3722,"Predict the next statement of this code snippet:
 <s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } bool EhDataRegFI = <ISA_LIT>FI -> isEhDataRegFI ( FrameIndex ) ; unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) || EhDataRegFI ) FrameReg = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; if ( MI . mayLoadOrStore ( ) ) Offset += MI . getOperand ( OpNo - <NUM_LIT> ) . getImm ( ) ; else Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADD = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned Reg ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; TII . loadImmediate ( MBB , II , & Reg , Offset ) ; BuildMI ( MBB , II , DL , TII . get ( ADD ) , Reg ) . addReg ( FrameReg ) . addReg ( Reg , RegState :: Kill ) ; FrameReg = Reg ; Offset = SignExtend64 < <NUM_LIT> > ( <NUM_LIT> ) ; IsKill = true ;"
LLVM,RISCV,3723,"Predict the next statement of this code snippet:
 <s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } bool EhDataRegFI = <ISA_LIT>FI -> isEhDataRegFI ( FrameIndex ) ; unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) || EhDataRegFI ) FrameReg = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ;"
LLVM,RISCV,3724,"Predict the next statement of this code snippet:
 <s> DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;"
LLVM,RISCV,3725,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . isRV64 ( ) ) if ( Subtarget . hasD ( ) ) return CSR_RV64D_SaveList ; else if ( Subtarget . hasF ( ) ) return CSR_RV64F_SaveList ; else return CSR_RV64_SaveList ;"
LLVM,RISCV,3726,"Predict the next statement of this code snippet:
 <s> if ( Subtarget . isRV64 ( ) ) if ( Subtarget . hasD ( ) ) return CSR_RV64D_SaveList ;"
LLVM,RISCV,3727,"Predict the next statement of this code snippet:
 <s> else return CSR_RV64_RegMask ; else if ( Subtarget . hasD ( ) ) return CSR_RV32D_RegMask ; else if ( Subtarget . hasF ( ) ) return CSR_RV32F_RegMask ; else return CSR_RV32_RegMask ;"
LLVM,RISCV,3728,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? ( Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) : ( Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) ;"
LLVM,RISCV,3729,"Predict the next statement of this code snippet:
 <s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;"
LLVM,RISCV,3730,"Predict the next statement of this code snippet:
 <s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ;"
LLVM,RISCV,3731,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( STI ) {"
LLVM,RISCV,3732,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( STI ) {"
LLVM,RISCV,3733,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const {"
LLVM,RISCV,3734,"Predict the next statement of this code snippet:
 <s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;"
LLVM,RISCV,3735,"Predict the next statement of this code snippet:
 <s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;"
LLVM,RISCV,3736,"Predict the next statement of this code snippet:
 <s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ;"
LLVM,RISCV,3737,"Predict the next statement of this code snippet:
 <s> if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; unsigned ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm32 ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill = true ;"
LLVM,RISCV,3738,"Predict the next statement of this code snippet:
 <s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) {"
LLVM,RISCV,3739,"Predict the next statement of this code snippet:
 <s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_SaveList ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_SaveList ; return CSR_Interrupt_SaveList ;"
LLVM,RISCV,3740,"Predict the next statement of this code snippet:
 <s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_RegMask ;"
LLVM,RISCV,3741,"Predict the next statement of this code snippet:
 <s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_RegMask ; return CSR_Interrupt_RegMask ;"
LLVM,RISCV,3742,"Predict the next statement of this code snippet:
 <s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask ( ) const {"
LLVM,RISCV,3743,"Predict the next statement of this code snippet:
 <s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;"
LLVM,RISCV,3744,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( unsigned PhysReg ) const { return PhysReg == <STR_LIT> ;"
LLVM,RISCV,3745,"Predict the next statement of this code snippet:
 <s> return PhysReg == <STR_LIT> ;"
LLVM,RISCV,3746,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( unsigned HwMode ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , HwMode ) {"
LLVM,RISCV,3747,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( unsigned HwMode ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , HwMode ) {"
LLVM,RISCV,3748,"Predict the next statement of this code snippet:
 <s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ;"
LLVM,RISCV,3749,"Predict the next statement of this code snippet:
 <s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ;"
LLVM,RISCV,3750,"Predict the next statement of this code snippet:
 <s> begin != MBB -> pred_end ( ) ; begin ++ ) { MachineInstr * predIterate = lastVSETVLIOfMBB . count ( * begin ) == <NUM_LIT> ? tailVSETVLI [ * begin ] : lastVSETVLIOfMBB [ * begin ] ; if ( predBlockVSETVLI == nullptr ) { predBlockVSETVLI = predIterate ; continue ; } if ( predIterate == nullptr || ( predIterate != nullptr && ! isSameVsetvli ( * predBlockVSETVLI , * predIterate ) ) ) break ; } if ( predBlockVSETVLI != nullptr ) { if ( headVSETVLI [ MBB ] != nullptr ) { if ( isSameVsetvli ( * predBlockVSETVLI , * headVSETVLI [ MBB ] , true ) ) redundancyVSETVLI . push_back ( headVSETVLI [ MBB ] ) ; lastVSETVLIOfMBB [ MBB ] = tailVSETVLI [ MBB ] ; } else { lastVSETVLIOfMBB [ MBB ] = predBlockVSETVLI ; } } else { lastVSETVLIOfMBB [ MBB ] = tailVSETVLI [ MBB ] ; } }"
LLVM,RISCV,3751,"Predict the next statement of this code snippet:
 <s> for ( llvm :: MachineBasicBlock :: iterator instr : MBB ) { if ( isVsetvli ( * instr ) ) { if ( firstEffectiveVSETVLI == nullptr ) firstEffectiveVSETVLI = & ( * instr ) ;"
LLVM,RISCV,3752,"Predict the next statement of this code snippet:
 <s> for ( llvm :: MachineBasicBlock :: iterator instr : MBB ) { if ( isVsetvli ( * instr ) ) { if ( firstEffectiveVSETVLI == nullptr ) firstEffectiveVSETVLI = & ( * instr ) ; else if ( ( lastEffectiveVSETVLI == nullptr && ! isSameVsetvli ( * firstEffectiveVSETVLI , * instr , true ) ) || ( lastEffectiveVSETVLI && ! isSameVsetvli ( * instr , * lastEffectiveVSETVLI ) ) ) lastEffectiveVSETVLI = & ( * instr ) ; else redundancyVSETVLI . push_back ( & ( * instr ) ) ; } }"
LLVM,RISCV,3753,"Predict the next statement of this code snippet:
 <s> collectRedundancyVSETVLIInMF ( MachineFunction & MF ) {"
LLVM,RISCV,3754,"Predict the next statement of this code snippet:
 <s> collectRedundancyVSETVLIInMF ( MachineFunction & MF ) { for ( auto & MBB : MF ) {"
LLVM,RISCV,3755,"Predict the next statement of this code snippet:
 <s> FunctionPass * create<ISA_LIT>RemoveRedundancyVSETVLPass ( ) {"
LLVM,RISCV,3756,"Predict the next statement of this code snippet:
 <s> FunctionPass * create<ISA_LIT>RemoveRedundancyVSETVLPass ( ) { return new <ISA_LIT>RemoveRedundancyVSETVL ( ) ;"
LLVM,RISCV,3757,"Predict the next statement of this code snippet:
 <s> return <ISA_LIT>_VECTOR_REMOVE_REDUNDANCY_VSETVL ;"
LLVM,RISCV,3758,"Predict the next statement of this code snippet:
 <s> return <ISA_LIT>_VECTOR_REMOVE_REDUNDANCY_VSETVL ;"
LLVM,RISCV,3759,"Predict the next statement of this code snippet:
 <s> assert ( ( ( frontOperand . isReg ( ) && backOperand . isReg ( ) ) || ( frontOperand . isImm ( ) && backOperand . isImm ( ) ) ) && <STR_LIT> ) ; if ( order ) { if ( frontOperand . isReg ( ) && backOperand . isReg ( ) && backOperand . getReg ( ) != <STR_LIT> && frontOperand . getReg ( ) != backOperand . getReg ( ) ) return false ; } else { if ( frontOperand . isReg ( ) && backOperand . isReg ( ) && frontOperand . getReg ( ) != backOperand . getReg ( ) ) return false ; } if ( frontOperand . isImm ( ) && backOperand . isImm ( ) && ! ( frontOperand . getImm ( ) == backOperand . getImm ( ) ) ) return false ; }"
LLVM,RISCV,3760,"Predict the next statement of this code snippet:
 <s> static bool isVsetvli ( MachineInstr & instr ) {"
LLVM,RISCV,3761,"Predict the next statement of this code snippet:
 <s> static bool isVsetvli ( MachineInstr & instr ) { return instr . getOpcode ( ) == <STR_LIT> ;"
LLVM,RISCV,3762,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RemoveRedundancyVSETVL :: removeRedundancy ( ) { if ( ! redundancyVSETVLI . size ( ) ) return false ;"
LLVM,RISCV,3763,"Predict the next statement of this code snippet:
 <s> collectRedundancyVSETVLIInMF ( MF ) ;"
LLVM,RISCV,3764,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RemoveRedundancyVSETVL :: runOnMachineFunction ( MachineFunction & MF ) {"
LLVM,RISCV,3765,"Predict the next statement of this code snippet:
 <s> immediates [ pos ] = value ;"
LLVM,RISCV,3766,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>RI5CYIRPass ( ) {"
LLVM,RISCV,3767,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>RI5CYIRPass ( ) { return new <ISA_LIT>RI5CYIR ( ) ;"
LLVM,RISCV,3768,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,RISCV,3769,"Predict the next statement of this code snippet:
 <s> status = AFTER ; l_limit = i - <NUM_LIT> ; } } else { if ( status == BEFORE ) { status = IN ; r_limit = i ; } else if ( status == AFTER ) { status = INVALID ; return false ; } else { l_limit = i ; } } } if ( status == BEFORE ) { return false ;"
LLVM,RISCV,3770,"Predict the next statement of this code snippet:
 <s> } } else { return false ; } auto setcc_inner = Dest . getOperand ( select ) . getOperand ( <NUM_LIT> ) ; auto reg_xxx = & Dest . getOperand ( select ) . getOperand ( <NUM_LIT> ) ; const SDValue * reg_out ; int inner_pos_constant_low_cc ; if ( setcc_inner . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { inner_pos_constant_low_cc = <NUM_LIT> ; reg_out = & setcc_inner . getOperand ( <NUM_LIT> ) ; } else if ( setcc_outer . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { reg_out = & setcc_inner . getOperand ( <NUM_LIT> ) ; inner_pos_constant_low_cc = <NUM_LIT> ; } else { return false ; } MemSDNode * mem_in = cast < MemSDNode > ( * reg_in ) ; MemSDNode * mem_out = cast < MemSDNode > ( * reg_out ) ; MemSDNode * mem_xxx = cast < MemSDNode > ( * reg_xxx ) ; if ( * ( mem_in -> getMemOperand ( ) ) != * ( mem_out -> getMemOperand ( ) ) || * ( mem_in -> getMemOperand ( ) ) != * ( mem_xxx -> getMemOperand ( ) ) ) { return false ; } int32_t inner_low_constant_cc = setcc_inner . getConstantOperandVal ( inner_pos_constant_low_cc ) ; if ( setcc_inner . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < CondCodeSDNode > ( * setcc_inner . getOperand ( <NUM_LIT> ) . getNode ( ) ) . get ( ) == <STR_LIT> ) { if ( ! unsign && inner_low_constant_cc != - low_constant_cc ) { return false ; }"
LLVM,RISCV,3771,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Metadata ( <ISA_LIT>_metadata_type_t t ) : Metadata ( Metadata_ID , Uniqued ) , type ( t ) {"
LLVM,RISCV,3772,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Metadata ( <ISA_LIT>_metadata_type_t t ) : Metadata ( Metadata_ID , Uniqued ) , type ( t ) {"
LLVM,RISCV,3773,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RI5CYIR ( ) : FunctionPass ( ID ) {"
LLVM,RISCV,3774,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RI5CYIR :: runOnFunction ( Function & F ) {"
LLVM,RISCV,3775,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RI5CYIR :: runOnFunction ( Function & F ) { errs ( ) << <STR_LIT> << F . getName ( ) . str ( ) << <STR_LIT> ; this -> transformBitManipulation ( F ) ; return false ;"
LLVM,RISCV,3776,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>RI5CYIR :: transformBitManipulation ( Function & F ) { for ( auto & BB : F ) { for ( auto & I : BB ) { if ( I . getOpcode ( ) == Instruction :: And ) { Value * op1 = I . getOperand ( <NUM_LIT> ) ; Value * op2 = I . getOperand ( <NUM_LIT> ) ; unsigned size = op2 -> getType ( ) -> getPrimitiveSizeInBits ( ) ; unsigned int immediate = <NUM_LIT> ; if ( isa < ConstantInt > ( op1 ) && size >= <NUM_LIT> && size <= <NUM_LIT> ) { immediate = cast < ConstantInt > ( op1 ) -> getLimitedValue ( ~ ( uint32_t ) <NUM_LIT> ) ; } else if ( isa < ConstantInt > ( op2 ) && size >= <NUM_LIT> && size <= <NUM_LIT> ) { immediate = cast < ConstantInt > ( op2 ) -> getLimitedValue ( ~ ( uint32_t ) <NUM_LIT> ) ; } if ( immediate == <NUM_LIT> ) { errs ( ) << <STR_LIT> ; continue ; } unsigned int limit_l ; unsigned int limit_r ;"
LLVM,RISCV,3777,"Predict the next statement of this code snippet:
 <s> immediate = cast < ConstantInt > ( op1 ) -> getLimitedValue ( ~ ( uint32_t ) <NUM_LIT> ) ; } else if ( isa < ConstantInt > ( op2 ) && size >= <NUM_LIT> && size <= <NUM_LIT> ) { immediate = cast < ConstantInt > ( op2 ) -> getLimitedValue ( ~ ( uint32_t ) <NUM_LIT> ) ; } if ( immediate == <NUM_LIT> ) { errs ( ) << <STR_LIT> ; continue ; } unsigned int limit_l ; unsigned int limit_r ; } }"
LLVM,RISCV,3778,"Predict the next statement of this code snippet:
 <s> virtual ~ <ISA_LIT>RI5CYIR ( ) { if ( dag != NULL ) { delete dag ;"
LLVM,RISCV,3779,"Predict the next statement of this code snippet:
 <s> if ( dag != NULL ) { delete dag ;"
LLVM,RISCV,3780,"Predict the next statement of this code snippet:
 <s> SDValue callFunction ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , const char * fnName , SDValue Dst , SDValue Src , SDValue Size ) { auto & Ctx = * DAG . getContext ( ) ; auto & STI = get<ISA_LIT>Subtarget ( DAG ) ; TargetLowering :: ArgListTy Args ; auto pushArg = [ & ] ( SDValue & Op ) { TargetLowering :: ArgListEntry Entry ; Entry . Node = Op ; Entry . Ty = Op . getValueType ( ) . getTypeForEVT ( Ctx ) ;"
LLVM,RISCV,3781,"Predict the next statement of this code snippet:
 <s> return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , false , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , false ) ;"
LLVM,RISCV,3782,"Predict the next statement of this code snippet:
 <s> if ( ( DstAS == <NUM_LIT> ) && ( SrcAS == <NUM_LIT> ) ) return SDValue ( ) ; auto & STI = get<ISA_LIT>Subtarget ( DAG ) ; MVT CapType = STI . typeForCapabilities ( ) ; if ( DstAS == <NUM_LIT> ) Dst = DAG . getAddrSpaceCast ( dl , CapType , Dst , <NUM_LIT> , <NUM_LIT> ) ; if ( SrcAS == <NUM_LIT> ) Src = DAG . getAddrSpaceCast ( dl , CapType , Src , <NUM_LIT> , <NUM_LIT> ) ; const char * memFnName = isMemCpy ? ( <STR_LIT> ( STI . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> ) : ( <STR_LIT> ( STI . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> ) ; return callFunction ( DAG , dl , Chain , memFnName , Dst , Src , Size ) ;"
LLVM,RISCV,3783,"Predict the next statement of this code snippet:
 <s> if ( DstAS == <NUM_LIT> ) Dst = DAG . getAddrSpaceCast ( dl , CapType , Dst , <NUM_LIT> , <NUM_LIT> ) ; if ( SrcAS == <NUM_LIT> ) Src = DAG . getAddrSpaceCast ( dl , CapType , Src , <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,3784,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( SelectionDAG & DAG ) { return reinterpret_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ;"
LLVM,RISCV,3785,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( SelectionDAG & DAG ) {"
LLVM,RISCV,3786,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {"
LLVM,RISCV,3787,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {"
LLVM,RISCV,3788,"Predict the next statement of this code snippet:
 <s> static void addUses ( const MachineInstr & MI , SmallVectorImpl < const MachineInstr * > & Worklist , MachineRegisterInfo & MRI ) { for ( auto & UserOp : MRI . reg_operands ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) {"
LLVM,RISCV,3789,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,RISCV,3790,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,RISCV,3791,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ) return false ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { E = MI -> getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) return false ; Register SrcReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ;"
LLVM,RISCV,3792,"Predict the next statement of this code snippet:
 <s> Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { E = MI -> getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) return false ; Register SrcReg = MI -> getOperand ( I ) . getReg ( ) ;"
LLVM,RISCV,3793,"Predict the next statement of this code snippet:
 <s> const MachineInstr * MI = Worklist . pop_back_val ( ) ; if ( ! Visited . insert ( MI ) . second ) continue ; if ( isSignExtendingOpW ( * MI ) ) continue ; switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,3794,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> :"
LLVM,RISCV,3795,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ;"
LLVM,RISCV,3796,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>SExtWRemoval ( ) ;"
LLVM,RISCV,3797,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <STR_LIT> ;"
LLVM,RISCV,3798,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override {"
LLVM,RISCV,3799,"Predict the next statement of this code snippet:
 <s> if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ) return false ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { E = MI -> getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) return false ; Register SrcReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; } break ; } } }"
LLVM,RISCV,3800,"Predict the next statement of this code snippet:
 <s> break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ) return false ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { E = MI -> getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) return false ; Register SrcReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ;"
LLVM,RISCV,3801,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return ! isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ;"
LLVM,RISCV,3802,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>SExtWRemoval ( ) : MachineFunctionPass ( ID ) {"
LLVM,RISCV,3803,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>SExtWRemoval ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>SExtWRemovalPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,RISCV,3804,"Predict the next statement of this code snippet:
 <s> const MachineInstr & SrcMI = * MRI . getVRegDef ( SrcReg ) ; if ( ! isSignExtendedW ( SrcMI , MRI ) ) continue ; Register DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . constrainRegClass ( SrcReg , MRI . getRegClass ( DstReg ) ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MRI . replaceRegWith ( DstReg , SrcReg ) ; MRI . clearKillFlags ( SrcReg ) ; MI -> eraseFromParent ( ) ; ++ NumRemovedSExtW ; MadeChange = true ; }"
LLVM,RISCV,3805,"Predict the next statement of this code snippet:
 <s> static bool bindsLocally ( const GlobalValue * GV , Reloc :: Model RM ) {"
LLVM,RISCV,3806,"Predict the next statement of this code snippet:
 <s> return & FrameLowering ;"
LLVM,RISCV,3807,"Predict the next statement of this code snippet:
 <s> const TargetFrameLowering * getFrameLowering ( ) const {"
LLVM,RISCV,3808,"Predict the next statement of this code snippet:
 <s> return & InstrInfo ;"
LLVM,RISCV,3809,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const {"
LLVM,RISCV,3810,"Predict the next statement of this code snippet:
 <s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const {"
LLVM,RISCV,3811,"Predict the next statement of this code snippet:
 <s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) { CPUName = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FS ) ; return * this ;"
LLVM,RISCV,3812,"Predict the next statement of this code snippet:
 <s> if ( CPUName . empty ( ) ) { CPUName = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FS ) ;"
LLVM,RISCV,3813,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>Subtarget :: isPC32DBLSymbol ( const GlobalValue * GV , Reloc :: Model RM , CodeModel :: Model CM ) const { if ( GV -> getAlignment ( ) == <NUM_LIT> ) return false ; if ( CM == CodeModel :: Small ) return bindsLocally ( GV , RM ) ;"
LLVM,RISCV,3814,"Predict the next statement of this code snippet:
 <s> bool isTargetELF ( ) const { return TargetTriple . isOSBinFormatELF ( ) ;"
LLVM,RISCV,3815,"Predict the next statement of this code snippet:
 <s> return TargetTriple . isOSBinFormatELF ( ) ;"
LLVM,RISCV,3816,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( RV32 ) , HasM ( false ) , HasA ( false ) , HasX ( false ) , HasF ( false ) , HasD ( false ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {"
LLVM,RISCV,3817,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( RV32 ) , HasM ( false ) , HasA ( false ) , HasX ( false ) , HasF ( false ) , HasD ( false ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {"
LLVM,RISCV,3818,"Predict the next statement of this code snippet:
 <s> bool useSoftFloat ( ) const { return UseSoftFloat ;"
LLVM,RISCV,3819,"Predict the next statement of this code snippet:
 <s> return EnableLinkerRelax ;"
LLVM,RISCV,3820,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,RISCV,3821,"Predict the next statement of this code snippet:
 <s> return EnableRVCHintInstrs ;"
LLVM,RISCV,3822,"Predict the next statement of this code snippet:
 <s> return EnableRVCHintInstrs ;"
LLVM,RISCV,3823,"Predict the next statement of this code snippet:
 <s> return EnableSaveRestore ;"
LLVM,RISCV,3824,"Predict the next statement of this code snippet:
 <s> return EnableUnalignedScalarMem ;"
LLVM,RISCV,3825,"Predict the next statement of this code snippet:
 <s> bool enableUnalignedScalarMem ( ) const {"
LLVM,RISCV,3826,"Predict the next statement of this code snippet:
 <s> return hasVInstructionsI64 ( ) ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,3827,"Predict the next statement of this code snippet:
 <s> return & InstrInfo ;"
LLVM,RISCV,3828,"Predict the next statement of this code snippet:
 <s> return & InstrInfo ;"
LLVM,RISCV,3829,"Predict the next statement of this code snippet:
 <s> unsigned getMaxInterleaveFactor ( ) const {"
LLVM,RISCV,3830,"Predict the next statement of this code snippet:
 <s> unsigned getMaxVLen ( ) const { return <NUM_LIT> ;"
LLVM,RISCV,3831,"Predict the next statement of this code snippet:
 <s> unsigned getMaxVLen ( ) const {"
LLVM,RISCV,3832,"Predict the next statement of this code snippet:
 <s> unsigned getMinVLen ( ) const { return ZvlLen ;"
LLVM,RISCV,3833,"Predict the next statement of this code snippet:
 <s> return <ISA_LIT>ProcFamily ;"
LLVM,RISCV,3834,"Predict the next statement of this code snippet:
 <s> return <ISA_LIT>ProcFamily ;"
LLVM,RISCV,3835,"Predict the next statement of this code snippet:
 <s> unsigned getRealMaxVLen ( ) const { unsigned VLen = getMaxRVVVectorSizeInBits ( ) ;"
LLVM,RISCV,3836,"Predict the next statement of this code snippet:
 <s> return & TSInfo ;"
LLVM,RISCV,3837,"Predict the next statement of this code snippet:
 <s> return & TSInfo ;"
LLVM,RISCV,3838,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;"
LLVM,RISCV,3839,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;"
LLVM,RISCV,3840,"Predict the next statement of this code snippet:
 <s> unsigned getXLen ( ) const { return XLen ;"
LLVM,RISCV,3841,"Predict the next statement of this code snippet:
 <s> MVT getXLenVT ( ) const {"
LLVM,RISCV,3842,"Predict the next statement of this code snippet:
 <s> return XLenVT ;"
LLVM,RISCV,3843,"Predict the next statement of this code snippet:
 <s> bool hasStdExtA ( ) const { return HasStdExtA ;"
LLVM,RISCV,3844,"Predict the next statement of this code snippet:
 <s> return HasStdExtC ;"
LLVM,RISCV,3845,"Predict the next statement of this code snippet:
 <s> return HasStdExtC ;"
LLVM,RISCV,3846,"Predict the next statement of this code snippet:
 <s> bool hasStdExtF ( ) const {"
LLVM,RISCV,3847,"Predict the next statement of this code snippet:
 <s> bool hasStdExtF ( ) const {"
LLVM,RISCV,3848,"Predict the next statement of this code snippet:
 <s> bool hasStdExtM ( ) const {"
LLVM,RISCV,3849,"Predict the next statement of this code snippet:
 <s> return HasStdExtV ;"
LLVM,RISCV,3850,"Predict the next statement of this code snippet:
 <s> return HasStdExtZba ;"
LLVM,RISCV,3851,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZba ( ) const {"
LLVM,RISCV,3852,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZbb ( ) const { return HasStdExtZbb ;"
LLVM,RISCV,3853,"Predict the next statement of this code snippet:
 <s> return HasStdExtZbb ;"
LLVM,RISCV,3854,"Predict the next statement of this code snippet:
 <s> return HasStdExtZbc ;"
LLVM,RISCV,3855,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZbe ( ) const {"
LLVM,RISCV,3856,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZbf ( ) const {"
LLVM,RISCV,3857,"Predict the next statement of this code snippet:
 <s> return HasStdExtZbkb ;"
LLVM,RISCV,3858,"Predict the next statement of this code snippet:
 <s> return HasStdExtZbkc ;"
LLVM,RISCV,3859,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZbkx ( ) const { return HasStdExtZbkx ;"
LLVM,RISCV,3860,"Predict the next statement of this code snippet:
 <s> return HasStdExtZbkx ;"
LLVM,RISCV,3861,"Predict the next statement of this code snippet:
 <s> return HasStdExtZbm ;"
LLVM,RISCV,3862,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZbm ( ) const { return HasStdExtZbm ;"
LLVM,RISCV,3863,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZbp ( ) const {"
LLVM,RISCV,3864,"Predict the next statement of this code snippet:
 <s> return HasStdExtZbp ;"
LLVM,RISCV,3865,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZbr ( ) const { return HasStdExtZbr ;"
LLVM,RISCV,3866,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZbr ( ) const {"
LLVM,RISCV,3867,"Predict the next statement of this code snippet:
 <s> return HasStdExtZbt ;"
LLVM,RISCV,3868,"Predict the next statement of this code snippet:
 <s> return HasStdExtZdinx ;"
LLVM,RISCV,3869,"Predict the next statement of this code snippet:
 <s> return HasStdExtZfh ;"
LLVM,RISCV,3870,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZfh ( ) const { return HasStdExtZfh ;"
LLVM,RISCV,3871,"Predict the next statement of this code snippet:
 <s> return HasStdExtZfhmin ;"
LLVM,RISCV,3872,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZfhmin ( ) const { return HasStdExtZfhmin ;"
LLVM,RISCV,3873,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZfinx ( ) const {"
LLVM,RISCV,3874,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZhinx ( ) const {"
LLVM,RISCV,3875,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZhinx ( ) const { return HasStdExtZhinx ;"
LLVM,RISCV,3876,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZihintpause ( ) const {"
LLVM,RISCV,3877,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZknd ( ) const {"
LLVM,RISCV,3878,"Predict the next statement of this code snippet:
 <s> return HasStdExtZknd ;"
LLVM,RISCV,3879,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZkne ( ) const {"
LLVM,RISCV,3880,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZkr ( ) const {"
LLVM,RISCV,3881,"Predict the next statement of this code snippet:
 <s> return HasStdExtZksed ;"
LLVM,RISCV,3882,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZksed ( ) const {"
LLVM,RISCV,3883,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZksh ( ) const {"
LLVM,RISCV,3884,"Predict the next statement of this code snippet:
 <s> return HasStdExtZksh ;"
LLVM,RISCV,3885,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZvfh ( ) const { return HasStdExtZvfh ;"
LLVM,RISCV,3886,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZvfh ( ) const {"
LLVM,RISCV,3887,"Predict the next statement of this code snippet:
 <s> bool hasVInstructions ( ) const {"
LLVM,RISCV,3888,"Predict the next statement of this code snippet:
 <s> return HasStdExtZve32x ;"
LLVM,RISCV,3889,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsAnyF ( ) const {"
LLVM,RISCV,3890,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsF32 ( ) const { return HasStdExtZve32f && HasStdExtF ;"
LLVM,RISCV,3891,"Predict the next statement of this code snippet:
 <s> return HasStdExtZve64d && HasStdExtD ;"
LLVM,RISCV,3892,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsI64 ( ) const {"
LLVM,RISCV,3893,"Predict the next statement of this code snippet:
 <s> return HasStdExtZve64x ;"
LLVM,RISCV,3894,"Predict the next statement of this code snippet:
 <s> bool is64Bit ( ) const {"
LLVM,RISCV,3895,"Predict the next statement of this code snippet:
 <s> bool is64Bit ( ) const { return HasRV64 ;"
LLVM,RISCV,3896,"Predict the next statement of this code snippet:
 <s> assert ( i < <STR_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,3897,"Predict the next statement of this code snippet:
 <s> assert ( i < <STR_LIT> && <STR_LIT> ) ; return UserReservedRegister [ i ] ;"
LLVM,RISCV,3898,"Predict the next statement of this code snippet:
 <s> return IsRV32E ;"
LLVM,RISCV,3899,"Predict the next statement of this code snippet:
 <s> bool isRV32E ( ) const {"
LLVM,RISCV,3900,"Predict the next statement of this code snippet:
 <s> assert ( hasVInstructions ( ) && <STR_LIT> ) ; assert ( RVVVectorLMULMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorLMULMax ) && <STR_LIT> ) ;"
LLVM,RISCV,3901,"Predict the next statement of this code snippet:
 <s> assert ( RVVVectorBitsMax >= RVVVectorBitsMin && <STR_LIT> <STR_LIT> ) ; unsigned Max = std :: max ( RVVVectorBitsMin , RVVVectorBitsMax ) ; return PowerOf2Floor ( ( Max < <NUM_LIT> || Max > <NUM_LIT> ) ? <NUM_LIT> : Max ) ;"
LLVM,RISCV,3902,"Predict the next statement of this code snippet:
 <s> assert ( ( RVVVectorBitsMin == <NUM_LIT> || ( RVVVectorBitsMin >= <NUM_LIT> && RVVVectorBitsMin <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMin ) ) ) && <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,3903,"Predict the next statement of this code snippet:
 <s> bool hasStdExtB ( ) const {"
LLVM,RISCV,3904,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZbproposedc ( ) const { return HasStdExtZbproposedc ;"
LLVM,RISCV,3905,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZbproposedc ( ) const { return HasStdExtZbproposedc ;"
LLVM,RISCV,3906,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; if ( CPU . empty ( ) || CPU == <STR_LIT> ) CPU = Is64Bit ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,3907,"Predict the next statement of this code snippet:
 <s> bool Is64Bit = TT . isArch64Bit ( ) ; if ( CPU . empty ( ) || CPU == <STR_LIT> ) CPU = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( TuneCPU . empty ( ) ) TuneCPU = CPU ; ParseSubtargetFeatures ( CPU , TuneCPU , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT> ; XLen = <NUM_LIT> ;"
LLVM,RISCV,3908,"Predict the next statement of this code snippet:
 <s> return ! <ISA_LIT>DisableUsingConstantPoolForLargeInts ;"
LLVM,RISCV,3909,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>Subtarget :: useConstantPoolForLargeInts ( ) const { return ! <ISA_LIT>DisableUsingConstantPoolForLargeInts ;"
LLVM,RISCV,3910,"Predict the next statement of this code snippet:
 <s> return hasVInstructions ( ) && getMinRVVVectorSizeInBits ( ) != <NUM_LIT> ;"
LLVM,RISCV,3911,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>Subtarget :: enableSubRegLiveness ( ) const { return EnableSubRegLiveness ;"
LLVM,RISCV,3912,"Predict the next statement of this code snippet:
 <s> if ( RVVVectorBitsMax == <NUM_LIT> ) return <NUM_LIT> ; if ( RVVVectorBitsMax < ( int ) ZvlLen ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,3913,"Predict the next statement of this code snippet:
 <s> if ( RVVVectorBitsMax < ( int ) ZvlLen ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= RVVVectorBitsMin && <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,3914,"Predict the next statement of this code snippet:
 <s> assert ( ( RVVVectorBitsMin == <NUM_LIT> || ( RVVVectorBitsMin >= <NUM_LIT> && RVVVectorBitsMin <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMin ) ) ) && <STR_LIT> <STR_LIT> ) ; assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == <NUM_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned Min = RVVVectorBitsMin ;"
LLVM,RISCV,3915,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>Subtarget :: getMaxLMULForFixedLengthVectors ( ) const { assert ( hasStdExtV ( ) && <STR_LIT> ) ;"
LLVM,RISCV,3916,"Predict the next statement of this code snippet:
 <s> assert ( hasStdExtV ( ) && <STR_LIT> ) ;"
LLVM,RISCV,3917,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , bool Is64Bit ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT> ; XLen = <NUM_LIT> ; }"
LLVM,RISCV,3918,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS , TT . isArch64Bit ( ) ) ) , InstrInfo ( ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {"
LLVM,RISCV,3919,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS , TT . isArch64Bit ( ) ) ) , InstrInfo ( ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {"
LLVM,RISCV,3920,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT> ; XLen = <NUM_LIT> ; }"
LLVM,RISCV,3921,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT> ; XLen = <NUM_LIT> ; } TargetABI = <STR_LIT> ( TT , getFeatureBits ( ) , ABIName ) ; <STR_LIT> ( TT , getFeatureBits ( ) ) ; return * this ;"
LLVM,RISCV,3922,"Predict the next statement of this code snippet:
 <s> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ;"
LLVM,RISCV,3923,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS , TT . isArch64Bit ( ) ) ) , InstrInfo ( ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {"
LLVM,RISCV,3924,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS , TT . isArch64Bit ( ) ) ) , InstrInfo ( ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {"
LLVM,RISCV,3925,"Predict the next statement of this code snippet:
 <s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT> ; XLen = <NUM_LIT> ; }"
LLVM,RISCV,3926,"Predict the next statement of this code snippet:
 <s> assert ( hasVInstructions ( ) && <STR_LIT> ) ; assert ( RVVVectorELENMax <= <NUM_LIT> && RVVVectorELENMax >= <NUM_LIT> && isPowerOf2_32 ( RVVVectorELENMax ) && <STR_LIT> ) ; unsigned ELEN = hasVInstructionsI64 ( ) ? <NUM_LIT> : <NUM_LIT> ; return PowerOf2Floor ( std :: max < unsigned > ( std :: min < unsigned > ( RVVVectorELENMax , ELEN ) , <NUM_LIT> ) ) ;"
LLVM,RISCV,3927,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>Subtarget :: getMaxELENForFixedLengthVectors ( ) const { assert ( hasVInstructions ( ) && <STR_LIT> ) ; assert ( RVVVectorELENMax <= <NUM_LIT> && RVVVectorELENMax >= <NUM_LIT> && isPowerOf2_32 ( RVVVectorELENMax ) && <STR_LIT> ) ; unsigned ELEN = hasVInstructionsI64 ( ) ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,3928,"Predict the next statement of this code snippet:
 <s> bool hasC910 ( ) const { return HasC910 ;"
LLVM,RISCV,3929,"Predict the next statement of this code snippet:
 <s> bool hasC910 ( ) const {"
LLVM,RISCV,3930,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( RV32 ) , HasM ( false ) , HasA ( false ) , HasF ( false ) , HasD ( false ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {"
LLVM,RISCV,3931,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( RV32 ) , HasM ( false ) , HasA ( false ) , HasF ( false ) , HasD ( false ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {"
LLVM,RISCV,3932,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZvqmac ( ) const {"
LLVM,RISCV,3933,"Predict the next statement of this code snippet:
 <s> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ;"
LLVM,RISCV,3934,"Predict the next statement of this code snippet:
 <s> return EnableCheriRVCInstrs ;"
LLVM,RISCV,3935,"Predict the next statement of this code snippet:
 <s> bool enableCheriRVCInstrs ( ) const {"
LLVM,RISCV,3936,"Predict the next statement of this code snippet:
 <s> return IsCapMode ;"
LLVM,RISCV,3937,"Predict the next statement of this code snippet:
 <s> bool isCapMode ( ) const {"
LLVM,RISCV,3938,"Predict the next statement of this code snippet:
 <s> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ;"
LLVM,RISCV,3939,"Predict the next statement of this code snippet:
 <s> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM ) , * this , * RBI ) ) ;"
LLVM,RISCV,3940,"Predict the next statement of this code snippet:
 <s> return is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,3941,"Predict the next statement of this code snippet:
 <s> return is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,RISCV,3942,"Predict the next statement of this code snippet:
 <s> bool Is64Bit = TT . isArch64Bit ( ) ; std :: string CPUName = std :: string ( CPU ) ; std :: string TuneCPUName = std :: string ( TuneCPU ) ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; ParseSubtargetFeatures ( CPUName , TuneCPUName , FS ) ; if ( Is64Bit ) {"
LLVM,RISCV,3943,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( RV32 ) , HasM ( false ) , HasA ( false ) , HasF ( false ) , HasD ( false ) , IsR5CY ( false ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {"
LLVM,RISCV,3944,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( RV32 ) , HasM ( false ) , HasA ( false ) , HasF ( false ) , HasD ( false ) , IsR5CY ( false ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {"
LLVM,RISCV,3945,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS , TT . isArch64Bit ( ) ) ) , InstrInfo ( * this ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {"
LLVM,RISCV,3946,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS , TT . isArch64Bit ( ) ) ) , InstrInfo ( * this ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {"
LLVM,RISCV,3947,"Predict the next statement of this code snippet:
 <s> assert ( hasVInstructions ( ) && <STR_LIT> ) ;"
LLVM,RISCV,3948,"Predict the next statement of this code snippet:
 <s> assert ( hasVInstructions ( ) && <STR_LIT> ) ; assert ( RVVVectorELENMax <= <NUM_LIT> && RVVVectorELENMax >= <NUM_LIT> && isPowerOf2_32 ( RVVVectorELENMax ) && <STR_LIT> ) ; return PowerOf2Floor ( std :: max < unsigned > ( std :: min < unsigned > ( RVVVectorELENMax , <NUM_LIT> ) , <NUM_LIT> ) ) ;"
LLVM,RISCV,3949,"Predict the next statement of this code snippet:
 <s> if ( RVVVectorBitsMax == <NUM_LIT> ) return <NUM_LIT> ; assert ( RVVVectorBitsMax >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= RVVVectorBitsMin && <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,3950,"Predict the next statement of this code snippet:
 <s> assert ( hasVInstructions ( ) && <STR_LIT> ) ; assert ( ( RVVVectorBitsMin == <NUM_LIT> || ( RVVVectorBitsMin >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMin ) ) ) && <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,3951,"Predict the next statement of this code snippet:
 <s> assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == <NUM_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned Min = RVVVectorBitsMin ;"
LLVM,RISCV,3952,"Predict the next statement of this code snippet:
 <s> return HasStdExtP ;"
LLVM,RISCV,3953,"Predict the next statement of this code snippet:
 <s> return Zvl65536b ;"
LLVM,RISCV,3954,"Predict the next statement of this code snippet:
 <s> bool hasVInstructions ( ) const { return HasStdExtV || HasStdExtZve32x ;"
LLVM,RISCV,3955,"Predict the next statement of this code snippet:
 <s> return HasStdExtV || HasStdExtZve32x ;"
LLVM,RISCV,3956,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsF32 ( ) const { return HasStdExtV || ( HasStdExtZve32f && HasStdExtF ) ;"
LLVM,RISCV,3957,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsF32 ( ) const { return HasStdExtV || ( HasStdExtZve32f && HasStdExtF ) ;"
LLVM,RISCV,3958,"Predict the next statement of this code snippet:
 <s> return HasStdExtV || ( HasStdExtZve64d && HasStdExtD ) ;"
LLVM,RISCV,3959,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsF64 ( ) const {"
LLVM,RISCV,3960,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsI64 ( ) const { return HasStdExtV || HasStdExtZve64x ;"
LLVM,RISCV,3961,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsI64 ( ) const {"
LLVM,RISCV,3962,"Predict the next statement of this code snippet:
 <s> bool hasNonStdExtPulp ( ) const {"
LLVM,RISCV,3963,"Predict the next statement of this code snippet:
 <s> return HasExtXCoreV ;"
LLVM,RISCV,3964,"Predict the next statement of this code snippet:
 <s> bool hasExtXCoreVMac ( ) const { return HasExtXCoreVMac ;"
LLVM,RISCV,3965,"Predict the next statement of this code snippet:
 <s> return HasExtXCoreVMem ;"
LLVM,RISCV,3966,"Predict the next statement of this code snippet:
 <s> bool hasVInstructions ( ) const { return HasStdExtV ;"
LLVM,RISCV,3967,"Predict the next statement of this code snippet:
 <s> bool hasVInstructions ( ) const { return HasStdExtV ;"
LLVM,RISCV,3968,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsF16 ( ) const { return HasStdExtV && hasStdExtZfh ( ) ;"
LLVM,RISCV,3969,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsF32 ( ) const {"
LLVM,RISCV,3970,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsF64 ( ) const { return HasStdExtV && hasStdExtD ( ) ;"
LLVM,RISCV,3971,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsF64 ( ) const {"
LLVM,RISCV,3972,"Predict the next statement of this code snippet:
 <s> return HasStdExtV ;"
LLVM,RISCV,3973,"Predict the next statement of this code snippet:
 <s> bool hasVInstructionsI64 ( ) const {"
LLVM,RISCV,3974,"Predict the next statement of this code snippet:
 <s> auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ;"
LLVM,RISCV,3975,"Predict the next statement of this code snippet:
 <s> if ( RVVVectorBitsMax == <NUM_LIT> ) return <NUM_LIT> ; assert ( RVVVectorBitsMax >= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= RVVVectorBitsMin && <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,3976,"Predict the next statement of this code snippet:
 <s> if ( RVVVectorBitsMax != <NUM_LIT> ) Min = std :: min ( RVVVectorBitsMin , RVVVectorBitsMax ) ;"
LLVM,RISCV,3977,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , StringRef ABIName , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( TT , CPU , FS , ABIName ) ) , InstrInfo ( ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {"
LLVM,RISCV,3978,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , StringRef ABIName , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( TT , CPU , FS , ABIName ) ) , InstrInfo ( ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {"
LLVM,RISCV,3979,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>Subtarget :: anchor ( ) {"
LLVM,RISCV,3980,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>Subtarget :: anchor ( ) {"
LLVM,RISCV,3981,"Predict the next statement of this code snippet:
 <s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( ) const {"
LLVM,RISCV,3982,"Predict the next statement of this code snippet:
 <s> return InstSelector . get ( ) ;"
LLVM,RISCV,3983,"Predict the next statement of this code snippet:
 <s> return Legalizer . get ( ) ;"
LLVM,RISCV,3984,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>Subtarget :: getMaxELENForFixedLengthVectors ( ) const { assert ( hasStdExtV ( ) && <STR_LIT> ) ; assert ( RVVVectorELENMax <= <NUM_LIT> && RVVVectorELENMax >= <NUM_LIT> && isPowerOf2_32 ( RVVVectorELENMax ) && <STR_LIT> ) ;"
LLVM,RISCV,3985,"Predict the next statement of this code snippet:
 <s> return PowerOf2Floor ( std :: max < unsigned > ( std :: min < unsigned > ( RVVVectorELENMax , <NUM_LIT> ) , <NUM_LIT> ) ) ;"
LLVM,RISCV,3986,"Predict the next statement of this code snippet:
 <s> return hasStdExtV ( ) ? MaxInterleaveFactor : <NUM_LIT> ;"
LLVM,RISCV,3987,"Predict the next statement of this code snippet:
 <s> assert ( hasStdExtV ( ) && <STR_LIT> ) ;"
LLVM,RISCV,3988,"Predict the next statement of this code snippet:
 <s> assert ( RVVVectorBitsMax >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= RVVVectorBitsMin && <STR_LIT> <STR_LIT> ) ; unsigned Max = std :: max ( RVVVectorBitsMin , RVVVectorBitsMax ) ; return PowerOf2Floor ( ( Max < <NUM_LIT> || Max > <NUM_LIT> ) ? <NUM_LIT> : Max ) ;"
LLVM,RISCV,3989,"Predict the next statement of this code snippet:
 <s> assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == <NUM_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned Min = RVVVectorBitsMin ; if ( RVVVectorBitsMax != <NUM_LIT> ) Min = std :: min ( RVVVectorBitsMin , RVVVectorBitsMax ) ; return PowerOf2Floor ( ( Min < <NUM_LIT> || Min > <NUM_LIT> ) ? <NUM_LIT> : Min ) ;"
LLVM,RISCV,3990,"Predict the next statement of this code snippet:
 <s> return HasStdExtZvamo ;"
LLVM,RISCV,3991,"Predict the next statement of this code snippet:
 <s> bool hasStdExtZvlsseg ( ) const {"
LLVM,RISCV,3992,"Predict the next statement of this code snippet:
 <s> if ( CPU == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> ) + ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; if ( TuneCPU . empty ( ) ) TuneCPU = CPU ; ParseSubtargetFeatures ( CPU , TuneCPU , FS ) ; if ( Is64Bit ) {"
LLVM,RISCV,3993,"Predict the next statement of this code snippet:
 <s> if ( CPU == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> ) + ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; if ( TuneCPU . empty ( ) ) TuneCPU = CPU ;"
LLVM,RISCV,3994,"Predict the next statement of this code snippet:
 <s> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM ) , * this , * RBI ) ) ;"
LLVM,RISCV,3995,"Predict the next statement of this code snippet:
 <s> RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,3996,"Predict the next statement of this code snippet:
 <s> Target & getThe<ISA_LIT>32Target ( ) { static Target The<ISA_LIT>32Target ;"
LLVM,RISCV,3997,"Predict the next statement of this code snippet:
 <s> static Target The<ISA_LIT>32Target ;"
LLVM,RISCV,3998,"Predict the next statement of this code snippet:
 <s> Target & getThe<ISA_LIT>64Target ( ) { static Target The<ISA_LIT>64Target ;"
LLVM,RISCV,3999,"Predict the next statement of this code snippet:
 <s> RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,4000,"Predict the next statement of this code snippet:
 <s> static Target The<ISA_LIT>32Target ;"
LLVM,RISCV,4001,"Predict the next statement of this code snippet:
 <s> Target & llvm :: getThe<ISA_LIT>32Target ( ) { static Target The<ISA_LIT>32Target ;"
LLVM,RISCV,4002,"Predict the next statement of this code snippet:
 <s> static Target The<ISA_LIT>64Target ;"
LLVM,RISCV,4003,"Predict the next statement of this code snippet:
 <s> RegisterTarget < Triple :: riscv64 > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,4004,"Predict the next statement of this code snippet:
 <s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,4005,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {"
LLVM,RISCV,4006,"Predict the next statement of this code snippet:
 <s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret = TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> <STR_LIT> ;"
LLVM,RISCV,4007,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>PassConfig ( this , PM ) ;"
LLVM,RISCV,4008,"Predict the next statement of this code snippet:
 <s> return getTM < <ISA_LIT>TargetMachine > ( ) ;"
LLVM,RISCV,4009,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > A ( The<ISA_LIT>Target ) ; RegisterTargetMachine < <ISA_LIT>64TargetMachine > B ( The<ISA_LIT>64Target ) ;"
LLVM,RISCV,4010,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>64TargetMachine :: <ISA_LIT>64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) {"
LLVM,RISCV,4011,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>64TargetMachine :: <ISA_LIT>64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) {"
LLVM,RISCV,4012,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {"
LLVM,RISCV,4013,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {"
LLVM,RISCV,4014,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {"
LLVM,RISCV,4015,"Predict the next statement of this code snippet:
 <s> return TLOF . get ( ) ;"
LLVM,RISCV,4016,"Predict the next statement of this code snippet:
 <s> const auto * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return new yaml :: <ISA_LIT>MachineFunctionInfo ( * MFI ) ;"
LLVM,RISCV,4017,"Predict the next statement of this code snippet:
 <s> const auto * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;"
LLVM,RISCV,4018,"Predict the next statement of this code snippet:
 <s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) {"
LLVM,RISCV,4019,"Predict the next statement of this code snippet:
 <s> bool IsRV64 ( ) const { return getTargetTriple ( ) . isArch64Bit ( ) ;"
LLVM,RISCV,4020,"Predict the next statement of this code snippet:
 <s> PFS . MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> initializeBaseYamlFields ( YamlMFI ) ;"
LLVM,RISCV,4021,"Predict the next statement of this code snippet:
 <s> if ( TT . isArch64Bit ( ) ) { return <STR_LIT> ; } else { assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ;"
LLVM,RISCV,4022,"Predict the next statement of this code snippet:
 <s> assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ;"
LLVM,RISCV,4023,"Predict the next statement of this code snippet:
 <s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {"
LLVM,RISCV,4024,"Predict the next statement of this code snippet:
 <s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TargetPassConfig ( * this , PM ) ;"
LLVM,RISCV,4025,"Predict the next statement of this code snippet:
 <s> if ( CM ) return * CM ; return CodeModel :: Small ;"
LLVM,RISCV,4026,"Predict the next statement of this code snippet:
 <s> if ( CM ) return * CM ;"
LLVM,RISCV,4027,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ;"
LLVM,RISCV,4028,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) {"
LLVM,RISCV,4029,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {"
LLVM,RISCV,4030,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {"
LLVM,RISCV,4031,"Predict the next statement of this code snippet:
 <s> if ( TT . isArch64Bit ( ) ) { return <STR_LIT> ; } else {"
LLVM,RISCV,4032,"Predict the next statement of this code snippet:
 <s> static std :: string computeDataLayout ( const Triple & TT ) { if ( TT . isArch64Bit ( ) ) { return <STR_LIT> ; } else {"
LLVM,RISCV,4033,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) {"
LLVM,RISCV,4034,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) {"
LLVM,RISCV,4035,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ;"
LLVM,RISCV,4036,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) {"
LLVM,RISCV,4037,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) {"
LLVM,RISCV,4038,"Predict the next statement of this code snippet:
 <s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ;"
LLVM,RISCV,4039,"Predict the next statement of this code snippet:
 <s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ;"
LLVM,RISCV,4040,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ; auto * PR = PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( * PR ) ; initialize<ISA_LIT>MergeBaseOffsetOptPass ( * PR ) ;"
LLVM,RISCV,4041,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ;"
LLVM,RISCV,4042,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; } else {"
LLVM,RISCV,4043,"Predict the next statement of this code snippet:
 <s> assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ;"
LLVM,RISCV,4044,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ;"
LLVM,RISCV,4045,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , Options . MCOptions . getABIName ( ) , * this ) {"
LLVM,RISCV,4046,"Predict the next statement of this code snippet:
 <s> initializeGlobalISel ( * PR ) ; initialize<ISA_LIT>MergeBaseOffsetOptPass ( * PR ) ; initialize<ISA_LIT>ExpandPseudoPass ( * PR ) ; initialize<ISA_LIT>CleanupVSETVLIPass ( * PR ) ;"
LLVM,RISCV,4047,"Predict the next statement of this code snippet:
 <s> addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ;"
LLVM,RISCV,4048,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( create<ISA_LIT>GatherScatterLoweringPass ( ) ) ;"
LLVM,RISCV,4049,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ;"
LLVM,RISCV,4050,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PassConfig :: addLegalizeMachineIR ( ) {"
LLVM,RISCV,4051,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ;"
LLVM,RISCV,4052,"Predict the next statement of this code snippet:
 <s> if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: riscv64 ) addPass ( create<ISA_LIT>SExtWRemovalPass ( ) ) ;"
LLVM,RISCV,4053,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) {"
LLVM,RISCV,4054,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableRedundantCopyElimination ) addPass ( create<ISA_LIT>RedundantCopyEliminationPass ( ) ) ;"
LLVM,RISCV,4055,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ExpandAtomicPseudoPass ( ) ) ;"
LLVM,RISCV,4056,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ExpandAtomicPseudoPass ( ) ) ;"
LLVM,RISCV,4057,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ;"
LLVM,RISCV,4058,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ;"
LLVM,RISCV,4059,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) {"
LLVM,RISCV,4060,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) {"
LLVM,RISCV,4061,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ;"
LLVM,RISCV,4062,"Predict the next statement of this code snippet:
 <s> addPass ( new RegBankSelect ( ) ) ;"
LLVM,RISCV,4063,"Predict the next statement of this code snippet:
 <s> static StringRef computeDataLayout ( const Triple & TT ) { if ( TT . isArch64Bit ( ) ) return <STR_LIT> ; assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ;"
LLVM,RISCV,4064,"Predict the next statement of this code snippet:
 <s> assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ;"
LLVM,RISCV,4065,"Predict the next statement of this code snippet:
 <s> std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + TuneCPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) {"
LLVM,RISCV,4066,"Predict the next statement of this code snippet:
 <s> Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute TuneAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + TuneCPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; auto ABIName = Options . MCOptions . getABIName ( ) ; if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) { auto TargetABI = <STR_LIT> ( ABIName ) ; if ( TargetABI != <STR_LIT> && ModuleTargetABI -> getString ( ) != ABIName ) {"
LLVM,RISCV,4067,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const {"
LLVM,RISCV,4068,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const {"
LLVM,RISCV,4069,"Predict the next statement of this code snippet:
 <s> initializeGlobalISel ( * PR ) ; initialize<ISA_LIT>GatherScatterLoweringPass ( * PR ) ; initialize<ISA_LIT>MergeBaseOffsetOptPass ( * PR ) ;"
LLVM,RISCV,4070,"Predict the next statement of this code snippet:
 <s> addPass ( & BranchRelaxationPassID ) ; addPass ( create<ISA_LIT>MakeCompressibleOptPass ( ) ) ;"
LLVM,RISCV,4071,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) {"
LLVM,RISCV,4072,"Predict the next statement of this code snippet:
 <s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createBarrierNoopPass ( ) ) ;"
LLVM,RISCV,4073,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ; auto * PR = PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( * PR ) ; initialize<ISA_LIT>MakeCompressibleOptPass ( * PR ) ;"
LLVM,RISCV,4074,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) { initAsmInfo ( ) ; setMachineOutliner ( true ) ;"
LLVM,RISCV,4075,"Predict the next statement of this code snippet:
 <s> if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( create<ISA_LIT>RemoveRedundancyVSETVLPass ( ) ) ;"
LLVM,RISCV,4076,"Predict the next statement of this code snippet:
 <s> if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( create<ISA_LIT>RemoveRedundancyVSETVLPass ( ) ) ;"
LLVM,RISCV,4077,"Predict the next statement of this code snippet:
 <s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; auto ABIName = Options . MCOptions . getABIName ( ) ; if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) {"
LLVM,RISCV,4078,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ; auto PR = PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( * PR ) ; initialize<ISA_LIT>ExpandPseudoPass ( * PR ) ;"
LLVM,RISCV,4079,"Predict the next statement of this code snippet:
 <s> addPass ( createCheriBoundAllocasPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ;"
LLVM,RISCV,4080,"Predict the next statement of this code snippet:
 <s> addPass ( createCheriBoundAllocasPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ;"
LLVM,RISCV,4081,"Predict the next statement of this code snippet:
 <s> IntegerTypes = <STR_LIT> ; } else { IntegerTypes = <STR_LIT> ; } StringRef CapTypes = <STR_LIT> ; StringRef PurecapOptions = <STR_LIT> ; if ( FS . contains ( <STR_LIT> ) ) { if ( TT . isArch64Bit ( ) ) CapTypes = <STR_LIT> ; else CapTypes = <STR_LIT> ; <STR_LIT> ABI = <STR_LIT> ( Options . MCOptions . getABIName ( ) ) ; if ( ABI != <STR_LIT> && <STR_LIT> ( ABI ) ) PurecapOptions = <STR_LIT> ; }"
LLVM,RISCV,4082,"Predict the next statement of this code snippet:
 <s> } else { IntegerTypes = <STR_LIT> ; } StringRef CapTypes = <STR_LIT> ; StringRef PurecapOptions = <STR_LIT> ; if ( FS . contains ( <STR_LIT> ) ) { if ( TT . isArch64Bit ( ) ) CapTypes = <STR_LIT> ; else CapTypes = <STR_LIT> ; <STR_LIT> ABI = <STR_LIT> ( Options . MCOptions . getABIName ( ) ) ; if ( ABI != <STR_LIT> && <STR_LIT> ( ABI ) ) PurecapOptions = <STR_LIT> ; } return ( <STR_LIT> + CapTypes + IntegerTypes + <STR_LIT> + PurecapOptions ) . str ( ) ;"
LLVM,RISCV,4083,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const {"
LLVM,RISCV,4084,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT , FS , Options ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) {"
LLVM,RISCV,4085,"Predict the next statement of this code snippet:
 <s> std :: string Key = CPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ;"
LLVM,RISCV,4086,"Predict the next statement of this code snippet:
 <s> initializeGlobalISel ( * PR ) ; initialize<ISA_LIT>GatherScatterLoweringPass ( * PR ) ; initialize<ISA_LIT>MergeBaseOffsetOptPass ( * PR ) ; initialize<ISA_LIT>ExpandPseudoPass ( * PR ) ; initialize<ISA_LIT>InsertVSETVLIPass ( * PR ) ;"
LLVM,RISCV,4087,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo ( ) ;"
LLVM,RISCV,4088,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ExpandAtomicPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>ExpandCoreVHwlpPseudoPass ( ) ) ;"
LLVM,RISCV,4089,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ;"
LLVM,RISCV,4090,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) {"
LLVM,RISCV,4091,"Predict the next statement of this code snippet:
 <s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createHardwareLoopsPass ( ) ) ; }"
LLVM,RISCV,4092,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ;"
LLVM,RISCV,4093,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ; addPass ( create<ISA_LIT>CoreVHwlpBlocksPass ( ) ) ;"
LLVM,RISCV,4094,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , Options . MCOptions . getABIName ( ) , * this ) { initAsmInfo ( ) ;"
LLVM,RISCV,4095,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , Options . MCOptions . getABIName ( ) , * this ) { initAsmInfo ( ) ;"
LLVM,RISCV,4096,"Predict the next statement of this code snippet:
 <s> std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; auto ABIName = Options . MCOptions . getABIName ( ) ; if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) { auto TargetABI = <STR_LIT> ( ABIName ) ;"
LLVM,RISCV,4097,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ; auto PR = PassRegistry :: getPassRegistry ( ) ;"
LLVM,RISCV,4098,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ; auto PR = PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( * PR ) ;"
LLVM,RISCV,4099,"Predict the next statement of this code snippet:
 <s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>PulpHWLoopsPass ( ) ) ;"
LLVM,RISCV,4100,"Predict the next statement of this code snippet:
 <s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ;"
LLVM,RISCV,4101,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addISelPrepare ( ) { TargetPassConfig :: addISelPrepare ( ) ;"
LLVM,RISCV,4102,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ;"
LLVM,RISCV,4103,"Predict the next statement of this code snippet:
 <s> TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( create<ISA_LIT>OptimizeVSETVLUsesPass ( ) ) ;"
LLVM,RISCV,4104,"Predict the next statement of this code snippet:
 <s> if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return * RM ;"
LLVM,RISCV,4105,"Predict the next statement of this code snippet:
 <s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ;"
LLVM,RISCV,4106,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>64TargetMachine :: <ISA_LIT>64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) {"
LLVM,RISCV,4107,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>64TargetMachine :: <ISA_LIT>64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) {"
LLVM,RISCV,4108,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;"
LLVM,RISCV,4109,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {"
LLVM,RISCV,4110,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {"
LLVM,RISCV,4111,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;"
LLVM,RISCV,4112,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ;"
LLVM,RISCV,4113,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addIRPasses ( ) {"
LLVM,RISCV,4114,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ;"
LLVM,RISCV,4115,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ;"
LLVM,RISCV,4116,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) {"
LLVM,RISCV,4117,"Predict the next statement of this code snippet:
 <s> assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ;"
LLVM,RISCV,4118,"Predict the next statement of this code snippet:
 <s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM ) ;"
LLVM,RISCV,4119,"Predict the next statement of this code snippet:
 <s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM ) ;"
LLVM,RISCV,4120,"Predict the next statement of this code snippet:
 <s> auto PR = PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>ExpandPseudoPass ( * PR ) ;"
LLVM,RISCV,4121,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ; auto PR = PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>ExpandPseudoPass ( * PR ) ;"
LLVM,RISCV,4122,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {"
LLVM,RISCV,4123,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {"
LLVM,RISCV,4124,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;"
LLVM,RISCV,4125,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;"
LLVM,RISCV,4126,"Predict the next statement of this code snippet:
 <s> StringRef Key = MFE . Key -> getString ( ) ; if ( Key == <STR_LIT> ) { SSThreshold = mdconst :: extract < ConstantInt > ( MFE . Val ) -> getZExtValue ( ) ; break ;"
LLVM,RISCV,4127,"Predict the next statement of this code snippet:
 <s> for ( const auto & MFE : ModuleFlags ) { StringRef Key = MFE . Key -> getString ( ) ; if ( Key == <STR_LIT> ) {"
LLVM,RISCV,4128,"Predict the next statement of this code snippet:
 <s> SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;"
LLVM,RISCV,4129,"Predict the next statement of this code snippet:
 <s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ;"
LLVM,RISCV,4130,"Predict the next statement of this code snippet:
 <s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVA ) return false ; if ( GVA -> hasSection ( ) ) { StringRef Section = GVA -> getSection ( ) ; if ( Section == <STR_LIT> || Section == <STR_LIT> ) return true ; return false ; } if ( ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) ) ) return false ; Type * Ty = GVA -> getValueType ( ) ; if ( ! Ty -> isSized ( ) ) return false ;"
LLVM,RISCV,4131,"Predict the next statement of this code snippet:
 <s> return Size > <NUM_LIT> && Size <= SSThreshold ;"
LLVM,RISCV,4132,"Predict the next statement of this code snippet:
 <s> if ( Kind . isData ( ) && isGlobalInSmallSection ( GO , TM ) ) return SmallDataSection ;"
LLVM,RISCV,4133,"Predict the next statement of this code snippet:
 <s> Align <ISA_LIT>ELFTargetObjectFile :: getAlignmentForPreciseBounds ( uint64_t Size , const TargetMachine & TM ) const { if ( ! getContext ( ) . getAsmInfo ( ) -> isCheriPurecapABI ( ) ) return Align ( ) ; const <ISA_LIT>TargetMachine & RTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ;"
LLVM,RISCV,4134,"Predict the next statement of this code snippet:
 <s> MCSection * <ISA_LIT>ELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const {"
LLVM,RISCV,4135,"Predict the next statement of this code snippet:
 <s> MCSection * <ISA_LIT>ELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align ) ;"
LLVM,RISCV,4136,"Predict the next statement of this code snippet:
 <s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;"
LLVM,RISCV,4137,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) {"
LLVM,RISCV,4138,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { OS << <STR_LIT> << Attribute << <STR_LIT> << Twine ( Value ) << <STR_LIT> ;"
LLVM,RISCV,4139,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> << Attribute << <STR_LIT> << Twine ( Value ) << <STR_LIT> ;"
LLVM,RISCV,4140,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ;"
LLVM,RISCV,4141,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveOptionNoPIC ( ) { OS << <STR_LIT> ;"
LLVM,RISCV,4142,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ;"
LLVM,RISCV,4143,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ;"
LLVM,RISCV,4144,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ;"
LLVM,RISCV,4145,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveOptionPIC ( ) { OS << <STR_LIT> ;"
LLVM,RISCV,4146,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ;"
LLVM,RISCV,4147,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ;"
LLVM,RISCV,4148,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ;"
LLVM,RISCV,4149,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveOptionRVC ( ) { OS << <STR_LIT> ;"
LLVM,RISCV,4150,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) {"
LLVM,RISCV,4151,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) {"
LLVM,RISCV,4152,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else emitAttribute ( <STR_LIT> , <STR_LIT> ) ; auto ParseResult = <STR_LIT> ( STI . hasFeature ( <STR_LIT> ) , STI . getFeatureBits ( ) ) ; if ( ! ParseResult ) { report_fatal_error ( ParseResult . takeError ( ) ) ; } else { auto & ISAInfo = * ParseResult ;"
LLVM,RISCV,4153,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) { OS << <STR_LIT> << Attribute << <STR_LIT> << String << <STR_LIT> ;"
LLVM,RISCV,4154,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: finish ( ) { finishAttributeSection ( ) ;"
LLVM,RISCV,4155,"Predict the next statement of this code snippet:
 <s> finishAttributeSection ( ) ;"
LLVM,RISCV,4156,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: finishAttributeSection ( ) {"
LLVM,RISCV,4157,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: finishAttributeSection ( ) {"
LLVM,RISCV,4158,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: reset ( ) {"
LLVM,RISCV,4159,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: reset ( ) {"
LLVM,RISCV,4160,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) {"
LLVM,RISCV,4161,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) {"
LLVM,RISCV,4162,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {"
LLVM,RISCV,4163,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {"
LLVM,RISCV,4164,"Predict the next statement of this code snippet:
 <s> assert ( ABI != <STR_LIT> && <STR_LIT> ) ;"
LLVM,RISCV,4165,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveOptionCapMode ( ) { OS << <STR_LIT> ;"
LLVM,RISCV,4166,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ;"
LLVM,RISCV,4167,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveOptionNoCapMode ( ) { OS << <STR_LIT> ;"
LLVM,RISCV,4168,"Predict the next statement of this code snippet:
 <s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;"
LLVM,RISCV,4169,"Predict the next statement of this code snippet:
 <s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch = <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; else Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;"
LLVM,RISCV,4170,"Predict the next statement of this code snippet:
 <s> else emitAttribute ( <STR_LIT> , <STR_LIT> ) ; std :: string Arch = <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch = <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; else Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;"
LLVM,RISCV,4171,"Predict the next statement of this code snippet:
 <s> else emitAttribute ( <STR_LIT> , <STR_LIT> ) ; unsigned XLen = STI . hasFeature ( <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; std :: vector < std :: string > FeatureVector ; <STR_LIT> ( FeatureVector , STI . getFeatureBits ( ) ) ; auto ParseResult = llvm :: <STR_LIT> ( XLen , FeatureVector ) ; if ( ! ParseResult ) { consumeError ( ParseResult . takeError ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; } else { auto & ISAInfo = * ParseResult ; emitTextAttribute ( <STR_LIT> , ISAInfo -> toString ( ) ) ;"
LLVM,RISCV,4172,"Predict the next statement of this code snippet:
 <s> std :: vector < std :: string > FeatureVector ; <STR_LIT> ( FeatureVector , STI . getFeatureBits ( ) ) ; auto ParseResult = llvm :: <STR_LIT> ( XLen , FeatureVector ) ; if ( ! ParseResult ) { consumeError ( ParseResult . takeError ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; } else {"
LLVM,RISCV,4173,"Predict the next statement of this code snippet:
 <s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;"
LLVM,RISCV,4174,"Predict the next statement of this code snippet:
 <s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; emitTextAttribute ( <STR_LIT> , Arch ) ;"
LLVM,RISCV,4175,"Predict the next statement of this code snippet:
 <s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;"
LLVM,RISCV,4176,"Predict the next statement of this code snippet:
 <s> else Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;"
LLVM,RISCV,4177,"Predict the next statement of this code snippet:
 <s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;"
LLVM,RISCV,4178,"Predict the next statement of this code snippet:
 <s> assert ( ISD && <STR_LIT> ) ; if ( ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; InstructionCost BaseCost = <NUM_LIT> ; unsigned VL = cast < FixedVectorType > ( VTy ) -> getNumElements ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VTy ) ;"
LLVM,RISCV,4179,"Predict the next statement of this code snippet:
 <s> if ( ! isTypeLegal ( Src ) || ! isTypeLegal ( Dst ) ) return BaseT :: getCastInstrCost ( Opcode , Dst , Src , CCH , CostKind , I ) ; if ( Src -> getScalarSizeInBits ( ) > ST -> getELEN ( ) || Dst -> getScalarSizeInBits ( ) > ST -> getELEN ( ) ) return BaseT :: getCastInstrCost ( Opcode , Dst , Src , CCH , CostKind , I ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; int PowDiff = ( int ) Log2_32 ( Dst -> getScalarSizeInBits ( ) ) - ( int ) Log2_32 ( Src -> getScalarSizeInBits ( ) ) ; switch ( ISD ) { case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> :"
LLVM,RISCV,4180,"Predict the next statement of this code snippet:
 <s> auto * RetTy = ICA . getReturnType ( ) ; switch ( ICA . getID ( ) ) { case <STR_LIT> : { unsigned Cost = <NUM_LIT> ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; return Cost + ( LT . first - <NUM_LIT> ) ; } default :"
LLVM,RISCV,4181,"Predict the next statement of this code snippet:
 <s> if ( ! isa < ScalableVectorType > ( Src ) ) return BaseT :: getMaskedMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; return getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ;"
LLVM,RISCV,4182,"Predict the next statement of this code snippet:
 <s> InstructionCost <ISA_LIT>TTIImpl :: getMaskedMemoryOpCost ( unsigned Opcode , Type * Src , Align Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind ) { if ( ! isa < ScalableVectorType > ( Src ) ) return BaseT :: getMaskedMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; return getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ;"
LLVM,RISCV,4183,"Predict the next statement of this code snippet:
 <s> unsigned getMaxInterleaveFactor ( unsigned VF ) { return ST -> getMaxInterleaveFactor ( ) ;"
LLVM,RISCV,4184,"Predict the next statement of this code snippet:
 <s> if ( ST -> hasVInstructions ( ) && MaxVectorSizeInBits != <NUM_LIT> ) return MaxVectorSizeInBits / <STR_LIT> ;"
LLVM,RISCV,4185,"Predict the next statement of this code snippet:
 <s> if ( ! ST -> useRVVForFixedLengthVectors ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; if ( Ty -> getScalarSizeInBits ( ) > ST -> getELEN ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; InstructionCost BaseCost = <NUM_LIT> ; unsigned VL = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ;"
LLVM,RISCV,4186,"Predict the next statement of this code snippet:
 <s> case TargetTransformInfo :: RGK_FixedWidthVector : return TypeSize :: getFixed ( ST -> hasStdExtV ( ) ? ST -> getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ) ; case TargetTransformInfo :: RGK_ScalableVector : return TypeSize :: getScalable ( ST -> hasStdExtV ( ) ? <STR_LIT> : <NUM_LIT> ) ;"
LLVM,RISCV,4187,"Predict the next statement of this code snippet:
 <s> return TypeSize :: getFixed ( ST -> getXLen ( ) ) ; case TargetTransformInfo :: RGK_FixedWidthVector :"
LLVM,RISCV,4188,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>TTIImpl :: getRegUsageForType ( Type * Ty ) { TypeSize Size = Ty -> getPrimitiveSizeInBits ( ) ; if ( Ty -> isVectorTy ( ) ) { if ( Size . isScalable ( ) && ST -> hasVInstructions ( ) ) return divideCeil ( Size . getKnownMinValue ( ) , <STR_LIT> ) ;"
LLVM,RISCV,4189,"Predict the next statement of this code snippet:
 <s> if ( Kind == TTI :: SK_Splice && isa < ScalableVectorType > ( Tp ) ) return getSpliceCost ( Tp , Index ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( Kind == TTI :: SK_Broadcast && isa < ScalableVectorType > ( Tp ) ) return LT . first * <NUM_LIT> ;"
LLVM,RISCV,4190,"Predict the next statement of this code snippet:
 <s> if ( Kind == TTI :: SK_Splice && isa < ScalableVectorType > ( Tp ) ) return getSpliceCost ( Tp , Index ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( Kind == TTI :: SK_Broadcast && isa < ScalableVectorType > ( Tp ) ) return LT . first * <NUM_LIT> ; return BaseT :: getShuffleCost ( Kind , Tp , Mask , Index , SubTp ) ;"
LLVM,RISCV,4191,"Predict the next statement of this code snippet:
 <s> InstructionCost <ISA_LIT>TTIImpl :: getSpliceCost ( VectorType * Tp , int Index ) {"
LLVM,RISCV,4192,"Predict the next statement of this code snippet:
 <s> InstructionCost <ISA_LIT>TTIImpl :: getSpliceCost ( VectorType * Tp , int Index ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; unsigned Cost = <NUM_LIT> ;"
LLVM,RISCV,4193,"Predict the next statement of this code snippet:
 <s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * > Operands ( I . operand_values ( ) ) ; Cost += getUserCost ( & I , Operands , TargetTransformInfo :: TCK_SizeAndLatency ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ;"
LLVM,RISCV,4194,"Predict the next statement of this code snippet:
 <s> bool isLegalMaskedGather ( Type * DataType , Align Alignment ) {"
LLVM,RISCV,4195,"Predict the next statement of this code snippet:
 <s> bool isLegalMaskedGather ( Type * DataType , Align Alignment ) { return isLegalMaskedGatherScatter ( DataType , Alignment ) ;"
LLVM,RISCV,4196,"Predict the next statement of this code snippet:
 <s> if ( ! ST -> hasStdExtV ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return isLegalElementTypeForRVV ( DataType -> getScalarType ( ) ) ;"
LLVM,RISCV,4197,"Predict the next statement of this code snippet:
 <s> return isLegalMaskedLoadStore ( DataType , Alignment ) ;"
LLVM,RISCV,4198,"Predict the next statement of this code snippet:
 <s> return isLegalMaskedLoadStore ( DataType , Alignment ) ;"
LLVM,RISCV,4199,"Predict the next statement of this code snippet:
 <s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return isLegalElementTypeForRVV ( DataType -> getScalarType ( ) ) ;"
LLVM,RISCV,4200,"Predict the next statement of this code snippet:
 <s> if ( ! ST -> hasStdExtV ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ;"
LLVM,RISCV,4201,"Predict the next statement of this code snippet:
 <s> return isLegalMaskedGatherScatter ( DataType , Alignment ) ;"
LLVM,RISCV,4202,"Predict the next statement of this code snippet:
 <s> bool isLegalMaskedStore ( Type * DataType , Align Alignment ) {"
LLVM,RISCV,4203,"Predict the next statement of this code snippet:
 <s> bool isLegalToVectorizeReduction ( const RecurrenceDescriptor & RdxDesc , ElementCount VF ) const { if ( ! ST -> hasStdExtV ( ) ) return false ; if ( ! VF . isScalable ( ) ) return true ; Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( ! isLegalElementTypeForRVV ( Ty ) ) return false ; switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add : case RecurKind :: FAdd : case RecurKind :: And : case RecurKind :: Or :"
LLVM,RISCV,4204,"Predict the next statement of this code snippet:
 <s> bool supportsScalableVectors ( ) const {"
LLVM,RISCV,4205,"Predict the next statement of this code snippet:
 <s> bool supportsScalableVectors ( ) const {"
LLVM,RISCV,4206,"Predict the next statement of this code snippet:
 <s> case Instruction :: Mul : Takes12BitImm = true ; break ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : Takes12BitImm = true ; ImmArgIdx = <NUM_LIT> ; break ; default : break ; } if ( Takes12BitImm ) { if ( Instruction :: isCommutative ( Opcode ) || Idx == ImmArgIdx ) { if ( Imm . getMinSignedBits ( ) <= <NUM_LIT> && getTLI ( ) -> isLegalAddImmediate ( Imm . getSExtValue ( ) ) ) { return TTI :: TCC_Free ; } } return getIntImmCost ( Imm , Ty , CostKind ) ; } return TTI :: TCC_Free ;"
LLVM,RISCV,4207,"Predict the next statement of this code snippet:
 <s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ;"
LLVM,RISCV,4208,"Predict the next statement of this code snippet:
 <s> bool isLegalMaskedLoadStore ( Type * DataType , Align Alignment ) { if ( ! ST -> hasStdExtV ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ;"
LLVM,RISCV,4209,"Predict the next statement of this code snippet:
 <s> if ( ! ST -> hasStdExtV ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ;"
LLVM,RISCV,4210,"Predict the next statement of this code snippet:
 <s> InstructionCost <ISA_LIT>TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) && <STR_LIT> ) ; if ( Imm == <NUM_LIT> ) return TTI :: TCC_Free ; const DataLayout & DL = getDataLayout ( ) ; return <STR_LIT> ( Imm , DL . getTypeSizeInBits ( Ty ) , getST ( ) -> is64Bit ( ) ) ;"
LLVM,RISCV,4211,"Predict the next statement of this code snippet:
 <s> const DataLayout & DL = getDataLayout ( ) ;"
LLVM,RISCV,4212,"Predict the next statement of this code snippet:
 <s> return ST -> useRVVForFixedLengthVectors ( ) ? <NUM_LIT> : <NUM_LIT> ;"
LLVM,RISCV,4213,"Predict the next statement of this code snippet:
 <s> if ( ST -> hasVInstructions ( ) ) return <NUM_LIT> ;"
LLVM,RISCV,4214,"Predict the next statement of this code snippet:
 <s> if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ;"
LLVM,RISCV,4215,"Predict the next statement of this code snippet:
 <s> if ( ! ST -> hasVInstructions ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ;"
LLVM,RISCV,4216,"Predict the next statement of this code snippet:
 <s> if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ;"
LLVM,RISCV,4217,"Predict the next statement of this code snippet:
 <s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ;"
LLVM,RISCV,4218,"Predict the next statement of this code snippet:
 <s> switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add : case RecurKind :: FAdd : case RecurKind :: And : case RecurKind :: Or : case RecurKind :: Xor : case RecurKind :: SMin : case RecurKind :: SMax : case RecurKind :: UMin : case RecurKind :: UMax : case RecurKind :: FMin : case RecurKind :: FMax : return true ; default : return false ; }"
LLVM,RISCV,4219,"Predict the next statement of this code snippet:
 <s> if ( ! VF . isScalable ( ) ) return true ; Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( ! TLI -> isLegalElementTypeForRVV ( Ty ) ) return false ; switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add : case RecurKind :: FAdd : case RecurKind :: And : case RecurKind :: Or : case RecurKind :: Xor : case RecurKind :: SMin : case RecurKind :: SMax : case RecurKind :: UMin : case RecurKind :: UMax : case RecurKind :: FMin : case RecurKind :: FMax : return true ; default :"
LLVM,RISCV,4220,"Predict the next statement of this code snippet:
 <s> return ST -> hasVInstructions ( ) ;"
LLVM,RISCV,4221,"Predict the next statement of this code snippet:
 <s> bool supportsScalableVectors ( ) const {"
LLVM,RISCV,4222,"Predict the next statement of this code snippet:
 <s> int <ISA_LIT>TTIImpl :: getIntImmCost ( <STR_LIT> IID , unsigned Idx , const APInt & Imm , Type * Ty ) {"
LLVM,RISCV,4223,"Predict the next statement of this code snippet:
 <s> return ST -> hasStdExtV ( ) ? ST -> getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ;"
LLVM,RISCV,4224,"Predict the next statement of this code snippet:
 <s> if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ;"
LLVM,RISCV,4225,"Predict the next statement of this code snippet:
 <s> } if ( VT . isFloatingPoint ( ) && ! TLI -> isOperationLegalOrCustom ( ISD , VT ) ) return true ; return false ; } ; auto IsHardwareLoopIntrinsic = [ ] ( Instruction & I ) { if ( auto * Call = dyn_cast < IntrinsicInst > ( & I ) ) { switch ( Call -> getIntrinsicID ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } return false ; } ; bool hasInnerHardwareLoop = false ; auto ScanLoop = [ & ] ( Loop * L ) { for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : BB -> instructionsWithoutDebug ( ) ) { hasInnerHardwareLoop |= IsHardwareLoopIntrinsic ( I ) ; if ( MaybeCall ( I ) ) { return false ; } } } return true ; } ; for ( auto Inner : * L ) if ( ! ScanLoop ( Inner ) ) return false ; if ( ! ScanLoop ( L ) ) return false ;"
LLVM,RISCV,4226,"Predict the next statement of this code snippet:
 <s> L -> getExitingBlocks ( ExitingBlocks ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; }"
LLVM,RISCV,4227,"Predict the next statement of this code snippet:
 <s> bool UseDefaultPreferences = true ; if ( ST -> getTuneCPU ( ) . contains ( <STR_LIT> ) || ST -> getTuneCPU ( ) . contains ( <STR_LIT> ) || ST -> getTuneCPU ( ) . contains ( <STR_LIT> ) || ST -> getTuneCPU ( ) . contains ( <STR_LIT> ) ) UseDefaultPreferences = false ; if ( UseDefaultPreferences ) return BasicTTIImplBase :: getUnrollingPreferences ( L , SE , UP , ORE ) ; UP . UpperBound = true ; UP . OptSizeThreshold = <NUM_LIT> ; UP . PartialOptSizeThreshold = <NUM_LIT> ; if ( L -> getHeader ( ) -> getParent ( ) -> hasOptSize ( ) ) return ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost = <NUM_LIT> ;"
LLVM,RISCV,4228,"Predict the next statement of this code snippet:
 <s> unsigned getMinVectorRegisterBitWidth ( ) const { return ST -> hasVInstructions ( ) ? ST -> getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ;"
LLVM,RISCV,4229,"Predict the next statement of this code snippet:
 <s> return TypeSize :: getFixed ( ST -> getXLen ( ) ) ; case TargetTransformInfo :: RGK_FixedWidthVector : return TypeSize :: getFixed ( ST -> hasVInstructions ( ) ? ST -> getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ) ; case TargetTransformInfo :: RGK_ScalableVector : return TypeSize :: getScalable ( ST -> hasVInstructions ( ) ? <STR_LIT> : <NUM_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,4230,"Predict the next statement of this code snippet:
 <s> case TargetTransformInfo :: RGK_ScalableVector : return TypeSize :: getScalable ( ST -> hasVInstructions ( ) ? <STR_LIT> : <NUM_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,RISCV,4231,"Predict the next statement of this code snippet:
 <s> int <ISA_LIT>TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) && <STR_LIT> ) ; if ( Imm == <NUM_LIT> ) return TTI :: TCC_Free ; const DataLayout & DL = getDataLayout ( ) ;"
LLVM,RISCV,4232,"Predict the next statement of this code snippet:
 <s> case Instruction :: Or : case Instruction :: Xor : case Instruction :: Mul : Takes12BitImm = true ; break ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : Takes12BitImm = true ; ImmArgIdx = <NUM_LIT> ; break ; default : break ; } if ( Takes12BitImm ) {"
LLVM,RISCV,4233,"Predict the next statement of this code snippet:
 <s> int <ISA_LIT>TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { assert ( Ty -> isIntegerTy ( ) && <STR_LIT> ) ; if ( Imm == <NUM_LIT> ) return TTI :: TCC_Free ; bool Takes12BitImm = false ; unsigned ImmArgIdx = ~ <NUM_LIT> ; switch ( Opcode ) { case Instruction :: GetElementPtr : return TTI :: TCC_Free ; case Instruction :: Add :"
LLVM,RISCV,4234,"Predict the next statement of this code snippet:
 <s> int <ISA_LIT>TTIImpl :: getIntImmCostIntrin ( <STR_LIT> IID , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { return TTI :: TCC_Free ;"
LLVM,RISCV,4235,"Predict the next statement of this code snippet:
 <s> BasicBlock * BB = L -> getHeader ( ) ; while ( BB ) { BasicBlock * Next = BB -> getSingleSuccessor ( ) ; for ( auto & I : BB -> instructionsWithoutDebug ( ) ) { InstrCount ++ ; const <ISA_LIT>TargetLowering * TLI = getTLI ( ) ; unsigned ISD = TLI -> InstructionOpcodeToISD ( I . getOpcode ( ) ) ; EVT VT = TLI -> getValueType ( DL , I . getType ( ) , true ) ; if ( TLI -> getOperationAction ( ISD , VT ) == TargetLowering :: LibCall ) { return false ; } if ( auto * Call = dyn_cast < CallInst > ( & I ) ) { if ( isa < IntrinsicInst > ( Call ) ) { if ( ! isLoweredToCall ( Call -> getCalledFunction ( ) ) ) { continue ; } } return false ; } if ( auto * Branch = dyn_cast < BranchInst > ( & I ) ) { if ( Branch -> isUnconditional ( ) || L -> isLoopLatch ( BB ) ) { InstrCount -- ; continue ; }"
LLVM,RISCV,4236,"Predict the next statement of this code snippet:
 <s> if ( ! isLoweredToCall ( Call -> getCalledFunction ( ) ) ) { continue ; } } return false ; } if ( auto * Branch = dyn_cast < BranchInst > ( & I ) ) { if ( Branch -> isUnconditional ( ) || L -> isLoopLatch ( BB ) ) { InstrCount -- ; continue ; } else if ( auto * Cond = dyn_cast < IntrinsicInst > ( Branch -> getCondition ( ) ) ) { if ( Cond -> getIntrinsicID ( ) == <STR_LIT> ) { HasInnerHardwareLoop = true ; Next = Branch -> getSuccessor ( <NUM_LIT> ) ; InstrCount = <NUM_LIT> ; continue ; } } } if ( I . isTerminator ( ) ) return false ; if ( VT . isFloatingPoint ( ) && ! TLI -> isOperationLegalOrCustom ( ISD , VT ) ) return false ;"
LLVM,RISCV,4237,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TTIImpl :: shouldFavorPostInc ( ) const { return ST -> hasExtXCoreVMem ( ) ;"
LLVM,RISCV,4238,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TTIImpl :: shouldFavorPostInc ( ) const { return ST -> hasExtXCoreVMem ( ) ;"
LLVM,RISCV,4239,"Predict the next statement of this code snippet:
 <s> unsigned ImmArgIdx = ~ <NUM_LIT> ; switch ( Opcode ) { case Instruction :: GetElementPtr : return TTI :: TCC_Free ; case Instruction :: Add : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: Mul : Takes12BitImm = true ; break ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : Takes12BitImm = true ; ImmArgIdx = <NUM_LIT> ; break ; default : break ; } if ( Takes12BitImm ) { if ( Instruction :: isCommutative ( Opcode ) || Idx == ImmArgIdx ) { if ( Imm . getMinSignedBits ( ) <= <NUM_LIT> && getTLI ( ) -> isLegalAddImmediate ( Imm . getSExtValue ( ) ) ) { return TTI :: TCC_Free ; } } return getIntImmCost ( Imm , Ty ) ; }"
LLVM,RISCV,4240,"Predict the next statement of this code snippet:
 <s> int <ISA_LIT>TTIImpl :: getIntImmCostIntrin ( <STR_LIT> IID , unsigned Idx , const APInt & Imm , Type * Ty ) { return TTI :: TCC_Free ;"
LLVM,RISCV,4241,"Predict the next statement of this code snippet:
 <s> if ( Size . isScalable ( ) && ST -> hasVInstructions ( ) ) return divideCeil ( Size . getKnownMinValue ( ) , <STR_LIT> ) ; if ( ST -> useRVVForFixedLengthVectors ( ) ) return divideCeil ( Size , ST -> getMinRVVVectorSizeInBits ( ) ) ;"
LLVM,RISCV,4242,"Predict the next statement of this code snippet:
 <s> TypeSize Size = Ty -> getPrimitiveSizeInBits ( ) ; if ( Ty -> isVectorTy ( ) ) {"
LLVM,RISCV,4243,"Predict the next statement of this code snippet:
 <s> if ( L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * > Operands ( I . operand_values ( ) ) ; Cost += getUserCost ( & I , Operands , TargetTransformInfo :: TCK_SizeAndLatency ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ;"
LLVM,RISCV,4244,"Predict the next statement of this code snippet:
 <s> InstructionCost <ISA_LIT>TTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * VTy , Optional < FastMathFlags > FMF , TTI :: TargetCostKind CostKind ) { if ( ! isa < FixedVectorType > ( VTy ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; if ( VTy -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; if ( ! ST -> useRVVForFixedLengthVectors ( ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; if ( VTy -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ;"
LLVM,RISCV,4245,"Predict the next statement of this code snippet:
 <s> if ( VTy -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; if ( ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ;"
LLVM,RISCV,4246,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: abs ( PowDiff ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( std :: abs ( PowDiff ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( Src -> isIntOrIntVectorTy ( ) ) return <NUM_LIT> ; return std :: abs ( PowDiff ) ; } }"
LLVM,RISCV,4247,"Predict the next statement of this code snippet:
 <s> if ( ! isa < FixedVectorType > ( Ty ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; if ( ! ST -> useRVVForFixedLengthVectors ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; if ( Ty -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; InstructionCost BaseCost = <NUM_LIT> ;"
LLVM,RISCV,4248,"Predict the next statement of this code snippet:
 <s> if ( Kind == TTI :: SK_Splice && isa < ScalableVectorType > ( Tp ) ) return getSpliceCost ( Tp , Index ) ; return BaseT :: getShuffleCost ( Kind , Tp , Mask , Index , SubTp ) ;"
LLVM,RISCV,4249,"Predict the next statement of this code snippet:
 <s> case TargetTransformInfo :: RGK_FixedWidthVector : return TypeSize :: getFixed ( ST -> hasStdExtV ( ) ? ST -> getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ) ; case TargetTransformInfo :: RGK_ScalableVector : return TypeSize :: getScalable ( ST -> hasStdExtV ( ) ? ST -> getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ) ;"
LLVM,RISCV,4250,"Predict the next statement of this code snippet:
 <s> case TargetTransformInfo :: RGK_Scalar : return TypeSize :: getFixed ( ST -> getXLen ( ) ) ; case TargetTransformInfo :: RGK_FixedWidthVector :"
LLVM,RISCV,4251,"Predict the next statement of this code snippet:
 <s> if ( ! ST -> hasStdExtV ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ;"
LLVM,RISCV,4252,"Predict the next statement of this code snippet:
 <s> if ( ! ST -> hasStdExtV ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ;"
LLVM,RISCV,4253,"Predict the next statement of this code snippet:
 <s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ;"
LLVM,RISCV,4254,"Predict the next statement of this code snippet:
 <s> if ( ! VF . isScalable ( ) ) return true ; Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( ! isLegalElementTypeForRVV ( Ty ) ) return false ; switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add :"
LLVM,RISCV,4255,"Predict the next statement of this code snippet:
 <s> case Instruction :: Mul : Takes12BitImm = true ; break ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : Takes12BitImm = true ; ImmArgIdx = <NUM_LIT> ; break ; default : break ; } if ( Takes12BitImm ) { if ( Instruction :: isCommutative ( Opcode ) || Idx == ImmArgIdx ) { if ( getTLI ( ) -> isLegalAddImmediate ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; }"
LLVM,RISCV,4256,"Predict the next statement of this code snippet:
 <s> if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getELEN ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return TLI -> isLegalElementTypeForRVV ( DataType -> getScalarType ( ) ) ;"
LLVM,RISCV,4257,"Predict the next statement of this code snippet:
 <s> if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ;"
LLVM,RISCV,4258,"Predict the next statement of this code snippet:
 <s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getELEN ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ;"
LLVM,RISCV,4259,"Predict the next statement of this code snippet:
 <s> if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ;"
LLVM,RISCV,4260,"Predict the next statement of this code snippet:
 <s> bool isLegalToVectorizeReduction ( const RecurrenceDescriptor & RdxDesc , ElementCount VF ) const { if ( ! VF . isScalable ( ) ) return true ; Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( ! TLI -> isLegalElementTypeForRVV ( Ty ) ) return false ; switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add : case RecurKind :: FAdd : case RecurKind :: And : case RecurKind :: Or : case RecurKind :: Xor : case RecurKind :: SMin : case RecurKind :: SMax : case RecurKind :: UMin : case RecurKind :: UMax : case RecurKind :: FMin : case RecurKind :: FMax : return true ; default :"
LLVM,RISCV,4261,"Predict the next statement of this code snippet:
 <s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ;"
LLVM,RISCV,4262,"Predict the next statement of this code snippet:
 <s> if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( DataTy , Align ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( DataTy , Align ( Alignment ) ) ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; if ( ! isa < FixedVectorType > ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VTy = cast < FixedVectorType > ( DataTy ) ; unsigned NumLoads = VTy -> getNumElements ( ) ;"
LLVM,RISCV,4263,"Predict the next statement of this code snippet:
 <s> InstructionCost <ISA_LIT>TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) && <STR_LIT> ) ; if ( Imm == <NUM_LIT> ) return TTI :: TCC_Free ;"
LLVM,RISCV,4264,"Predict the next statement of this code snippet:
 <s> case Instruction :: Add : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: Mul : Takes12BitImm = true ; break ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : Takes12BitImm = true ; ImmArgIdx = <NUM_LIT> ; break ; default : break ; } if ( Takes12BitImm ) { if ( Instruction :: isCommutative ( Opcode ) || Idx == ImmArgIdx ) { if ( Imm . getMinSignedBits ( ) <= <NUM_LIT> && getTLI ( ) -> isLegalAddImmediate ( Imm . getSExtValue ( ) ) ) { return TTI :: TCC_Free ; } }"
LLVM,RISCV,4265,"Predict the next statement of this code snippet:
 <s> unsigned MaxVectorSizeInBits = ST -> getMaxRVVVectorSizeInBits ( ) ; if ( ST -> hasStdExtV ( ) && MaxVectorSizeInBits != <NUM_LIT> ) return MaxVectorSizeInBits / <STR_LIT> ; return BaseT :: getMaxVScale ( ) ;"
LLVM,RISCV,4266,"Predict the next statement of this code snippet:
 <s> assert ( isPowerOf2_32 ( TyWidth ) && <STR_LIT> ) ;"
LLVM,RISCV,4267,"Predict the next statement of this code snippet:
 <s> TargetTransformInfo :: PopcntSupportKind <ISA_LIT>TTIImpl :: getPopcntSupport ( unsigned TyWidth ) {"
LLVM,RISCV,4268,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget * getST ( ) const {"
LLVM,RISCV,4269,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget * getST ( ) const { return ST ;"
LLVM,RISCV,4270,"Predict the next statement of this code snippet:
 <s> return TLI ;"
LLVM,RISCV,4271,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {"
LLVM,RISCV,4272,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {"
LLVM,RISCV,4273,"Predict the next statement of this code snippet:
 <s> default : return false ; case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,0,"Predict the next statement of this code snippet:
 <s> std :: tie ( NewFunc , ImplicitOffset ) = addOffsetArgumentToFunction ( M , Caller ) ; } if ( ! CalleeWithImplicitParam ) { CallToOld -> replaceAllUsesWith ( ImplicitOffset ) ; } else { llvm :: SmallVector < Value * , <NUM_LIT> > ImplicitOffsets ; for ( Use & U : CallToOld -> args ( ) ) { ImplicitOffsets . push_back ( U ) ; } ImplicitOffsets . push_back ( ImplicitOffset ) ; auto NewCaller = CallInst :: Create ( CalleeWithImplicitParam -> getFunctionType ( ) , CalleeWithImplicitParam , ImplicitOffsets , Twine ( ) , CallToOld ) ; NewCaller -> setTailCallKind ( CallToOld -> getTailCallKind ( ) ) ; NewCaller -> copyMetadata ( * CallToOld ) ; CallToOld -> replaceAllUsesWith ( NewCaller ) ; if ( CallToOld -> hasName ( ) ) { NewCaller -> takeName ( CallToOld ) ; } } CallToOld -> eraseFromParent ( ) ; if ( ! AlreadyProcessed ) { addImplicitParameterToCallers ( M , Caller , NewFunc ) ; Caller -> dropAllReferences ( ) ; Caller -> eraseFromParent ( ) ;"
LLVM,NVPTX,1,"Predict the next statement of this code snippet:
 <s> assert ( ! FuncTy -> isVarArg ( ) && <STR_LIT> ) ; FunctionType * NewFuncTy = FunctionType :: get ( FuncTy -> getReturnType ( ) , Arguments , FuncTy -> isVarArg ( ) ) ; Function * NewFunc = Function :: Create ( NewFuncTy , Func -> getLinkage ( ) , Func -> getAddressSpace ( ) ) ; M . getFunctionList ( ) . insertAfter ( Func -> getIterator ( ) , NewFunc ) ; if ( KeepOriginal ) { NewFunc -> setName ( Func -> getName ( ) + <STR_LIT> ) ; ValueToValueMapTy VMap ; for ( Function :: arg_iterator FuncArg = Func -> arg_begin ( ) , FuncEnd = Func -> arg_end ( ) , NewFuncArg = NewFunc -> arg_begin ( ) ; FuncArg != FuncEnd ; ++ FuncArg , ++ NewFuncArg ) { VMap [ FuncArg ] = NewFuncArg ; } SmallVector < ReturnInst * , <NUM_LIT> > Returns ; CloneFunctionInto ( NewFunc , Func , VMap , CloneFunctionChangeType :: GlobalChanges , Returns ) ; } else { NewFunc -> copyAttributesFrom ( Func ) ; NewFunc -> setComdat ( Func -> getComdat ( ) ) ; NewFunc -> setAttributes ( NAttrs ) ; NewFunc -> takeName ( Func ) ; NewFunc -> getBasicBlockList ( ) . splice ( NewFunc -> begin ( ) , Func -> getBasicBlockList ( ) ) ; for ( Function :: arg_iterator FuncArg = Func -> arg_begin ( ) , FuncEnd = Func -> arg_end ( ) , NewFuncArg = NewFunc -> arg_begin ( ) ; FuncArg != FuncEnd ; ++ FuncArg , ++ NewFuncArg ) { FuncArg -> replaceAllUsesWith ( NewFuncArg ) ; } SmallVector < std :: pair < unsigned , MDNode * > , <NUM_LIT> > MDs ; Func -> getAllMetadata ( MDs ) ; for ( auto MD : MDs ) NewFunc -> addMetadata ( MD . first , * MD . second ) ; }"
LLVM,NVPTX,2,"Predict the next statement of this code snippet:
 <s> auto HasUseOtherThanLLVMUsed = [ & Used ] ( GlobalValue * GV ) { if ( GV -> use_empty ( ) ) return false ; return ! GV -> hasOneUse ( ) || ! Used . count ( GV ) ; } ; llvm :: DenseMap < Function * , MDNode * > NvvmEntryPointMetadata ; for ( auto MetadataNode : NvvmMetadata -> operands ( ) ) { if ( MetadataNode -> getNumOperands ( ) != <NUM_LIT> ) continue ; auto Type = dyn_cast < MDString > ( MetadataNode -> getOperand ( <NUM_LIT> ) ) ; if ( ! Type || Type -> getString ( ) != <STR_LIT> ) continue ; const auto & FuncOperand = MetadataNode -> getOperand ( <NUM_LIT> ) ; if ( ! FuncOperand ) continue ; auto FuncConstant = dyn_cast < ConstantAsMetadata > ( FuncOperand ) ; if ( ! FuncConstant ) continue ; auto Func = dyn_cast < Function > ( FuncConstant -> getValue ( ) ) ; if ( ! Func ) continue ; assert ( ! HasUseOtherThanLLVMUsed ( Func ) && <STR_LIT> ) ; NvvmEntryPointMetadata [ Func ] = MetadataNode ; } return NvvmEntryPointMetadata ;"
LLVM,NVPTX,3,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,4,"Predict the next statement of this code snippet:
 <s> GlobalOffset ( ) : ModulePass ( ID ) {"
LLVM,NVPTX,5,"Predict the next statement of this code snippet:
 <s> GlobalOffset ( ) : ModulePass ( ID ) {"
LLVM,NVPTX,6,"Predict the next statement of this code snippet:
 <s> IRBuilder < > Builder ( EntryBlock , EntryBlock -> getFirstInsertionPt ( ) ) ; Type * ImplicitOffsetType = ArrayType :: get ( Type :: getInt32Ty ( M . getContext ( ) ) , <NUM_LIT> ) ; AllocaInst * ImplicitOffset = Builder . CreateAlloca ( ImplicitOffsetType ) ; uint64_t AllocByteSize = ImplicitOffset -> getAllocationSizeInBits ( M . getDataLayout ( ) ) . getValue ( ) / <NUM_LIT> ; CallInst * MemsetCall = Builder . CreateMemSet ( ImplicitOffset , Builder . getInt8 ( <NUM_LIT> ) , AllocByteSize , ImplicitOffset -> getAlign ( ) ) ; MemsetCall -> addParamAttr ( <NUM_LIT> , Attribute :: NonNull ) ; MemsetCall -> addDereferenceableParamAttr ( <NUM_LIT> , AllocByteSize ) ;"
LLVM,NVPTX,7,"Predict the next statement of this code snippet:
 <s> assert ( ( ! ImplicitOffsetIntrinsic || ImplicitOffsetIntrinsic -> getReturnType ( ) == ImplicitOffsetPtrType ) && <STR_LIT> <STR_LIT> ) ; EntryPointMetadata = getEntryPointMetadata ( M ) ; addImplicitParameterToCallers ( M , ImplicitOffsetIntrinsic , nullptr ) ; assert ( ImplicitOffsetIntrinsic -> use_empty ( ) && <STR_LIT> ) ;"
LLVM,NVPTX,8,"Predict the next statement of this code snippet:
 <s> if ( Type -> getString ( ) != <STR_LIT> ) continue ; const MDOperand & FuncOperand = MetadataNode -> getOperand ( <NUM_LIT> ) ; auto FuncConstant = dyn_cast < ConstantAsMetadata > ( FuncOperand ) ; if ( ! FuncConstant ) continue ; auto Func = dyn_cast < Function > ( FuncConstant -> getValue ( ) ) ; if ( ! Func ) continue ; auto NewFunc = this -> ProcessFunction ( M , Func ) ; if ( NewFunc ) { Changed = true ; MetadataNode -> replaceOperandWith ( <NUM_LIT> , llvm :: ConstantAsMetadata :: get ( NewFunc ) ) ; } } return Changed ;"
LLVM,NVPTX,9,"Predict the next statement of this code snippet:
 <s> virtual llvm :: StringRef getPassName ( ) const { return <STR_LIT> ;"
LLVM,NVPTX,10,"Predict the next statement of this code snippet:
 <s> LocalAccessorToSharedMemory ( ) : ModulePass ( ID ) {"
LLVM,NVPTX,11,"Predict the next statement of this code snippet:
 <s> LocalAccessorToSharedMemory ( ) : ModulePass ( ID ) {"
LLVM,NVPTX,12,"Predict the next statement of this code snippet:
 <s> if ( ! FuncConstant ) continue ; auto Func = dyn_cast < Function > ( FuncConstant -> getValue ( ) ) ; if ( ! Func ) continue ; auto NewFunc = this -> ProcessFunction ( M , Func ) ; if ( NewFunc ) { Changed = true ; MetadataNode -> replaceOperandWith ( <NUM_LIT> , llvm :: ConstantAsMetadata :: get ( NewFunc ) ) ; } }"
LLVM,NVPTX,13,"Predict the next statement of this code snippet:
 <s> const MDOperand & FuncOperand = MetadataNode -> getOperand ( <NUM_LIT> ) ; if ( ! FuncOperand ) continue ; auto FuncConstant = dyn_cast < ConstantAsMetadata > ( FuncOperand ) ; if ( ! FuncConstant ) continue ; auto Func = dyn_cast < Function > ( FuncConstant -> getValue ( ) ) ; if ( ! Func ) continue ; auto NewFunc = this -> ProcessFunction ( M , Func ) ; if ( NewFunc ) { Changed = true ; MetadataNode -> replaceOperandWith ( <NUM_LIT> , llvm :: ConstantAsMetadata :: get ( NewFunc ) ) ; } }"
LLVM,NVPTX,14,"Predict the next statement of this code snippet:
 <s> SmallVector < std :: string * , <NUM_LIT> > :: iterator Current = Pool . begin ( ) ; while ( Current != Pool . end ( ) ) {"
LLVM,NVPTX,15,"Predict the next statement of this code snippet:
 <s> while ( Current != Pool . end ( ) ) { delete * Current ; ++ Current ; }"
LLVM,NVPTX,16,"Predict the next statement of this code snippet:
 <s> std :: string * Str = new std :: string ( S ) ;"
LLVM,NVPTX,17,"Predict the next statement of this code snippet:
 <s> ManagedStringPool ( ) {"
LLVM,NVPTX,18,"Predict the next statement of this code snippet:
 <s> ManagedStringPool ( ) {"
LLVM,NVPTX,19,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,20,"Predict the next statement of this code snippet:
 <s> NVVMIntrRangePass ( unsigned SmVersion ) : SmVersion ( SmVersion ) {"
LLVM,NVPTX,21,"Predict the next statement of this code snippet:
 <s> NVVMIntrRangePass ( unsigned SmVersion ) : SmVersion ( SmVersion ) {"
LLVM,NVPTX,22,"Predict the next statement of this code snippet:
 <s> NVVMReflectPass ( unsigned SmVersion ) : SmVersion ( SmVersion ) {"
LLVM,NVPTX,23,"Predict the next statement of this code snippet:
 <s> NVVMReflectPass ( unsigned SmVersion ) : SmVersion ( SmVersion ) {"
LLVM,NVPTX,24,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>AllocaHoisting ;"
LLVM,NVPTX,25,"Predict the next statement of this code snippet:
 <s> AU . addPreserved < StackProtector > ( ) ;"
LLVM,NVPTX,26,"Predict the next statement of this code snippet:
 <s> AU . addPreserved < StackProtector > ( ) ;"
LLVM,NVPTX,27,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,28,"Predict the next statement of this code snippet:
 <s> AU . addRequired < DataLayout > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ;"
LLVM,NVPTX,29,"Predict the next statement of this code snippet:
 <s> virtual const char * getPassName ( ) const {"
LLVM,NVPTX,30,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,31,"Predict the next statement of this code snippet:
 <s> for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) { for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) { AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ; if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) { allocaInst -> moveBefore ( firstTerminatorInst ) ; functionModified = true ; }"
LLVM,NVPTX,32,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DataLayoutPass > ( ) ;"
LLVM,NVPTX,33,"Predict the next statement of this code snippet:
 <s> bool functionModified = false ; Function :: iterator I = function . begin ( ) ; TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ; for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) { for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) { AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ; if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) {"
LLVM,NVPTX,34,"Predict the next statement of this code snippet:
 <s> AU . addPreserved < MachineFunctionAnalysis > ( ) ;"
LLVM,NVPTX,35,"Predict the next statement of this code snippet:
 <s> AU . addRequired < DataLayoutPass > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ;"
LLVM,NVPTX,36,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetData > ( ) ;"
LLVM,NVPTX,37,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {"
LLVM,NVPTX,38,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DataLayoutPass > ( ) ; AU . addPreserved ( <STR_LIT> ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ;"
LLVM,NVPTX,39,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AllocaHoisting ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,40,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AllocaHoisting ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,41,"Predict the next statement of this code snippet:
 <s> break ; } if ( Cexpr -> getOpcode ( ) == Instruction :: PtrToInt ) { Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else if ( ETy == Type :: getInt64Ty ( CPV -> getContext ( ) ) ) { if ( const ConstantInt * constInt = dyn_cast < ConstantInt > ( CPV ) ) { long long int64 = ( long long ) ( constInt -> getZExtValue ( ) ) ; ptr = ( unsigned char * ) & int64 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { if ( const ConstantInt * constInt = dyn_cast < ConstantInt > ( ConstantFoldConstantExpression ( Cexpr , TD ) ) ) { long long int64 = ( long long ) ( constInt -> getZExtValue ( ) ) ; ptr = ( unsigned char * ) & int64 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } if ( Cexpr -> getOpcode ( ) == Instruction :: PtrToInt ) { Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; } case Type :: FloatTyID : case Type :: DoubleTyID : { const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ; const Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ptr = ( unsigned char * ) & float32 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) {"
LLVM,NVPTX,42,"Predict the next statement of this code snippet:
 <s> if ( Pty -> getAddressSpace ( ) != llvm :: ADDRESS_SPACE_SHARED ) return false ; const Function * oneFunc = <NUM_LIT> ; bool flag = usedInOneFunc ( gv , oneFunc ) ; if ( flag == false ) return false ; if ( ! oneFunc ) return false ; f = oneFunc ;"
LLVM,NVPTX,43,"Predict the next statement of this code snippet:
 <s> i = <NUM_LIT> ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; delete [ ] gv_array ; return ret ;"
LLVM,NVPTX,44,"Predict the next statement of this code snippet:
 <s> emitGlobals ( M ) ; GlobalsEmitted = true ; } Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = <NUM_LIT> ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ;"
LLVM,NVPTX,45,"Predict the next statement of this code snippet:
 <s> OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; } if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; GlobalsEmitted = false ;"
LLVM,NVPTX,46,"Predict the next statement of this code snippet:
 <s> printReturnValStr ( F , O ) ; O << * Mang -> getSymbol ( F ) << <STR_LIT> ; emitFunctionParamList ( F , O ) ;"
LLVM,NVPTX,47,"Predict the next statement of this code snippet:
 <s> printReturnValStr ( F , O ) ; O << * Mang -> getSymbol ( F ) << <STR_LIT> ;"
LLVM,NVPTX,48,"Predict the next statement of this code snippet:
 <s> if ( F -> getIntrinsicID ( ) ) continue ; emitDeclaration ( F , O ) ; continue ; } for ( Value :: const_use_iterator iter = F -> use_begin ( ) , iterEnd = F -> use_end ( ) ; iter != iterEnd ; ++ iter ) { if ( const Constant * C = dyn_cast < Constant > ( * iter ) ) { if ( usedInGlobalVarDef ( C ) ) { emitDeclaration ( F , O ) ; break ; } if ( useFuncSeen ( C , seenMap ) ) { emitDeclaration ( F , O ) ; break ; } } if ( ! isa < Instruction > ( * iter ) ) continue ; const Instruction * instr = cast < Instruction > ( * iter ) ; const BasicBlock * bb = instr -> getParent ( ) ; if ( ! bb ) continue ; const Function * caller = bb -> getParent ( ) ; if ( ! caller ) continue ; if ( seenMap . find ( caller ) != seenMap . end ( ) ) { emitDeclaration ( F , O ) ;"
LLVM,NVPTX,49,"Predict the next statement of this code snippet:
 <s> bool first = true ; bool isKernelFunc = llvm :: isKernelFunction ( * F ) ; bool isABI = ( nvptxSubtarget . getSmVersion ( ) >= <NUM_LIT> ) ; MVT thePointerTy = TLI -> getPointerTy ( ) ; O << <STR_LIT> ; for ( I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , paramIndex ++ ) { Type * Ty = I -> getType ( ) ; if ( ! first ) O << <STR_LIT> ; first = false ; if ( llvm :: isSampler ( * I ) || llvm :: isImage ( * I ) ) { if ( llvm :: isImage ( * I ) ) { std :: string sname = I -> getName ( ) ; if ( llvm :: isImageWriteOnly ( * I ) ) O << <STR_LIT> << * Mang -> getSymbol ( F ) << <STR_LIT> << paramIndex ; else O << <STR_LIT> << * Mang -> getSymbol ( F ) << <STR_LIT> << paramIndex ; } else O << <STR_LIT> << * Mang -> getSymbol ( F ) << <STR_LIT> << paramIndex ; continue ; } if ( PAL . hasAttribute ( paramIndex + <NUM_LIT> , Attribute :: ByVal ) == false ) { if ( Ty -> isVectorTy ( ) ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( Ty ) ; unsigned sz = TD -> getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST :"
LLVM,NVPTX,50,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) emitLineNumberAsDotLoc ( * MI ) ; MCInst Inst ; lowerToMCInst ( MI , Inst ) ;"
LLVM,NVPTX,51,"Predict the next statement of this code snippet:
 <s> assert ( ( ! Scope || Scope . isScope ( ) ) && <STR_LIT> ) ; if ( ! Scope ) return ; StringRef fileName ( Scope . getFilename ( ) ) ; StringRef dirName ( Scope . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) { sys :: path :: append ( FullPathName , fileName ) ; fileName = FullPathName . str ( ) ; } if ( filenameMap . find ( fileName . str ( ) ) == filenameMap . end ( ) ) return ; if ( llvm :: InterleaveSrcInPtx ) this -> emitSrcInText ( fileName . str ( ) , curLoc . getLine ( ) ) ; std :: stringstream temp ; temp << <STR_LIT> << filenameMap [ fileName . str ( ) ] << <STR_LIT> << curLoc . getLine ( ) << <STR_LIT> << curLoc . getCol ( ) ;"
LLVM,NVPTX,52,"Predict the next statement of this code snippet:
 <s> if ( curLoc . isUnknown ( ) ) return ; const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const LLVMContext & ctx = MF -> getFunction ( ) -> getContext ( ) ; DIScope Scope ( curLoc . getScope ( ctx ) ) ; assert ( ( ! Scope || Scope . isScope ( ) ) && <STR_LIT> ) ; if ( ! Scope ) return ; StringRef fileName ( Scope . getFilename ( ) ) ; StringRef dirName ( Scope . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) {"
LLVM,NVPTX,53,"Predict the next statement of this code snippet:
 <s> msg . append ( <STR_LIT> ) ; msg . append ( <STR_LIT> ) ; if ( V -> hasName ( ) ) msg . append ( V -> getName ( ) . str ( ) ) ; msg . append ( <STR_LIT> ) ; llvm_unreachable ( msg . c_str ( ) ) ; }"
LLVM,NVPTX,54,"Predict the next statement of this code snippet:
 <s> O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * Mang -> getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> << * Mang -> getSymbol ( GVar ) << <STR_LIT> ; if ( ElementSize ) { O << itostr ( ElementSize ) ; } O << <STR_LIT> ;"
LLVM,NVPTX,55,"Predict the next statement of this code snippet:
 <s> getVirtualRegisterName ( vr , isVec , O ) ;"
LLVM,NVPTX,56,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitVirtualRegister ( unsigned int vr , bool isVec , raw_ostream & O ) {"
LLVM,NVPTX,57,"Predict the next statement of this code snippet:
 <s> unsigned int numE = VTy -> getNumElements ( ) ; unsigned int alignE = TD -> getPrefTypeAlignment ( ETy ) ; if ( numE == <NUM_LIT> ) return <NUM_LIT> * alignE ; else return numE * alignE ; } const StructType * STy = dyn_cast < StructType > ( Ty ) ; if ( STy ) { unsigned int alignStruct = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; i ++ ) { Type * ETy = STy -> getElementType ( i ) ; unsigned int align = getOpenCLAlignment ( TD , ETy ) ; if ( align > alignStruct ) alignStruct = align ; } return alignStruct ; } const FunctionType * FTy = dyn_cast < FunctionType > ( Ty ) ; if ( FTy ) return TD -> getPointerPrefAlignment ( ) ; return TD -> getPrefTypeAlignment ( Ty ) ;"
LLVM,NVPTX,58,"Predict the next statement of this code snippet:
 <s> case Type :: IntegerTyID : { unsigned NumBits = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( NumBits == <NUM_LIT> ) return <STR_LIT> ; else if ( NumBits <= <NUM_LIT> ) { std :: string name = <STR_LIT> ; return name + utostr ( NumBits ) ; } else { llvm_unreachable ( <STR_LIT> ) ; break ; } break ; } case Type :: FloatTyID : return <STR_LIT> ; case Type :: DoubleTyID : return <STR_LIT> ;"
LLVM,NVPTX,59,"Predict the next statement of this code snippet:
 <s> reader = new LineReader ( filename ) ; } if ( reader -> fileName ( ) != filename ) { delete reader ; reader = new LineReader ( filename ) ; } return reader ;"
LLVM,NVPTX,60,"Predict the next statement of this code snippet:
 <s> } if ( reader -> fileName ( ) != filename ) { delete reader ; reader = new LineReader ( filename ) ; } return reader ;"
LLVM,NVPTX,61,"Predict the next statement of this code snippet:
 <s> Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; return MCOperand :: CreateExpr ( Expr ) ;"
LLVM,NVPTX,62,"Predict the next statement of this code snippet:
 <s> Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ;"
LLVM,NVPTX,63,"Predict the next statement of this code snippet:
 <s> DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; unsigned mapped_vr = regmap [ vr ] ; if ( ! isVec ) { O << get<ISA_LIT>RegClassStr ( RC ) << mapped_vr ; return ; } report_fatal_error ( <STR_LIT> ) ;"
LLVM,NVPTX,64,"Predict the next statement of this code snippet:
 <s> break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , OutContext ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( MO , Mang -> getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_FPImmediate : { const ConstantFP * Cnt = MO . getFPImm ( ) ; APFloat Val = Cnt -> getValueAPF ( ) ; switch ( Cnt -> getType ( ) -> getTypeID ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; break ; case Type :: FloatTyID : MCOp = MCOperand :: CreateExpr ( <ISA_LIT>FloatMCExpr :: CreateConstantFPSingle ( Val , OutContext ) ) ; break ; case Type :: DoubleTyID : MCOp = MCOperand :: CreateExpr ( <ISA_LIT>FloatMCExpr :: CreateConstantFPDouble ( Val , OutContext ) ) ; break ; }"
LLVM,NVPTX,65,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {"
LLVM,NVPTX,66,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ;"
LLVM,NVPTX,67,"Predict the next statement of this code snippet:
 <s> return ; } if ( llvm :: isSurface ( * GVar ) ) { O << <STR_LIT> << llvm :: getSurfaceName ( * GVar ) << <STR_LIT> ; return ; } if ( GVar -> isDeclaration ( ) ) { emitPTXGlobalVariable ( GVar , O ) ; O << <STR_LIT> ; return ; } if ( llvm :: isSampler ( * GVar ) ) { O << <STR_LIT> << llvm :: getSamplerName ( * GVar ) ; const Constant * Initializer = NULL ; if ( GVar -> hasInitializer ( ) ) Initializer = GVar -> getInitializer ( ) ; const ConstantInt * CI = NULL ; if ( Initializer ) CI = dyn_cast < ConstantInt > ( Initializer ) ; if ( CI ) { unsigned sample = CI -> getZExtValue ( ) ; O << <STR_LIT> ; for ( int i = <NUM_LIT> , addr = ( ( sample & __CLK_ADDRESS_MASK ) >> __CLK_ADDRESS_BASE ) ; i < <NUM_LIT> ; i ++ ) { O << <STR_LIT> << i << <STR_LIT> ; switch ( addr ) { case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; } O << <STR_LIT> ; } O << <STR_LIT> ; switch ( ( sample & __CLK_FILTER_MASK ) >> __CLK_FILTER_BASE ) { case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; default : O << <STR_LIT> ; break ; } if ( ! ( ( sample & __CLK_NORMALIZED_MASK ) >> __CLK_NORMALIZED_BASE ) ) { O << <STR_LIT> ; } O << <STR_LIT> ; } O << <STR_LIT> ; return ; } if ( GVar -> hasPrivateLinkage ( ) ) { if ( ! strncmp ( GVar -> getName ( ) . data ( ) , <STR_LIT> , <NUM_LIT> ) ) return ; if ( ! strncmp ( GVar -> getName ( ) . data ( ) , <STR_LIT> , <NUM_LIT> ) ) return ; if ( GVar -> use_empty ( ) ) return ; } const Function * demotedFunc = <NUM_LIT> ; if ( ! processDemoted && canDemoteGlobalVar ( GVar , demotedFunc ) ) { O << <STR_LIT> << GVar -> getName ( ) . str ( ) << <STR_LIT> ; if ( localDecls . find ( demotedFunc ) != localDecls . end ( ) ) localDecls [ demotedFunc ] . push_back ( GVar ) ; else { std :: vector < const GlobalVariable * > temp ;"
LLVM,NVPTX,68,"Predict the next statement of this code snippet:
 <s> const char * p = argName . c_str ( ) ; while ( * p ) { if ( * p == '.' ) O << <STR_LIT> ; else O << * p ; p ++ ; }"
LLVM,NVPTX,69,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printScalarConstant ( const Constant * CPV , raw_ostream & O ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CPV ) ) { O << CI -> getValue ( ) ; return ; } if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ) { printFPConstant ( CFP , O ) ; return ; } if ( isa < ConstantPointerNull > ( CPV ) ) { O << <STR_LIT> ; return ;"
LLVM,NVPTX,70,"Predict the next statement of this code snippet:
 <s> if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CPV ) ) { O << CI -> getValue ( ) ; return ; } if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ) { printFPConstant ( CFP , O ) ; return ; } if ( isa < ConstantPointerNull > ( CPV ) ) { O << <STR_LIT> ; return ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { O << * Mang -> getSymbol ( GVar ) ; return ; } if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { O << * Mang -> getSymbol ( GVar ) ; return ; } else { O << * LowerConstant ( CPV , * this ) ; return ;"
LLVM,NVPTX,71,"Predict the next statement of this code snippet:
 <s> for ( DebugInfoFinder :: iterator I = DbgFinder . compile_unit_begin ( ) , E = DbgFinder . compile_unit_end ( ) ; I != E ; ++ I ) { DICompileUnit DIUnit ( * I ) ; StringRef Filename ( DIUnit . getFilename ( ) ) ; StringRef Dirname ( DIUnit . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName . str ( ) ; } if ( filenameMap . find ( Filename . str ( ) ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename . str ( ) ] = i ; OutStreamer . EmitDwarfFileDirective ( i , <STR_LIT> , Filename . str ( ) ) ; ++ i ; } for ( DebugInfoFinder :: iterator I = DbgFinder . subprogram_begin ( ) , E = DbgFinder . subprogram_end ( ) ; I != E ; ++ I ) { DISubprogram SP ( * I ) ; StringRef Filename ( SP . getFilename ( ) ) ; StringRef Dirname ( SP . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ;"
LLVM,NVPTX,72,"Predict the next statement of this code snippet:
 <s> for ( Value :: const_use_iterator ui = C -> use_begin ( ) , ue = C -> use_end ( ) ; ui != ue ; ++ ui ) { const Constant * C = dyn_cast < Constant > ( * ui ) ; if ( usedInGlobalVarDef ( C ) ) return true ; } return false ;"
LLVM,NVPTX,73,"Predict the next statement of this code snippet:
 <s> if ( oneFunc && ( curFunc != oneFunc ) ) return false ; oneFunc = curFunc ; return true ; } else return false ; } if ( const MDNode * md = dyn_cast < MDNode > ( U ) ) if ( md -> hasName ( ) && ( ( md -> getName ( ) . str ( ) == <STR_LIT> ) || ( md -> getName ( ) . str ( ) == <STR_LIT> ) ) ) return true ; for ( User :: const_use_iterator ui = U -> use_begin ( ) , ue = U -> use_end ( ) ; ui != ue ; ++ ui ) { if ( usedInOneFunc ( * ui , oneFunc ) == false ) return false ;"
LLVM,NVPTX,74,"Predict the next statement of this code snippet:
 <s> if ( useFuncSeen ( cu , seenMap ) ) return true ; } else if ( const Instruction * I = dyn_cast < Instruction > ( * ui ) ) { const BasicBlock * bb = I -> getParent ( ) ; if ( ! bb ) continue ; const Function * caller = bb -> getParent ( ) ; if ( ! caller ) continue ;"
LLVM,NVPTX,75,"Predict the next statement of this code snippet:
 <s> delete reader ;"
LLVM,NVPTX,76,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>AsmPrinter ( ) override { delete reader ;"
LLVM,NVPTX,77,"Predict the next statement of this code snippet:
 <s> unsigned int nSym = <NUM_LIT> ; unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( AP . nvptxSubtarget . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . getSymbol ( GVar ) ; PointerType * PTy = dyn_cast < PointerType > ( GVar -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; O << * Name ; O << <STR_LIT> ; } else { O << * Name ; } } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) { O << * AP . lowerConstant ( Cexpr ) ; } else llvm_unreachable ( <STR_LIT> ) ; nSym ++ ; if ( nSym >= numSymbols ) nextSymbolPos = size + <NUM_LIT> ; else nextSymbolPos = symbolPosInBuffer [ nSym ] ; } else if ( nBytes == <NUM_LIT> ) O << * ( unsigned int * ) ( & buffer [ pos ] ) ; else O << * ( unsigned long long * ) ( & buffer [ pos ] ) ; } }"
LLVM,NVPTX,78,"Predict the next statement of this code snippet:
 <s> if ( numSymbols == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < size ; i ++ ) { if ( i ) O << <STR_LIT> ; O << ( unsigned int ) buffer [ i ] ; } } else { unsigned int pos = <NUM_LIT> ; unsigned int nSym = <NUM_LIT> ; unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( AP . nvptxSubtarget . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . getSymbol ( GVar ) ; PointerType * PTy = dyn_cast < PointerType > ( GVar -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; }"
LLVM,NVPTX,79,"Predict the next statement of this code snippet:
 <s> const Instruction * instr = cast < Instruction > ( U ) ; const BasicBlock * bb = instr -> getParent ( ) ; if ( ! bb ) continue ; const Function * caller = bb -> getParent ( ) ; if ( ! caller ) continue ; if ( seenMap . find ( caller ) != seenMap . end ( ) ) { emitDeclaration ( F , O ) ; break ; } }"
LLVM,NVPTX,80,"Predict the next statement of this code snippet:
 <s> assert ( GVVisiting . size ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Globals . size ( ) ; i != e ; ++ i ) printModuleLevelGV ( Globals [ i ] , OS2 ) ; OS2 << '\n' ;"
LLVM,NVPTX,81,"Predict the next statement of this code snippet:
 <s> case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { if ( MO . getReg ( ) == <STR_LIT> ) O << DEPOTNAME << getFunctionNumber ( ) ; else O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; } else { emitVirtualRegister ( MO . getReg ( ) , false , O ) ; } return ; case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : { const char * symbname = MO . getSymbolName ( ) ; if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; printParamName ( index , O ) ; } else if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; O << * CurrentFnSym << <STR_LIT> << index << <STR_LIT> ; } else O << symbname ; break ; }"
LLVM,NVPTX,82,"Predict the next statement of this code snippet:
 <s> if ( CPV -> getNumOperands ( ) ) for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( const ConstantDataSequential * CDS = dyn_cast < ConstantDataSequential > ( CPV ) ) { if ( CDS -> getNumElements ( ) ) for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) bufferLEByte ( cast < Constant > ( CDS -> getElementAsConstant ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ;"
LLVM,NVPTX,83,"Predict the next statement of this code snippet:
 <s> const DataLayout * TD = TM . getDataLayout ( ) ; int Bytes ; if ( isa < ConstantArray > ( CPV ) || isa < ConstantVector > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( const ConstantDataSequential * CDS = dyn_cast < ConstantDataSequential > ( CPV ) ) { if ( CDS -> getNumElements ( ) ) for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) bufferLEByte ( cast < Constant > ( CDS -> getElementAsConstant ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( isa < ConstantStruct > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) { StructType * ST = cast < StructType > ( CPV -> getType ( ) ) ;"
LLVM,NVPTX,84,"Predict the next statement of this code snippet:
 <s> const Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ptr = ( unsigned char * ) & float32 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ; ptr = ( unsigned char * ) & float64 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } break ; } case Type :: PointerTyID : { if ( GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { aggBuffer -> addSymbol ( GVar ) ; } else if ( ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { Value * v = Cexpr -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v ) ; } unsigned int s = TD -> getTypeAllocSize ( CPV -> getType ( ) ) ; aggBuffer -> addZeros ( s ) ; break ; } case Type :: ArrayTyID : case Type :: VectorTyID : case Type :: StructTyID : { if ( isa < ConstantArray > ( CPV ) || isa < ConstantVector > ( CPV ) || isa < ConstantStruct > ( CPV ) ) { int ElementSize = TD -> getTypeAllocSize ( CPV -> getType ( ) ) ; bufferAggregateConstant ( CPV , aggBuffer ) ; if ( Bytes > ElementSize ) aggBuffer -> addZeros ( Bytes - ElementSize ) ; } else if ( isa < ConstantAggregateZero > ( CPV ) ) aggBuffer -> addZeros ( Bytes ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; } default :"
LLVM,NVPTX,85,"Predict the next statement of this code snippet:
 <s> I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ;"
LLVM,NVPTX,86,"Predict the next statement of this code snippet:
 <s> raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( OutContext , * TM . getDataLayout ( ) ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; SmallString < <NUM_LIT> > Str2 ; raw_svector_ostream OS2 ( Str2 ) ;"
LLVM,NVPTX,87,"Predict the next statement of this code snippet:
 <s> if ( llvm :: isKernelFunction ( * F ) ) O << <STR_LIT> ; else O << <STR_LIT> ; printReturnValStr ( F , O ) ; O << * CurrentFnSym << <STR_LIT> ;"
LLVM,NVPTX,88,"Predict the next statement of this code snippet:
 <s> emitLinkageDirective ( F , O ) ;"
LLVM,NVPTX,89,"Predict the next statement of this code snippet:
 <s> } for ( Value :: const_use_iterator iter = F -> use_begin ( ) , iterEnd = F -> use_end ( ) ; iter != iterEnd ; ++ iter ) { if ( const Constant * C = dyn_cast < Constant > ( * iter ) ) { if ( usedInGlobalVarDef ( C ) ) { CurrentFnSym = Mang -> getSymbol ( F ) ; emitDeclaration ( F , O ) ; break ; } if ( useFuncSeen ( C , seenMap ) ) { CurrentFnSym = Mang -> getSymbol ( F ) ;"
LLVM,NVPTX,90,"Predict the next statement of this code snippet:
 <s> if ( localDecls . find ( f ) == localDecls . end ( ) ) return ; std :: vector < GlobalVariable * > & gvars = localDecls [ f ] ; for ( unsigned i = <NUM_LIT> , e = gvars . size ( ) ; i != e ; ++ i ) { O << <STR_LIT> ; printModuleLevelGV ( gvars [ i ] , O , true ) ; }"
LLVM,NVPTX,91,"Predict the next statement of this code snippet:
 <s> std :: vector < GlobalVariable * > & gvars = localDecls [ f ] ;"
LLVM,NVPTX,92,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) { OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ;"
LLVM,NVPTX,93,"Predict the next statement of this code snippet:
 <s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; setAndEmitFunctionVirtualRegisters ( * MF ) ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ;"
LLVM,NVPTX,94,"Predict the next statement of this code snippet:
 <s> F = MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( llvm :: isKernelFunction ( * F ) ) O << <STR_LIT> ; else { O << <STR_LIT> ; printReturnValStr ( * MF , O ) ; }"
LLVM,NVPTX,95,"Predict the next statement of this code snippet:
 <s> if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( ! nvptxSubtarget . hasDouble ( ) ) O << <STR_LIT> ; } if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ;"
LLVM,NVPTX,96,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; O << nvptxSubtarget . getTargetName ( ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( ! nvptxSubtarget . hasDouble ( ) ) O << <STR_LIT> ; }"
LLVM,NVPTX,97,"Predict the next statement of this code snippet:
 <s> printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ;"
LLVM,NVPTX,98,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) emitLineNumberAsDotLoc ( * MI ) ; printInstruction ( MI , OS ) ;"
LLVM,NVPTX,99,"Predict the next statement of this code snippet:
 <s> unsigned reqntidx , reqntidy , reqntidz ; bool specified = false ; if ( llvm :: getReqNTIDx ( F , reqntidx ) == false ) reqntidx = <NUM_LIT> ; else specified = true ; if ( llvm :: getReqNTIDy ( F , reqntidy ) == false ) reqntidy = <NUM_LIT> ; else specified = true ;"
LLVM,NVPTX,100,"Predict the next statement of this code snippet:
 <s> sys :: path :: append ( FullPathName , fileName ) ; fileName = FullPathName . str ( ) ; } if ( filenameMap . find ( fileName . str ( ) ) == filenameMap . end ( ) ) return ; if ( llvm :: InterleaveSrcInPtx ) this -> emitSrcInText ( fileName . str ( ) , curLoc . getLine ( ) ) ; std :: stringstream temp ; temp << <STR_LIT> << filenameMap [ fileName . str ( ) ] << <STR_LIT> << curLoc . getLine ( ) << <STR_LIT> << curLoc . getCol ( ) ; OutStreamer . EmitRawText ( Twine ( temp . str ( ) . c_str ( ) ) ) ;"
LLVM,NVPTX,101,"Predict the next statement of this code snippet:
 <s> std :: string msg ; msg . append ( <STR_LIT> ) ; msg . append ( <STR_LIT> ) ; if ( V -> hasName ( ) ) msg . append ( V -> getName ( ) . str ( ) ) ; msg . append ( <STR_LIT> ) ;"
LLVM,NVPTX,102,"Predict the next statement of this code snippet:
 <s> int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> << * Mang -> getSymbol ( GVar ) << <STR_LIT> ; if ( ElementSize ) { O << itostr ( ElementSize ) ; } O << <STR_LIT> ; break ; default :"
LLVM,NVPTX,103,"Predict the next statement of this code snippet:
 <s> const DataLayout * TD = TM . getDataLayout ( ) ; const PointerType * PTy = GVar -> getType ( ) ; Type * ETy = PTy -> getElementType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isPrimitiveType ( ) || ETy -> isIntegerTy ( ) || isa < PointerType > ( ETy ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * Mang -> getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ;"
LLVM,NVPTX,104,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitSrcInText ( StringRef filename , unsigned line ) { std :: stringstream temp ; LineReader * reader = this -> getReader ( filename . str ( ) ) ; temp << <STR_LIT> ; temp << filename . str ( ) ; temp << <STR_LIT> ; temp << line ;"
LLVM,NVPTX,105,"Predict the next statement of this code snippet:
 <s> } const StructType * STy = dyn_cast < StructType > ( Ty ) ; if ( STy ) { unsigned int alignStruct = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; i ++ ) { Type * ETy = STy -> getElementType ( i ) ; unsigned int align = getOpenCLAlignment ( TD , ETy ) ; if ( align > alignStruct ) alignStruct = align ; }"
LLVM,NVPTX,106,"Predict the next statement of this code snippet:
 <s> LineReader * <ISA_LIT>AsmPrinter :: getReader ( std :: string filename ) { if ( reader == NULL ) { reader = new LineReader ( filename ) ; }"
LLVM,NVPTX,107,"Predict the next statement of this code snippet:
 <s> O << get<ISA_LIT>RegClassStr ( RC ) << mapped_vr ; return ; } if ( get<ISA_LIT>VectorSize ( RC ) == <NUM_LIT> ) O << <STR_LIT> << get<ISA_LIT>RegClassStr ( RC ) << mapped_vr << <STR_LIT> << get<ISA_LIT>RegClassStr ( RC ) << mapped_vr << <STR_LIT> << get<ISA_LIT>RegClassStr ( RC ) << mapped_vr << <STR_LIT> << get<ISA_LIT>RegClassStr ( RC ) << mapped_vr << <STR_LIT> << <STR_LIT> ; else if ( get<ISA_LIT>VectorSize ( RC ) == <NUM_LIT> ) O << <STR_LIT> << get<ISA_LIT>RegClassStr ( RC ) << mapped_vr << <STR_LIT> << get<ISA_LIT>RegClassStr ( RC ) << mapped_vr << <STR_LIT> << <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,108,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,109,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,110,"Predict the next statement of this code snippet:
 <s> const MCExpr * Base = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; if ( Offset == <NUM_LIT> ) return Base ; unsigned PtrSize = TD . getPointerTypeSizeInBits ( PtrVal -> getType ( ) ) ; if ( PtrSize != <NUM_LIT> ) { int SExtAmount = <NUM_LIT> - PtrSize ; Offset = ( Offset << SExtAmount ) >> SExtAmount ; } return MCBinaryExpr :: CreateAdd ( Base , MCConstantExpr :: Create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; case Instruction :: IntToPtr : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , TD . getIntPtrType ( CE -> getType ( ) ) , false ) ; return LowerConstant ( Op , AP ) ; } case Instruction :: PtrToInt : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = LowerConstant ( Op , AP ) ; if ( TD . getTypeAllocSize ( Ty ) == TD . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = TD . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: Create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: CreateAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: SDiv : case Instruction :: SRem : case Instruction :: Shl : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : { const MCExpr * LHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; const MCExpr * RHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; switch ( CE -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Add : return MCBinaryExpr :: CreateAdd ( LHS , RHS , Ctx ) ; case Instruction :: Sub : return MCBinaryExpr :: CreateSub ( LHS , RHS , Ctx ) ; case Instruction :: Mul : return MCBinaryExpr :: CreateMul ( LHS , RHS , Ctx ) ;"
LLVM,NVPTX,111,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ;"
LLVM,NVPTX,112,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ;"
LLVM,NVPTX,113,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printFPConstant ( const ConstantFP * Fp , raw_ostream & O ) { APFloat APF = APFloat ( Fp -> getValueAPF ( ) ) ; bool ignored ; unsigned int numHex ; const char * lead ; if ( Fp -> getType ( ) -> getTypeID ( ) == Type :: FloatTyID ) { numHex = <NUM_LIT> ; lead = <STR_LIT> ; APF . convert ( APFloat :: IEEEsingle , APFloat :: rmNearestTiesToEven , & ignored ) ; } else if ( Fp -> getType ( ) -> getTypeID ( ) == Type :: DoubleTyID ) { numHex = <NUM_LIT> ; lead = <STR_LIT> ; APF . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & ignored ) ; } else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,114,"Predict the next statement of this code snippet:
 <s> printImplicitDef ( const MachineInstr * MI , raw_ostream & O ) const { O << <STR_LIT> ;"
LLVM,NVPTX,115,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printLdStCode ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier ) { if ( Modifier ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; int Imm = ( int ) MO . getImm ( ) ; if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm ) O << <STR_LIT> ; } else if ( ! strcmp ( Modifier , <STR_LIT> ) ) { switch ( Imm ) { case <STR_LIT> :: GLOBAL : O << <STR_LIT> ; break ; case <STR_LIT> :: SHARED : O << <STR_LIT> ; break ; case <STR_LIT> :: LOCAL : O << <STR_LIT> ; break ; case <STR_LIT> :: PARAM : O << <STR_LIT> ; break ; case <STR_LIT> :: CONSTANT : O << <STR_LIT> ; break ; case <STR_LIT> :: GENERIC : if ( ! nvptxSubtarget . hasGenericLdSt ( ) ) O << <STR_LIT> ; break ; default : assert ( <STR_LIT> ) ; } } else if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm == <STR_LIT> :: Signed ) O << <STR_LIT> ; else if ( Imm == <STR_LIT> :: Unsigned ) O << <STR_LIT> ; else O << <STR_LIT> ;"
LLVM,NVPTX,116,"Predict the next statement of this code snippet:
 <s> printOperand ( MI , opNum , O ) ; if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ; } else { if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ;"
LLVM,NVPTX,117,"Predict the next statement of this code snippet:
 <s> if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) emitVirtualRegister ( MO . getReg ( ) , true , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } return ; case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ;"
LLVM,NVPTX,118,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { if ( MO . getReg ( ) == <STR_LIT> ) O << DEPOTNAME << getFunctionNumber ( ) ; else O << getRegisterName ( MO . getReg ( ) ) ; } else { if ( ! Modifier ) emitVirtualRegister ( MO . getReg ( ) , false , O ) ; else { if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) emitVirtualRegister ( MO . getReg ( ) , true , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } return ; case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : { const char * symbname = MO . getSymbolName ( ) ; if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; printParamName ( index , O ) ; } else if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ;"
LLVM,NVPTX,119,"Predict the next statement of this code snippet:
 <s> O << * CurrentFnSym << <STR_LIT> << paramIndex ; return ; } for ( I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , i ++ ) { if ( i == paramIndex ) { printParamName ( I , paramIndex , O ) ; return ; } } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,120,"Predict the next statement of this code snippet:
 <s> } for ( I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , i ++ ) {"
LLVM,NVPTX,121,"Predict the next statement of this code snippet:
 <s> elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; totalsz += sz / <NUM_LIT> ; } } unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else assert ( false && <STR_LIT> ) ; } } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) {"
LLVM,NVPTX,122,"Predict the next statement of this code snippet:
 <s> return ; } if ( ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ) { printFPConstant ( CFP , O ) ; return ; } if ( isa < ConstantPointerNull > ( CPV ) ) { O << <STR_LIT> ; return ; } if ( GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { O << * Mang -> getSymbol ( GVar ) ; return ; } if ( ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { Value * v = Cexpr -> stripPointerCasts ( ) ; if ( GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { O << * Mang -> getSymbol ( GVar ) ;"
LLVM,NVPTX,123,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> << vecelem [ Imm % <NUM_LIT> ] ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm < <NUM_LIT> ) Imm = <NUM_LIT> ;"
LLVM,NVPTX,124,"Predict the next statement of this code snippet:
 <s> } while ( theCurLine < lineNum ) { fstr . getline ( buff , <NUM_LIT> ) ; theCurLine ++ ; }"
LLVM,NVPTX,125,"Predict the next statement of this code snippet:
 <s> while ( theCurLine < lineNum ) { fstr . getline ( buff , <NUM_LIT> ) ;"
LLVM,NVPTX,126,"Predict the next statement of this code snippet:
 <s> ++ i ; } for ( DebugInfoFinder :: iterator I = DbgFinder . subprogram_begin ( ) , E = DbgFinder . subprogram_end ( ) ; I != E ; ++ I ) { DISubprogram SP ( * I ) ; StringRef Filename ( SP . getFilename ( ) ) ; StringRef Dirname ( SP . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName . str ( ) ;"
LLVM,NVPTX,127,"Predict the next statement of this code snippet:
 <s> StringRef Dirname ( DIUnit . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName . str ( ) ; } if ( filenameMap . find ( Filename . str ( ) ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename . str ( ) ] = i ; OutStreamer . EmitDwarfFileDirective ( i , <STR_LIT> , Filename . str ( ) ) ; ++ i ; } for ( DebugInfoFinder :: iterator I = DbgFinder . subprogram_begin ( ) , E = DbgFinder . subprogram_end ( ) ; I != E ; ++ I ) { DISubprogram SP ( * I ) ;"
LLVM,NVPTX,128,"Predict the next statement of this code snippet:
 <s> } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = TRI -> index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ; std :: map < unsigned , unsigned > & regmap = VRidGlobal2LocalMap [ RC -> getID ( ) ] ; int n = regmap . size ( ) ; regmap . insert ( std :: make_pair ( vr , n + <NUM_LIT> ) ) ; } O << <STR_LIT> << <ISA_LIT>NumRegisters << <STR_LIT> ; O << <STR_LIT> << <ISA_LIT>NumRegisters << <STR_LIT> ; O << <STR_LIT> << <ISA_LIT>NumRegisters << <STR_LIT> ; O << <STR_LIT> << <ISA_LIT>NumRegisters << <STR_LIT> ;"
LLVM,NVPTX,129,"Predict the next statement of this code snippet:
 <s> } else return false ; } if ( const MDNode * md = dyn_cast < MDNode > ( U ) ) if ( md -> hasName ( ) && ( ( md -> getName ( ) . str ( ) == <STR_LIT> ) || ( md -> getName ( ) . str ( ) == <STR_LIT> ) ) ) return true ; for ( User :: const_use_iterator ui = U -> use_begin ( ) , ue = U -> use_end ( ) ;"
LLVM,NVPTX,130,"Predict the next statement of this code snippet:
 <s> } else if ( const Instruction * I = dyn_cast < Instruction > ( * ui ) ) { const BasicBlock * bb = I -> getParent ( ) ; if ( ! bb ) continue ; const Function * caller = bb -> getParent ( ) ;"
LLVM,NVPTX,131,"Predict the next statement of this code snippet:
 <s> static bool useFuncSeen ( const Constant * C , llvm :: DenseMap < const Function * , bool > & seenMap ) { for ( Value :: const_use_iterator ui = C -> use_begin ( ) , ue = C -> use_end ( ) ; ui != ue ; ++ ui ) {"
LLVM,NVPTX,132,"Predict the next statement of this code snippet:
 <s> int Bytes ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CPV ) ) { APInt Val = CI -> getValue ( ) ; for ( unsigned I = <NUM_LIT> , E = DL . getTypeAllocSize ( CPV -> getType ( ) ) ; I < E ; ++ I ) { uint8_t Byte = Val . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ; aggBuffer -> addBytes ( & Byte , <NUM_LIT> , <NUM_LIT> ) ; Val . lshrInPlace ( <NUM_LIT> ) ; } return ; } if ( isa < ConstantArray > ( CPV ) || isa < ConstantVector > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; }"
LLVM,NVPTX,133,"Predict the next statement of this code snippet:
 <s> size_t NumBytes = ( Val . getBitWidth ( ) + <NUM_LIT> ) / <NUM_LIT> ; SmallVector < unsigned char , <NUM_LIT> > Buf ( NumBytes ) ; for ( unsigned I = <NUM_LIT> ; I < NumBytes ; ++ I ) { Buf [ I ] = Val . extractBitsAsZExtValue ( <NUM_LIT> , I * <NUM_LIT> ) ; } AggBuffer -> addBytes ( Buf . data ( ) , NumBytes , Bytes ) ; } ; switch ( CPV -> getType ( ) -> getTypeID ( ) ) { case Type :: IntegerTyID : if ( const auto CI = dyn_cast < ConstantInt > ( CPV ) ) { AddIntToBuffer ( CI -> getValue ( ) ) ; break ; } if ( const auto * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { if ( const auto * CI = dyn_cast < ConstantInt > ( ConstantFoldConstant ( Cexpr , DL ) ) ) { AddIntToBuffer ( CI -> getValue ( ) ) ; break ; } if ( Cexpr -> getOpcode ( ) == Instruction :: PtrToInt ) { Value * V = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; AggBuffer -> addSymbol ( V , Cexpr -> getOperand ( <NUM_LIT> ) ) ; AggBuffer -> addZeros ( AllocSize ) ; break ;"
LLVM,NVPTX,134,"Predict the next statement of this code snippet:
 <s> static bool canDemoteGlobalVar ( const GlobalVariable * gv , Function const * & f ) { if ( ! gv -> hasInternalLinkage ( ) ) return false ; PointerType * Pty = gv -> getType ( ) ;"
LLVM,NVPTX,135,"Predict the next statement of this code snippet:
 <s> if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( V ) ) Globals . insert ( GV ) ; else { if ( const User * U = dyn_cast < User > ( V ) ) { for ( unsigned i = <NUM_LIT> , e = U -> getNumOperands ( ) ; i != e ; ++ i ) { DiscoverDependentGlobals ( U -> getOperand ( i ) , Globals ) ; } } }"
LLVM,NVPTX,136,"Predict the next statement of this code snippet:
 <s> static void DiscoverDependentGlobals ( const Value * V , DenseSet < const GlobalVariable * > & Globals ) { if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( V ) ) Globals . insert ( GV ) ; else { if ( const User * U = dyn_cast < User > ( V ) ) { for ( unsigned i = <NUM_LIT> , e = U -> getNumOperands ( ) ; i != e ; ++ i ) { DiscoverDependentGlobals ( U -> getOperand ( i ) , Globals ) ;"
LLVM,NVPTX,137,"Predict the next statement of this code snippet:
 <s> I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; if ( HasDebugInfo ) { static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> closeLastSection ( ) ; OutStreamer -> emitRawText ( <STR_LIT> ) ; }"
LLVM,NVPTX,138,"Predict the next statement of this code snippet:
 <s> if ( ! isEmptyXXStructor ( M . getNamedGlobal ( <STR_LIT> ) ) ) { report_fatal_error ( <STR_LIT> ) ; return true ; } bool Result = AsmPrinter :: doInitialization ( M ) ; GlobalsEmitted = false ;"
LLVM,NVPTX,139,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitBasicBlockStart ( const MachineBasicBlock & MBB ) { AsmPrinter :: emitBasicBlockStart ( MBB ) ; if ( isLoopHeaderOfNoUnroll ( MBB ) ) OutStreamer -> emitRawText ( StringRef ( <STR_LIT> ) ) ;"
LLVM,NVPTX,140,"Predict the next statement of this code snippet:
 <s> getSymbol ( F ) -> print ( O , MAI ) ; O << <STR_LIT> ; emitFunctionParamList ( F , O ) ; O << <STR_LIT> ;"
LLVM,NVPTX,141,"Predict the next statement of this code snippet:
 <s> printReturnValStr ( F , O ) ; getSymbol ( F ) -> print ( O , MAI ) ; O << <STR_LIT> ;"
LLVM,NVPTX,142,"Predict the next statement of this code snippet:
 <s> for ( const User * U : F -> users ( ) ) { if ( const Constant * C = dyn_cast < Constant > ( U ) ) { if ( usedInGlobalVarDef ( C ) ) { emitDeclaration ( F , O ) ; break ; } if ( useFuncSeen ( C , seenMap ) ) { emitDeclaration ( F , O ) ; break ; } } if ( ! isa < Instruction > ( U ) ) continue ; const Instruction * instr = cast < Instruction > ( U ) ; const BasicBlock * bb = instr -> getParent ( ) ;"
LLVM,NVPTX,143,"Predict the next statement of this code snippet:
 <s> } if ( ! isa < Instruction > ( U ) ) continue ; const Instruction * instr = cast < Instruction > ( U ) ; const BasicBlock * bb = instr -> getParent ( ) ; if ( ! bb ) continue ; const Function * caller = bb -> getParent ( ) ; if ( ! caller ) continue ; if ( seenMap . find ( caller ) != seenMap . end ( ) ) { emitDeclaration ( F , O ) ; break ;"
LLVM,NVPTX,144,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitFunctionBodyEnd ( ) {"
LLVM,NVPTX,145,"Predict the next statement of this code snippet:
 <s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ;"
LLVM,NVPTX,146,"Predict the next statement of this code snippet:
 <s> raw_svector_ostream O ( Str ) ;"
LLVM,NVPTX,147,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitFunctionParamList ( const MachineFunction & MF , raw_ostream & O ) { const Function & F = MF . getFunction ( ) ;"
LLVM,NVPTX,148,"Predict the next statement of this code snippet:
 <s> for ( const GlobalVariable & I : M . globals ( ) ) VisitGlobalVariableForEmission ( & I , Globals , GVVisited , GVVisiting ) ; assert ( GVVisited . size ( ) == M . getGlobalList ( ) . size ( ) && <STR_LIT> ) ; assert ( GVVisiting . size ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Globals . size ( ) ; i != e ; ++ i ) printModuleLevelGV ( Globals [ i ] , OS2 ) ;"
LLVM,NVPTX,149,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; unsigned PTXVersion = STI . getPTXVersion ( ) ; O << <STR_LIT> << ( PTXVersion / <NUM_LIT> ) << <STR_LIT> << ( PTXVersion % <NUM_LIT> ) << <STR_LIT> ; O << <STR_LIT> ; O << STI . getTargetName ( ) ; const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; if ( NTM . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; bool HasFullDebugInfo = false ; for ( DICompileUnit * CU : M . debug_compile_units ( ) ) { switch ( CU -> getEmissionKind ( ) ) { case DICompileUnit :: NoDebug : case DICompileUnit :: DebugDirectivesOnly : break ; case DICompileUnit :: LineTablesOnly : case DICompileUnit :: FullDebug : HasFullDebugInfo = true ; break ; } if ( HasFullDebugInfo ) break ; }"
LLVM,NVPTX,150,"Predict the next statement of this code snippet:
 <s> } else { const <ISA_LIT>Subtarget & STI = MI -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;"
LLVM,NVPTX,151,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget & STI = MI -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; OutStreamer -> AddComment ( Twine ( <STR_LIT> ) + STI . getRegisterInfo ( ) -> getName ( RegNo ) ) ; }"
LLVM,NVPTX,152,"Predict the next statement of this code snippet:
 <s> MCInst Inst ; lowerToMCInst ( MI , Inst ) ; EmitToStreamer ( * OutStreamer , Inst ) ;"
LLVM,NVPTX,153,"Predict the next statement of this code snippet:
 <s> if ( ! getReqNTIDx ( F , reqntidx ) ) reqntidx = <NUM_LIT> ; else specified = true ; if ( ! getReqNTIDy ( F , reqntidy ) ) reqntidy = <NUM_LIT> ; else specified = true ; if ( ! getReqNTIDz ( F , reqntidz ) ) reqntidz = <NUM_LIT> ; else specified = true ; if ( specified ) O << <STR_LIT> << reqntidx << <STR_LIT> << reqntidy << <STR_LIT> << reqntidz << <STR_LIT> ; unsigned maxntidx , maxntidy , maxntidz ; specified = false ; if ( ! getMaxNTIDx ( F , maxntidx ) ) maxntidx = <NUM_LIT> ; else specified = true ; if ( ! getMaxNTIDy ( F , maxntidy ) ) maxntidy = <NUM_LIT> ; else specified = true ; if ( ! getMaxNTIDz ( F , maxntidz ) ) maxntidz = <NUM_LIT> ; else specified = true ; if ( specified ) O << <STR_LIT> << maxntidx << <STR_LIT> << maxntidy << <STR_LIT> << maxntidz << <STR_LIT> ; unsigned mincta ; if ( getMinCTASm ( F , mincta ) ) O << <STR_LIT> << mincta << <STR_LIT> ; unsigned maxnreg ; if ( getMaxNReg ( F , maxnreg ) ) O << <STR_LIT> << maxnreg << <STR_LIT> ;"
LLVM,NVPTX,154,"Predict the next statement of this code snippet:
 <s> std :: string msg ; msg . append ( <STR_LIT> ) ; msg . append ( <STR_LIT> ) ; if ( V -> hasName ( ) ) msg . append ( std :: string ( V -> getName ( ) ) ) ; msg . append ( <STR_LIT> ) ; llvm_unreachable ( msg . c_str ( ) ) ; } else if ( ! V -> hasInternalLinkage ( ) && ! V -> hasPrivateLinkage ( ) ) { O << <STR_LIT> ; }"
LLVM,NVPTX,155,"Predict the next statement of this code snippet:
 <s> break ; case ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> + llvm :: Twine ( AddressSpace ) ) ; break ; }"
LLVM,NVPTX,156,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> + llvm :: Twine ( AddressSpace ) ) ;"
LLVM,NVPTX,157,"Predict the next statement of this code snippet:
 <s> getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: FixedVectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; if ( ElementSize ) { O << ElementSize ; } O << <STR_LIT> ; break ;"
LLVM,NVPTX,158,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const auto * STI = static_cast < const <ISA_LIT>Subtarget * > ( NTM . getSubtargetImpl ( ) ) ; SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; emitHeader ( M , OS1 , * STI ) ; OutStreamer -> emitRawText ( OS1 . str ( ) ) ;"
LLVM,NVPTX,159,"Predict the next statement of this code snippet:
 <s> if ( Register :: isVirtualRegister ( Reg ) ) { const TargetRegisterClass * RC = MRI -> getRegClass ( Reg ) ; DenseMap < unsigned , unsigned > & RegMap = VRegMapping [ RC ] ; unsigned RegNum = RegMap [ Reg ] ; unsigned Ret = <NUM_LIT> ; if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else { report_fatal_error ( <STR_LIT> ) ;"
LLVM,NVPTX,160,"Predict the next statement of this code snippet:
 <s> Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else { report_fatal_error ( <STR_LIT> ) ; } Ret |= ( RegNum & <NUM_LIT> ) ; return Ret ; } else { return Reg & <NUM_LIT> ; }"
LLVM,NVPTX,161,"Predict the next statement of this code snippet:
 <s> const MCSymbol * <ISA_LIT>AsmPrinter :: getFunctionFrameSymbol ( ) const { SmallString < <NUM_LIT> > Str ; raw_svector_ostream ( Str ) << DEPOTNAME << getFunctionNumber ( ) ; return OutContext . getOrCreateSymbol ( Str ) ;"
LLVM,NVPTX,162,"Predict the next statement of this code snippet:
 <s> raw_svector_ostream ( Str ) << DEPOTNAME << getFunctionNumber ( ) ;"
LLVM,NVPTX,163,"Predict the next statement of this code snippet:
 <s> switch ( Ty -> getTypeID ( ) ) { case Type :: IntegerTyID : { unsigned NumBits = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( NumBits == <NUM_LIT> ) return <STR_LIT> ; else if ( NumBits <= <NUM_LIT> ) { std :: string name = <STR_LIT> ; return name + utostr ( NumBits ) ; } else { llvm_unreachable ( <STR_LIT> ) ; break ; } break ; } case Type :: HalfTyID : return <STR_LIT> ; case Type :: FloatTyID :"
LLVM,NVPTX,164,"Predict the next statement of this code snippet:
 <s> case Type :: HalfTyID : return <STR_LIT> ; case Type :: FloatTyID : return <STR_LIT> ; case Type :: DoubleTyID : return <STR_LIT> ; case Type :: PointerTyID :"
LLVM,NVPTX,165,"Predict the next statement of this code snippet:
 <s> const ConstantArray * InitList = dyn_cast < ConstantArray > ( GV -> getInitializer ( ) ) ;"
LLVM,NVPTX,166,"Predict the next statement of this code snippet:
 <s> static bool isEmptyXXStructor ( GlobalVariable * GV ) { if ( ! GV ) return true ; const ConstantArray * InitList = dyn_cast < ConstantArray > ( GV -> getInitializer ( ) ) ; if ( ! InitList ) return true ;"
LLVM,NVPTX,167,"Predict the next statement of this code snippet:
 <s> MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; if ( ! LI . isLoopHeader ( & MBB ) ) return false ; for ( const MachineBasicBlock * PMBB : MBB . predecessors ( ) ) {"
LLVM,NVPTX,168,"Predict the next statement of this code snippet:
 <s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target32 ( ) ) ;"
LLVM,NVPTX,169,"Predict the next statement of this code snippet:
 <s> LLVMTargetMachine & TM = const_cast < LLVMTargetMachine & > ( MF -> getTarget ( ) ) ; <ISA_LIT>TargetMachine & nvTM = static_cast < <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const char * Sym = MFI -> getImageHandleSymbol ( Index ) ; std :: string * SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( Sym ) ;"
LLVM,NVPTX,170,"Predict the next statement of this code snippet:
 <s> std :: string * SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( Sym ) ;"
LLVM,NVPTX,171,"Predict the next statement of this code snippet:
 <s> const ConstantFP * Cnt = MO . getFPImm ( ) ; const APFloat & Val = Cnt -> getValueAPF ( ) ; switch ( Cnt -> getType ( ) -> getTypeID ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; break ; case Type :: HalfTyID : MCOp = MCOperand :: createExpr ( <ISA_LIT>FloatMCExpr :: createConstantFPHalf ( Val , OutContext ) ) ; break ; case Type :: FloatTyID : MCOp = MCOperand :: createExpr ( <ISA_LIT>FloatMCExpr :: createConstantFPSingle ( Val , OutContext ) ) ;"
LLVM,NVPTX,172,"Predict the next statement of this code snippet:
 <s> OutMI . addOperand ( GetSymbolRef ( OutContext . getOrCreateSymbol ( Twine ( MO . getSymbolName ( ) ) ) ) ) ; return ; } const <ISA_LIT>Subtarget & STI = MI -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; if ( ! STI . hasImageHandles ( ) ) { if ( lowerImageHandleOperand ( MI , i , MCOp ) ) { OutMI . addOperand ( MCOp ) ; continue ; } } if ( lowerOperand ( MO , MCOp ) ) OutMI . addOperand ( MCOp ) ; }"
LLVM,NVPTX,173,"Predict the next statement of this code snippet:
 <s> O << '[' ; printMemOperand ( MI , OpNo , O ) ; O << ']' ; return false ;"
LLVM,NVPTX,174,"Predict the next statement of this code snippet:
 <s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; O << '[' ;"
LLVM,NVPTX,175,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'r' : break ; }"
LLVM,NVPTX,176,"Predict the next statement of this code snippet:
 <s> if ( Fp -> getType ( ) -> getTypeID ( ) == Type :: FloatTyID ) { numHex = <NUM_LIT> ; lead = <STR_LIT> ; APF . convert ( APFloat :: IEEEsingle ( ) , APFloat :: rmNearestTiesToEven , & ignored ) ; } else if ( Fp -> getType ( ) -> getTypeID ( ) == Type :: DoubleTyID ) { numHex = <NUM_LIT> ; lead = <STR_LIT> ; APF . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & ignored ) ; } else llvm_unreachable ( <STR_LIT> ) ; APInt API = APF . bitcastToAPInt ( ) ; O << lead << format_hex_no_prefix ( API . getZExtValue ( ) , numHex , true ) ;"
LLVM,NVPTX,177,"Predict the next statement of this code snippet:
 <s> printOperand ( MI , opNum , O ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ; } else { if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ;"
LLVM,NVPTX,178,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; return ; } if ( isSampler ( * GVar ) ) { O << <STR_LIT> << getSamplerName ( * GVar ) ; const Constant * Initializer = nullptr ; if ( GVar -> hasInitializer ( ) ) Initializer = GVar -> getInitializer ( ) ; const ConstantInt * CI = nullptr ; if ( Initializer ) CI = dyn_cast < ConstantInt > ( Initializer ) ; if ( CI ) { unsigned sample = CI -> getZExtValue ( ) ; O << <STR_LIT> ; for ( int i = <NUM_LIT> , addr = ( ( sample & __CLK_ADDRESS_MASK ) >> __CLK_ADDRESS_BASE ) ; i < <NUM_LIT> ; i ++ ) { O << <STR_LIT> << i << <STR_LIT> ; switch ( addr ) { case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; } O << <STR_LIT> ; } O << <STR_LIT> ; switch ( ( sample & __CLK_FILTER_MASK ) >> __CLK_FILTER_BASE ) { case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : O << <STR_LIT> ; break ; } if ( ! ( ( sample & __CLK_NORMALIZED_MASK ) >> __CLK_NORMALIZED_BASE ) ) { O << <STR_LIT> ; } O << <STR_LIT> ; } O << <STR_LIT> ; return ; } if ( GVar -> hasPrivateLinkage ( ) ) { if ( strncmp ( GVar -> getName ( ) . data ( ) , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return ; if ( strncmp ( GVar -> getName ( ) . data ( ) , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return ; if ( GVar -> use_empty ( ) ) return ; } const Function * demotedFunc = nullptr ; if ( ! processDemoted && canDemoteGlobalVar ( GVar , demotedFunc ) ) { O << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> ; if ( localDecls . find ( demotedFunc ) != localDecls . end ( ) ) localDecls [ demotedFunc ] . push_back ( GVar ) ; else { std :: vector < const GlobalVariable * > temp ; temp . push_back ( GVar ) ; localDecls [ demotedFunc ] = temp ; } return ; } O << <STR_LIT> ;"
LLVM,NVPTX,179,"Predict the next statement of this code snippet:
 <s> emitVirtualRegister ( MO . getReg ( ) , O ) ; } break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , O ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,NVPTX,180,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printReturnValStr ( const MachineFunction & MF , raw_ostream & O ) { const Function & F = MF . getFunction ( ) ;"
LLVM,NVPTX,181,"Predict the next statement of this code snippet:
 <s> const Function & F = MF . getFunction ( ) ;"
LLVM,NVPTX,182,"Predict the next statement of this code snippet:
 <s> } if ( EmitGeneric && ! isa < Function > ( CPV ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; } else { getSymbol ( GVar ) -> print ( O , MAI ) ; } return ; } if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; PointerType * PTy = dyn_cast < PointerType > ( Cexpr -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ;"
LLVM,NVPTX,183,"Predict the next statement of this code snippet:
 <s> bool Result = AsmPrinter :: runOnMachineFunction ( F ) ; OutStreamer -> emitRawText ( StringRef ( <STR_LIT> ) ) ; return Result ;"
LLVM,NVPTX,184,"Predict the next statement of this code snippet:
 <s> bool Result = AsmPrinter :: runOnMachineFunction ( F ) ;"
LLVM,NVPTX,185,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: setAndEmitFunctionVirtualRegisters ( const MachineFunction & MF ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; if ( NumBytes ) { O << <STR_LIT> << MFI . getMaxAlign ( ) . value ( ) << <STR_LIT> << DEPOTNAME << getFunctionNumber ( ) << <STR_LIT> << NumBytes << <STR_LIT> ; if ( static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . is64Bit ( ) ) { O << <STR_LIT> ; O << <STR_LIT> ; } else {"
LLVM,NVPTX,186,"Predict the next statement of this code snippet:
 <s> if ( const Constant * cu = dyn_cast < Constant > ( U ) ) { if ( useFuncSeen ( cu , seenMap ) ) return true ;"
LLVM,NVPTX,187,"Predict the next statement of this code snippet:
 <s> for ( DenseSet < const GlobalVariable * > :: iterator I = Others . begin ( ) , E = Others . end ( ) ; I != E ; ++ I ) VisitGlobalVariableForEmission ( * I , Order , Visited , Visiting ) ; Order . push_back ( GV ) ;"
LLVM,NVPTX,188,"Predict the next statement of this code snippet:
 <s> assert ( ( curpos + Num ) <= size ) ; assert ( ( curpos + Bytes ) <= size ) ; for ( int i = <NUM_LIT> ; i < Num ; ++ i ) { buffer [ curpos ] = Ptr [ i ] ; curpos ++ ; } for ( int i = Num ; i < Bytes ; ++ i ) { buffer [ curpos ] = <NUM_LIT> ; curpos ++ ; } return curpos ;"
LLVM,NVPTX,189,"Predict the next statement of this code snippet:
 <s> for ( int i = Num ; i < Bytes ; ++ i ) { buffer [ curpos ] = <NUM_LIT> ; curpos ++ ; }"
LLVM,NVPTX,190,"Predict the next statement of this code snippet:
 <s> Symbols . push_back ( GVar ) ; numSymbols ++ ;"
LLVM,NVPTX,191,"Predict the next statement of this code snippet:
 <s> Symbols . push_back ( GVar ) ;"
LLVM,NVPTX,192,"Predict the next statement of this code snippet:
 <s> assert ( ( curpos + Num ) <= size ) ; for ( int i = <NUM_LIT> ; i < Num ; ++ i ) {"
LLVM,NVPTX,193,"Predict the next statement of this code snippet:
 <s> AggBuffer ( unsigned _size , raw_ostream & _O , <ISA_LIT>AsmPrinter & _AP ) : O ( _O ) , AP ( _AP ) {"
LLVM,NVPTX,194,"Predict the next statement of this code snippet:
 <s> if ( HasDebugInfo ) { static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> closeLastSection ( ) ; OutStreamer -> emitRawText ( <STR_LIT> ) ; }"
LLVM,NVPTX,195,"Predict the next statement of this code snippet:
 <s> void EmitAlignment ( unsigned NumBits , const GlobalValue * GV = <NUM_LIT> ) const {"
LLVM,NVPTX,196,"Predict the next statement of this code snippet:
 <s> void EmitAlignment ( unsigned NumBits , const GlobalValue * GV = <NUM_LIT> ) const {"
LLVM,NVPTX,197,"Predict the next statement of this code snippet:
 <s> } if ( ! isa < Instruction > ( U ) ) continue ; const Instruction * instr = cast < Instruction > ( U ) ; const BasicBlock * bb = instr -> getParent ( ) ; if ( ! bb ) continue ; const Function * caller = bb -> getParent ( ) ; if ( ! caller ) continue ; if ( seenMap . find ( caller ) != seenMap . end ( ) ) { emitDeclaration ( & F , O ) ; break ; } } seenMap [ & F ] = true ;"
LLVM,NVPTX,198,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitDemotedVars ( const Function * f , raw_ostream & O ) { if ( localDecls . find ( f ) == localDecls . end ( ) ) return ; std :: vector < const GlobalVariable * > & gvars = localDecls [ f ] ; for ( const GlobalVariable * GV : gvars ) { O << <STR_LIT> ; printModuleLevelGV ( GV , O , true ) ; }"
LLVM,NVPTX,199,"Predict the next statement of this code snippet:
 <s> for ( const GlobalVariable * GV : gvars ) { O << <STR_LIT> ;"
LLVM,NVPTX,200,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( DL , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getPointerElementType ( ) ; if ( isABI || isKernelFunc ) { Align align = DL . getValueOrABITypeAlignment ( PAL . getParamAlignment ( paramIndex ) , ETy ) ; if ( ! isKernelFunc && align < Align ( <NUM_LIT> ) ) align = Align ( <NUM_LIT> ) ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align . value ( ) << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , ETy , vtparts ) ;"
LLVM,NVPTX,201,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; return ; } if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntOrPtrTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: FixedVectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; if ( ElementSize ) { O << ElementSize ; }"
LLVM,NVPTX,202,"Predict the next statement of this code snippet:
 <s> MCSymbol * Name = AP . Mang -> getSymbol ( GVar ) ; O << * Name ; } else if ( ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) { O << * <STR_LIT> ( Cexpr , AP ) ; } else llvm_unreachable ( <STR_LIT> ) ; nSym ++ ; if ( nSym >= numSymbols ) nextSymbolPos = size + <NUM_LIT> ; else nextSymbolPos = symbolPosInBuffer [ nSym ] ; } else if ( nBytes == <NUM_LIT> ) O << * ( unsigned int * ) ( buffer + pos ) ;"
LLVM,NVPTX,203,"Predict the next statement of this code snippet:
 <s> if ( ETy -> isFloatingPointTy ( ) || ETy -> isPointerTy ( ) || ( ETy -> isIntegerTy ( ) && ETy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) ) { O << <STR_LIT> ; if ( ETy -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( ETy , false ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; if ( GVar -> hasInitializer ( ) ) { if ( ( PTy -> getAddressSpace ( ) == ADDRESS_SPACE_GLOBAL ) || ( PTy -> getAddressSpace ( ) == ADDRESS_SPACE_CONST ) ) { const Constant * Initializer = GVar -> getInitializer ( ) ; if ( ! Initializer -> isNullValue ( ) && ! isa < UndefValue > ( Initializer ) ) { O << <STR_LIT> ; printScalarConstant ( Initializer , O ) ; } } else { if ( ! GVar -> getInitializer ( ) -> isNullValue ( ) && ! isa < UndefValue > ( GVar -> getInitializer ( ) ) ) { report_fatal_error ( <STR_LIT> + GVar -> getName ( ) + <STR_LIT> + Twine ( PTy -> getAddressSpace ( ) ) + <STR_LIT> ) ; } } } } else { unsigned int ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: IntegerTyID : case Type :: StructTyID : case Type :: ArrayTyID : case Type :: FixedVectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; if ( ( ( PTy -> getAddressSpace ( ) == ADDRESS_SPACE_GLOBAL ) || ( PTy -> getAddressSpace ( ) == ADDRESS_SPACE_CONST ) ) && GVar -> hasInitializer ( ) ) { const Constant * Initializer = GVar -> getInitializer ( ) ; if ( ! isa < UndefValue > ( Initializer ) && ! Initializer -> isNullValue ( ) ) { AggBuffer aggBuffer ( ElementSize , O , * this ) ; bufferAggregateConstant ( Initializer , & aggBuffer ) ; if ( aggBuffer . numSymbols ) { if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is64Bit ( ) ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; O << ElementSize / <NUM_LIT> ; } else { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; O << ElementSize / <NUM_LIT> ; } O << <STR_LIT> ; } else { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; O << ElementSize ; O << <STR_LIT> ;"
LLVM,NVPTX,204,"Predict the next statement of this code snippet:
 <s> DenseSet < const GlobalVariable * > Others ; for ( unsigned i = <NUM_LIT> , e = GV -> getNumOperands ( ) ; i != e ; ++ i ) DiscoverDependentGlobals ( GV -> getOperand ( i ) , Others ) ; for ( const GlobalVariable * GV : Others ) VisitGlobalVariableForEmission ( GV , Order , Visited , Visiting ) ; Order . push_back ( GV ) ; Visited . insert ( GV ) ; Visiting . erase ( GV ) ;"
LLVM,NVPTX,205,"Predict the next statement of this code snippet:
 <s> delete [ ] buffer ;"
LLVM,NVPTX,206,"Predict the next statement of this code snippet:
 <s> ~ AggBuffer ( ) { delete [ ] buffer ;"
LLVM,NVPTX,207,"Predict the next statement of this code snippet:
 <s> const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ; Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ConvertFloatToBytes ( ptr , float32 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ; ConvertDoubleToBytes ( ptr , float64 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } break ; } case Type :: PointerTyID : { if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { aggBuffer -> addSymbol ( GVar , GVar ) ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr ) ; } unsigned int s = DL . getTypeAllocSize ( CPV -> getType ( ) ) ; aggBuffer -> addZeros ( s ) ; break ; } case Type :: ArrayTyID : case Type :: VectorTyID : case Type :: StructTyID : { if ( isa < ConstantAggregate > ( CPV ) || isa < ConstantDataSequential > ( CPV ) ) { int ElementSize = DL . getTypeAllocSize ( CPV -> getType ( ) ) ; bufferAggregateConstant ( CPV , aggBuffer ) ; if ( Bytes > ElementSize ) aggBuffer -> addZeros ( Bytes - ElementSize ) ; } else if ( isa < ConstantAggregateZero > ( CPV ) ) aggBuffer -> addZeros ( Bytes ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,208,"Predict the next statement of this code snippet:
 <s> report_fatal_error ( <STR_LIT> ) ; return true ; } if ( ! isEmptyXXStructor ( M . getNamedGlobal ( <STR_LIT> ) ) ) { report_fatal_error ( <STR_LIT> ) ; return true ; } SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; emitHeader ( M , OS1 , STI ) ; OutStreamer -> EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer -> AddComment ( <STR_LIT> ) ;"
LLVM,NVPTX,209,"Predict the next statement of this code snippet:
 <s> const Function * F = & * FI ; if ( F -> isDeclaration ( ) ) { if ( F -> use_empty ( ) ) continue ; if ( F -> getIntrinsicID ( ) ) continue ; emitDeclaration ( F , O ) ; continue ; } for ( const User * U : F -> users ( ) ) { if ( const Constant * C = dyn_cast < Constant > ( U ) ) { if ( usedInGlobalVarDef ( C ) ) { emitDeclaration ( F , O ) ; break ; } if ( useFuncSeen ( C , seenMap ) ) {"
LLVM,NVPTX,210,"Predict the next statement of this code snippet:
 <s> for ( const User * U : F -> users ( ) ) { if ( const Constant * C = dyn_cast < Constant > ( U ) ) { if ( usedInGlobalVarDef ( C ) ) { emitDeclaration ( F , O ) ; break ; } if ( useFuncSeen ( C , seenMap ) ) { emitDeclaration ( F , O ) ; break ; } } if ( ! isa < Instruction > ( U ) ) continue ;"
LLVM,NVPTX,211,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; if ( ! GlobalsEmitted ) { emitGlobals ( * MF -> getFunction ( ) -> getParent ( ) ) ; GlobalsEmitted = true ; } MRI = & MF -> getRegInfo ( ) ; F = MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( isKernelFunction ( * F ) ) O << <STR_LIT> ;"
LLVM,NVPTX,212,"Predict the next statement of this code snippet:
 <s> MRI = & MF -> getRegInfo ( ) ; F = MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( isKernelFunction ( * F ) ) O << <STR_LIT> ; else { O << <STR_LIT> ;"
LLVM,NVPTX,213,"Predict the next statement of this code snippet:
 <s> void emitGlobalVariable ( const GlobalVariable * GV ) override {"
LLVM,NVPTX,214,"Predict the next statement of this code snippet:
 <s> void emitGlobalVariable ( const GlobalVariable * GV ) override {"
LLVM,NVPTX,215,"Predict the next statement of this code snippet:
 <s> if ( ! Scope ) return ; StringRef fileName ( Scope -> getFilename ( ) ) ; StringRef dirName ( Scope -> getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) { sys :: path :: append ( FullPathName , fileName ) ; fileName = FullPathName ; } if ( filenameMap . find ( fileName ) == filenameMap . end ( ) ) return ;"
LLVM,NVPTX,216,"Predict the next statement of this code snippet:
 <s> if ( ! Scope ) return ; StringRef fileName ( Scope -> getFilename ( ) ) ; StringRef dirName ( Scope -> getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) { sys :: path :: append ( FullPathName , fileName ) ; fileName = FullPathName ; } if ( filenameMap . find ( fileName ) == filenameMap . end ( ) ) return ; if ( InterleaveSrc ) this -> emitSrcInText ( fileName , curLoc . getLine ( ) ) ; std :: stringstream temp ; temp << <STR_LIT> << filenameMap [ fileName ] << <STR_LIT> << curLoc . getLine ( ) << <STR_LIT> << curLoc . getCol ( ) ;"
LLVM,NVPTX,217,"Predict the next statement of this code snippet:
 <s> break ; case ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : O << <STR_LIT> ;"
LLVM,NVPTX,218,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitPTXAddressSpace ( unsigned int AddressSpace , raw_ostream & O ) const { switch ( AddressSpace ) { case ADDRESS_SPACE_LOCAL : O << <STR_LIT> ; break ; case ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> ) ; break ;"
LLVM,NVPTX,219,"Predict the next statement of this code snippet:
 <s> const DataLayout & DL = getDataLayout ( ) ; Type * ETy = GVar -> getValueType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( GVar -> getType ( ) -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) DL . getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ;"
LLVM,NVPTX,220,"Predict the next statement of this code snippet:
 <s> if ( reader -> fileName ( ) != filename ) { delete reader ; reader = new LineReader ( filename ) ; }"
LLVM,NVPTX,221,"Predict the next statement of this code snippet:
 <s> if ( ! reader ) { reader = new LineReader ( filename ) ; } if ( reader -> fileName ( ) != filename ) { delete reader ;"
LLVM,NVPTX,222,"Predict the next statement of this code snippet:
 <s> if ( LI . getLoopFor ( PMBB ) != LI . getLoopFor ( & MBB ) ) { continue ; } if ( const BasicBlock * PBB = PMBB -> getBasicBlock ( ) ) { if ( MDNode * LoopID = PBB -> getTerminator ( ) -> getMetadata ( LLVMContext :: MD_loop ) ) { if ( GetUnrollMetadata ( LoopID , <STR_LIT> ) ) return true ; }"
LLVM,NVPTX,223,"Predict the next statement of this code snippet:
 <s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target32 ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>Target64 ( ) ) ;"
LLVM,NVPTX,224,"Predict the next statement of this code snippet:
 <s> const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , DL . getIntPtrType ( CV -> getType ( ) ) , false ) ; return lowerConstantForGV ( Op , ProcessingGeneric ) ; } case Instruction :: PtrToInt : { const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = lowerConstantForGV ( Op , ProcessingGeneric ) ; if ( DL . getTypeAllocSize ( Ty ) == DL . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = DL . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: createAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : { const MCExpr * LHS = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; const MCExpr * RHS = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; switch ( CE -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Add : return MCBinaryExpr :: createAdd ( LHS , RHS , Ctx ) ; }"
LLVM,NVPTX,225,"Predict the next statement of this code snippet:
 <s> const char * Sym = MFI -> getImageHandleSymbol ( Index ) ; std :: string * SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( Sym ) ; MCOp = GetSymbolRef ( OutContext . getOrCreateSymbol ( StringRef ( * SymNamePtr ) ) ) ;"
LLVM,NVPTX,226,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: lowerImageHandleSymbol ( unsigned Index , MCOperand & MCOp ) { TargetMachine & TM = const_cast < TargetMachine & > ( MF -> getTarget ( ) ) ; <ISA_LIT>TargetMachine & nvTM = static_cast < <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;"
LLVM,NVPTX,227,"Predict the next statement of this code snippet:
 <s> MCOp = GetSymbolRef ( GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_FPImmediate : { const ConstantFP * Cnt = MO . getFPImm ( ) ; const APFloat & Val = Cnt -> getValueAPF ( ) ; switch ( Cnt -> getType ( ) -> getTypeID ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; break ; case Type :: FloatTyID : MCOp = MCOperand :: createExpr ( <ISA_LIT>FloatMCExpr :: createConstantFPSingle ( Val , OutContext ) ) ; break ; case Type :: DoubleTyID :"
LLVM,NVPTX,228,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printFPConstant ( const ConstantFP * Fp , raw_ostream & O ) { APFloat APF = APFloat ( Fp -> getValueAPF ( ) ) ; bool ignored ; unsigned int numHex ; const char * lead ; if ( Fp -> getType ( ) -> getTypeID ( ) == Type :: FloatTyID ) { numHex = <NUM_LIT> ; lead = <STR_LIT> ; APF . convert ( APFloat :: IEEEsingle ( ) , APFloat :: rmNearestTiesToEven , & ignored ) ; } else if ( Fp -> getType ( ) -> getTypeID ( ) == Type :: DoubleTyID ) { numHex = <NUM_LIT> ; lead = <STR_LIT> ; APF . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & ignored ) ; } else llvm_unreachable ( <STR_LIT> ) ; APInt API = APF . bitcastToAPInt ( ) ; std :: string hexstr ( utohexstr ( API . getZExtValue ( ) ) ) ; O << lead ; if ( hexstr . length ( ) < numHex ) O << std :: string ( numHex - hexstr . length ( ) , '0' ) ; O << utohexstr ( API . getZExtValue ( ) ) ;"
LLVM,NVPTX,229,"Predict the next statement of this code snippet:
 <s> if ( isManaged ( * GVar ) ) { O << <STR_LIT> ; } if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) DL . getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; if ( ETy -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( ETy , false ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; if ( GVar -> hasInitializer ( ) ) { if ( ( PTy -> getAddressSpace ( ) == ADDRESS_SPACE_GLOBAL ) || ( PTy -> getAddressSpace ( ) == ADDRESS_SPACE_CONST ) ) { const Constant * Initializer = GVar -> getInitializer ( ) ; if ( ! Initializer -> isNullValue ( ) && ! isa < UndefValue > ( Initializer ) ) { O << <STR_LIT> ; printScalarConstant ( Initializer , O ) ; } } else { if ( ! GVar -> getInitializer ( ) -> isNullValue ( ) && ! isa < UndefValue > ( GVar -> getInitializer ( ) ) ) { report_fatal_error ( <STR_LIT> + GVar -> getName ( ) + <STR_LIT> + Twine ( PTy -> getAddressSpace ( ) ) + <STR_LIT> ) ; } } } } else { unsigned int ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; if ( ( ( PTy -> getAddressSpace ( ) == ADDRESS_SPACE_GLOBAL ) || ( PTy -> getAddressSpace ( ) == ADDRESS_SPACE_CONST ) ) && GVar -> hasInitializer ( ) ) { const Constant * Initializer = GVar -> getInitializer ( ) ; if ( ! isa < UndefValue > ( Initializer ) && ! Initializer -> isNullValue ( ) ) { AggBuffer aggBuffer ( ElementSize , O , * this ) ; bufferAggregateConstant ( Initializer , & aggBuffer ) ; if ( aggBuffer . numSymbols ) { if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is64Bit ( ) ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; O << ElementSize / <NUM_LIT> ; } else {"
LLVM,NVPTX,230,"Predict the next statement of this code snippet:
 <s> if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( auto * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; if ( size < <NUM_LIT> ) size = <NUM_LIT> ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( DL ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned totalsz = DL . getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = DL . getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ;"
LLVM,NVPTX,231,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> << idx ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ idx ; }"
LLVM,NVPTX,232,"Predict the next statement of this code snippet:
 <s> filenameMap [ Filename ] = i ; OutStreamer -> EmitDwarfFileDirective ( i , <STR_LIT> , Filename ) ; ++ i ; } for ( DISubprogram * SP : DbgFinder . subprograms ( ) ) { StringRef Filename = SP -> getFilename ( ) ; StringRef Dirname = SP -> getDirectory ( ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ;"
LLVM,NVPTX,233,"Predict the next statement of this code snippet:
 <s> ++ i ; } for ( DISubprogram * SP : DbgFinder . subprograms ( ) ) { StringRef Filename = SP -> getFilename ( ) ; StringRef Dirname = SP -> getDirectory ( ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName ; } if ( filenameMap . find ( Filename ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename ] = i ; OutStreamer -> EmitDwarfFileDirective ( i , <STR_LIT> , Filename ) ; ++ i ;"
LLVM,NVPTX,234,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> :: GT : O << <STR_LIT> ; break ; case <STR_LIT> :: GE : O << <STR_LIT> ; break ; case <STR_LIT> :: LO : O << <STR_LIT> ; break ; case <STR_LIT> :: LS : O << <STR_LIT> ; break ; case <STR_LIT> :: HI : O << <STR_LIT> ; break ; case <STR_LIT> :: HS : O << <STR_LIT> ; break ; case <STR_LIT> :: EQU : O << <STR_LIT> ; break ; case <STR_LIT> :: NEU : O << <STR_LIT> ; break ; case <STR_LIT> :: LTU : O << <STR_LIT> ; break ; case <STR_LIT> :: LEU : O << <STR_LIT> ; break ; case <STR_LIT> :: GTU : O << <STR_LIT> ; break ; case <STR_LIT> :: GEU : O << <STR_LIT> ; break ; case <STR_LIT> :: NUM :"
LLVM,NVPTX,235,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; O << <STR_LIT> ;"
LLVM,NVPTX,236,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printImplicitDef ( const MachineInstr * MI , raw_ostream & O ) const { O << <STR_LIT> ; O << <STR_LIT> ;"
LLVM,NVPTX,237,"Predict the next statement of this code snippet:
 <s> if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm ) O << <STR_LIT> ; } else if ( ! strcmp ( Modifier , <STR_LIT> ) ) { switch ( Imm ) { case <STR_LIT> :: GLOBAL : O << <STR_LIT> ; break ; case <STR_LIT> :: SHARED : O << <STR_LIT> ; break ; case <STR_LIT> :: LOCAL : O << <STR_LIT> ; break ; case <STR_LIT> :: PARAM : O << <STR_LIT> ; break ; case <STR_LIT> :: CONSTANT : O << <STR_LIT> ; break ; case <STR_LIT> :: GENERIC : if ( ! nvptxSubtarget . hasGenericLdSt ( ) ) O << <STR_LIT> ;"
LLVM,NVPTX,238,"Predict the next statement of this code snippet:
 <s> switch ( Imm ) { case <STR_LIT> :: GLOBAL : O << <STR_LIT> ; break ; case <STR_LIT> :: SHARED : O << <STR_LIT> ; break ; case <STR_LIT> :: LOCAL : O << <STR_LIT> ; break ; case <STR_LIT> :: PARAM : O << <STR_LIT> ; break ; case <STR_LIT> :: CONSTANT : O << <STR_LIT> ; break ; case <STR_LIT> :: GENERIC : if ( ! nvptxSubtarget . hasGenericLdSt ( ) ) O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm == <STR_LIT> :: Signed ) O << <STR_LIT> ; else if ( Imm == <STR_LIT> :: Unsigned ) O << <STR_LIT> ;"
LLVM,NVPTX,239,"Predict the next statement of this code snippet:
 <s> case MachineOperand :: MO_ExternalSymbol : { const char * symbname = MO . getSymbolName ( ) ; if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; printParamName ( index , O ) ; } else if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; O << * CurrentFnSym << <STR_LIT> << index << <STR_LIT> ; } else O << symbname ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; default :"
LLVM,NVPTX,240,"Predict the next statement of this code snippet:
 <s> Symbols . push_back ( GVar ) ;"
LLVM,NVPTX,241,"Predict the next statement of this code snippet:
 <s> Symbols . push_back ( GVar ) ;"
LLVM,NVPTX,242,"Predict the next statement of this code snippet:
 <s> AggBuffer ( unsigned _size , raw_ostream & _O , <ISA_LIT>AsmPrinter & _AP ) : O ( _O ) , AP ( _AP ) { buffer = new unsigned char [ _size ] ; size = _size ;"
LLVM,NVPTX,243,"Predict the next statement of this code snippet:
 <s> if ( CPV -> getNumOperands ( ) ) { StructType * ST = cast < StructType > ( CPV -> getType ( ) ) ; for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == ( e - <NUM_LIT> ) ) Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( <NUM_LIT> ) + TD -> getTypeAllocSize ( ST ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; else Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( i + <NUM_LIT> ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , Bytes , aggBuffer ) ; } } return ; }"
LLVM,NVPTX,244,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == ( e - <NUM_LIT> ) ) Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( <NUM_LIT> ) + TD -> getTypeAllocSize ( ST ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; else Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( i + <NUM_LIT> ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , Bytes , aggBuffer ) ;"
LLVM,NVPTX,245,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; } else if ( ETy == Type :: getInt64Ty ( CPV -> getContext ( ) ) ) { if ( const ConstantInt * constInt = dyn_cast < ConstantInt > ( CPV ) ) { long long int64 = ( long long ) ( constInt -> getZExtValue ( ) ) ; ptr = ( unsigned char * ) & int64 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { if ( const ConstantInt * constInt = dyn_cast < ConstantInt > ( ConstantFoldConstantExpression ( Cexpr , TD ) ) ) { long long int64 = ( long long ) ( constInt -> getZExtValue ( ) ) ; ptr = ( unsigned char * ) & int64 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } if ( Cexpr -> getOpcode ( ) == Instruction :: PtrToInt ) { Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; } case Type :: FloatTyID : case Type :: DoubleTyID : { const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ; const Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ptr = ( unsigned char * ) & float32 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ; ptr = ( unsigned char * ) & float64 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } break ; } case Type :: PointerTyID : { if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { aggBuffer -> addSymbol ( GVar ) ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v ) ; } unsigned int s = TD -> getTypeAllocSize ( CPV -> getType ( ) ) ;"
LLVM,NVPTX,246,"Predict the next statement of this code snippet:
 <s> static bool canDemoteGlobalVar ( const GlobalVariable * gv , Function const * & f ) { if ( gv -> hasInternalLinkage ( ) == false ) return false ; const PointerType * Pty = gv -> getType ( ) ; if ( Pty -> getAddressSpace ( ) != llvm :: ADDRESS_SPACE_SHARED ) return false ; const Function * oneFunc = nullptr ; bool flag = usedInOneFunc ( gv , oneFunc ) ; if ( flag == false ) return false ; if ( ! oneFunc ) return false ; f = oneFunc ; return true ;"
LLVM,NVPTX,247,"Predict the next statement of this code snippet:
 <s> static bool canDemoteGlobalVar ( const GlobalVariable * gv , Function const * & f ) { if ( gv -> hasInternalLinkage ( ) == false ) return false ; const PointerType * Pty = gv -> getType ( ) ; if ( Pty -> getAddressSpace ( ) != llvm :: ADDRESS_SPACE_SHARED ) return false ; const Function * oneFunc = nullptr ;"
LLVM,NVPTX,248,"Predict the next statement of this code snippet:
 <s> SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( TM . getDataLayout ( ) ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ;"
LLVM,NVPTX,249,"Predict the next statement of this code snippet:
 <s> MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( TM . getDataLayout ( ) ) ;"
LLVM,NVPTX,250,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitDeclaration ( const Function * F , raw_ostream & O ) { emitLinkageDirective ( F , O ) ; if ( llvm :: isKernelFunction ( * F ) ) O << <STR_LIT> ; else O << <STR_LIT> ; printReturnValStr ( F , O ) ; O << * getSymbol ( F ) << <STR_LIT> ; emitFunctionParamList ( F , O ) ; O << <STR_LIT> ;"
LLVM,NVPTX,251,"Predict the next statement of this code snippet:
 <s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ;"
LLVM,NVPTX,252,"Predict the next statement of this code snippet:
 <s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; VRegMapping . clear ( ) ;"
LLVM,NVPTX,253,"Predict the next statement of this code snippet:
 <s> emitDemotedVars ( MF -> getFunction ( ) , O ) ; OutStreamer . EmitRawText ( O . str ( ) ) ;"
LLVM,NVPTX,254,"Predict the next statement of this code snippet:
 <s> setAndEmitFunctionVirtualRegisters ( * MF ) ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ;"
LLVM,NVPTX,255,"Predict the next statement of this code snippet:
 <s> } MRI = & MF -> getRegInfo ( ) ; F = MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( llvm :: isKernelFunction ( * F ) ) O << <STR_LIT> ; else { O << <STR_LIT> ; printReturnValStr ( * MF , O ) ; }"
LLVM,NVPTX,256,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; if ( ! GlobalsEmitted ) { emitGlobals ( * MF -> getFunction ( ) -> getParent ( ) ) ; GlobalsEmitted = true ; } MRI = & MF -> getRegInfo ( ) ; F = MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( llvm :: isKernelFunction ( * F ) ) O << <STR_LIT> ; else { O << <STR_LIT> ; printReturnValStr ( * MF , O ) ; } O << * CurrentFnSym ; emitFunctionParamList ( * MF , O ) ; if ( llvm :: isKernelFunction ( * F ) ) emitKernelFunctionDirectives ( * F , O ) ;"
LLVM,NVPTX,257,"Predict the next statement of this code snippet:
 <s> bool isKernelFunc = llvm :: isKernelFunction ( * F ) ; bool isABI = ( nvptxSubtarget . getSmVersion ( ) >= <NUM_LIT> ) ; MVT thePointerTy = TLI -> getPointerTy ( ) ; O << <STR_LIT> ; for ( I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , paramIndex ++ ) { Type * Ty = I -> getType ( ) ; if ( ! first ) O << <STR_LIT> ; first = false ; if ( isKernelFunction ( * F ) ) { if ( isSampler ( * I ) || isImage ( * I ) ) { if ( isImage ( * I ) ) { std :: string sname = I -> getName ( ) ; if ( isImageWriteOnly ( * I ) || isImageReadWrite ( * I ) ) { if ( nvptxSubtarget . hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> << paramIndex ; } else { if ( nvptxSubtarget . hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> << paramIndex ; } } else { if ( nvptxSubtarget . hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> << paramIndex ; } continue ; } } if ( PAL . hasAttribute ( paramIndex + <NUM_LIT> , Attribute :: ByVal ) == false ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( Ty ) ; unsigned sz = TD -> getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ;"
LLVM,NVPTX,258,"Predict the next statement of this code snippet:
 <s> raw_svector_ostream OS2 ( Str2 ) ; emitDeclarations ( M , OS2 ) ; SmallVector < const GlobalVariable * , <NUM_LIT> > Globals ; DenseSet < const GlobalVariable * > GVVisited ; DenseSet < const GlobalVariable * > GVVisiting ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) VisitGlobalVariableForEmission ( I , Globals , GVVisited , GVVisiting ) ; assert ( GVVisited . size ( ) == M . getGlobalList ( ) . size ( ) && <STR_LIT> ) ; assert ( GVVisiting . size ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Globals . size ( ) ; i != e ; ++ i ) printModuleLevelGV ( Globals [ i ] , OS2 ) ; OS2 << '\n' ;"
LLVM,NVPTX,259,"Predict the next statement of this code snippet:
 <s> SmallString < <NUM_LIT> > Str2 ; raw_svector_ostream OS2 ( Str2 ) ; emitDeclarations ( M , OS2 ) ; SmallVector < const GlobalVariable * , <NUM_LIT> > Globals ; DenseSet < const GlobalVariable * > GVVisited ; DenseSet < const GlobalVariable * > GVVisiting ;"
LLVM,NVPTX,260,"Predict the next statement of this code snippet:
 <s> O << nvptxSubtarget . getTargetName ( ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( ! nvptxSubtarget . hasDouble ( ) ) O << <STR_LIT> ; } if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << <STR_LIT> ;"
LLVM,NVPTX,261,"Predict the next statement of this code snippet:
 <s> if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( ! nvptxSubtarget . hasDouble ( ) ) O << <STR_LIT> ; } if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) O << <STR_LIT> ;"
LLVM,NVPTX,262,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitImplicitDef ( const MachineInstr * MI ) const { unsigned RegNo = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterInfo * TRI = TM . getRegisterInfo ( ) ; if ( TRI -> isVirtualRegister ( RegNo ) ) { OutStreamer . AddComment ( Twine ( <STR_LIT> ) + getVirtualRegisterName ( RegNo ) ) ; } else { OutStreamer . AddComment ( Twine ( <STR_LIT> ) + TM . getRegisterInfo ( ) -> getName ( RegNo ) ) ; } OutStreamer . AddBlankLine ( ) ;"
LLVM,NVPTX,263,"Predict the next statement of this code snippet:
 <s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) emitLineNumberAsDotLoc ( * MI ) ; MCInst Inst ; lowerToMCInst ( MI , Inst ) ; EmitToStreamer ( OutStreamer , Inst ) ;"
LLVM,NVPTX,264,"Predict the next statement of this code snippet:
 <s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) emitLineNumberAsDotLoc ( * MI ) ; MCInst Inst ; lowerToMCInst ( MI , Inst ) ;"
LLVM,NVPTX,265,"Predict the next statement of this code snippet:
 <s> else specified = true ; if ( specified ) O << <STR_LIT> << reqntidx << <STR_LIT> << reqntidy << <STR_LIT> << reqntidz << <STR_LIT> ; unsigned maxntidx , maxntidy , maxntidz ; specified = false ; if ( llvm :: getMaxNTIDx ( F , maxntidx ) == false ) maxntidx = <NUM_LIT> ; else specified = true ;"
LLVM,NVPTX,266,"Predict the next statement of this code snippet:
 <s> DebugLoc curLoc = MI . getDebugLoc ( ) ; if ( prevDebugLoc . isUnknown ( ) && curLoc . isUnknown ( ) ) return ; if ( prevDebugLoc == curLoc ) return ; prevDebugLoc = curLoc ; if ( curLoc . isUnknown ( ) ) return ; const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const LLVMContext & ctx = MF -> getFunction ( ) -> getContext ( ) ; DIScope Scope ( curLoc . getScope ( ctx ) ) ; assert ( ( ! Scope || Scope . isScope ( ) ) && <STR_LIT> ) ; if ( ! Scope ) return ; StringRef fileName ( Scope . getFilename ( ) ) ; StringRef dirName ( Scope . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) { sys :: path :: append ( FullPathName , fileName ) ;"
LLVM,NVPTX,267,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitLinkageDirective ( const GlobalValue * V , raw_ostream & O ) { if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( V -> hasExternalLinkage ( ) ) { if ( isa < GlobalVariable > ( V ) ) { const GlobalVariable * GVar = cast < GlobalVariable > ( V ) ; if ( GVar ) { if ( GVar -> hasInitializer ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; }"
LLVM,NVPTX,268,"Predict the next statement of this code snippet:
 <s> } } else if ( V -> isDeclaration ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; } else if ( V -> hasAppendingLinkage ( ) ) { std :: string msg ; msg . append ( <STR_LIT> ) ; msg . append ( <STR_LIT> ) ; if ( V -> hasName ( ) ) msg . append ( V -> getName ( ) . str ( ) ) ; msg . append ( <STR_LIT> ) ; llvm_unreachable ( msg . c_str ( ) ) ; } else if ( ! V -> hasInternalLinkage ( ) && ! V -> hasPrivateLinkage ( ) ) { O << <STR_LIT> ;"
LLVM,NVPTX,269,"Predict the next statement of this code snippet:
 <s> else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isSingleValueType ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID :"
LLVM,NVPTX,270,"Predict the next statement of this code snippet:
 <s> int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> << * getSymbol ( GVar ) << <STR_LIT> ; if ( ElementSize ) { O << itostr ( ElementSize ) ; } O << <STR_LIT> ;"
LLVM,NVPTX,271,"Predict the next statement of this code snippet:
 <s> temp << reader -> readLine ( line ) ; temp << <STR_LIT> ;"
LLVM,NVPTX,272,"Predict the next statement of this code snippet:
 <s> if ( numE == <NUM_LIT> ) return <NUM_LIT> * alignE ; else return numE * alignE ; } const StructType * STy = dyn_cast < StructType > ( Ty ) ; if ( STy ) { unsigned int alignStruct = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; i ++ ) {"
LLVM,NVPTX,273,"Predict the next statement of this code snippet:
 <s> case Type :: FloatTyID : return <STR_LIT> ; case Type :: DoubleTyID : return <STR_LIT> ; case Type :: PointerTyID : if ( nvptxSubtarget . is64Bit ( ) ) if ( useB4PTR ) return <STR_LIT> ; else return <STR_LIT> ; else if ( useB4PTR ) return <STR_LIT> ; else return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; return nullptr ;"
LLVM,NVPTX,274,"Predict the next statement of this code snippet:
 <s> Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; return MCOperand :: CreateExpr ( Expr ) ;"
LLVM,NVPTX,275,"Predict the next statement of this code snippet:
 <s> const MCExpr * Expr ; Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; return MCOperand :: CreateExpr ( Expr ) ;"
LLVM,NVPTX,276,"Predict the next statement of this code snippet:
 <s> if ( PI != TypeNameMap . end ( ) && ( ! PI -> second . compare ( <STR_LIT> ) || ! PI -> second . compare ( <STR_LIT> ) || ! PI -> second . compare ( <STR_LIT> ) ) ) return true ;"
LLVM,NVPTX,277,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: isImageType ( const Type * Ty ) {"
LLVM,NVPTX,278,"Predict the next statement of this code snippet:
 <s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( The<ISA_LIT>Target64 ) ;"
LLVM,NVPTX,279,"Predict the next statement of this code snippet:
 <s> if ( CV -> isNullValue ( ) || isa < UndefValue > ( CV ) ) return MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) return MCConstantExpr :: Create ( CI -> getZExtValue ( ) , Ctx ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) return MCSymbolRefExpr :: Create ( AP . getSymbol ( GV ) , Ctx ) ; if ( const BlockAddress * BA = dyn_cast < BlockAddress > ( CV ) ) return MCSymbolRefExpr :: Create ( AP . GetBlockAddressSymbol ( BA ) , Ctx ) ; const ConstantExpr * CE = dyn_cast < ConstantExpr > ( CV ) ; if ( ! CE ) llvm_unreachable ( <STR_LIT> ) ; switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstantExpression ( CE , AP . TM . getDataLayout ( ) ) ) if ( C != CE ) return LowerConstant ( C , AP ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! AP . MF ? nullptr : AP . MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; PointerType * SrcTy = cast < PointerType > ( CE -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( SrcTy -> getAddressSpace ( ) == <NUM_LIT> && DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return LowerConstant ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , AP ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! AP . MF ? nullptr : AP . MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; }"
LLVM,NVPTX,280,"Predict the next statement of this code snippet:
 <s> if ( OpNo == <NUM_LIT> ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNo == <NUM_LIT> ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNo == <NUM_LIT> ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNo == <NUM_LIT> ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ;"
LLVM,NVPTX,281,"Predict the next statement of this code snippet:
 <s> std :: string * SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( Sym ) ; MCOp = GetSymbolRef ( OutContext . GetOrCreateSymbol ( StringRef ( SymNamePtr -> c_str ( ) ) ) ) ;"
LLVM,NVPTX,282,"Predict the next statement of this code snippet:
 <s> case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , OutContext ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_FPImmediate : { const ConstantFP * Cnt = MO . getFPImm ( ) ; APFloat Val = Cnt -> getValueAPF ( ) ; switch ( Cnt -> getType ( ) -> getTypeID ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; break ; case Type :: FloatTyID : MCOp = MCOperand :: CreateExpr ( <ISA_LIT>FloatMCExpr :: CreateConstantFPSingle ( Val , OutContext ) ) ; break ; case Type :: DoubleTyID : MCOp = MCOperand :: CreateExpr ( <ISA_LIT>FloatMCExpr :: CreateConstantFPDouble ( Val , OutContext ) ) ; break ; } break ; }"
LLVM,NVPTX,283,"Predict the next statement of this code snippet:
 <s> unsigned int pos = <NUM_LIT> ; unsigned int nSym = <NUM_LIT> ; unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( AP . nvptxSubtarget . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . getSymbol ( GVar ) ; PointerType * PTy = dyn_cast < PointerType > ( GVar -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; O << * Name ; O << <STR_LIT> ; } else { O << * Name ; } } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) {"
LLVM,NVPTX,284,"Predict the next statement of this code snippet:
 <s> case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress :"
LLVM,NVPTX,285,"Predict the next statement of this code snippet:
 <s> int i = <NUM_LIT> ; if ( ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) || ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) ) { O << * CurrentFnSym << <STR_LIT> << paramIndex ; return ; } for ( I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , i ++ ) {"
LLVM,NVPTX,286,"Predict the next statement of this code snippet:
 <s> } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( ) . getSizeInBits ( ) << <STR_LIT> ; } else { if ( ( Ty -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( Ty ) ) { unsigned totalsz = TD -> getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else assert ( false && <STR_LIT> ) ; } } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ;"
LLVM,NVPTX,287,"Predict the next statement of this code snippet:
 <s> } if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ) { printFPConstant ( CFP , O ) ; return ; } if ( isa < ConstantPointerNull > ( CPV ) ) { O << <STR_LIT> ; return ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { PointerType * PTy = dyn_cast < PointerType > ( GVar -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( EmitGeneric && ! isa < Function > ( CPV ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; O << * getSymbol ( GVar ) ; O << <STR_LIT> ; } else { O << * getSymbol ( GVar ) ; } return ; } if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; PointerType * PTy = dyn_cast < PointerType > ( Cexpr -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ;"
LLVM,NVPTX,288,"Predict the next statement of this code snippet:
 <s> O << * getSymbol ( GVar ) ; O << <STR_LIT> ; } else { O << * getSymbol ( GVar ) ; } return ; } if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; PointerType * PTy = dyn_cast < PointerType > ( Cexpr -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; O << * getSymbol ( GVar ) ; O << <STR_LIT> ; } else { O << * getSymbol ( GVar ) ; }"
LLVM,NVPTX,289,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: recordAndEmitFilenames ( Module & M ) { DebugInfoFinder DbgFinder ; DbgFinder . processModule ( M ) ; unsigned i = <NUM_LIT> ; for ( DICompileUnit DIUnit : DbgFinder . compile_units ( ) ) { StringRef Filename ( DIUnit . getFilename ( ) ) ; StringRef Dirname ( DIUnit . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName . str ( ) ; } if ( filenameMap . find ( Filename . str ( ) ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename . str ( ) ] = i ; OutStreamer . EmitDwarfFileDirective ( i , <STR_LIT> , Filename . str ( ) ) ; ++ i ; } for ( DISubprogram SP : DbgFinder . subprograms ( ) ) { StringRef Filename ( SP . getFilename ( ) ) ; StringRef Dirname ( SP . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) {"
LLVM,NVPTX,290,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: setAndEmitFunctionVirtualRegisters ( const MachineFunction & MF ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( NumBytes ) { O << <STR_LIT> << MFI -> getMaxAlignment ( ) << <STR_LIT> << DEPOTNAME << getFunctionNumber ( ) << <STR_LIT> << NumBytes << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) { O << <STR_LIT> ; O << <STR_LIT> ; } else { O << <STR_LIT> ; O << <STR_LIT> ; } } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = TRI -> index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ;"
LLVM,NVPTX,291,"Predict the next statement of this code snippet:
 <s> raw_svector_ostream O ( Str ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( NumBytes ) { O << <STR_LIT> << MFI -> getMaxAlignment ( ) << <STR_LIT> << DEPOTNAME << getFunctionNumber ( ) << <STR_LIT> << NumBytes << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) { O << <STR_LIT> ; O << <STR_LIT> ; } else { O << <STR_LIT> ; O << <STR_LIT> ; } } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = TRI -> index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; int n = regmap . size ( ) ;"
LLVM,NVPTX,292,"Predict the next statement of this code snippet:
 <s> if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( C ) ) { if ( GV -> getName ( ) . str ( ) == <STR_LIT> ) return false ;"
LLVM,NVPTX,293,"Predict the next statement of this code snippet:
 <s> if ( const Instruction * instr = dyn_cast < Instruction > ( U ) ) { if ( instr -> getParent ( ) && instr -> getParent ( ) -> getParent ( ) ) { const Function * curFunc = instr -> getParent ( ) -> getParent ( ) ; if ( oneFunc && ( curFunc != oneFunc ) ) return false ; oneFunc = curFunc ; return true ; } else return false ; } if ( const MDNode * md = dyn_cast < MDNode > ( U ) ) if ( md -> hasName ( ) && ( ( md -> getName ( ) . str ( ) == <STR_LIT> ) || ( md -> getName ( ) . str ( ) == <STR_LIT> ) ) ) return true ; for ( const User * UU : U -> users ( ) ) if ( usedInOneFunc ( UU , oneFunc ) == false ) return false ; return true ;"
LLVM,NVPTX,294,"Predict the next statement of this code snippet:
 <s> if ( const Instruction * instr = dyn_cast < Instruction > ( U ) ) { if ( instr -> getParent ( ) && instr -> getParent ( ) -> getParent ( ) ) { const Function * curFunc = instr -> getParent ( ) -> getParent ( ) ; if ( oneFunc && ( curFunc != oneFunc ) ) return false ;"
LLVM,NVPTX,295,"Predict the next statement of this code snippet:
 <s> void VisitGlobalVariableForEmission ( const GlobalVariable * GV , SmallVectorImpl < const GlobalVariable * > & Order , DenseSet < const GlobalVariable * > & Visited , DenseSet < const GlobalVariable * > & Visiting ) { if ( Visited . count ( GV ) ) return ; if ( Visiting . count ( GV ) ) report_fatal_error ( <STR_LIT> ) ; Visiting . insert ( GV ) ;"
LLVM,NVPTX,296,"Predict the next statement of this code snippet:
 <s> if ( Visited . count ( GV ) ) return ; if ( Visiting . count ( GV ) ) report_fatal_error ( <STR_LIT> ) ; Visiting . insert ( GV ) ; DenseSet < const GlobalVariable * > Others ; for ( unsigned i = <NUM_LIT> , e = GV -> getNumOperands ( ) ; i != e ; ++ i ) DiscoverDependentGlobals ( GV -> getOperand ( i ) , Others ) ;"
LLVM,NVPTX,297,"Predict the next statement of this code snippet:
 <s> ~ AggBuffer ( ) { delete [ ] buffer ;"
LLVM,NVPTX,298,"Predict the next statement of this code snippet:
 <s> printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { unsigned align = PAL . getParamAlignment ( paramIndex ) ; if ( align == <NUM_LIT> ) align = DL . getABITypeAlignment ( ETy ) ; if ( ! isKernelFunc && align < <NUM_LIT> ) align = <NUM_LIT> ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , ETy , vtparts ) ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ paramIndex ; } if ( i < e - <NUM_LIT> ) O << <STR_LIT> ; } -- paramIndex ; continue ; } } O << <STR_LIT> ;"
LLVM,NVPTX,299,"Predict the next statement of this code snippet:
 <s> const DataLayout & DL = getDataLayout ( ) ; Type * ETy = GVar -> getValueType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( GVar -> getType ( ) -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) DL . getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isIntegerTy ( <NUM_LIT> ) ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; return ;"
LLVM,NVPTX,300,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ;"
LLVM,NVPTX,301,"Predict the next statement of this code snippet:
 <s> if ( ! getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = DL . getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ;"
LLVM,NVPTX,302,"Predict the next statement of this code snippet:
 <s> emitGlobals ( M ) ; GlobalsEmitted = true ; } Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = <NUM_LIT> ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ;"
LLVM,NVPTX,303,"Predict the next statement of this code snippet:
 <s> while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ;"
LLVM,NVPTX,304,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; unsigned PTXVersion = STI . getPTXVersion ( ) ; O << <STR_LIT> << ( PTXVersion / <NUM_LIT> ) << <STR_LIT> << ( PTXVersion % <NUM_LIT> ) << <STR_LIT> ; O << <STR_LIT> ;"
LLVM,NVPTX,305,"Predict the next statement of this code snippet:
 <s> bool Result = AsmPrinter :: runOnMachineFunction ( F ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; return Result ;"
LLVM,NVPTX,306,"Predict the next statement of this code snippet:
 <s> OutStreamer . AddComment ( Twine ( <STR_LIT> ) + getVirtualRegisterName ( RegNo ) ) ; } else { OutStreamer . AddComment ( Twine ( <STR_LIT> ) + TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) -> getName ( RegNo ) ) ; }"
LLVM,NVPTX,307,"Predict the next statement of this code snippet:
 <s> Type * ETy = PTy -> getElementType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> << * getSymbol ( GVar ) << <STR_LIT> ; if ( ElementSize ) { O << itostr ( ElementSize ) ; } O << <STR_LIT> ; break ;"
LLVM,NVPTX,308,"Predict the next statement of this code snippet:
 <s> static unsigned int getOpenCLAlignment ( const DataLayout * TD , Type * Ty ) { if ( Ty -> isSingleValueType ( ) ) return TD -> getPrefTypeAlignment ( Ty ) ; const ArrayType * ATy = dyn_cast < ArrayType > ( Ty ) ; if ( ATy ) return getOpenCLAlignment ( TD , ATy -> getElementType ( ) ) ; const StructType * STy = dyn_cast < StructType > ( Ty ) ; if ( STy ) { unsigned int alignStruct = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; i ++ ) { Type * ETy = STy -> getElementType ( i ) ;"
LLVM,NVPTX,309,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: isLoopHeaderOfNoUnroll ( const MachineBasicBlock & MBB ) const { MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; if ( ! LI . isLoopHeader ( const_cast < MachineBasicBlock * > ( & MBB ) ) ) return false ; for ( auto I = MBB . pred_begin ( ) ; I != MBB . pred_end ( ) ; ++ I ) { const MachineBasicBlock * PMBB = * I ; if ( LI . getLoopFor ( PMBB ) != LI . getLoopFor ( & MBB ) ) { continue ;"
LLVM,NVPTX,310,"Predict the next statement of this code snippet:
 <s> } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ;"
LLVM,NVPTX,311,"Predict the next statement of this code snippet:
 <s> size = Ty -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( ( Ty -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( Ty ) ) { unsigned totalsz = TD -> getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ;"
LLVM,NVPTX,312,"Predict the next statement of this code snippet:
 <s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ) { printFPConstant ( CFP , O ) ; return ; } if ( isa < ConstantPointerNull > ( CPV ) ) { O << <STR_LIT> ; return ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { PointerType * PTy = dyn_cast < PointerType > ( GVar -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( EmitGeneric && ! isa < Function > ( CPV ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; O << * getSymbol ( GVar ) ; O << <STR_LIT> ; } else { O << * getSymbol ( GVar ) ; } return ; } if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; PointerType * PTy = dyn_cast < PointerType > ( Cexpr -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; O << * getSymbol ( GVar ) ; O << <STR_LIT> ; } else { O << * getSymbol ( GVar ) ; }"
LLVM,NVPTX,313,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; int n = regmap . size ( ) ; regmap . insert ( std :: make_pair ( vr , n + <NUM_LIT> ) ) ; } for ( unsigned i = <NUM_LIT> ; i < TRI -> getNumRegClasses ( ) ; i ++ ) { const TargetRegisterClass * RC = TRI -> getRegClass ( i ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; std :: string rcname = get<ISA_LIT>RegClassName ( RC ) ; std :: string rcStr = get<ISA_LIT>RegClassStr ( RC ) ; int n = regmap . size ( ) ; if ( n ) {"
LLVM,NVPTX,314,"Predict the next statement of this code snippet:
 <s> } if ( const Instruction * instr = dyn_cast < Instruction > ( U ) ) { if ( instr -> getParent ( ) && instr -> getParent ( ) -> getParent ( ) ) { const Function * curFunc = instr -> getParent ( ) -> getParent ( ) ; if ( oneFunc && ( curFunc != oneFunc ) ) return false ; oneFunc = curFunc ; return true ; } else return false ; } for ( const User * UU : U -> users ( ) ) if ( usedInOneFunc ( UU , oneFunc ) == false ) return false ; return true ;"
LLVM,NVPTX,315,"Predict the next statement of this code snippet:
 <s> if ( instr -> getParent ( ) && instr -> getParent ( ) -> getParent ( ) ) { const Function * curFunc = instr -> getParent ( ) -> getParent ( ) ; if ( oneFunc && ( curFunc != oneFunc ) ) return false ;"
LLVM,NVPTX,316,"Predict the next statement of this code snippet:
 <s> else O << <STR_LIT> ; printReturnValStr ( F , O ) ; O << getSymbolName ( F ) << <STR_LIT> ; emitFunctionParamList ( F , O ) ; O << <STR_LIT> ;"
LLVM,NVPTX,317,"Predict the next statement of this code snippet:
 <s> continue ; } if ( PAL . hasAttribute ( paramIndex + <NUM_LIT> , Attribute :: ByVal ) == false ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( Ty ) ; unsigned sz = TD -> getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; }"
LLVM,NVPTX,318,"Predict the next statement of this code snippet:
 <s> if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( ETy ) ; unsigned sz = TD -> getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ;"
LLVM,NVPTX,319,"Predict the next statement of this code snippet:
 <s> emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isSingleValueType ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << getSymbolName ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> << getSymbolName ( GVar ) << <STR_LIT> ; if ( ElementSize ) { O << itostr ( ElementSize ) ; } O << <STR_LIT> ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ;"
LLVM,NVPTX,320,"Predict the next statement of this code snippet:
 <s> switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> << getSymbolName ( GVar ) << <STR_LIT> ; if ( ElementSize ) { O << itostr ( ElementSize ) ; } O << <STR_LIT> ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } return ;"
LLVM,NVPTX,321,"Predict the next statement of this code snippet:
 <s> MCSymbol * Sym = getSymbol ( GV ) ; std :: string OriginalName ; raw_string_ostream OriginalNameStream ( OriginalName ) ; Sym -> print ( OriginalNameStream ) ; OriginalNameStream . flush ( ) ; std :: string CleanName ; raw_string_ostream CleanNameStream ( CleanName ) ; for ( unsigned I = <NUM_LIT> , E = OriginalName . size ( ) ; I != E ; ++ I ) { char C = OriginalName [ I ] ; if ( C == '.' ) { CleanNameStream << <STR_LIT> ;"
LLVM,NVPTX,322,"Predict the next statement of this code snippet:
 <s> std :: string OriginalName ; raw_string_ostream OriginalNameStream ( OriginalName ) ; Sym -> print ( OriginalNameStream ) ; OriginalNameStream . flush ( ) ; std :: string CleanName ; raw_string_ostream CleanNameStream ( CleanName ) ; for ( unsigned I = <NUM_LIT> , E = OriginalName . size ( ) ; I != E ; ++ I ) { char C = OriginalName [ I ] ; if ( C == '.' ) { CleanNameStream << <STR_LIT> ;"
LLVM,NVPTX,323,"Predict the next statement of this code snippet:
 <s> if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: CreateAdd ( Base , MCConstantExpr :: Create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; case Instruction :: IntToPtr : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , TD . getIntPtrType ( CV -> getContext ( ) ) , false ) ; return LowerConstant ( Op , AP ) ; } case Instruction :: PtrToInt : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = LowerConstant ( Op , AP ) ; if ( TD . getTypeAllocSize ( Ty ) == TD . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = TD . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: Create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: CreateAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: SDiv : case Instruction :: SRem : case Instruction :: Shl : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : { const MCExpr * LHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; const MCExpr * RHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; switch ( CE -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Add :"
LLVM,NVPTX,324,"Predict the next statement of this code snippet:
 <s> break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( MO , getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_FPImmediate : { const ConstantFP * Cnt = MO . getFPImm ( ) ; APFloat Val = Cnt -> getValueAPF ( ) ; switch ( Cnt -> getType ( ) -> getTypeID ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; break ; case Type :: FloatTyID : MCOp = MCOperand :: CreateExpr ( <ISA_LIT>FloatMCExpr :: CreateConstantFPSingle ( Val , OutContext ) ) ; break ; case Type :: DoubleTyID : MCOp = MCOperand :: CreateExpr ( <ISA_LIT>FloatMCExpr :: CreateConstantFPDouble ( Val , OutContext ) ) ;"
LLVM,NVPTX,325,"Predict the next statement of this code snippet:
 <s> case MachineOperand :: MO_Register : MCOp = MCOperand :: CreateReg ( encodeVirtualRegister ( MO . getReg ( ) ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , OutContext ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( MO , getSymbol ( MO . getGlobal ( ) ) ) ; break ;"
LLVM,NVPTX,326,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; if ( lowerOperand ( MO , MCOp ) ) OutMI . addOperand ( MCOp ) ;"
LLVM,NVPTX,327,"Predict the next statement of this code snippet:
 <s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { if ( MO . getReg ( ) == <STR_LIT> ) O << DEPOTNAME << getFunctionNumber ( ) ; else O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; } else { emitVirtualRegister ( MO . getReg ( ) , O ) ; } return ; case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : O << getSymbolName ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock :"
LLVM,NVPTX,328,"Predict the next statement of this code snippet:
 <s> } return ; case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress :"
LLVM,NVPTX,329,"Predict the next statement of this code snippet:
 <s> } if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ) { printFPConstant ( CFP , O ) ; return ; } if ( isa < ConstantPointerNull > ( CPV ) ) { O << <STR_LIT> ; return ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { O << getSymbolName ( GVar ) ;"
LLVM,NVPTX,330,"Predict the next statement of this code snippet:
 <s> const Function * oneFunc = nullptr ; bool flag = usedInOneFunc ( gv , oneFunc ) ; if ( ! flag ) return false ; if ( ! oneFunc ) return false ; f = oneFunc ; return true ;"
LLVM,NVPTX,331,"Predict the next statement of this code snippet:
 <s> Mang = new Mangler ( TM . getDataLayout ( ) ) ; emitHeader ( M , OS1 , STI ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ;"
LLVM,NVPTX,332,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: doInitialization ( Module & M ) { StringRef TT = TM . getTargetTriple ( ) ; StringRef CPU = TM . getTargetCPU ( ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , NTM ) ; SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( TM . getDataLayout ( ) ) ; emitHeader ( M , OS1 , STI ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) {"
LLVM,NVPTX,333,"Predict the next statement of this code snippet:
 <s> case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( ETy ) ; unsigned sz = TD -> getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , ETy , vtparts ) ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ paramIndex ; } if ( i < e - <NUM_LIT> ) O << <STR_LIT> ; } -- paramIndex ; continue ; }"
LLVM,NVPTX,334,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitImplicitDef ( const MachineInstr * MI ) const { unsigned RegNo = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegNo ) ) { OutStreamer . AddComment ( Twine ( <STR_LIT> ) + getVirtualRegisterName ( RegNo ) ) ; } else { OutStreamer . AddComment ( Twine ( <STR_LIT> ) + nvptxSubtarget -> getRegisterInfo ( ) -> getName ( RegNo ) ) ; }"
LLVM,NVPTX,335,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ;"
LLVM,NVPTX,336,"Predict the next statement of this code snippet:
 <s> } if ( filenameMap . find ( fileName ) == filenameMap . end ( ) ) return ; if ( InterleaveSrc ) this -> emitSrcInText ( fileName , curLoc . getLine ( ) ) ; std :: stringstream temp ; temp << <STR_LIT> << filenameMap [ fileName ] << <STR_LIT> << curLoc . getLine ( ) << <STR_LIT> << curLoc . getCol ( ) ; OutStreamer . EmitRawText ( temp . str ( ) ) ;"
LLVM,NVPTX,337,"Predict the next statement of this code snippet:
 <s> temp << filename . str ( ) ; temp << <STR_LIT> ; temp << line ; temp << <STR_LIT> ;"
LLVM,NVPTX,338,"Predict the next statement of this code snippet:
 <s> temp << line ; temp << <STR_LIT> ; temp << reader -> readLine ( line ) ; temp << <STR_LIT> ;"
LLVM,NVPTX,339,"Predict the next statement of this code snippet:
 <s> break ; } break ; } case Type :: FloatTyID : return <STR_LIT> ; case Type :: DoubleTyID : return <STR_LIT> ; case Type :: PointerTyID : if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is64Bit ( ) ) if ( useB4PTR ) return <STR_LIT> ; else return <STR_LIT> ; else if ( useB4PTR ) return <STR_LIT> ; else return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,340,"Predict the next statement of this code snippet:
 <s> OutMI . addOperand ( GetSymbolRef ( OutContext . GetOrCreateSymbol ( Twine ( MO . getSymbolName ( ) ) ) ) ) ; return ; } for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; if ( ! nvptxSubtarget -> hasImageHandles ( ) ) { if ( lowerImageHandleOperand ( MI , i , MCOp ) ) { OutMI . addOperand ( MCOp ) ; continue ; } } if ( lowerOperand ( MO , MCOp ) ) OutMI . addOperand ( MCOp ) ; }"
LLVM,NVPTX,341,"Predict the next statement of this code snippet:
 <s> if ( MI -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; OutMI . addOperand ( GetSymbolRef ( OutContext . GetOrCreateSymbol ( Twine ( MO . getSymbolName ( ) ) ) ) ) ; return ; } for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; if ( ! nvptxSubtarget -> hasImageHandles ( ) ) { if ( lowerImageHandleOperand ( MI , i , MCOp ) ) { OutMI . addOperand ( MCOp ) ; continue ;"
LLVM,NVPTX,342,"Predict the next statement of this code snippet:
 <s> else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; if ( ETy -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( ETy , false ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; if ( GVar -> hasInitializer ( ) ) { if ( ( PTy -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GLOBAL ) || ( PTy -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_CONST ) ) { const Constant * Initializer = GVar -> getInitializer ( ) ; if ( ! Initializer -> isNullValue ( ) && ! isa < UndefValue > ( Initializer ) ) { O << <STR_LIT> ; printScalarConstant ( Initializer , O ) ; } } else { if ( ! GVar -> getInitializer ( ) -> isNullValue ( ) ) { std :: string warnMsg = ( <STR_LIT> + GVar -> getName ( ) + <STR_LIT> + Twine ( llvm :: utostr_32 ( PTy -> getAddressSpace ( ) ) ) + <STR_LIT> ) . str ( ) ; report_fatal_error ( warnMsg . c_str ( ) ) ; } } } } else { unsigned int ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; if ( ( ( PTy -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GLOBAL ) || ( PTy -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_CONST ) ) && GVar -> hasInitializer ( ) ) { const Constant * Initializer = GVar -> getInitializer ( ) ; if ( ! isa < UndefValue > ( Initializer ) && ! Initializer -> isNullValue ( ) ) { AggBuffer aggBuffer ( ElementSize , O , * this ) ; bufferAggregateConstant ( Initializer , & aggBuffer ) ; if ( aggBuffer . numSymbols ) { if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is64Bit ( ) ) { O << <STR_LIT> << * getSymbol ( GVar ) << <STR_LIT> ; O << ElementSize / <NUM_LIT> ; } else { O << <STR_LIT> << * getSymbol ( GVar ) << <STR_LIT> ; O << ElementSize / <NUM_LIT> ; } O << <STR_LIT> ; } else { O << <STR_LIT> << * getSymbol ( GVar ) << <STR_LIT> ; O << ElementSize ; O << <STR_LIT> ; } O << <STR_LIT> ; aggBuffer . print ( ) ; O << <STR_LIT> ; } else { O << <STR_LIT> << * getSymbol ( GVar ) ;"
LLVM,NVPTX,343,"Predict the next statement of this code snippet:
 <s> if ( GVar -> use_empty ( ) ) return ; } const Function * demotedFunc = nullptr ; if ( ! processDemoted && canDemoteGlobalVar ( GVar , demotedFunc ) ) { O << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> ; if ( localDecls . find ( demotedFunc ) != localDecls . end ( ) ) localDecls [ demotedFunc ] . push_back ( GVar ) ; else { std :: vector < const GlobalVariable * > temp ; temp . push_back ( GVar ) ; localDecls [ demotedFunc ] = temp ; } return ; } O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( isManaged ( * GVar ) ) { O << <STR_LIT> ; } if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; if ( ETy -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( ETy , false ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; if ( GVar -> hasInitializer ( ) ) { if ( ( PTy -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GLOBAL ) || ( PTy -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_CONST ) ) { const Constant * Initializer = GVar -> getInitializer ( ) ; if ( ! Initializer -> isNullValue ( ) && ! isa < UndefValue > ( Initializer ) ) { O << <STR_LIT> ; printScalarConstant ( Initializer , O ) ; } } else { if ( ! GVar -> getInitializer ( ) -> isNullValue ( ) ) { std :: string warnMsg = ( <STR_LIT> + GVar -> getName ( ) + <STR_LIT> + Twine ( llvm :: utostr_32 ( PTy -> getAddressSpace ( ) ) ) + <STR_LIT> ) . str ( ) ; report_fatal_error ( warnMsg . c_str ( ) ) ; } } } } else { unsigned int ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID :"
LLVM,NVPTX,344,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printParamName ( int paramIndex , raw_ostream & O ) { O << * CurrentFnSym << <STR_LIT> << paramIndex ;"
LLVM,NVPTX,345,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; if ( isABI ) { if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( const IntegerType * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; if ( size < <NUM_LIT> ) size = <NUM_LIT> ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( ( Ty -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( Ty ) ) { unsigned totalsz = TD -> getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) {"
LLVM,NVPTX,346,"Predict the next statement of this code snippet:
 <s> } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> << idx ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ idx ; } if ( i < e - <NUM_LIT> ) O << <STR_LIT> ; } } O << <STR_LIT> ;"
LLVM,NVPTX,347,"Predict the next statement of this code snippet:
 <s> DebugInfoFinder DbgFinder ; DbgFinder . processModule ( M ) ; unsigned i = <NUM_LIT> ; for ( const MDCompileUnit * DIUnit : DbgFinder . compile_units ( ) ) { StringRef Filename = DIUnit -> getFilename ( ) ; StringRef Dirname = DIUnit -> getDirectory ( ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName ; } if ( filenameMap . find ( Filename ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename ] = i ; OutStreamer . EmitDwarfFileDirective ( i , <STR_LIT> , Filename ) ; ++ i ; } for ( MDSubprogram * SP : DbgFinder . subprograms ( ) ) { StringRef Filename = SP -> getFilename ( ) ; StringRef Dirname = SP -> getDirectory ( ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ;"
LLVM,NVPTX,348,"Predict the next statement of this code snippet:
 <s> unsigned i = <NUM_LIT> ; for ( const MDCompileUnit * DIUnit : DbgFinder . compile_units ( ) ) { StringRef Filename = DIUnit -> getFilename ( ) ; StringRef Dirname = DIUnit -> getDirectory ( ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName ; } if ( filenameMap . find ( Filename ) != filenameMap . end ( ) ) continue ;"
LLVM,NVPTX,349,"Predict the next statement of this code snippet:
 <s> } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = TRI -> index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; int n = regmap . size ( ) ; regmap . insert ( std :: make_pair ( vr , n + <NUM_LIT> ) ) ; } for ( unsigned i = <NUM_LIT> ; i < TRI -> getNumRegClasses ( ) ; i ++ ) { const TargetRegisterClass * RC = TRI -> getRegClass ( i ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; std :: string rcname = get<ISA_LIT>RegClassName ( RC ) ;"
LLVM,NVPTX,350,"Predict the next statement of this code snippet:
 <s> if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( C ) ) { if ( GV -> getName ( ) == <STR_LIT> ) return false ; return true ; } for ( const User * U : C -> users ( ) ) if ( const Constant * C = dyn_cast < Constant > ( U ) ) if ( usedInGlobalVarDef ( C ) ) return true ; return false ;"
LLVM,NVPTX,351,"Predict the next statement of this code snippet:
 <s> if ( F -> arg_empty ( ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; for ( I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , paramIndex ++ ) { Type * Ty = I -> getType ( ) ; if ( ! first ) O << <STR_LIT> ; first = false ; if ( isKernelFunction ( * F ) ) { if ( isSampler ( * I ) || isImage ( * I ) ) { if ( isImage ( * I ) ) { std :: string sname = I -> getName ( ) ; if ( isImageWriteOnly ( * I ) || isImageReadWrite ( * I ) ) { if ( nvptxSubtarget -> hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; CurrentFnSym -> print ( O , MAI ) ; O << <STR_LIT> << paramIndex ; } else { if ( nvptxSubtarget -> hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; CurrentFnSym -> print ( O , MAI ) ; O << <STR_LIT> << paramIndex ; } } else { if ( nvptxSubtarget -> hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; CurrentFnSym -> print ( O , MAI ) ; O << <STR_LIT> << paramIndex ; } continue ; } } if ( ! PAL . hasAttribute ( paramIndex + <NUM_LIT> , Attribute :: ByVal ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( static_cast < <ISA_LIT>TargetMachine & > ( TM ) . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; }"
LLVM,NVPTX,352,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>AsmPrinter :: encodeVirtualRegister ( unsigned Reg ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { const TargetRegisterClass * RC = MRI -> getRegClass ( Reg ) ; DenseMap < unsigned , unsigned > & RegMap = VRegMapping [ RC ] ; unsigned RegNum = RegMap [ Reg ] ; unsigned Ret = <NUM_LIT> ; if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) {"
LLVM,NVPTX,353,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printReturnValStr ( const Function * F , raw_ostream & O ) { const DataLayout & DL = getDataLayout ( ) ; const TargetLowering * TLI = nvptxSubtarget -> getTargetLowering ( ) ; Type * Ty = F -> getReturnType ( ) ; bool isABI = ( nvptxSubtarget -> getSmVersion ( ) >= <NUM_LIT> ) ; if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return ; O << <STR_LIT> ; if ( isABI ) { if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( auto * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } if ( size < <NUM_LIT> ) size = <NUM_LIT> ; O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( DL ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned totalsz = DL . getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = DL . getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ;"
LLVM,NVPTX,354,"Predict the next statement of this code snippet:
 <s> AggBuffer ( unsigned _size , raw_ostream & _O , <ISA_LIT>AsmPrinter & _AP ) : O ( _O ) , AP ( _AP ) { buffer = new unsigned char [ _size ] ;"
LLVM,NVPTX,355,"Predict the next statement of this code snippet:
 <s> } Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = <NUM_LIT> ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; if ( HasDebugInfo ) OutStreamer -> EmitRawText ( <STR_LIT> ) ;"
LLVM,NVPTX,356,"Predict the next statement of this code snippet:
 <s> for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; if ( HasDebugInfo ) OutStreamer -> EmitRawText ( <STR_LIT> ) ;"
LLVM,NVPTX,357,"Predict the next statement of this code snippet:
 <s> bool Result = AsmPrinter :: doInitialization ( M ) ; emitHeader ( M , OS1 , STI ) ; OutStreamer -> EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> AddBlankLine ( ) ; OutStreamer -> EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer -> AddBlankLine ( ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> AddBlankLine ( ) ; }"
LLVM,NVPTX,358,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) {"
LLVM,NVPTX,359,"Predict the next statement of this code snippet:
 <s> VRegMapping . clear ( ) ;"
LLVM,NVPTX,360,"Predict the next statement of this code snippet:
 <s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ;"
LLVM,NVPTX,361,"Predict the next statement of this code snippet:
 <s> emitDemotedVars ( & MF -> getFunction ( ) , O ) ;"
LLVM,NVPTX,362,"Predict the next statement of this code snippet:
 <s> else { O << <STR_LIT> ; printReturnValStr ( * MF , O ) ; } CurrentFnSym -> print ( O , MAI ) ; emitFunctionParamList ( * MF , O ) ; if ( isKernelFunction ( * F ) ) emitKernelFunctionDirectives ( * F , O ) ; OutStreamer -> EmitRawText ( O . str ( ) ) ; VRegMapping . clear ( ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ;"
LLVM,NVPTX,363,"Predict the next statement of this code snippet:
 <s> CurrentFnSym -> print ( O , MAI ) ; emitFunctionParamList ( * MF , O ) ; if ( isKernelFunction ( * F ) ) emitKernelFunctionDirectives ( * F , O ) ; OutStreamer -> EmitRawText ( O . str ( ) ) ; VRegMapping . clear ( ) ;"
LLVM,NVPTX,364,"Predict the next statement of this code snippet:
 <s> unsigned RegNo = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegNo ) ) { OutStreamer -> AddComment ( Twine ( <STR_LIT> ) + getVirtualRegisterName ( RegNo ) ) ; } else { const <ISA_LIT>Subtarget & STI = MI -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; OutStreamer -> AddComment ( Twine ( <STR_LIT> ) + STI . getRegisterInfo ( ) -> getName ( RegNo ) ) ;"
LLVM,NVPTX,365,"Predict the next statement of this code snippet:
 <s> unsigned RegNo = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegNo ) ) { OutStreamer -> AddComment ( Twine ( <STR_LIT> ) + getVirtualRegisterName ( RegNo ) ) ; } else { const <ISA_LIT>Subtarget & STI = MI -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; OutStreamer -> AddComment ( Twine ( <STR_LIT> ) + STI . getRegisterInfo ( ) -> getName ( RegNo ) ) ; }"
LLVM,NVPTX,366,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst Inst ; lowerToMCInst ( MI , Inst ) ;"
LLVM,NVPTX,367,"Predict the next statement of this code snippet:
 <s> if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntOrPtrTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ;"
LLVM,NVPTX,368,"Predict the next statement of this code snippet:
 <s> } if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntOrPtrTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; if ( ElementSize ) { O << ElementSize ; } O << <STR_LIT> ;"
LLVM,NVPTX,369,"Predict the next statement of this code snippet:
 <s> Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) {"
LLVM,NVPTX,370,"Predict the next statement of this code snippet:
 <s> PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : LLVM_FALLTHROUGH ; case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : { const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , DL . getIntPtrType ( CV -> getType ( ) ) , false ) ; return lowerConstantForGV ( Op , ProcessingGeneric ) ; } case Instruction :: PtrToInt : { const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = lowerConstantForGV ( Op , ProcessingGeneric ) ; if ( DL . getTypeAllocSize ( Ty ) == DL . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = DL . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: createAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : { const MCExpr * LHS = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; const MCExpr * RHS = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; switch ( CE -> getOpcode ( ) ) {"
LLVM,NVPTX,371,"Predict the next statement of this code snippet:
 <s> } } const ConstantExpr * CE = dyn_cast < ConstantExpr > ( CV ) ; if ( ! CE ) { llvm_unreachable ( <STR_LIT> ) ; } switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstant ( CE , getDataLayout ( ) ) ) if ( C && C != CE ) return lowerConstantForGV ( C , ProcessingGeneric ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : LLVM_FALLTHROUGH ; case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : {"
LLVM,NVPTX,372,"Predict the next statement of this code snippet:
 <s> for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . Mang -> getSymbol ( GVar ) ; O << * Name ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) { O << * <STR_LIT> ( Cexpr , AP ) ; } else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,373,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> ; i < size ; i ++ ) { if ( i ) O << <STR_LIT> ; O << ( unsigned int ) buffer [ i ] ; } } else { unsigned int pos = <NUM_LIT> ; unsigned int nSym = <NUM_LIT> ; unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( AP . nvptxSubtarget . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . Mang -> getSymbol ( GVar ) ; O << * Name ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) { O << * <STR_LIT> ( Cexpr , AP ) ; } else llvm_unreachable ( <STR_LIT> ) ; nSym ++ ;"
LLVM,NVPTX,374,"Predict the next statement of this code snippet:
 <s> bool Result = AsmPrinter :: runOnMachineFunction ( F ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ;"
LLVM,NVPTX,375,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & F ) { bool Result = AsmPrinter :: runOnMachineFunction ( F ) ;"
LLVM,NVPTX,376,"Predict the next statement of this code snippet:
 <s> if ( GlobalVariable * GV = dyn_cast < GlobalVariable > ( V ) ) Globals . insert ( GV ) ; else { if ( User * U = dyn_cast < User > ( V ) ) { for ( unsigned i = <NUM_LIT> , e = U -> getNumOperands ( ) ; i != e ; ++ i ) {"
LLVM,NVPTX,377,"Predict the next statement of this code snippet:
 <s> MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( OutContext , * TM . getDataLayout ( ) ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; SmallString < <NUM_LIT> > Str2 ; raw_svector_ostream OS2 ( Str2 ) ; emitDeclarations ( M , OS2 ) ; SmallVector < GlobalVariable * , <NUM_LIT> > Globals ; DenseSet < GlobalVariable * > GVVisited ; DenseSet < GlobalVariable * > GVVisiting ;"
LLVM,NVPTX,378,"Predict the next statement of this code snippet:
 <s> const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST_NOT_GEN : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> << getPTXFundamentalTypeStr ( Ty ) << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( ETy ) ; unsigned sz = TD -> getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , ETy , vtparts ) ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ;"
LLVM,NVPTX,379,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; unsigned PTXVersion = nvptxSubtarget . getPTXVersion ( ) ; O << <STR_LIT> << ( PTXVersion / <NUM_LIT> ) << <STR_LIT> << ( PTXVersion % <NUM_LIT> ) << <STR_LIT> ; O << <STR_LIT> ; O << nvptxSubtarget . getTargetName ( ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( ! nvptxSubtarget . hasDouble ( ) ) O << <STR_LIT> ; } if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << <STR_LIT> ;"
LLVM,NVPTX,380,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; unsigned PTXVersion = nvptxSubtarget . getPTXVersion ( ) ; O << <STR_LIT> << ( PTXVersion / <NUM_LIT> ) << <STR_LIT> << ( PTXVersion % <NUM_LIT> ) << <STR_LIT> ; O << <STR_LIT> ; O << nvptxSubtarget . getTargetName ( ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( ! nvptxSubtarget . hasDouble ( ) ) O << <STR_LIT> ; } if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ;"
LLVM,NVPTX,381,"Predict the next statement of this code snippet:
 <s> if ( STy ) { unsigned int alignStruct = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; i ++ ) { Type * ETy = STy -> getElementType ( i ) ; unsigned int align = getOpenCLAlignment ( TD , ETy ) ; if ( align > alignStruct ) alignStruct = align ; } return alignStruct ; } const FunctionType * FTy = dyn_cast < FunctionType > ( Ty ) ; if ( FTy ) return TD -> getPointerPrefAlignment ( ) ; return TD -> getPrefTypeAlignment ( Ty ) ;"
LLVM,NVPTX,382,"Predict the next statement of this code snippet:
 <s> if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: CreateAdd ( Base , MCConstantExpr :: Create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; case Instruction :: IntToPtr : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , TD . getIntPtrType ( CV -> getContext ( ) ) , false ) ; return LowerConstant ( Op , AP ) ; } case Instruction :: PtrToInt : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = LowerConstant ( Op , AP ) ; if ( TD . getTypeAllocSize ( Ty ) == TD . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = TD . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: Create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: CreateAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: SDiv : case Instruction :: SRem : case Instruction :: Shl : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : { const MCExpr * LHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; const MCExpr * RHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; switch ( CE -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Add : return MCBinaryExpr :: CreateAdd ( LHS , RHS , Ctx ) ; case Instruction :: Sub : return MCBinaryExpr :: CreateSub ( LHS , RHS , Ctx ) ; case Instruction :: Mul : return MCBinaryExpr :: CreateMul ( LHS , RHS , Ctx ) ; case Instruction :: SDiv : return MCBinaryExpr :: CreateDiv ( LHS , RHS , Ctx ) ;"
LLVM,NVPTX,383,"Predict the next statement of this code snippet:
 <s> if ( ! nvptxSubtarget . hasGenericLdSt ( ) ) O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm == <STR_LIT> :: Signed ) O << <STR_LIT> ; else if ( Imm == <STR_LIT> :: Unsigned ) O << <STR_LIT> ; else O << <STR_LIT> ; } else if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm == <STR_LIT> :: V2 ) O << <STR_LIT> ;"
LLVM,NVPTX,384,"Predict the next statement of this code snippet:
 <s> Visiting . insert ( GV ) ; DenseSet < GlobalVariable * > Others ; for ( unsigned i = <NUM_LIT> , e = GV -> getNumOperands ( ) ; i != e ; ++ i ) DiscoverDependentGlobals ( GV -> getOperand ( i ) , Others ) ; for ( DenseSet < GlobalVariable * > :: iterator I = Others . begin ( ) , E = Others . end ( ) ; I != E ; ++ I ) VisitGlobalVariableForEmission ( * I , Order , Visited , Visiting ) ; Order . push_back ( GV ) ;"
LLVM,NVPTX,385,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { VRegMapping . clear ( ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; setAndEmitFunctionVirtualRegisters ( * MF ) ;"
LLVM,NVPTX,386,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { VRegMapping . clear ( ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; setAndEmitFunctionVirtualRegisters ( * MF ) ;"
LLVM,NVPTX,387,"Predict the next statement of this code snippet:
 <s> } MRI = & MF -> getRegInfo ( ) ; F = & MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( isKernelFunction ( * F ) ) O << <STR_LIT> ; else { O << <STR_LIT> ; printReturnValStr ( * MF , O ) ; } CurrentFnSym -> print ( O , MAI ) ; emitFunctionParamList ( * MF , O ) ; if ( isKernelFunction ( * F ) ) emitKernelFunctionDirectives ( * F , O ) ; OutStreamer -> EmitRawText ( O . str ( ) ) ;"
LLVM,NVPTX,388,"Predict the next statement of this code snippet:
 <s> O << STI . getTargetName ( ) ; const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; if ( NTM . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ;"
LLVM,NVPTX,389,"Predict the next statement of this code snippet:
 <s> if ( localDecls . find ( f ) == localDecls . end ( ) ) return ; std :: vector < const GlobalVariable * > & gvars = localDecls [ f ] ; const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget & STI = * static_cast < const <ISA_LIT>Subtarget * > ( NTM . getSubtargetImpl ( ) ) ; for ( const GlobalVariable * GV : gvars ) { O << <STR_LIT> ; printModuleLevelGV ( GV , O , true , STI ) ; }"
LLVM,NVPTX,390,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ;"
LLVM,NVPTX,391,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitGlobals ( const Module & M ) { SmallString < <NUM_LIT> > Str2 ; raw_svector_ostream OS2 ( Str2 ) ; emitDeclarations ( M , OS2 ) ; SmallVector < const GlobalVariable * , <NUM_LIT> > Globals ; DenseSet < const GlobalVariable * > GVVisited ; DenseSet < const GlobalVariable * > GVVisiting ;"
LLVM,NVPTX,392,"Predict the next statement of this code snippet:
 <s> emitPTXAddressSpace ( GVar -> getType ( ) -> getAddressSpace ( ) , O ) ; if ( isManaged ( * GVar ) ) { if ( STI . getPTXVersion ( ) < <NUM_LIT> || STI . getSmVersion ( ) < <NUM_LIT> ) { report_fatal_error ( <STR_LIT> ) ; } O << <STR_LIT> ; } if ( MaybeAlign A = GVar -> getAlign ( ) ) O << <STR_LIT> << A -> value ( ) ; else O << <STR_LIT> << ( int ) DL . getPrefTypeAlignment ( ETy ) ; if ( ETy -> isIntegerTy ( <NUM_LIT> ) ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; return ; } if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntOrPtrTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: FixedVectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; if ( ElementSize ) { O << ElementSize ;"
LLVM,NVPTX,393,"Predict the next statement of this code snippet:
 <s> const DataLayout & DL = getDataLayout ( ) ; Type * ETy = GVar -> getValueType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( GVar -> getType ( ) -> getAddressSpace ( ) , O ) ; if ( isManaged ( * GVar ) ) { if ( STI . getPTXVersion ( ) < <NUM_LIT> || STI . getSmVersion ( ) < <NUM_LIT> ) { report_fatal_error ( <STR_LIT> ) ; } O << <STR_LIT> ; } if ( MaybeAlign A = GVar -> getAlign ( ) ) O << <STR_LIT> << A -> value ( ) ; else O << <STR_LIT> << ( int ) DL . getPrefTypeAlignment ( ETy ) ; if ( ETy -> isIntegerTy ( <NUM_LIT> ) ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; return ; } if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntOrPtrTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: FixedVectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ;"
LLVM,NVPTX,394,"Predict the next statement of this code snippet:
 <s> const MCSymbol * <ISA_LIT>AsmPrinter :: getFunctionFrameSymbol ( int ) const { SmallString < <NUM_LIT> > Str ; raw_svector_ostream ( Str ) << DEPOTNAME << getFunctionNumber ( ) ; return OutContext . getOrCreateSymbol ( Str ) ;"
LLVM,NVPTX,395,"Predict the next statement of this code snippet:
 <s> int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = <NUM_LIT> ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; if ( HasDebugInfo ) { static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> closeLastSection ( ) ; OutStreamer -> EmitRawText ( <STR_LIT> ) ; } static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> outputDwarfFileDirectives ( ) ; return ret ;"
LLVM,NVPTX,396,"Predict the next statement of this code snippet:
 <s> for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; if ( HasDebugInfo ) { static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> closeLastSection ( ) ; OutStreamer -> EmitRawText ( <STR_LIT> ) ; } static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> outputDwarfFileDirectives ( ) ;"
LLVM,NVPTX,397,"Predict the next statement of this code snippet:
 <s> AsmPrinter :: EmitBasicBlockStart ( MBB ) ; if ( isLoopHeaderOfNoUnroll ( MBB ) ) OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ;"
LLVM,NVPTX,398,"Predict the next statement of this code snippet:
 <s> DenseMap < const Function * , bool > seenMap ; for ( Module :: const_iterator FI = M . begin ( ) , FE = M . end ( ) ; FI != FE ; ++ FI ) { const Function * F = & * FI ; if ( F -> getAttributes ( ) . hasFnAttribute ( <STR_LIT> ) ) { emitDeclaration ( F , O ) ; continue ; } if ( F -> isDeclaration ( ) ) { if ( F -> use_empty ( ) ) continue ; if ( F -> getIntrinsicID ( ) ) continue ; emitDeclaration ( F , O ) ; continue ; }"
LLVM,NVPTX,399,"Predict the next statement of this code snippet:
 <s> continue ; } for ( const User * U : F -> users ( ) ) { if ( const Constant * C = dyn_cast < Constant > ( U ) ) { if ( usedInGlobalVarDef ( C ) ) { emitDeclaration ( F , O ) ; break ; } if ( useFuncSeen ( C , seenMap ) ) { emitDeclaration ( F , O ) ; break ; } } if ( ! isa < Instruction > ( U ) ) continue ; const Instruction * instr = cast < Instruction > ( U ) ; const BasicBlock * bb = instr -> getParent ( ) ; if ( ! bb ) continue ; const Function * caller = bb -> getParent ( ) ; if ( ! caller ) continue ; if ( seenMap . find ( caller ) != seenMap . end ( ) ) { emitDeclaration ( F , O ) ; break ; }"
LLVM,NVPTX,400,"Predict the next statement of this code snippet:
 <s> CurrentFnSym -> print ( O , MAI ) ; emitFunctionParamList ( * MF , O ) ; if ( isKernelFunction ( * F ) ) emitKernelFunctionDirectives ( * F , O ) ; OutStreamer -> EmitRawText ( O . str ( ) ) ; VRegMapping . clear ( ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ;"
LLVM,NVPTX,401,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; printReturnValStr ( * MF , O ) ; } CurrentFnSym -> print ( O , MAI ) ; emitFunctionParamList ( * MF , O ) ; if ( isKernelFunction ( * F ) ) emitKernelFunctionDirectives ( * F , O ) ; OutStreamer -> EmitRawText ( O . str ( ) ) ; VRegMapping . clear ( ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ;"
LLVM,NVPTX,402,"Predict the next statement of this code snippet:
 <s> } O << <STR_LIT> << ( int ) getOpenCLAlignment ( DL , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { Align align = DL . getValueOrABITypeAlignment ( PAL . getParamAlignment ( paramIndex ) , ETy ) ; if ( ! isKernelFunc && align < Align ( <NUM_LIT> ) ) align = Align ( <NUM_LIT> ) ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align . value ( ) << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , ETy , vtparts ) ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ paramIndex ; } if ( i < e - <NUM_LIT> ) O << <STR_LIT> ; }"
LLVM,NVPTX,403,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: setAndEmitFunctionVirtualRegisters ( const MachineFunction & MF ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; if ( NumBytes ) { O << <STR_LIT> << MFI . getMaxAlignment ( ) << <STR_LIT> << DEPOTNAME << getFunctionNumber ( ) << <STR_LIT> << NumBytes << <STR_LIT> ; if ( static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . is64Bit ( ) ) { O << <STR_LIT> ; O << <STR_LIT> ; } else { O << <STR_LIT> ; O << <STR_LIT> ; } } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = Register :: index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; int n = regmap . size ( ) ; regmap . insert ( std :: make_pair ( vr , n + <NUM_LIT> ) ) ; } for ( unsigned i = <NUM_LIT> ; i < TRI -> getNumRegClasses ( ) ; i ++ ) {"
LLVM,NVPTX,404,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; } } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = Register :: index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; int n = regmap . size ( ) ; regmap . insert ( std :: make_pair ( vr , n + <NUM_LIT> ) ) ; } for ( unsigned i = <NUM_LIT> ; i < TRI -> getNumRegClasses ( ) ; i ++ ) { const TargetRegisterClass * RC = TRI -> getRegClass ( i ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; std :: string rcname = get<ISA_LIT>RegClassName ( RC ) ;"
LLVM,NVPTX,405,"Predict the next statement of this code snippet:
 <s> break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST : if ( nvptxSubtarget . hasGenericLdSt ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST_NOT_GEN :"
LLVM,NVPTX,406,"Predict the next statement of this code snippet:
 <s> break ; case llvm :: ADDRESS_SPACE_CONST_NOT_GEN : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> ) ; break ;"
LLVM,NVPTX,407,"Predict the next statement of this code snippet:
 <s> unsigned id = RC -> getID ( ) ; std :: map < unsigned , unsigned > & regmap = VRidGlobal2LocalMap [ id ] ; unsigned mapped_vr = regmap [ vr ] ; if ( ! isVec ) { O << get<ISA_LIT>RegClassStr ( RC ) << mapped_vr ;"
LLVM,NVPTX,408,"Predict the next statement of this code snippet:
 <s> switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,409,"Predict the next statement of this code snippet:
 <s> } else { unsigned int pos = <NUM_LIT> ; unsigned int nSym = <NUM_LIT> ; unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( static_cast < const <ISA_LIT>TargetMachine & > ( AP . TM ) . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; const Value * v0 = SymbolsBeforeStripping [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . getSymbol ( GVar ) ; PointerType * PTy = dyn_cast < PointerType > ( v0 -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ;"
LLVM,NVPTX,410,"Predict the next statement of this code snippet:
 <s> } } else { unsigned int pos = <NUM_LIT> ; unsigned int nSym = <NUM_LIT> ; unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( static_cast < const <ISA_LIT>TargetMachine & > ( AP . TM ) . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; const Value * v0 = SymbolsBeforeStripping [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . getSymbol ( GVar ) ; PointerType * PTy = dyn_cast < PointerType > ( v0 -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; O << * Name ; O << <STR_LIT> ;"
LLVM,NVPTX,411,"Predict the next statement of this code snippet:
 <s> GlobalsEmitted = true ; } bool ret = AsmPrinter :: doFinalization ( M ) ; clearAnnotationCache ( & M ) ; if ( auto * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) { if ( HasDebugInfo ) { TS -> closeLastSection ( ) ; OutStreamer -> emitRawText ( <STR_LIT> ) ; }"
LLVM,NVPTX,412,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( * F ) ; const auto * TLI = cast < <ISA_LIT>TargetLowering > ( STI . getTargetLowering ( ) ) ; Function :: const_arg_iterator I , E ; unsigned paramIndex = <NUM_LIT> ; bool first = true ; bool isKernelFunc = isKernelFunction ( * F ) ; bool isABI = ( STI . getSmVersion ( ) >= <NUM_LIT> ) ; bool hasImageHandles = STI . hasImageHandles ( ) ; MVT thePointerTy = TLI -> getPointerTy ( DL ) ; if ( F -> arg_empty ( ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; for ( I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , paramIndex ++ ) { Type * Ty = I -> getType ( ) ; if ( ! first ) O << <STR_LIT> ; first = false ; if ( isKernelFunction ( * F ) ) { if ( isSampler ( * I ) || isImage ( * I ) ) { if ( isImage ( * I ) ) { std :: string sname = std :: string ( I -> getName ( ) ) ; if ( isImageWriteOnly ( * I ) || isImageReadWrite ( * I ) ) { if ( hasImageHandles ) O << <STR_LIT> ; else O << <STR_LIT> ; CurrentFnSym -> print ( O , MAI ) ; O << <STR_LIT> << paramIndex ; } else { if ( hasImageHandles ) O << <STR_LIT> ; else O << <STR_LIT> ; CurrentFnSym -> print ( O , MAI ) ; O << <STR_LIT> << paramIndex ; } } else { if ( hasImageHandles ) O << <STR_LIT> ; else O << <STR_LIT> ; CurrentFnSym -> print ( O , MAI ) ; O << <STR_LIT> << paramIndex ; } continue ; } } auto getOptimalAlignForParam = [ TLI , & DL , & PAL , F , paramIndex ] ( Type * Ty ) -> Align { Align TypeAlign = TLI -> getFunctionParamOptimizedAlign ( F , Ty , DL ) ; MaybeAlign ParamAlign = PAL . getParamAlignment ( paramIndex ) ; return max ( TypeAlign , ParamAlign ) ; } ; if ( ! PAL . hasParamAttr ( paramIndex , Attribute :: ByVal ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) {"
LLVM,NVPTX,413,"Predict the next statement of this code snippet:
 <s> getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; return ; } if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntOrPtrTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: FixedVectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; if ( ElementSize ) { O << ElementSize ; } O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,NVPTX,414,"Predict the next statement of this code snippet:
 <s> } else { unsigned int pos = <NUM_LIT> ; unsigned int nSym = <NUM_LIT> ; unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( AP . nvptxSubtarget . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . getSymbol ( GVar ) ; O << * Name ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) { O << * <STR_LIT> ( Cexpr , AP ) ;"
LLVM,NVPTX,415,"Predict the next statement of this code snippet:
 <s> bool isABI = ( STI . getSmVersion ( ) >= <NUM_LIT> ) ; if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return ; O << <STR_LIT> ; if ( isABI ) { if ( Ty -> isFloatingPointTy ( ) || ( Ty -> isIntegerTy ( ) && ! Ty -> isIntegerTy ( <NUM_LIT> ) ) ) { unsigned size = <NUM_LIT> ; if ( auto * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } if ( size < <NUM_LIT> ) size = <NUM_LIT> ; O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( DL ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned totalsz = DL . getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TLI -> getFunctionParamOptimizedAlign ( F , Ty , DL ) . value ( ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ;"
LLVM,NVPTX,416,"Predict the next statement of this code snippet:
 <s> } else if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned totalsz = DL . getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TLI -> getFunctionParamOptimizedAlign ( F , Ty , DL ) . value ( ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> << idx ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ;"
LLVM,NVPTX,417,"Predict the next statement of this code snippet:
 <s> getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; } else { getSymbol ( GVar ) -> print ( O , MAI ) ; } return ; } if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( true ) ; PointerType * PTy = dyn_cast < PointerType > ( Cexpr -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; } else { getSymbol ( GVar ) -> print ( O , MAI ) ;"
LLVM,NVPTX,418,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isSingleValueType ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> << * getSymbol ( GVar ) << <STR_LIT> ; if ( ElementSize ) { O << itostr ( ElementSize ) ;"
LLVM,NVPTX,419,"Predict the next statement of this code snippet:
 <s> if ( Cexpr -> getOpcode ( ) == Instruction :: PtrToInt ) { Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr -> getOperand ( <NUM_LIT> ) ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; } case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : { const auto * CFP = cast < ConstantFP > ( CPV ) ; Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getHalfTy ( CPV -> getContext ( ) ) ) { APInt API = CFP -> getValueAPF ( ) . bitcastToAPInt ( ) ; uint16_t float16 = API . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ; ConvertIntToBytes < > ( ptr , float16 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ConvertFloatToBytes ( ptr , float32 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ; ConvertDoubleToBytes ( ptr , float64 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } break ; } case Type :: PointerTyID : { if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { aggBuffer -> addSymbol ( GVar , GVar ) ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr ) ;"
LLVM,NVPTX,420,"Predict the next statement of this code snippet:
 <s> if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { Align align = DL . getValueOrABITypeAlignment ( PAL . getParamAlignment ( paramIndex ) , ETy ) ; if ( ! isKernelFunc && align < Align ( <NUM_LIT> ) ) align = Align ( <NUM_LIT> ) ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align . value ( ) << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , ETy , vtparts ) ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ;"
LLVM,NVPTX,421,"Predict the next statement of this code snippet:
 <s> auto * STy = dyn_cast < StructType > ( Ty ) ; if ( STy ) { unsigned int alignStruct = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; i ++ ) { Type * ETy = STy -> getElementType ( i ) ; unsigned int align = getOpenCLAlignment ( DL , ETy ) ; if ( align > alignStruct ) alignStruct = align ; } return alignStruct ; } auto * FTy = dyn_cast < FunctionType > ( Ty ) ;"
LLVM,NVPTX,422,"Predict the next statement of this code snippet:
 <s> const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( getSymbol ( GV ) , Ctx ) ; if ( ProcessingGeneric ) { return <ISA_LIT>GenericMCSymbolRefExpr :: create ( Expr , Ctx ) ; } else { return Expr ; } } const ConstantExpr * CE = dyn_cast < ConstantExpr > ( CV ) ; if ( ! CE ) { llvm_unreachable ( <STR_LIT> ) ; } switch ( CE -> getOpcode ( ) ) { default : { Constant * C = ConstantFoldConstant ( CE , getDataLayout ( ) ) ; if ( C != CE ) return lowerConstantForGV ( C , ProcessingGeneric ) ; std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : LLVM_FALLTHROUGH ; case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : { const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , DL . getIntPtrType ( CV -> getType ( ) ) , false ) ; return lowerConstantForGV ( Op , ProcessingGeneric ) ; } case Instruction :: PtrToInt : { const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,423,"Predict the next statement of this code snippet:
 <s> std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; }"
LLVM,NVPTX,424,"Predict the next statement of this code snippet:
 <s> report_fatal_error ( <STR_LIT> ) ; return true ; } if ( ! isEmptyXXStructor ( M . getNamedGlobal ( <STR_LIT> ) ) ) { report_fatal_error ( <STR_LIT> ) ; return true ; } SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; bool Result = AsmPrinter :: doInitialization ( M ) ; emitHeader ( M , OS1 , * STI ) ;"
LLVM,NVPTX,425,"Predict the next statement of this code snippet:
 <s> if ( ! curLoc ) return ; DIScope Scope ( curLoc . getScope ( ) ) ; assert ( ( ! Scope || Scope . isScope ( ) ) && <STR_LIT> ) ; if ( ! Scope ) return ; StringRef fileName ( Scope . getFilename ( ) ) ; StringRef dirName ( Scope . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) { sys :: path :: append ( FullPathName , fileName ) ; fileName = FullPathName ; }"
LLVM,NVPTX,426,"Predict the next statement of this code snippet:
 <s> IsNonGenericPointer = true ; } if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; O << * Name ; O << <STR_LIT> ; } else { O << * Name ; } } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) { O << * <STR_LIT> ( Cexpr , AP ) ; } else llvm_unreachable ( <STR_LIT> ) ; nSym ++ ; if ( nSym >= numSymbols ) nextSymbolPos = size + <NUM_LIT> ; else nextSymbolPos = symbolPosInBuffer [ nSym ] ; } else if ( nBytes == <NUM_LIT> ) O << * ( unsigned int * ) ( & buffer [ pos ] ) ; else O << * ( unsigned long long * ) ( & buffer [ pos ] ) ; } }"
LLVM,NVPTX,427,"Predict the next statement of this code snippet:
 <s> Filename = FullPathName ; } if ( filenameMap . find ( Filename ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename ] = i ; OutStreamer . EmitDwarfFileDirective ( i , <STR_LIT> , Filename ) ; ++ i ; } for ( DISubprogram SP : DbgFinder . subprograms ( ) ) { StringRef Filename ( SP . getFilename ( ) ) ; StringRef Dirname ( SP . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName ; } if ( filenameMap . find ( Filename ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename ] = i ;"
LLVM,NVPTX,428,"Predict the next statement of this code snippet:
 <s> StringRef Dirname ( DIUnit . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName ; } if ( filenameMap . find ( Filename ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename ] = i ; OutStreamer . EmitDwarfFileDirective ( i , <STR_LIT> , Filename ) ; ++ i ; } for ( DISubprogram SP : DbgFinder . subprograms ( ) ) { StringRef Filename ( SP . getFilename ( ) ) ; StringRef Dirname ( SP . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ;"
LLVM,NVPTX,429,"Predict the next statement of this code snippet:
 <s> continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( ETy ) ; unsigned sz = TD -> getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , ETy , vtparts ) ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ paramIndex ; } if ( i < e - <NUM_LIT> ) O << <STR_LIT> ; } -- paramIndex ;"
LLVM,NVPTX,430,"Predict the next statement of this code snippet:
 <s> switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstantExpression ( CE , AP . TM . getDataLayout ( ) ) ) if ( C != CE ) return LowerConstant ( C , AP ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; WriteAsOperand ( OS , CE , false , ! AP . MF ? <NUM_LIT> : AP . MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; const Constant * PtrVal = CE -> getOperand ( <NUM_LIT> ) ; SmallVector < Value * , <NUM_LIT> > IdxVec ( CE -> op_begin ( ) + <NUM_LIT> , CE -> op_end ( ) ) ; int64_t Offset = TD . getIndexedOffset ( PtrVal -> getType ( ) , IdxVec ) ; const MCExpr * Base = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; if ( Offset == <NUM_LIT> ) return Base ; if ( TD . getPointerSizeInBits ( ) != <NUM_LIT> ) { int SExtAmount = <NUM_LIT> - TD . getPointerSizeInBits ( ) ; Offset = ( Offset << SExtAmount ) >> SExtAmount ; } return MCBinaryExpr :: CreateAdd ( Base , MCConstantExpr :: Create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; case Instruction :: IntToPtr : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , TD . getIntPtrType ( CV -> getContext ( ) ) , false ) ; return LowerConstant ( Op , AP ) ; } case Instruction :: PtrToInt : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,431,"Predict the next statement of this code snippet:
 <s> default : O << <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( DL , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { unsigned align = PAL . getParamAlignment ( paramIndex ) ; if ( align == <NUM_LIT> ) align = DL . getABITypeAlignment ( ETy ) ; if ( ! isKernelFunc && align < <NUM_LIT> ) align = <NUM_LIT> ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ;"
LLVM,NVPTX,432,"Predict the next statement of this code snippet:
 <s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { if ( MO . getReg ( ) == <STR_LIT> ) O << DEPOTNAME << getFunctionNumber ( ) ; else O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; } else { emitVirtualRegister ( MO . getReg ( ) , O ) ; } break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , O ) ; break ;"
LLVM,NVPTX,433,"Predict the next statement of this code snippet:
 <s> aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { if ( const ConstantInt * constInt = dyn_cast < ConstantInt > ( ConstantFoldConstantExpression ( Cexpr , DL ) ) ) { int int32 = ( int ) ( constInt -> getZExtValue ( ) ) ; ConvertIntToBytes < > ( ptr , int32 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } if ( Cexpr -> getOpcode ( ) == Instruction :: PtrToInt ) { Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr -> getOperand ( <NUM_LIT> ) ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else if ( ETy == Type :: getInt64Ty ( CPV -> getContext ( ) ) ) { if ( const ConstantInt * constInt = dyn_cast < ConstantInt > ( CPV ) ) { long long int64 = ( long long ) ( constInt -> getZExtValue ( ) ) ; ConvertIntToBytes < > ( ptr , int64 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { if ( const ConstantInt * constInt = dyn_cast < ConstantInt > ( ConstantFoldConstantExpression ( Cexpr , DL ) ) ) { long long int64 = ( long long ) ( constInt -> getZExtValue ( ) ) ; ConvertIntToBytes < > ( ptr , int64 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } if ( Cexpr -> getOpcode ( ) == Instruction :: PtrToInt ) { Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr -> getOperand ( <NUM_LIT> ) ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; } case Type :: FloatTyID : case Type :: DoubleTyID : { const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ; Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ConvertFloatToBytes ( ptr , float32 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ;"
LLVM,NVPTX,434,"Predict the next statement of this code snippet:
 <s> if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> AddBlankLine ( ) ; OutStreamer -> EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer -> AddBlankLine ( ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> AddBlankLine ( ) ; } if ( TM . getTargetTriple ( ) . getOS ( ) != Triple :: NVCL ) recordAndEmitFilenames ( M ) ; GlobalsEmitted = false ; return false ;"
LLVM,NVPTX,435,"Predict the next statement of this code snippet:
 <s> OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; } if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; GlobalsEmitted = false ;"
LLVM,NVPTX,436,"Predict the next statement of this code snippet:
 <s> MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( & TM ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ;"
LLVM,NVPTX,437,"Predict the next statement of this code snippet:
 <s> if ( ETy -> isPrimitiveType ( ) || ETy -> isIntegerTy ( ) || isa < PointerType > ( ETy ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID :"
LLVM,NVPTX,438,"Predict the next statement of this code snippet:
 <s> const MCExpr * Base = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: CreateAdd ( Base , MCConstantExpr :: Create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; case Instruction :: IntToPtr : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , TD . getIntPtrType ( CV -> getContext ( ) ) , false ) ; return LowerConstant ( Op , AP ) ; } case Instruction :: PtrToInt : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = LowerConstant ( Op , AP ) ; if ( TD . getTypeAllocSize ( Ty ) == TD . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = TD . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: Create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: CreateAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: SDiv : case Instruction :: SRem : case Instruction :: Shl : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : { const MCExpr * LHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; const MCExpr * RHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; switch ( CE -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Add : return MCBinaryExpr :: CreateAdd ( LHS , RHS , Ctx ) ; case Instruction :: Sub : return MCBinaryExpr :: CreateSub ( LHS , RHS , Ctx ) ; case Instruction :: Mul : return MCBinaryExpr :: CreateMul ( LHS , RHS , Ctx ) ; case Instruction :: SDiv : return MCBinaryExpr :: CreateDiv ( LHS , RHS , Ctx ) ; case Instruction :: SRem : return MCBinaryExpr :: CreateMod ( LHS , RHS , Ctx ) ; case Instruction :: Shl : return MCBinaryExpr :: CreateShl ( LHS , RHS , Ctx ) ; case Instruction :: And : return MCBinaryExpr :: CreateAnd ( LHS , RHS , Ctx ) ;"
LLVM,NVPTX,439,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { if ( MO . getReg ( ) == <STR_LIT> ) O << DEPOTNAME << getFunctionNumber ( ) ; else O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; } else { emitVirtualRegister ( MO . getReg ( ) , O ) ; } return ; case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : { const char * symbname = MO . getSymbolName ( ) ; if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; printParamName ( index , O ) ; } else if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ;"
LLVM,NVPTX,440,"Predict the next statement of this code snippet:
 <s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ) { printFPConstant ( CFP , O ) ; return ; } if ( isa < ConstantPointerNull > ( CPV ) ) { O << <STR_LIT> ; return ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { O << * getSymbol ( GVar ) ; return ; } if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { O << * getSymbol ( GVar ) ; return ; } else { O << * LowerConstant ( CPV , * this ) ; return ; } } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,441,"Predict the next statement of this code snippet:
 <s> } if ( ! isEmptyXXStructor ( M . getNamedGlobal ( <STR_LIT> ) ) ) { report_fatal_error ( <STR_LIT> ) ; return true ; } if ( ! isEmptyXXStructor ( M . getNamedGlobal ( <STR_LIT> ) ) ) { report_fatal_error ( <STR_LIT> ) ; return true ; } SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( ) ; emitHeader ( M , OS1 , STI ) ;"
LLVM,NVPTX,442,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> << paramIndex ; } continue ; } } if ( ! PAL . hasAttribute ( paramIndex + <NUM_LIT> , Attribute :: ByVal ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( static_cast < <ISA_LIT>TargetMachine & > ( TM ) . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( DL , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ;"
LLVM,NVPTX,443,"Predict the next statement of this code snippet:
 <s> break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( DL , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = DL . getABITypeAlignment ( ETy ) ; if ( ! isKernelFunc && align < <NUM_LIT> ) align = <NUM_LIT> ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , ETy , vtparts ) ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ paramIndex ; } if ( i < e - <NUM_LIT> ) O << <STR_LIT> ; } -- paramIndex ;"
LLVM,NVPTX,444,"Predict the next statement of this code snippet:
 <s> return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; if ( ElementSize ) { O << ElementSize ; } O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return ;"
LLVM,NVPTX,445,"Predict the next statement of this code snippet:
 <s> if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) DL . getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; if ( ElementSize ) { O << ElementSize ; } O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return ;"
LLVM,NVPTX,446,"Predict the next statement of this code snippet:
 <s> } case Instruction :: Trunc : case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : { const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , DL . getIntPtrType ( CV -> getType ( ) ) , false ) ; return lowerConstantForGV ( Op , ProcessingGeneric ) ; } case Instruction :: PtrToInt : { const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = lowerConstantForGV ( Op , ProcessingGeneric ) ; if ( DL . getTypeAllocSize ( Ty ) == DL . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = DL . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: createAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : { const MCExpr * LHS = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; const MCExpr * RHS = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; switch ( CE -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Add : return MCBinaryExpr :: createAdd ( LHS , RHS , Ctx ) ; }"
LLVM,NVPTX,447,"Predict the next statement of this code snippet:
 <s> } switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstant ( CE , getDataLayout ( ) ) ) if ( C && C != CE ) return lowerConstantForGV ( C , ProcessingGeneric ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? <NUM_LIT> : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : { const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , DL . getIntPtrType ( CV -> getType ( ) ) , false ) ;"
LLVM,NVPTX,448,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; if ( isABI ) { if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( auto * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; if ( size < <NUM_LIT> ) size = <NUM_LIT> ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( DL ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned totalsz = DL . getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = DL . getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,449,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; if ( isABI ) { if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( auto * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; if ( size < <NUM_LIT> ) size = <NUM_LIT> ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( DL ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned totalsz = DL . getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = DL . getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> << idx ;"
LLVM,NVPTX,450,"Predict the next statement of this code snippet:
 <s> I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ;"
LLVM,NVPTX,451,"Predict the next statement of this code snippet:
 <s> Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = <NUM_LIT> ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ;"
LLVM,NVPTX,452,"Predict the next statement of this code snippet:
 <s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; if ( NumBytes ) { O << <STR_LIT> << MFI . getMaxAlignment ( ) << <STR_LIT> << DEPOTNAME << getFunctionNumber ( ) << <STR_LIT> << NumBytes << <STR_LIT> ; if ( static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . is64Bit ( ) ) { O << <STR_LIT> ; O << <STR_LIT> ; } else { O << <STR_LIT> ; O << <STR_LIT> ; } } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ;"
LLVM,NVPTX,453,"Predict the next statement of this code snippet:
 <s> if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ptr = ( unsigned char * ) & float32 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ; ptr = ( unsigned char * ) & float64 ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } break ; } case Type :: PointerTyID : { if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { aggBuffer -> addSymbol ( GVar , GVar ) ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr ) ; } unsigned int s = TD -> getTypeAllocSize ( CPV -> getType ( ) ) ; aggBuffer -> addZeros ( s ) ; break ; } case Type :: ArrayTyID : case Type :: VectorTyID : case Type :: StructTyID : { if ( isa < ConstantArray > ( CPV ) || isa < ConstantVector > ( CPV ) || isa < ConstantStruct > ( CPV ) || isa < ConstantDataSequential > ( CPV ) ) { int ElementSize = TD -> getTypeAllocSize ( CPV -> getType ( ) ) ; bufferAggregateConstant ( CPV , aggBuffer ) ; if ( Bytes > ElementSize ) aggBuffer -> addZeros ( Bytes - ElementSize ) ; } else if ( isa < ConstantAggregateZero > ( CPV ) ) aggBuffer -> addZeros ( Bytes ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; }"
LLVM,NVPTX,454,"Predict the next statement of this code snippet:
 <s> MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( TM . getDataLayout ( ) ) ; emitHeader ( M , OS1 , STI ) ; OutStreamer -> EmitRawText ( OS1 . str ( ) ) ;"
LLVM,NVPTX,455,"Predict the next statement of this code snippet:
 <s> if ( ! GlobalsEmitted ) { emitGlobals ( * MF -> getFunction ( ) -> getParent ( ) ) ; GlobalsEmitted = true ; } MRI = & MF -> getRegInfo ( ) ; F = MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( llvm :: isKernelFunction ( * F ) ) O << <STR_LIT> ; else { O << <STR_LIT> ;"
LLVM,NVPTX,456,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ;"
LLVM,NVPTX,457,"Predict the next statement of this code snippet:
 <s> const DataLayout * TD = TM . getDataLayout ( ) ; const PointerType * PTy = GVar -> getType ( ) ; Type * ETy = PTy -> getElementType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ;"
LLVM,NVPTX,458,"Predict the next statement of this code snippet:
 <s> if ( CPV -> getNumOperands ( ) ) for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( const ConstantDataSequential * CDS = dyn_cast < ConstantDataSequential > ( CPV ) ) { if ( CDS -> getNumElements ( ) ) for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) bufferLEByte ( cast < Constant > ( CDS -> getElementAsConstant ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( isa < ConstantStruct > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) { StructType * ST = cast < StructType > ( CPV -> getType ( ) ) ; for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == ( e - <NUM_LIT> ) ) Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( <NUM_LIT> ) + TD -> getTypeAllocSize ( ST ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; else Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( i + <NUM_LIT> ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , Bytes , aggBuffer ) ; } } return ;"
LLVM,NVPTX,459,"Predict the next statement of this code snippet:
 <s> MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( OutContext , * TM . getTargetData ( ) ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; SmallString < <NUM_LIT> > Str2 ; raw_svector_ostream OS2 ( Str2 ) ; emitDeclarations ( M , OS2 ) ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) printModuleLevelGV ( I , OS2 ) ; OS2 << '\n' ; OutStreamer . EmitRawText ( OS2 . str ( ) ) ; return false ;"
LLVM,NVPTX,460,"Predict the next statement of this code snippet:
 <s> if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; SmallString < <NUM_LIT> > Str2 ; raw_svector_ostream OS2 ( Str2 ) ; emitDeclarations ( M , OS2 ) ;"
LLVM,NVPTX,461,"Predict the next statement of this code snippet:
 <s> std :: string sname = I -> getName ( ) ; if ( llvm :: isImageWriteOnly ( * I ) ) O << <STR_LIT> << * CurrentFnSym << <STR_LIT> << paramIndex ; else O << <STR_LIT> << * CurrentFnSym << <STR_LIT> << paramIndex ; } else O << <STR_LIT> << * CurrentFnSym << <STR_LIT> << paramIndex ; continue ; } if ( PAL . paramHasAttr ( paramIndex + <NUM_LIT> , Attribute :: ByVal ) == false ) { const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST_NOT_GEN : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> << getPTXFundamentalTypeStr ( Ty ) << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ;"
LLVM,NVPTX,462,"Predict the next statement of this code snippet:
 <s> std :: string sname = I -> getName ( ) ; if ( llvm :: isImageWriteOnly ( * I ) ) O << <STR_LIT> << * CurrentFnSym << <STR_LIT> << paramIndex ; else O << <STR_LIT> << * CurrentFnSym << <STR_LIT> << paramIndex ; } else O << <STR_LIT> << * CurrentFnSym << <STR_LIT> << paramIndex ; continue ; } if ( PAL . paramHasAttr ( paramIndex + <NUM_LIT> , Attribute :: ByVal ) == false ) { const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST_NOT_GEN : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> << getPTXFundamentalTypeStr ( Ty ) << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ;"
LLVM,NVPTX,463,"Predict the next statement of this code snippet:
 <s> const TargetData * TD = TM . getTargetData ( ) ; const PointerType * PTy = GVar -> getType ( ) ; Type * ETy = PTy -> getElementType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isPrimitiveType ( ) || ETy -> isIntegerTy ( ) || isa < PointerType > ( ETy ) ) {"
LLVM,NVPTX,464,"Predict the next statement of this code snippet:
 <s> const VectorType * VTy = dyn_cast < VectorType > ( Ty ) ; if ( VTy ) { Type * ETy = VTy -> getElementType ( ) ; unsigned int numE = VTy -> getNumElements ( ) ; unsigned int alignE = TD -> getPrefTypeAlignment ( ETy ) ; if ( numE == <NUM_LIT> ) return <NUM_LIT> * alignE ; else return numE * alignE ; } const StructType * STy = dyn_cast < StructType > ( Ty ) ; if ( STy ) { unsigned int alignStruct = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; i ++ ) { Type * ETy = STy -> getElementType ( i ) ; unsigned int align = getOpenCLAlignment ( TD , ETy ) ; if ( align > alignStruct ) alignStruct = align ; } return alignStruct ; } const FunctionType * FTy = dyn_cast < FunctionType > ( Ty ) ; if ( FTy ) return TD -> getPointerPrefAlignment ( ) ; return TD -> getPrefTypeAlignment ( Ty ) ;"
LLVM,NVPTX,465,"Predict the next statement of this code snippet:
 <s> else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( ) . getSizeInBits ( ) << <STR_LIT> ; } else { if ( ( Ty -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( Ty ) ) { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned totalsz = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; totalsz += sz / <NUM_LIT> ; } } unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else assert ( false && <STR_LIT> ) ; } } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ;"
LLVM,NVPTX,466,"Predict the next statement of this code snippet:
 <s> EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; totalsz += sz / <NUM_LIT> ; } } unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else assert ( false && <STR_LIT> ) ; } } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ;"
LLVM,NVPTX,467,"Predict the next statement of this code snippet:
 <s> Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr -> getOperand ( <NUM_LIT> ) ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; } case Type :: FloatTyID : case Type :: DoubleTyID : { const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ; const Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ConvertFloatToBytes ( ptr , float32 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ; ConvertDoubleToBytes ( ptr , float64 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } break ; } case Type :: PointerTyID : { if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { aggBuffer -> addSymbol ( GVar , GVar ) ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr ) ; } unsigned int s = TD -> getTypeAllocSize ( CPV -> getType ( ) ) ; aggBuffer -> addZeros ( s ) ; break ; } case Type :: ArrayTyID : case Type :: VectorTyID : case Type :: StructTyID : { if ( isa < ConstantArray > ( CPV ) || isa < ConstantVector > ( CPV ) || isa < ConstantStruct > ( CPV ) || isa < ConstantDataSequential > ( CPV ) ) { int ElementSize = TD -> getTypeAllocSize ( CPV -> getType ( ) ) ; bufferAggregateConstant ( CPV , aggBuffer ) ; if ( Bytes > ElementSize ) aggBuffer -> addZeros ( Bytes - ElementSize ) ; } else if ( isa < ConstantAggregateZero > ( CPV ) ) aggBuffer -> addZeros ( Bytes ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; }"
LLVM,NVPTX,468,"Predict the next statement of this code snippet:
 <s> if ( isImageWriteOnly ( * I ) || isImageReadWrite ( * I ) ) { if ( nvptxSubtarget -> hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; CurrentFnSym -> print ( O , MAI ) ; O << <STR_LIT> << paramIndex ; } else { if ( nvptxSubtarget -> hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; CurrentFnSym -> print ( O , MAI ) ; O << <STR_LIT> << paramIndex ; } } else { if ( nvptxSubtarget -> hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; CurrentFnSym -> print ( O , MAI ) ; O << <STR_LIT> << paramIndex ; } continue ; } } if ( ! PAL . hasAttribute ( paramIndex + <NUM_LIT> , Attribute :: ByVal ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( Ty ) ; unsigned sz = TD -> getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( static_cast < <ISA_LIT>TargetMachine & > ( TM ) . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ;"
LLVM,NVPTX,469,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ;"
LLVM,NVPTX,470,"Predict the next statement of this code snippet:
 <s> return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : { const DataLayout & DL = * TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , DL . getIntPtrType ( CV -> getType ( ) ) , false ) ; return lowerConstantForGV ( Op , ProcessingGeneric ) ; } case Instruction :: PtrToInt : { const DataLayout & DL = * TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = lowerConstantForGV ( Op , ProcessingGeneric ) ; if ( DL . getTypeAllocSize ( Ty ) == DL . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = DL . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: createAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : { const MCExpr * LHS = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ;"
LLVM,NVPTX,471,"Predict the next statement of this code snippet:
 <s> SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> << idx ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ;"
LLVM,NVPTX,472,"Predict the next statement of this code snippet:
 <s> const ConstantExpr * CE = dyn_cast < ConstantExpr > ( CV ) ; if ( ! CE ) { llvm_unreachable ( <STR_LIT> ) ; } switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstant ( CE , getDataLayout ( ) ) ) if ( C && C != CE ) return lowerConstantForGV ( C , ProcessingGeneric ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? <NUM_LIT> : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : LLVM_FALLTHROUGH ; case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : { const DataLayout & DL = getDataLayout ( ) ;"
LLVM,NVPTX,473,"Predict the next statement of this code snippet:
 <s> std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? <NUM_LIT> : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : LLVM_FALLTHROUGH ; case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ;"
LLVM,NVPTX,474,"Predict the next statement of this code snippet:
 <s> return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : { const char * symbname = MO . getSymbolName ( ) ; if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; printParamName ( index , O ) ; } else if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; O << * CurrentFnSym << <STR_LIT> << index << <STR_LIT> ; } else O << symbname ; break ; }"
LLVM,NVPTX,475,"Predict the next statement of this code snippet:
 <s> emitVirtualRegister ( MO . getReg ( ) , O ) ; } return ; case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : { const char * symbname = MO . getSymbolName ( ) ; if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; printParamName ( index , O ) ; } else if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; O << * CurrentFnSym << <STR_LIT> << index << <STR_LIT> ; } else O << symbname ;"
LLVM,NVPTX,476,"Predict the next statement of this code snippet:
 <s> return ; } if ( isa < ConstantStruct > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) { StructType * ST = cast < StructType > ( CPV -> getType ( ) ) ; for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == ( e - <NUM_LIT> ) ) Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( <NUM_LIT> ) + TD -> getTypeAllocSize ( ST ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ;"
LLVM,NVPTX,477,"Predict the next statement of this code snippet:
 <s> } if ( isa < ConstantStruct > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) { StructType * ST = cast < StructType > ( CPV -> getType ( ) ) ; for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == ( e - <NUM_LIT> ) ) Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( <NUM_LIT> ) + TD -> getTypeAllocSize ( ST ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; else Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( i + <NUM_LIT> ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , Bytes , aggBuffer ) ; } } return ;"
LLVM,NVPTX,478,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: doInitialization ( Module & M ) { SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; } if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; GlobalsEmitted = false ; return false ;"
LLVM,NVPTX,479,"Predict the next statement of this code snippet:
 <s> emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; }"
LLVM,NVPTX,480,"Predict the next statement of this code snippet:
 <s> if ( isKernelFunction ( * F ) ) { if ( isSampler ( * I ) || isImage ( * I ) ) { if ( isImage ( * I ) ) { std :: string sname = I -> getName ( ) ; if ( isImageWriteOnly ( * I ) || isImageReadWrite ( * I ) ) { if ( nvptxSubtarget . hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> << paramIndex ; } else { if ( nvptxSubtarget . hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> << paramIndex ; } } else { if ( nvptxSubtarget . hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> << paramIndex ; } continue ; } } if ( PAL . hasAttribute ( paramIndex + <NUM_LIT> , Attribute :: ByVal ) == false ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( Ty ) ; unsigned sz = TD -> getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ;"
LLVM,NVPTX,481,"Predict the next statement of this code snippet:
 <s> const DataLayout * TD = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; const PointerType * PTy = GVar -> getType ( ) ; Type * ETy = PTy -> getElementType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; }"
LLVM,NVPTX,482,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> << * getSymbol ( GVar ) << <STR_LIT> ; if ( ElementSize ) { O << itostr ( ElementSize ) ; } O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,NVPTX,483,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; if ( isABI ) { if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( const IntegerType * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; if ( size < <NUM_LIT> ) size = <NUM_LIT> ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( ( Ty -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( Ty ) ) { unsigned totalsz = TD -> getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> << idx ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ idx ; } if ( i < e - <NUM_LIT> ) O << <STR_LIT> ; } }"
LLVM,NVPTX,484,"Predict the next statement of this code snippet:
 <s> unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ;"
LLVM,NVPTX,485,"Predict the next statement of this code snippet:
 <s> const DataLayout * TD = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; const PointerType * PTy = GVar -> getType ( ) ; Type * ETy = PTy -> getElementType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isSingleValueType ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID :"
LLVM,NVPTX,486,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitPTXGlobalVariable ( const GlobalVariable * GVar , raw_ostream & O ) { const DataLayout * TD = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; const PointerType * PTy = GVar -> getType ( ) ; Type * ETy = PTy -> getElementType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ;"
LLVM,NVPTX,487,"Predict the next statement of this code snippet:
 <s> case Instruction :: GetElementPtr : { const DataLayout & TD = * AP . TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; APInt OffsetAI ( TD . getPointerSizeInBits ( ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( TD , OffsetAI ) ; const MCExpr * Base = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: CreateAdd ( Base , MCConstantExpr :: Create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; case Instruction :: IntToPtr : { const DataLayout & TD = * AP . TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , TD . getIntPtrType ( CV -> getContext ( ) ) , false ) ; return LowerConstant ( Op , AP ) ; } case Instruction :: PtrToInt : { const DataLayout & TD = * AP . TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = LowerConstant ( Op , AP ) ; if ( TD . getTypeAllocSize ( Ty ) == TD . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = TD . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: Create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: CreateAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: SDiv : case Instruction :: SRem : case Instruction :: Shl : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : { const MCExpr * LHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; const MCExpr * RHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; switch ( CE -> getOpcode ( ) ) { default :"
LLVM,NVPTX,488,"Predict the next statement of this code snippet:
 <s> Mang = new Mangler ( OutContext , & TM ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; GlobalsEmitted = false ; return false ;"
LLVM,NVPTX,489,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: doInitialization ( Module & M ) { SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( OutContext , & TM ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ;"
LLVM,NVPTX,490,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,491,"Predict the next statement of this code snippet:
 <s> assert ( ( curpos + Bytes ) <= size ) ; for ( int i = <NUM_LIT> ; i < Num ; ++ i ) { buffer [ curpos ] = Ptr [ i ] ; curpos ++ ; } for ( int i = Num ; i < Bytes ; ++ i ) { buffer [ curpos ] = <NUM_LIT> ; curpos ++ ; } return curpos ;"
LLVM,NVPTX,492,"Predict the next statement of this code snippet:
 <s> symbolPosInBuffer . push_back ( curpos ) ; Symbols . push_back ( GVar ) ; SymbolsBeforeStripping . push_back ( GVarBeforeStripping ) ; numSymbols ++ ;"
LLVM,NVPTX,493,"Predict the next statement of this code snippet:
 <s> for ( int i = <NUM_LIT> ; i < Num ; ++ i ) { buffer [ curpos ] = <NUM_LIT> ; curpos ++ ;"
LLVM,NVPTX,494,"Predict the next statement of this code snippet:
 <s> int Bytes ; if ( isa < ConstantArray > ( CPV ) || isa < ConstantVector > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( const ConstantDataSequential * CDS = dyn_cast < ConstantDataSequential > ( CPV ) ) { if ( CDS -> getNumElements ( ) ) for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) bufferLEByte ( cast < Constant > ( CDS -> getElementAsConstant ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( isa < ConstantStruct > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) {"
LLVM,NVPTX,495,"Predict the next statement of this code snippet:
 <s> if ( ! gv -> hasInternalLinkage ( ) ) return false ; PointerType * Pty = gv -> getType ( ) ; if ( Pty -> getAddressSpace ( ) != llvm :: ADDRESS_SPACE_SHARED ) return false ; const Function * oneFunc = nullptr ;"
LLVM,NVPTX,496,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> ; i < sizeof ( int64_t ) ; ++ i ) { p [ i ] = ( unsigned char ) * vp ;"
LLVM,NVPTX,497,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> ; i < sizeof ( int64_t ) ; ++ i ) {"
LLVM,NVPTX,498,"Predict the next statement of this code snippet:
 <s> int32_t * vp = ( int32_t * ) & val ; for ( unsigned i = <NUM_LIT> ; i < sizeof ( int32_t ) ; ++ i ) {"
LLVM,NVPTX,499,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> ; i < sizeof ( T ) ; ++ i ) { p [ i ] = ( unsigned char ) vp ; vp >>= <NUM_LIT> ; }"
LLVM,NVPTX,500,"Predict the next statement of this code snippet:
 <s> p [ i ] = ( unsigned char ) vp ; vp >>= <NUM_LIT> ; }"
LLVM,NVPTX,501,"Predict the next statement of this code snippet:
 <s> if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( V ) ) Globals . insert ( GV ) ; else { if ( const User * U = dyn_cast < User > ( V ) ) { for ( unsigned i = <NUM_LIT> , e = U -> getNumOperands ( ) ; i != e ; ++ i ) {"
LLVM,NVPTX,502,"Predict the next statement of this code snippet:
 <s> I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ;"
LLVM,NVPTX,503,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: doInitialization ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = TM . getTargetCPU ( ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , NTM ) ; SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( ) ; emitHeader ( M , OS1 , STI ) ; OutStreamer -> EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> AddBlankLine ( ) ; OutStreamer -> EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer -> AddBlankLine ( ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> AddBlankLine ( ) ;"
LLVM,NVPTX,504,"Predict the next statement of this code snippet:
 <s> StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , NTM ) ; SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( ) ; emitHeader ( M , OS1 , STI ) ; OutStreamer -> EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> AddBlankLine ( ) ; OutStreamer -> EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer -> AddBlankLine ( ) ; OutStreamer -> AddComment ( <STR_LIT> ) ;"
LLVM,NVPTX,505,"Predict the next statement of this code snippet:
 <s> void EmitAlignment ( unsigned NumBits , const GlobalValue * GV = nullptr ) const {"
LLVM,NVPTX,506,"Predict the next statement of this code snippet:
 <s> void EmitAlignment ( unsigned NumBits , const GlobalValue * GV = nullptr ) const {"
LLVM,NVPTX,507,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitBasicBlockStart ( const MachineBasicBlock & MBB ) const { AsmPrinter :: EmitBasicBlockStart ( MBB ) ;"
LLVM,NVPTX,508,"Predict the next statement of this code snippet:
 <s> getSymbol ( F ) -> print ( O , MAI ) ; O << <STR_LIT> ; emitFunctionParamList ( F , O ) ; O << <STR_LIT> ;"
LLVM,NVPTX,509,"Predict the next statement of this code snippet:
 <s> if ( ! isa < Instruction > ( U ) ) continue ; const Instruction * instr = cast < Instruction > ( U ) ; const BasicBlock * bb = instr -> getParent ( ) ; if ( ! bb ) continue ; const Function * caller = bb -> getParent ( ) ; if ( ! caller ) continue ; if ( seenMap . find ( caller ) != seenMap . end ( ) ) { emitDeclaration ( F , O ) ; break ; } } seenMap [ F ] = true ;"
LLVM,NVPTX,510,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitDeclarations ( const Module & M , raw_ostream & O ) { llvm :: DenseMap < const Function * , bool > seenMap ; for ( Module :: const_iterator FI = M . begin ( ) , FE = M . end ( ) ; FI != FE ; ++ FI ) { const Function * F = FI ; if ( F -> isDeclaration ( ) ) { if ( F -> use_empty ( ) ) continue ; if ( F -> getIntrinsicID ( ) ) continue ; emitDeclaration ( F , O ) ; continue ; } for ( const User * U : F -> users ( ) ) { if ( const Constant * C = dyn_cast < Constant > ( U ) ) { if ( usedInGlobalVarDef ( C ) ) { emitDeclaration ( F , O ) ; break ; } if ( useFuncSeen ( C , seenMap ) ) { emitDeclaration ( F , O ) ; break ; } } if ( ! isa < Instruction > ( U ) ) continue ; const Instruction * instr = cast < Instruction > ( U ) ; const BasicBlock * bb = instr -> getParent ( ) ; if ( ! bb ) continue ;"
LLVM,NVPTX,511,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitDemotedVars ( const Function * f , raw_ostream & O ) { if ( localDecls . find ( f ) == localDecls . end ( ) ) return ; std :: vector < const GlobalVariable * > & gvars = localDecls [ f ] ; for ( unsigned i = <NUM_LIT> , e = gvars . size ( ) ; i != e ; ++ i ) { O << <STR_LIT> ; printModuleLevelGV ( gvars [ i ] , O , true ) ; }"
LLVM,NVPTX,512,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { VRegMapping . clear ( ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; setAndEmitFunctionVirtualRegisters ( * MF ) ; SmallString < <NUM_LIT> > Str ;"
LLVM,NVPTX,513,"Predict the next statement of this code snippet:
 <s> else { O << <STR_LIT> ; printReturnValStr ( * MF , O ) ; } CurrentFnSym -> print ( O , MAI ) ; emitFunctionParamList ( * MF , O ) ; if ( llvm :: isKernelFunction ( * F ) ) emitKernelFunctionDirectives ( * F , O ) ;"
LLVM,NVPTX,514,"Predict the next statement of this code snippet:
 <s> const Function * F = MF . getFunction ( ) ;"
LLVM,NVPTX,515,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitImplicitDef ( const MachineInstr * MI ) const {"
LLVM,NVPTX,516,"Predict the next statement of this code snippet:
 <s> if ( specified ) O << <STR_LIT> << reqntidx << <STR_LIT> << reqntidy << <STR_LIT> << reqntidz << <STR_LIT> ; unsigned maxntidx , maxntidy , maxntidz ; specified = false ; if ( ! llvm :: getMaxNTIDx ( F , maxntidx ) ) maxntidx = <NUM_LIT> ; else specified = true ; if ( ! llvm :: getMaxNTIDy ( F , maxntidy ) ) maxntidy = <NUM_LIT> ; else specified = true ; if ( ! llvm :: getMaxNTIDz ( F , maxntidz ) ) maxntidz = <NUM_LIT> ; else specified = true ; if ( specified ) O << <STR_LIT> << maxntidx << <STR_LIT> << maxntidy << <STR_LIT> << maxntidz << <STR_LIT> ; unsigned mincta ;"
LLVM,NVPTX,517,"Predict the next statement of this code snippet:
 <s> if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) { sys :: path :: append ( FullPathName , fileName ) ; fileName = FullPathName ; } if ( filenameMap . find ( fileName ) == filenameMap . end ( ) ) return ; if ( InterleaveSrc ) this -> emitSrcInText ( fileName , curLoc . getLine ( ) ) ;"
LLVM,NVPTX,518,"Predict the next statement of this code snippet:
 <s> if ( isa < GlobalVariable > ( V ) ) { const GlobalVariable * GVar = cast < GlobalVariable > ( V ) ; if ( GVar ) { if ( GVar -> hasInitializer ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; } } else if ( V -> isDeclaration ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; } else if ( V -> hasAppendingLinkage ( ) ) { std :: string msg ; msg . append ( <STR_LIT> ) ; msg . append ( <STR_LIT> ) ; if ( V -> hasName ( ) ) msg . append ( V -> getName ( ) ) ; msg . append ( <STR_LIT> ) ; llvm_unreachable ( msg . c_str ( ) ) ; } else if ( ! V -> hasInternalLinkage ( ) && ! V -> hasPrivateLinkage ( ) ) {"
LLVM,NVPTX,519,"Predict the next statement of this code snippet:
 <s> break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED :"
LLVM,NVPTX,520,"Predict the next statement of this code snippet:
 <s> int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; if ( ElementSize ) { O << ElementSize ; } O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,521,"Predict the next statement of this code snippet:
 <s> temp << filename . str ( ) ; temp << <STR_LIT> ; temp << line ; temp << <STR_LIT> ; temp << reader -> readLine ( line ) ; temp << <STR_LIT> ;"
LLVM,NVPTX,522,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: emitVirtualRegister ( unsigned int vr , raw_ostream & O ) { O << getVirtualRegisterName ( vr ) ;"
LLVM,NVPTX,523,"Predict the next statement of this code snippet:
 <s> return theFileName ;"
LLVM,NVPTX,524,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {"
LLVM,NVPTX,525,"Predict the next statement of this code snippet:
 <s> case Type :: DoubleTyID : return <STR_LIT> ; case Type :: PointerTyID : if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is64Bit ( ) ) if ( useB4PTR ) return <STR_LIT> ; else return <STR_LIT> ; else if ( useB4PTR ) return <STR_LIT> ;"
LLVM,NVPTX,526,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; break ; case Type :: IntegerTyID : { unsigned NumBits = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( NumBits == <NUM_LIT> ) return <STR_LIT> ; else if ( NumBits <= <NUM_LIT> ) { std :: string name = <STR_LIT> ; return name + utostr ( NumBits ) ; } else { llvm_unreachable ( <STR_LIT> ) ; break ; }"
LLVM,NVPTX,527,"Predict the next statement of this code snippet:
 <s> reader = new LineReader ( filename ) ; } if ( reader -> fileName ( ) != filename ) { delete reader ; reader = new LineReader ( filename ) ; }"
LLVM,NVPTX,528,"Predict the next statement of this code snippet:
 <s> if ( reader -> fileName ( ) != filename ) { delete reader ; reader = new LineReader ( filename ) ; }"
LLVM,NVPTX,529,"Predict the next statement of this code snippet:
 <s> MCOperand <ISA_LIT>AsmPrinter :: GetSymbolRef ( const MCSymbol * Symbol ) { const MCExpr * Expr ; Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ;"
LLVM,NVPTX,530,"Predict the next statement of this code snippet:
 <s> MCOperand <ISA_LIT>AsmPrinter :: GetSymbolRef ( const MCSymbol * Symbol ) {"
LLVM,NVPTX,531,"Predict the next statement of this code snippet:
 <s> const DenseMap < unsigned , unsigned > & RegMap = I -> second ; VRegMap :: const_iterator VI = RegMap . find ( Reg ) ; assert ( VI != RegMap . end ( ) && <STR_LIT> ) ; unsigned MappedVR = VI -> second ;"
LLVM,NVPTX,532,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false ;"
LLVM,NVPTX,533,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: isImageType ( Type * Ty ) {"
LLVM,NVPTX,534,"Predict the next statement of this code snippet:
 <s> for ( auto I = MBB . pred_begin ( ) ; I != MBB . pred_end ( ) ; ++ I ) { const MachineBasicBlock * PMBB = * I ;"
LLVM,NVPTX,535,"Predict the next statement of this code snippet:
 <s> MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; if ( ! LI . isLoopHeader ( & MBB ) ) return false ; for ( auto I = MBB . pred_begin ( ) ; I != MBB . pred_end ( ) ; ++ I ) { const MachineBasicBlock * PMBB = * I ; if ( LI . getLoopFor ( PMBB ) != LI . getLoopFor ( & MBB ) ) { continue ; }"
LLVM,NVPTX,536,"Predict the next statement of this code snippet:
 <s> theCurLine = <NUM_LIT> ; fstr . open ( filename . c_str ( ) ) ; theFileName = filename ;"
LLVM,NVPTX,537,"Predict the next statement of this code snippet:
 <s> LineReader ( std :: string filename ) { theCurLine = <NUM_LIT> ;"
LLVM,NVPTX,538,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) {"
LLVM,NVPTX,539,"Predict the next statement of this code snippet:
 <s> } } const ConstantExpr * CE = dyn_cast < ConstantExpr > ( CV ) ; if ( ! CE ) { llvm_unreachable ( <STR_LIT> ) ; } switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstantExpression ( CE , getDataLayout ( ) ) ) if ( C != CE ) return lowerConstantForGV ( C , ProcessingGeneric ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? <NUM_LIT> : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ;"
LLVM,NVPTX,540,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: lowerImageHandleOperand ( const MachineInstr * MI , unsigned OpNo , MCOperand & MCOp ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . TSFlags & <STR_LIT> ) { if ( OpNo == <NUM_LIT> && MO . isImm ( ) ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; } if ( OpNo == <NUM_LIT> && MO . isImm ( ) && ! ( MCID . TSFlags & <STR_LIT> ) ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; } return false ; } else if ( MCID . TSFlags & <STR_LIT> ) { unsigned VecSize = <NUM_LIT> << ( ( ( MCID . TSFlags & <STR_LIT> ) >> <STR_LIT> ) - <NUM_LIT> ) ; if ( OpNo == VecSize && MO . isImm ( ) ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; } return false ; } else if ( MCID . TSFlags & <STR_LIT> ) { if ( OpNo == <NUM_LIT> && MO . isImm ( ) ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; }"
LLVM,NVPTX,541,"Predict the next statement of this code snippet:
 <s> std :: string * SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( Sym ) ;"
LLVM,NVPTX,542,"Predict the next statement of this code snippet:
 <s> const char * Sym = MFI -> getImageHandleSymbol ( Index ) ; std :: string * SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( Sym ) ; MCOp = GetSymbolRef ( OutContext . getOrCreateSymbol ( StringRef ( SymNamePtr -> c_str ( ) ) ) ) ;"
LLVM,NVPTX,543,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) { switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : MCOp = MCOperand :: createReg ( encodeVirtualRegister ( MO . getReg ( ) ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ;"
LLVM,NVPTX,544,"Predict the next statement of this code snippet:
 <s> MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , OutContext ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_FPImmediate : { const ConstantFP * Cnt = MO . getFPImm ( ) ; APFloat Val = Cnt -> getValueAPF ( ) ; switch ( Cnt -> getType ( ) -> getTypeID ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; break ; case Type :: FloatTyID : MCOp = MCOperand :: createExpr ( <ISA_LIT>FloatMCExpr :: createConstantFPSingle ( Val , OutContext ) ) ; break ; case Type :: DoubleTyID : MCOp = MCOperand :: createExpr ( <ISA_LIT>FloatMCExpr :: createConstantFPDouble ( Val , OutContext ) ) ; break ;"
LLVM,NVPTX,545,"Predict the next statement of this code snippet:
 <s> const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; if ( ! nvptxSubtarget -> hasImageHandles ( ) ) { if ( lowerImageHandleOperand ( MI , i , MCOp ) ) { OutMI . addOperand ( MCOp ) ; continue ; } }"
LLVM,NVPTX,546,"Predict the next statement of this code snippet:
 <s> unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( static_cast < const <ISA_LIT>TargetMachine & > ( AP . TM ) . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; const Value * v0 = SymbolsBeforeStripping [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . getSymbol ( GVar ) ; PointerType * PTy = dyn_cast < PointerType > ( v0 -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; Name -> print ( O , AP . MAI ) ; O << <STR_LIT> ; } else { Name -> print ( O , AP . MAI ) ; } } else if ( const ConstantExpr * CExpr = dyn_cast < ConstantExpr > ( v0 ) ) { const MCExpr * Expr = AP . lowerConstantForGV ( cast < Constant > ( CExpr ) , false ) ; AP . printMCExpr ( * Expr , O ) ;"
LLVM,NVPTX,547,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ;"
LLVM,NVPTX,548,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) {"
LLVM,NVPTX,549,"Predict the next statement of this code snippet:
 <s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'r' : break ; }"
LLVM,NVPTX,550,"Predict the next statement of this code snippet:
 <s> } else llvm_unreachable ( <STR_LIT> ) ; APInt API = APF . bitcastToAPInt ( ) ; std :: string hexstr ( utohexstr ( API . getZExtValue ( ) ) ) ; O << lead ;"
LLVM,NVPTX,551,"Predict the next statement of this code snippet:
 <s> case MCExpr :: Constant : OS << cast < MCConstantExpr > ( Expr ) . getValue ( ) ; return ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SRE = cast < MCSymbolRefExpr > ( Expr ) ; const MCSymbol & Sym = SRE . getSymbol ( ) ; Sym . print ( OS , MAI ) ; return ; } case MCExpr :: Unary : { const MCUnaryExpr & UE = cast < MCUnaryExpr > ( Expr ) ; switch ( UE . getOpcode ( ) ) { case MCUnaryExpr :: LNot : OS << '!' ; break ; case MCUnaryExpr :: Minus : OS << '-' ; break ; case MCUnaryExpr :: Not : OS << '~' ; break ; case MCUnaryExpr :: Plus : OS << '+' ; break ; } printMCExpr ( * UE . getSubExpr ( ) , OS ) ; return ; } case MCExpr :: Binary : { const MCBinaryExpr & BE = cast < MCBinaryExpr > ( Expr ) ; if ( isa < MCConstantExpr > ( BE . getLHS ( ) ) || isa < MCSymbolRefExpr > ( BE . getLHS ( ) ) || isa < <ISA_LIT>GenericMCSymbolRefExpr > ( BE . getLHS ( ) ) ) { printMCExpr ( * BE . getLHS ( ) , OS ) ; } else { OS << '(' ; printMCExpr ( * BE . getLHS ( ) , OS ) ; OS << ')' ; } switch ( BE . getOpcode ( ) ) { case MCBinaryExpr :: Add : if ( const MCConstantExpr * RHSC = dyn_cast < MCConstantExpr > ( BE . getRHS ( ) ) ) { if ( RHSC -> getValue ( ) < <NUM_LIT> ) { OS << RHSC -> getValue ( ) ; return ; } }"
LLVM,NVPTX,552,"Predict the next statement of this code snippet:
 <s> } else { if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ;"
LLVM,NVPTX,553,"Predict the next statement of this code snippet:
 <s> if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ; } else { if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ;"
LLVM,NVPTX,554,"Predict the next statement of this code snippet:
 <s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { if ( MO . getReg ( ) == <STR_LIT> ) O << DEPOTNAME << getFunctionNumber ( ) ; else O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ;"
LLVM,NVPTX,555,"Predict the next statement of this code snippet:
 <s> const Function * F = MF . getFunction ( ) ;"
LLVM,NVPTX,556,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: printReturnValStr ( const MachineFunction & MF , raw_ostream & O ) { const Function * F = MF . getFunction ( ) ;"
LLVM,NVPTX,557,"Predict the next statement of this code snippet:
 <s> return ; } if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; PointerType * PTy = dyn_cast < PointerType > ( Cexpr -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; } else { getSymbol ( GVar ) -> print ( O , MAI ) ; } return ; } else { lowerConstant ( CPV ) -> print ( O , MAI ) ; return ; } } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,558,"Predict the next statement of this code snippet:
 <s> return ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { PointerType * PTy = dyn_cast < PointerType > ( GVar -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( EmitGeneric && ! isa < Function > ( CPV ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; } else { getSymbol ( GVar ) -> print ( O , MAI ) ; } return ; } if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; PointerType * PTy = dyn_cast < PointerType > ( Cexpr -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; } else { getSymbol ( GVar ) -> print ( O , MAI ) ; }"
LLVM,NVPTX,559,"Predict the next statement of this code snippet:
 <s> if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm < <NUM_LIT> ) Imm = <NUM_LIT> ; O << <STR_LIT> << vecelem [ Imm % <NUM_LIT> ] ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm < <NUM_LIT> ) Imm = <NUM_LIT> ;"
LLVM,NVPTX,560,"Predict the next statement of this code snippet:
 <s> } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm < <NUM_LIT> ) Imm = <NUM_LIT> ; O << <STR_LIT> << vecelem [ Imm % <NUM_LIT> ] ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) {"
LLVM,NVPTX,561,"Predict the next statement of this code snippet:
 <s> std :: string LineReader :: readLine ( unsigned lineNum ) { if ( lineNum < theCurLine ) { theCurLine = <NUM_LIT> ; fstr . seekg ( <NUM_LIT> , std :: ios :: beg ) ; } while ( theCurLine < lineNum ) { fstr . getline ( buff , <NUM_LIT> ) ; theCurLine ++ ;"
LLVM,NVPTX,562,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>AsmPrinter :: recordAndEmitFilenames ( Module & M ) { DebugInfoFinder DbgFinder ; DbgFinder . processModule ( M ) ; unsigned i = <NUM_LIT> ; for ( const DICompileUnit * DIUnit : DbgFinder . compile_units ( ) ) { StringRef Filename = DIUnit -> getFilename ( ) ; StringRef Dirname = DIUnit -> getDirectory ( ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName ; } if ( filenameMap . find ( Filename ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename ] = i ; OutStreamer -> EmitDwarfFileDirective ( i , <STR_LIT> , Filename ) ; ++ i ; } for ( DISubprogram * SP : DbgFinder . subprograms ( ) ) { StringRef Filename = SP -> getFilename ( ) ; StringRef Dirname = SP -> getDirectory ( ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName ; } if ( filenameMap . find ( Filename ) != filenameMap . end ( ) ) continue ;"
LLVM,NVPTX,563,"Predict the next statement of this code snippet:
 <s> nvptxSubtarget = & F . getSubtarget < <ISA_LIT>Subtarget > ( ) ;"
LLVM,NVPTX,564,"Predict the next statement of this code snippet:
 <s> bool runOnMachineFunction ( MachineFunction & F ) override { nvptxSubtarget = & F . getSubtarget < <ISA_LIT>Subtarget > ( ) ;"
LLVM,NVPTX,565,"Predict the next statement of this code snippet:
 <s> } } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = TRI -> index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; int n = regmap . size ( ) ; regmap . insert ( std :: make_pair ( vr , n + <NUM_LIT> ) ) ; } for ( unsigned i = <NUM_LIT> ; i < TRI -> getNumRegClasses ( ) ; i ++ ) { const TargetRegisterClass * RC = TRI -> getRegClass ( i ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; std :: string rcname = get<ISA_LIT>RegClassName ( RC ) ; std :: string rcStr = get<ISA_LIT>RegClassStr ( RC ) ; int n = regmap . size ( ) ;"
LLVM,NVPTX,566,"Predict the next statement of this code snippet:
 <s> unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = TRI -> index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; int n = regmap . size ( ) ; regmap . insert ( std :: make_pair ( vr , n + <NUM_LIT> ) ) ; }"
LLVM,NVPTX,567,"Predict the next statement of this code snippet:
 <s> }"
LLVM,NVPTX,568,"Predict the next statement of this code snippet:
 <s> for ( const User * U : C -> users ( ) ) if ( const Constant * C = dyn_cast < Constant > ( U ) ) if ( usedInGlobalVarDef ( C ) ) return true ; return false ;"
LLVM,NVPTX,569,"Predict the next statement of this code snippet:
 <s> if ( const Instruction * instr = dyn_cast < Instruction > ( U ) ) { if ( instr -> getParent ( ) && instr -> getParent ( ) -> getParent ( ) ) { const Function * curFunc = instr -> getParent ( ) -> getParent ( ) ; if ( oneFunc && ( curFunc != oneFunc ) ) return false ;"
LLVM,NVPTX,570,"Predict the next statement of this code snippet:
 <s> } else if ( const Instruction * I = dyn_cast < Instruction > ( U ) ) { const BasicBlock * bb = I -> getParent ( ) ; if ( ! bb ) continue ; const Function * caller = bb -> getParent ( ) ; if ( ! caller ) continue ;"
LLVM,NVPTX,571,"Predict the next statement of this code snippet:
 <s> void VisitGlobalVariableForEmission ( const GlobalVariable * GV , SmallVectorImpl < const GlobalVariable * > & Order , DenseSet < const GlobalVariable * > & Visited , DenseSet < const GlobalVariable * > & Visiting ) { if ( Visited . count ( GV ) ) return ; if ( ! Visiting . insert ( GV ) . second ) report_fatal_error ( <STR_LIT> ) ; DenseSet < const GlobalVariable * > Others ; for ( unsigned i = <NUM_LIT> , e = GV -> getNumOperands ( ) ; i != e ; ++ i ) DiscoverDependentGlobals ( GV -> getOperand ( i ) , Others ) ; for ( DenseSet < const GlobalVariable * > :: iterator I = Others . begin ( ) , E = Others . end ( ) ; I != E ; ++ I ) VisitGlobalVariableForEmission ( * I , Order , Visited , Visiting ) ; Order . push_back ( GV ) ; Visited . insert ( GV ) ; Visiting . erase ( GV ) ;"
LLVM,NVPTX,572,"Predict the next statement of this code snippet:
 <s> ~ LineReader ( ) {"
LLVM,NVPTX,573,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>AsmPrinter ( ) {"
LLVM,NVPTX,574,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>AsmPrinter ( ) { if ( ! reader ) delete reader ;"
LLVM,NVPTX,575,"Predict the next statement of this code snippet:
 <s> if ( C == '.' || C == '@' ) { ValidNameStream << <STR_LIT> ; } else { ValidNameStream << C ; } } return ValidNameStream . str ( ) ;"
LLVM,NVPTX,576,"Predict the next statement of this code snippet:
 <s> GV . setName ( cleanUpName ( GV . getName ( ) ) ) ; } }"
LLVM,NVPTX,577,"Predict the next statement of this code snippet:
 <s> raw_string_ostream ValidNameStream ( ValidName ) ; for ( unsigned I = <NUM_LIT> , E = Name . size ( ) ; I != E ; ++ I ) { char C = Name [ I ] ; if ( C == '.' || C == '@' ) { ValidNameStream << <STR_LIT> ; } else {"
LLVM,NVPTX,578,"Predict the next statement of this code snippet:
 <s> ModulePass * llvm :: create<ISA_LIT>AssignValidGlobalNamesPass ( ) { return new <ISA_LIT>AssignValidGlobalNames ( ) ;"
LLVM,NVPTX,579,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>AssignValidGlobalNames ( ) ;"
LLVM,NVPTX,580,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AssignValidGlobalNames ( ) : ModulePass ( ID ) {"
LLVM,NVPTX,581,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AssignValidGlobalNames ( ) : ModulePass ( ID ) {"
LLVM,NVPTX,582,"Predict the next statement of this code snippet:
 <s> for ( GlobalVariable & GV : M . globals ( ) ) { if ( GV . hasLocalLinkage ( ) ) { GV . setName ( cleanUpName ( GV . getName ( ) ) ) ; } } for ( Function & F : M . functions ( ) ) if ( F . hasLocalLinkage ( ) ) F . setName ( cleanUpName ( F . getName ( ) ) ) ;"
LLVM,NVPTX,583,"Predict the next statement of this code snippet:
 <s> GV . setName ( cleanUpName ( GV . getName ( ) ) ) ; } }"
LLVM,NVPTX,584,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {"
LLVM,NVPTX,585,"Predict the next statement of this code snippet:
 <s> AU . setPreservesCFG ( ) ;"
LLVM,NVPTX,586,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override {"
LLVM,NVPTX,587,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,588,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AtomicLower ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,589,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>AtomicLower ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,590,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>AtomicLower :: runOnFunction ( Function & F ) { SmallVector < AtomicRMWInst * > LocalMemoryAtomics ; for ( Instruction & I : instructions ( F ) ) if ( AtomicRMWInst * RMWI = dyn_cast < AtomicRMWInst > ( & I ) ) if ( RMWI -> getPointerAddressSpace ( ) == ADDRESS_SPACE_LOCAL ) LocalMemoryAtomics . push_back ( RMWI ) ;"
LLVM,NVPTX,591,"Predict the next statement of this code snippet:
 <s> NewGEPI -> setIsInBounds ( GEP -> isInBounds ( ) ) ; GEP -> replaceAllUsesWith ( new AddrSpaceCastInst ( NewGEPI , GEP -> getType ( ) , <STR_LIT> , GEPI ) ) ; } else { Constant * NewGEPCE = ConstantExpr :: getGetElementPtr ( cast < Constant > ( Cast -> getOperand ( <NUM_LIT> ) ) , Indices , GEP -> isInBounds ( ) ) ; GEP -> replaceAllUsesWith ( ConstantExpr :: getAddrSpaceCast ( NewGEPCE , GEP -> getType ( ) ) ) ; } return true ;"
LLVM,NVPTX,592,"Predict the next statement of this code snippet:
 <s> if ( SrcTy -> getElementType ( ) != DestTy -> getElementType ( ) ) return false ;"
LLVM,NVPTX,593,"Predict the next statement of this code snippet:
 <s> hoistAddrSpaceCastFromGEP ( GEP ) ; } if ( Operator * Cast = dyn_cast < Operator > ( MI -> getOperand ( Idx ) ) ) { if ( IsEliminableAddrSpaceCast ( Cast ) ) {"
LLVM,NVPTX,594,"Predict the next statement of this code snippet:
 <s> if ( GEPOperator * GEP = dyn_cast < GEPOperator > ( MI -> getOperand ( Idx ) ) ) { hoistAddrSpaceCastFromGEP ( GEP ) ; } if ( Operator * Cast = dyn_cast < Operator > ( MI -> getOperand ( Idx ) ) ) { if ( IsEliminableAddrSpaceCast ( Cast ) ) { MI -> setOperand ( Idx , Cast -> getOperand ( <NUM_LIT> ) ) ; return true ; }"
LLVM,NVPTX,595,"Predict the next statement of this code snippet:
 <s> GEP -> replaceAllUsesWith ( new AddrSpaceCastInst ( NewGEPI , GEP -> getType ( ) , <STR_LIT> , GEPI ) ) ; } else { Constant * NewGEPCE = ConstantExpr :: getGetElementPtr ( GEP -> getSourceElementType ( ) , cast < Constant > ( Cast -> getOperand ( <NUM_LIT> ) ) , Indices , GEP -> isInBounds ( ) ) ; GEP -> replaceAllUsesWith ( ConstantExpr :: getAddrSpaceCast ( NewGEPCE , GEP -> getType ( ) ) ) ; }"
LLVM,NVPTX,596,"Predict the next statement of this code snippet:
 <s> NewGEPI -> setIsInBounds ( GEP -> isInBounds ( ) ) ; GEP -> replaceAllUsesWith ( new AddrSpaceCastInst ( NewGEPI , GEP -> getType ( ) , <STR_LIT> , GEPI ) ) ; } else { Constant * NewGEPCE = ConstantExpr :: getGetElementPtr ( GEP -> getSourceElementType ( ) , cast < Constant > ( Cast -> getOperand ( <NUM_LIT> ) ) , Indices , GEP -> isInBounds ( ) ) ;"
LLVM,NVPTX,597,"Predict the next statement of this code snippet:
 <s> if ( DisableFavorNonGeneric ) return false ; bool Changed = false ; for ( BasicBlock & B : F ) { for ( Instruction & I : B ) { if ( isa < LoadInst > ( I ) ) { Changed |= optimizeMemoryInstruction ( & I , <NUM_LIT> ) ;"
LLVM,NVPTX,598,"Predict the next statement of this code snippet:
 <s> if ( DisableFavorNonGeneric ) return false ; bool Changed = false ; for ( BasicBlock & B : F ) { for ( Instruction & I : B ) { if ( isa < LoadInst > ( I ) ) {"
LLVM,NVPTX,599,"Predict the next statement of this code snippet:
 <s> if ( isEliminableAddrSpaceCast ( V ) ) return true ; const int MaxDepth = <NUM_LIT> ; if ( Depth >= MaxDepth ) return false ; if ( GEPOperator * GEP = dyn_cast < GEPOperator > ( V ) ) return hoistAddrSpaceCastFromGEP ( GEP , Depth ) ; if ( BitCastOperator * BC = dyn_cast < BitCastOperator > ( V ) ) return hoistAddrSpaceCastFromBitCast ( BC , Depth ) ;"
LLVM,NVPTX,600,"Predict the next statement of this code snippet:
 <s> if ( isEliminableAddrSpaceCast ( V ) ) return true ; const int MaxDepth = <NUM_LIT> ; if ( Depth >= MaxDepth ) return false ; if ( GEPOperator * GEP = dyn_cast < GEPOperator > ( V ) ) return hoistAddrSpaceCastFromGEP ( GEP , Depth ) ; if ( BitCastOperator * BC = dyn_cast < BitCastOperator > ( V ) ) return hoistAddrSpaceCastFromBitCast ( BC , Depth ) ;"
LLVM,NVPTX,601,"Predict the next statement of this code snippet:
 <s> Type * TypeOfNewCast = PointerType :: get ( BC -> getType ( ) -> getPointerElementType ( ) , Src -> getType ( ) -> getPointerAddressSpace ( ) ) ; if ( BitCastInst * BCI = dyn_cast < BitCastInst > ( BC ) ) { Value * NewCast = new BitCastInst ( Src , TypeOfNewCast , <STR_LIT> , BCI ) ; Value * NewBC = new AddrSpaceCastInst ( NewCast , BC -> getType ( ) , <STR_LIT> , BCI ) ; NewBC -> takeName ( BC ) ; BC -> replaceAllUsesWith ( NewBC ) ; } else { Constant * NewCast = ConstantExpr :: getBitCast ( cast < Constant > ( Src ) , TypeOfNewCast ) ; Constant * NewBC = ConstantExpr :: getAddrSpaceCast ( NewCast , BC -> getType ( ) ) ; BC -> replaceAllUsesWith ( NewBC ) ;"
LLVM,NVPTX,602,"Predict the next statement of this code snippet:
 <s> Operator * Cast = cast < Operator > ( BC -> getOperand ( <NUM_LIT> ) ) ; Value * Src = Cast -> getOperand ( <NUM_LIT> ) ; Type * TypeOfNewCast = PointerType :: get ( BC -> getType ( ) -> getPointerElementType ( ) , Src -> getType ( ) -> getPointerAddressSpace ( ) ) ; if ( BitCastInst * BCI = dyn_cast < BitCastInst > ( BC ) ) { Value * NewCast = new BitCastInst ( Src , TypeOfNewCast , <STR_LIT> , BCI ) ; Value * NewBC = new AddrSpaceCastInst ( NewCast , BC -> getType ( ) , <STR_LIT> , BCI ) ; NewBC -> takeName ( BC ) ; BC -> replaceAllUsesWith ( NewBC ) ; } else {"
LLVM,NVPTX,603,"Predict the next statement of this code snippet:
 <s> SmallVector < Value * , <NUM_LIT> > Indices ( GEP -> idx_begin ( ) , GEP -> idx_end ( ) ) ; if ( Instruction * GEPI = dyn_cast < Instruction > ( GEP ) ) { GetElementPtrInst * NewGEP = GetElementPtrInst :: Create ( GEP -> getSourceElementType ( ) , Cast -> getOperand ( <NUM_LIT> ) , Indices , <STR_LIT> , GEPI ) ; NewGEP -> setIsInBounds ( GEP -> isInBounds ( ) ) ; Value * NewASC = new AddrSpaceCastInst ( NewGEP , GEP -> getType ( ) , <STR_LIT> , GEPI ) ; NewASC -> takeName ( GEP ) ; GEP -> replaceAllUsesWith ( NewASC ) ; } else { Constant * NewGEP = ConstantExpr :: getGetElementPtr ( GEP -> getSourceElementType ( ) , cast < Constant > ( Cast -> getOperand ( <NUM_LIT> ) ) , Indices , GEP -> isInBounds ( ) ) ; GEP -> replaceAllUsesWith ( ConstantExpr :: getAddrSpaceCast ( NewGEP , GEP -> getType ( ) ) ) ; } return true ;"
LLVM,NVPTX,604,"Predict the next statement of this code snippet:
 <s> if ( Instruction * GEPI = dyn_cast < Instruction > ( GEP ) ) { GetElementPtrInst * NewGEP = GetElementPtrInst :: Create ( GEP -> getSourceElementType ( ) , Cast -> getOperand ( <NUM_LIT> ) , Indices , <STR_LIT> , GEPI ) ; NewGEP -> setIsInBounds ( GEP -> isInBounds ( ) ) ; Value * NewASC = new AddrSpaceCastInst ( NewGEP , GEP -> getType ( ) , <STR_LIT> , GEPI ) ; NewASC -> takeName ( GEP ) ; GEP -> replaceAllUsesWith ( NewASC ) ; } else { Constant * NewGEP = ConstantExpr :: getGetElementPtr ( GEP -> getSourceElementType ( ) , cast < Constant > ( Cast -> getOperand ( <NUM_LIT> ) ) , Indices , GEP -> isInBounds ( ) ) ;"
LLVM,NVPTX,605,"Predict the next statement of this code snippet:
 <s> Operator * ASC = dyn_cast < Operator > ( MI -> getOperand ( Idx ) ) ; MI -> setOperand ( Idx , ASC -> getOperand ( <NUM_LIT> ) ) ; return true ;"
LLVM,NVPTX,606,"Predict the next statement of this code snippet:
 <s> GetElementPtrInst * NewGEP = GetElementPtrInst :: Create ( GEP -> getSourceElementType ( ) , Cast -> getOperand ( <NUM_LIT> ) , Indices , <STR_LIT> , GEPI ) ; NewGEP -> setIsInBounds ( GEP -> isInBounds ( ) ) ; NewGEP -> takeName ( GEP ) ; NewASC = new AddrSpaceCastInst ( NewGEP , GEP -> getType ( ) , <STR_LIT> , GEPI ) ; GEP -> replaceAllUsesWith ( NewASC ) ; } else {"
LLVM,NVPTX,607,"Predict the next statement of this code snippet:
 <s> } else if ( isa < StoreInst > ( I ) ) { Changed |= optimizeMemoryInstruction ( & I , <NUM_LIT> ) ; } } } return Changed ;"
LLVM,NVPTX,608,"Predict the next statement of this code snippet:
 <s> if ( GEPOperator * GEP = dyn_cast < GEPOperator > ( V ) ) return hoistAddrSpaceCastFromGEP ( GEP , Depth ) ; if ( BitCastOperator * BC = dyn_cast < BitCastOperator > ( V ) ) return hoistAddrSpaceCastFromBitCast ( BC , Depth ) ;"
LLVM,NVPTX,609,"Predict the next statement of this code snippet:
 <s> Value * NewOperand = hoistAddrSpaceCastFrom ( BC -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( NewOperand == nullptr ) return nullptr ; assert ( isEliminableAddrSpaceCast ( NewOperand ) ) ; Operator * Cast = cast < Operator > ( NewOperand ) ; Value * Src = Cast -> getOperand ( <NUM_LIT> ) ; Type * TypeOfNewCast = PointerType :: get ( BC -> getType ( ) -> getPointerElementType ( ) , Src -> getType ( ) -> getPointerAddressSpace ( ) ) ; Value * NewBC ; if ( BitCastInst * BCI = dyn_cast < BitCastInst > ( BC ) ) { Value * NewCast = new BitCastInst ( Src , TypeOfNewCast , <STR_LIT> , BCI ) ; NewBC = new AddrSpaceCastInst ( NewCast , BC -> getType ( ) , <STR_LIT> , BCI ) ; NewBC -> takeName ( BC ) ; BC -> replaceAllUsesWith ( NewBC ) ; } else {"
LLVM,NVPTX,610,"Predict the next statement of this code snippet:
 <s> assert ( isEliminableAddrSpaceCast ( NewOperand ) ) ; Operator * Cast = cast < Operator > ( NewOperand ) ; SmallVector < Value * , <NUM_LIT> > Indices ( GEP -> idx_begin ( ) , GEP -> idx_end ( ) ) ; Value * NewASC ; if ( Instruction * GEPI = dyn_cast < Instruction > ( GEP ) ) { GetElementPtrInst * NewGEP = GetElementPtrInst :: Create ( GEP -> getSourceElementType ( ) , Cast -> getOperand ( <NUM_LIT> ) , Indices , <STR_LIT> , GEPI ) ; NewGEP -> setIsInBounds ( GEP -> isInBounds ( ) ) ; NewASC = new AddrSpaceCastInst ( NewGEP , GEP -> getType ( ) , <STR_LIT> , GEPI ) ; NewASC -> takeName ( GEP ) ; GEP -> replaceAllUsesWith ( NewASC ) ; } else {"
LLVM,NVPTX,611,"Predict the next statement of this code snippet:
 <s> if ( Instruction * GEPI = dyn_cast < Instruction > ( GEP ) ) { GetElementPtrInst * NewGEP = GetElementPtrInst :: Create ( GEP -> getSourceElementType ( ) , Cast -> getOperand ( <NUM_LIT> ) , Indices , <STR_LIT> , GEPI ) ; NewGEP -> setIsInBounds ( GEP -> isInBounds ( ) ) ; NewASC = new AddrSpaceCastInst ( NewGEP , GEP -> getType ( ) , <STR_LIT> , GEPI ) ; NewASC -> takeName ( GEP ) ; GEP -> replaceAllUsesWith ( NewASC ) ; } else { Constant * NewGEP = ConstantExpr :: getGetElementPtr ( GEP -> getSourceElementType ( ) , cast < Constant > ( Cast -> getOperand ( <NUM_LIT> ) ) , Indices , GEP -> isInBounds ( ) ) ; NewASC = ConstantExpr :: getAddrSpaceCast ( NewGEP , GEP -> getType ( ) ) ; } return NewASC ;"
LLVM,NVPTX,612,"Predict the next statement of this code snippet:
 <s> Value * Src = Cast -> getOperand ( <NUM_LIT> ) ; PointerType * SrcTy = cast < PointerType > ( Src -> getType ( ) ) ; PointerType * DestTy = cast < PointerType > ( Cast -> getType ( ) ) ;"
LLVM,NVPTX,613,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FavorNonGenericAddrSpaces ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,614,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FavorNonGenericAddrSpaces ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,615,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FavorNonGenericAddrSpaces :: optimizeMemoryInstruction ( Instruction * MI , unsigned Idx ) { Value * NewOperand = hoistAddrSpaceCastFrom ( MI -> getOperand ( Idx ) ) ; if ( NewOperand == nullptr ) return false ; assert ( isEliminableAddrSpaceCast ( NewOperand ) ) ; Operator * ASC = dyn_cast < Operator > ( NewOperand ) ; MI -> setOperand ( Idx , ASC -> getOperand ( <NUM_LIT> ) ) ;"
LLVM,NVPTX,616,"Predict the next statement of this code snippet:
 <s> if ( DisableFavorNonGeneric ) return false ; bool Changed = false ; for ( Function :: iterator B = F . begin ( ) , BE = F . end ( ) ; B != BE ; ++ B ) {"
LLVM,NVPTX,617,"Predict the next statement of this code snippet:
 <s> bool Changed = false ; for ( Function :: iterator B = F . begin ( ) , BE = F . end ( ) ; B != BE ; ++ B ) { for ( BasicBlock :: iterator I = B -> begin ( ) , IE = B -> end ( ) ; I != IE ; ++ I ) { if ( isa < LoadInst > ( I ) ) { Changed |= optimizeMemoryInstruction ( I , <NUM_LIT> ) ;"
LLVM,NVPTX,618,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {"
LLVM,NVPTX,619,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {"
LLVM,NVPTX,620,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {"
LLVM,NVPTX,621,"Predict the next statement of this code snippet:
 <s> unsigned MovDepotOpcode = ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; if ( ! MR . use_empty ( <STR_LIT> ) ) { MI = BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( CvtaLocalOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; }"
LLVM,NVPTX,622,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {"
LLVM,NVPTX,623,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) {"
LLVM,NVPTX,624,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) {"
LLVM,NVPTX,625,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {"
LLVM,NVPTX,626,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { if ( MF . getFrameInfo ( ) . hasStackObjects ( ) ) { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineInstr * MI = & MBB . front ( ) ; MachineRegisterInfo & MR = MF . getRegInfo ( ) ; const <ISA_LIT>RegisterInfo * NRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; DebugLoc dl = DebugLoc ( ) ; bool Is64Bit = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . is64Bit ( ) ;"
LLVM,NVPTX,627,"Predict the next statement of this code snippet:
 <s> return { DwarfFrameBase :: CFA , { <NUM_LIT> } } ;"
LLVM,NVPTX,628,"Predict the next statement of this code snippet:
 <s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;"
LLVM,NVPTX,629,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsUp , Align ( <NUM_LIT> ) , <NUM_LIT> ) {"
LLVM,NVPTX,630,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsUp , Align ( <NUM_LIT> ) , <NUM_LIT> ) {"
LLVM,NVPTX,631,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FrameLowering ( <ISA_LIT>TargetMachine & _tm , bool _is64bit ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , tm ( _tm ) , is64bit ( _is64bit ) {"
LLVM,NVPTX,632,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FrameLowering ( <ISA_LIT>TargetMachine & _tm , bool _is64bit ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , tm ( _tm ) , is64bit ( _is64bit ) {"
LLVM,NVPTX,633,"Predict the next statement of this code snippet:
 <s> unsigned CvtaLocalOpcode = ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; unsigned MovDepotOpcode = ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; if ( ! MR . use_empty ( <STR_LIT> ) ) { MI = BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( CvtaLocalOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; }"
LLVM,NVPTX,634,"Predict the next statement of this code snippet:
 <s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;"
LLVM,NVPTX,635,"Predict the next statement of this code snippet:
 <s> FrameReg = <STR_LIT> ; return MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ;"
LLVM,NVPTX,636,"Predict the next statement of this code snippet:
 <s> MI = BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( CvtaLocalOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( MovDepotOpcode ) , <STR_LIT> ) . addImm ( MF . getFunctionNumber ( ) ) ; }"
LLVM,NVPTX,637,"Predict the next statement of this code snippet:
 <s> MachineInstr * MI = & MBB . front ( ) ; MachineRegisterInfo & MR = MF . getRegInfo ( ) ; DebugLoc dl = DebugLoc ( ) ; bool Is64Bit = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . is64Bit ( ) ; unsigned CvtaLocalOpcode = ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; unsigned MovDepotOpcode = ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; if ( ! MR . use_empty ( <STR_LIT> ) ) { MI = BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( CvtaLocalOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ;"
LLVM,NVPTX,638,"Predict the next statement of this code snippet:
 <s> MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } else {"
LLVM,NVPTX,639,"Predict the next statement of this code snippet:
 <s> if ( MF . getFrameInfo ( ) -> hasStackObjects ( ) ) { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = DebugLoc ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . is64Bit ( ) ) { unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } else { unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } }"
LLVM,NVPTX,640,"Predict the next statement of this code snippet:
 <s> if ( tm . getSubtargetImpl ( ) -> hasGenericLdSt ( ) ) { if ( is64bit ) { MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } } else { if ( is64bit ) BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; }"
LLVM,NVPTX,641,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {"
LLVM,NVPTX,642,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {"
LLVM,NVPTX,643,"Predict the next statement of this code snippet:
 <s> BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } } else { if ( is64bit ) BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ;"
LLVM,NVPTX,644,"Predict the next statement of this code snippet:
 <s> } else { unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; }"
LLVM,NVPTX,645,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>FrameLowering ::"
LLVM,NVPTX,646,"Predict the next statement of this code snippet:
 <s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {"
LLVM,NVPTX,647,"Predict the next statement of this code snippet:
 <s> unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; }"
LLVM,NVPTX,648,"Predict the next statement of this code snippet:
 <s> unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ;"
LLVM,NVPTX,649,"Predict the next statement of this code snippet:
 <s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;"
LLVM,NVPTX,650,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = DebugLoc ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( is64bit ) { unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } else { unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; }"
LLVM,NVPTX,651,"Predict the next statement of this code snippet:
 <s> MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } else { unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; }"
LLVM,NVPTX,652,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , is64bit ( STI . is64Bit ( ) ) {"
LLVM,NVPTX,653,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , is64bit ( STI . is64Bit ( ) ) {"
LLVM,NVPTX,654,"Predict the next statement of this code snippet:
 <s> GlobalVariable * GV = & * I ++ ; if ( GV -> getType ( ) -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GENERIC && ! llvm :: isTexture ( * GV ) && ! llvm :: isSurface ( * GV ) && ! llvm :: isSampler ( * GV ) && ! GV -> getName ( ) . startswith ( <STR_LIT> ) ) { GlobalVariable * NewGV = new GlobalVariable ( M , GV -> getValueType ( ) , GV -> isConstant ( ) , GV -> getLinkage ( ) , GV -> hasInitializer ( ) ? GV -> getInitializer ( ) : nullptr , <STR_LIT> , GV , GV -> getThreadLocalMode ( ) , llvm :: ADDRESS_SPACE_GLOBAL ) ; NewGV -> copyAttributesFrom ( GV ) ; GVMap [ GV ] = NewGV ; } } if ( GVMap . empty ( ) ) { return false ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; }"
LLVM,NVPTX,655,"Predict the next statement of this code snippet:
 <s> ParamTypes . push_back ( DestTy ) ; Function * CVTAFunction = <STR_LIT> ( M , <STR_LIT> , ParamTypes ) ; CVTA = Builder . CreateCall ( CVTAFunction , CVTA , <STR_LIT> ) ; DestTy = PointerType :: get ( GVType -> getElementType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ; CVTA = Builder . CreateBitCast ( CVTA , DestTy , <STR_LIT> ) ; } else { SmallVector < Type * , <NUM_LIT> > ParamTypes ; ParamTypes . push_back ( PointerType :: get ( GVType -> getElementType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ) ;"
LLVM,NVPTX,656,"Predict the next statement of this code snippet:
 <s> Type * ResultType = PointerType :: get ( Type :: getInt8Ty ( Context ) , llvm :: ADDRESS_SPACE_GENERIC ) ; SmallVector < Type * , <NUM_LIT> > ParamTypes ; ParamTypes . push_back ( ResultType ) ; ParamTypes . push_back ( DestTy ) ; Function * CVTAFunction = <STR_LIT> ( M , <STR_LIT> , ParamTypes ) ; CVTA = Builder . CreateCall ( CVTAFunction , CVTA , <STR_LIT> ) ; DestTy = PointerType :: get ( GVType -> getElementType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ; CVTA = Builder . CreateBitCast ( CVTA , DestTy , <STR_LIT> ) ; } else { SmallVector < Type * , <NUM_LIT> > ParamTypes ;"
LLVM,NVPTX,657,"Predict the next statement of this code snippet:
 <s> } else if ( isa < ConstantVector > ( C ) || isa < ConstantArray > ( C ) || isa < ConstantStruct > ( C ) ) { NewValue = remapConstantVectorOrConstantAggregate ( M , F , C , Builder ) ; } else if ( isa < ConstantExpr > ( C ) ) { NewValue = remapConstantExpr ( M , F , cast < ConstantExpr > ( C ) , Builder ) ; } ConstantToValueMap [ C ] = NewValue ;"
LLVM,NVPTX,658,"Predict the next statement of this code snippet:
 <s> MDNode * GenericToNVVM :: remapMDNode ( Module * M , MDNode * N ) { bool OperandChanged = false ; SmallVector < Value * , <NUM_LIT> > NewOperands ; unsigned NumOperands = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { Value * Operand = N -> getOperand ( i ) ; Value * NewOperand = Operand ; if ( Operand ) { if ( isa < GlobalVariable > ( Operand ) ) { GVMapTy :: iterator I = GVMap . find ( cast < GlobalVariable > ( Operand ) ) ; if ( I != GVMap . end ( ) ) { NewOperand = I -> second ; if ( ++ i < NumOperands ) { NewOperands . push_back ( NewOperand ) ; NewOperand = ConstantInt :: get ( Type :: getInt32Ty ( M -> getContext ( ) ) , I -> second -> getType ( ) -> getAddressSpace ( ) ) ; } } } else if ( isa < MDNode > ( Operand ) ) { NewOperand = remapMDNode ( M , cast < MDNode > ( Operand ) ) ; }"
LLVM,NVPTX,659,"Predict the next statement of this code snippet:
 <s> Value * NewOperand = Operand ; if ( Operand ) { if ( isa < GlobalVariable > ( Operand ) ) { GVMapTy :: iterator I = GVMap . find ( cast < GlobalVariable > ( Operand ) ) ; if ( I != GVMap . end ( ) ) { NewOperand = I -> second ; if ( ++ i < NumOperands ) { NewOperands . push_back ( NewOperand ) ; NewOperand = ConstantInt :: get ( Type :: getInt32Ty ( M -> getContext ( ) ) , I -> second -> getType ( ) -> getAddressSpace ( ) ) ; } } } else if ( isa < MDNode > ( Operand ) ) { NewOperand = remapMDNode ( M , cast < MDNode > ( Operand ) ) ; } } OperandChanged |= Operand != NewOperand ; NewOperands . push_back ( NewOperand ) ; } if ( ! OperandChanged ) { return N ;"
LLVM,NVPTX,660,"Predict the next statement of this code snippet:
 <s> MDNode * Operand = N -> getOperand ( i ) ; MDNode * NewOperand = remapMDNode ( M , Operand ) ; OperandChanged |= Operand != NewOperand ; NewOperands . push_back ( NewOperand ) ; } if ( ! OperandChanged ) { return ; } N -> dropAllReferences ( ) ;"
LLVM,NVPTX,661,"Predict the next statement of this code snippet:
 <s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const {"
LLVM,NVPTX,662,"Predict the next statement of this code snippet:
 <s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const {"
LLVM,NVPTX,663,"Predict the next statement of this code snippet:
 <s> case Instruction :: GetElementPtr : return Builder . CreateGEP ( cast < GEPOperator > ( C ) -> getSourceElementType ( ) , NewOperands [ <NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) , <STR_LIT> , cast < GEPOperator > ( C ) -> isInBounds ( ) ) ; case Instruction :: Select : return Builder . CreateSelect ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; default : if ( Instruction :: isBinaryOp ( Opcode ) ) { return Builder . CreateBinOp ( Instruction :: BinaryOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; } if ( Instruction :: isCast ( Opcode ) ) { return Builder . CreateCast ( Instruction :: CastOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , C -> getType ( ) ) ;"
LLVM,NVPTX,664,"Predict the next statement of this code snippet:
 <s> } } } } ConstantToValueMap . clear ( ) ; } ValueToValueMapTy VM ; for ( auto I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ++ I ) VM [ I -> first ] = I -> second ; for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; auto Next = std :: next ( I ) ; GVMap . erase ( I ) ; I = Next ; Constant * BitCastNewGV = ConstantExpr :: getPointerCast ( NewGV , GV -> getType ( ) ) ; GV -> replaceAllUsesWith ( BitCastNewGV ) ; std :: string Name = std :: string ( GV -> getName ( ) ) ; GV -> eraseFromParent ( ) ; NewGV -> setName ( Name ) ; } assert ( GVMap . empty ( ) && <STR_LIT> ) ;"
LLVM,NVPTX,665,"Predict the next statement of this code snippet:
 <s> unsigned int AddrSpace = GVType -> getAddressSpace ( ) ; Type * DestTy = PointerType :: get ( Type :: getInt8Ty ( Context ) , AddrSpace ) ; CVTA = Builder . CreateBitCast ( GV , DestTy , <STR_LIT> ) ; Type * ResultType = PointerType :: get ( Type :: getInt8Ty ( Context ) , llvm :: ADDRESS_SPACE_GENERIC ) ; SmallVector < Type * , <NUM_LIT> > ParamTypes ; ParamTypes . push_back ( ResultType ) ; ParamTypes . push_back ( DestTy ) ; Function * CVTAFunction = <STR_LIT> ( M , <STR_LIT> , ParamTypes ) ; CVTA = Builder . CreateCall ( CVTAFunction , CVTA , <STR_LIT> ) ; DestTy = PointerType :: get ( GV -> getValueType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ; CVTA = Builder . CreateBitCast ( CVTA , DestTy , <STR_LIT> ) ;"
LLVM,NVPTX,666,"Predict the next statement of this code snippet:
 <s> Value * GenericToNVVM :: getOrInsertCVTA ( Module * M , Function * F , GlobalVariable * GV , IRBuilder < > & Builder ) { PointerType * GVType = GV -> getType ( ) ; Value * CVTA = nullptr ; EVT ExtendedGVType = EVT :: getEVT ( GV -> getValueType ( ) , true ) ; if ( ! ExtendedGVType . isInteger ( ) && ! ExtendedGVType . isFloatingPoint ( ) ) { LLVMContext & Context = M -> getContext ( ) ;"
LLVM,NVPTX,667,"Predict the next statement of this code snippet:
 <s> MDNode * Operand = N -> getOperand ( i ) ; MDNode * NewOperand = MapMetadata ( Operand , VM ) ; OperandChanged |= Operand != NewOperand ; NewOperands . push_back ( NewOperand ) ; } if ( ! OperandChanged ) {"
LLVM,NVPTX,668,"Predict the next statement of this code snippet:
 <s> OperandChanged |= Operand != NewOperand ; NewOperands . push_back ( NewOperand ) ; } if ( ! OperandChanged ) { return ; } N -> dropAllReferences ( ) ; for ( SmallVectorImpl < MDNode * > :: iterator I = NewOperands . begin ( ) , E = NewOperands . end ( ) ; I != E ; ++ I ) { N -> addOperand ( * I ) ;"
LLVM,NVPTX,669,"Predict the next statement of this code snippet:
 <s> } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , & * I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } ValueToValueMapTy VM ; for ( auto I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ++ I ) VM [ I -> first ] = I -> second ; for ( NamedMDNode & I : M . named_metadata ( ) ) { remapNamedMDNode ( VM , & I ) ; } for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; auto Next = std :: next ( I ) ; GVMap . erase ( I ) ; I = Next ;"
LLVM,NVPTX,670,"Predict the next statement of this code snippet:
 <s> for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , & * I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } ValueToValueMapTy VM ;"
LLVM,NVPTX,671,"Predict the next statement of this code snippet:
 <s> for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , & * I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } ValueToValueMapTy VM ; for ( auto I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ++ I ) VM [ I -> first ] = I -> second ; for ( NamedMDNode & I : M . named_metadata ( ) ) { remapNamedMDNode ( VM , & I ) ; } for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; auto Next = std :: next ( I ) ; GVMap . erase ( I ) ; I = Next ; Constant * BitCastNewGV = ConstantExpr :: getPointerCast ( NewGV , GV -> getType ( ) ) ; GV -> replaceAllUsesWith ( BitCastNewGV ) ;"
LLVM,NVPTX,672,"Predict the next statement of this code snippet:
 <s> Value * CVTA = nullptr ; EVT ExtendedGVType = EVT :: getEVT ( GV -> getValueType ( ) , true ) ; if ( ! ExtendedGVType . isInteger ( ) && ! ExtendedGVType . isFloatingPoint ( ) ) { LLVMContext & Context = M -> getContext ( ) ; unsigned int AddrSpace = GVType -> getAddressSpace ( ) ; Type * DestTy = PointerType :: get ( Type :: getInt8Ty ( Context ) , AddrSpace ) ; CVTA = Builder . CreateBitCast ( GV , DestTy , <STR_LIT> ) ; Type * ResultType = PointerType :: get ( Type :: getInt8Ty ( Context ) , llvm :: ADDRESS_SPACE_GENERIC ) ; Function * CVTAFunction = <STR_LIT> ( M , <STR_LIT> , { ResultType , DestTy } ) ;"
LLVM,NVPTX,673,"Predict the next statement of this code snippet:
 <s> return CTII -> second ; } Value * NewValue = C ; if ( isa < GlobalVariable > ( C ) ) { GVMapTy :: iterator I = GVMap . find ( cast < GlobalVariable > ( C ) ) ; if ( I != GVMap . end ( ) ) { NewValue = getOrInsertCVTA ( M , F , I -> second , Builder ) ; } } else if ( isa < ConstantAggregate > ( C ) ) { NewValue = remapConstantVectorOrConstantAggregate ( M , F , C , Builder ) ;"
LLVM,NVPTX,674,"Predict the next statement of this code snippet:
 <s> return CTII -> second ; } Value * NewValue = C ; if ( isa < GlobalVariable > ( C ) ) { GVMapTy :: iterator I = GVMap . find ( cast < GlobalVariable > ( C ) ) ; if ( I != GVMap . end ( ) ) { NewValue = getOrInsertCVTA ( M , F , I -> second , Builder ) ; } } else if ( isa < ConstantAggregate > ( C ) ) { NewValue = remapConstantVectorOrConstantAggregate ( M , F , C , Builder ) ; } else if ( isa < ConstantExpr > ( C ) ) { NewValue = remapConstantExpr ( M , F , cast < ConstantExpr > ( C ) , Builder ) ; }"
LLVM,NVPTX,675,"Predict the next statement of this code snippet:
 <s> } if ( ! OperandChanged ) { return C ; } Value * NewValue = UndefValue :: get ( C -> getType ( ) ) ; if ( isa < ConstantVector > ( C ) ) { for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { Value * Idx = ConstantInt :: get ( Type :: getInt32Ty ( M -> getContext ( ) ) , i ) ; NewValue = Builder . CreateInsertElement ( NewValue , NewOperands [ i ] , Idx ) ; } } else {"
LLVM,NVPTX,676,"Predict the next statement of this code snippet:
 <s> } if ( ! OperandChanged ) { return C ; } Value * NewValue = UndefValue :: get ( C -> getType ( ) ) ; if ( isa < ConstantVector > ( C ) ) { for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { Value * Idx = ConstantInt :: get ( Type :: getInt32Ty ( M -> getContext ( ) ) , i ) ; NewValue = Builder . CreateInsertElement ( NewValue , NewOperands [ i ] , Idx ) ; } } else { for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { NewValue = Builder . CreateInsertValue ( NewValue , NewOperands [ i ] , makeArrayRef ( i ) ) ; }"
LLVM,NVPTX,677,"Predict the next statement of this code snippet:
 <s> GVMap [ GV ] = NewGV ; } } if ( GVMap . empty ( ) ) { return false ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , & * I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } ValueToValueMapTy VM ;"
LLVM,NVPTX,678,"Predict the next statement of this code snippet:
 <s> SmallVector < Value * , <NUM_LIT> > NewOperands ; unsigned NumOperands = C -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { Value * Operand = C -> getOperand ( i ) ; Value * NewOperand = remapConstant ( M , F , cast < Constant > ( Operand ) , Builder ) ; OperandChanged |= Operand != NewOperand ; NewOperands . push_back ( NewOperand ) ; } if ( ! OperandChanged ) { return C ; } unsigned Opcode = C -> getOpcode ( ) ; switch ( Opcode ) { case Instruction :: ICmp : return Builder . CreateICmp ( CmpInst :: Predicate ( C -> getPredicate ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: FCmp : assert ( false && <STR_LIT> <STR_LIT> ) ; return C ; case Instruction :: ExtractElement : return Builder . CreateExtractElement ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: InsertElement : return Builder . CreateInsertElement ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: ShuffleVector : return Builder . CreateShuffleVector ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: ExtractValue : return Builder . CreateExtractValue ( NewOperands [ <NUM_LIT> ] , C -> getIndices ( ) ) ; case Instruction :: InsertValue : return Builder . CreateInsertValue ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , C -> getIndices ( ) ) ; case Instruction :: GetElementPtr :"
LLVM,NVPTX,679,"Predict the next statement of this code snippet:
 <s> switch ( Opcode ) { case Instruction :: ICmp : return Builder . CreateICmp ( CmpInst :: Predicate ( C -> getPredicate ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: FCmp : assert ( false && <STR_LIT> <STR_LIT> ) ; return C ; case Instruction :: ExtractElement : return Builder . CreateExtractElement ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: InsertElement : return Builder . CreateInsertElement ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: ShuffleVector : return Builder . CreateShuffleVector ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: ExtractValue : return Builder . CreateExtractValue ( NewOperands [ <NUM_LIT> ] , C -> getIndices ( ) ) ; case Instruction :: InsertValue : return Builder . CreateInsertValue ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , C -> getIndices ( ) ) ; case Instruction :: GetElementPtr : return cast < GEPOperator > ( C ) -> isInBounds ( ) ? Builder . CreateGEP ( cast < GEPOperator > ( C ) -> getSourceElementType ( ) , NewOperands [ <NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) ) : Builder . CreateInBoundsGEP ( cast < GEPOperator > ( C ) -> getSourceElementType ( ) , NewOperands [ <NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) ) ; case Instruction :: Select : return Builder . CreateSelect ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; default : if ( Instruction :: isBinaryOp ( Opcode ) ) { return Builder . CreateBinOp ( Instruction :: BinaryOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; } if ( Instruction :: isCast ( Opcode ) ) { return Builder . CreateCast ( Instruction :: CastOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , C -> getType ( ) ) ; }"
LLVM,NVPTX,680,"Predict the next statement of this code snippet:
 <s> if ( GV -> getType ( ) -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GENERIC && ! llvm :: isTexture ( * GV ) && ! llvm :: isSurface ( * GV ) && ! GV -> getName ( ) . startswith ( <STR_LIT> ) ) { GlobalVariable * NewGV = new GlobalVariable ( M , GV -> getType ( ) -> getElementType ( ) , GV -> isConstant ( ) , GV -> getLinkage ( ) , GV -> hasInitializer ( ) ? GV -> getInitializer ( ) : NULL , <STR_LIT> , GV , GV -> getThreadLocalMode ( ) , llvm :: ADDRESS_SPACE_GLOBAL ) ; NewGV -> copyAttributesFrom ( GV ) ; GVMap [ GV ] = NewGV ; } } if ( GVMap . empty ( ) ) { return false ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ;"
LLVM,NVPTX,681,"Predict the next statement of this code snippet:
 <s> if ( GVMap . empty ( ) ) { return false ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } for ( Module :: named_metadata_iterator I = M . named_metadata_begin ( ) , E = M . named_metadata_end ( ) ; I != E ; I ++ ) { remapNamedMDNode ( & M , I ) ; } for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; ++ I ; Constant * BitCastNewGV = ConstantExpr :: getBitCast ( NewGV , GV -> getType ( ) ) ; for ( Value :: use_iterator UI = GV -> use_begin ( ) , UE = GV -> use_end ( ) ; UI != UE ; ) { Use & U = ( UI ++ ) . getUse ( ) ; U . set ( BitCastNewGV ) ; } std :: string Name = GV -> getName ( ) ; GV -> removeDeadConstantUsers ( ) ; GV -> eraseFromParent ( ) ; NewGV -> setName ( Name ) ; } GVMap . clear ( ) ;"
LLVM,NVPTX,682,"Predict the next statement of this code snippet:
 <s> MDNode * GenericToNVVM :: remapMDNode ( Module * M , MDNode * N ) { bool OperandChanged = false ; SmallVector < Metadata * , <NUM_LIT> > NewOperands ; unsigned NumOperands = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { Metadata * Operand = N -> getOperand ( i ) ; Metadata * NewOperand = Operand ; if ( Operand ) { if ( auto * N = dyn_cast < MDNode > ( Operand ) ) { NewOperand = remapMDNode ( M , N ) ; } else if ( auto * C = dyn_cast < ConstantAsMetadata > ( Operand ) ) { if ( auto * G = dyn_cast < GlobalVariable > ( C -> getValue ( ) ) ) {"
LLVM,NVPTX,683,"Predict the next statement of this code snippet:
 <s> GlobalVariable * GV = I ++ ; if ( GV -> getType ( ) -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GENERIC && ! llvm :: isTexture ( * GV ) && ! llvm :: isSurface ( * GV ) && ! llvm :: isSampler ( * GV ) && ! GV -> getName ( ) . startswith ( <STR_LIT> ) ) { GlobalVariable * NewGV = new GlobalVariable ( M , GV -> getType ( ) -> getElementType ( ) , GV -> isConstant ( ) , GV -> getLinkage ( ) , GV -> hasInitializer ( ) ? GV -> getInitializer ( ) : nullptr , <STR_LIT> , GV , GV -> getThreadLocalMode ( ) , llvm :: ADDRESS_SPACE_GLOBAL ) ; NewGV -> copyAttributesFrom ( GV ) ; GVMap [ GV ] = NewGV ; } } if ( GVMap . empty ( ) ) { return false ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; }"
LLVM,NVPTX,684,"Predict the next statement of this code snippet:
 <s> for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; }"
LLVM,NVPTX,685,"Predict the next statement of this code snippet:
 <s> ParamTypes . push_back ( ResultType ) ; ParamTypes . push_back ( DestTy ) ; Function * CVTAFunction = <STR_LIT> ( M , <STR_LIT> , ParamTypes ) ; CVTA = Builder . CreateCall ( CVTAFunction , CVTA , <STR_LIT> ) ; DestTy = PointerType :: get ( GVType -> getElementType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ; CVTA = Builder . CreateBitCast ( CVTA , DestTy , <STR_LIT> ) ; } else { SmallVector < Type * , <NUM_LIT> > ParamTypes ; ParamTypes . push_back ( PointerType :: get ( GVType -> getElementType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ) ; ParamTypes . push_back ( GVType ) ; Function * CVTAFunction = <STR_LIT> ( M , <STR_LIT> , ParamTypes ) ; CVTA = Builder . CreateCall ( CVTAFunction , GV , <STR_LIT> ) ; }"
LLVM,NVPTX,686,"Predict the next statement of this code snippet:
 <s> LLVMContext & Context = M -> getContext ( ) ; unsigned int AddrSpace = GVType -> getAddressSpace ( ) ; Type * DestTy = PointerType :: get ( Type :: getInt8Ty ( Context ) , AddrSpace ) ; CVTA = Builder . CreateBitCast ( GV , DestTy , <STR_LIT> ) ; Type * ResultType = PointerType :: get ( Type :: getInt8Ty ( Context ) , llvm :: ADDRESS_SPACE_GENERIC ) ; SmallVector < Type * , <NUM_LIT> > ParamTypes ; ParamTypes . push_back ( ResultType ) ; ParamTypes . push_back ( DestTy ) ; Function * CVTAFunction = <STR_LIT> ( M , <STR_LIT> , ParamTypes ) ; CVTA = Builder . CreateCall ( CVTAFunction , CVTA , <STR_LIT> ) ; DestTy = PointerType :: get ( GVType -> getElementType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ; CVTA = Builder . CreateBitCast ( CVTA , DestTy , <STR_LIT> ) ; } else { SmallVector < Type * , <NUM_LIT> > ParamTypes ; ParamTypes . push_back ( PointerType :: get ( GVType -> getElementType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ) ;"
LLVM,NVPTX,687,"Predict the next statement of this code snippet:
 <s> if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } for ( Module :: named_metadata_iterator I = M . named_metadata_begin ( ) , E = M . named_metadata_end ( ) ; I != E ; I ++ ) { remapNamedMDNode ( & M , I ) ; } for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; ++ I ; Constant * BitCastNewGV = ConstantExpr :: getPointerCast ( NewGV , GV -> getType ( ) ) ; for ( Value :: use_iterator UI = GV -> use_begin ( ) , UE = GV -> use_end ( ) ; UI != UE ; ) ( UI ++ ) -> set ( BitCastNewGV ) ; std :: string Name = GV -> getName ( ) ; GV -> removeDeadConstantUsers ( ) ;"
LLVM,NVPTX,688,"Predict the next statement of this code snippet:
 <s> IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } for ( Module :: named_metadata_iterator I = M . named_metadata_begin ( ) , E = M . named_metadata_end ( ) ;"
LLVM,NVPTX,689,"Predict the next statement of this code snippet:
 <s> ModulePass * llvm :: createGenericToNVVMPass ( ) { return new GenericToNVVM ( ) ;"
LLVM,NVPTX,690,"Predict the next statement of this code snippet:
 <s> ModulePass * llvm :: createGenericToNVVMPass ( ) {"
LLVM,NVPTX,691,"Predict the next statement of this code snippet:
 <s> GenericToNVVM ( ) : ModulePass ( ID ) {"
LLVM,NVPTX,692,"Predict the next statement of this code snippet:
 <s> GenericToNVVM ( ) : ModulePass ( ID ) {"
LLVM,NVPTX,693,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {"
LLVM,NVPTX,694,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {"
LLVM,NVPTX,695,"Predict the next statement of this code snippet:
 <s> } Value * NewValue = C ; if ( isa < GlobalVariable > ( C ) ) { GVMapTy :: iterator I = GVMap . find ( cast < GlobalVariable > ( C ) ) ; if ( I != GVMap . end ( ) ) { GlobalVariable * GV = I -> second ;"
LLVM,NVPTX,696,"Predict the next statement of this code snippet:
 <s> GlobalVariable * GV = I -> second ; NewValue = Builder . CreateAddrSpaceCast ( GV , PointerType :: get ( GV -> getValueType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ) ; } } else if ( isa < ConstantAggregate > ( C ) ) { NewValue = remapConstantVectorOrConstantAggregate ( M , F , C , Builder ) ; } else if ( isa < ConstantExpr > ( C ) ) { NewValue = remapConstantExpr ( M , F , cast < ConstantExpr > ( C ) , Builder ) ; } ConstantToValueMap [ C ] = NewValue ; return NewValue ;"
LLVM,NVPTX,697,"Predict the next statement of this code snippet:
 <s> case Instruction :: ICmp : return Builder . CreateICmp ( CmpInst :: Predicate ( C -> getPredicate ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: FCmp : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; case Instruction :: ExtractElement : return Builder . CreateExtractElement ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: InsertElement : return Builder . CreateInsertElement ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: ShuffleVector : return Builder . CreateShuffleVector ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: ExtractValue : return Builder . CreateExtractValue ( NewOperands [ <NUM_LIT> ] , C -> getIndices ( ) ) ; case Instruction :: InsertValue : return Builder . CreateInsertValue ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , C -> getIndices ( ) ) ; case Instruction :: GetElementPtr : return cast < GEPOperator > ( C ) -> isInBounds ( ) ? Builder . CreateGEP ( cast < GEPOperator > ( C ) -> getSourceElementType ( ) , NewOperands [ <NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) ) : Builder . CreateInBoundsGEP ( cast < GEPOperator > ( C ) -> getSourceElementType ( ) , NewOperands [ <NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) ) ; case Instruction :: Select : return Builder . CreateSelect ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; default : if ( Instruction :: isBinaryOp ( Opcode ) ) { return Builder . CreateBinOp ( Instruction :: BinaryOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; } if ( Instruction :: isCast ( Opcode ) ) { return Builder . CreateCast ( Instruction :: CastOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , C -> getType ( ) ) ; } llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,NVPTX,698,"Predict the next statement of this code snippet:
 <s> } Value * NewValue = PoisonValue :: get ( C -> getType ( ) ) ; if ( isa < ConstantVector > ( C ) ) { for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { Value * Idx = ConstantInt :: get ( Type :: getInt32Ty ( M -> getContext ( ) ) , i ) ; NewValue = Builder . CreateInsertElement ( NewValue , NewOperands [ i ] , Idx ) ; } } else { for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { NewValue = Builder . CreateInsertValue ( NewValue , NewOperands [ i ] , makeArrayRef ( i ) ) ; } } return NewValue ;"
LLVM,NVPTX,699,"Predict the next statement of this code snippet:
 <s> if ( GV . getType ( ) -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GENERIC && ! llvm :: isTexture ( GV ) && ! llvm :: isSurface ( GV ) && ! llvm :: isSampler ( GV ) && ! GV . getName ( ) . startswith ( <STR_LIT> ) ) { GlobalVariable * NewGV = new GlobalVariable ( M , GV . getValueType ( ) , GV . isConstant ( ) , GV . getLinkage ( ) , GV . hasInitializer ( ) ? GV . getInitializer ( ) : nullptr , <STR_LIT> , & GV , GV . getThreadLocalMode ( ) , llvm :: ADDRESS_SPACE_GLOBAL ) ; NewGV -> copyAttributesFrom ( & GV ) ; GVMap [ & GV ] = NewGV ; } } if ( GVMap . empty ( ) ) { return false ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , & * I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } ValueToValueMapTy VM ; for ( auto I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ++ I ) VM [ I -> first ] = I -> second ; for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; auto Next = std :: next ( I ) ; GVMap . erase ( I ) ; I = Next ; Constant * BitCastNewGV = ConstantExpr :: getPointerCast ( NewGV , GV -> getType ( ) ) ; GV -> replaceAllUsesWith ( BitCastNewGV ) ; std :: string Name = std :: string ( GV -> getName ( ) ) ;"
LLVM,NVPTX,700,"Predict the next statement of this code snippet:
 <s> return cleanupValue ( EVI -> getAggregateOperand ( ) ) ; }"
LLVM,NVPTX,701,"Predict the next statement of this code snippet:
 <s> Value * <ISA_LIT>ImageOptimizer :: cleanupValue ( Value * V ) { if ( ExtractValueInst * EVI = dyn_cast < ExtractValueInst > ( V ) ) { return cleanupValue ( EVI -> getAggregateOperand ( ) ) ;"
LLVM,NVPTX,702,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>ImageOptimizerPass ( ) { return new <ISA_LIT>ImageOptimizer ( ) ;"
LLVM,NVPTX,703,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>ImageOptimizerPass ( ) { return new <ISA_LIT>ImageOptimizer ( ) ;"
LLVM,NVPTX,704,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ImageOptimizer :: <ISA_LIT>ImageOptimizer ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,705,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ImageOptimizer :: <ISA_LIT>ImageOptimizer ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,706,"Predict the next statement of this code snippet:
 <s> if ( isSampler ( * TexHandle ) ) { replaceWith ( & I , ConstantInt :: getTrue ( I . getContext ( ) ) ) ; return true ; } else if ( isImage ( * TexHandle ) ) { replaceWith ( & I , ConstantInt :: getFalse ( I . getContext ( ) ) ) ; return true ;"
LLVM,NVPTX,707,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ImageOptimizer :: replaceIsTypePSurface ( Instruction & I ) { Value * TexHandle = cleanupValue ( I . getOperand ( <NUM_LIT> ) ) ; if ( isImageReadWrite ( * TexHandle ) || isImageWriteOnly ( * TexHandle ) ) {"
LLVM,NVPTX,708,"Predict the next statement of this code snippet:
 <s> return true ; } else if ( isImageReadOnly ( * TexHandle ) || isSampler ( * TexHandle ) ) { replaceWith ( & I , ConstantInt :: getFalse ( I . getContext ( ) ) ) ; return true ; } else {"
LLVM,NVPTX,709,"Predict the next statement of this code snippet:
 <s> replaceWith ( & I , ConstantInt :: getTrue ( I . getContext ( ) ) ) ; return true ;"
LLVM,NVPTX,710,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>ImageOptimizer :: replaceWith ( Instruction * From , ConstantInt * To ) { for ( CallInst :: use_iterator UI = From -> use_begin ( ) , UE = From -> use_end ( ) ; UI != UE ; ++ UI ) { if ( BranchInst * BI = dyn_cast < BranchInst > ( * UI ) ) { if ( BI -> isUnconditional ( ) ) continue ; BasicBlock * Dest ; if ( To -> isZero ( ) ) Dest = BI -> getSuccessor ( <NUM_LIT> ) ;"
LLVM,NVPTX,711,"Predict the next statement of this code snippet:
 <s> BasicBlock * Dest ; if ( To -> isZero ( ) ) Dest = BI -> getSuccessor ( <NUM_LIT> ) ; else Dest = BI -> getSuccessor ( <NUM_LIT> ) ; BranchInst :: Create ( Dest , BI ) ;"
LLVM,NVPTX,712,"Predict the next statement of this code snippet:
 <s> for ( Use & U : From -> uses ( ) ) { if ( BranchInst * BI = dyn_cast < BranchInst > ( U ) ) { if ( BI -> isUnconditional ( ) ) continue ; BasicBlock * Dest ; if ( To -> isZero ( ) ) Dest = BI -> getSuccessor ( <NUM_LIT> ) ; else Dest = BI -> getSuccessor ( <NUM_LIT> ) ; BranchInst :: Create ( Dest , BI ) ; InstrToDelete . push_back ( BI ) ; }"
LLVM,NVPTX,713,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ImageOptimizer :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; bool Changed = false ; InstrToDelete . clear ( ) ; for ( BasicBlock & BB : F ) { for ( Instruction & Instr : BB ) { if ( CallInst * CI = dyn_cast < CallInst > ( & Instr ) ) { Function * CalledF = CI -> getCalledFunction ( ) ; if ( CalledF && CalledF -> isIntrinsic ( ) ) { switch ( CalledF -> getIntrinsicID ( ) ) { default : break ; case <STR_LIT> : Changed |= replaceIsTypePSampler ( Instr ) ; break ; case <STR_LIT> : Changed |= replaceIsTypePSurface ( Instr ) ; break ; case <STR_LIT> : Changed |= replaceIsTypePTexture ( Instr ) ; break ; } } } }"
LLVM,NVPTX,714,"Predict the next statement of this code snippet:
 <s> } else if ( isImageWriteOnly ( * TexHandle ) || isImageReadWrite ( * TexHandle ) || isImageReadOnly ( * TexHandle ) ) { replaceWith ( & I , ConstantInt :: getFalse ( I . getContext ( ) ) ) ; return true ; } else { return false ;"
LLVM,NVPTX,715,"Predict the next statement of this code snippet:
 <s> return true ; } else if ( isImageWriteOnly ( * TexHandle ) || isImageReadWrite ( * TexHandle ) || isImageReadOnly ( * TexHandle ) ) { replaceWith ( & I , ConstantInt :: getFalse ( I . getContext ( ) ) ) ; return true ; } else { return false ;"
LLVM,NVPTX,716,"Predict the next statement of this code snippet:
 <s> Function * CalledF = CI -> getCalledFunction ( ) ; if ( CalledF && CalledF -> isIntrinsic ( ) ) { switch ( CalledF -> getIntrinsicID ( ) ) { default : break ; case <STR_LIT> : Changed |= replaceIsTypePSampler ( Instr ) ; break ; case <STR_LIT> : Changed |= replaceIsTypePSurface ( Instr ) ; break ; case <STR_LIT> : Changed |= replaceIsTypePTexture ( Instr ) ; break ; } } } } }"
LLVM,NVPTX,717,"Predict the next statement of this code snippet:
 <s> assert ( V -> getType ( ) -> isPointerTy ( ) ) ; if ( isAddressExpression ( * V ) && V -> getType ( ) -> getPointerAddressSpace ( ) == AddressSpace :: ADDRESS_SPACE_GENERIC ) { if ( Visited -> insert ( V ) . second ) PostorderStack -> push_back ( std :: make_pair ( V , false ) ) ;"
LLVM,NVPTX,718,"Predict the next statement of this code snippet:
 <s> Type * TargetType = CE -> getType ( ) -> getPointerElementType ( ) -> getPointerTo ( NewAddrSpace ) ; if ( CE -> getOpcode ( ) == Instruction :: AddrSpaceCast ) { assert ( CE -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getPointerAddressSpace ( ) == NewAddrSpace ) ; return ConstantExpr :: getBitCast ( CE -> getOperand ( <NUM_LIT> ) , TargetType ) ; } SmallVector < Constant * , <NUM_LIT> > NewOperands ; for ( unsigned Index = <NUM_LIT> ; Index < CE -> getNumOperands ( ) ; ++ Index ) { Constant * Operand = CE -> getOperand ( Index ) ; if ( Value * NewOperand = ValueWithNewAddrSpace . lookup ( Operand ) ) { NewOperands . push_back ( cast < Constant > ( NewOperand ) ) ; } else { NewOperands . push_back ( Operand ) ; } } if ( CE -> getOpcode ( ) == Instruction :: GetElementPtr ) {"
LLVM,NVPTX,719,"Predict the next statement of this code snippet:
 <s> SmallVector < Constant * , <NUM_LIT> > NewOperands ; for ( unsigned Index = <NUM_LIT> ; Index < CE -> getNumOperands ( ) ; ++ Index ) { Constant * Operand = CE -> getOperand ( Index ) ; if ( Value * NewOperand = ValueWithNewAddrSpace . lookup ( Operand ) ) { NewOperands . push_back ( cast < Constant > ( NewOperand ) ) ; } else { NewOperands . push_back ( Operand ) ; }"
LLVM,NVPTX,720,"Predict the next statement of this code snippet:
 <s> PHINode * NewPHI = PHINode :: Create ( NewPtrType , PHI -> getNumIncomingValues ( ) ) ; for ( unsigned Index = <NUM_LIT> ; Index < PHI -> getNumIncomingValues ( ) ; ++ Index ) { unsigned OperandNo = PHINode :: getOperandNumForIncomingValue ( Index ) ; NewPHI -> addIncoming ( NewPointerOperands [ OperandNo ] , PHI -> getIncomingBlock ( Index ) ) ; } return NewPHI ; } case Instruction :: GetElementPtr : { GetElementPtrInst * GEP = cast < GetElementPtrInst > ( I ) ; GetElementPtrInst * NewGEP = GetElementPtrInst :: Create ( GEP -> getSourceElementType ( ) , NewPointerOperands [ <NUM_LIT> ] , SmallVector < Value * , <NUM_LIT> > ( GEP -> idx_begin ( ) , GEP -> idx_end ( ) ) ) ; NewGEP -> setIsInBounds ( GEP -> isInBounds ( ) ) ; return NewGEP ; }"
LLVM,NVPTX,721,"Predict the next statement of this code snippet:
 <s> static std :: vector < Value * > collectGenericAddressExpressions ( Function & F ) { std :: vector < std :: pair < Value * , bool >> PostorderStack ; DenseSet < Value * > Visited ; for ( Instruction & I : instructions ( F ) ) { if ( isa < LoadInst > ( I ) ) {"
LLVM,NVPTX,722,"Predict the next statement of this code snippet:
 <s> if ( isa < LoadInst > ( I ) ) { appendsGenericAddressExpressionToPostorderStack ( I . getOperand ( <NUM_LIT> ) , & PostorderStack , & Visited ) ; } else if ( isa < StoreInst > ( I ) ) { appendsGenericAddressExpressionToPostorderStack ( I . getOperand ( <NUM_LIT> ) , & PostorderStack , & Visited ) ; } } std :: vector < Value * > Postorder ; while ( ! PostorderStack . empty ( ) ) { if ( PostorderStack . back ( ) . second ) { Postorder . push_back ( PostorderStack . back ( ) . first ) ; PostorderStack . pop_back ( ) ; continue ; } PostorderStack . back ( ) . second = true ; for ( Value * PtrOperand : getPointerOperands ( * PostorderStack . back ( ) . first ) ) {"
LLVM,NVPTX,723,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>InferAddressSpacesPass ( ) {"
LLVM,NVPTX,724,"Predict the next statement of this code snippet:
 <s> const Operator & Op = cast < Operator > ( V ) ; switch ( Op . getOpcode ( ) ) { case Instruction :: PHI : { auto IncomingValues = cast < PHINode > ( Op ) . incoming_values ( ) ; return SmallVector < Value * , <NUM_LIT> > ( IncomingValues . begin ( ) , IncomingValues . end ( ) ) ; } case Instruction :: BitCast : case Instruction :: AddrSpaceCast : case Instruction :: GetElementPtr :"
LLVM,NVPTX,725,"Predict the next statement of this code snippet:
 <s> assert ( isAddressExpression ( V ) ) ; const Operator & Op = cast < Operator > ( V ) ; switch ( Op . getOpcode ( ) ) { case Instruction :: PHI : { auto IncomingValues = cast < PHINode > ( Op ) . incoming_values ( ) ; return SmallVector < Value * , <NUM_LIT> > ( IncomingValues . begin ( ) , IncomingValues . end ( ) ) ; } case Instruction :: BitCast : case Instruction :: AddrSpaceCast : case Instruction :: GetElementPtr : return { Op . getOperand ( <NUM_LIT> ) } ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,NVPTX,726,"Predict the next statement of this code snippet:
 <s> Optional < unsigned > NewAS = updateAddressSpace ( * V , * InferredAddrSpace ) ; if ( ! NewAS . hasValue ( ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << NewAS . getValue ( ) << <STR_LIT> ) ; ( * InferredAddrSpace ) [ V ] = NewAS . getValue ( ) ; for ( Value * User : V -> users ( ) ) { if ( Worklist . count ( User ) ) continue ; auto Pos = InferredAddrSpace -> find ( User ) ; if ( Pos == InferredAddrSpace -> end ( ) ) continue ; if ( Pos -> second == AddressSpace :: ADDRESS_SPACE_GENERIC ) continue ;"
LLVM,NVPTX,727,"Predict the next statement of this code snippet:
 <s> switch ( cast < Operator > ( V ) . getOpcode ( ) ) { case Instruction :: PHI : case Instruction :: BitCast : case Instruction :: AddrSpaceCast : case Instruction :: GetElementPtr :"
LLVM,NVPTX,728,"Predict the next statement of this code snippet:
 <s> if ( AS2 == ADDRESS_SPACE_UNINITIALIZED ) return AS1 ; return AS1 == AS2 ? AS1 : ( unsigned ) AddressSpace :: ADDRESS_SPACE_GENERIC ;"
LLVM,NVPTX,729,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InferAddressSpaces ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,730,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InferAddressSpaces ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,731,"Predict the next statement of this code snippet:
 <s> UndefUsesToFix -> push_back ( & OperandUse ) ; return UndefValue :: get ( Operand -> getType ( ) -> getPointerElementType ( ) -> getPointerTo ( NewAddrSpace ) ) ;"
LLVM,NVPTX,732,"Predict the next statement of this code snippet:
 <s> if ( NewV == nullptr ) continue ; SmallVector < Use * , <NUM_LIT> > Uses ; for ( Use & U : V -> uses ( ) ) Uses . push_back ( & U ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> << * NewV << <STR_LIT> ) ; for ( Use * U : Uses ) { if ( isa < LoadInst > ( U -> getUser ( ) ) || ( isa < StoreInst > ( U -> getUser ( ) ) && U -> getOperandNo ( ) == <NUM_LIT> ) ) { U -> set ( NewV ) ; } else if ( isa < Instruction > ( U -> getUser ( ) ) ) { if ( Instruction * I = dyn_cast < Instruction > ( V ) ) {"
LLVM,NVPTX,733,"Predict the next statement of this code snippet:
 <s> std :: vector < Value * > Postorder = collectGenericAddressExpressions ( F ) ; ValueToAddrSpaceMapTy InferredAddrSpace ;"
LLVM,NVPTX,734,"Predict the next statement of this code snippet:
 <s> if ( skipFunction ( F ) ) return false ; std :: vector < Value * > Postorder = collectGenericAddressExpressions ( F ) ; ValueToAddrSpaceMapTy InferredAddrSpace ;"
LLVM,NVPTX,735,"Predict the next statement of this code snippet:
 <s> if ( InferredAddrSpace . count ( PtrOperand ) ) OperandAS = InferredAddrSpace . lookup ( PtrOperand ) ; else OperandAS = PtrOperand -> getType ( ) -> getPointerAddressSpace ( ) ; NewAS = joinAddressSpaces ( NewAS , OperandAS ) ; if ( NewAS == AddressSpace :: ADDRESS_SPACE_GENERIC ) break ; } unsigned OldAS = InferredAddrSpace . lookup ( & V ) ; assert ( OldAS != AddressSpace :: ADDRESS_SPACE_GENERIC ) ; if ( OldAS == NewAS ) return None ;"
LLVM,NVPTX,736,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {"
LLVM,NVPTX,737,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {"
LLVM,NVPTX,738,"Predict the next statement of this code snippet:
 <s> printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ;"
LLVM,NVPTX,739,"Predict the next statement of this code snippet:
 <s> if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm ) O << <STR_LIT> ; } else if ( ! strcmp ( Modifier , <STR_LIT> ) ) { switch ( Imm ) { case <STR_LIT> :: GLOBAL : O << <STR_LIT> ; break ; case <STR_LIT> :: SHARED : O << <STR_LIT> ; break ; case <STR_LIT> :: LOCAL : O << <STR_LIT> ; break ; case <STR_LIT> :: PARAM : O << <STR_LIT> ; break ; case <STR_LIT> :: CONSTANT : O << <STR_LIT> ; break ; case <STR_LIT> :: GENERIC : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm == <STR_LIT> :: Signed ) O << <STR_LIT> ;"
LLVM,NVPTX,740,"Predict the next statement of this code snippet:
 <s> int Imm = ( int ) MO . getImm ( ) ; if ( Modifier == nullptr || strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << Imm ; } else if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( Imm >= <NUM_LIT> ) O << <STR_LIT> ;"
LLVM,NVPTX,741,"Predict the next statement of this code snippet:
 <s> unsigned Reg = Op . getReg ( ) ; printRegName ( O , Reg ) ; } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;"
LLVM,NVPTX,742,"Predict the next statement of this code snippet:
 <s> unsigned Reg = Op . getReg ( ) ; printRegName ( O , Reg ) ; } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print ( O , & MAI ) ; }"
LLVM,NVPTX,743,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; }"
LLVM,NVPTX,744,"Predict the next statement of this code snippet:
 <s> printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ;"
LLVM,NVPTX,745,"Predict the next statement of this code snippet:
 <s> int64_t Imm = MO . getImm ( ) ; if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( Imm & <STR_LIT> :: FTZ_FLAG ) O << <STR_LIT> ; } else if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( Imm & <STR_LIT> :: SAT_FLAG ) O << <STR_LIT> ; } else if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( Imm & <STR_LIT> :: RELU_FLAG ) O << <STR_LIT> ; } else if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { switch ( Imm & <STR_LIT> :: BASE_MASK ) { default : return ; case <STR_LIT> :: NONE : break ; case <STR_LIT> :: RNI : O << <STR_LIT> ; break ;"
LLVM,NVPTX,746,"Predict the next statement of this code snippet:
 <s> case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; } unsigned VReg = RegNo & <NUM_LIT> ; OS << VReg ;"
LLVM,NVPTX,747,"Predict the next statement of this code snippet:
 <s> case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; }"
LLVM,NVPTX,748,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; } unsigned VReg = RegNo & <NUM_LIT> ; OS << VReg ;"
LLVM,NVPTX,749,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) : MCInstPrinter ( MAI , MII , MRI ) { setAvailableFeatures ( STI . getFeatureBits ( ) ) ;"
LLVM,NVPTX,750,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> :: LO : O << <STR_LIT> ; break ; case <STR_LIT> :: LS : O << <STR_LIT> ; break ; case <STR_LIT> :: HI : O << <STR_LIT> ; break ; case <STR_LIT> :: HS : O << <STR_LIT> ; break ; case <STR_LIT> :: EQU : O << <STR_LIT> ; break ; case <STR_LIT> :: NEU : O << <STR_LIT> ; break ; case <STR_LIT> :: LTU : O << <STR_LIT> ; break ; case <STR_LIT> :: LEU : O << <STR_LIT> ; break ; case <STR_LIT> :: GTU : O << <STR_LIT> ; break ; case <STR_LIT> :: GEU : O << <STR_LIT> ; break ; case <STR_LIT> :: NUM : O << <STR_LIT> ; break ; case <STR_LIT> :: NotANumber : O << <STR_LIT> ; break ; }"
LLVM,NVPTX,751,"Predict the next statement of this code snippet:
 <s> if ( Imm & <STR_LIT> :: FTZ_FLAG ) O << <STR_LIT> ; } else if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( Imm & <STR_LIT> :: SAT_FLAG ) O << <STR_LIT> ; } else if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { switch ( Imm & <STR_LIT> :: BASE_MASK ) { default : return ; case <STR_LIT> :: NONE : break ; case <STR_LIT> :: RNI : O << <STR_LIT> ; break ; case <STR_LIT> :: RZI : O << <STR_LIT> ; break ; case <STR_LIT> :: RMI : O << <STR_LIT> ; break ; case <STR_LIT> :: RPI :"
LLVM,NVPTX,752,"Predict the next statement of this code snippet:
 <s> default : return ; case <STR_LIT> :: NONE : break ; case <STR_LIT> :: RNI : O << <STR_LIT> ; break ; case <STR_LIT> :: RZI : O << <STR_LIT> ; break ; case <STR_LIT> :: RMI : O << <STR_LIT> ; break ; case <STR_LIT> :: RPI : O << <STR_LIT> ; break ; case <STR_LIT> :: RN : O << <STR_LIT> ; break ; case <STR_LIT> :: RZ : O << <STR_LIT> ; break ; case <STR_LIT> :: RM : O << <STR_LIT> ; break ; case <STR_LIT> :: RP : O << <STR_LIT> ; break ; } } else {"
LLVM,NVPTX,753,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { printInstruction ( MI , OS ) ;"
LLVM,NVPTX,754,"Predict the next statement of this code snippet:
 <s> printInstruction ( MI , OS ) ;"
LLVM,NVPTX,755,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; break ; case <STR_LIT> :: LOCAL : O << <STR_LIT> ; break ; case <STR_LIT> :: PARAM : O << <STR_LIT> ; break ; case <STR_LIT> :: CONSTANT : O << <STR_LIT> ; break ; case <STR_LIT> :: GENERIC : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm == <STR_LIT> :: Signed ) O << <STR_LIT> ; else if ( Imm == <STR_LIT> :: Unsigned ) O << <STR_LIT> ; else O << <STR_LIT> ;"
LLVM,NVPTX,756,"Predict the next statement of this code snippet:
 <s> } else { if ( MI -> getOperand ( OpNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ; printOperand ( MI , OpNum + <NUM_LIT> , O ) ; }"
LLVM,NVPTX,757,"Predict the next statement of this code snippet:
 <s> printRegName ( O , Reg ) ; } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;"
LLVM,NVPTX,758,"Predict the next statement of this code snippet:
 <s> const MCSymbol & Sym = cast < MCSymbolRefExpr > ( Expr ) -> getSymbol ( ) ;"
LLVM,NVPTX,759,"Predict the next statement of this code snippet:
 <s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RegInfo ;"
LLVM,NVPTX,760,"Predict the next statement of this code snippet:
 <s> else if ( DestRC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( DestRC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,NVPTX,761,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ;"
LLVM,NVPTX,762,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( ) , TM ( tm ) , RegInfo ( * TM . getSubtargetImpl ( ) ) {"
LLVM,NVPTX,763,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( ) , TM ( tm ) , RegInfo ( * TM . getSubtargetImpl ( ) ) {"
LLVM,NVPTX,764,"Predict the next statement of this code snippet:
 <s> Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , I , DL , get ( Op ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,NVPTX,765,"Predict the next statement of this code snippet:
 <s> else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else { llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,NVPTX,766,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , MCRegister DestReg , MCRegister SrcReg , bool KillSrc ) const { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( DestReg ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( RegInfo . getRegSizeInBits ( * DestRC ) != RegInfo . getRegSizeInBits ( * SrcRC ) ) report_fatal_error ( <STR_LIT> ) ; unsigned Op ; if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) {"
LLVM,NVPTX,767,"Predict the next statement of this code snippet:
 <s> } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,NVPTX,768,"Predict the next statement of this code snippet:
 <s> assert ( ! BytesAdded && <STR_LIT> ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return <NUM_LIT> ;"
LLVM,NVPTX,769,"Predict the next statement of this code snippet:
 <s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return <NUM_LIT> ;"
LLVM,NVPTX,770,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : RegInfo ( ) {"
LLVM,NVPTX,771,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : RegInfo ( ) {"
LLVM,NVPTX,772,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: anchor ( ) {"
LLVM,NVPTX,773,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>InstrInfo :: anchor ( ) {"
LLVM,NVPTX,774,"Predict the next statement of this code snippet:
 <s> } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,775,"Predict the next statement of this code snippet:
 <s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ;"
LLVM,NVPTX,776,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( ) , RegInfo ( ) {"
LLVM,NVPTX,777,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( ) , RegInfo ( ) {"
LLVM,NVPTX,778,"Predict the next statement of this code snippet:
 <s> I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ;"
LLVM,NVPTX,779,"Predict the next statement of this code snippet:
 <s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ;"
LLVM,NVPTX,780,"Predict the next statement of this code snippet:
 <s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; }"
LLVM,NVPTX,781,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( ) , RegInfo ( STI ) {"
LLVM,NVPTX,782,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( ) , RegInfo ( STI ) {"
LLVM,NVPTX,783,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( DestRC -> getSize ( ) != SrcRC -> getSize ( ) ) report_fatal_error ( <STR_LIT> ) ; unsigned Op ; if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ;"
LLVM,NVPTX,784,"Predict the next statement of this code snippet:
 <s> } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } return true ;"
LLVM,NVPTX,785,"Predict the next statement of this code snippet:
 <s> } else if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; }"
LLVM,NVPTX,786,"Predict the next statement of this code snippet:
 <s> Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else {"
LLVM,NVPTX,787,"Predict the next statement of this code snippet:
 <s> else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return <NUM_LIT> ;"
LLVM,NVPTX,788,"Predict the next statement of this code snippet:
 <s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ;"
LLVM,NVPTX,789,"Predict the next statement of this code snippet:
 <s> else if ( DestRC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( DestRC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( DestRC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else {"
LLVM,NVPTX,790,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( DestRC != SrcRC ) report_fatal_error ( <STR_LIT> ) ; if ( DestRC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( DestRC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,NVPTX,791,"Predict the next statement of this code snippet:
 <s> if ( DestRC -> getSize ( ) != SrcRC -> getSize ( ) ) report_fatal_error ( <STR_LIT> ) ; unsigned Op ; if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ;"
LLVM,NVPTX,792,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL ) const { assert ( TBB && <STR_LIT> ) ;"
LLVM,NVPTX,793,"Predict the next statement of this code snippet:
 <s> if ( LastInst . getOpcode ( ) == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastInst . getOpcode ( ) == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst . getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ; if ( I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ;"
LLVM,NVPTX,794,"Predict the next statement of this code snippet:
 <s> if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( LastInst . getOpcode ( ) == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastInst . getOpcode ( ) == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst . getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ; if ( I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) {"
LLVM,NVPTX,795,"Predict the next statement of this code snippet:
 <s> unsigned addrspace = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return false ;"
LLVM,NVPTX,796,"Predict the next statement of this code snippet:
 <s> return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;"
LLVM,NVPTX,797,"Predict the next statement of this code snippet:
 <s> TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) {"
LLVM,NVPTX,798,"Predict the next statement of this code snippet:
 <s> if ( isLoadInstr ( * MI , addrspace ) ) if ( addrspace == <STR_LIT> :: SHARED ) return false ; if ( isStoreInstr ( * MI , addrspace ) ) if ( addrspace == <STR_LIT> :: SHARED ) return false ;"
LLVM,NVPTX,799,"Predict the next statement of this code snippet:
 <s> else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,NVPTX,800,"Predict the next statement of this code snippet:
 <s> unsigned getLdStCodeAddrSpace ( const MachineInstr & MI ) const { return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;"
LLVM,NVPTX,801,"Predict the next statement of this code snippet:
 <s> return RegInfo ;"
LLVM,NVPTX,802,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {"
LLVM,NVPTX,803,"Predict the next statement of this code snippet:
 <s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return <NUM_LIT> ;"
LLVM,NVPTX,804,"Predict the next statement of this code snippet:
 <s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ;"
LLVM,NVPTX,805,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>InstrInfo :: isLoadInstr ( const MachineInstr & MI , unsigned & AddrSpace ) const { bool isLoad = false ; unsigned TSFlags = ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) >> <STR_LIT> ; isLoad = ( TSFlags == <NUM_LIT> ) ; if ( isLoad ) AddrSpace = getLdStCodeAddrSpace ( MI ) ; return isLoad ;"
LLVM,NVPTX,806,"Predict the next statement of this code snippet:
 <s> isLoad = ( TSFlags == <NUM_LIT> ) ; if ( isLoad ) AddrSpace = getLdStCodeAddrSpace ( MI ) ; return isLoad ;"
LLVM,NVPTX,807,"Predict the next statement of this code snippet:
 <s> bool isMove = false ; unsigned TSFlags = ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) >> <STR_LIT> ; isMove = ( TSFlags == <NUM_LIT> ) ; if ( isMove ) { MachineOperand dest = MI . getOperand ( <NUM_LIT> ) ; MachineOperand src = MI . getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,808,"Predict the next statement of this code snippet:
 <s> unsigned TSFlags = ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) >> <STR_LIT> ; isMove = ( TSFlags == <NUM_LIT> ) ; if ( isMove ) { MachineOperand dest = MI . getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,809,"Predict the next statement of this code snippet:
 <s> bool isStore = false ; unsigned TSFlags = ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) >> <STR_LIT> ; isStore = ( TSFlags == <NUM_LIT> ) ; if ( isStore ) AddrSpace = getLdStCodeAddrSpace ( MI ) ; return isStore ;"
LLVM,NVPTX,810,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( ) , TM ( tm ) , RegInfo ( * this , * TM . getSubtargetImpl ( ) ) {"
LLVM,NVPTX,811,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( ) , TM ( tm ) , RegInfo ( * this , * TM . getSubtargetImpl ( ) ) {"
LLVM,NVPTX,812,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ;"
LLVM,NVPTX,813,"Predict the next statement of this code snippet:
 <s> if ( auto * A = dyn_cast < const Argument > ( V ) ) return IsKernelFn && A -> onlyReadsMemory ( ) && A -> hasNoAliasAttr ( ) ;"
LLVM,NVPTX,814,"Predict the next statement of this code snippet:
 <s> return CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ;"
LLVM,NVPTX,815,"Predict the next statement of this code snippet:
 <s> return CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ;"
LLVM,NVPTX,816,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override {"
LLVM,NVPTX,817,"Predict the next statement of this code snippet:
 <s> Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ;"
LLVM,NVPTX,818,"Predict the next statement of this code snippet:
 <s> if ( IdxConst -> getZExtValue ( ) == <NUM_LIT> ) E0 . push_back ( U ) ; else if ( IdxConst -> getZExtValue ( ) == <NUM_LIT> ) E1 . push_back ( U ) ; else llvm_unreachable ( <STR_LIT> ) ; } } if ( E0 . empty ( ) || E1 . empty ( ) ) return false ; unsigned Op = <STR_LIT> ; SDValue Source = Vector ; if ( Vector -> getOpcode ( ) == <STR_LIT> ) { Op = <STR_LIT> ;"
LLVM,NVPTX,819,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: allowFMA ( ) const { const <ISA_LIT>TargetLowering * TL = Subtarget -> getTargetLowering ( ) ; return TL -> allowFMA ( * MF , OptLevel ) ;"
LLVM,NVPTX,820,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetLowering * TL = Subtarget -> getTargetLowering ( ) ; return TL -> allowUnsafeFPMath ( * MF ) ;"
LLVM,NVPTX,821,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetLowering * TL = Subtarget -> getTargetLowering ( ) ; return TL -> allowUnsafeFPMath ( * MF ) ;"
LLVM,NVPTX,822,"Predict the next statement of this code snippet:
 <s> static bool canLowerToLDG ( MemSDNode * N , const <ISA_LIT>Subtarget & Subtarget , unsigned CodeAddrSpace , MachineFunction * F ) { if ( ! Subtarget . hasLDG ( ) || CodeAddrSpace != <STR_LIT> :: GLOBAL ) return false ; if ( N -> isInvariant ( ) ) return true ; bool IsKernelFn = isKernelFunction ( F -> getFunction ( ) ) ; SmallVector < const Value * , <NUM_LIT> > Objs ;"
LLVM,NVPTX,823,"Predict the next statement of this code snippet:
 <s> if ( auto * A = dyn_cast < const Argument > ( V ) ) return IsKernelFn && A -> onlyReadsMemory ( ) && A -> hasNoAliasAttr ( ) ;"
LLVM,NVPTX,824,"Predict the next statement of this code snippet:
 <s> } if ( ! Src ) return false ; if ( auto * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) return ( PT -> getAddressSpace ( ) == spN ) ; return false ;"
LLVM,NVPTX,825,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;"
LLVM,NVPTX,826,"Predict the next statement of this code snippet:
 <s> if ( ! Src ) return <STR_LIT> :: GENERIC ; if ( auto * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) { switch ( PT -> getAddressSpace ( ) ) { case llvm :: ADDRESS_SPACE_LOCAL : return <STR_LIT> :: LOCAL ; case llvm :: ADDRESS_SPACE_GLOBAL : return <STR_LIT> :: GLOBAL ; case llvm :: ADDRESS_SPACE_SHARED : return <STR_LIT> :: SHARED ; case llvm :: ADDRESS_SPACE_GENERIC : return <STR_LIT> :: GENERIC ;"
LLVM,NVPTX,827,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : switch ( DestTy . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : switch ( DestTy . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : switch ( DestTy . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :"
LLVM,NVPTX,828,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : switch ( DestTy . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : switch ( DestTy . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : switch ( DestTy . SimpleTy ) {"
LLVM,NVPTX,829,"Predict the next statement of this code snippet:
 <s> int <ISA_LIT>DAGToDAGISel :: getDivF32Level ( ) const {"
LLVM,NVPTX,830,"Predict the next statement of this code snippet:
 <s> inline SDValue getI32Imm ( unsigned Imm , SDLoc DL ) { return CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ;"
LLVM,NVPTX,831,"Predict the next statement of this code snippet:
 <s> inline SDValue getI32Imm ( unsigned Imm , SDLoc DL ) {"
LLVM,NVPTX,832,"Predict the next statement of this code snippet:
 <s> const char * getPassName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,833,"Predict the next statement of this code snippet:
 <s> const char * getPassName ( ) const override {"
LLVM,NVPTX,834,"Predict the next statement of this code snippet:
 <s> return CmpMode :: EQ ; case <STR_LIT> : return CmpMode :: GT ; case <STR_LIT> : return CmpMode :: GE ; case <STR_LIT> : return CmpMode :: LT ; case <STR_LIT> : return CmpMode :: LE ; case <STR_LIT> : return CmpMode :: NE ; case <STR_LIT> : return CmpMode :: NUM ; case <STR_LIT> : return CmpMode :: NotANumber ; case <STR_LIT> : return CmpMode :: EQU ; case <STR_LIT> : return CmpMode :: GTU ; case <STR_LIT> : return CmpMode :: GEU ; case <STR_LIT> : return CmpMode :: LTU ; case <STR_LIT> : return CmpMode :: LEU ; case <STR_LIT> : return CmpMode :: NEU ; case <STR_LIT> : return CmpMode :: EQ ; case <STR_LIT> : return CmpMode :: GT ; case <STR_LIT> : return CmpMode :: GE ; case <STR_LIT> : return CmpMode :: LT ;"
LLVM,NVPTX,835,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>DAGToDAGISel :: <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) , TM ( tm ) {"
LLVM,NVPTX,836,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ;"
LLVM,NVPTX,837,"Predict the next statement of this code snippet:
 <s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;"
LLVM,NVPTX,838,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRri ( SDNode * OpNode , SDValue Addr , SDValue & Base , SDValue & Offset ) {"
LLVM,NVPTX,839,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRri64 ( SDNode * OpNode , SDValue Addr , SDValue & Base , SDValue & Offset ) {"
LLVM,NVPTX,840,"Predict the next statement of this code snippet:
 <s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( SelectDirectAddr ( Addr . getOperand ( <NUM_LIT> ) , Addr ) ) { return false ; } if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , mvt ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( OpNode ) , mvt ) ; return true ;"
LLVM,NVPTX,841,"Predict the next statement of this code snippet:
 <s> return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( SelectDirectAddr ( Addr . getOperand ( <NUM_LIT> ) , Addr ) ) { return false ; } if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) {"
LLVM,NVPTX,842,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRsi64 ( SDNode * OpNode , SDValue Addr , SDValue & Base , SDValue & Offset ) {"
LLVM,NVPTX,843,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRsi_imp ( SDNode * OpNode , SDValue Addr , SDValue & Base , SDValue & Offset , MVT mvt ) { if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { SDValue base = Addr . getOperand ( <NUM_LIT> ) ; if ( SelectDirectAddr ( base , Base ) ) { Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( OpNode ) , mvt ) ; return true ; } } } return false ;"
LLVM,NVPTX,844,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRsi_imp ( SDNode * OpNode , SDValue Addr , SDValue & Base , SDValue & Offset , MVT mvt ) { if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { SDValue base = Addr . getOperand ( <NUM_LIT> ) ; if ( SelectDirectAddr ( base , Base ) ) { Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( OpNode ) , mvt ) ; return true ; } } } return false ;"
LLVM,NVPTX,845,"Predict the next statement of this code snippet:
 <s> case ADDRESS_SPACE_SHARED : Opc = TM . is64Bit ( ) ? ( useShortPointers ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : Opc = TM . is64Bit ( ) ? ( useShortPointers ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; break ; case ADDRESS_SPACE_LOCAL : Opc = TM . is64Bit ( ) ? ( useShortPointers ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; break ; } ReplaceNode ( N , CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Src ) ) ; return ; } else { if ( SrcAddrSpace != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; unsigned Opc ; switch ( DstAddrSpace ) { default : report_fatal_error ( <STR_LIT> ) ; case ADDRESS_SPACE_GLOBAL : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED :"
LLVM,NVPTX,846,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectDirectAddr ( SDValue N , SDValue & Address ) { if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { Address = N ; return true ; }"
LLVM,NVPTX,847,"Predict the next statement of this code snippet:
 <s> if ( SelectDirectAddr ( Op , Op0 ) ) { OutOps . push_back ( Op0 ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ) ; return false ; }"
LLVM,NVPTX,848,"Predict the next statement of this code snippet:
 <s> OutOps . push_back ( Op0 ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ) ; return false ; } if ( SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ) {"
LLVM,NVPTX,849,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( N ) ;"
LLVM,NVPTX,850,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: SelectTexSurfHandle ( SDNode * N ) {"
LLVM,NVPTX,851,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>DAGToDAGISel :: SelectTexSurfHandle ( SDNode * N ) {"
LLVM,NVPTX,852,"Predict the next statement of this code snippet:
 <s> if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return false ;"
LLVM,NVPTX,853,"Predict the next statement of this code snippet:
 <s> SDNode * LoadConstF16 = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Val ) ; ReplaceNode ( N , LoadConstF16 ) ;"
LLVM,NVPTX,854,"Predict the next statement of this code snippet:
 <s> SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; if ( Vector . getSimpleValueType ( ) != <STR_LIT> ) return false ; SmallVector < SDNode * , <NUM_LIT> > E0 , E1 ; for ( auto U : Vector . getNode ( ) -> uses ( ) ) { if ( U -> getOpcode ( ) != <STR_LIT> ) continue ; if ( U -> getOperand ( <NUM_LIT> ) != Vector ) continue ; if ( const ConstantSDNode * IdxConst = dyn_cast < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) ) { if ( IdxConst -> getZExtValue ( ) == <NUM_LIT> ) E0 . push_back ( U ) ; else if ( IdxConst -> getZExtValue ( ) == <NUM_LIT> ) E1 . push_back ( U ) ; else llvm_unreachable ( <STR_LIT> ) ; } } if ( E0 . empty ( ) || E1 . empty ( ) ) return false ; unsigned Op = <STR_LIT> ; SDValue Source = Vector ; if ( Vector -> getOpcode ( ) == <STR_LIT> ) { Op = <STR_LIT> ; Source = Vector -> getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,855,"Predict the next statement of this code snippet:
 <s> switch ( IID ) { default : return false ; case <STR_LIT> : SelectTexSurfHandle ( N ) ;"
LLVM,NVPTX,856,"Predict the next statement of this code snippet:
 <s> } else if ( PointerSize == <NUM_LIT> ? SelectADDRsi64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRsi ( N1 . getNode ( ) , N1 , Base , Offset ) ) { Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRri64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRri ( N1 . getNode ( ) , N1 , Base , Offset ) ) { if ( PointerSize == <NUM_LIT> ) Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } else { if ( PointerSize == <NUM_LIT> ) Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , N1 , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } if ( ! <ISA_LIT>LD ) return false ; MachineMemOperand * MemRef = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( <ISA_LIT>LD ) , { MemRef } ) ; ReplaceNode ( N , <ISA_LIT>LD ) ;"
LLVM,NVPTX,857,"Predict the next statement of this code snippet:
 <s> switch ( Node -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : VecSize = <NUM_LIT> ; break ; case <STR_LIT> : VecSize = <NUM_LIT> ; break ; case <STR_LIT> : VecSize = <NUM_LIT> ; break ; } EVT EltVT = Node -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Mem -> getMemoryVT ( ) ; Optional < unsigned > Opcode ; switch ( VecSize ) { default : return false ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( MemVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( MemVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( MemVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } if ( ! Opcode ) return false ; SDVTList VTs ; if ( VecSize == <NUM_LIT> ) {"
LLVM,NVPTX,858,"Predict the next statement of this code snippet:
 <s> SDValue Value = PlainStore ? PlainStore -> getValue ( ) : AtomicStore -> getVal ( ) ; SDValue BasePtr = ST -> getBasePtr ( ) ; SDValue Addr ; SDValue Offset , Base ; Optional < unsigned > Opcode ; <STR_LIT> SourceVT = Value . getNode ( ) -> getSimpleValueType ( <NUM_LIT> ) . SimpleTy ; if ( SelectDirectAddr ( BasePtr , Addr ) ) { Opcode = pickOpcodeForVT ( SourceVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { Value , getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( toType , dl ) , getI32Imm ( toTypeWidth , dl ) , Addr , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , <STR_LIT> , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRsi64 ( BasePtr . getNode ( ) , BasePtr , Base , Offset ) : SelectADDRsi ( BasePtr . getNode ( ) , BasePtr , Base , Offset ) ) { Opcode = pickOpcodeForVT ( SourceVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { Value , getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( toType , dl ) , getI32Imm ( toTypeWidth , dl ) , Base , Offset , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , <STR_LIT> , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRri64 ( BasePtr . getNode ( ) , BasePtr , Base , Offset ) : SelectADDRri ( BasePtr . getNode ( ) , BasePtr , Base , Offset ) ) { if ( PointerSize == <NUM_LIT> ) Opcode = pickOpcodeForVT ( SourceVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Opcode = pickOpcodeForVT ( SourceVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ;"
LLVM,NVPTX,859,"Predict the next statement of this code snippet:
 <s> if ( ! Opcode ) return false ; break ; case <STR_LIT> : { Opcode = <STR_LIT> ; SDValue CvtNone = CurDAG -> getTargetConstant ( <STR_LIT> :: NONE , DL , <STR_LIT> ) ; SDNode * Cvt = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , CvtNone ) ; Ops [ <NUM_LIT> ] = SDValue ( Cvt , <NUM_LIT> ) ; break ; } case <STR_LIT> : { Opcode = <STR_LIT> ; SDValue CvtNone = CurDAG -> getTargetConstant ( <STR_LIT> :: NONE , DL , <STR_LIT> ) ; SDNode * Cvt = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , CvtNone ) ; Ops [ <NUM_LIT> ] = SDValue ( Cvt , <NUM_LIT> ) ; break ; } } SDVTList RetVTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; SDNode * Ret = CurDAG -> getMachineNode ( Opcode . getValue ( ) , DL , RetVTs , Ops ) ; MachineMemOperand * MemRef = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Ret ) , { MemRef } ) ;"
LLVM,NVPTX,860,"Predict the next statement of this code snippet:
 <s> return Subtarget -> getTargetLowering ( ) -> useF32FTZ ( * MF ) ;"
LLVM,NVPTX,861,"Predict the next statement of this code snippet:
 <s> return Subtarget -> getTargetLowering ( ) -> usePrecSqrtF32 ( ) ;"
LLVM,NVPTX,862,"Predict the next statement of this code snippet:
 <s> return TM . useShortPointers ( ) ;"
LLVM,NVPTX,863,"Predict the next statement of this code snippet:
 <s> if ( ! Src ) return false ; if ( const PointerType * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) return ( PT -> getAddressSpace ( ) == spN ) ; return false ;"
LLVM,NVPTX,864,"Predict the next statement of this code snippet:
 <s> Src = mN -> getSrcValue ( ) ; } else if ( MemSDNode * mN = dyn_cast < MemIntrinsicSDNode > ( N ) ) { Src = mN -> getSrcValue ( ) ; }"
LLVM,NVPTX,865,"Predict the next statement of this code snippet:
 <s> case llvm :: ADDRESS_SPACE_LOCAL : return <STR_LIT> :: LOCAL ; case llvm :: ADDRESS_SPACE_GLOBAL : return <STR_LIT> :: GLOBAL ; case llvm :: ADDRESS_SPACE_SHARED : return <STR_LIT> :: SHARED ; case llvm :: ADDRESS_SPACE_GENERIC : return <STR_LIT> :: GENERIC ; case llvm :: ADDRESS_SPACE_PARAM : return <STR_LIT> :: PARAM ; case llvm :: ADDRESS_SPACE_CONST : return <STR_LIT> :: CONSTANT ; default : break ; }"
LLVM,NVPTX,866,"Predict the next statement of this code snippet:
 <s> const Value * Src = N -> getSrcValue ( ) ; if ( ! Src ) return <STR_LIT> :: GENERIC ; if ( const PointerType * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) { switch ( PT -> getAddressSpace ( ) ) { case llvm :: ADDRESS_SPACE_LOCAL : return <STR_LIT> :: LOCAL ; case llvm :: ADDRESS_SPACE_GLOBAL : return <STR_LIT> :: GLOBAL ; case llvm :: ADDRESS_SPACE_SHARED : return <STR_LIT> :: SHARED ; case llvm :: ADDRESS_SPACE_GENERIC : return <STR_LIT> :: GENERIC ; case llvm :: ADDRESS_SPACE_PARAM : return <STR_LIT> :: PARAM ; case llvm :: ADDRESS_SPACE_CONST : return <STR_LIT> :: CONSTANT ; default : break ; } } return <STR_LIT> :: GENERIC ;"
LLVM,NVPTX,867,"Predict the next statement of this code snippet:
 <s> doFMAF64AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF64 ( ) && ( FMAContractLevel == <NUM_LIT> ) ; allowFMA = ( FMAContractLevel >= <NUM_LIT> ) || UseFMADInstruction ; UseF32FTZ = false ; doMulWide = ( OptLevel > <NUM_LIT> ) ; do_DIVF32_PREC = UsePrecDivF32 ; do_SQRTF32_PREC = UsePrecSqrtF32 ;"
LLVM,NVPTX,868,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : ResNode = SelectLoadVector ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ResNode = SelectLDGLDUVector ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : ResNode = SelectStoreVector ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ResNode = SelectLoadParam ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ResNode = SelectStoreRetval ( N ) ; break ;"
LLVM,NVPTX,869,"Predict the next statement of this code snippet:
 <s> return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( SelectDirectAddr ( Addr . getOperand ( <NUM_LIT> ) , Addr ) ) { return false ; } if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , mvt ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , mvt ) ; return true ; }"
LLVM,NVPTX,870,"Predict the next statement of this code snippet:
 <s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , mvt ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , mvt ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) {"
LLVM,NVPTX,871,"Predict the next statement of this code snippet:
 <s> SDValue base = Addr . getOperand ( <NUM_LIT> ) ; if ( SelectDirectAddr ( base , Base ) ) {"
LLVM,NVPTX,872,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( SelectDirectAddr ( Op , Op0 ) ) { OutOps . push_back ( Op0 ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return false ; } if ( SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ) { OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } break ; } return true ;"
LLVM,NVPTX,873,"Predict the next statement of this code snippet:
 <s> Opcode = <STR_LIT> ; break ; default : return NULL ; } SDValue Ops [ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode , dl , TargetVT , <STR_LIT> , Ops ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRri64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRri ( N1 . getNode ( ) , N1 , Base , Offset ) ) { if ( Subtarget . is64Bit ( ) ) { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } } else { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } } SDValue Ops [ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode , dl , TargetVT , <STR_LIT> , Ops ) ; } else { if ( Subtarget . is64Bit ( ) ) { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } } else { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;"
LLVM,NVPTX,874,"Predict the next statement of this code snippet:
 <s> return NULL ; case <STR_LIT> : NumElts = <NUM_LIT> ; break ; case <STR_LIT> : NumElts = <NUM_LIT> ; break ; case <STR_LIT> : NumElts = <NUM_LIT> ; break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( N -> getOperand ( i + <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( OffsetVal , <STR_LIT> ) ) ; Ops . push_back ( Chain ) ; unsigned Opcode = <NUM_LIT> ; switch ( NumElts ) { default : return NULL ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;"
LLVM,NVPTX,875,"Predict the next statement of this code snippet:
 <s> return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;"
LLVM,NVPTX,876,"Predict the next statement of this code snippet:
 <s> if ( ! isKernelFunction ( * F -> getFunction ( ) ) ) return false ; SmallVector < Value * , <NUM_LIT> > Objs ; GetUnderlyingObjects ( const_cast < Value * > ( N -> getMemOperand ( ) -> getValue ( ) ) , Objs , F -> getDataLayout ( ) ) ; for ( Value * Obj : Objs ) { auto * A = dyn_cast < const Argument > ( Obj ) ; if ( ! A || ! A -> onlyReadsMemory ( ) || ! A -> hasNoAliasAttr ( ) ) return false ;"
LLVM,NVPTX,877,"Predict the next statement of this code snippet:
 <s> return false ; case <STR_LIT> : SelectTexSurfHandle ( N ) ; return true ; case <STR_LIT> : case <STR_LIT> : SelectMatchAll ( N ) ; return true ; }"
LLVM,NVPTX,878,"Predict the next statement of this code snippet:
 <s> if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( codeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } else if ( TM . is64Bit ( ) ? SelectADDRri64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRri ( N1 . getNode ( ) , N1 , Base , Offset ) ) { if ( TM . is64Bit ( ) ) Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( codeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } else { if ( TM . is64Bit ( ) ) Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( codeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , N1 , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } if ( ! <ISA_LIT>LD ) return false ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( <ISA_LIT>LD ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; ReplaceNode ( N , <ISA_LIT>LD ) ; return true ;"
LLVM,NVPTX,879,"Predict the next statement of this code snippet:
 <s> return false ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( IsVolatile , DL ) , getI32Imm ( CodeAddrSpace , DL ) , getI32Imm ( VecType , DL ) , getI32Imm ( FromType , DL ) , getI32Imm ( FromTypeWidth , DL ) , Base , Offset , Chain } ; LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , DL , N -> getVTList ( ) , Ops ) ; } else if ( TM . is64Bit ( ) ? SelectADDRri64 ( Op1 . getNode ( ) , Op1 , Base , Offset ) : SelectADDRri ( Op1 . getNode ( ) , Op1 , Base , Offset ) ) { if ( TM . is64Bit ( ) ) { switch ( N -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } } else { switch ( N -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } } if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( IsVolatile , DL ) , getI32Imm ( CodeAddrSpace , DL ) , getI32Imm ( VecType , DL ) , getI32Imm ( FromType , DL ) , getI32Imm ( FromTypeWidth , DL ) , Base , Offset , Chain } ; LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , DL , N -> getVTList ( ) , Ops ) ; } else { if ( TM . is64Bit ( ) ) { switch ( N -> getOpcode ( ) ) { default : return false ; case <STR_LIT> :"
LLVM,NVPTX,880,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( N -> getOperand ( i + <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( ParamVal , DL , <STR_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( OffsetVal , DL , <STR_LIT> ) ) ; Ops . push_back ( Chain ) ; Ops . push_back ( Flag ) ; Optional < unsigned > Opcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : switch ( NumElts ) { default : return false ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } if ( ! Opcode ) return false ; break ; case <STR_LIT> : { Opcode = <STR_LIT> ; SDValue CvtNone = CurDAG -> getTargetConstant ( <STR_LIT> :: NONE , DL , <STR_LIT> ) ; SDNode * Cvt = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , CvtNone ) ; Ops [ <NUM_LIT> ] = SDValue ( Cvt , <NUM_LIT> ) ; break ; } case <STR_LIT> : { Opcode = <STR_LIT> ; SDValue CvtNone = CurDAG -> getTargetConstant ( <STR_LIT> :: NONE , DL , <STR_LIT> ) ; SDNode * Cvt = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , CvtNone ) ;"
LLVM,NVPTX,881,"Predict the next statement of this code snippet:
 <s> break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( N -> getOperand ( i + <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( ParamVal , DL , <STR_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( OffsetVal , DL , <STR_LIT> ) ) ; Ops . push_back ( Chain ) ; Ops . push_back ( Flag ) ; Optional < unsigned > Opcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : switch ( NumElts ) { default : return false ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } if ( ! Opcode ) return false ; break ; case <STR_LIT> : { Opcode = <STR_LIT> ; SDValue CvtNone = CurDAG -> getTargetConstant ( <STR_LIT> :: NONE , DL , <STR_LIT> ) ; SDNode * Cvt = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , CvtNone ) ; Ops [ <NUM_LIT> ] = SDValue ( Cvt , <NUM_LIT> ) ; break ; } case <STR_LIT> : { Opcode = <STR_LIT> ; SDValue CvtNone = CurDAG -> getTargetConstant ( <STR_LIT> :: NONE , DL , <STR_LIT> ) ; SDNode * Cvt = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , CvtNone ) ;"
LLVM,NVPTX,882,"Predict the next statement of this code snippet:
 <s> return false ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( IsVolatile , DL ) , getI32Imm ( CodeAddrSpace , DL ) , getI32Imm ( VecType , DL ) , getI32Imm ( FromType , DL ) , getI32Imm ( FromTypeWidth , DL ) , Addr , Chain } ; LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , DL , N -> getVTList ( ) , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRsi64 ( Op1 . getNode ( ) , Op1 , Base , Offset ) : SelectADDRsi ( Op1 . getNode ( ) , Op1 , Base , Offset ) ) { switch ( N -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( IsVolatile , DL ) , getI32Imm ( CodeAddrSpace , DL ) , getI32Imm ( VecType , DL ) , getI32Imm ( FromType , DL ) , getI32Imm ( FromTypeWidth , DL ) , Base , Offset , Chain } ; LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , DL , N -> getVTList ( ) , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRri64 ( Op1 . getNode ( ) , Op1 , Base , Offset ) : SelectADDRri ( Op1 . getNode ( ) , Op1 , Base , Offset ) ) { if ( PointerSize == <NUM_LIT> ) { switch ( N -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } } else { switch ( N -> getOpcode ( ) ) {"
LLVM,NVPTX,883,"Predict the next statement of this code snippet:
 <s> } unsigned int PointerSize = CurDAG -> getDataLayout ( ) . getPointerSizeInBits ( MemSD -> getAddressSpace ( ) ) ; bool IsVolatile = MemSD -> isVolatile ( ) ; if ( CodeAddrSpace != <STR_LIT> :: GLOBAL && CodeAddrSpace != <STR_LIT> :: SHARED && CodeAddrSpace != <STR_LIT> :: GENERIC ) IsVolatile = false ; MVT SimpleVT = LoadedVT . getSimpleVT ( ) ; MVT ScalarVT = SimpleVT . getScalarType ( ) ; unsigned FromTypeWidth = std :: max ( <NUM_LIT> , ScalarVT . getSizeInBits ( ) ) ; unsigned int FromType ; unsigned ExtensionType = cast < ConstantSDNode > ( N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ExtensionType == <STR_LIT> ) FromType = <STR_LIT> :: Signed ; else if ( ScalarVT . isFloatingPoint ( ) ) FromType = ScalarVT . SimpleTy == <STR_LIT> ? <STR_LIT> :: Untyped : <STR_LIT> :: Float ; else FromType = <STR_LIT> :: Unsigned ; unsigned VecType ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : VecType = <STR_LIT> :: V2 ; break ; case <STR_LIT> : VecType = <STR_LIT> :: V4 ; break ; default : return false ; } EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; if ( EltVT == <STR_LIT> ) { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EltVT = <STR_LIT> ; FromType = <STR_LIT> :: Untyped ; FromTypeWidth = <NUM_LIT> ; } if ( SelectDirectAddr ( Op1 , Addr ) ) { switch ( N -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( IsVolatile , DL ) , getI32Imm ( CodeAddrSpace , DL ) , getI32Imm ( VecType , DL ) , getI32Imm ( FromType , DL ) , getI32Imm ( FromTypeWidth , DL ) , Addr , Chain } ; LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , DL , N -> getVTList ( ) , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRsi64 ( Op1 . getNode ( ) , Op1 , Base , Offset ) : SelectADDRsi ( Op1 . getNode ( ) , Op1 , Base , Offset ) ) { switch ( N -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ;"
LLVM,NVPTX,884,"Predict the next statement of this code snippet:
 <s> if ( ! Opcode ) return false ; SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( toType , dl ) , getI32Imm ( toTypeWidth , dl ) , Addr , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , <STR_LIT> , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRsi64 ( N2 . getNode ( ) , N2 , Base , Offset ) : SelectADDRsi ( N2 . getNode ( ) , N2 , Base , Offset ) ) { Opcode = pickOpcodeForVT ( SourceVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( toType , dl ) , getI32Imm ( toTypeWidth , dl ) , Base , Offset , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , <STR_LIT> , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRri64 ( N2 . getNode ( ) , N2 , Base , Offset ) : SelectADDRri ( N2 . getNode ( ) , N2 , Base , Offset ) ) { if ( PointerSize == <NUM_LIT> ) Opcode = pickOpcodeForVT ( SourceVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Opcode = pickOpcodeForVT ( SourceVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,885,"Predict the next statement of this code snippet:
 <s> } else { if ( TM . Options . UnsafeFPMath ) return <NUM_LIT> ; else return <NUM_LIT> ; }"
LLVM,NVPTX,886,"Predict the next statement of this code snippet:
 <s> doFMAF32AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF32 ( ) && ( FMAContractLevel == <NUM_LIT> ) ; doFMAF64AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF64 ( ) && ( FMAContractLevel == <NUM_LIT> ) ; allowFMA = ( FMAContractLevel >= <NUM_LIT> ) ; doMulWide = ( OptLevel > <NUM_LIT> ) ;"
LLVM,NVPTX,887,"Predict the next statement of this code snippet:
 <s> doFMAF32AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF32 ( ) && ( FMAContractLevel == <NUM_LIT> ) ; doFMAF64AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF64 ( ) && ( FMAContractLevel == <NUM_LIT> ) ;"
LLVM,NVPTX,888,"Predict the next statement of this code snippet:
 <s> } SDNode * ResNode = NULL ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : ResNode = SelectLoad ( N ) ; break ; case <STR_LIT> : ResNode = SelectStore ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : ResNode = SelectLoadVector ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ResNode = SelectLDGLDUVector ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : ResNode = SelectStoreVector ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ResNode = SelectLoadParam ( N ) ; break ; case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,889,"Predict the next statement of this code snippet:
 <s> } EVT EltVT = Node -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Mem -> getMemoryVT ( ) ; unsigned Opc = <NUM_LIT> ; switch ( VecSize ) { default : return NULL ; case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> :"
LLVM,NVPTX,890,"Predict the next statement of this code snippet:
 <s> if ( F -> hasFnAttribute ( <STR_LIT> ) ) return ( F -> getAttributes ( ) . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) ; else return false ; }"
LLVM,NVPTX,891,"Predict the next statement of this code snippet:
 <s> const Function * F = MF -> getFunction ( ) ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) return ( F -> getAttributes ( ) . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) ;"
LLVM,NVPTX,892,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: usePrecSqrtF32 ( ) const { if ( UsePrecSqrtF32 . getNumOccurrences ( ) > <NUM_LIT> ) { return UsePrecSqrtF32 ; } else { if ( TM . Options . UnsafeFPMath ) return false ; else return true ;"
LLVM,NVPTX,893,"Predict the next statement of this code snippet:
 <s> if ( ! Src ) return false ; if ( const PointerType * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) return ( PT -> getAddressSpace ( ) == spN ) ;"
LLVM,NVPTX,894,"Predict the next statement of this code snippet:
 <s> switch ( PT -> getAddressSpace ( ) ) { case llvm :: ADDRESS_SPACE_LOCAL : return <STR_LIT> :: LOCAL ; case llvm :: ADDRESS_SPACE_GLOBAL : return <STR_LIT> :: GLOBAL ; case llvm :: ADDRESS_SPACE_SHARED : return <STR_LIT> :: SHARED ; case llvm :: ADDRESS_SPACE_GENERIC : return <STR_LIT> :: GENERIC ; case llvm :: ADDRESS_SPACE_PARAM : return <STR_LIT> :: PARAM ; case llvm :: ADDRESS_SPACE_CONST : return <STR_LIT> :: CONSTANT ; default : break ; }"
LLVM,NVPTX,895,"Predict the next statement of this code snippet:
 <s> NumZeros = countTrailingZeros ( MaskVal ) ; unsigned NumOnes = countTrailingOnes ( MaskVal >> NumZeros ) ; NumBits = NumZeros + NumOnes - ShiftAmt ; } else { return NULL ; } if ( ShiftAmt < NumZeros ) { return NULL ; } Val = AndLHS ; Start = CurDAG -> getTargetConstant ( ShiftAmt , <STR_LIT> ) ; Len = CurDAG -> getTargetConstant ( NumBits , <STR_LIT> ) ; } else if ( LHS -> getOpcode ( ) == <STR_LIT> ) { Val = LHS -> getOperand ( <NUM_LIT> ) ; SDValue ShlRHS = LHS -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ShlCnst = dyn_cast < ConstantSDNode > ( ShlRHS ) ; if ( ! ShlCnst ) { return NULL ; } uint64_t InnerShiftAmt = ShlCnst -> getZExtValue ( ) ; SDValue ShrRHS = RHS ; ConstantSDNode * ShrCnst = dyn_cast < ConstantSDNode > ( ShrRHS ) ; if ( ! ShrCnst ) { return NULL ; } uint64_t OuterShiftAmt = ShrCnst -> getZExtValue ( ) ; if ( OuterShiftAmt < InnerShiftAmt ) { return NULL ; } if ( OuterShiftAmt >= Val . getValueType ( ) . getSizeInBits ( ) ) { return NULL ; } Start = CurDAG -> getTargetConstant ( OuterShiftAmt - InnerShiftAmt , <STR_LIT> ) ; Len = CurDAG -> getTargetConstant ( Val . getValueType ( ) . getSizeInBits ( ) - OuterShiftAmt , <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) { IsSigned = true ; } } else { return NULL ; }"
LLVM,NVPTX,896,"Predict the next statement of this code snippet:
 <s> if ( ! ShiftCnst ) { return NULL ; } uint64_t ShiftAmt = ShiftCnst -> getZExtValue ( ) ; SDValue AndLHS = LHS -> getOperand ( <NUM_LIT> ) ; SDValue AndRHS = LHS -> getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( AndLHS ) ) { std :: swap ( AndLHS , AndRHS ) ; } ConstantSDNode * MaskCnst = dyn_cast < ConstantSDNode > ( AndRHS ) ; if ( ! MaskCnst ) { return NULL ; } uint64_t MaskVal = MaskCnst -> getZExtValue ( ) ; uint64_t NumZeros ; uint64_t NumBits ; if ( isMask_64 ( MaskVal ) ) { NumZeros = <NUM_LIT> ; NumBits = countTrailingOnes ( MaskVal ) - ShiftAmt ; } else if ( isShiftedMask_64 ( MaskVal ) ) { NumZeros = countTrailingZeros ( MaskVal ) ; unsigned NumOnes = countTrailingOnes ( MaskVal >> NumZeros ) ; NumBits = NumZeros + NumOnes - ShiftAmt ; } else { return NULL ; } if ( ShiftAmt < NumZeros ) { return NULL ; } Val = AndLHS ; Start = CurDAG -> getTargetConstant ( ShiftAmt , <STR_LIT> ) ; Len = CurDAG -> getTargetConstant ( NumBits , <STR_LIT> ) ; } else if ( LHS -> getOpcode ( ) == <STR_LIT> ) { Val = LHS -> getOperand ( <NUM_LIT> ) ; SDValue ShlRHS = LHS -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ShlCnst = dyn_cast < ConstantSDNode > ( ShlRHS ) ; if ( ! ShlCnst ) { return NULL ; } uint64_t InnerShiftAmt = ShlCnst -> getZExtValue ( ) ; SDValue ShrRHS = RHS ; ConstantSDNode * ShrCnst = dyn_cast < ConstantSDNode > ( ShrRHS ) ; if ( ! ShrCnst ) { return NULL ; } uint64_t OuterShiftAmt = ShrCnst -> getZExtValue ( ) ; if ( OuterShiftAmt < InnerShiftAmt ) { return NULL ; } if ( OuterShiftAmt >= Val . getValueType ( ) . getSizeInBits ( ) ) { return NULL ; } Start = CurDAG -> getTargetConstant ( OuterShiftAmt - InnerShiftAmt , <STR_LIT> ) ; Len = CurDAG -> getTargetConstant ( Val . getValueType ( ) . getSizeInBits ( ) - OuterShiftAmt , <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) { IsSigned = true ; } } else { return NULL ; } } else { return NULL ;"
LLVM,NVPTX,897,"Predict the next statement of this code snippet:
 <s> OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return false ; } if ( SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ) { OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } break ;"
LLVM,NVPTX,898,"Predict the next statement of this code snippet:
 <s> unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IID ) { default : return nullptr ; case <STR_LIT> :"
LLVM,NVPTX,899,"Predict the next statement of this code snippet:
 <s> Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ;"
LLVM,NVPTX,900,"Predict the next statement of this code snippet:
 <s> Ops . push_back ( Chain ) ; Ops . push_back ( Flag ) ; unsigned Opcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : switch ( NumElts ) { default : return nullptr ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;"
LLVM,NVPTX,901,"Predict the next statement of this code snippet:
 <s> default : return nullptr ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> :"
LLVM,NVPTX,902,"Predict the next statement of this code snippet:
 <s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectTexSurfHandle ( SDNode * N ) { SDValue Wrapper = N -> getOperand ( <NUM_LIT> ) ; SDValue GlobalVal = Wrapper . getOperand ( <NUM_LIT> ) ; return CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , GlobalVal ) ;"
LLVM,NVPTX,903,"Predict the next statement of this code snippet:
 <s> return CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , GlobalVal ) ;"
LLVM,NVPTX,904,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: useF32FTZ ( ) const { if ( FtzEnabled . getNumOccurrences ( ) > <NUM_LIT> ) { return FtzEnabled ; } else { const Function * F = MF -> getFunction ( ) ;"
LLVM,NVPTX,905,"Predict the next statement of this code snippet:
 <s> } else { const Function * F = MF -> getFunction ( ) ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) return F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; else return false ; }"
LLVM,NVPTX,906,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: usePrecSqrtF32 ( ) const { if ( UsePrecSqrtF32 . getNumOccurrences ( ) > <NUM_LIT> ) {"
LLVM,NVPTX,907,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: allowFMA ( ) const {"
LLVM,NVPTX,908,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetLowering * TL = ( <ISA_LIT>TargetLowering * ) getTargetLowering ( ) ;"
LLVM,NVPTX,909,"Predict the next statement of this code snippet:
 <s> Src = mN -> getMemOperand ( ) -> getValue ( ) ; } else if ( MemSDNode * mN = dyn_cast < MemIntrinsicSDNode > ( N ) ) { if ( spN == <NUM_LIT> && mN -> getMemOperand ( ) -> getPseudoValue ( ) ) return true ;"
LLVM,NVPTX,910,"Predict the next statement of this code snippet:
 <s> case llvm :: ADDRESS_SPACE_SHARED : return <STR_LIT> :: SHARED ; case llvm :: ADDRESS_SPACE_GENERIC : return <STR_LIT> :: GENERIC ; case llvm :: ADDRESS_SPACE_PARAM : return <STR_LIT> :: PARAM ; case llvm :: ADDRESS_SPACE_CONST : return <STR_LIT> :: CONSTANT ; default : break ; } } return <STR_LIT> :: GENERIC ;"
LLVM,NVPTX,911,"Predict the next statement of this code snippet:
 <s> static unsigned int getCodeAddrSpace ( MemSDNode * N , const <ISA_LIT>Subtarget & Subtarget ) { const Value * Src = N -> getMemOperand ( ) -> getValue ( ) ; if ( ! Src ) return <STR_LIT> :: GENERIC ; if ( const PointerType * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) { switch ( PT -> getAddressSpace ( ) ) { case llvm :: ADDRESS_SPACE_LOCAL : return <STR_LIT> :: LOCAL ;"
LLVM,NVPTX,912,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>DAGToDAGISel :: <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) , Subtarget ( tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ) { doMulWide = ( OptLevel > <NUM_LIT> ) ;"
LLVM,NVPTX,913,"Predict the next statement of this code snippet:
 <s> case ADDRESS_SPACE_LOCAL : Opc = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; } return CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Src ) ; } else { if ( SrcAddrSpace != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; unsigned Opc ; switch ( DstAddrSpace ) { default : report_fatal_error ( <STR_LIT> ) ; case ADDRESS_SPACE_GLOBAL : Opc = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : Opc = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : Opc = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_LOCAL : Opc = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; }"
LLVM,NVPTX,914,"Predict the next statement of this code snippet:
 <s> ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! Mask ) { return NULL ; } uint64_t MaskVal = Mask -> getZExtValue ( ) ; if ( ! isMask_64 ( MaskVal ) ) { return NULL ; } uint64_t NumBits = CountTrailingOnes_64 ( MaskVal ) ; Len = CurDAG -> getTargetConstant ( NumBits , <STR_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) { Val = LHS . getNode ( ) -> getOperand ( <NUM_LIT> ) ; Start = LHS . getNode ( ) -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * StartConst = dyn_cast < ConstantSDNode > ( Start ) ; if ( StartConst ) { uint64_t StartVal = StartConst -> getZExtValue ( ) ; uint64_t GoodBits = Start . getValueType ( ) . getSizeInBits ( ) - StartVal ; if ( NumBits > GoodBits ) { return NULL ; } Start = CurDAG -> getTargetConstant ( StartVal , <STR_LIT> ) ; } else { return NULL ; } } else { return NULL ; } } else if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) { if ( LHS -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * ShiftCnst = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! ShiftCnst ) { return NULL ; } uint64_t ShiftAmt = ShiftCnst -> getZExtValue ( ) ; SDValue AndLHS = LHS -> getOperand ( <NUM_LIT> ) ; SDValue AndRHS = LHS -> getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( AndLHS ) ) { std :: swap ( AndLHS , AndRHS ) ; }"
LLVM,NVPTX,915,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( toType ) , getI32Imm ( toTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRri64 ( N2 . getNode ( ) , N2 , Base , Offset ) : SelectADDRri ( N2 . getNode ( ) , N2 , Base , Offset ) ) { if ( Subtarget . is64Bit ( ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } } else { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } } SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( toType ) , getI32Imm ( toTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; } else { if ( Subtarget . is64Bit ( ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } } else { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;"
LLVM,NVPTX,916,"Predict the next statement of this code snippet:
 <s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; SDValue Addr ; SDValue Offset , Base ; unsigned Opcode ; <STR_LIT> SourceVT = N1 . getNode ( ) -> getSimpleValueType ( <NUM_LIT> ) . SimpleTy ; if ( SelectDirectAddr ( N2 , Addr ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( toType ) , getI32Imm ( toTypeWidth ) , Addr , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRsi64 ( N2 . getNode ( ) , N2 , Base , Offset ) : SelectADDRsi ( N2 . getNode ( ) , N2 , Base , Offset ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( toType ) , getI32Imm ( toTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRri64 ( N2 . getNode ( ) , N2 , Base , Offset ) : SelectADDRri ( N2 . getNode ( ) , N2 , Base , Offset ) ) { if ( Subtarget . is64Bit ( ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } } else { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;"
LLVM,NVPTX,917,"Predict the next statement of this code snippet:
 <s> ResNode = SelectLoad ( N ) ; break ; case <STR_LIT> : ResNode = SelectStore ( N ) ; break ; } if ( ResNode ) return ResNode ;"
LLVM,NVPTX,918,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } SDValue Ops [ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode , dl , TargetVT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRri64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRri ( N1 . getNode ( ) , N1 , Base , Offset ) ) { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } SDValue Ops [ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode , dl , TargetVT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;"
LLVM,NVPTX,919,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: ChkMemSDNodeAddressSpace ( SDNode * N , unsigned int spN ) const { const Value * Src = NULL ; if ( MemSDNode * mN = dyn_cast < MemSDNode > ( N ) ) { Src = mN -> getSrcValue ( ) ; } else if ( MemSDNode * mN = dyn_cast < MemIntrinsicSDNode > ( N ) ) { Src = mN -> getSrcValue ( ) ; }"
LLVM,NVPTX,920,"Predict the next statement of this code snippet:
 <s> static unsigned int getCodeAddrSpace ( MemSDNode * N , const <ISA_LIT>Subtarget & Subtarget ) { const Value * Src = N -> getSrcValue ( ) ; if ( ! Src ) return <STR_LIT> :: LOCAL ; if ( const PointerType * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) { switch ( PT -> getAddressSpace ( ) ) {"
LLVM,NVPTX,921,"Predict the next statement of this code snippet:
 <s> doFMAF32AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF32 ( ) && ( FMAContractLevel == <NUM_LIT> ) ; doFMAF64AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF64 ( ) && ( FMAContractLevel == <NUM_LIT> ) ; allowFMA = ( FMAContractLevel >= <NUM_LIT> ) || UseFMADInstruction ;"
LLVM,NVPTX,922,"Predict the next statement of this code snippet:
 <s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : ResNode = SelectLoad ( N ) ; break ; case <STR_LIT> : ResNode = SelectStore ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : ResNode = SelectLoadVector ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ResNode = SelectLDGLDUVector ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : ResNode = SelectStoreVector ( N ) ; break ; default : break ; } if ( ResNode ) return ResNode ;"
LLVM,NVPTX,923,"Predict the next statement of this code snippet:
 <s> } if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , mvt ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , mvt ) ; return true ; } }"
LLVM,NVPTX,924,"Predict the next statement of this code snippet:
 <s> return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( SelectDirectAddr ( Addr . getOperand ( <NUM_LIT> ) , Addr ) ) { return false ; }"
LLVM,NVPTX,925,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRsi_imp ( SDNode * OpNode , SDValue Addr , SDValue & Base , SDValue & Offset , MVT mvt ) { if ( Addr . getOpcode ( ) == <STR_LIT> ) {"
LLVM,NVPTX,926,"Predict the next statement of this code snippet:
 <s> if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { SDValue base = Addr . getOperand ( <NUM_LIT> ) ; if ( SelectDirectAddr ( base , Base ) ) { Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , mvt ) ; return true ; } } } return false ;"
LLVM,NVPTX,927,"Predict the next statement of this code snippet:
 <s> unsigned IID = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IID == <STR_LIT> ) if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ( SelectDirectAddr ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Address ) ) ;"
LLVM,NVPTX,928,"Predict the next statement of this code snippet:
 <s> OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return false ; } if ( SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ) { OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ;"
LLVM,NVPTX,929,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: UndefOrImm ( SDValue Op , SDValue N , SDValue & Retval ) { if ( ! ( N . getOpcode ( ) == <STR_LIT> ) && ! ( N . getOpcode ( ) == <STR_LIT> ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> ) Retval = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; else {"
LLVM,NVPTX,930,"Predict the next statement of this code snippet:
 <s> case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ;"
LLVM,NVPTX,931,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;"
LLVM,NVPTX,932,"Predict the next statement of this code snippet:
 <s> const Value * Src = N -> getSrcValue ( ) ; if ( ! Src ) return <STR_LIT> :: LOCAL ; if ( const PointerType * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) { switch ( PT -> getAddressSpace ( ) ) {"
LLVM,NVPTX,933,"Predict the next statement of this code snippet:
 <s> if ( ! Src ) return <STR_LIT> :: LOCAL ; if ( const PointerType * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) { switch ( PT -> getAddressSpace ( ) ) { case llvm :: ADDRESS_SPACE_LOCAL : return <STR_LIT> :: LOCAL ; case llvm :: ADDRESS_SPACE_GLOBAL : return <STR_LIT> :: GLOBAL ; case llvm :: ADDRESS_SPACE_SHARED : return <STR_LIT> :: SHARED ; case llvm :: ADDRESS_SPACE_CONST_NOT_GEN : return <STR_LIT> :: CONSTANT ; case llvm :: ADDRESS_SPACE_GENERIC : return <STR_LIT> :: GENERIC ; case llvm :: ADDRESS_SPACE_PARAM :"
LLVM,NVPTX,934,"Predict the next statement of this code snippet:
 <s> ResNode = SelectStore ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : ResNode = SelectLoadVector ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ResNode = SelectLDGLDUVector ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : ResNode = SelectStoreVector ( N ) ; break ; default :"
LLVM,NVPTX,935,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; } } else { switch ( N -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;"
LLVM,NVPTX,936,"Predict the next statement of this code snippet:
 <s> return NULL ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; } } SDValue Ops [ ] = { Op1 , Chain } ; LD = CurDAG -> getMachineNode ( Opcode , DL , N -> getVTList ( ) , Ops ) ;"
LLVM,NVPTX,937,"Predict the next statement of this code snippet:
 <s> else fromType = <STR_LIT> :: Unsigned ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Addr ; SDValue Offset , Base ; unsigned Opcode ; <STR_LIT> TargetVT = LD -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) . SimpleTy ; if ( SelectDirectAddr ( N1 , Addr ) ) { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } SDValue Ops [ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Addr , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode , dl , TargetVT , <STR_LIT> , Ops ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRsi64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRsi ( N1 . getNode ( ) , N1 , Base , Offset ) ) { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } SDValue Ops [ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode , dl , TargetVT , <STR_LIT> , Ops ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRri64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRri ( N1 . getNode ( ) , N1 , Base , Offset ) ) { if ( Subtarget . is64Bit ( ) ) { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;"
LLVM,NVPTX,938,"Predict the next statement of this code snippet:
 <s> switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( toType ) , getI32Imm ( toTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRri64 ( N2 . getNode ( ) , N2 , Base , Offset ) : SelectADDRri ( N2 . getNode ( ) , N2 , Base , Offset ) ) { if ( Subtarget . is64Bit ( ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } } else { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } } SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( toType ) , getI32Imm ( toTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; } else { if ( Subtarget . is64Bit ( ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;"
LLVM,NVPTX,939,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>DAGToDAGISel :: <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) {"
LLVM,NVPTX,940,"Predict the next statement of this code snippet:
 <s> case ADDRESS_SPACE_SHARED : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_LOCAL : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; } return CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Src ) ; } else { if ( SrcAddrSpace != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; unsigned Opc ; switch ( DstAddrSpace ) { default : report_fatal_error ( <STR_LIT> ) ; case ADDRESS_SPACE_GLOBAL : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_LOCAL :"
LLVM,NVPTX,941,"Predict the next statement of this code snippet:
 <s> default : report_fatal_error ( <STR_LIT> ) ; case ADDRESS_SPACE_GLOBAL : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_LOCAL : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; } return CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Src ) ; } else { if ( SrcAddrSpace != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ;"
LLVM,NVPTX,942,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } SDValue Ops [ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode , dl , TargetVT , <STR_LIT> , Ops ) ; } else if ( Subtarget -> is64Bit ( ) ? SelectADDRri64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRri ( N1 . getNode ( ) , N1 , Base , Offset ) ) { if ( Subtarget -> is64Bit ( ) ) { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } } else { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } } SDValue Ops [ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode , dl , TargetVT , <STR_LIT> , Ops ) ; } else { if ( Subtarget -> is64Bit ( ) ) { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ;"
LLVM,NVPTX,943,"Predict the next statement of this code snippet:
 <s> StoreSDNode * ST = cast < StoreSDNode > ( N ) ; EVT StoreVT = ST -> getMemoryVT ( ) ; SDNode * <ISA_LIT>ST = nullptr ; if ( ST -> isIndexed ( ) ) return nullptr ; if ( ! StoreVT . isSimple ( ) ) return nullptr ; unsigned int codeAddrSpace = getCodeAddrSpace ( ST ) ; bool isVolatile = ST -> isVolatile ( ) ; if ( codeAddrSpace != <STR_LIT> :: GLOBAL && codeAddrSpace != <STR_LIT> :: SHARED && codeAddrSpace != <STR_LIT> :: GENERIC ) isVolatile = false ; MVT SimpleVT = StoreVT . getSimpleVT ( ) ; unsigned vecType = <STR_LIT> :: Scalar ; if ( SimpleVT . isVector ( ) ) { unsigned num = SimpleVT . getVectorNumElements ( ) ; if ( num == <NUM_LIT> ) vecType = <STR_LIT> :: V2 ; else if ( num == <NUM_LIT> ) vecType = <STR_LIT> :: V4 ; else return nullptr ; } MVT ScalarVT = SimpleVT . getScalarType ( ) ; unsigned toTypeWidth = ScalarVT . getSizeInBits ( ) ; unsigned int toType ; if ( ScalarVT . isFloatingPoint ( ) ) toType = <STR_LIT> :: Float ; else toType = <STR_LIT> :: Unsigned ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; SDValue Addr ; SDValue Offset , Base ; unsigned Opcode ; <STR_LIT> SourceVT = N1 . getNode ( ) -> getSimpleValueType ( <NUM_LIT> ) . SimpleTy ; if ( SelectDirectAddr ( N2 , Addr ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( toType ) , getI32Imm ( toTypeWidth ) , Addr , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; } else if ( Subtarget -> is64Bit ( ) ? SelectADDRsi64 ( N2 . getNode ( ) , N2 , Base , Offset ) : SelectADDRsi ( N2 . getNode ( ) , N2 , Base , Offset ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ;"
LLVM,NVPTX,944,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : ResNode = SelectIntrinsicNoChain ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ResNode = SelectTextureIntrinsic ( N ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,945,"Predict the next statement of this code snippet:
 <s> Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Ops . push_back ( TexRef ) ; Ops . push_back ( SampRef ) ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } Ops . push_back ( Chain ) ;"
LLVM,NVPTX,946,"Predict the next statement of this code snippet:
 <s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectAddrSpaceCast ( SDNode * N ) { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; AddrSpaceCastSDNode * CastN = cast < AddrSpaceCastSDNode > ( N ) ; unsigned SrcAddrSpace = CastN -> getSrcAddressSpace ( ) ; unsigned DstAddrSpace = CastN -> getDestAddressSpace ( ) ; assert ( SrcAddrSpace != DstAddrSpace && <STR_LIT> ) ; if ( DstAddrSpace == ADDRESS_SPACE_GENERIC ) { unsigned Opc ; switch ( SrcAddrSpace ) { default : report_fatal_error ( <STR_LIT> ) ; case ADDRESS_SPACE_GLOBAL : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_LOCAL : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; } return CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Src ) ; } else { if ( SrcAddrSpace != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; unsigned Opc ; switch ( DstAddrSpace ) { default : report_fatal_error ( <STR_LIT> ) ; case ADDRESS_SPACE_GLOBAL : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ;"
LLVM,NVPTX,947,"Predict the next statement of this code snippet:
 <s> break ; case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } break ; } SDVTList VTs ; if ( VecSize == <NUM_LIT> ) { VTs = CurDAG -> getVTList ( EltVT , <STR_LIT> , <STR_LIT> ) ; } else if ( VecSize == <NUM_LIT> ) { VTs = CurDAG -> getVTList ( EltVT , EltVT , <STR_LIT> , <STR_LIT> ) ; } else {"
LLVM,NVPTX,948,"Predict the next statement of this code snippet:
 <s> MemSDNode * Mem = cast < MemSDNode > ( Node ) ; unsigned VecSize ; switch ( Node -> getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : VecSize = <NUM_LIT> ; break ; case <STR_LIT> : VecSize = <NUM_LIT> ; break ; case <STR_LIT> : VecSize = <NUM_LIT> ; break ; } EVT EltVT = Node -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Mem -> getMemoryVT ( ) ; unsigned Opc = <NUM_LIT> ; switch ( VecSize ) { default : return nullptr ; case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } break ;"
LLVM,NVPTX,949,"Predict the next statement of this code snippet:
 <s> if ( Stride ) { if ( Variant == WMMA_VARIANT_ARI64 ) Variant = WMMA_VARIANT_ARI64_STRIDE ; else if ( Variant == WMMA_VARIANT_AVAR ) Variant = WMMA_VARIANT_AVAR_STRIDE ; }"
LLVM,NVPTX,950,"Predict the next statement of this code snippet:
 <s> SDValue ValueOp = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * ValueConst = dyn_cast < ConstantSDNode > ( ValueOp ) ) { OpcodeIndex |= HAS_CONST_VALUE ; ValueOp = CurDAG -> getTargetConstant ( ValueConst -> getZExtValue ( ) , DL , ValueConst -> getValueType ( <NUM_LIT> ) ) ; } if ( ConstantSDNode * MaskConst = dyn_cast < ConstantSDNode > ( MaskOp ) ) { OpcodeIndex |= HAS_CONST_MASK ; MaskOp = CurDAG -> getTargetConstant ( MaskConst -> getZExtValue ( ) , DL , MaskConst -> getValueType ( <NUM_LIT> ) ) ; } unsigned Opcodes [ <NUM_LIT> ] = {"
LLVM,NVPTX,951,"Predict the next statement of this code snippet:
 <s> enum { IS_I64 = <NUM_LIT> , HAS_CONST_VALUE = <NUM_LIT> , HAS_CONST_MASK = <NUM_LIT> } ; unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned OpcodeIndex = ( IID == <STR_LIT> ) ? IS_I64 : <NUM_LIT> ; SDValue MaskOp = N -> getOperand ( <NUM_LIT> ) ; SDValue ValueOp = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * ValueConst = dyn_cast < ConstantSDNode > ( ValueOp ) ) {"
LLVM,NVPTX,952,"Predict the next statement of this code snippet:
 <s> SelectMatchAll ( N ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryLDGLDU ( N ) ;"
LLVM,NVPTX,953,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>DAGToDAGISel :: tryIntrinsicChain ( SDNode * N ) { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( getWmmaLdStOpcode ( IID ) ) return tryWMMA_LDST ( N ) ; switch ( IID ) {"
LLVM,NVPTX,954,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,955,"Predict the next statement of this code snippet:
 <s> Variant = WMMA_VARIANT_AVAR ; Ops . push_back ( Addr ) ; } else if ( SelectADDRsi64 ( Op1 . getNode ( ) , Op1 , Base , Offset ) || SelectADDRri64 ( Op1 . getNode ( ) , Op1 , Base , Offset ) ) { Variant = WMMA_VARIANT_ARI64 ; Ops . push_back ( Base ) ; Ops . push_back ( Offset ) ; } else { Variant = WMMA_VARIANT_AVAR ; Ops . push_back ( Op1 ) ; } unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ; Ops . push_back ( Chain ) ; Opcode = getWmmaLdStOpcode ( IID , Variant ) ; if ( ! Opcode ) { llvm :: errs ( ) << <STR_LIT> ; return false ;"
LLVM,NVPTX,956,"Predict the next statement of this code snippet:
 <s> if ( N -> isInvariant ( ) ) return true ; if ( ! isKernelFunction ( F -> getFunction ( ) ) ) return false ; SmallVector < Value * , <NUM_LIT> > Objs ; GetUnderlyingObjects ( const_cast < Value * > ( N -> getMemOperand ( ) -> getValue ( ) ) , Objs , F -> getDataLayout ( ) ) ; for ( Value * Obj : Objs ) { auto * A = dyn_cast < const Argument > ( Obj ) ; if ( ! A || ! A -> onlyReadsMemory ( ) || ! A -> hasNoAliasAttr ( ) ) return false ; }"
LLVM,NVPTX,957,"Predict the next statement of this code snippet:
 <s> static bool canLowerToLDG ( MemSDNode * N , const <ISA_LIT>Subtarget & Subtarget , unsigned CodeAddrSpace , MachineFunction * F ) { if ( ! Subtarget . hasLDG ( ) || CodeAddrSpace != <STR_LIT> :: GLOBAL ) return false ; if ( N -> isInvariant ( ) ) return true ; if ( ! isKernelFunction ( F -> getFunction ( ) ) ) return false ; SmallVector < Value * , <NUM_LIT> > Objs ; GetUnderlyingObjects ( const_cast < Value * > ( N -> getMemOperand ( ) -> getValue ( ) ) , Objs , F -> getDataLayout ( ) ) ; for ( Value * Obj : Objs ) { auto * A = dyn_cast < const Argument > ( Obj ) ; if ( ! A || ! A -> onlyReadsMemory ( ) || ! A -> hasNoAliasAttr ( ) ) return false ; } return true ;"
LLVM,NVPTX,958,"Predict the next statement of this code snippet:
 <s> SmallVector < Value * , <NUM_LIT> > Objs ; GetUnderlyingObjects ( const_cast < Value * > ( N -> getMemOperand ( ) -> getValue ( ) ) , Objs , F -> getDataLayout ( ) ) ;"
LLVM,NVPTX,959,"Predict the next statement of this code snippet:
 <s> for ( Value * Obj : Objs ) { auto * A = dyn_cast < const Argument > ( Obj ) ; if ( ! A || ! A -> onlyReadsMemory ( ) || ! A -> hasNoAliasAttr ( ) ) return false ; } return true ;"
LLVM,NVPTX,960,"Predict the next statement of this code snippet:
 <s> } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( N -> getOperand ( i + <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( ParamVal , DL , <STR_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( OffsetVal , DL , <STR_LIT> ) ) ; Ops . push_back ( Chain ) ; Ops . push_back ( Flag ) ; unsigned Opcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : switch ( NumElts ) { default : return false ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ;"
LLVM,NVPTX,961,"Predict the next statement of this code snippet:
 <s> } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( N -> getOperand ( i + <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( OffsetVal , DL , <STR_LIT> ) ) ; Ops . push_back ( Chain ) ; unsigned Opcode = <NUM_LIT> ; switch ( NumElts ) { default : return false ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;"
LLVM,NVPTX,962,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetLowering * TL = Subtarget . getTargetLowering ( ) ; return TL -> allowFMA ( * MF , OptLevel ) ;"
LLVM,NVPTX,963,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; } } else { switch ( N -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;"
LLVM,NVPTX,964,"Predict the next statement of this code snippet:
 <s> if ( ! Subtarget . hasLDG ( ) || CodeAddrSpace != <STR_LIT> :: GLOBAL ) return false ; if ( N -> isInvariant ( ) ) return true ; bool IsKernelFn = isKernelFunction ( F -> getFunction ( ) ) ; SmallVector < Value * , <NUM_LIT> > Objs ; GetUnderlyingObjects ( const_cast < Value * > ( N -> getMemOperand ( ) -> getValue ( ) ) , Objs , F -> getDataLayout ( ) ) ; return all_of ( Objs , [ & ] ( Value * V ) { if ( auto * A = dyn_cast < const Argument > ( V ) ) return IsKernelFn && A -> onlyReadsMemory ( ) && A -> hasNoAliasAttr ( ) ; if ( auto * GV = dyn_cast < const GlobalVariable > ( V ) ) return GV -> isConstant ( ) ;"
LLVM,NVPTX,965,"Predict the next statement of this code snippet:
 <s> static bool canLowerToLDG ( MemSDNode * N , const <ISA_LIT>Subtarget & Subtarget , unsigned CodeAddrSpace , MachineFunction * F ) { if ( ! Subtarget . hasLDG ( ) || CodeAddrSpace != <STR_LIT> :: GLOBAL ) return false ; if ( N -> isInvariant ( ) ) return true ; bool IsKernelFn = isKernelFunction ( F -> getFunction ( ) ) ; SmallVector < Value * , <NUM_LIT> > Objs ; GetUnderlyingObjects ( const_cast < Value * > ( N -> getMemOperand ( ) -> getValue ( ) ) , Objs , F -> getDataLayout ( ) ) ;"
LLVM,NVPTX,966,"Predict the next statement of this code snippet:
 <s> inline SDValue getI32Imm ( unsigned Imm ) {"
LLVM,NVPTX,967,"Predict the next statement of this code snippet:
 <s> inline SDValue getI32Imm ( unsigned Imm ) {"
LLVM,NVPTX,968,"Predict the next statement of this code snippet:
 <s> SDValue Addr ; SDValue Offset , Base ; Optional < unsigned > Opcode ; <STR_LIT> TargetVT = LD -> getSimpleValueType ( <NUM_LIT> ) . SimpleTy ; if ( SelectDirectAddr ( N1 , Addr ) ) { Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , Addr , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRsi64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRsi ( N1 . getNode ( ) , N1 , Base , Offset ) ) { Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRri64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRri ( N1 . getNode ( ) , N1 , Base , Offset ) ) {"
LLVM,NVPTX,969,"Predict the next statement of this code snippet:
 <s> if ( OptLevel == <NUM_LIT> ) return false ;"
LLVM,NVPTX,970,"Predict the next statement of this code snippet:
 <s> if ( OptLevel == <NUM_LIT> ) return false ; if ( MF . getTarget ( ) . Options . AllowFPOpFusion == FPOpFusion :: Fast ) return true ; return allowUnsafeFPMath ( MF ) ;"
LLVM,NVPTX,971,"Predict the next statement of this code snippet:
 <s> Attribute Attr = F -> getFnAttribute ( <STR_LIT> ) ; StringRef Val = Attr . getValueAsString ( ) ; if ( Val == <STR_LIT> ) return true ; }"
LLVM,NVPTX,972,"Predict the next statement of this code snippet:
 <s> unsigned NumElts = AccessSize / EltSize ; if ( AccessSize != EltSize * NumElts ) return <NUM_LIT> ; if ( Idx + NumElts > ValueVTs . size ( ) ) return <NUM_LIT> ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return <NUM_LIT> ;"
LLVM,NVPTX,973,"Predict the next statement of this code snippet:
 <s> if ( VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> && NumElts % <NUM_LIT> == <NUM_LIT> ) { EltVT = <STR_LIT> ; NumElts /= <NUM_LIT> ; } for ( unsigned j = <NUM_LIT> ; j != NumElts ; ++ j ) {"
LLVM,NVPTX,974,"Predict the next statement of this code snippet:
 <s> if ( VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> && NumElts % <NUM_LIT> == <NUM_LIT> ) { EltVT = <STR_LIT> ; NumElts /= <NUM_LIT> ; } for ( unsigned j = <NUM_LIT> ; j != NumElts ; ++ j ) { ValueVTs . push_back ( EltVT ) ; if ( Offsets ) Offsets -> push_back ( Off + j * EltVT . getStoreSize ( ) ) ; } } else { ValueVTs . push_back ( VT ) ; if ( Offsets ) Offsets -> push_back ( Off ) ; }"
LLVM,NVPTX,975,"Predict the next statement of this code snippet:
 <s> if ( ! DirectCallee ) { const Instruction * CalleeI = CS -> getInstruction ( ) ; assert ( CalleeI && <STR_LIT> ) ; if ( isa < CallInst > ( CalleeI ) ) { if ( getAlign ( * cast < CallInst > ( CalleeI ) , Idx , Align ) ) return Align ;"
LLVM,NVPTX,976,"Predict the next statement of this code snippet:
 <s> while ( isa < ConstantExpr > ( CalleeV ) ) { const ConstantExpr * CE = cast < ConstantExpr > ( CalleeV ) ; if ( ! CE -> isCast ( ) ) break ; CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ; } if ( isa < Function > ( CalleeV ) ) DirectCallee = CalleeV ; } }"
LLVM,NVPTX,977,"Predict the next statement of this code snippet:
 <s> return UsePrecDivF32 ; } else { if ( getTargetMachine ( ) . Options . UnsafeFPMath ) return <NUM_LIT> ; else return <NUM_LIT> ;"
LLVM,NVPTX,978,"Predict the next statement of this code snippet:
 <s> return UsePrecDivF32 ; } else { if ( getTargetMachine ( ) . Options . UnsafeFPMath ) return <NUM_LIT> ;"
LLVM,NVPTX,979,"Predict the next statement of this code snippet:
 <s> if ( VT == <STR_LIT> ) return TypeLegal ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;"
LLVM,NVPTX,980,"Predict the next statement of this code snippet:
 <s> if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getScalarType ( ) == <STR_LIT> ) return TypeSplitVector ; if ( VT == <STR_LIT> ) return TypeLegal ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;"
LLVM,NVPTX,981,"Predict the next statement of this code snippet:
 <s> if ( ! ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && ! usePrecSqrtF32 ( ) ) ) ) return SDValue ( ) ; if ( ExtraSteps == ReciprocalEstimate :: Unspecified ) ExtraSteps = <NUM_LIT> ; SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; bool Ftz = useF32FTZ ( DAG . getMachineFunction ( ) ) ;"
LLVM,NVPTX,982,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; bool Ftz = useF32FTZ ( DAG . getMachineFunction ( ) ) ; auto MakeIntrinsicCall = [ & ] ( <STR_LIT> IID ) { return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( IID , DL , <STR_LIT> ) , Operand ) ; } ; if ( Reciprocal || ExtraSteps > <NUM_LIT> ) {"
LLVM,NVPTX,983,"Predict the next statement of this code snippet:
 <s> static bool isImageOrSamplerVal ( const Value * arg , const Module * context ) { static const char * const specialTypes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Type * Ty = arg -> getType ( ) ; auto * PTy = dyn_cast < PointerType > ( Ty ) ; if ( ! PTy ) return false ; if ( ! context ) return false ;"
LLVM,NVPTX,984,"Predict the next statement of this code snippet:
 <s> auto * PTy = dyn_cast < PointerType > ( Ty ) ; if ( ! PTy ) return false ; if ( ! context ) return false ; auto * STy = dyn_cast < StructType > ( PTy -> getElementType ( ) ) ; if ( ! STy || STy -> isLiteral ( ) ) return false ;"
LLVM,NVPTX,985,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,986,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,987,"Predict the next statement of this code snippet:
 <s> if ( ! ( Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> && isa < ConstantFPSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) && isa < ConstantFPSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) ) return Op ;"
LLVM,NVPTX,988,"Predict the next statement of this code snippet:
 <s> APInt E1 = cast < ConstantFPSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getValueAPF ( ) . bitcastToAPInt ( ) ; SDValue Const = DAG . getConstant ( E1 . zext ( <NUM_LIT> ) . shl ( <NUM_LIT> ) | E0 . zext ( <NUM_LIT> ) , SDLoc ( Op ) , <STR_LIT> ) ;"
LLVM,NVPTX,989,"Predict the next statement of this code snippet:
 <s> SDNode * Node = Op . getNode ( ) ; SDLoc dl ( Node ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumOperands = Node -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { SDValue SubOp = Node -> getOperand ( i ) ; EVT VVT = SubOp . getNode ( ) -> getValueType ( <NUM_LIT> ) ; EVT EltVT = VVT . getVectorElementType ( ) ; unsigned NumSubElem = VVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumSubElem ; ++ j ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SubOp , DAG . getIntPtrConstant ( j , dl ) ) ) ; } }"
LLVM,NVPTX,990,"Predict the next statement of this code snippet:
 <s> if ( isa < ConstantSDNode > ( Index . getNode ( ) ) ) return Op ; SDValue Vector = Op -> getOperand ( <NUM_LIT> ) ; EVT VectorVT = Vector . getValueType ( ) ; assert ( VectorVT == <STR_LIT> && <STR_LIT> ) ; EVT EltVT = VectorVT . getVectorElementType ( ) ; SDLoc dl ( Op . getNode ( ) ) ; SDValue E0 = DAG . getNode ( <STR_LIT> , dl , EltVT , Vector , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue E1 = DAG . getNode ( <STR_LIT> , dl , EltVT , Vector , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getSelectCC ( dl , Index , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) , E0 , E1 , <STR_LIT> :: SETEQ ) ;"
LLVM,NVPTX,991,"Predict the next statement of this code snippet:
 <s> int VecIdx = - <NUM_LIT> ; for ( unsigned parti = <NUM_LIT> , parte = VTs . size ( ) ; parti != parte ; ++ parti ) { if ( VectorInfo [ parti ] & PVF_FIRST ) { assert ( VecIdx == - <NUM_LIT> && <STR_LIT> ) ; VecIdx = parti ; } if ( VectorInfo [ parti ] & PVF_LAST ) { unsigned NumElts = parti - VecIdx + <NUM_LIT> ; EVT EltVT = VTs [ parti ] ; EVT LoadVT = EltVT ; if ( EltVT == <STR_LIT> ) LoadVT = <STR_LIT> ; else if ( EltVT == <STR_LIT> ) LoadVT = <STR_LIT> ; EVT VecVT = EVT :: getVectorVT ( F -> getContext ( ) , LoadVT , NumElts ) ; SDValue VecAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Arg , DAG . getConstant ( Offsets [ VecIdx ] , dl , PtrVT ) ) ; Value * srcValue = Constant :: getNullValue ( PointerType :: get ( EltVT . getTypeForEVT ( F -> getContext ( ) ) , ADDRESS_SPACE_PARAM ) ) ; SDValue P = DAG . getLoad ( VecVT , dl , Root , VecAddr , MachinePointerInfo ( srcValue ) , aggregateIsPacked , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; if ( P . getNode ( ) ) P . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; ++ j ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , LoadVT , P , DAG . getIntPtrConstant ( j , dl ) ) ; if ( EltVT == <STR_LIT> ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt ) ; else if ( EltVT == <STR_LIT> ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt ) ; if ( Ins [ InsIdx ] . VT . isInteger ( ) && Ins [ InsIdx ] . VT . getSizeInBits ( ) > LoadVT . getSizeInBits ( ) ) { unsigned Extend = Ins [ InsIdx ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> ; Elt = DAG . getNode ( Extend , dl , Ins [ InsIdx ] . VT , Elt ) ; } InVals . push_back ( Elt ) ; } VecIdx = - <NUM_LIT> ; } ++ InsIdx ;"
LLVM,NVPTX,992,"Predict the next statement of this code snippet:
 <s> LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT MemVT = Load -> getMemoryVT ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , Load -> getAddressSpace ( ) , Load -> getAlignment ( ) ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( Op ) ) ; } } return SDValue ( ) ;"
LLVM,NVPTX,993,"Predict the next statement of this code snippet:
 <s> LoadSDNode * LD = cast < LoadSDNode > ( Node ) ; SDLoc dl ( Node ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ;"
LLVM,NVPTX,994,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return Op ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerSelect ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,NVPTX,995,"Predict the next statement of this code snippet:
 <s> Type * RetTy = MF . getFunction ( ) -> getReturnType ( ) ; bool isABI = ( STI . getSmVersion ( ) >= <NUM_LIT> ) ; assert ( isABI && <STR_LIT> ) ; if ( ! isABI ) return Chain ; const DataLayout DL = DAG . getDataLayout ( ) ; SmallVector < EVT , <NUM_LIT> > VTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputePTXValueVTs ( * this , DL , RetTy , VTs , & Offsets ) ; assert ( VTs . size ( ) == OutVals . size ( ) && <STR_LIT> ) ; auto VectorInfo = VectorizePTXValueVTs ( VTs , Offsets , RetTy -> isSized ( ) ? DL . getABITypeAlignment ( RetTy ) : <NUM_LIT> ) ; bool ExtendIntegerRetVal = RetTy -> isIntegerTy ( ) && DL . getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > StoreOperands ; for ( unsigned i = <NUM_LIT> , e = VTs . size ( ) ; i != e ; ++ i ) { if ( VectorInfo [ i ] & PVF_FIRST ) { assert ( StoreOperands . empty ( ) && <STR_LIT> ) ; StoreOperands . push_back ( Chain ) ; StoreOperands . push_back ( DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) ) ; } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size ( ) - <NUM_LIT> ; switch ( NumElts ) { case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,996,"Predict the next statement of this code snippet:
 <s> if ( VT == <STR_LIT> ) return LowerSTOREi1 ( Op , DAG ) ; if ( VT == <STR_LIT> && ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , Store -> getAddressSpace ( ) , Store -> getAlignment ( ) ) ) return expandUnalignedStore ( Store , DAG ) ; if ( VT . isVector ( ) ) return LowerSTOREVector ( Op , DAG ) ; return SDValue ( ) ;"
LLVM,NVPTX,997,"Predict the next statement of this code snippet:
 <s> SDValue Tmp2 = ST -> getBasePtr ( ) ; SDValue Tmp3 = ST -> getValue ( ) ; assert ( Tmp3 . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ;"
LLVM,NVPTX,998,"Predict the next statement of this code snippet:
 <s> switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } MemSDNode * MemSD = cast < MemSDNode > ( N ) ; const DataLayout & TD = DAG . getDataLayout ( ) ; unsigned Align = MemSD -> getAlignment ( ) ; unsigned PrefAlign = TD . getPrefTypeAlignment ( ValVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return SDValue ( ) ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; bool StoreF16x2 = false ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : assert ( EltVT == <STR_LIT> && <STR_LIT> ) ; Opcode = <STR_LIT> ; StoreF16x2 = true ; break ; }"
LLVM,NVPTX,999,"Predict the next statement of this code snippet:
 <s> unsigned Align = MemSD -> getAlignment ( ) ; unsigned PrefAlign = TD . getPrefTypeAlignment ( ValVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return SDValue ( ) ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; bool StoreF16x2 = false ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : assert ( EltVT == <STR_LIT> && <STR_LIT> ) ; Opcode = <STR_LIT> ; StoreF16x2 = true ; break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; if ( StoreF16x2 ) { NumElts /= <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue E0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getIntPtrConstant ( i * <NUM_LIT> , DL ) ) ; SDValue E1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getIntPtrConstant ( i * <NUM_LIT> + <NUM_LIT> , DL ) ) ;"
LLVM,NVPTX,1000,"Predict the next statement of this code snippet:
 <s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,1001,"Predict the next statement of this code snippet:
 <s> if ( SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget , OptLevel ) ) return Result ;"
LLVM,NVPTX,1002,"Predict the next statement of this code snippet:
 <s> } if ( Val -> isMachineOpcode ( ) && Val -> getMachineOpcode ( ) == <STR_LIT> ) { Val = Val -> getOperand ( <NUM_LIT> ) ; } if ( Val -> getOpcode ( ) == <STR_LIT> || Val -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * MaskCnst = dyn_cast < ConstantSDNode > ( Mask ) ; if ( ! MaskCnst ) { return SDValue ( ) ; } uint64_t MaskVal = MaskCnst -> getZExtValue ( ) ; if ( MaskVal != <NUM_LIT> ) { return SDValue ( ) ; } MemSDNode * Mem = dyn_cast < MemSDNode > ( Val ) ; if ( ! Mem ) { return SDValue ( ) ; } EVT MemVT = Mem -> getMemoryVT ( ) ; if ( MemVT != <STR_LIT> && MemVT != <STR_LIT> ) { return SDValue ( ) ; } unsigned ExtType = cast < ConstantSDNode > ( Val -> getOperand ( Val -> getNumOperands ( ) - <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ExtType == <STR_LIT> ) { return SDValue ( ) ; } bool AddTo = false ; if ( AExt . getNode ( ) != nullptr ) { Val = DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , AExt . getValueType ( ) , Val ) ;"
LLVM,NVPTX,1003,"Predict the next statement of this code snippet:
 <s> MemSDNode * Mem = dyn_cast < MemSDNode > ( Val ) ; if ( ! Mem ) { return SDValue ( ) ; } EVT MemVT = Mem -> getMemoryVT ( ) ; if ( MemVT != <STR_LIT> && MemVT != <STR_LIT> ) { return SDValue ( ) ; } unsigned ExtType = cast < ConstantSDNode > ( Val -> getOperand ( Val -> getNumOperands ( ) - <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ExtType == <STR_LIT> ) { return SDValue ( ) ; } bool AddTo = false ;"
LLVM,NVPTX,1004,"Predict the next statement of this code snippet:
 <s> default : break ; case <STR_LIT> : case <STR_LIT> : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformSHLCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformREMCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DCI ) ;"
LLVM,NVPTX,1005,"Predict the next statement of this code snippet:
 <s> if ( SDValue Ret = TryMULWIDECombine ( N , DCI ) ) return Ret ;"
LLVM,NVPTX,1006,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool IsSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned DivOpc = IsSigned ? <STR_LIT> : <STR_LIT> ; const SDValue & Num = N -> getOperand ( <NUM_LIT> ) ; const SDValue & Den = N -> getOperand ( <NUM_LIT> ) ; for ( const SDNode * U : Num -> uses ( ) ) { if ( U -> getOpcode ( ) == DivOpc && U -> getOperand ( <NUM_LIT> ) == Num && U -> getOperand ( <NUM_LIT> ) == Den ) { return DAG . getNode ( <STR_LIT> , DL , VT , Num , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( DivOpc , DL , VT , Num , Den ) , Den ) ) ; }"
LLVM,NVPTX,1007,"Predict the next statement of this code snippet:
 <s> unsigned DivOpc = IsSigned ? <STR_LIT> : <STR_LIT> ; const SDValue & Num = N -> getOperand ( <NUM_LIT> ) ; const SDValue & Den = N -> getOperand ( <NUM_LIT> ) ; for ( const SDNode * U : Num -> uses ( ) ) {"
LLVM,NVPTX,1008,"Predict the next statement of this code snippet:
 <s> SDValue B = N -> getOperand ( <NUM_LIT> ) ; if ( CCType != <STR_LIT> || A . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ;"
LLVM,NVPTX,1009,"Predict the next statement of this code snippet:
 <s> static SDValue PerformSHLCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , CodeGenOpt :: Level OptLevel ) { if ( OptLevel > <NUM_LIT> ) { if ( SDValue Ret = TryMULWIDECombine ( N , DCI ) ) return Ret ; } return SDValue ( ) ;"
LLVM,NVPTX,1010,"Predict the next statement of this code snippet:
 <s> MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ; } SDValue LoadChain = NewLD . getValue ( NumElts ) ; SDValue BuildVec = DAG . getBuildVector ( ResVT , DL , ScalarRes ) ; Results . push_back ( BuildVec ) ; Results . push_back ( LoadChain ) ; } else { assert ( ResVT . isSimple ( ) && ResVT . getSimpleVT ( ) . SimpleTy == <STR_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( N -> op_begin ( ) , N -> op_end ( ) ) ; SDVTList LdResVTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ;"
LLVM,NVPTX,1011,"Predict the next statement of this code snippet:
 <s> bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; bool LoadF16x2 = false ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } case <NUM_LIT> : { assert ( EltVT == <STR_LIT> && <STR_LIT> ) ; LoadF16x2 = true ; Opcode = <STR_LIT> ; EVT ListVTs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) , DL ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ;"
LLVM,NVPTX,1012,"Predict the next statement of this code snippet:
 <s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { return getDataSection ( ) ;"
LLVM,NVPTX,1013,"Predict the next statement of this code snippet:
 <s> if ( F -> hasFnAttribute ( <STR_LIT> ) ) return F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; else return false ; }"
LLVM,NVPTX,1014,"Predict the next statement of this code snippet:
 <s> return FtzEnabled ; } else { const Function * F = MF . getFunction ( ) ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) return F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ;"
LLVM,NVPTX,1015,"Predict the next statement of this code snippet:
 <s> return UsePrecSqrtF32 ; } else { return ! getTargetMachine ( ) . Options . UnsafeFPMath ; }"
LLVM,NVPTX,1016,"Predict the next statement of this code snippet:
 <s> if ( UsePrecSqrtF32 . getNumOccurrences ( ) > <NUM_LIT> ) { return UsePrecSqrtF32 ; } else { return ! getTargetMachine ( ) . Options . UnsafeFPMath ;"
LLVM,NVPTX,1017,"Predict the next statement of this code snippet:
 <s> VectorInfo . assign ( ValueVTs . size ( ) , PVF_SCALAR ) ; for ( int I = <NUM_LIT> , E = ValueVTs . size ( ) ; I != E ; ++ I ) { assert ( VectorInfo [ I ] == PVF_SCALAR && <STR_LIT> ) ; for ( unsigned AccessSize : { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) { unsigned NumElts = CanMergeParamLoadStoresStartingAt ( I , AccessSize , ValueVTs , Offsets , ParamAlignment ) ; switch ( NumElts ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : continue ; case <NUM_LIT> : assert ( I + <NUM_LIT> < E && <STR_LIT> ) ; VectorInfo [ I ] = PVF_FIRST ; VectorInfo [ I + <NUM_LIT> ] = PVF_LAST ; I += <NUM_LIT> ;"
LLVM,NVPTX,1018,"Predict the next statement of this code snippet:
 <s> delete static_cast < <ISA_LIT>Section * > ( LSDASection ) ; delete static_cast < <ISA_LIT>Section * > ( EHFrameSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfAbbrevSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfInfoSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfLineSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfFrameSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfPubTypesSection ) ; delete static_cast < const <ISA_LIT>Section * > ( DwarfDebugInlineSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfStrSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfLocSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfARangesSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfRangesSection ) ;"
LLVM,NVPTX,1019,"Predict the next statement of this code snippet:
 <s> if ( MF . getTarget ( ) . Options . UnsafeFPMath ) return true ; const Function & F = MF . getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { Attribute Attr = F . getFnAttribute ( <STR_LIT> ) ; StringRef Val = Attr . getValueAsString ( ) ;"
LLVM,NVPTX,1020,"Predict the next statement of this code snippet:
 <s> return ; } ComputeValueVTs ( TLI , DL , Ty , TempVTs , & TempOffsets , StartingOffset ) ; for ( unsigned i = <NUM_LIT> , e = TempVTs . size ( ) ; i != e ; ++ i ) { EVT VT = TempVTs [ i ] ; uint64_t Off = TempOffsets [ i ] ; if ( VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> && NumElts % <NUM_LIT> == <NUM_LIT> ) { EltVT = <STR_LIT> ; NumElts /= <NUM_LIT> ; } for ( unsigned j = <NUM_LIT> ; j != NumElts ; ++ j ) { ValueVTs . push_back ( EltVT ) ; if ( Offsets ) Offsets -> push_back ( Off + j * EltVT . getStoreSize ( ) ) ; } } else {"
LLVM,NVPTX,1021,"Predict the next statement of this code snippet:
 <s> static void ComputePTXValueVTs ( const TargetLowering & TLI , const DataLayout & DL , Type * Ty , SmallVectorImpl < EVT > & ValueVTs , SmallVectorImpl < uint64_t > * Offsets = nullptr , uint64_t StartingOffset = <NUM_LIT> ) { SmallVector < EVT , <NUM_LIT> > TempVTs ; SmallVector < uint64_t , <NUM_LIT> > TempOffsets ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) { ValueVTs . push_back ( EVT ( <STR_LIT> ) ) ; ValueVTs . push_back ( EVT ( <STR_LIT> ) ) ; if ( Offsets ) { Offsets -> push_back ( StartingOffset + <NUM_LIT> ) ; Offsets -> push_back ( StartingOffset + <NUM_LIT> ) ; } return ; } if ( StructType * STy = dyn_cast < StructType > ( Ty ) ) { auto const * SL = DL . getStructLayout ( STy ) ; auto ElementNum = <NUM_LIT> ; for ( auto * EI : STy -> elements ( ) ) { ComputePTXValueVTs ( TLI , DL , EI , ValueVTs , Offsets , StartingOffset + SL -> getElementOffset ( ElementNum ) ) ; ++ ElementNum ; } return ; } ComputeValueVTs ( TLI , DL , Ty , TempVTs , & TempOffsets , StartingOffset ) ; for ( unsigned i = <NUM_LIT> , e = TempVTs . size ( ) ; i != e ; ++ i ) { EVT VT = TempVTs [ i ] ; uint64_t Off = TempOffsets [ i ] ; if ( VT . isVector ( ) ) {"
LLVM,NVPTX,1022,"Predict the next statement of this code snippet:
 <s> } unsigned Align = <NUM_LIT> ; const Value * DirectCallee = CS . getCalledFunction ( ) ; if ( ! DirectCallee ) { const Instruction * CalleeI = CS . getInstruction ( ) ; assert ( CalleeI && <STR_LIT> ) ; if ( isa < CallInst > ( CalleeI ) ) { if ( getAlign ( * cast < CallInst > ( CalleeI ) , Idx , Align ) ) return Align ; const Value * CalleeV = cast < CallInst > ( CalleeI ) -> getCalledValue ( ) ; while ( isa < ConstantExpr > ( CalleeV ) ) { const ConstantExpr * CE = cast < ConstantExpr > ( CalleeV ) ; if ( ! CE -> isCast ( ) ) break ; CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,1023,"Predict the next statement of this code snippet:
 <s> if ( isa < CallInst > ( CalleeI ) ) { if ( getAlign ( * cast < CallInst > ( CalleeI ) , Idx , Align ) ) return Align ; const Value * CalleeV = cast < CallInst > ( CalleeI ) -> getCalledValue ( ) ; while ( isa < ConstantExpr > ( CalleeV ) ) { const ConstantExpr * CE = cast < ConstantExpr > ( CalleeV ) ; if ( ! CE -> isCast ( ) ) break ; CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ; }"
LLVM,NVPTX,1024,"Predict the next statement of this code snippet:
 <s> TargetLoweringBase :: LegalizeTypeAction <ISA_LIT>TargetLowering :: getPreferredVectorAction ( MVT VT ) const {"
LLVM,NVPTX,1025,"Predict the next statement of this code snippet:
 <s> if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getScalarType ( ) == <STR_LIT> ) return TypeSplitVector ; if ( VT == <STR_LIT> ) return TypeLegal ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;"
LLVM,NVPTX,1026,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) { return ! AM . BaseOffs && ! AM . HasBaseReg && ! AM . Scale ; }"
LLVM,NVPTX,1027,"Predict the next statement of this code snippet:
 <s> for ( unsigned parti = <NUM_LIT> , parte = VTs . size ( ) ; parti != parte ; ++ parti ) { if ( VectorInfo [ parti ] & PVF_FIRST ) { assert ( VecIdx == - <NUM_LIT> && <STR_LIT> ) ; VecIdx = parti ; } if ( VectorInfo [ parti ] & PVF_LAST ) { unsigned NumElts = parti - VecIdx + <NUM_LIT> ; EVT EltVT = VTs [ parti ] ; EVT LoadVT = EltVT ; if ( EltVT == <STR_LIT> ) LoadVT = <STR_LIT> ; else if ( EltVT == <STR_LIT> ) LoadVT = <STR_LIT> ; EVT VecVT = EVT :: getVectorVT ( F -> getContext ( ) , LoadVT , NumElts ) ; SDValue VecAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Arg , DAG . getConstant ( Offsets [ VecIdx ] , dl , PtrVT ) ) ; Value * srcValue = Constant :: getNullValue ( PointerType :: get ( EltVT . getTypeForEVT ( F -> getContext ( ) ) , ADDRESS_SPACE_PARAM ) ) ; SDValue P = DAG . getLoad ( VecVT , dl , Root , VecAddr , MachinePointerInfo ( srcValue ) , aggregateIsPacked , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; if ( P . getNode ( ) ) P . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; ++ j ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , LoadVT , P , DAG . getIntPtrConstant ( j , dl ) ) ; if ( EltVT == <STR_LIT> ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt ) ; else if ( EltVT == <STR_LIT> ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt ) ; if ( Ins [ InsIdx ] . VT . isInteger ( ) && Ins [ InsIdx ] . VT . getSizeInBits ( ) > LoadVT . getSizeInBits ( ) ) { unsigned Extend = Ins [ InsIdx ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> ; Elt = DAG . getNode ( Extend , dl , Ins [ InsIdx ] . VT , Elt ) ; } InVals . push_back ( Elt ) ; } VecIdx = - <NUM_LIT> ; } ++ InsIdx ; } if ( VTs . size ( ) > <NUM_LIT> ) -- InsIdx ; continue ; } EVT ObjectVT = getValueType ( DL , Ty ) ; assert ( ObjectVT == Ins [ InsIdx ] . VT && <STR_LIT> ) ; SDValue Arg = getParamSymbol ( DAG , idx , PtrVT ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ;"
LLVM,NVPTX,1028,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerFROUND ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> ) return LowerFROUND32 ( Op , DAG ) ;"
LLVM,NVPTX,1029,"Predict the next statement of this code snippet:
 <s> SDValue RoundedA = DAG . getNode ( <STR_LIT> , SL , VT , AdjustedA ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue IsLarge = DAG . getSetCC ( SL , SetCCVT , AbsA , DAG . getConstantFP ( pow ( <NUM_LIT> , <NUM_LIT> ) , SL , VT ) , <STR_LIT> ) ; RoundedA = DAG . getNode ( <STR_LIT> , SL , VT , IsLarge , A , RoundedA ) ;"
LLVM,NVPTX,1030,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerFROUND64 ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; SDValue A = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue AbsA = DAG . getNode ( <STR_LIT> , SL , VT , A ) ;"
LLVM,NVPTX,1031,"Predict the next statement of this code snippet:
 <s> RoundedA = DAG . getNode ( <STR_LIT> , SL , VT , IsSmall , DAG . getConstantFP ( <NUM_LIT> , SL , VT ) , RoundedA ) ; RoundedA = DAG . getNode ( <STR_LIT> , SL , VT , RoundedA , A ) ; DAG . getNode ( <STR_LIT> , SL , VT , A ) ;"
LLVM,NVPTX,1032,"Predict the next statement of this code snippet:
 <s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) , GAN -> getAddressSpace ( ) ) ;"
LLVM,NVPTX,1033,"Predict the next statement of this code snippet:
 <s> SDLoc dl ( Op ) ; const GlobalAddressSDNode * GAN = cast < GlobalAddressSDNode > ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) , GAN -> getAddressSpace ( ) ) ; Op = DAG . getTargetGlobalAddress ( GAN -> getGlobal ( ) , dl , PtrVT ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Op ) ;"
LLVM,NVPTX,1034,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) == <STR_LIT> ) return LowerLOADi1 ( Op , DAG ) ; if ( Op . getValueType ( ) == <STR_LIT> ) { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ;"
LLVM,NVPTX,1035,"Predict the next statement of this code snippet:
 <s> if ( Op . getValueType ( ) == <STR_LIT> ) return LowerLOADi1 ( Op , DAG ) ; if ( Op . getValueType ( ) == <STR_LIT> ) { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT MemVT = Load -> getMemoryVT ( ) ; if ( ! allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , * Load -> getMemOperand ( ) ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( Op ) ) ; } }"
LLVM,NVPTX,1036,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerSelect ( Op , DAG ) ;"
LLVM,NVPTX,1037,"Predict the next statement of this code snippet:
 <s> auto VectorInfo = VectorizePTXValueVTs ( VTs , Offsets , RetTy -> isSized ( ) ? DL . getABITypeAlignment ( RetTy ) : <NUM_LIT> ) ; bool ExtendIntegerRetVal = RetTy -> isIntegerTy ( ) && DL . getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > StoreOperands ; for ( unsigned i = <NUM_LIT> , e = VTs . size ( ) ; i != e ; ++ i ) { if ( VectorInfo [ i ] & PVF_FIRST ) { assert ( StoreOperands . empty ( ) && <STR_LIT> ) ; StoreOperands . push_back ( Chain ) ; StoreOperands . push_back ( DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) ) ; } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size ( ) - <NUM_LIT> ; switch ( NumElts ) { case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> :"
LLVM,NVPTX,1038,"Predict the next statement of this code snippet:
 <s> SmallVector < EVT , <NUM_LIT> > VTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputePTXValueVTs ( * this , DL , RetTy , VTs , & Offsets ) ; assert ( VTs . size ( ) == OutVals . size ( ) && <STR_LIT> ) ; auto VectorInfo = VectorizePTXValueVTs ( VTs , Offsets , RetTy -> isSized ( ) ? DL . getABITypeAlignment ( RetTy ) : <NUM_LIT> ) ; bool ExtendIntegerRetVal = RetTy -> isIntegerTy ( ) && DL . getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > StoreOperands ; for ( unsigned i = <NUM_LIT> , e = VTs . size ( ) ; i != e ; ++ i ) { if ( VectorInfo [ i ] & PVF_FIRST ) { assert ( StoreOperands . empty ( ) && <STR_LIT> ) ; StoreOperands . push_back ( Chain ) ; StoreOperands . push_back ( DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) ) ; } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ;"
LLVM,NVPTX,1039,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerSTORE ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; EVT VT = Store -> getMemoryVT ( ) ; if ( VT == <STR_LIT> ) return LowerSTOREi1 ( Op , DAG ) ; if ( VT == <STR_LIT> && ! allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , * Store -> getMemOperand ( ) ) ) return expandUnalignedStore ( Store , DAG ) ; if ( VT . isVector ( ) ) return LowerSTOREVector ( Op , DAG ) ;"
LLVM,NVPTX,1040,"Predict the next statement of this code snippet:
 <s> } else { const Function & F = MF . getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) return F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ;"
LLVM,NVPTX,1041,"Predict the next statement of this code snippet:
 <s> } else { const Function & F = MF . getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) return F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; else return false ;"
LLVM,NVPTX,1042,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetObjectFile :: ~ <ISA_LIT>TargetObjectFile ( ) {"
LLVM,NVPTX,1043,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetObjectFile :: ~ <ISA_LIT>TargetObjectFile ( ) {"
LLVM,NVPTX,1044,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: allowFMA ( MachineFunction & MF , CodeGenOpt :: Level OptLevel ) const { const Function * F = MF . getFunction ( ) ; const TargetOptions & TO = MF . getTarget ( ) . Options ;"
LLVM,NVPTX,1045,"Predict the next statement of this code snippet:
 <s> if ( FMAContractLevelOpt . getNumOccurrences ( ) > <NUM_LIT> ) { return FMAContractLevelOpt > <NUM_LIT> ; } else if ( OptLevel == <NUM_LIT> ) { return false ; } else if ( TO . AllowFPOpFusion == FPOpFusion :: Fast || TO . UnsafeFPMath ) { return true ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) {"
LLVM,NVPTX,1046,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>Section :: anchor ( ) {"
LLVM,NVPTX,1047,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>Section :: anchor ( ) {"
LLVM,NVPTX,1048,"Predict the next statement of this code snippet:
 <s> OperandSignedness LHSSign ; if ( ! IsMulWideOperandDemotable ( LHS , OptSize , LHSSign ) ) return false ; if ( LHSSign == Unknown ) return false ; IsSigned = ( LHSSign == Signed ) ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( RHS ) ) {"
LLVM,NVPTX,1049,"Predict the next statement of this code snippet:
 <s> SmallVector < uint64_t , <NUM_LIT> > TempOffsets ; ComputeValueVTs ( TLI , DL , Ty , TempVTs , & TempOffsets , StartingOffset ) ; for ( unsigned i = <NUM_LIT> , e = TempVTs . size ( ) ; i != e ; ++ i ) { EVT VT = TempVTs [ i ] ; uint64_t Off = TempOffsets [ i ] ; if ( VT . isVector ( ) ) for ( unsigned j = <NUM_LIT> , je = VT . getVectorNumElements ( ) ; j != je ; ++ j ) { ValueVTs . push_back ( VT . getVectorElementType ( ) ) ; if ( Offsets ) Offsets -> push_back ( Off + j * VT . getVectorElementType ( ) . getStoreSize ( ) ) ; } else { ValueVTs . push_back ( VT ) ;"
LLVM,NVPTX,1050,"Predict the next statement of this code snippet:
 <s> if ( llvm :: getAlign ( * cast < CallInst > ( CalleeI ) , Idx , Align ) ) return Align ; const Value * CalleeV = cast < CallInst > ( CalleeI ) -> getCalledValue ( ) ; while ( isa < ConstantExpr > ( CalleeV ) ) { const ConstantExpr * CE = cast < ConstantExpr > ( CalleeV ) ; if ( ! CE -> isCast ( ) ) break ; CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,1051,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'b' : case 'r' : case 'h' : case 'c' :"
LLVM,NVPTX,1052,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: getParamSymbol ( SelectionDAG & DAG , int idx , EVT v ) const { std :: string ParamSym ; raw_string_ostream ParamStr ( ParamSym ) ; ParamStr << DAG . getMachineFunction ( ) . getName ( ) << <STR_LIT> << idx ; ParamStr . flush ( ) ;"
LLVM,NVPTX,1053,"Predict the next statement of this code snippet:
 <s> ParamStr << DAG . getMachineFunction ( ) . getName ( ) << <STR_LIT> << idx ; ParamStr . flush ( ) ; std :: string * SavedStr = nvTM -> getManagedStrPool ( ) -> getManagedString ( ParamSym . c_str ( ) ) ;"
LLVM,NVPTX,1054,"Predict the next statement of this code snippet:
 <s> if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getScalarType ( ) == <STR_LIT> ) return TypeSplitVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;"
LLVM,NVPTX,1055,"Predict the next statement of this code snippet:
 <s> if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getScalarType ( ) == <STR_LIT> ) return TypeSplitVector ;"
LLVM,NVPTX,1056,"Predict the next statement of this code snippet:
 <s> size = retTy -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( retTy ) ) { O << <STR_LIT> << PtrVT . getSizeInBits ( ) << <STR_LIT> ; } else if ( ( retTy -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( retTy ) ) { auto & DL = CS -> getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << DL . getTypeAllocSize ( retTy ) << <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; if ( ! llvm :: getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) {"
LLVM,NVPTX,1057,"Predict the next statement of this code snippet:
 <s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : case 'N' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ;"
LLVM,NVPTX,1058,"Predict the next statement of this code snippet:
 <s> const std :: string TypeName = STy && ! STy -> isLiteral ( ) ? STy -> getName ( ) : <STR_LIT> ; return std :: find ( std :: begin ( specialTypes ) , std :: end ( specialTypes ) , TypeName ) != std :: end ( specialTypes ) ;"
LLVM,NVPTX,1059,"Predict the next statement of this code snippet:
 <s> if ( ! PTy ) return false ; if ( ! context ) return false ; auto * STy = dyn_cast < StructType > ( PTy -> getElementType ( ) ) ; const std :: string TypeName = STy && ! STy -> isLiteral ( ) ? STy -> getName ( ) : <STR_LIT> ;"
LLVM,NVPTX,1060,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) { return ! AM . BaseOffs && ! AM . HasBaseReg && ! AM . Scale ; } switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( AM . HasBaseReg ) return false ; break ;"
LLVM,NVPTX,1061,"Predict the next statement of this code snippet:
 <s> EVT OrigVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OrigVT . getSizeInBits ( ) <= OptSize ) { S = Signed ; return true ; } } else if ( Op . getOpcode ( ) == <STR_LIT> ) {"
LLVM,NVPTX,1062,"Predict the next statement of this code snippet:
 <s> static bool IsPTXVectorType ( MVT VT ) { switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,1063,"Predict the next statement of this code snippet:
 <s> if ( Constraint . length ( ) > <NUM_LIT> ) return ; else TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ;"
LLVM,NVPTX,1064,"Predict the next statement of this code snippet:
 <s> if ( Constraint . length ( ) > <NUM_LIT> ) return ;"
LLVM,NVPTX,1065,"Predict the next statement of this code snippet:
 <s> unsigned NumSubElem = VVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumSubElem ; ++ j ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SubOp , DAG . getIntPtrConstant ( j , dl ) ) ) ; } } return DAG . getNode ( <STR_LIT> , dl , Node -> getValueType ( <NUM_LIT> ) , Ops ) ;"
LLVM,NVPTX,1066,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) const { SDNode * Node = Op . getNode ( ) ; SDLoc dl ( Node ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumOperands = Node -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) {"
LLVM,NVPTX,1067,"Predict the next statement of this code snippet:
 <s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ;"
LLVM,NVPTX,1068,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) == <STR_LIT> ) return LowerLOADi1 ( Op , DAG ) ;"
LLVM,NVPTX,1069,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerLOADi1 ( SDValue Op , SelectionDAG & DAG ) const { SDNode * Node = Op . getNode ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( Node ) ; SDLoc dl ( Node ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ;"
LLVM,NVPTX,1070,"Predict the next statement of this code snippet:
 <s> SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , newLD ) ; SDValue Ops [ ] = { result , LD -> getChain ( ) } ;"
LLVM,NVPTX,1071,"Predict the next statement of this code snippet:
 <s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op2 ) ; SDValue Select = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 , Op2 ) ;"
LLVM,NVPTX,1072,"Predict the next statement of this code snippet:
 <s> SDValue Op1 = Op -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = Op -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op . getNode ( ) ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op2 ) ; SDValue Select = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 , Op2 ) ;"
LLVM,NVPTX,1073,"Predict the next statement of this code snippet:
 <s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ; } else { SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ;"
LLVM,NVPTX,1074,"Predict the next statement of this code snippet:
 <s> if ( VTBits == <NUM_LIT> && STI . getSmVersion ( ) >= <NUM_LIT> ) { SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ; } else { SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue Cmp = DAG . getSetCC ( dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , Cmp , TrueVal , FalseVal ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ;"
LLVM,NVPTX,1075,"Predict the next statement of this code snippet:
 <s> SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue Cmp = DAG . getSetCC ( dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , Cmp , TrueVal , FalseVal ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ;"
LLVM,NVPTX,1076,"Predict the next statement of this code snippet:
 <s> else if ( ValVT . isVector ( ) ) return LowerSTOREVector ( Op , DAG ) ;"
LLVM,NVPTX,1077,"Predict the next statement of this code snippet:
 <s> else if ( ValVT . isVector ( ) ) return LowerSTOREVector ( Op , DAG ) ;"
LLVM,NVPTX,1078,"Predict the next statement of this code snippet:
 <s> bool isNonTemporal = ST -> isNonTemporal ( ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp3 ) ;"
LLVM,NVPTX,1079,"Predict the next statement of this code snippet:
 <s> bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue ExtVal = DAG . getNode ( <STR_LIT> , DL , EltVT , Val , DAG . getIntPtrConstant ( i , DL ) ) ; if ( NeedExt ) ExtVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ExtVal ) ; Ops . push_back ( ExtVal ) ; }"
LLVM,NVPTX,1080,"Predict the next statement of this code snippet:
 <s> return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } MemSDNode * MemSD = cast < MemSDNode > ( N ) ; const DataLayout & TD = DAG . getDataLayout ( ) ; unsigned Align = MemSD -> getAlignment ( ) ; unsigned PrefAlign = TD . getPrefTypeAlignment ( ValVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return SDValue ( ) ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : {"
LLVM,NVPTX,1081,"Predict the next statement of this code snippet:
 <s> static SDValue PerformADDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget , CodeGenOpt :: Level OptLevel ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget , OptLevel ) ;"
LLVM,NVPTX,1082,"Predict the next statement of this code snippet:
 <s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget , OptLevel ) ; if ( Result . getNode ( ) ) return Result ;"
LLVM,NVPTX,1083,"Predict the next statement of this code snippet:
 <s> return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; } else if ( N0 . getOpcode ( ) == <STR_LIT> ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) { const auto * TLI = static_cast < const <ISA_LIT>TargetLowering * > ( & DAG . getTargetLoweringInfo ( ) ) ; if ( ! TLI -> allowFMA ( DAG . getMachineFunction ( ) , OptLevel ) ) return SDValue ( ) ; int numUses = <NUM_LIT> ; int nonAddCount = <NUM_LIT> ; for ( SDNode :: use_iterator UI = N0 . getNode ( ) -> use_begin ( ) , UE = N0 . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { numUses ++ ; SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> ) ++ nonAddCount ; } if ( numUses >= <NUM_LIT> ) return SDValue ( ) ; if ( nonAddCount ) { int orderNo = N -> getIROrder ( ) ; int orderNo2 = N0 . getNode ( ) -> getIROrder ( ) ; if ( orderNo - orderNo2 < <NUM_LIT> ) return SDValue ( ) ; bool opIsLive = false ; const SDNode * left = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; const SDNode * right = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( isa < ConstantSDNode > ( left ) || isa < ConstantSDNode > ( right ) ) opIsLive = true ; if ( ! opIsLive ) for ( SDNode :: use_iterator UI = left -> use_begin ( ) , UE = left -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) { opIsLive = true ; break ; } } if ( ! opIsLive ) for ( SDNode :: use_iterator UI = right -> use_begin ( ) , UE = right -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) { opIsLive = true ;"
LLVM,NVPTX,1084,"Predict the next statement of this code snippet:
 <s> Val = Val -> getOperand ( <NUM_LIT> ) ; } if ( Val -> getOpcode ( ) == <STR_LIT> || Val -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * MaskCnst = dyn_cast < ConstantSDNode > ( Mask ) ; if ( ! MaskCnst ) { return SDValue ( ) ; } uint64_t MaskVal = MaskCnst -> getZExtValue ( ) ; if ( MaskVal != <NUM_LIT> ) { return SDValue ( ) ; } MemSDNode * Mem = dyn_cast < MemSDNode > ( Val ) ; if ( ! Mem ) { return SDValue ( ) ; } EVT MemVT = Mem -> getMemoryVT ( ) ; if ( MemVT != <STR_LIT> && MemVT != <STR_LIT> ) { return SDValue ( ) ; }"
LLVM,NVPTX,1085,"Predict the next statement of this code snippet:
 <s> if ( Val -> isMachineOpcode ( ) && Val -> getMachineOpcode ( ) == <STR_LIT> ) { Val = Val -> getOperand ( <NUM_LIT> ) ; } if ( Val -> getOpcode ( ) == <STR_LIT> || Val -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * MaskCnst = dyn_cast < ConstantSDNode > ( Mask ) ; if ( ! MaskCnst ) { return SDValue ( ) ; } uint64_t MaskVal = MaskCnst -> getZExtValue ( ) ; if ( MaskVal != <NUM_LIT> ) { return SDValue ( ) ; } MemSDNode * Mem = dyn_cast < MemSDNode > ( Val ) ; if ( ! Mem ) { return SDValue ( ) ; } EVT MemVT = Mem -> getMemoryVT ( ) ;"
LLVM,NVPTX,1086,"Predict the next statement of this code snippet:
 <s> return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformSHLCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DCI ) ;"
LLVM,NVPTX,1087,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return PerformMULCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformSHLCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DCI ) ; } return SDValue ( ) ;"
LLVM,NVPTX,1088,"Predict the next statement of this code snippet:
 <s> static SDValue PerformMULCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , CodeGenOpt :: Level OptLevel ) { if ( OptLevel > <NUM_LIT> ) { SDValue Ret = TryMULWIDECombine ( N , DCI ) ; if ( Ret . getNode ( ) ) return Ret ;"
LLVM,NVPTX,1089,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : Larger = RHS ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Larger = LHS ; break ; default : return SDValue ( ) ; } const bool IsMax = ( Larger == True ) ; const bool IsSigned = <STR_LIT> ( CC ) ; unsigned IntrinsicId ; if ( VT == <STR_LIT> ) { if ( IsSigned ) IntrinsicId = IsMax ? <STR_LIT> : <STR_LIT> ; else IntrinsicId = IsMax ? <STR_LIT> : <STR_LIT> ; } else { assert ( VT == <STR_LIT> ) ; if ( IsSigned ) IntrinsicId = IsMax ? <STR_LIT> : <STR_LIT> ; else IntrinsicId = IsMax ? <STR_LIT> : <STR_LIT> ;"
LLVM,NVPTX,1090,"Predict the next statement of this code snippet:
 <s> if ( Ret . getNode ( ) ) return Ret ; }"
LLVM,NVPTX,1091,"Predict the next statement of this code snippet:
 <s> if ( Ret . getNode ( ) ) return Ret ; }"
LLVM,NVPTX,1092,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ResVT . isVector ( ) ) { unsigned NumElts = ResVT . getVectorNumElements ( ) ; EVT EltVT = ResVT . getVectorElementType ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : switch ( IntrinNo ) { default : return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { switch ( IntrinNo ) { default : return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; OtherOps . push_back ( Chain ) ; OtherOps . append ( N -> op_begin ( ) + <NUM_LIT> , N -> op_end ( ) ) ;"
LLVM,NVPTX,1093,"Predict the next statement of this code snippet:
 <s> auto & TD = DAG . getDataLayout ( ) ; unsigned PrefAlign = TD . getPrefTypeAlignment ( ResVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) , DL ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ; }"
LLVM,NVPTX,1094,"Predict the next statement of this code snippet:
 <s> default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : ReplaceLoadVector ( N , DAG , Results ) ; return ;"
LLVM,NVPTX,1095,"Predict the next statement of this code snippet:
 <s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const {"
LLVM,NVPTX,1096,"Predict the next statement of this code snippet:
 <s> APInt ShiftAmt = ShlRHS -> getAPIntValue ( ) ; unsigned BitWidth = MulType . getSizeInBits ( ) ; if ( ShiftAmt . sge ( <NUM_LIT> ) && ShiftAmt . slt ( BitWidth ) ) { APInt MulVal = APInt ( BitWidth , <NUM_LIT> ) << ShiftAmt ; RHS = DCI . DAG . getConstant ( MulVal , DL , MulType ) ; } else { return SDValue ( ) ; } } bool Signed ; if ( ! AreMulWideOperandsDemotable ( LHS , RHS , OptSize , Signed ) ) { return SDValue ( ) ; } EVT DemotedVT ; if ( MulType == <STR_LIT> ) { DemotedVT = <STR_LIT> ; } else { DemotedVT = <STR_LIT> ; } SDValue TruncLHS = DCI . DAG . getNode ( <STR_LIT> , DL , DemotedVT , LHS ) ; SDValue TruncRHS = DCI . DAG . getNode ( <STR_LIT> , DL , DemotedVT , RHS ) ; unsigned Opc ; if ( Signed ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } return DCI . DAG . getNode ( Opc , DL , MulType , TruncLHS , TruncRHS ) ;"
LLVM,NVPTX,1097,"Predict the next statement of this code snippet:
 <s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) { if ( isa < ConstantSDNode > ( LHS ) ) { std :: swap ( LHS , RHS ) ; } } if ( N -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * ShlRHS = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! ShlRHS ) { return SDValue ( ) ; } APInt ShiftAmt = ShlRHS -> getAPIntValue ( ) ; unsigned BitWidth = MulType . getSizeInBits ( ) ; if ( ShiftAmt . sge ( <NUM_LIT> ) && ShiftAmt . slt ( BitWidth ) ) { APInt MulVal = APInt ( BitWidth , <NUM_LIT> ) << ShiftAmt ; RHS = DCI . DAG . getConstant ( MulVal , DL , MulType ) ; } else { return SDValue ( ) ; } } bool Signed ; if ( ! AreMulWideOperandsDemotable ( LHS , RHS , OptSize , Signed ) ) { return SDValue ( ) ; } EVT DemotedVT ; if ( MulType == <STR_LIT> ) {"
LLVM,NVPTX,1098,"Predict the next statement of this code snippet:
 <s> delete static_cast < <ISA_LIT>Section * > ( DwarfFrameSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfPubTypesSection ) ; delete static_cast < const <ISA_LIT>Section * > ( DwarfDebugInlineSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfStrSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfLocSection ) ;"
LLVM,NVPTX,1099,"Predict the next statement of this code snippet:
 <s> bool isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT ) const override {"
LLVM,NVPTX,1100,"Predict the next statement of this code snippet:
 <s> bool isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT ) const override { return true ;"
LLVM,NVPTX,1101,"Predict the next statement of this code snippet:
 <s> if ( VT . isVector ( ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ;"
LLVM,NVPTX,1102,"Predict the next statement of this code snippet:
 <s> if ( VT . isVector ( ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ;"
LLVM,NVPTX,1103,"Predict the next statement of this code snippet:
 <s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const {"
LLVM,NVPTX,1104,"Predict the next statement of this code snippet:
 <s> static void ComputePTXValueVTs ( const TargetLowering & TLI , const DataLayout & DL , Type * Ty , SmallVectorImpl < EVT > & ValueVTs , SmallVectorImpl < uint64_t > * Offsets = nullptr , uint64_t StartingOffset = <NUM_LIT> ) { SmallVector < EVT , <NUM_LIT> > TempVTs ; SmallVector < uint64_t , <NUM_LIT> > TempOffsets ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) { ValueVTs . push_back ( EVT ( <STR_LIT> ) ) ; ValueVTs . push_back ( EVT ( <STR_LIT> ) ) ; if ( Offsets ) { Offsets -> push_back ( StartingOffset + <NUM_LIT> ) ; Offsets -> push_back ( StartingOffset + <NUM_LIT> ) ; } return ; } ComputeValueVTs ( TLI , DL , Ty , TempVTs , & TempOffsets , StartingOffset ) ; for ( unsigned i = <NUM_LIT> , e = TempVTs . size ( ) ; i != e ; ++ i ) { EVT VT = TempVTs [ i ] ; uint64_t Off = TempOffsets [ i ] ; if ( VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> && NumElts % <NUM_LIT> == <NUM_LIT> ) { EltVT = <STR_LIT> ; NumElts /= <NUM_LIT> ; } for ( unsigned j = <NUM_LIT> ; j != NumElts ; ++ j ) { ValueVTs . push_back ( EltVT ) ; if ( Offsets ) Offsets -> push_back ( Off + j * EltVT . getStoreSize ( ) ) ; } } else { ValueVTs . push_back ( VT ) ; if ( Offsets ) Offsets -> push_back ( Off ) ; }"
LLVM,NVPTX,1105,"Predict the next statement of this code snippet:
 <s> if ( ! isABI ) return <STR_LIT> ; std :: stringstream O ; O << <STR_LIT> << uniqueCallSite << <STR_LIT> ; if ( retTy -> getTypeID ( ) == Type :: VoidTyID ) { O << <STR_LIT> ; } else { O << <STR_LIT> ; if ( retTy -> isFloatingPointTy ( ) || ( retTy -> isIntegerTy ( ) && ! retTy -> isIntegerTy ( <NUM_LIT> ) ) ) { unsigned size = <NUM_LIT> ; if ( auto * ITy = dyn_cast < IntegerType > ( retTy ) ) { size = ITy -> getBitWidth ( ) ; } else { assert ( retTy -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = retTy -> getPrimitiveSizeInBits ( ) ; } if ( size < <NUM_LIT> ) size = <NUM_LIT> ; O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( retTy ) ) { O << <STR_LIT> << PtrVT . getSizeInBits ( ) << <STR_LIT> ; } else if ( retTy -> isAggregateType ( ) || retTy -> isVectorTy ( ) || retTy -> isIntegerTy ( <NUM_LIT> ) ) { auto & DL = CS . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << DL . getTypeAllocSize ( retTy ) << <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) {"
LLVM,NVPTX,1106,"Predict the next statement of this code snippet:
 <s> } O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS . getInstruction ( ) ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ;"
LLVM,NVPTX,1107,"Predict the next statement of this code snippet:
 <s> if ( Offsets [ Idx ] & ( AccessSize - <NUM_LIT> ) ) return <NUM_LIT> ; EVT EltVT = ValueVTs [ Idx ] ; unsigned EltSize = EltVT . getStoreSize ( ) ; if ( EltSize >= AccessSize ) return <NUM_LIT> ; unsigned NumElts = AccessSize / EltSize ; if ( AccessSize != EltSize * NumElts ) return <NUM_LIT> ; if ( Idx + NumElts > ValueVTs . size ( ) ) return <NUM_LIT> ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return <NUM_LIT> ; for ( unsigned j = Idx + <NUM_LIT> ; j < Idx + NumElts ; ++ j ) {"
LLVM,NVPTX,1108,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ; } O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS . getInstruction ( ) ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; Align align = Outs [ OIdx ] . Flags . getNonZeroByValAlign ( ) ;"
LLVM,NVPTX,1109,"Predict the next statement of this code snippet:
 <s> } else { O << <STR_LIT> ; if ( retTy -> isFloatingPointTy ( ) || ( retTy -> isIntegerTy ( ) && ! retTy -> isIntegerTy ( <NUM_LIT> ) ) ) { unsigned size = <NUM_LIT> ; if ( auto * ITy = dyn_cast < IntegerType > ( retTy ) ) { size = ITy -> getBitWidth ( ) ; } else { assert ( retTy -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = retTy -> getPrimitiveSizeInBits ( ) ; } if ( size < <NUM_LIT> ) size = <NUM_LIT> ; O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( retTy ) ) { O << <STR_LIT> << PtrVT . getSizeInBits ( ) << <STR_LIT> ; } else if ( retTy -> isAggregateType ( ) || retTy -> isVectorTy ( ) || retTy -> isIntegerTy ( <NUM_LIT> ) ) { O << <STR_LIT> << ( retAlignment ? retAlignment -> value ( ) : <NUM_LIT> ) << <STR_LIT> << DL . getTypeAllocSize ( retTy ) << <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ;"
LLVM,NVPTX,1110,"Predict the next statement of this code snippet:
 <s> return MF . getDenormalMode ( APFloat :: IEEEsingle ( ) ) . Output == DenormalMode :: PreserveSign ;"
LLVM,NVPTX,1111,"Predict the next statement of this code snippet:
 <s> if ( FtzEnabled . getNumOccurrences ( ) > <NUM_LIT> ) { return FtzEnabled ; }"
LLVM,NVPTX,1112,"Predict the next statement of this code snippet:
 <s> return MF . getDenormalMode ( APFloat :: IEEEsingle ( ) ) == DenormalMode :: PreserveSign ;"
LLVM,NVPTX,1113,"Predict the next statement of this code snippet:
 <s> return getExtSymb ( DAG , <STR_LIT> , idx , v ) ;"
LLVM,NVPTX,1114,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; MVT thePointerTy = getPointerTy ( ) ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { const Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( Outs [ i ] . Flags . isByVal ( ) == false ) { unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI ) { unsigned align = Outs [ i ] . Flags . getByValAlign ( ) ; unsigned sz = getDataLayout ( ) -> getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , ETy , vtparts ) ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) {"
LLVM,NVPTX,1115,"Predict the next statement of this code snippet:
 <s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;"
LLVM,NVPTX,1116,"Predict the next statement of this code snippet:
 <s> case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : case 'N' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } }"
LLVM,NVPTX,1117,"Predict the next statement of this code snippet:
 <s> default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }"
LLVM,NVPTX,1118,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; if ( Intrinsic == <STR_LIT> ) Info . memVT = <STR_LIT> ; else if ( Intrinsic == <STR_LIT> ) Info . memVT = getPointerTy ( ) ; else Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = false ; Info . align = <NUM_LIT> ; return true ;"
LLVM,NVPTX,1119,"Predict the next statement of this code snippet:
 <s> const StructType * STy = dyn_cast < StructType > ( PTy -> getElementType ( ) ) ; const std :: string TypeName = STy ? STy -> getName ( ) : <STR_LIT> ; for ( int i = <NUM_LIT> , e = array_lengthof ( specialTypes ) ; i != e ; ++ i ) if ( TypeName == specialTypes [ i ] ) return true ; return false ;"
LLVM,NVPTX,1120,"Predict the next statement of this code snippet:
 <s> const Type * Ty = arg -> getType ( ) ; const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( ! PTy ) return false ; if ( ! context ) return false ; const StructType * STy = dyn_cast < StructType > ( PTy -> getElementType ( ) ) ; const std :: string TypeName = STy ? STy -> getName ( ) : <STR_LIT> ; for ( int i = <NUM_LIT> , e = array_lengthof ( specialTypes ) ; i != e ; ++ i ) if ( TypeName == specialTypes [ i ] ) return true ; return false ;"
LLVM,NVPTX,1121,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) > <NUM_LIT> ) return ;"
LLVM,NVPTX,1122,"Predict the next statement of this code snippet:
 <s> if ( Constraint . length ( ) > <NUM_LIT> ) return ; else TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ;"
LLVM,NVPTX,1123,"Predict the next statement of this code snippet:
 <s> DebugLoc dl = Node -> getDebugLoc ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumOperands = Node -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { SDValue SubOp = Node -> getOperand ( i ) ; EVT VVT = SubOp . getNode ( ) -> getValueType ( <NUM_LIT> ) ; EVT EltVT = VVT . getVectorElementType ( ) ; unsigned NumSubElem = VVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumSubElem ; ++ j ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SubOp , DAG . getIntPtrConstant ( j ) ) ) ; } } return DAG . getNode ( <STR_LIT> , dl , Node -> getValueType ( <NUM_LIT> ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;"
LLVM,NVPTX,1124,"Predict the next statement of this code snippet:
 <s> EVT EltVT = VVT . getVectorElementType ( ) ; unsigned NumSubElem = VVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumSubElem ; ++ j ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SubOp , DAG . getIntPtrConstant ( j ) ) ) ;"
LLVM,NVPTX,1125,"Predict the next statement of this code snippet:
 <s> if ( isABI || isKernel ) { SDValue Arg = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) DAG . AssignOrdering ( p . getNode ( ) , idx + <NUM_LIT> ) ; if ( isKernel ) InVals . push_back ( p ) ; else { SDValue p2 = DAG . getNode ( <STR_LIT> , dl , ObjectVT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , p ) ; InVals . push_back ( p2 ) ; } } else { const PointerType * elemPtrType = dyn_cast < PointerType > ( argTypes [ i ] ) ; assert ( elemPtrType && <STR_LIT> ) ; Type * elemType = elemPtrType -> getElementType ( ) ; SmallVector < EVT , <NUM_LIT> > vtparts ; SmallVector < uint64_t , <NUM_LIT> > offsets ; ComputeValueVTs ( * this , elemType , vtparts , & offsets , <NUM_LIT> ) ; unsigned totalsize = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> , je = vtparts . size ( ) ; j != je ; ++ j ) totalsize += vtparts [ j ] . getStoreSizeInBits ( ) ; SDValue localcopy = DAG . getFrameIndex ( MF . getFrameInfo ( ) -> CreateStackObject ( totalsize / <NUM_LIT> , <NUM_LIT> , false ) , getPointerTy ( ) ) ; unsigned sizesofar = <NUM_LIT> ; std :: vector < SDValue > theChains ; for ( unsigned j = <NUM_LIT> , je = vtparts . size ( ) ; j != je ; ++ j ) { unsigned numElems = <NUM_LIT> ; if ( vtparts [ j ] . isVector ( ) ) numElems = vtparts [ j ] . getVectorNumElements ( ) ; for ( unsigned k = <NUM_LIT> , ke = numElems ; k != ke ; ++ k ) { EVT tmpvt = vtparts [ j ] ; if ( tmpvt . isVector ( ) ) tmpvt = tmpvt . getVectorElementType ( ) ; SDValue arg = DAG . getNode ( <STR_LIT> , dl , tmpvt , getParamSymbol ( DAG , idx , tmpvt ) ) ; SDValue addr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , localcopy , DAG . getConstant ( sizesofar , getPointerTy ( ) ) ) ; theChains . push_back ( DAG . getStore ( Chain , dl , arg , addr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; sizesofar += tmpvt . getStoreSizeInBits ( ) / <NUM_LIT> ; ++ idx ; }"
LLVM,NVPTX,1126,"Predict the next statement of this code snippet:
 <s> DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Op = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Op ) ;"
LLVM,NVPTX,1127,"Predict the next statement of this code snippet:
 <s> LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : case <STR_LIT> : return Op ;"
LLVM,NVPTX,1128,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : case <STR_LIT> : return Op ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,NVPTX,1129,"Predict the next statement of this code snippet:
 <s> if ( theValType . isVector ( ) ) tmpval = DAG . getNode ( <STR_LIT> , dl , theValType . getVectorElementType ( ) , tmpval , DAG . getIntPtrConstant ( j ) ) ; Chain = DAG . getNode ( isABI ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getConstant ( isABI ? sizesofar : idx , <STR_LIT> ) , tmpval ) ;"
LLVM,NVPTX,1130,"Predict the next statement of this code snippet:
 <s> if ( Op . getValueType ( ) == <STR_LIT> ) { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT MemVT = Load -> getMemoryVT ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , * Load -> getMemOperand ( ) ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( Op ) ) ; } }"
LLVM,NVPTX,1131,"Predict the next statement of this code snippet:
 <s> SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( Op ) ) ; } }"
LLVM,NVPTX,1132,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerSTORE ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; EVT VT = Store -> getMemoryVT ( ) ; if ( VT == <STR_LIT> ) return LowerSTOREi1 ( Op , DAG ) ; if ( VT == <STR_LIT> && ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , * Store -> getMemOperand ( ) ) ) return expandUnalignedStore ( Store , DAG ) ;"
LLVM,NVPTX,1133,"Predict the next statement of this code snippet:
 <s> if ( MF . getTarget ( ) . Options . UnsafeFPMath ) return true ; const Function & F = MF . getFunction ( ) ; return F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ;"
LLVM,NVPTX,1134,"Predict the next statement of this code snippet:
 <s> if ( MF . getTarget ( ) . Options . UnsafeFPMath ) return true ; const Function & F = MF . getFunction ( ) ;"
LLVM,NVPTX,1135,"Predict the next statement of this code snippet:
 <s> Align <ISA_LIT>TargetLowering :: getArgumentAlignment ( SDValue Callee , const CallBase * CB , Type * Ty , unsigned Idx , const DataLayout & DL ) const { if ( ! CB ) { return DL . getABITypeAlign ( Ty ) ; } unsigned Alignment = <NUM_LIT> ; const Function * DirectCallee = CB -> getCalledFunction ( ) ; if ( ! DirectCallee ) { if ( const auto * CI = dyn_cast < CallInst > ( CB ) ) { if ( getAlign ( * CI , Idx , Alignment ) ) return Align ( Alignment ) ; const Value * CalleeV = CI -> getCalledOperand ( ) ; while ( isa < ConstantExpr > ( CalleeV ) ) { const ConstantExpr * CE = cast < ConstantExpr > ( CalleeV ) ; if ( ! CE -> isCast ( ) ) break ; CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ; } if ( const auto * CalleeF = dyn_cast < Function > ( CalleeV ) ) DirectCallee = CalleeF ; }"
LLVM,NVPTX,1136,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( & CB ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getPointerElementType ( ) ; Align align = Outs [ OIdx ] . Flags . getNonZeroByValAlign ( ) ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align . value ( ) << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; }"
LLVM,NVPTX,1137,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( retTy ) ) { O << <STR_LIT> << PtrVT . getSizeInBits ( ) << <STR_LIT> ; } else if ( retTy -> isAggregateType ( ) || retTy -> isVectorTy ( ) || retTy -> isIntegerTy ( <NUM_LIT> ) ) { O << <STR_LIT> << ( retAlignment ? retAlignment -> value ( ) : <NUM_LIT> ) << <STR_LIT> << DL . getTypeAllocSize ( retTy ) << <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( & CB ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ;"
LLVM,NVPTX,1138,"Predict the next statement of this code snippet:
 <s> virtual bool isFMAFasterThanFMulAndFAdd ( EVT ) const { return true ;"
LLVM,NVPTX,1139,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,NVPTX,1140,"Predict the next statement of this code snippet:
 <s> static const char * const specialTypes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Type * Ty = arg -> getType ( ) ; auto * PTy = dyn_cast < PointerType > ( Ty ) ; if ( ! PTy ) return false ; if ( ! context ) return false ;"
LLVM,NVPTX,1141,"Predict the next statement of this code snippet:
 <s> static const char * const specialTypes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Type * Ty = arg -> getType ( ) ; auto * PTy = dyn_cast < PointerType > ( Ty ) ;"
LLVM,NVPTX,1142,"Predict the next statement of this code snippet:
 <s> static bool IsMulWideOperandDemotable ( SDValue Op , unsigned OptSize , OperandSignedness & S ) { S = Unknown ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) { EVT OrigVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OrigVT . getFixedSizeInBits ( ) <= OptSize ) {"
LLVM,NVPTX,1143,"Predict the next statement of this code snippet:
 <s> if ( ! isABI ) return Chain ; const DataLayout & DL = DAG . getDataLayout ( ) ; SmallVector < EVT , <NUM_LIT> > VTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputePTXValueVTs ( * this , DL , RetTy , VTs , & Offsets ) ; assert ( VTs . size ( ) == OutVals . size ( ) && <STR_LIT> ) ; auto VectorInfo = VectorizePTXValueVTs ( VTs , Offsets , RetTy -> isSized ( ) ? DL . getABITypeAlign ( RetTy ) : Align ( <NUM_LIT> ) ) ; bool ExtendIntegerRetVal = RetTy -> isIntegerTy ( ) && DL . getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > StoreOperands ; for ( unsigned i = <NUM_LIT> , e = VTs . size ( ) ; i != e ; ++ i ) { if ( VectorInfo [ i ] & PVF_FIRST ) { assert ( StoreOperands . empty ( ) && <STR_LIT> ) ; StoreOperands . push_back ( Chain ) ; StoreOperands . push_back ( DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) ) ; } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size ( ) - <NUM_LIT> ; switch ( NumElts ) {"
LLVM,NVPTX,1144,"Predict the next statement of this code snippet:
 <s> } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size ( ) - <NUM_LIT> ; switch ( NumElts ) { case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } EVT TheStoreType = ExtendIntegerRetVal ? <STR_LIT> : VTs [ i ] ; Chain = DAG . getMemIntrinsicNode ( Op , dl , DAG . getVTList ( <STR_LIT> ) , StoreOperands , TheStoreType , MachinePointerInfo ( ) , Align ( <NUM_LIT> ) , MachineMemOperand :: MOStore ) ; StoreOperands . clear ( ) ; } } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;"
LLVM,NVPTX,1145,"Predict the next statement of this code snippet:
 <s> int orderNo2 = N0 . getNode ( ) -> getIROrder ( ) ; if ( orderNo - orderNo2 < <NUM_LIT> ) return SDValue ( ) ; bool opIsLive = false ; const SDNode * left = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; const SDNode * right = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( isa < ConstantSDNode > ( left ) || isa < ConstantSDNode > ( right ) ) opIsLive = true ; if ( ! opIsLive ) for ( const SDNode * User : left -> uses ( ) ) { int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) { opIsLive = true ; break ; } } if ( ! opIsLive ) for ( const SDNode * User : right -> uses ( ) ) { int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) { opIsLive = true ; break ; } }"
LLVM,NVPTX,1146,"Predict the next statement of this code snippet:
 <s> if ( VT . isVector ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { assert ( VT . isInteger ( ) ) ; if ( OptLevel == CodeGenOpt :: None || VT != <STR_LIT> || ! N0 . getNode ( ) -> hasOneUse ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; } else if ( N0 . getOpcode ( ) == <STR_LIT> ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) { const auto * TLI = static_cast < const <ISA_LIT>TargetLowering * > ( & DAG . getTargetLoweringInfo ( ) ) ; if ( ! TLI -> allowFMA ( DAG . getMachineFunction ( ) , OptLevel ) ) return SDValue ( ) ; int numUses = <NUM_LIT> ; int nonAddCount = <NUM_LIT> ; for ( const SDNode * User : N0 . getNode ( ) -> uses ( ) ) { numUses ++ ; if ( User -> getOpcode ( ) != <STR_LIT> ) ++ nonAddCount ; } if ( numUses >= <NUM_LIT> ) return SDValue ( ) ; if ( nonAddCount ) { int orderNo = N -> getIROrder ( ) ; int orderNo2 = N0 . getNode ( ) -> getIROrder ( ) ; if ( orderNo - orderNo2 < <NUM_LIT> ) return SDValue ( ) ; bool opIsLive = false ; const SDNode * left = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; const SDNode * right = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( isa < ConstantSDNode > ( left ) || isa < ConstantSDNode > ( right ) ) opIsLive = true ; if ( ! opIsLive ) for ( const SDNode * User : left -> uses ( ) ) { int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) {"
LLVM,NVPTX,1147,"Predict the next statement of this code snippet:
 <s> LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } case <NUM_LIT> : { assert ( EltVT == <STR_LIT> && <STR_LIT> ) ; LoadF16x2 = true ; Opcode = <STR_LIT> ; EVT ListVTs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) , DL ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; if ( LoadF16x2 ) { NumElts /= <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue SubVector = NewLD . getValue ( i ) ; SDValue E0 = DAG . getNode ( <STR_LIT> , DL , EltVT , SubVector , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue E1 = DAG . getNode ( <STR_LIT> , DL , EltVT , SubVector , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; ScalarRes . push_back ( E0 ) ; ScalarRes . push_back ( E1 ) ; }"
LLVM,NVPTX,1148,"Predict the next statement of this code snippet:
 <s> static bool AreMulWideOperandsDemotable ( SDValue LHS , SDValue RHS , unsigned OptSize , bool & IsSigned ) { OperandSignedness LHSSign ; if ( ! IsMulWideOperandDemotable ( LHS , OptSize , LHSSign ) ) return false ; if ( LHSSign == Unknown ) return false ; IsSigned = ( LHSSign == Signed ) ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( RHS ) ) { APInt Val = CI -> getAPIntValue ( ) ; if ( LHSSign == Unsigned ) { if ( Val . isIntN ( OptSize ) ) { return true ;"
LLVM,NVPTX,1149,"Predict the next statement of this code snippet:
 <s> SmallVector < EVT , <NUM_LIT> > TempVTs ; SmallVector < uint64_t , <NUM_LIT> > TempOffsets ; ComputeValueVTs ( TLI , Ty , TempVTs , & TempOffsets , StartingOffset ) ; for ( unsigned i = <NUM_LIT> , e = TempVTs . size ( ) ; i != e ; ++ i ) {"
LLVM,NVPTX,1150,"Predict the next statement of this code snippet:
 <s> if ( llvm :: getAlign ( * cast < CallInst > ( CalleeI ) , Idx , Align ) ) return Align ; const Value * CalleeV = cast < CallInst > ( CalleeI ) -> getCalledValue ( ) ; while ( isa < ConstantExpr > ( CalleeV ) ) { const ConstantExpr * CE = cast < ConstantExpr > ( CalleeV ) ; if ( ! CE -> isCast ( ) ) break ; CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ; } if ( isa < Function > ( CalleeV ) ) DirectCallee = CalleeV ;"
LLVM,NVPTX,1151,"Predict the next statement of this code snippet:
 <s> if ( llvm :: getAlign ( * cast < CallInst > ( CalleeI ) , Idx , Align ) ) return Align ; const Value * CalleeV = cast < CallInst > ( CalleeI ) -> getCalledValue ( ) ; while ( isa < ConstantExpr > ( CalleeV ) ) { const ConstantExpr * CE = cast < ConstantExpr > ( CalleeV ) ; if ( ! CE -> isCast ( ) ) break ; CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ; } if ( isa < Function > ( CalleeV ) ) DirectCallee = CalleeV ; } } if ( DirectCallee ) if ( llvm :: getAlign ( * cast < Function > ( DirectCallee ) , Idx , Align ) ) return Align ; return TD -> getABITypeAlignment ( Ty ) ;"
LLVM,NVPTX,1152,"Predict the next statement of this code snippet:
 <s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'b' : case 'r' : case 'h' : case 'c' : case 'l' : case 'f' : case 'd' : case '0' : case 'N' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ;"
LLVM,NVPTX,1153,"Predict the next statement of this code snippet:
 <s> case 'b' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'c' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : case 'N' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,NVPTX,1154,"Predict the next statement of this code snippet:
 <s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1155,"Predict the next statement of this code snippet:
 <s> if ( VT . isVector ( ) ) return EVT :: getVectorVT ( Ctx , <STR_LIT> , VT . getVectorNumElements ( ) ) ;"
LLVM,NVPTX,1156,"Predict the next statement of this code snippet:
 <s> if ( VT . isVector ( ) ) return EVT :: getVectorVT ( Ctx , <STR_LIT> , VT . getVectorNumElements ( ) ) ;"
LLVM,NVPTX,1157,"Predict the next statement of this code snippet:
 <s> bool llvm :: isImageOrSamplerVal ( const Value * arg , const Module * context ) { static const char * const specialTypes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const Type * Ty = arg -> getType ( ) ; const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( ! PTy ) return false ; if ( ! context ) return false ; const StructType * STy = dyn_cast < StructType > ( PTy -> getElementType ( ) ) ;"
LLVM,NVPTX,1158,"Predict the next statement of this code snippet:
 <s> const std :: string TypeName = STy && ! STy -> isLiteral ( ) ? STy -> getName ( ) : <STR_LIT> ;"
LLVM,NVPTX,1159,"Predict the next statement of this code snippet:
 <s> } switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ;"
LLVM,NVPTX,1160,"Predict the next statement of this code snippet:
 <s> static bool IsMulWideOperandDemotable ( SDValue Op , unsigned OptSize , OperandSignedness & S ) { S = Unknown ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) { EVT OrigVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OrigVT . getSizeInBits ( ) == OptSize ) { S = Signed ; return true ; } } else if ( Op . getOpcode ( ) == <STR_LIT> ) { EVT OrigVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OrigVT . getSizeInBits ( ) == OptSize ) { S = Unsigned ;"
LLVM,NVPTX,1161,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) const { SDNode * Node = Op . getNode ( ) ; SDLoc dl ( Node ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumOperands = Node -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) {"
LLVM,NVPTX,1162,"Predict the next statement of this code snippet:
 <s> SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Op = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) ) ;"
LLVM,NVPTX,1163,"Predict the next statement of this code snippet:
 <s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Op = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) ) ;"
LLVM,NVPTX,1164,"Predict the next statement of this code snippet:
 <s> Ops . push_back ( DAG . getConstant ( Offset , <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ; EVT ExtendedVT = ( NeedExtend ) ? <STR_LIT> : OutVals [ <NUM_LIT> ] . getValueType ( ) ; StoreVal = OutVals [ i ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( VecSize == <NUM_LIT> ) { Opc = <STR_LIT> ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; } Chain = DAG . getMemIntrinsicNode ( Opc , dl , DAG . getVTList ( <STR_LIT> ) , Ops , EltVT , MachinePointerInfo ( ) ) ; Offset += PerStoreOffset ; } } } else { SmallVector < EVT , <NUM_LIT> > ValVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputePTXValueVTs ( * this , RetTy , ValVTs , & Offsets , <NUM_LIT> ) ; assert ( ValVTs . size ( ) == OutVals . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { SDValue theVal = OutVals [ i ] ; EVT TheValType = theVal . getValueType ( ) ; unsigned numElems = <NUM_LIT> ; if ( TheValType . isVector ( ) ) numElems = TheValType . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> , je = numElems ; j != je ; ++ j ) { SDValue TmpVal = theVal ; if ( TheValType . isVector ( ) ) TmpVal = DAG . getNode ( <STR_LIT> , dl , TheValType . getVectorElementType ( ) , TmpVal , DAG . getIntPtrConstant ( j ) ) ; EVT TheStoreType = ValVTs [ i ] ; if ( RetTy -> isIntegerTy ( ) && TD -> getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ) { TmpVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TmpVal ) ; TheStoreType = <STR_LIT> ; }"
LLVM,NVPTX,1165,"Predict the next statement of this code snippet:
 <s> unsigned VTBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; if ( VTBits == <NUM_LIT> && nvptxSubtarget . getSmVersion ( ) >= <NUM_LIT> ) { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ; } else { SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue Cmp = DAG . getSetCC ( dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , Cmp , TrueVal , FalseVal ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ;"
LLVM,NVPTX,1166,"Predict the next statement of this code snippet:
 <s> unsigned VTBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; if ( VTBits == <NUM_LIT> && nvptxSubtarget . getSmVersion ( ) >= <NUM_LIT> ) { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ; } else { SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ;"
LLVM,NVPTX,1167,"Predict the next statement of this code snippet:
 <s> SDLoc dl ( Op ) ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( VTBits == <NUM_LIT> && nvptxSubtarget . getSmVersion ( ) >= <NUM_LIT> ) { SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ; } else { SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ;"
LLVM,NVPTX,1168,"Predict the next statement of this code snippet:
 <s> EVT VT = Op . getValueType ( ) ; unsigned VTBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( VTBits == <NUM_LIT> && nvptxSubtarget . getSmVersion ( ) >= <NUM_LIT> ) { SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ; } else { SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue Cmp = DAG . getSetCC ( dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ;"
LLVM,NVPTX,1169,"Predict the next statement of this code snippet:
 <s> return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) {"
LLVM,NVPTX,1170,"Predict the next statement of this code snippet:
 <s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; OtherOps . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ; } SDValue LoadChain = NewLD . getValue ( NumElts ) ; SDValue BuildVec = DAG . getNode ( <STR_LIT> , DL , ResVT , ScalarRes ) ; Results . push_back ( BuildVec ) ; Results . push_back ( LoadChain ) ; } else { assert ( ResVT . isSimple ( ) && ResVT . getSimpleVT ( ) . SimpleTy == <STR_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ; SDVTList LdResVTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , LdResVTs , Ops , <STR_LIT> , MemSD -> getMemOperand ( ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewLD . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( NewLD . getValue ( <NUM_LIT> ) ) ; }"
LLVM,NVPTX,1171,"Predict the next statement of this code snippet:
 <s> SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ; }"
LLVM,NVPTX,1172,"Predict the next statement of this code snippet:
 <s> if ( MulType != <STR_LIT> && MulType != <STR_LIT> ) { return SDValue ( ) ; } unsigned OptSize = MulType . getSizeInBits ( ) >> <NUM_LIT> ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) { if ( isa < ConstantSDNode > ( LHS ) ) { std :: swap ( LHS , RHS ) ; } } if ( N -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * ShlRHS = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! ShlRHS ) { return SDValue ( ) ;"
LLVM,NVPTX,1173,"Predict the next statement of this code snippet:
 <s> } bool Signed ; if ( ! AreMulWideOperandsDemotable ( LHS , RHS , OptSize , Signed ) ) { return SDValue ( ) ; } EVT DemotedVT ; if ( MulType == <STR_LIT> ) { DemotedVT = <STR_LIT> ; } else { DemotedVT = <STR_LIT> ; } SDValue TruncLHS = DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DemotedVT , LHS ) ; SDValue TruncRHS = DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DemotedVT , RHS ) ; unsigned Opc ; if ( Signed ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } return DCI . DAG . getNode ( Opc , SDLoc ( N ) , MulType , TruncLHS , TruncRHS ) ;"
LLVM,NVPTX,1174,"Predict the next statement of this code snippet:
 <s> delete StaticDtorSection ; delete LSDASection ; delete EHFrameSection ; delete DwarfAbbrevSection ; delete DwarfInfoSection ; delete DwarfLineSection ; delete DwarfFrameSection ; delete DwarfPubTypesSection ;"
LLVM,NVPTX,1175,"Predict the next statement of this code snippet:
 <s> delete DwarfAbbrevSection ; delete DwarfInfoSection ; delete DwarfLineSection ; delete DwarfFrameSection ; delete DwarfPubTypesSection ; delete DwarfDebugInlineSection ; delete DwarfStrSection ;"
LLVM,NVPTX,1176,"Predict the next statement of this code snippet:
 <s> SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = PtrVT . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; unsigned align = Outs [ OIdx ] . Flags . getByValAlign ( ) ;"
LLVM,NVPTX,1177,"Predict the next statement of this code snippet:
 <s> if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = PtrVT . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ;"
LLVM,NVPTX,1178,"Predict the next statement of this code snippet:
 <s> return PerformSHLCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformREMCombine ( N , DCI , OptLevel ) ;"
LLVM,NVPTX,1179,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformSHLCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DCI ) ; case <STR_LIT> :"
LLVM,NVPTX,1180,"Predict the next statement of this code snippet:
 <s> static void ReplaceLoadVector ( SDNode * N , SelectionDAG & DAG , SmallVectorImpl < SDValue > & Results ) { EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; assert ( ResVT . isVector ( ) && <STR_LIT> ) ; assert ( ResVT . isSimple ( ) && <STR_LIT> ) ; switch ( ResVT . getSimpleVT ( ) . SimpleTy ) { default : return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } LoadSDNode * LD = cast < LoadSDNode > ( N ) ; unsigned Align = LD -> getAlignment ( ) ; auto & TD = DAG . getDataLayout ( ) ; unsigned PrefAlign = TD . getPrefTypeAlignment ( ResVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) {"
LLVM,NVPTX,1181,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : break ; } LoadSDNode * LD = cast < LoadSDNode > ( N ) ; unsigned Align = LD -> getAlignment ( ) ; auto & TD = DAG . getDataLayout ( ) ; unsigned PrefAlign = TD . getPrefTypeAlignment ( ResVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) , DL ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) {"
LLVM,NVPTX,1182,"Predict the next statement of this code snippet:
 <s> return AtomicExpansionKind :: None ;"
LLVM,NVPTX,1183,"Predict the next statement of this code snippet:
 <s> return AtomicExpansionKind :: None ;"
LLVM,NVPTX,1184,"Predict the next statement of this code snippet:
 <s> return AtomicExpansionKind :: None ;"
LLVM,NVPTX,1185,"Predict the next statement of this code snippet:
 <s> uint64_t Off = TempOffsets [ i ] ; if ( VT . isVector ( ) ) for ( unsigned j = <NUM_LIT> , je = VT . getVectorNumElements ( ) ; j != je ; ++ j ) { ValueVTs . push_back ( VT . getVectorElementType ( ) ) ; if ( Offsets ) Offsets -> push_back ( Off + j * VT . getVectorElementType ( ) . getStoreSize ( ) ) ; } else { ValueVTs . push_back ( VT ) ; if ( Offsets ) Offsets -> push_back ( Off ) ;"
LLVM,NVPTX,1186,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = TempVTs . size ( ) ; i != e ; ++ i ) { EVT VT = TempVTs [ i ] ; uint64_t Off = TempOffsets [ i ] ; if ( VT . isVector ( ) ) for ( unsigned j = <NUM_LIT> , je = VT . getVectorNumElements ( ) ; j != je ; ++ j ) { ValueVTs . push_back ( VT . getVectorElementType ( ) ) ;"
LLVM,NVPTX,1187,"Predict the next statement of this code snippet:
 <s> const DataLayout * TD = getDataLayout ( ) ; unsigned align = <NUM_LIT> ; GlobalAddressSDNode * Func = dyn_cast < GlobalAddressSDNode > ( Callee . getNode ( ) ) ; if ( Func ) { assert ( CS -> getCalledFunction ( ) && <STR_LIT> ) ; if ( ! llvm :: getAlign ( * ( CS -> getCalledFunction ( ) ) , Idx , align ) ) align = TD -> getABITypeAlignment ( Ty ) ; }"
LLVM,NVPTX,1188,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> << uniqueCallSite << <STR_LIT> ; if ( retTy -> getTypeID ( ) == Type :: VoidTyID ) { O << <STR_LIT> ; } else { O << <STR_LIT> ; if ( retTy -> isPrimitiveType ( ) || retTy -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( const IntegerType * ITy = dyn_cast < IntegerType > ( retTy ) ) { size = ITy -> getBitWidth ( ) ; if ( size < <NUM_LIT> ) size = <NUM_LIT> ; } else { assert ( retTy -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = retTy -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( retTy ) ) { O << <STR_LIT> << getPointerTy ( ) . getSizeInBits ( ) << <STR_LIT> ; } else { if ( ( retTy -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( retTy ) ) { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , retTy , vtparts ) ; unsigned totalsz = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; totalsz += sz / <NUM_LIT> ; } } O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ;"
LLVM,NVPTX,1189,"Predict the next statement of this code snippet:
 <s> MVT thePointerTy = getPointerTy ( ) ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( Outs [ OIdx ] . Flags . isByVal ( ) == false ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; const DataLayout * TD = getDataLayout ( ) ; if ( ! llvm :: getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = TD -> getABITypeAlignment ( Ty ) ; unsigned sz = TD -> getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( Ty ) == Outs [ OIdx ] . VT || ( getValueType ( Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ;"
LLVM,NVPTX,1190,"Predict the next statement of this code snippet:
 <s> case 'c' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : case 'N' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' :"
LLVM,NVPTX,1191,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,NVPTX,1192,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { default : return false ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = true ; Info . align = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = true ; Info . align = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; if ( Intrinsic == <STR_LIT> ) Info . memVT = getValueType ( I . getType ( ) ) ; else if ( Intrinsic == <STR_LIT> ) Info . memVT = getValueType ( I . getType ( ) ) ; else Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ;"
LLVM,NVPTX,1193,"Predict the next statement of this code snippet:
 <s> SDNode * Node = Op . getNode ( ) ; SDLoc dl ( Node ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumOperands = Node -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { SDValue SubOp = Node -> getOperand ( i ) ; EVT VVT = SubOp . getNode ( ) -> getValueType ( <NUM_LIT> ) ; EVT EltVT = VVT . getVectorElementType ( ) ; unsigned NumSubElem = VVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumSubElem ; ++ j ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SubOp , DAG . getIntPtrConstant ( j ) ) ) ; } } return DAG . getNode ( <STR_LIT> , dl , Node -> getValueType ( <NUM_LIT> ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;"
LLVM,NVPTX,1194,"Predict the next statement of this code snippet:
 <s> SDNode * Node = Op . getNode ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( Node ) ; SDLoc dl ( Node ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , newLD ) ;"
LLVM,NVPTX,1195,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerLOADi1 ( SDValue Op , SelectionDAG & DAG ) const { SDNode * Node = Op . getNode ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( Node ) ; SDLoc dl ( Node ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , newLD ) ;"
LLVM,NVPTX,1196,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,1197,"Predict the next statement of this code snippet:
 <s> return SDValue ( ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : case <STR_LIT> : return Op ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ;"
LLVM,NVPTX,1198,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue ExtVal = DAG . getNode ( <STR_LIT> , DL , EltVT , Val , DAG . getIntPtrConstant ( i ) ) ; if ( NeedExt ) ExtVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ExtVal ) ;"
LLVM,NVPTX,1199,"Predict the next statement of this code snippet:
 <s> default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue ExtVal = DAG . getNode ( <STR_LIT> , DL , EltVT , Val , DAG . getIntPtrConstant ( i ) ) ; if ( NeedExt ) ExtVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ExtVal ) ; Ops . push_back ( ExtVal ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } MemSDNode * MemSD = cast < MemSDNode > ( N ) ; SDValue NewSt = DAG . getMemIntrinsicNode ( Opcode , DL , DAG . getVTList ( <STR_LIT> ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; return NewSt ; } return SDValue ( ) ;"
LLVM,NVPTX,1200,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs , <NUM_LIT> ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; OtherOps . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , & OtherOps [ <NUM_LIT> ] , OtherOps . size ( ) , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ;"
LLVM,NVPTX,1201,"Predict the next statement of this code snippet:
 <s> assert ( ResVT . isSimple ( ) && <STR_LIT> ) ; switch ( ResVT . getSimpleVT ( ) . SimpleTy ) { default : return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs , <NUM_LIT> ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ;"
LLVM,NVPTX,1202,"Predict the next statement of this code snippet:
 <s> unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs , <NUM_LIT> ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , & OtherOps [ <NUM_LIT> ] , OtherOps . size ( ) , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ;"
LLVM,NVPTX,1203,"Predict the next statement of this code snippet:
 <s> return VT == <STR_LIT> ;"
LLVM,NVPTX,1204,"Predict the next statement of this code snippet:
 <s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const {"
LLVM,NVPTX,1205,"Predict the next statement of this code snippet:
 <s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const {"
LLVM,NVPTX,1206,"Predict the next statement of this code snippet:
 <s> virtual EVT getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( VT . isVector ( ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; return <STR_LIT> ;"
LLVM,NVPTX,1207,"Predict the next statement of this code snippet:
 <s> if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; } Chain = DAG . getMemIntrinsicNode ( Opc , dl , DAG . getVTList ( <STR_LIT> ) , Ops , EltVT , MachinePointerInfo ( ) ) ; Offset += PerStoreOffset ; } } } else { SmallVector < EVT , <NUM_LIT> > ValVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputePTXValueVTs ( * this , RetTy , ValVTs , & Offsets , <NUM_LIT> ) ; assert ( ValVTs . size ( ) == OutVals . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { SDValue theVal = OutVals [ i ] ; EVT TheValType = theVal . getValueType ( ) ; unsigned numElems = <NUM_LIT> ; if ( TheValType . isVector ( ) ) numElems = TheValType . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> , je = numElems ; j != je ; ++ j ) { SDValue TmpVal = theVal ; if ( TheValType . isVector ( ) ) TmpVal = DAG . getNode ( <STR_LIT> , dl , TheValType . getVectorElementType ( ) , TmpVal , DAG . getIntPtrConstant ( j ) ) ; EVT TheStoreType = ValVTs [ i ] ; if ( RetTy -> isIntegerTy ( ) && TD -> getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ) { TmpVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TmpVal ) ; TheStoreType = <STR_LIT> ; } else if ( TmpVal . getValueType ( ) . getSizeInBits ( ) < <NUM_LIT> ) TmpVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TmpVal ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( Offsets [ i ] , <STR_LIT> ) , TmpVal } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , TheStoreType , MachinePointerInfo ( ) ) ; }"
LLVM,NVPTX,1208,"Predict the next statement of this code snippet:
 <s> else { SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue Cmp = DAG . getSetCC ( dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) , <STR_LIT> ) ;"
LLVM,NVPTX,1209,"Predict the next statement of this code snippet:
 <s> assert ( Op . getOpcode ( ) == <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; unsigned VTBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; if ( VTBits == <NUM_LIT> && STI . getSmVersion ( ) >= <NUM_LIT> ) { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ;"
LLVM,NVPTX,1210,"Predict the next statement of this code snippet:
 <s> break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue ExtVal = DAG . getNode ( <STR_LIT> , DL , EltVT , Val , DAG . getIntPtrConstant ( i ) ) ; if ( NeedExt ) ExtVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ExtVal ) ; Ops . push_back ( ExtVal ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } SDValue NewSt = DAG . getMemIntrinsicNode ( Opcode , DL , DAG . getVTList ( <STR_LIT> ) , Ops , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; return NewSt ; }"
LLVM,NVPTX,1211,"Predict the next statement of this code snippet:
 <s> if ( ! ValVT . isSimple ( ) ) return SDValue ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } MemSDNode * MemSD = cast < MemSDNode > ( N ) ; const DataLayout * TD = getDataLayout ( ) ; unsigned Align = MemSD -> getAlignment ( ) ; unsigned PrefAlign = TD -> getPrefTypeAlignment ( ValVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return SDValue ( ) ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue ExtVal = DAG . getNode ( <STR_LIT> , DL , EltVT , Val , DAG . getIntPtrConstant ( i ) ) ; if ( NeedExt ) ExtVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ExtVal ) ; Ops . push_back ( ExtVal ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ;"
LLVM,NVPTX,1212,"Predict the next statement of this code snippet:
 <s> int nonAddCount = <NUM_LIT> ; for ( SDNode :: use_iterator UI = N0 . getNode ( ) -> use_begin ( ) , UE = N0 . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { numUses ++ ; SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> ) ++ nonAddCount ; } if ( numUses >= <NUM_LIT> ) return SDValue ( ) ; if ( nonAddCount ) { int orderNo = N -> getIROrder ( ) ; int orderNo2 = N0 . getNode ( ) -> getIROrder ( ) ; if ( orderNo - orderNo2 < <NUM_LIT> ) return SDValue ( ) ; bool opIsLive = false ; const SDNode * left = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; const SDNode * right = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( dyn_cast < ConstantSDNode > ( left ) || dyn_cast < ConstantSDNode > ( right ) ) opIsLive = true ; if ( ! opIsLive ) for ( SDNode :: use_iterator UI = left -> use_begin ( ) , UE = left -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) { opIsLive = true ; break ; } } if ( ! opIsLive ) for ( SDNode :: use_iterator UI = right -> use_begin ( ) , UE = right -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) { opIsLive = true ; break ; } } if ( ! opIsLive ) return SDValue ( ) ; } return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; } } return SDValue ( ) ;"
LLVM,NVPTX,1213,"Predict the next statement of this code snippet:
 <s> return PerformMULCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformSHLCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; } return SDValue ( ) ;"
LLVM,NVPTX,1214,"Predict the next statement of this code snippet:
 <s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : return PerformADDCombine ( N , DCI , STI , OptLevel ) ;"
LLVM,NVPTX,1215,"Predict the next statement of this code snippet:
 <s> break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ; } SDValue LoadChain = NewLD . getValue ( NumElts ) ; SDValue BuildVec = DAG . getNode ( <STR_LIT> , DL , ResVT , ScalarRes ) ; Results . push_back ( BuildVec ) ; Results . push_back ( LoadChain ) ;"
LLVM,NVPTX,1216,"Predict the next statement of this code snippet:
 <s> } first = false ; if ( Outs [ OIdx ] . Flags . isByVal ( ) == false ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; const DataLayout * TD = getDataLayout ( ) ; if ( ! llvm :: getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = TD -> getABITypeAlignment ( Ty ) ; unsigned sz = TD -> getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( Ty ) == Outs [ OIdx ] . VT || ( getValueType ( Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; unsigned align = Outs [ OIdx ] . Flags . getByValAlign ( ) ; unsigned sz = getDataLayout ( ) -> getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ;"
LLVM,NVPTX,1217,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,NVPTX,1218,"Predict the next statement of this code snippet:
 <s> first = false ; if ( Outs [ i ] . Flags . isByVal ( ) == false ) { unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI ) { unsigned align = Outs [ i ] . Flags . getByValAlign ( ) ; unsigned sz = getTargetData ( ) -> getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , ETy , vtparts ) ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; }"
LLVM,NVPTX,1219,"Predict the next statement of this code snippet:
 <s> if ( ( retTy -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( retTy ) ) { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , retTy , vtparts ) ; unsigned totalsz = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; totalsz += sz / <NUM_LIT> ; } } O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else { assert ( false && <STR_LIT> ) ; } } } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , retTy , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ idx ; } if ( i < e - <NUM_LIT> ) O << <STR_LIT> ; } } O << <STR_LIT> ;"
LLVM,NVPTX,1220,"Predict the next statement of this code snippet:
 <s> virtual EVT getSetCCResultType ( EVT VT ) const {"
LLVM,NVPTX,1221,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { bool isABI = ( nvptxSubtarget . getSmVersion ( ) >= <NUM_LIT> ) ; unsigned sizesofar = <NUM_LIT> ; unsigned idx = <NUM_LIT> ;"
LLVM,NVPTX,1222,"Predict the next statement of this code snippet:
 <s> EVT theValType = theVal . getValueType ( ) ; unsigned numElems = <NUM_LIT> ; if ( theValType . isVector ( ) ) numElems = theValType . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> , je = numElems ; j != je ; ++ j ) { SDValue tmpval = theVal ;"
LLVM,NVPTX,1223,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> << uniqueCallSite << <STR_LIT> ; if ( retTy -> getTypeID ( ) == Type :: VoidTyID ) { O << <STR_LIT> ; } else { O << <STR_LIT> ; if ( retTy -> isFloatingPointTy ( ) || ( retTy -> isIntegerTy ( ) && ! retTy -> isIntegerTy ( <NUM_LIT> ) ) ) { unsigned size = <NUM_LIT> ; if ( auto * ITy = dyn_cast < IntegerType > ( retTy ) ) { size = ITy -> getBitWidth ( ) ; } else { assert ( retTy -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = retTy -> getPrimitiveSizeInBits ( ) ; } if ( size < <NUM_LIT> ) size = <NUM_LIT> ; O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( retTy ) ) { O << <STR_LIT> << PtrVT . getSizeInBits ( ) << <STR_LIT> ; } else if ( retTy -> isAggregateType ( ) || retTy -> isVectorTy ( ) || retTy -> isIntegerTy ( <NUM_LIT> ) ) { O << <STR_LIT> << ( retAlignment ? retAlignment -> value ( ) : <NUM_LIT> ) << <STR_LIT> << DL . getTypeAllocSize ( retTy ) << <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) {"
LLVM,NVPTX,1224,"Predict the next statement of this code snippet:
 <s> } else if ( NumElts == <NUM_LIT> ) { SDValue StoreVal0 = OutVals [ <NUM_LIT> ] ; SDValue StoreVal1 = OutVals [ <NUM_LIT> ] ; if ( NeedExtend ) { StoreVal0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreVal0 ) ; StoreVal1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreVal1 ) ; } SDValue Ops [ ] = { Chain , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , StoreVal0 , StoreVal1 } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , EltVT , MachinePointerInfo ( ) ) ; } else { unsigned VecSize = <NUM_LIT> ; if ( OutVals [ <NUM_LIT> ] . getValueSizeInBits ( ) == <NUM_LIT> ) VecSize = <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; EVT VecVT = EVT :: getVectorVT ( F -> getContext ( ) , EltVT , VecSize ) ; unsigned PerStoreOffset = TD . getTypeAllocSize ( VecVT . getTypeForEVT ( F -> getContext ( ) ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += VecSize ) { SDValue StoreVal ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getConstant ( Offset , dl , <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ; EVT ExtendedVT = ( NeedExtend ) ? <STR_LIT> : OutVals [ <NUM_LIT> ] . getValueType ( ) ; StoreVal = OutVals [ i ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( VecSize == <NUM_LIT> ) { Opc = <STR_LIT> ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; } Chain = DAG . getMemIntrinsicNode ( Opc , dl , DAG . getVTList ( <STR_LIT> ) , Ops , EltVT , MachinePointerInfo ( ) ) ; Offset += PerStoreOffset ; } }"
LLVM,NVPTX,1225,"Predict the next statement of this code snippet:
 <s> switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return LowerSTOREi1 ( Op , DAG ) ; default :"
LLVM,NVPTX,1226,"Predict the next statement of this code snippet:
 <s> EVT ValVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return LowerSTOREi1 ( Op , DAG ) ; default :"
LLVM,NVPTX,1227,"Predict the next statement of this code snippet:
 <s> CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformSHLCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformREMCombine ( N , DCI , OptLevel ) ;"
LLVM,NVPTX,1228,"Predict the next statement of this code snippet:
 <s> unsigned getInlineAsmMemConstraint ( const std :: string & ConstraintCode ) const override {"
LLVM,NVPTX,1229,"Predict the next statement of this code snippet:
 <s> int orderNo = N -> getIROrder ( ) ; int orderNo2 = N0 . getNode ( ) -> getIROrder ( ) ; if ( orderNo - orderNo2 < <NUM_LIT> ) return SDValue ( ) ; bool opIsLive = false ; const SDNode * left = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; const SDNode * right = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( dyn_cast < ConstantSDNode > ( left ) || dyn_cast < ConstantSDNode > ( right ) ) opIsLive = true ; if ( ! opIsLive ) for ( SDNode :: use_iterator UI = left -> use_begin ( ) , UE = left -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) { opIsLive = true ; break ; } } if ( ! opIsLive ) for ( SDNode :: use_iterator UI = right -> use_begin ( ) , UE = right -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) {"
LLVM,NVPTX,1230,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : return PerformADDCombine ( N , DCI , nvptxSubtarget , OptLevel ) ;"
LLVM,NVPTX,1231,"Predict the next statement of this code snippet:
 <s> const Type * Ty = arg -> getType ( ) ; const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( ! PTy ) return false ; if ( ! context ) return false ; const StructType * STy = dyn_cast < StructType > ( PTy -> getElementType ( ) ) ; const std :: string TypeName = STy && ! STy -> isLiteral ( ) ? STy -> getName ( ) : <STR_LIT> ; for ( int i = <NUM_LIT> , e = array_lengthof ( specialTypes ) ; i != e ; ++ i ) if ( TypeName == specialTypes [ i ] ) return true ;"
LLVM,NVPTX,1232,"Predict the next statement of this code snippet:
 <s> static const char * const specialTypes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const Type * Ty = arg -> getType ( ) ; const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( ! PTy ) return false ;"
LLVM,NVPTX,1233,"Predict the next statement of this code snippet:
 <s> continue ; } if ( PAL . hasAttribute ( i + <NUM_LIT> , Attribute :: ByVal ) == false ) { if ( isABI || isKernel ) { SDValue Arg = getParamSymbol ( DAG , idx ) ; Value * srcValue = new Argument ( PointerType :: get ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) , llvm :: ADDRESS_SPACE_PARAM ) ) ; SDValue p = DAG . getLoad ( ObjectVT , dl , Root , Arg , MachinePointerInfo ( srcValue ) , false , false , false , TD -> getABITypeAlignment ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) ) ) ; if ( p . getNode ( ) ) DAG . AssignOrdering ( p . getNode ( ) , idx + <NUM_LIT> ) ; InVals . push_back ( p ) ; } else { SDValue Arg = getParamSymbol ( DAG , idx , ObjectVT ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) DAG . AssignOrdering ( p . getNode ( ) , idx + <NUM_LIT> ) ; InVals . push_back ( p ) ; } continue ; } if ( isABI || isKernel ) { SDValue Arg = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) DAG . AssignOrdering ( p . getNode ( ) , idx + <NUM_LIT> ) ; if ( isKernel ) InVals . push_back ( p ) ; else { SDValue p2 = DAG . getNode ( <STR_LIT> , dl , ObjectVT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , p ) ; InVals . push_back ( p2 ) ; } } else { const PointerType * elemPtrType = dyn_cast < PointerType > ( argTypes [ i ] ) ; assert ( elemPtrType && <STR_LIT> ) ; Type * elemType = elemPtrType -> getElementType ( ) ; SmallVector < EVT , <NUM_LIT> > vtparts ; SmallVector < uint64_t , <NUM_LIT> > offsets ; ComputeValueVTs ( * this , elemType , vtparts , & offsets , <NUM_LIT> ) ; unsigned totalsize = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> , je = vtparts . size ( ) ; j != je ; ++ j ) totalsize += vtparts [ j ] . getStoreSizeInBits ( ) ; SDValue localcopy = DAG . getFrameIndex ( MF . getFrameInfo ( ) -> CreateStackObject ( totalsize / <NUM_LIT> , <NUM_LIT> , false ) , getPointerTy ( ) ) ; unsigned sizesofar = <NUM_LIT> ; std :: vector < SDValue > theChains ;"
LLVM,NVPTX,1234,"Predict the next statement of this code snippet:
 <s> assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , newLD ) ; SDValue Ops [ ] = { result , LD -> getChain ( ) } ;"
LLVM,NVPTX,1235,"Predict the next statement of this code snippet:
 <s> DebugLoc dl = Node -> getDebugLoc ( ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ;"
LLVM,NVPTX,1236,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : case <STR_LIT> : return Op ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,1237,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerSTORE ( SDValue Op , SelectionDAG & DAG ) const { SDNode * Node = Op . getNode ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; StoreSDNode * ST = cast < StoreSDNode > ( Node ) ; SDValue Tmp1 = ST -> getChain ( ) ; SDValue Tmp2 = ST -> getBasePtr ( ) ; SDValue Tmp3 = ST -> getValue ( ) ; assert ( Tmp3 . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned Alignment = ST -> getAlignment ( ) ; bool isVolatile = ST -> isVolatile ( ) ;"
LLVM,NVPTX,1238,"Predict the next statement of this code snippet:
 <s> unsigned Alignment = <NUM_LIT> ; const Function * DirectCallee = CB -> getCalledFunction ( ) ; if ( ! DirectCallee ) { if ( const auto * CI = dyn_cast < CallInst > ( CB ) ) { if ( getAlign ( * CI , Idx , Alignment ) ) return Align ( Alignment ) ; const Value * CalleeV = CI -> getCalledOperand ( ) ; while ( isa < ConstantExpr > ( CalleeV ) ) { const ConstantExpr * CE = cast < ConstantExpr > ( CalleeV ) ; if ( ! CE -> isCast ( ) ) break ; CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ; } if ( const auto * CalleeF = dyn_cast < Function > ( CalleeV ) ) DirectCallee = CalleeF ;"
LLVM,NVPTX,1239,"Predict the next statement of this code snippet:
 <s> unsigned Alignment = <NUM_LIT> ; const Function * DirectCallee = CB -> getCalledFunction ( ) ; if ( ! DirectCallee ) { if ( const auto * CI = dyn_cast < CallInst > ( CB ) ) { if ( getAlign ( * CI , Idx , Alignment ) ) return Align ( Alignment ) ; const Value * CalleeV = CI -> getCalledOperand ( ) ; while ( isa < ConstantExpr > ( CalleeV ) ) { const ConstantExpr * CE = cast < ConstantExpr > ( CalleeV ) ; if ( ! CE -> isCast ( ) ) break ; CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ; } if ( const auto * CalleeF = dyn_cast < Function > ( CalleeV ) ) DirectCallee = CalleeF ; } } if ( DirectCallee ) { if ( getAlign ( * DirectCallee , Idx , Alignment ) ) return Align ( Alignment ) ; return getFunctionParamOptimizedAlign ( DirectCallee , Ty , DL ) ; } return DL . getABITypeAlign ( Ty ) ;"
LLVM,NVPTX,1240,"Predict the next statement of this code snippet:
 <s> assert ( ! isKernelFunction ( * F ) && <STR_LIT> ) ; return Align ( std :: max ( uint64_t ( <NUM_LIT> ) , ABITypeAlign ) ) ;"
LLVM,NVPTX,1241,"Predict the next statement of this code snippet:
 <s> const uint64_t ABITypeAlign = DL . getABITypeAlign ( ArgTy ) . value ( ) ;"
LLVM,NVPTX,1242,"Predict the next statement of this code snippet:
 <s> if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned ParamAlign = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( & CB ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , ParamAlign ) ) ParamAlign = getFunctionParamOptimizedAlign ( F , Ty , DL ) . value ( ) ; O << <STR_LIT> << ParamAlign << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << DL . getTypeAllocSize ( Ty ) << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } Align ParamByValAlign = Outs [ OIdx ] . Flags . getNonZeroByValAlign ( ) ; Type * ETy = Args [ i ] . IndirectType ; Align AlignCandidate = getFunctionParamOptimizedAlign ( F , ETy , DL ) ; ParamByValAlign = std :: max ( ParamByValAlign , AlignCandidate ) ; O << <STR_LIT> << ParamByValAlign . value ( ) << <STR_LIT> ; O << <STR_LIT> ;"
LLVM,NVPTX,1243,"Predict the next statement of this code snippet:
 <s> StoreOperands . push_back ( Chain ) ; StoreOperands . push_back ( DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) ) ; } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size ( ) - <NUM_LIT> ; switch ( NumElts ) { case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } EVT TheStoreType = ExtendIntegerRetVal ? <STR_LIT> : VTs [ i ] ; Chain = DAG . getMemIntrinsicNode ( Op , dl , DAG . getVTList ( <STR_LIT> ) , StoreOperands , TheStoreType , MachinePointerInfo ( ) , Align ( <NUM_LIT> ) , MachineMemOperand :: MOStore ) ; StoreOperands . clear ( ) ; }"
LLVM,NVPTX,1244,"Predict the next statement of this code snippet:
 <s> for ( std :: size_t I = <NUM_LIT> , OpsCount = N -> ops ( ) . size ( ) ; I != OpsCount ; ++ I ) if ( ! N -> getOperand ( I ) . isUndef ( ) ) return SDValue ( ) ;"
LLVM,NVPTX,1245,"Predict the next statement of this code snippet:
 <s> static SDValue PerformStoreRetvalCombine ( SDNode * N ) { for ( std :: size_t I = <NUM_LIT> , OpsCount = N -> ops ( ) . size ( ) ; I != OpsCount ; ++ I ) if ( ! N -> getOperand ( I ) . isUndef ( ) ) return SDValue ( ) ;"
LLVM,NVPTX,1246,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; if ( ! llvm :: getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = PtrVT . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ;"
LLVM,NVPTX,1247,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) { if ( AM . BaseOffs || AM . HasBaseReg || AM . Scale ) return false ; return true ; } switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( AM . HasBaseReg ) return false ; break ;"
LLVM,NVPTX,1248,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; } else { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setTruncStoreAction ( VT , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { if ( IsPTXVectorType ( VT ) ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;"
LLVM,NVPTX,1249,"Predict the next statement of this code snippet:
 <s> delete DwarfFrameSection ; delete DwarfPubTypesSection ; delete DwarfDebugInlineSection ; delete DwarfStrSection ; delete DwarfLocSection ; delete DwarfARangesSection ;"
LLVM,NVPTX,1250,"Predict the next statement of this code snippet:
 <s> default : return AtomicExpansionKind :: CmpXChg ; case AtomicRMWInst :: BinOp :: And : case AtomicRMWInst :: BinOp :: Or : case AtomicRMWInst :: BinOp :: Xor : case AtomicRMWInst :: BinOp :: Xchg : switch ( ITy -> getBitWidth ( ) ) { case <NUM_LIT> : case <NUM_LIT> : return AtomicExpansionKind :: CmpXChg ; case <NUM_LIT> : return AtomicExpansionKind :: None ; case <NUM_LIT> : if ( STI . hasAtomBitwise64 ( ) ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: CmpXChg ; default : llvm_unreachable ( <STR_LIT> ) ; } case AtomicRMWInst :: BinOp :: Add : case AtomicRMWInst :: BinOp :: Sub : case AtomicRMWInst :: BinOp :: Max : case AtomicRMWInst :: BinOp :: Min : case AtomicRMWInst :: BinOp :: UMax : case AtomicRMWInst :: BinOp :: UMin : switch ( ITy -> getBitWidth ( ) ) {"
LLVM,NVPTX,1251,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( & CB ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; Align align = Outs [ OIdx ] . Flags . getNonZeroByValAlign ( ) ;"
LLVM,NVPTX,1252,"Predict the next statement of this code snippet:
 <s> static const char * const specialTypes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Type * Ty = arg -> getType ( ) ; auto * PTy = dyn_cast < PointerType > ( Ty ) ; if ( ! PTy ) return false ;"
LLVM,NVPTX,1253,"Predict the next statement of this code snippet:
 <s> if ( ! PTy ) return false ; if ( ! context ) return false ; auto * STy = dyn_cast < StructType > ( PTy -> getElementType ( ) ) ;"
LLVM,NVPTX,1254,"Predict the next statement of this code snippet:
 <s> if ( NumRegs > <NUM_LIT> ) -- InsIdx ; continue ; } InVals . push_back ( DAG . getNode ( <STR_LIT> , dl , Ins [ InsIdx ] . VT ) ) ; continue ; } if ( ! PAL . hasAttribute ( i + <NUM_LIT> , Attribute :: ByVal ) ) { bool aggregateIsPacked = false ; if ( StructType * STy = dyn_cast < StructType > ( Ty ) ) aggregateIsPacked = STy -> isPacked ( ) ; SmallVector < EVT , <NUM_LIT> > VTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputePTXValueVTs ( * this , DL , Ty , VTs , & Offsets , <NUM_LIT> ) ; assert ( VTs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; auto VectorInfo = VectorizePTXValueVTs ( VTs , Offsets , DL . getABITypeAlignment ( Ty ) ) ; SDValue Arg = getParamSymbol ( DAG , idx , PtrVT ) ; int VecIdx = - <NUM_LIT> ; for ( unsigned parti = <NUM_LIT> , parte = VTs . size ( ) ; parti != parte ; ++ parti ) { if ( VectorInfo [ parti ] & PVF_FIRST ) { assert ( VecIdx == - <NUM_LIT> && <STR_LIT> ) ; VecIdx = parti ; } if ( VectorInfo [ parti ] & PVF_LAST ) { unsigned NumElts = parti - VecIdx + <NUM_LIT> ; EVT EltVT = VTs [ parti ] ; EVT LoadVT = EltVT ; if ( EltVT == <STR_LIT> ) LoadVT = <STR_LIT> ; else if ( EltVT == <STR_LIT> ) LoadVT = <STR_LIT> ; EVT VecVT = EVT :: getVectorVT ( F -> getContext ( ) , LoadVT , NumElts ) ; SDValue VecAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Arg , DAG . getConstant ( Offsets [ VecIdx ] , dl , PtrVT ) ) ; Value * srcValue = Constant :: getNullValue ( PointerType :: get ( EltVT . getTypeForEVT ( F -> getContext ( ) ) , ADDRESS_SPACE_PARAM ) ) ; SDValue P = DAG . getLoad ( VecVT , dl , Root , VecAddr , MachinePointerInfo ( srcValue ) , aggregateIsPacked , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; if ( P . getNode ( ) ) P . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; ++ j ) {"
LLVM,NVPTX,1255,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,NVPTX,1256,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = getOpcForTextureInstr ( Intrinsic ) ; Info . memVT = <STR_LIT> ; Info . ptrVal = nullptr ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = false ; Info . align = <NUM_LIT> ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = getOpcForTextureInstr ( Intrinsic ) ; Info . memVT = <STR_LIT> ; Info . ptrVal = nullptr ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = false ; Info . align = <NUM_LIT> ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = getOpcForSurfaceInstr ( Intrinsic ) ; Info . memVT = <STR_LIT> ; Info . ptrVal = nullptr ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = false ; Info . align = <NUM_LIT> ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,1257,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += VecSize ) { SDValue StoreVal ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getConstant ( Offset , <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ; EVT ExtendedVT = ( NeedExtend ) ? <STR_LIT> : OutVals [ <NUM_LIT> ] . getValueType ( ) ; StoreVal = OutVals [ i ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( VecSize == <NUM_LIT> ) { Opc = <STR_LIT> ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; } Chain = DAG . getMemIntrinsicNode ( Opc , dl , DAG . getVTList ( <STR_LIT> ) , Ops , EltVT , MachinePointerInfo ( ) ) ; Offset += PerStoreOffset ; } } } else { SmallVector < EVT , <NUM_LIT> > ValVTs ; ComputePTXValueVTs ( * this , RetTy , ValVTs ) ; assert ( ValVTs . size ( ) == OutVals . size ( ) && <STR_LIT> ) ; unsigned SizeSoFar = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { SDValue theVal = OutVals [ i ] ; EVT TheValType = theVal . getValueType ( ) ; unsigned numElems = <NUM_LIT> ; if ( TheValType . isVector ( ) ) numElems = TheValType . getVectorNumElements ( ) ;"
LLVM,NVPTX,1258,"Predict the next statement of this code snippet:
 <s> return VT . getScalarType ( ) == <STR_LIT> ;"
LLVM,NVPTX,1259,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,NVPTX,1260,"Predict the next statement of this code snippet:
 <s> InVals . push_back ( p ) ; } continue ; } if ( isABI || isKernel ) { SDValue Arg = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) DAG . AssignOrdering ( p . getNode ( ) , idx + <NUM_LIT> ) ; if ( isKernel ) InVals . push_back ( p ) ; else { SDValue p2 = DAG . getNode ( <STR_LIT> , dl , ObjectVT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , p ) ; InVals . push_back ( p2 ) ; } } else { const PointerType * elemPtrType = dyn_cast < PointerType > ( argTypes [ i ] ) ; assert ( elemPtrType && <STR_LIT> ) ; Type * elemType = elemPtrType -> getElementType ( ) ; SmallVector < EVT , <NUM_LIT> > vtparts ; SmallVector < uint64_t , <NUM_LIT> > offsets ; ComputeValueVTs ( * this , elemType , vtparts , & offsets , <NUM_LIT> ) ; unsigned totalsize = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> , je = vtparts . size ( ) ; j != je ; ++ j ) totalsize += vtparts [ j ] . getStoreSizeInBits ( ) ; SDValue localcopy = DAG . getFrameIndex ( MF . getFrameInfo ( ) -> CreateStackObject ( totalsize / <NUM_LIT> , <NUM_LIT> , false ) , getPointerTy ( ) ) ; unsigned sizesofar = <NUM_LIT> ; std :: vector < SDValue > theChains ; for ( unsigned j = <NUM_LIT> , je = vtparts . size ( ) ; j != je ; ++ j ) { unsigned numElems = <NUM_LIT> ; if ( vtparts [ j ] . isVector ( ) ) numElems = vtparts [ j ] . getVectorNumElements ( ) ; for ( unsigned k = <NUM_LIT> , ke = numElems ; k != ke ; ++ k ) { EVT tmpvt = vtparts [ j ] ; if ( tmpvt . isVector ( ) ) tmpvt = tmpvt . getVectorElementType ( ) ; SDValue arg = DAG . getNode ( <STR_LIT> , dl , tmpvt , getParamSymbol ( DAG , idx , tmpvt ) ) ; SDValue addr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , localcopy , DAG . getConstant ( sizesofar , getPointerTy ( ) ) ) ; theChains . push_back ( DAG . getStore ( Chain , dl , arg , addr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ;"
LLVM,NVPTX,1261,"Predict the next statement of this code snippet:
 <s> LoadSDNode * LD = cast < LoadSDNode > ( Node ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ;"
LLVM,NVPTX,1262,"Predict the next statement of this code snippet:
 <s> SDValue ExtVal = DAG . getNode ( <STR_LIT> , DL , EltVT , Val , DAG . getIntPtrConstant ( i ) ) ; if ( NeedExt ) ExtVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ExtVal ) ; Ops . push_back ( ExtVal ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } MemSDNode * MemSD = cast < MemSDNode > ( N ) ; SDValue NewSt = DAG . getMemIntrinsicNode ( Opcode , DL , DAG . getVTList ( <STR_LIT> ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ;"
LLVM,NVPTX,1263,"Predict the next statement of this code snippet:
 <s> static void ReplaceINTRINSIC_W_CHAIN ( SDNode * N , SelectionDAG & DAG , SmallVectorImpl < SDValue > & Results ) { SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Intrin = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; unsigned IntrinNo = cast < ConstantSDNode > ( Intrin . getNode ( ) ) -> getZExtValue ( ) ; switch ( IntrinNo ) { default : return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ResVT . isVector ( ) ) { unsigned NumElts = ResVT . getVectorNumElements ( ) ; EVT EltVT = ResVT . getVectorElementType ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : switch ( IntrinNo ) { default : return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ;"
LLVM,NVPTX,1264,"Predict the next statement of this code snippet:
 <s> static void ReplaceINTRINSIC_W_CHAIN ( SDNode * N , SelectionDAG & DAG , SmallVectorImpl < SDValue > & Results ) { SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Intrin = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; unsigned IntrinNo = cast < ConstantSDNode > ( Intrin . getNode ( ) ) -> getZExtValue ( ) ; switch ( IntrinNo ) { default : return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ResVT . isVector ( ) ) { unsigned NumElts = ResVT . getVectorNumElements ( ) ; EVT EltVT = ResVT . getVectorElementType ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : switch ( IntrinNo ) { default : return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { switch ( IntrinNo ) { default : return ; case <STR_LIT> :"
LLVM,NVPTX,1265,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs , <NUM_LIT> ) ; break ; }"
LLVM,NVPTX,1266,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs , <NUM_LIT> ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , & OtherOps [ <NUM_LIT> ] , OtherOps . size ( ) , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ;"
LLVM,NVPTX,1267,"Predict the next statement of this code snippet:
 <s> ReplaceLoadVector ( N , DAG , Results ) ; return ; case <STR_LIT> : ReplaceINTRINSIC_W_CHAIN ( N , DAG , Results ) ;"
LLVM,NVPTX,1268,"Predict the next statement of this code snippet:
 <s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'c' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : case 'N' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,NVPTX,1269,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,NVPTX,1270,"Predict the next statement of this code snippet:
 <s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;"
LLVM,NVPTX,1271,"Predict the next statement of this code snippet:
 <s> Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = true ; Info . align = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = true ; Info . align = <NUM_LIT> ; return true ;"
LLVM,NVPTX,1272,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,1273,"Predict the next statement of this code snippet:
 <s> continue ; } if ( theArgs [ i ] -> use_empty ( ) ) { if ( ObjectVT . isVector ( ) ) { EVT EltVT = ObjectVT . getVectorElementType ( ) ; unsigned NumElts = ObjectVT . getVectorNumElements ( ) ; for ( unsigned vi = <NUM_LIT> ; vi < NumElts ; ++ vi ) { InVals . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT ) ) ; } } else { InVals . push_back ( DAG . getNode ( <STR_LIT> , dl , ObjectVT ) ) ; } continue ; } if ( PAL . hasAttribute ( i + <NUM_LIT> , Attribute :: ByVal ) == false ) { if ( ObjectVT . isVector ( ) ) { unsigned NumElts = ObjectVT . getVectorNumElements ( ) ; EVT EltVT = ObjectVT . getVectorElementType ( ) ; unsigned Offset = <NUM_LIT> ; for ( unsigned vi = <NUM_LIT> ; vi < NumElts ; ++ vi ) { SDValue A = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; SDValue B = DAG . getIntPtrConstant ( Offset ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , A , B ) ; Value * SrcValue = Constant :: getNullValue ( PointerType :: get ( EltVT . getTypeForEVT ( F -> getContext ( ) ) , llvm :: ADDRESS_SPACE_PARAM ) ) ; SDValue Ld = DAG . getLoad ( EltVT , dl , Root , Addr , MachinePointerInfo ( SrcValue ) , false , false , false , TD -> getABITypeAlignment ( EltVT . getTypeForEVT ( F -> getContext ( ) ) ) ) ; Offset += EltVT . getStoreSizeInBits ( ) / <NUM_LIT> ; InVals . push_back ( Ld ) ; } continue ; } if ( isABI || isKernel ) { SDValue Arg = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; Value * srcValue = Constant :: getNullValue ( PointerType :: get ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) , llvm :: ADDRESS_SPACE_PARAM ) ) ; SDValue p = DAG . getLoad ( ObjectVT , dl , Root , Arg , MachinePointerInfo ( srcValue ) , false , false , false , TD -> getABITypeAlignment ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) ) ) ; if ( p . getNode ( ) ) p . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; InVals . push_back ( p ) ; } else { SDValue Arg = getParamSymbol ( DAG , idx , ObjectVT ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) p . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ;"
LLVM,NVPTX,1274,"Predict the next statement of this code snippet:
 <s> if ( theArgs [ i ] -> use_empty ( ) ) { if ( ObjectVT . isVector ( ) ) { EVT EltVT = ObjectVT . getVectorElementType ( ) ; unsigned NumElts = ObjectVT . getVectorNumElements ( ) ; for ( unsigned vi = <NUM_LIT> ; vi < NumElts ; ++ vi ) { InVals . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT ) ) ; } } else { InVals . push_back ( DAG . getNode ( <STR_LIT> , dl , ObjectVT ) ) ; } continue ; } if ( PAL . hasAttribute ( i + <NUM_LIT> , Attribute :: ByVal ) == false ) { if ( ObjectVT . isVector ( ) ) { unsigned NumElts = ObjectVT . getVectorNumElements ( ) ; EVT EltVT = ObjectVT . getVectorElementType ( ) ; unsigned Offset = <NUM_LIT> ; for ( unsigned vi = <NUM_LIT> ; vi < NumElts ; ++ vi ) { SDValue A = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; SDValue B = DAG . getIntPtrConstant ( Offset ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , A , B ) ; Value * SrcValue = Constant :: getNullValue ( PointerType :: get ( EltVT . getTypeForEVT ( F -> getContext ( ) ) , llvm :: ADDRESS_SPACE_PARAM ) ) ; SDValue Ld = DAG . getLoad ( EltVT , dl , Root , Addr , MachinePointerInfo ( SrcValue ) , false , false , false , TD -> getABITypeAlignment ( EltVT . getTypeForEVT ( F -> getContext ( ) ) ) ) ; Offset += EltVT . getStoreSizeInBits ( ) / <NUM_LIT> ; InVals . push_back ( Ld ) ; } continue ; } if ( isABI || isKernel ) { SDValue Arg = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; Value * srcValue = Constant :: getNullValue ( PointerType :: get ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) , llvm :: ADDRESS_SPACE_PARAM ) ) ; SDValue p = DAG . getLoad ( ObjectVT , dl , Root , Arg , MachinePointerInfo ( srcValue ) , false , false , false , TD -> getABITypeAlignment ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) ) ) ; if ( p . getNode ( ) ) p . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; InVals . push_back ( p ) ; } else { SDValue Arg = getParamSymbol ( DAG , idx , ObjectVT ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) p . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; InVals . push_back ( p ) ; } continue ; } if ( isABI || isKernel ) {"
LLVM,NVPTX,1275,"Predict the next statement of this code snippet:
 <s> SDNode * Node = Op . getNode ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( Node ) ; SDLoc dl ( Node ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , newLD ) ; SDValue Ops [ ] = { result , LD -> getChain ( ) } ;"
LLVM,NVPTX,1276,"Predict the next statement of this code snippet:
 <s> assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , newLD ) ; SDValue Ops [ ] = { result , LD -> getChain ( ) } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , dl ) ;"
LLVM,NVPTX,1277,"Predict the next statement of this code snippet:
 <s> bool isVolatile = ST -> isVolatile ( ) ; bool isNonTemporal = ST -> isNonTemporal ( ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp3 ) ; SDValue Result = DAG . getStore ( Tmp1 , dl , Tmp3 , Tmp2 , ST -> getPointerInfo ( ) , isVolatile , isNonTemporal , Alignment ) ;"
LLVM,NVPTX,1278,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerSTOREi1 ( SDValue Op , SelectionDAG & DAG ) const { SDNode * Node = Op . getNode ( ) ; SDLoc dl ( Node ) ; StoreSDNode * ST = cast < StoreSDNode > ( Node ) ; SDValue Tmp1 = ST -> getChain ( ) ; SDValue Tmp2 = ST -> getBasePtr ( ) ; SDValue Tmp3 = ST -> getValue ( ) ; assert ( Tmp3 . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned Alignment = ST -> getAlignment ( ) ; bool isVolatile = ST -> isVolatile ( ) ; bool isNonTemporal = ST -> isNonTemporal ( ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp3 ) ; SDValue Result = DAG . getStore ( Tmp1 , dl , Tmp3 , Tmp2 , ST -> getPointerInfo ( ) , isVolatile , isNonTemporal , Alignment ) ; return Result ;"
LLVM,NVPTX,1279,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; } else { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( nvptxSubtarget . hasROT32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; } else { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( int i = <STR_LIT> ; i <= <STR_LIT> ; ++ i ) {"
LLVM,NVPTX,1280,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs , <NUM_LIT> ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; OtherOps . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , & OtherOps [ <NUM_LIT> ] , OtherOps . size ( ) , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ; } SDValue LoadChain = NewLD . getValue ( NumElts ) ; SDValue BuildVec = DAG . getNode ( <STR_LIT> , DL , ResVT , & ScalarRes [ <NUM_LIT> ] , NumElts ) ; Results . push_back ( BuildVec ) ; Results . push_back ( LoadChain ) ; } else { assert ( ResVT . isSimple ( ) && ResVT . getSimpleVT ( ) . SimpleTy == <STR_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ; SDVTList LdResVTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , LdResVTs , & Ops [ <NUM_LIT> ] , Ops . size ( ) , <STR_LIT> , MemSD -> getMemOperand ( ) ) ; Results . push_back ( NewLD . getValue ( <NUM_LIT> ) ) ; Results . push_back ( NewLD . getValue ( <NUM_LIT> ) ) ; }"
LLVM,NVPTX,1281,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> << retAlignment << <STR_LIT> << DL . getTypeAllocSize ( retTy ) << <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS . getInstruction ( ) ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; Align align = Outs [ OIdx ] . Flags . getNonZeroByValAlign ( ) ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align . value ( ) << <STR_LIT> ; O << <STR_LIT> ;"
LLVM,NVPTX,1282,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TargetLowering :: useF32FTZ ( const MachineFunction & MF ) const { if ( FtzEnabled . getNumOccurrences ( ) > <NUM_LIT> ) { return FtzEnabled ; } return MF . getDenormalMode ( APFloat :: IEEEsingle ( ) ) . Output == DenormalMode :: PreserveSign ;"
LLVM,NVPTX,1283,"Predict the next statement of this code snippet:
 <s> return FtzEnabled ; }"
LLVM,NVPTX,1284,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> << getPointerTy ( ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( ( retTy -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( retTy ) ) { O << <STR_LIT> << retAlignment << <STR_LIT> << getDataLayout ( ) -> getTypeAllocSize ( retTy ) << <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; MVT thePointerTy = getPointerTy ( ) ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; const DataLayout * TD = getDataLayout ( ) ; if ( ! llvm :: getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = TD -> getABITypeAlignment ( Ty ) ; unsigned sz = TD -> getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( Ty ) == Outs [ OIdx ] . VT || ( getValueType ( Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ;"
LLVM,NVPTX,1285,"Predict the next statement of this code snippet:
 <s> case 'b' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'c' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : case 'N' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' :"
LLVM,NVPTX,1286,"Predict the next statement of this code snippet:
 <s> SDLoc DL ( N ) ; EVT ValVT = Val . getValueType ( ) ; if ( ValVT . isVector ( ) ) { if ( ! ValVT . isSimple ( ) ) return SDValue ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } MemSDNode * MemSD = cast < MemSDNode > ( N ) ; const DataLayout * TD = getDataLayout ( ) ; unsigned Align = MemSD -> getAlignment ( ) ; unsigned PrefAlign = TD -> getPrefTypeAlignment ( ValVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return SDValue ( ) ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue ExtVal = DAG . getNode ( <STR_LIT> , DL , EltVT , Val , DAG . getIntPtrConstant ( i ) ) ; if ( NeedExt ) ExtVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ExtVal ) ; Ops . push_back ( ExtVal ) ; } Ops . append ( N -> op_begin ( ) + <NUM_LIT> , N -> op_end ( ) ) ; SDValue NewSt = DAG . getMemIntrinsicNode ( Opcode , DL , DAG . getVTList ( <STR_LIT> ) , Ops , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; return NewSt ; }"
LLVM,NVPTX,1287,"Predict the next statement of this code snippet:
 <s> unsigned PrefAlign = TD -> getPrefTypeAlignment ( ResVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ; } SDValue LoadChain = NewLD . getValue ( NumElts ) ; SDValue BuildVec = DAG . getNode ( <STR_LIT> , DL , ResVT , ScalarRes ) ;"
LLVM,NVPTX,1288,"Predict the next statement of this code snippet:
 <s> } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ;"
LLVM,NVPTX,1289,"Predict the next statement of this code snippet:
 <s> if ( OutVals [ <NUM_LIT> ] . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) VecSize = <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; EVT VecVT = EVT :: getVectorVT ( F -> getContext ( ) , EltVT , VecSize ) ; unsigned PerStoreOffset = TD . getTypeAllocSize ( VecVT . getTypeForEVT ( F -> getContext ( ) ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += VecSize ) { SDValue StoreVal ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getConstant ( Offset , dl , <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ; EVT ExtendedVT = ( NeedExtend ) ? <STR_LIT> : OutVals [ <NUM_LIT> ] . getValueType ( ) ; StoreVal = OutVals [ i ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( VecSize == <NUM_LIT> ) { Opc = <STR_LIT> ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; } Chain = DAG . getMemIntrinsicNode ( Opc , dl , DAG . getVTList ( <STR_LIT> ) , Ops , EltVT , MachinePointerInfo ( ) ) ; Offset += PerStoreOffset ; } }"
LLVM,NVPTX,1290,"Predict the next statement of this code snippet:
 <s> if ( AM . BaseGV ) { if ( AM . BaseOffs || AM . HasBaseReg || AM . Scale ) return false ; return true ; } switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( AM . HasBaseReg ) return false ;"
LLVM,NVPTX,1291,"Predict the next statement of this code snippet:
 <s> } Chain = DAG . getMemIntrinsicNode ( Opc , dl , DAG . getVTList ( <STR_LIT> ) , Ops , EltVT , MachinePointerInfo ( ) ) ; Offset += PerStoreOffset ; } } } else { SmallVector < EVT , <NUM_LIT> > ValVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputePTXValueVTs ( * this , RetTy , ValVTs , & Offsets , <NUM_LIT> ) ; assert ( ValVTs . size ( ) == OutVals . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { SDValue theVal = OutVals [ i ] ; EVT TheValType = theVal . getValueType ( ) ; unsigned numElems = <NUM_LIT> ; if ( TheValType . isVector ( ) ) numElems = TheValType . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> , je = numElems ; j != je ; ++ j ) { SDValue TmpVal = theVal ; if ( TheValType . isVector ( ) ) TmpVal = DAG . getNode ( <STR_LIT> , dl , TheValType . getVectorElementType ( ) , TmpVal , DAG . getIntPtrConstant ( j , dl ) ) ; EVT TheStoreType = ValVTs [ i ] ; if ( RetTy -> isIntegerTy ( ) && TD -> getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ) { TmpVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TmpVal ) ; TheStoreType = <STR_LIT> ; } else if ( TmpVal . getValueType ( ) . getSizeInBits ( ) < <NUM_LIT> ) TmpVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TmpVal ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) , TmpVal } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , TheStoreType , MachinePointerInfo ( ) ) ; } } } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;"
LLVM,NVPTX,1292,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerSTOREVector ( SDValue Op , SelectionDAG & DAG ) const { SDNode * N = Op . getNode ( ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT ValVT = Val . getValueType ( ) ; if ( ValVT . isVector ( ) ) { if ( ! ValVT . isSimple ( ) ) return SDValue ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } MemSDNode * MemSD = cast < MemSDNode > ( N ) ; const DataLayout * TD = getDataLayout ( ) ; unsigned Align = MemSD -> getAlignment ( ) ; unsigned PrefAlign = TD -> getPrefTypeAlignment ( ValVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return SDValue ( ) ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ;"
LLVM,NVPTX,1293,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } LoadSDNode * LD = cast < LoadSDNode > ( N ) ; unsigned Align = LD -> getAlignment ( ) ; unsigned PrefAlign = TD -> getPrefTypeAlignment ( ResVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ;"
LLVM,NVPTX,1294,"Predict the next statement of this code snippet:
 <s> } LoadSDNode * LD = cast < LoadSDNode > ( N ) ; unsigned Align = LD -> getAlignment ( ) ; unsigned PrefAlign = TD -> getPrefTypeAlignment ( ResVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) , DL ) ) ;"
LLVM,NVPTX,1295,"Predict the next statement of this code snippet:
 <s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : case 'N' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' :"
LLVM,NVPTX,1296,"Predict the next statement of this code snippet:
 <s> SDValue <ISA_LIT>TargetLowering :: LowerCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) const { SDNode * Node = Op . getNode ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumOperands = Node -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { SDValue SubOp = Node -> getOperand ( i ) ; EVT VVT = SubOp . getNode ( ) -> getValueType ( <NUM_LIT> ) ; EVT EltVT = VVT . getVectorElementType ( ) ; unsigned NumSubElem = VVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumSubElem ; ++ j ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SubOp , DAG . getIntPtrConstant ( j ) ) ) ; } } return DAG . getNode ( <STR_LIT> , dl , Node -> getValueType ( <NUM_LIT> ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;"
LLVM,NVPTX,1297,"Predict the next statement of this code snippet:
 <s> unsigned NumSubElem = VVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumSubElem ; ++ j ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SubOp , DAG . getIntPtrConstant ( j ) ) ) ; } }"
LLVM,NVPTX,1298,"Predict the next statement of this code snippet:
 <s> SDValue Arg = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) DAG . AssignOrdering ( p . getNode ( ) , idx + <NUM_LIT> ) ; if ( isKernel ) InVals . push_back ( p ) ; else { SDValue p2 = DAG . getNode ( <STR_LIT> , dl , ObjectVT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , p ) ; InVals . push_back ( p2 ) ; } } else { const PointerType * elemPtrType = dyn_cast < PointerType > ( argTypes [ i ] ) ; assert ( elemPtrType && <STR_LIT> ) ; Type * elemType = elemPtrType -> getElementType ( ) ; SmallVector < EVT , <NUM_LIT> > vtparts ; SmallVector < uint64_t , <NUM_LIT> > offsets ; ComputeValueVTs ( * this , elemType , vtparts , & offsets , <NUM_LIT> ) ; unsigned totalsize = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> , je = vtparts . size ( ) ; j != je ; ++ j ) totalsize += vtparts [ j ] . getStoreSizeInBits ( ) ; SDValue localcopy = DAG . getFrameIndex ( MF . getFrameInfo ( ) -> CreateStackObject ( totalsize / <NUM_LIT> , <NUM_LIT> , false ) , getPointerTy ( ) ) ; unsigned sizesofar = <NUM_LIT> ; std :: vector < SDValue > theChains ; for ( unsigned j = <NUM_LIT> , je = vtparts . size ( ) ; j != je ; ++ j ) { unsigned numElems = <NUM_LIT> ; if ( vtparts [ j ] . isVector ( ) ) numElems = vtparts [ j ] . getVectorNumElements ( ) ; for ( unsigned k = <NUM_LIT> , ke = numElems ; k != ke ; ++ k ) { EVT tmpvt = vtparts [ j ] ; if ( tmpvt . isVector ( ) ) tmpvt = tmpvt . getVectorElementType ( ) ; SDValue arg = DAG . getNode ( <STR_LIT> , dl , tmpvt , getParamSymbol ( DAG , idx , tmpvt ) ) ; SDValue addr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , localcopy , DAG . getConstant ( sizesofar , getPointerTy ( ) ) ) ; theChains . push_back ( DAG . getStore ( Chain , dl , arg , addr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; sizesofar += tmpvt . getStoreSizeInBits ( ) / <NUM_LIT> ; ++ idx ; } } -- idx ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & theChains [ <NUM_LIT> ] , theChains . size ( ) ) ; InVals . push_back ( localcopy ) ; } } if ( ! OutChains . empty ( ) ) DAG . setRoot ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & OutChains [ <NUM_LIT> ] , OutChains . size ( ) ) ) ;"
LLVM,NVPTX,1299,"Predict the next statement of this code snippet:
 <s> assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ;"
LLVM,NVPTX,1300,"Predict the next statement of this code snippet:
 <s> if ( theValType . isVector ( ) ) tmpval = DAG . getNode ( <STR_LIT> , dl , theValType . getVectorElementType ( ) , tmpval , DAG . getIntPtrConstant ( j ) ) ; Chain = DAG . getNode ( isABI ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getConstant ( isABI ? sizesofar : idx , <STR_LIT> ) , tmpval ) ;"
LLVM,NVPTX,1301,"Predict the next statement of this code snippet:
 <s> for ( unsigned j = <NUM_LIT> , je = numElems ; j != je ; ++ j ) { SDValue tmpval = theVal ; if ( theValType . isVector ( ) ) tmpval = DAG . getNode ( <STR_LIT> , dl , theValType . getVectorElementType ( ) , tmpval , DAG . getIntPtrConstant ( j ) ) ; Chain = DAG . getNode ( isABI ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getConstant ( isABI ? sizesofar : idx , <STR_LIT> ) , tmpval ) ;"
LLVM,NVPTX,1302,"Predict the next statement of this code snippet:
 <s> SDValue Tmp3 = ST -> getValue ( ) ; assert ( Tmp3 . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned Alignment = ST -> getAlignment ( ) ; bool isVolatile = ST -> isVolatile ( ) ; bool isNonTemporal = ST -> isNonTemporal ( ) ;"
LLVM,NVPTX,1303,"Predict the next statement of this code snippet:
 <s> Opcode = <STR_LIT> ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue ExtVal = DAG . getNode ( <STR_LIT> , DL , EltVT , Val , DAG . getIntPtrConstant ( i ) ) ; if ( NeedExt ) ExtVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ExtVal ) ; Ops . push_back ( ExtVal ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } MemSDNode * MemSD = cast < MemSDNode > ( N ) ; SDValue NewSt = DAG . getMemIntrinsicNode ( Opcode , DL , DAG . getVTList ( <STR_LIT> ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; return NewSt ;"
LLVM,NVPTX,1304,"Predict the next statement of this code snippet:
 <s> LdResVTs = DAG . getVTList ( ListVTs , <NUM_LIT> ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; OtherOps . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , & OtherOps [ <NUM_LIT> ] , OtherOps . size ( ) , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ; } SDValue LoadChain = NewLD . getValue ( NumElts ) ; SDValue BuildVec = DAG . getNode ( <STR_LIT> , DL , ResVT , & ScalarRes [ <NUM_LIT> ] , NumElts ) ; Results . push_back ( BuildVec ) ; Results . push_back ( LoadChain ) ; } else { assert ( ResVT . isSimple ( ) && ResVT . getSimpleVT ( ) . SimpleTy == <STR_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ; SDVTList LdResVTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , LdResVTs , & Ops [ <NUM_LIT> ] , Ops . size ( ) , <STR_LIT> , MemSD -> getMemOperand ( ) ) ; Results . push_back ( NewLD . getValue ( <NUM_LIT> ) ) ; Results . push_back ( NewLD . getValue ( <NUM_LIT> ) ) ; } } }"
LLVM,NVPTX,1305,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs , <NUM_LIT> ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ; OtherOps . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , & OtherOps [ <NUM_LIT> ] , OtherOps . size ( ) , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ; } SDValue LoadChain = NewLD . getValue ( NumElts ) ; SDValue BuildVec = DAG . getNode ( <STR_LIT> , DL , ResVT , & ScalarRes [ <NUM_LIT> ] , NumElts ) ; Results . push_back ( BuildVec ) ; Results . push_back ( LoadChain ) ; } else { assert ( ResVT . isSimple ( ) && ResVT . getSimpleVT ( ) . SimpleTy == <STR_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ; SDVTList LdResVTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MemIntrinsicSDNode * MemSD = cast < MemIntrinsicSDNode > ( N ) ;"
LLVM,NVPTX,1306,"Predict the next statement of this code snippet:
 <s> SmallVector < SDValue , <NUM_LIT> > OtherOps ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , & OtherOps [ <NUM_LIT> ] , OtherOps . size ( ) , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ;"
LLVM,NVPTX,1307,"Predict the next statement of this code snippet:
 <s> SDValue Offset = DAG . getConstant ( GN -> getOffset ( ) , dl , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Op = DAG . getNode ( <STR_LIT> , Op , getPointerTy ( DAG . getDataLayout ( ) ) , Op , Offset ) ; } return Op ;"
LLVM,NVPTX,1308,"Predict the next statement of this code snippet:
 <s> if ( ! llvm :: getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = TD -> getABITypeAlignment ( Ty ) ; unsigned sz = TD -> getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( Ty ) == Outs [ OIdx ] . VT || ( getValueType ( Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; unsigned align = Outs [ OIdx ] . Flags . getByValAlign ( ) ;"
LLVM,NVPTX,1309,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( nvptxSubtarget . hasROT64 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; } else { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( nvptxSubtarget . hasROT32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; } else { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setTruncStoreAction ( VT , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { if ( IsPTXVectorType ( VT ) ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,NVPTX,1310,"Predict the next statement of this code snippet:
 <s> O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ;"
LLVM,NVPTX,1311,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) {"
LLVM,NVPTX,1312,"Predict the next statement of this code snippet:
 <s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( nvptxSubtarget . hasROT32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; } else { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,NVPTX,1313,"Predict the next statement of this code snippet:
 <s> } if ( isABI || isKernel ) { SDValue Arg = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) p . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; if ( isKernel ) InVals . push_back ( p ) ; else { SDValue p2 = DAG . getNode ( <STR_LIT> , dl , ObjectVT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , p ) ; InVals . push_back ( p2 ) ; } } else { const PointerType * elemPtrType = dyn_cast < PointerType > ( argTypes [ i ] ) ; assert ( elemPtrType && <STR_LIT> ) ; Type * elemType = elemPtrType -> getElementType ( ) ; SmallVector < EVT , <NUM_LIT> > vtparts ; SmallVector < uint64_t , <NUM_LIT> > offsets ; ComputeValueVTs ( * this , elemType , vtparts , & offsets , <NUM_LIT> ) ; unsigned totalsize = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> , je = vtparts . size ( ) ; j != je ; ++ j ) totalsize += vtparts [ j ] . getStoreSizeInBits ( ) ; SDValue localcopy = DAG . getFrameIndex ( MF . getFrameInfo ( ) -> CreateStackObject ( totalsize / <NUM_LIT> , <NUM_LIT> , false ) , getPointerTy ( ) ) ; unsigned sizesofar = <NUM_LIT> ; std :: vector < SDValue > theChains ; for ( unsigned j = <NUM_LIT> , je = vtparts . size ( ) ; j != je ; ++ j ) { unsigned numElems = <NUM_LIT> ; if ( vtparts [ j ] . isVector ( ) ) numElems = vtparts [ j ] . getVectorNumElements ( ) ; for ( unsigned k = <NUM_LIT> , ke = numElems ; k != ke ; ++ k ) { EVT tmpvt = vtparts [ j ] ; if ( tmpvt . isVector ( ) ) tmpvt = tmpvt . getVectorElementType ( ) ; SDValue arg = DAG . getNode ( <STR_LIT> , dl , tmpvt , getParamSymbol ( DAG , idx , tmpvt ) ) ; SDValue addr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , localcopy , DAG . getConstant ( sizesofar , getPointerTy ( ) ) ) ; theChains . push_back ( DAG . getStore ( Chain , dl , arg , addr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; sizesofar += tmpvt . getStoreSizeInBits ( ) / <NUM_LIT> ;"
LLVM,NVPTX,1314,"Predict the next statement of this code snippet:
 <s> unsigned combineRepeatedFPDivisors ( ) const override { return <NUM_LIT> ;"
LLVM,NVPTX,1315,"Predict the next statement of this code snippet:
 <s> unsigned combineRepeatedFPDivisors ( ) const override { return <NUM_LIT> ;"
LLVM,NVPTX,1316,"Predict the next statement of this code snippet:
 <s> std :: string * name = nvTM -> getManagedStrPool ( ) -> getManagedString ( inname ) ; std :: stringstream suffix ; suffix << idx ; * name += suffix . str ( ) ;"
LLVM,NVPTX,1317,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>TargetLowering :: getFunctionAlignment ( const Function * ) const { return <NUM_LIT> ;"
LLVM,NVPTX,1318,"Predict the next statement of this code snippet:
 <s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override {"
LLVM,NVPTX,1319,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,NVPTX,1320,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,NVPTX,1321,"Predict the next statement of this code snippet:
 <s> bool isFMAFasterThanFMulAndFAdd ( EVT ) const override { return true ;"
LLVM,NVPTX,1322,"Predict the next statement of this code snippet:
 <s> if ( ! context ) return false ; auto * STy = dyn_cast < StructType > ( PTy -> getElementType ( ) ) ; const std :: string TypeName = STy && ! STy -> isLiteral ( ) ? STy -> getName ( ) : <STR_LIT> ;"
LLVM,NVPTX,1323,"Predict the next statement of this code snippet:
 <s> MVT eVT = VT . getVectorElementType ( ) ; if ( isTypeLegal ( eVT ) ) return true ;"
LLVM,NVPTX,1324,"Predict the next statement of this code snippet:
 <s> MVT eVT = VT . getVectorElementType ( ) ; if ( isTypeLegal ( eVT ) ) return true ; } return false ;"
LLVM,NVPTX,1325,"Predict the next statement of this code snippet:
 <s> BasicBlock * OrigBB = ConvertedInst -> getParent ( ) ; BasicBlock * NewBB = ConvertedInst -> getParent ( ) -> splitBasicBlock ( ConvertedInst , <STR_LIT> ) ; BasicBlock * LoopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , NewBB ) ; OrigBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , LoopBB ) ; IRBuilder < > Builder ( OrigBB -> getTerminator ( ) ) ; unsigned SrcAS = cast < PointerType > ( SrcAddr -> getType ( ) ) -> getAddressSpace ( ) ; unsigned DstAS = cast < PointerType > ( DstAddr -> getType ( ) ) -> getAddressSpace ( ) ;"
LLVM,NVPTX,1326,"Predict the next statement of this code snippet:
 <s> OrigBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , LoopBB ) ; IRBuilder < > Builder ( OrigBB -> getTerminator ( ) ) ; unsigned SrcAS = cast < PointerType > ( SrcAddr -> getType ( ) ) -> getAddressSpace ( ) ; unsigned DstAS = cast < PointerType > ( DstAddr -> getType ( ) ) -> getAddressSpace ( ) ; SrcAddr = Builder . CreateBitCast ( SrcAddr , Builder . getInt8PtrTy ( SrcAS ) ) ; DstAddr = Builder . CreateBitCast ( DstAddr , Builder . getInt8PtrTy ( DstAS ) ) ; IRBuilder < > LoopBuilder ( LoopBB ) ; PHINode * LoopIndex = LoopBuilder . CreatePHI ( TypeOfCopyLen , <NUM_LIT> ) ; LoopIndex -> addIncoming ( ConstantInt :: get ( TypeOfCopyLen , <NUM_LIT> ) , OrigBB ) ; Value * Element = LoopBuilder . CreateLoad ( LoopBuilder . CreateInBoundsGEP ( LoopBuilder . getInt8Ty ( ) , SrcAddr , LoopIndex ) , SrcIsVolatile ) ; LoopBuilder . CreateStore ( Element , LoopBuilder . CreateInBoundsGEP ( LoopBuilder . getInt8Ty ( ) , DstAddr , LoopIndex ) , DstIsVolatile ) ; Value * NewIndex = LoopBuilder . CreateAdd ( LoopIndex , ConstantInt :: get ( TypeOfCopyLen , <NUM_LIT> ) ) ; LoopIndex -> addIncoming ( NewIndex , LoopBB ) ;"
LLVM,NVPTX,1327,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,1328,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1329,"Predict the next statement of this code snippet:
 <s> AU . addRequired < TargetTransformInfoWrapperPass > ( ) ;"
LLVM,NVPTX,1330,"Predict the next statement of this code snippet:
 <s> AU . addPreserved < StackProtector > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ;"
LLVM,NVPTX,1331,"Predict the next statement of this code snippet:
 <s> for ( Instruction & I : BB ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( & I ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( <NUM_LIT> ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( & I ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ; } } } } if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ;"
LLVM,NVPTX,1332,"Predict the next statement of this code snippet:
 <s> if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ; } for ( LoadInst * LI : AggrLoads ) { auto * SI = cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( <NUM_LIT> ) ; Value * DstAddr = SI -> getOperand ( <NUM_LIT> ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; ConstantInt * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; createMemCpyLoopKnownSize ( SI , SrcAddr , DstAddr , CopyLen , LI -> getAlign ( ) , SI -> getAlign ( ) , LI -> isVolatile ( ) , SI -> isVolatile ( ) , true , TTI ) ; SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; }"
LLVM,NVPTX,1333,"Predict the next statement of this code snippet:
 <s> for ( Function :: iterator BI = F . begin ( ) , BE = F . end ( ) ; BI != BE ; ++ BI ) { for ( BasicBlock :: iterator II = BI -> begin ( ) , IE = BI -> end ( ) ; II != IE ; ++ II ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( II ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( <NUM_LIT> ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( II ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ; } } } } if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ; } for ( LoadInst * LI : AggrLoads ) { auto * SI = cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( <NUM_LIT> ) ; Value * DstAddr = SI -> getOperand ( <NUM_LIT> ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; ConstantInt * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; createMemCpyLoopKnownSize ( SI , SrcAddr , DstAddr , CopyLen , LI -> getAlign ( ) , SI -> getAlign ( ) , LI -> isVolatile ( ) , SI -> isVolatile ( ) , TTI ) ; SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; } for ( MemIntrinsic * MemCall : MemCalls ) { if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( MemCall ) ) { expandMemCpyAsLoop ( Memcpy , TTI ) ; } else if ( MemMoveInst * Memmove = dyn_cast < MemMoveInst > ( MemCall ) ) { expandMemMoveAsLoop ( Memmove ) ; } else if ( MemSetInst * Memset = dyn_cast < MemSetInst > ( MemCall ) ) { expandMemSetAsLoop ( Memset ) ; } MemCall -> eraseFromParent ( ) ;"
LLVM,NVPTX,1334,"Predict the next statement of this code snippet:
 <s> for ( Function :: iterator BI = F . begin ( ) , BE = F . end ( ) ; BI != BE ; ++ BI ) { for ( BasicBlock :: iterator II = BI -> begin ( ) , IE = BI -> end ( ) ; II != IE ; ++ II ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( II ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( <NUM_LIT> ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( II ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) {"
LLVM,NVPTX,1335,"Predict the next statement of this code snippet:
 <s> SmallVector < MemIntrinsic * , <NUM_LIT> > MemCalls ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; LLVMContext & Context = F . getParent ( ) -> getContext ( ) ; const TargetTransformInfo & TTI = getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; for ( Function :: iterator BI = F . begin ( ) , BE = F . end ( ) ; BI != BE ; ++ BI ) { for ( BasicBlock :: iterator II = BI -> begin ( ) , IE = BI -> end ( ) ; II != IE ; ++ II ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( II ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( <NUM_LIT> ) != LI ) continue ; AggrLoads . push_back ( LI ) ;"
LLVM,NVPTX,1336,"Predict the next statement of this code snippet:
 <s> for ( Function :: iterator BI = F . begin ( ) , BE = F . end ( ) ; BI != BE ; ++ BI ) { for ( BasicBlock :: iterator II = BI -> begin ( ) , IE = BI -> end ( ) ; II != IE ; ++ II ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( II ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( <NUM_LIT> ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( II ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ; } } } } if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ; } for ( LoadInst * LI : AggrLoads ) { StoreInst * SI = dyn_cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( <NUM_LIT> ) ; Value * DstAddr = SI -> getOperand ( <NUM_LIT> ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; ConstantInt * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; if ( ! TTI . useWideIRMemcpyLoopLowering ( ) ) { createMemCpyLoop ( SI , SrcAddr , DstAddr , CopyLen , LI -> getAlignment ( ) , SI -> getAlignment ( ) , LI -> isVolatile ( ) , SI -> isVolatile ( ) ) ; } else { createMemCpyLoopKnownSize ( SI , SrcAddr , DstAddr , CopyLen , LI -> getAlignment ( ) , SI -> getAlignment ( ) , LI -> isVolatile ( ) , SI -> isVolatile ( ) , TTI ) ; } SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; } for ( MemIntrinsic * MemCall : MemCalls ) { if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( MemCall ) ) { expandMemCpyAsLoop ( Memcpy , TTI ) ; } else if ( MemMoveInst * Memmove = dyn_cast < MemMoveInst > ( MemCall ) ) { expandMemMoveAsLoop ( Memmove ) ; } else if ( MemSetInst * Memset = dyn_cast < MemSetInst > ( MemCall ) ) {"
LLVM,NVPTX,1337,"Predict the next statement of this code snippet:
 <s> BasicBlock * loopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , newBB ) ; origBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , loopBB ) ; IRBuilder < > builder ( origBB , origBB -> getTerminator ( ) ) ; unsigned dstAS = dyn_cast < PointerType > ( dstAddr -> getType ( ) ) -> getAddressSpace ( ) ; dstAddr = builder . CreateBitCast ( dstAddr , PointerType :: get ( val -> getType ( ) , dstAS ) ) ; IRBuilder < > loop ( loopBB ) ; PHINode * ind = loop . CreatePHI ( len -> getType ( ) , <NUM_LIT> ) ; ind -> addIncoming ( ConstantInt :: get ( len -> getType ( ) , <NUM_LIT> ) , origBB ) ; loop . CreateStore ( val , loop . CreateGEP ( dstAddr , ind ) , false ) ; Value * newind = loop . CreateAdd ( ind , ConstantInt :: get ( len -> getType ( ) , <NUM_LIT> ) ) ;"
LLVM,NVPTX,1338,"Predict the next statement of this code snippet:
 <s> Type * indType = len -> getType ( ) ; BasicBlock * origBB = splitAt -> getParent ( ) ; BasicBlock * newBB = splitAt -> getParent ( ) -> splitBasicBlock ( splitAt , <STR_LIT> ) ; BasicBlock * loopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , newBB ) ; origBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , loopBB ) ; IRBuilder < > builder ( origBB , origBB -> getTerminator ( ) ) ; unsigned srcAS = dyn_cast < PointerType > ( srcAddr -> getType ( ) ) -> getAddressSpace ( ) ; unsigned dstAS = dyn_cast < PointerType > ( dstAddr -> getType ( ) ) -> getAddressSpace ( ) ; srcAddr = builder . CreateBitCast ( srcAddr , Type :: getInt8PtrTy ( Context , srcAS ) ) ; dstAddr = builder . CreateBitCast ( dstAddr , Type :: getInt8PtrTy ( Context , dstAS ) ) ; IRBuilder < > loop ( loopBB ) ; PHINode * ind = loop . CreatePHI ( indType , <NUM_LIT> ) ; ind -> addIncoming ( ConstantInt :: get ( indType , <NUM_LIT> ) , origBB ) ; Value * val = loop . CreateLoad ( loop . CreateGEP ( srcAddr , ind ) , srcVolatile ) ; loop . CreateStore ( val , loop . CreateGEP ( dstAddr , ind ) , dstVolatile ) ; Value * newind = loop . CreateAdd ( ind , ConstantInt :: get ( indType , <NUM_LIT> ) ) ; ind -> addIncoming ( newind , loopBB ) ; loop . CreateCondBr ( loop . CreateICmpULT ( newind , len ) , loopBB , newBB ) ;"
LLVM,NVPTX,1339,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,1340,"Predict the next statement of this code snippet:
 <s> aggrMemcpys . push_back ( intr ) ; } } else { aggrMemcpys . push_back ( intr ) ; } } else if ( MemSetInst * memsetintr = dyn_cast < MemSetInst > ( II ) ) { Value * len = memsetintr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemsets . push_back ( memsetintr ) ; } } else { aggrMemsets . push_back ( memsetintr ) ; } } } } if ( ( aggrLoads . size ( ) == <NUM_LIT> ) && ( aggrMemcpys . size ( ) == <NUM_LIT> ) && ( aggrMemsets . size ( ) == <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> , e = aggrLoads . size ( ) ; i != e ; ++ i ) { LoadInst * load = aggrLoads [ i ] ; StoreInst * store = dyn_cast < StoreInst > ( * load -> user_begin ( ) ) ; Value * srcAddr = load -> getOperand ( <NUM_LIT> ) ; Value * dstAddr = store -> getOperand ( <NUM_LIT> ) ; unsigned numLoads = DL -> getTypeStoreSize ( load -> getType ( ) ) ; Value * len = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , numLoads ) ; convertTransferToLoop ( store , srcAddr , dstAddr , len , load -> isVolatile ( ) , store -> isVolatile ( ) , Context , F ) ; store -> eraseFromParent ( ) ; load -> eraseFromParent ( ) ; } for ( unsigned i = <NUM_LIT> , e = aggrMemcpys . size ( ) ; i != e ; ++ i ) {"
LLVM,NVPTX,1341,"Predict the next statement of this code snippet:
 <s> BasicBlock * loopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , newBB ) ; origBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , loopBB ) ; IRBuilder < > builder ( origBB , origBB -> getTerminator ( ) ) ; unsigned srcAS = dyn_cast < PointerType > ( srcAddr -> getType ( ) ) -> getAddressSpace ( ) ; unsigned dstAS = dyn_cast < PointerType > ( dstAddr -> getType ( ) ) -> getAddressSpace ( ) ; srcAddr = builder . CreateBitCast ( srcAddr , Type :: getInt8PtrTy ( Context , srcAS ) ) ; dstAddr = builder . CreateBitCast ( dstAddr , Type :: getInt8PtrTy ( Context , dstAS ) ) ; IRBuilder < > loop ( loopBB ) ; PHINode * ind = loop . CreatePHI ( indType , <NUM_LIT> ) ; ind -> addIncoming ( ConstantInt :: get ( indType , <NUM_LIT> ) , origBB ) ;"
LLVM,NVPTX,1342,"Predict the next statement of this code snippet:
 <s> LLVMContext & Context = F . getParent ( ) -> getContext ( ) ; for ( Function :: iterator BI = F . begin ( ) , BE = F . end ( ) ; BI != BE ; ++ BI ) { for ( BasicBlock :: iterator II = BI -> begin ( ) , IE = BI -> end ( ) ; II != IE ; ++ II ) { if ( LoadInst * load = dyn_cast < LoadInst > ( II ) ) { if ( load -> hasOneUse ( ) == false ) continue ; if ( TD -> getTypeStoreSize ( load -> getType ( ) ) < MaxAggrCopySize ) continue ; User * use = * ( load -> use_begin ( ) ) ; if ( StoreInst * store = dyn_cast < StoreInst > ( use ) ) { if ( store -> getOperand ( <NUM_LIT> ) != load ) continue ; aggrLoads . push_back ( load ) ; } } else if ( MemTransferInst * intr = dyn_cast < MemTransferInst > ( II ) ) { Value * len = intr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemcpys . push_back ( intr ) ; } } else { aggrMemcpys . push_back ( intr ) ; } } else if ( MemSetInst * memsetintr = dyn_cast < MemSetInst > ( II ) ) { Value * len = memsetintr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) {"
LLVM,NVPTX,1343,"Predict the next statement of this code snippet:
 <s> BasicBlock * newBB = splitAt -> getParent ( ) -> splitBasicBlock ( splitAt , <STR_LIT> ) ; BasicBlock * loopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , newBB ) ; origBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , loopBB ) ; IRBuilder < > builder ( origBB , origBB -> getTerminator ( ) ) ;"
LLVM,NVPTX,1344,"Predict the next statement of this code snippet:
 <s> BasicBlock * origBB = splitAt -> getParent ( ) ; BasicBlock * newBB = splitAt -> getParent ( ) -> splitBasicBlock ( splitAt , <STR_LIT> ) ; BasicBlock * loopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , newBB ) ; origBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , loopBB ) ; IRBuilder < > builder ( origBB , origBB -> getTerminator ( ) ) ; unsigned dstAS = cast < PointerType > ( dstAddr -> getType ( ) ) -> getAddressSpace ( ) ; dstAddr = builder . CreateBitCast ( dstAddr , PointerType :: get ( val -> getType ( ) , dstAS ) ) ; IRBuilder < > loop ( loopBB ) ; PHINode * ind = loop . CreatePHI ( len -> getType ( ) , <NUM_LIT> ) ; ind -> addIncoming ( ConstantInt :: get ( len -> getType ( ) , <NUM_LIT> ) , origBB ) ; loop . CreateStore ( val , loop . CreateGEP ( val -> getType ( ) , dstAddr , ind ) , false ) ;"
LLVM,NVPTX,1345,"Predict the next statement of this code snippet:
 <s> PHINode * ind = loop . CreatePHI ( indType , <NUM_LIT> ) ; ind -> addIncoming ( ConstantInt :: get ( indType , <NUM_LIT> ) , origBB ) ; Value * val = loop . CreateLoad ( loop . CreateGEP ( loop . getInt8Ty ( ) , srcAddr , ind ) , srcVolatile ) ; loop . CreateStore ( val , loop . CreateGEP ( loop . getInt8Ty ( ) , dstAddr , ind ) , dstVolatile ) ;"
LLVM,NVPTX,1346,"Predict the next statement of this code snippet:
 <s> aggrLoads . push_back ( load ) ; } } else if ( MemTransferInst * intr = dyn_cast < MemTransferInst > ( II ) ) { Value * len = intr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemcpys . push_back ( intr ) ; } } else { aggrMemcpys . push_back ( intr ) ; } } else if ( MemSetInst * memsetintr = dyn_cast < MemSetInst > ( II ) ) { Value * len = memsetintr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemsets . push_back ( memsetintr ) ; } } else { aggrMemsets . push_back ( memsetintr ) ; } } } } if ( ( aggrLoads . size ( ) == <NUM_LIT> ) && ( aggrMemcpys . size ( ) == <NUM_LIT> ) && ( aggrMemsets . size ( ) == <NUM_LIT> ) ) return false ; for ( LoadInst * load : aggrLoads ) { StoreInst * store = dyn_cast < StoreInst > ( * load -> user_begin ( ) ) ; Value * srcAddr = load -> getOperand ( <NUM_LIT> ) ; Value * dstAddr = store -> getOperand ( <NUM_LIT> ) ; unsigned numLoads = DL . getTypeStoreSize ( load -> getType ( ) ) ; Value * len = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , numLoads ) ; convertTransferToLoop ( store , srcAddr , dstAddr , len , load -> isVolatile ( ) , store -> isVolatile ( ) , Context , F ) ; store -> eraseFromParent ( ) ; load -> eraseFromParent ( ) ; } for ( MemTransferInst * cpy : aggrMemcpys ) { convertTransferToLoop ( cpy , cpy -> getSource ( ) , cpy -> getDest ( ) , cpy -> getLength ( ) , cpy -> isVolatile ( ) , cpy -> isVolatile ( ) , Context , F ) ; cpy -> eraseFromParent ( ) ; } for ( MemSetInst * memsetinst : aggrMemsets ) { Value * len = memsetinst -> getLength ( ) ; Value * val = memsetinst -> getValue ( ) ; convertMemSetToLoop ( memsetinst , memsetinst -> getDest ( ) , len , val , Context , F ) ; memsetinst -> eraseFromParent ( ) ; } return true ;"
LLVM,NVPTX,1347,"Predict the next statement of this code snippet:
 <s> if ( LoadInst * load = dyn_cast < LoadInst > ( II ) ) { if ( load -> hasOneUse ( ) == false ) continue ; if ( TD -> getTypeStoreSize ( load -> getType ( ) ) < MaxAggrCopySize ) continue ; User * use = * ( load -> use_begin ( ) ) ; if ( StoreInst * store = dyn_cast < StoreInst > ( use ) ) { if ( store -> getOperand ( <NUM_LIT> ) != load ) continue ; aggrLoads . push_back ( load ) ; } } else if ( MemTransferInst * intr = dyn_cast < MemTransferInst > ( II ) ) { Value * len = intr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemcpys . push_back ( intr ) ; } } else { aggrMemcpys . push_back ( intr ) ; } } else if ( MemSetInst * memsetintr = dyn_cast < MemSetInst > ( II ) ) { Value * len = memsetintr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemsets . push_back ( memsetintr ) ; } } else { aggrMemsets . push_back ( memsetintr ) ; } } } } if ( ( aggrLoads . size ( ) == <NUM_LIT> ) && ( aggrMemcpys . size ( ) == <NUM_LIT> ) && ( aggrMemsets . size ( ) == <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> , e = aggrLoads . size ( ) ; i != e ; ++ i ) { LoadInst * load = aggrLoads [ i ] ; StoreInst * store = dyn_cast < StoreInst > ( * load -> use_begin ( ) ) ; Value * srcAddr = load -> getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,1348,"Predict the next statement of this code snippet:
 <s> ++ II ) { if ( LoadInst * load = dyn_cast < LoadInst > ( II ) ) { if ( ! load -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( load -> getType ( ) ) < MaxAggrCopySize ) continue ; User * use = load -> user_back ( ) ; if ( StoreInst * store = dyn_cast < StoreInst > ( use ) ) { if ( store -> getOperand ( <NUM_LIT> ) != load ) continue ; aggrLoads . push_back ( load ) ; } } else if ( MemTransferInst * intr = dyn_cast < MemTransferInst > ( II ) ) { Value * len = intr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemcpys . push_back ( intr ) ; } } else { aggrMemcpys . push_back ( intr ) ; } } else if ( MemSetInst * memsetintr = dyn_cast < MemSetInst > ( II ) ) { Value * len = memsetintr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemsets . push_back ( memsetintr ) ; } } else { aggrMemsets . push_back ( memsetintr ) ; } } } } if ( ( aggrLoads . size ( ) == <NUM_LIT> ) && ( aggrMemcpys . size ( ) == <NUM_LIT> ) && ( aggrMemsets . size ( ) == <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> , e = aggrLoads . size ( ) ; i != e ; ++ i ) { LoadInst * load = aggrLoads [ i ] ; StoreInst * store = dyn_cast < StoreInst > ( * load -> user_begin ( ) ) ; Value * srcAddr = load -> getOperand ( <NUM_LIT> ) ; Value * dstAddr = store -> getOperand ( <NUM_LIT> ) ; unsigned numLoads = DL . getTypeStoreSize ( load -> getType ( ) ) ; Value * len = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , numLoads ) ;"
LLVM,NVPTX,1349,"Predict the next statement of this code snippet:
 <s> if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ; } } } } if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ; } for ( LoadInst * LI : AggrLoads ) { StoreInst * SI = dyn_cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( <NUM_LIT> ) ; Value * DstAddr = SI -> getOperand ( <NUM_LIT> ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; Value * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ;"
LLVM,NVPTX,1350,"Predict the next statement of this code snippet:
 <s> LLVMContext & Context = F . getParent ( ) -> getContext ( ) ; const TargetTransformInfo & TTI = getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; for ( Function :: iterator BI = F . begin ( ) , BE = F . end ( ) ; BI != BE ; ++ BI ) { for ( BasicBlock :: iterator II = BI -> begin ( ) , IE = BI -> end ( ) ; II != IE ; ++ II ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( II ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( <NUM_LIT> ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( II ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ;"
LLVM,NVPTX,1351,"Predict the next statement of this code snippet:
 <s> if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ; } for ( LoadInst * LI : AggrLoads ) { auto * SI = cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( <NUM_LIT> ) ; Value * DstAddr = SI -> getOperand ( <NUM_LIT> ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; ConstantInt * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; createMemCpyLoopKnownSize ( SI , SrcAddr , DstAddr , CopyLen , LI -> getAlign ( ) , SI -> getAlign ( ) , LI -> isVolatile ( ) , SI -> isVolatile ( ) , TTI ) ; SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; } for ( MemIntrinsic * MemCall : MemCalls ) { if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( MemCall ) ) { expandMemCpyAsLoop ( Memcpy , TTI ) ; } else if ( MemMoveInst * Memmove = dyn_cast < MemMoveInst > ( MemCall ) ) {"
LLVM,NVPTX,1352,"Predict the next statement of this code snippet:
 <s> SmallVector < LoadInst * , <NUM_LIT> > AggrLoads ; SmallVector < MemIntrinsic * , <NUM_LIT> > MemCalls ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; LLVMContext & Context = F . getParent ( ) -> getContext ( ) ; const TargetTransformInfo & TTI = getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( & I ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( <NUM_LIT> ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( & I ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ; } } } } if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ; } for ( LoadInst * LI : AggrLoads ) { auto * SI = cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( <NUM_LIT> ) ; Value * DstAddr = SI -> getOperand ( <NUM_LIT> ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; ConstantInt * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; createMemCpyLoopKnownSize ( SI , SrcAddr , DstAddr , CopyLen , LI -> getAlign ( ) , SI -> getAlign ( ) , LI -> isVolatile ( ) , SI -> isVolatile ( ) , TTI ) ; SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; } for ( MemIntrinsic * MemCall : MemCalls ) { if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( MemCall ) ) { expandMemCpyAsLoop ( Memcpy , TTI ) ; } else if ( MemMoveInst * Memmove = dyn_cast < MemMoveInst > ( MemCall ) ) { expandMemMoveAsLoop ( Memmove ) ; } else if ( MemSetInst * Memset = dyn_cast < MemSetInst > ( MemCall ) ) { expandMemSetAsLoop ( Memset ) ; } MemCall -> eraseFromParent ( ) ; }"
LLVM,NVPTX,1353,"Predict the next statement of this code snippet:
 <s> ind -> addIncoming ( ConstantInt :: get ( len -> getType ( ) , <NUM_LIT> ) , origBB ) ; loop . CreateStore ( val , loop . CreateGEP ( val -> getType ( ) , dstAddr , ind ) , false ) ; Value * newind = loop . CreateAdd ( ind , ConstantInt :: get ( len -> getType ( ) , <NUM_LIT> ) ) ; ind -> addIncoming ( newind , loopBB ) ;"
LLVM,NVPTX,1354,"Predict the next statement of this code snippet:
 <s> BasicBlock * origBB = splitAt -> getParent ( ) ; BasicBlock * newBB = splitAt -> getParent ( ) -> splitBasicBlock ( splitAt , <STR_LIT> ) ; BasicBlock * loopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , newBB ) ; origBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , loopBB ) ; IRBuilder < > builder ( origBB , origBB -> getTerminator ( ) ) ; unsigned dstAS = dyn_cast < PointerType > ( dstAddr -> getType ( ) ) -> getAddressSpace ( ) ; dstAddr = builder . CreateBitCast ( dstAddr , PointerType :: get ( val -> getType ( ) , dstAS ) ) ; IRBuilder < > loop ( loopBB ) ; PHINode * ind = loop . CreatePHI ( len -> getType ( ) , <NUM_LIT> ) ; ind -> addIncoming ( ConstantInt :: get ( len -> getType ( ) , <NUM_LIT> ) , origBB ) ; loop . CreateStore ( val , loop . CreateGEP ( val -> getType ( ) , dstAddr , ind ) , false ) ; Value * newind = loop . CreateAdd ( ind , ConstantInt :: get ( len -> getType ( ) , <NUM_LIT> ) ) ; ind -> addIncoming ( newind , loopBB ) ; loop . CreateCondBr ( loop . CreateICmpULT ( newind , len ) , loopBB , newBB ) ;"
LLVM,NVPTX,1355,"Predict the next statement of this code snippet:
 <s> unsigned srcAS = dyn_cast < PointerType > ( srcAddr -> getType ( ) ) -> getAddressSpace ( ) ; unsigned dstAS = dyn_cast < PointerType > ( dstAddr -> getType ( ) ) -> getAddressSpace ( ) ; srcAddr = builder . CreateBitCast ( srcAddr , Type :: getInt8PtrTy ( Context , srcAS ) ) ; dstAddr = builder . CreateBitCast ( dstAddr , Type :: getInt8PtrTy ( Context , dstAS ) ) ; IRBuilder < > loop ( loopBB ) ; PHINode * ind = loop . CreatePHI ( indType , <NUM_LIT> ) ; ind -> addIncoming ( ConstantInt :: get ( indType , <NUM_LIT> ) , origBB ) ; Value * val = loop . CreateLoad ( loop . CreateGEP ( loop . getInt8Ty ( ) , srcAddr , ind ) , srcVolatile ) ; loop . CreateStore ( val , loop . CreateGEP ( loop . getInt8Ty ( ) , dstAddr , ind ) , dstVolatile ) ; Value * newind = loop . CreateAdd ( ind , ConstantInt :: get ( indType , <NUM_LIT> ) ) ;"
LLVM,NVPTX,1356,"Predict the next statement of this code snippet:
 <s> unsigned SrcAS = cast < PointerType > ( SrcAddr -> getType ( ) ) -> getAddressSpace ( ) ; unsigned DstAS = cast < PointerType > ( DstAddr -> getType ( ) ) -> getAddressSpace ( ) ; SrcAddr = Builder . CreateBitCast ( SrcAddr , Builder . getInt8PtrTy ( SrcAS ) ) ; DstAddr = Builder . CreateBitCast ( DstAddr , Builder . getInt8PtrTy ( DstAS ) ) ; IRBuilder < > LoopBuilder ( LoopBB ) ; PHINode * LoopIndex = LoopBuilder . CreatePHI ( TypeOfCopyLen , <NUM_LIT> ) ; LoopIndex -> addIncoming ( ConstantInt :: get ( TypeOfCopyLen , <NUM_LIT> ) , OrigBB ) ; Value * Element = LoopBuilder . CreateLoad ( LoopBuilder . CreateInBoundsGEP ( LoopBuilder . getInt8Ty ( ) , SrcAddr , LoopIndex ) , SrcIsVolatile ) ; LoopBuilder . CreateStore ( Element , LoopBuilder . CreateInBoundsGEP ( LoopBuilder . getInt8Ty ( ) , DstAddr , LoopIndex ) , DstIsVolatile ) ; Value * NewIndex = LoopBuilder . CreateAdd ( LoopIndex , ConstantInt :: get ( TypeOfCopyLen , <NUM_LIT> ) ) ; LoopIndex -> addIncoming ( NewIndex , LoopBB ) ; LoopBuilder . CreateCondBr ( LoopBuilder . CreateICmpULT ( NewIndex , CopyLen ) , LoopBB , NewBB ) ;"
LLVM,NVPTX,1357,"Predict the next statement of this code snippet:
 <s> BasicBlock * ExitBB = ConvertedInst -> getParent ( ) ; ExitBB -> setName ( <STR_LIT> ) ; ICmpInst * CompareN = new ICmpInst ( OrigBB -> getTerminator ( ) , ICmpInst :: ICMP_EQ , CopyLen , ConstantInt :: get ( TypeOfCopyLen , <NUM_LIT> ) , <STR_LIT> ) ; BasicBlock * LoopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , CopyForwardBB ) ; IRBuilder < > LoopBuilder ( LoopBB ) ; PHINode * LoopPhi = LoopBuilder . CreatePHI ( TypeOfCopyLen , <NUM_LIT> ) ; Value * IndexPtr = LoopBuilder . CreateSub ( LoopPhi , ConstantInt :: get ( TypeOfCopyLen , <NUM_LIT> ) , <STR_LIT> ) ; Value * Element = LoopBuilder . CreateLoad ( LoopBuilder . CreateInBoundsGEP ( SrcAddr , IndexPtr ) , <STR_LIT> ) ; LoopBuilder . CreateStore ( Element , LoopBuilder . CreateInBoundsGEP ( DstAddr , IndexPtr ) ) ; LoopBuilder . CreateCondBr ( LoopBuilder . CreateICmpEQ ( IndexPtr , ConstantInt :: get ( TypeOfCopyLen , <NUM_LIT> ) ) , ExitBB , LoopBB ) ; LoopPhi -> addIncoming ( IndexPtr , LoopBB ) ; LoopPhi -> addIncoming ( CopyLen , CopyBackwardsBB ) ; BranchInst :: Create ( ExitBB , LoopBB , CompareN , ThenTerm ) ; ThenTerm -> eraseFromParent ( ) ; BasicBlock * FwdLoopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , ExitBB ) ; IRBuilder < > FwdLoopBuilder ( FwdLoopBB ) ;"
LLVM,NVPTX,1358,"Predict the next statement of this code snippet:
 <s> BasicBlock * NewBB = ConvertedInst -> getParent ( ) -> splitBasicBlock ( ConvertedInst , <STR_LIT> ) ; BasicBlock * LoopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , NewBB ) ; OrigBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , LoopBB ) ; IRBuilder < > Builder ( OrigBB , OrigBB -> getTerminator ( ) ) ; unsigned dstAS = cast < PointerType > ( DstAddr -> getType ( ) ) -> getAddressSpace ( ) ; DstAddr = Builder . CreateBitCast ( DstAddr , PointerType :: get ( SetValue -> getType ( ) , dstAS ) ) ; IRBuilder < > LoopBuilder ( LoopBB ) ;"
LLVM,NVPTX,1359,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>LowerAggrCopies ( ) ;"
LLVM,NVPTX,1360,"Predict the next statement of this code snippet:
 <s> const char * getPassName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1361,"Predict the next statement of this code snippet:
 <s> const char * getPassName ( ) const override {"
LLVM,NVPTX,1362,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerAggrCopies ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,1363,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerAggrCopies ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,1364,"Predict the next statement of this code snippet:
 <s> } if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ; } for ( LoadInst * LI : AggrLoads ) { StoreInst * SI = dyn_cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( <NUM_LIT> ) ; Value * DstAddr = SI -> getOperand ( <NUM_LIT> ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; Value * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; convertMemCpyToLoop ( SI , SrcAddr , DstAddr , CopyLen , LI -> isVolatile ( ) , SI -> isVolatile ( ) , Context , F ) ; SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; } for ( MemIntrinsic * MemCall : MemCalls ) { if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( MemCall ) ) { convertMemCpyToLoop ( Memcpy , Memcpy -> getRawSource ( ) , Memcpy -> getRawDest ( ) , Memcpy -> getLength ( ) , Memcpy -> isVolatile ( ) , Memcpy -> isVolatile ( ) , Context , F ) ;"
LLVM,NVPTX,1365,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>LowerAggrCopies :: runOnFunction ( Function & F ) { SmallVector < LoadInst * , <NUM_LIT> > AggrLoads ; SmallVector < MemIntrinsic * , <NUM_LIT> > MemCalls ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; LLVMContext & Context = F . getParent ( ) -> getContext ( ) ; for ( Function :: iterator BI = F . begin ( ) , BE = F . end ( ) ; BI != BE ; ++ BI ) { for ( BasicBlock :: iterator II = BI -> begin ( ) , IE = BI -> end ( ) ; II != IE ; ++ II ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( II ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( <NUM_LIT> ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( II ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ; } } } } if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ; } for ( LoadInst * LI : AggrLoads ) { StoreInst * SI = dyn_cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( <NUM_LIT> ) ; Value * DstAddr = SI -> getOperand ( <NUM_LIT> ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; Value * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; convertMemCpyToLoop ( SI , SrcAddr , DstAddr , CopyLen , LI -> isVolatile ( ) , SI -> isVolatile ( ) , Context , F ) ; SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; } for ( MemIntrinsic * MemCall : MemCalls ) {"
LLVM,NVPTX,1366,"Predict the next statement of this code snippet:
 <s> BasicBlockPass * llvm :: create<ISA_LIT>LowerAllocaPass ( ) { return new <ISA_LIT>LowerAlloca ( ) ;"
LLVM,NVPTX,1367,"Predict the next statement of this code snippet:
 <s> BasicBlockPass * llvm :: create<ISA_LIT>LowerAllocaPass ( ) {"
LLVM,NVPTX,1368,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerAlloca ( ) : BasicBlockPass ( ID ) {"
LLVM,NVPTX,1369,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerAlloca ( ) : BasicBlockPass ( ID ) {"
LLVM,NVPTX,1370,"Predict the next statement of this code snippet:
 <s> NewASCToGeneric -> insertAfter ( NewASCToLocal ) ; for ( Value :: use_iterator UI = allocaInst -> use_begin ( ) , UE = allocaInst -> use_end ( ) ; UI != UE ; ) { const auto & AllocaUse = * UI ++ ; auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto GI = dyn_cast < GetElementPtrInst > ( AllocaUse . getUser ( ) ) ; if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto BI = dyn_cast < BitCastInst > ( AllocaUse . getUser ( ) ) ; if ( BI && BI -> getOperand ( <NUM_LIT> ) == allocaInst ) { BI -> setOperand ( <NUM_LIT> , NewASCToGeneric ) ;"
LLVM,NVPTX,1371,"Predict the next statement of this code snippet:
 <s> UI != UE ; ) { const auto & AllocaUse = * UI ++ ; auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ;"
LLVM,NVPTX,1372,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>LowerAlloca ( ) ;"
LLVM,NVPTX,1373,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,1374,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,1375,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerAlloca ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,1376,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerAlloca ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,1377,"Predict the next statement of this code snippet:
 <s> bool Changed = false ; for ( auto & BB : F ) for ( auto & I : BB ) { if ( auto allocaInst = dyn_cast < AllocaInst > ( & I ) ) { Changed = true ; auto ETy = cast < PointerType > ( allocaInst -> getType ( ) ) -> getElementType ( ) ; auto LocalAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_LOCAL ) ; auto NewASCToLocal = new AddrSpaceCastInst ( allocaInst , LocalAddrTy , <STR_LIT> ) ; auto GenericAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_GENERIC ) ; auto NewASCToGeneric = new AddrSpaceCastInst ( NewASCToLocal , GenericAddrTy , <STR_LIT> ) ; NewASCToLocal -> insertAfter ( allocaInst ) ; NewASCToGeneric -> insertAfter ( NewASCToLocal ) ; for ( Value :: use_iterator UI = allocaInst -> use_begin ( ) , UE = allocaInst -> use_end ( ) ; UI != UE ; ) { const auto & AllocaUse = * UI ++ ; auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto GI = dyn_cast < GetElementPtrInst > ( AllocaUse . getUser ( ) ) ; if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto BI = dyn_cast < BitCastInst > ( AllocaUse . getUser ( ) ) ; if ( BI && BI -> getOperand ( <NUM_LIT> ) == allocaInst ) {"
LLVM,NVPTX,1378,"Predict the next statement of this code snippet:
 <s> UI != UE ; ) { const auto & AllocaUse = * UI ++ ; auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto GI = dyn_cast < GetElementPtrInst > ( AllocaUse . getUser ( ) ) ; if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ;"
LLVM,NVPTX,1379,"Predict the next statement of this code snippet:
 <s> if ( skipBasicBlock ( BB ) ) return false ; bool Changed = false ; for ( auto & I : BB ) { if ( auto allocaInst = dyn_cast < AllocaInst > ( & I ) ) { Changed = true ; auto PTy = dyn_cast < PointerType > ( allocaInst -> getType ( ) ) ; auto ETy = PTy -> getElementType ( ) ; auto LocalAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_LOCAL ) ; auto NewASCToLocal = new AddrSpaceCastInst ( allocaInst , LocalAddrTy , <STR_LIT> ) ; auto GenericAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_GENERIC ) ; auto NewASCToGeneric = new AddrSpaceCastInst ( NewASCToLocal , GenericAddrTy , <STR_LIT> ) ; NewASCToLocal -> insertAfter ( allocaInst ) ; NewASCToGeneric -> insertAfter ( NewASCToLocal ) ; for ( Value :: use_iterator UI = allocaInst -> use_begin ( ) , UE = allocaInst -> use_end ( ) ; UI != UE ; ) { const auto & AllocaUse = * UI ++ ; auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; }"
LLVM,NVPTX,1380,"Predict the next statement of this code snippet:
 <s> Changed = true ; auto ETy = allocaInst -> getAllocatedType ( ) ; auto LocalAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_LOCAL ) ; auto NewASCToLocal = new AddrSpaceCastInst ( allocaInst , LocalAddrTy , <STR_LIT> ) ; auto GenericAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_GENERIC ) ; auto NewASCToGeneric = new AddrSpaceCastInst ( NewASCToLocal , GenericAddrTy , <STR_LIT> ) ; NewASCToLocal -> insertAfter ( allocaInst ) ; NewASCToGeneric -> insertAfter ( NewASCToLocal ) ; for ( Use & AllocaUse : llvm :: make_early_inc_range ( allocaInst -> uses ( ) ) ) { auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto GI = dyn_cast < GetElementPtrInst > ( AllocaUse . getUser ( ) ) ; if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto BI = dyn_cast < BitCastInst > ( AllocaUse . getUser ( ) ) ; if ( BI && BI -> getOperand ( <NUM_LIT> ) == allocaInst ) { BI -> setOperand ( <NUM_LIT> , NewASCToGeneric ) ;"
LLVM,NVPTX,1381,"Predict the next statement of this code snippet:
 <s> if ( skipFunction ( F ) ) return false ; bool Changed = false ; for ( auto & BB : F ) for ( auto & I : BB ) { if ( auto allocaInst = dyn_cast < AllocaInst > ( & I ) ) { Changed = true ; auto ETy = allocaInst -> getAllocatedType ( ) ; auto LocalAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_LOCAL ) ; auto NewASCToLocal = new AddrSpaceCastInst ( allocaInst , LocalAddrTy , <STR_LIT> ) ; auto GenericAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_GENERIC ) ; auto NewASCToGeneric = new AddrSpaceCastInst ( NewASCToLocal , GenericAddrTy , <STR_LIT> ) ; NewASCToLocal -> insertAfter ( allocaInst ) ; NewASCToGeneric -> insertAfter ( NewASCToLocal ) ; for ( Value :: use_iterator UI = allocaInst -> use_begin ( ) , UE = allocaInst -> use_end ( ) ; UI != UE ; ) { const auto & AllocaUse = * UI ++ ; auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto GI = dyn_cast < GetElementPtrInst > ( AllocaUse . getUser ( ) ) ; if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto BI = dyn_cast < BitCastInst > ( AllocaUse . getUser ( ) ) ;"
LLVM,NVPTX,1382,"Predict the next statement of this code snippet:
 <s> static void convertToParamAS ( Value * OldUser , Value * Param ) { Instruction * I = dyn_cast < Instruction > ( OldUser ) ; assert ( I && <STR_LIT> ) ; struct IP { Instruction * OldInstruction ; Value * NewParam ; } ; SmallVector < IP > ItemsToConvert = { { I , Param } } ; SmallVector < Instruction * > InstructionsToDelete ; auto CloneInstInParamAS = [ ] ( const IP & I ) -> Value * { if ( auto * LI = dyn_cast < LoadInst > ( I . OldInstruction ) ) { LI -> setOperand ( <NUM_LIT> , I . NewParam ) ; return LI ; } if ( auto * GEP = dyn_cast < GetElementPtrInst > ( I . OldInstruction ) ) { SmallVector < Value * , <NUM_LIT> > Indices ( GEP -> indices ( ) ) ; auto * NewGEP = GetElementPtrInst :: Create ( GEP -> getSourceElementType ( ) , I . NewParam , Indices , GEP -> getName ( ) , GEP ) ; NewGEP -> setIsInBounds ( GEP -> isInBounds ( ) ) ; return NewGEP ; } if ( auto * BC = dyn_cast < BitCastInst > ( I . OldInstruction ) ) { auto * NewBCType = PointerType :: getWithSamePointeeType ( cast < PointerType > ( BC -> getType ( ) ) , ADDRESS_SPACE_PARAM ) ; return BitCastInst :: Create ( BC -> getOpcode ( ) , I . NewParam , NewBCType , BC -> getName ( ) , BC ) ; } if ( auto * ASC = dyn_cast < AddrSpaceCastInst > ( I . OldInstruction ) ) { assert ( ASC -> getDestAddressSpace ( ) == ADDRESS_SPACE_PARAM ) ; ( void ) ASC ; return I . NewParam ; } llvm_unreachable ( <STR_LIT> ) ; } ; while ( ! ItemsToConvert . empty ( ) ) { IP I = ItemsToConvert . pop_back_val ( ) ; Value * NewInst = CloneInstInParamAS ( I ) ; if ( NewInst && NewInst != I . OldInstruction ) { llvm :: for_each ( I . OldInstruction -> users ( ) , [ NewInst , & ItemsToConvert ] ( Value * V ) { ItemsToConvert . push_back ( { cast < Instruction > ( V ) , NewInst } ) ;"
LLVM,NVPTX,1383,"Predict the next statement of this code snippet:
 <s> FunctionPass * llvm :: create<ISA_LIT>LowerArgsPass ( const <ISA_LIT>TargetMachine * TM ) { return new <ISA_LIT>LowerArgs ( TM ) ;"
LLVM,NVPTX,1384,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>LowerArgs ( TM ) ;"
LLVM,NVPTX,1385,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1386,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1387,"Predict the next statement of this code snippet:
 <s> SmallVector < Value * , <NUM_LIT> > ValuesToCheck = { Start } ; auto IsALoadChainInstr = [ ] ( Value * V ) -> bool { if ( isa < GetElementPtrInst > ( V ) || isa < BitCastInst > ( V ) || isa < LoadInst > ( V ) ) return true ; if ( auto * ASC = dyn_cast < AddrSpaceCastInst > ( V ) ) { if ( ASC -> getDestAddressSpace ( ) == ADDRESS_SPACE_PARAM ) return true ; } return false ; } ; while ( ! ValuesToCheck . empty ( ) ) { Value * V = ValuesToCheck . pop_back_val ( ) ; if ( ! IsALoadChainInstr ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Arg << <STR_LIT> << * V << <STR_LIT> ) ; ( void ) Arg ; return false ; } if ( ! isa < LoadInst > ( V ) ) llvm :: append_range ( ValuesToCheck , V -> users ( ) ) ; }"
LLVM,NVPTX,1388,"Predict the next statement of this code snippet:
 <s> InsertPt = ++ cast < Instruction > ( Ptr ) -> getIterator ( ) ; assert ( InsertPt != InsertPt -> getParent ( ) -> end ( ) && <STR_LIT> ) ; } Instruction * PtrInGlobal = new AddrSpaceCastInst ( Ptr , PointerType :: getWithSamePointeeType ( cast < PointerType > ( Ptr -> getType ( ) ) , ADDRESS_SPACE_GLOBAL ) , Ptr -> getName ( ) , & * InsertPt ) ;"
LLVM,NVPTX,1389,"Predict the next statement of this code snippet:
 <s> BasicBlock :: iterator InsertPt ; if ( Argument * Arg = dyn_cast < Argument > ( Ptr ) ) { InsertPt = Arg -> getParent ( ) -> getEntryBlock ( ) . begin ( ) ; } else { InsertPt = ++ cast < Instruction > ( Ptr ) -> getIterator ( ) ; assert ( InsertPt != InsertPt -> getParent ( ) -> end ( ) && <STR_LIT> ) ; } Instruction * PtrInGlobal = new AddrSpaceCastInst ( Ptr , PointerType :: getWithSamePointeeType ( cast < PointerType > ( Ptr -> getType ( ) ) , ADDRESS_SPACE_GLOBAL ) , Ptr -> getName ( ) , & * InsertPt ) ; Value * PtrInGeneric = new AddrSpaceCastInst ( PtrInGlobal , Ptr -> getType ( ) , Ptr -> getName ( ) , & * InsertPt ) ; Ptr -> replaceAllUsesWith ( PtrInGeneric ) ; PtrInGlobal -> setOperand ( <NUM_LIT> , Ptr ) ;"
LLVM,NVPTX,1390,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerArgs ( const <ISA_LIT>TargetMachine * TM = nullptr ) : FunctionPass ( ID ) , TM ( TM ) {"
LLVM,NVPTX,1391,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerArgs ( const <ISA_LIT>TargetMachine * TM = nullptr ) : FunctionPass ( ID ) , TM ( TM ) {"
LLVM,NVPTX,1392,"Predict the next statement of this code snippet:
 <s> for ( Argument & Arg : F . args ( ) ) if ( Arg . getType ( ) -> isPointerTy ( ) && Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ; return true ;"
LLVM,NVPTX,1393,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>LowerArgs :: runOnFunction ( Function & F ) { return isKernelFunction ( F ) ? runOnKernelFunction ( F ) : runOnDeviceFunction ( F ) ;"
LLVM,NVPTX,1394,"Predict the next statement of this code snippet:
 <s> return isKernelFunction ( F ) ? runOnKernelFunction ( F ) : runOnDeviceFunction ( F ) ;"
LLVM,NVPTX,1395,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>LowerArgs :: runOnKernelFunction ( Function & F ) { if ( TM && TM -> getDrvInterface ( ) == <STR_LIT> ) { for ( auto & B : F ) { for ( auto & I : B ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( & I ) ) { if ( LI -> getType ( ) -> isPointerTy ( ) ) { Value * UO = getUnderlyingObject ( LI -> getPointerOperand ( ) ) ; if ( Argument * Arg = dyn_cast < Argument > ( UO ) ) { if ( Arg -> hasByValAttr ( ) ) { markPointerAsGlobal ( LI ) ;"
LLVM,NVPTX,1396,"Predict the next statement of this code snippet:
 <s> AllocaInst * AllocA = new AllocaInst ( StructType , AS , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ; Value * ArgInParam = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ;"
LLVM,NVPTX,1397,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>LowerArgs :: handleByValParam ( Argument * Arg ) { Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ;"
LLVM,NVPTX,1398,"Predict the next statement of this code snippet:
 <s> AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) + <NUM_LIT> ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ; Value * ArgInParam = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ;"
LLVM,NVPTX,1399,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>LowerArgs :: handleByValParam ( Argument * Arg ) { Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; unsigned AS = Func -> getParent ( ) -> getDataLayout ( ) . getAllocaAddrSpace ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , AS , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) + <NUM_LIT> ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ; Value * ArgInParam = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ;"
LLVM,NVPTX,1400,"Predict the next statement of this code snippet:
 <s> auto IsALoadChain = [ & ] ( Value * Start ) { SmallVector < Value * , <NUM_LIT> > ValuesToCheck = { Start } ; auto IsALoadChainInstr = [ ] ( Value * V ) -> bool { if ( isa < GetElementPtrInst > ( V ) || isa < BitCastInst > ( V ) || isa < LoadInst > ( V ) ) return true ; if ( auto * ASC = dyn_cast < AddrSpaceCastInst > ( V ) ) { if ( ASC -> getDestAddressSpace ( ) == ADDRESS_SPACE_PARAM ) return true ; } return false ; } ; while ( ! ValuesToCheck . empty ( ) ) { Value * V = ValuesToCheck . pop_back_val ( ) ; if ( ! IsALoadChainInstr ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Arg << <STR_LIT> << * V << <STR_LIT> ) ; ( void ) Arg ;"
LLVM,NVPTX,1401,"Predict the next statement of this code snippet:
 <s> auto IsALoadChainInstr = [ ] ( Value * V ) -> bool { if ( isa < GetElementPtrInst > ( V ) || isa < BitCastInst > ( V ) || isa < LoadInst > ( V ) ) return true ; if ( auto * ASC = dyn_cast < AddrSpaceCastInst > ( V ) ) { if ( ASC -> getDestAddressSpace ( ) == ADDRESS_SPACE_PARAM ) return true ; } return false ; } ; while ( ! ValuesToCheck . empty ( ) ) { Value * V = ValuesToCheck . pop_back_val ( ) ; if ( ! IsALoadChainInstr ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Arg << <STR_LIT> << * V << <STR_LIT> ) ; ( void ) Arg ; return false ; } if ( ! isa < LoadInst > ( V ) ) llvm :: append_range ( ValuesToCheck , V -> users ( ) ) ; } return true ; } ; if ( llvm :: all_of ( Arg -> users ( ) , IsALoadChain ) ) { SmallVector < User * , <NUM_LIT> > UsersToUpdate ( Arg -> users ( ) ) ; Value * ArgInParamAS = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ; llvm :: for_each ( UsersToUpdate , [ ArgInParamAS ] ( Value * V ) { convertToParamAS ( V , ArgInParamAS ) ; } ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Arg << <STR_LIT> ) ; return ; } const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; unsigned AS = DL . getAllocaAddrSpace ( ) ;"
LLVM,NVPTX,1402,"Predict the next statement of this code snippet:
 <s> Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; unsigned AS = DL . getAllocaAddrSpace ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , AS , Arg -> getName ( ) , FirstInst ) ;"
LLVM,NVPTX,1403,"Predict the next statement of this code snippet:
 <s> if ( LoadInst * LI = dyn_cast < LoadInst > ( & I ) ) { if ( LI -> getType ( ) -> isPointerTy ( ) ) { Value * UO = getUnderlyingObject ( LI -> getPointerOperand ( ) ) ; if ( Argument * Arg = dyn_cast < Argument > ( UO ) ) { if ( Arg -> hasByValAttr ( ) ) { markPointerAsGlobal ( LI ) ; } } } } } } } for ( Argument & Arg : F . args ( ) ) {"
LLVM,NVPTX,1404,"Predict the next statement of this code snippet:
 <s> for ( Argument & Arg : F . args ( ) ) { if ( Arg . getType ( ) -> isPointerTy ( ) ) { if ( Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ; else if ( TM && TM -> getDrvInterface ( ) == <STR_LIT> ) markPointerAsGlobal ( & Arg ) ; } }"
LLVM,NVPTX,1405,"Predict the next statement of this code snippet:
 <s> Type * StructType = PType -> getElementType ( ) ; unsigned AS = Func -> getParent ( ) -> getDataLayout ( ) . getAllocaAddrSpace ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , AS , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ;"
LLVM,NVPTX,1406,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>LowerArgs :: handleByValParam ( Argument * Arg ) { Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ;"
LLVM,NVPTX,1407,"Predict the next statement of this code snippet:
 <s> Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ;"
LLVM,NVPTX,1408,"Predict the next statement of this code snippet:
 <s> if ( auto * GEP = dyn_cast < GetElementPtrInst > ( I . OldInstruction ) ) { SmallVector < Value * , <NUM_LIT> > Indices ( GEP -> indices ( ) ) ; auto * NewGEP = GetElementPtrInst :: Create ( nullptr , I . NewParam , Indices , GEP -> getName ( ) , GEP ) ; NewGEP -> setIsInBounds ( GEP -> isInBounds ( ) ) ; return NewGEP ; } if ( auto * BC = dyn_cast < BitCastInst > ( I . OldInstruction ) ) { auto * NewBCType = BC -> getType ( ) -> getPointerElementType ( ) -> getPointerTo ( ADDRESS_SPACE_PARAM ) ; return BitCastInst :: Create ( BC -> getOpcode ( ) , I . NewParam , NewBCType , BC -> getName ( ) , BC ) ; } if ( auto * ASC = dyn_cast < AddrSpaceCastInst > ( I . OldInstruction ) ) { assert ( ASC -> getDestAddressSpace ( ) == ADDRESS_SPACE_PARAM ) ; ( void ) ASC ; return I . NewParam ; } llvm_unreachable ( <STR_LIT> ) ; } ; while ( ! ItemsToConvert . empty ( ) ) { IP I = ItemsToConvert . pop_back_val ( ) ; Value * NewInst = CloneInstInParamAS ( I ) ; if ( NewInst && NewInst != I . OldInstruction ) { llvm :: for_each ( I . OldInstruction -> users ( ) , [ NewInst , & ItemsToConvert ] ( Value * V ) { ItemsToConvert . push_back ( { cast < Instruction > ( V ) , NewInst } ) ; } ) ; InstructionsToDelete . push_back ( I . OldInstruction ) ; } }"
LLVM,NVPTX,1409,"Predict the next statement of this code snippet:
 <s> const char * getPassName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1410,"Predict the next statement of this code snippet:
 <s> const char * getPassName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1411,"Predict the next statement of this code snippet:
 <s> assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) + <NUM_LIT> ) ) ;"
LLVM,NVPTX,1412,"Predict the next statement of this code snippet:
 <s> Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) + <NUM_LIT> ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ; Value * ArgInParam = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ; LoadInst * LI = new LoadInst ( ArgInParam , Arg -> getName ( ) , FirstInst ) ; new StoreInst ( LI , AllocA , FirstInst ) ;"
LLVM,NVPTX,1413,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>LowerArgs :: markPointerAsGlobal ( Value * Ptr ) { if ( Ptr -> getType ( ) -> getPointerAddressSpace ( ) == ADDRESS_SPACE_GLOBAL ) return ; BasicBlock :: iterator InsertPt ; if ( Argument * Arg = dyn_cast < Argument > ( Ptr ) ) { InsertPt = Arg -> getParent ( ) -> getEntryBlock ( ) . begin ( ) ; } else { InsertPt = ++ cast < Instruction > ( Ptr ) -> getIterator ( ) ; assert ( InsertPt != InsertPt -> getParent ( ) -> end ( ) && <STR_LIT> ) ; } Instruction * PtrInGlobal = new AddrSpaceCastInst ( Ptr , PointerType :: get ( Ptr -> getType ( ) -> getPointerElementType ( ) , ADDRESS_SPACE_GLOBAL ) , Ptr -> getName ( ) , & * InsertPt ) ; Value * PtrInGeneric = new AddrSpaceCastInst ( PtrInGlobal , Ptr -> getType ( ) , Ptr -> getName ( ) , & * InsertPt ) ; Ptr -> replaceAllUsesWith ( PtrInGeneric ) ; PtrInGlobal -> setOperand ( <NUM_LIT> , Ptr ) ;"
LLVM,NVPTX,1414,"Predict the next statement of this code snippet:
 <s> InsertPt = ++ cast < Instruction > ( Ptr ) -> getIterator ( ) ; assert ( InsertPt != InsertPt -> getParent ( ) -> end ( ) && <STR_LIT> ) ; } Instruction * PtrInGlobal = new AddrSpaceCastInst ( Ptr , PointerType :: get ( Ptr -> getType ( ) -> getPointerElementType ( ) , ADDRESS_SPACE_GLOBAL ) , Ptr -> getName ( ) , & * InsertPt ) ; Value * PtrInGeneric = new AddrSpaceCastInst ( PtrInGlobal , Ptr -> getType ( ) , Ptr -> getName ( ) , & * InsertPt ) ;"
LLVM,NVPTX,1415,"Predict the next statement of this code snippet:
 <s> for ( Argument & Arg : F . args ( ) ) if ( Arg . getType ( ) -> isPointerTy ( ) && Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ;"
LLVM,NVPTX,1416,"Predict the next statement of this code snippet:
 <s> } } } } } for ( Argument & Arg : F . args ( ) ) { if ( Arg . getType ( ) -> isPointerTy ( ) ) { if ( Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ; else if ( TM && TM -> getDrvInterface ( ) == <STR_LIT> ) markPointerAsGlobal ( & Arg ) ; }"
LLVM,NVPTX,1417,"Predict the next statement of this code snippet:
 <s> Instruction * ArgInGlobal = new AddrSpaceCastInst ( Arg , PointerType :: get ( Arg -> getType ( ) -> getPointerElementType ( ) , ADDRESS_SPACE_GLOBAL ) , Arg -> getName ( ) , FirstInst ) ; Value * ArgInGeneric = new AddrSpaceCastInst ( ArgInGlobal , Arg -> getType ( ) , Arg -> getName ( ) , FirstInst ) ;"
LLVM,NVPTX,1418,"Predict the next statement of this code snippet:
 <s> Value * ArgInGeneric = new AddrSpaceCastInst ( ArgInGlobal , Arg -> getType ( ) , Arg -> getName ( ) , FirstInst ) ; Arg -> replaceAllUsesWith ( ArgInGeneric ) ; ArgInGlobal -> setOperand ( <NUM_LIT> , Arg ) ;"
LLVM,NVPTX,1419,"Predict the next statement of this code snippet:
 <s> if ( Arg . getType ( ) -> isPointerTy ( ) ) { if ( Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ; else if ( TM && TM -> getDrvInterface ( ) == <STR_LIT> ) handlePointerParam ( & Arg ) ; }"
LLVM,NVPTX,1420,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>LowerKernelArgs :: handlePointerParam ( Argument * Arg ) { assert ( ! Arg -> hasByValAttr ( ) && <STR_LIT> ) ;"
LLVM,NVPTX,1421,"Predict the next statement of this code snippet:
 <s> if ( Ptr -> getType ( ) -> getPointerAddressSpace ( ) == ADDRESS_SPACE_GLOBAL ) return ; BasicBlock :: iterator InsertPt ; if ( Argument * Arg = dyn_cast < Argument > ( Ptr ) ) { InsertPt = Arg -> getParent ( ) -> getEntryBlock ( ) . begin ( ) ;"
LLVM,NVPTX,1422,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>LowerKernelArgs ( TM ) ;"
LLVM,NVPTX,1423,"Predict the next statement of this code snippet:
 <s> assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) + <NUM_LIT> ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ;"
LLVM,NVPTX,1424,"Predict the next statement of this code snippet:
 <s> Arg -> replaceAllUsesWith ( AllocA ) ; Value * ArgInParam = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ; LoadInst * LI = new LoadInst ( ArgInParam , Arg -> getName ( ) , FirstInst ) ;"
LLVM,NVPTX,1425,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerKernelArgs ( const <ISA_LIT>TargetMachine * TM = nullptr ) : FunctionPass ( ID ) , TM ( TM ) {"
LLVM,NVPTX,1426,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerKernelArgs ( const <ISA_LIT>TargetMachine * TM = nullptr ) : FunctionPass ( ID ) , TM ( TM ) {"
LLVM,NVPTX,1427,"Predict the next statement of this code snippet:
 <s> Value * UO = GetUnderlyingObject ( LI -> getPointerOperand ( ) , F . getParent ( ) -> getDataLayout ( ) ) ; if ( Argument * Arg = dyn_cast < Argument > ( UO ) ) { if ( Arg -> hasByValAttr ( ) ) { markPointerAsGlobal ( LI ) ; } } } } } } } for ( Argument & Arg : F . args ( ) ) { if ( Arg . getType ( ) -> isPointerTy ( ) ) { if ( Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ; else if ( TM && TM -> getDrvInterface ( ) == <STR_LIT> ) markPointerAsGlobal ( & Arg ) ; }"
LLVM,NVPTX,1428,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>LowerStructArgs ( ) ;"
LLVM,NVPTX,1429,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>LowerStructArgs ( ) ;"
LLVM,NVPTX,1430,"Predict the next statement of this code snippet:
 <s> Type :: getInt8PtrTy ( Func -> getParent ( ) -> getContext ( ) , ADDRESS_SPACE_PARAM ) , Type :: getInt8PtrTy ( Func -> getParent ( ) -> getContext ( ) , ADDRESS_SPACE_GENERIC ) } ; Function * CvtFunc = <STR_LIT> ( Func -> getParent ( ) , <STR_LIT> , CvtTypes ) ; Value * BitcastArgs [ ] = { new BitCastInst ( Arg , Type :: getInt8PtrTy ( Func -> getParent ( ) -> getContext ( ) , ADDRESS_SPACE_GENERIC ) , Arg -> getName ( ) , FirstInst ) } ;"
LLVM,NVPTX,1431,"Predict the next statement of this code snippet:
 <s> Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) + <NUM_LIT> ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ; Type * CvtTypes [ ] = { Type :: getInt8PtrTy ( Func -> getParent ( ) -> getContext ( ) , ADDRESS_SPACE_PARAM ) , Type :: getInt8PtrTy ( Func -> getParent ( ) -> getContext ( ) , ADDRESS_SPACE_GENERIC ) } ; Function * CvtFunc = <STR_LIT> ( Func -> getParent ( ) , <STR_LIT> , CvtTypes ) ; Value * BitcastArgs [ ] = { new BitCastInst ( Arg , Type :: getInt8PtrTy ( Func -> getParent ( ) -> getContext ( ) , ADDRESS_SPACE_GENERIC ) , Arg -> getName ( ) , FirstInst ) } ;"
LLVM,NVPTX,1432,"Predict the next statement of this code snippet:
 <s> if ( Arg . getType ( ) -> isPointerTy ( ) && Arg . hasByValAttr ( ) ) { handleParam ( & Arg ) ; } }"
LLVM,NVPTX,1433,"Predict the next statement of this code snippet:
 <s> if ( Arg . getType ( ) -> isPointerTy ( ) && Arg . hasByValAttr ( ) ) { handleParam ( & Arg ) ; } }"
LLVM,NVPTX,1434,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerStructArgs ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,1435,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>LowerStructArgs ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,1436,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>LowerStructArgs :: runOnFunction ( Function & F ) { if ( ! isKernelFunction ( F ) ) return false ; handleStructPtrArgs ( F ) ;"
LLVM,NVPTX,1437,"Predict the next statement of this code snippet:
 <s> assert ( ImageHandleList . size ( ) > Idx && <STR_LIT> ) ; return ImageHandleList [ Idx ] . c_str ( ) ;"
LLVM,NVPTX,1438,"Predict the next statement of this code snippet:
 <s> assert ( ImageHandleList . size ( ) > Idx && <STR_LIT> ) ; return ImageHandleList [ Idx ] . c_str ( ) ;"
LLVM,NVPTX,1439,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = ImageHandleList . size ( ) ; i != e ; ++ i ) if ( ImageHandleList [ i ] == std :: string ( Symbol ) ) return i ; ImageHandleList . push_back ( Symbol ) ;"
LLVM,NVPTX,1440,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {"
LLVM,NVPTX,1441,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {"
LLVM,NVPTX,1442,"Predict the next statement of this code snippet:
 <s> Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = nullptr ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = nullptr ; AscizDirective = nullptr ; SupportsQuotedNames = false ; SupportsExtendedDwarfLocDirective = false ; SupportsSignedData = false ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = PrivateGlobalPrefix ; WeakDirective = <STR_LIT> ;"
LLVM,NVPTX,1443,"Predict the next statement of this code snippet:
 <s> bool shouldOmitSectionDirective ( StringRef SectionName ) const override {"
LLVM,NVPTX,1444,"Predict the next statement of this code snippet:
 <s> bool shouldOmitSectionDirective ( StringRef SectionName ) const override {"
LLVM,NVPTX,1445,"Predict the next statement of this code snippet:
 <s> HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; HiddenDeclarationVisibilityAttr = HiddenVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = nullptr ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = nullptr ; AscizDirective = nullptr ;"
LLVM,NVPTX,1446,"Predict the next statement of this code snippet:
 <s> SupportsDebugInformation = true ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; HiddenDeclarationVisibilityAttr = HiddenVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = nullptr ;"
LLVM,NVPTX,1447,"Predict the next statement of this code snippet:
 <s> Triple TheTriple ( TT ) ; if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ;"
LLVM,NVPTX,1448,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TheTriple , const MCTargetOptions & Options ) { if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ;"
LLVM,NVPTX,1449,"Predict the next statement of this code snippet:
 <s> SupportsDebugInformation = CompileForDebugging ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; HiddenDeclarationVisibilityAttr = HiddenVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; WeakDirective = <STR_LIT> ; GlobalDirective = <STR_LIT> ;"
LLVM,NVPTX,1450,"Predict the next statement of this code snippet:
 <s> if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; HasSingleParameterDotFile = false ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; Data8bitsDirective = <STR_LIT> ;"
LLVM,NVPTX,1451,"Predict the next statement of this code snippet:
 <s> CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; AllowPeriodsInName = false ; HasSetDirective = false ; HasSingleParameterDotFile = false ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasDotTypeDotSizeDirective = false ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = <STR_LIT> ;"
LLVM,NVPTX,1452,"Predict the next statement of this code snippet:
 <s> InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; WeakDirective = <STR_LIT> ;"
LLVM,NVPTX,1453,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( StringRef TT ) { Triple TheTriple ( TT ) ; if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; HasSingleParameterDotFile = false ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasFunctionAlignment = false ;"
LLVM,NVPTX,1454,"Predict the next statement of this code snippet:
 <s> InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasDotTypeDotSizeDirective = false ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ;"
LLVM,NVPTX,1455,"Predict the next statement of this code snippet:
 <s> Triple TheTriple ( TT ) ; if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; HasSingleParameterDotFile = false ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasDotTypeDotSizeDirective = false ;"
LLVM,NVPTX,1456,"Predict the next statement of this code snippet:
 <s> InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; HiddenDeclarationVisibilityAttr = HiddenVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ;"
LLVM,NVPTX,1457,"Predict the next statement of this code snippet:
 <s> if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; HasSetDirective = false ; HasSingleParameterDotFile = false ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasDotTypeDotSizeDirective = false ; Data8bitsDirective = <STR_LIT> ;"
LLVM,NVPTX,1458,"Predict the next statement of this code snippet:
 <s> Triple TheTriple ( TT ) ; if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; HasSetDirective = false ; HasSingleParameterDotFile = false ; InlineAsmStart = <STR_LIT> ;"
LLVM,NVPTX,1459,"Predict the next statement of this code snippet:
 <s> CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; AllowPeriodsInName = false ; HasSetDirective = false ; HasSingleParameterDotFile = false ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasDotTypeDotSizeDirective = false ; Data8bitsDirective = <STR_LIT> ;"
LLVM,NVPTX,1460,"Predict the next statement of this code snippet:
 <s> if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) PointerSize = <NUM_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; AllowPeriodsInName = false ; HasSetDirective = false ; HasSingleParameterDotFile = false ;"
LLVM,NVPTX,1461,"Predict the next statement of this code snippet:
 <s> ProtectedVisibilityAttr = MCSA_Invalid ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = nullptr ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = nullptr ; AscizDirective = nullptr ; SupportsQuotedNames = false ; SupportsExtendedDwarfLocDirective = false ; SupportsSignedData = false ; WeakDirective = <STR_LIT> ; GlobalDirective = <STR_LIT> ;"
LLVM,NVPTX,1462,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {"
LLVM,NVPTX,1463,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {"
LLVM,NVPTX,1464,"Predict the next statement of this code snippet:
 <s> HasDotTypeDotSizeDirective = false ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = <STR_LIT> ;"
LLVM,NVPTX,1465,"Predict the next statement of this code snippet:
 <s> return E -> getKind ( ) == MCExpr :: Target ;"
LLVM,NVPTX,1466,"Predict the next statement of this code snippet:
 <s> return create ( VK_<ISA_LIT>_DOUBLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1467,"Predict the next statement of this code snippet:
 <s> return create ( VK_<ISA_LIT>_DOUBLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1468,"Predict the next statement of this code snippet:
 <s> bool evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const override {"
LLVM,NVPTX,1469,"Predict the next statement of this code snippet:
 <s> return nullptr ;"
LLVM,NVPTX,1470,"Predict the next statement of this code snippet:
 <s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {"
LLVM,NVPTX,1471,"Predict the next statement of this code snippet:
 <s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {"
LLVM,NVPTX,1472,"Predict the next statement of this code snippet:
 <s> return Flt ;"
LLVM,NVPTX,1473,"Predict the next statement of this code snippet:
 <s> APFloat getAPFloat ( ) const { return Flt ;"
LLVM,NVPTX,1474,"Predict the next statement of this code snippet:
 <s> VariantKind getKind ( ) const {"
LLVM,NVPTX,1475,"Predict the next statement of this code snippet:
 <s> return Kind ;"
LLVM,NVPTX,1476,"Predict the next statement of this code snippet:
 <s> return SymExpr ;"
LLVM,NVPTX,1477,"Predict the next statement of this code snippet:
 <s> return SymExpr ;"
LLVM,NVPTX,1478,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FloatMCExpr ( VariantKind Kind , APFloat Flt ) : Kind ( Kind ) , Flt ( Flt ) {"
LLVM,NVPTX,1479,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FloatMCExpr ( VariantKind Kind , APFloat Flt ) : Kind ( Kind ) , Flt ( Flt ) {"
LLVM,NVPTX,1480,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>GenericMCSymbolRefExpr ( const MCSymbolRefExpr * _SymExpr ) : SymExpr ( _SymExpr ) {"
LLVM,NVPTX,1481,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>GenericMCSymbolRefExpr ( const MCSymbolRefExpr * _SymExpr ) : SymExpr ( _SymExpr ) {"
LLVM,NVPTX,1482,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>GenericMCSymbolRefExpr * <ISA_LIT>GenericMCSymbolRefExpr :: create ( const MCSymbolRefExpr * SymExpr , MCContext & Ctx ) {"
LLVM,NVPTX,1483,"Predict the next statement of this code snippet:
 <s> static const <ISA_LIT>FloatMCExpr * createConstantFPDouble ( const APFloat & Flt , MCContext & Ctx ) { return create ( VK_<ISA_LIT>_DOUBLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1484,"Predict the next statement of this code snippet:
 <s> return create ( VK_<ISA_LIT>_HALF_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1485,"Predict the next statement of this code snippet:
 <s> static const <ISA_LIT>FloatMCExpr * createConstantFPSingle ( const APFloat & Flt , MCContext & Ctx ) { return create ( VK_<ISA_LIT>_SINGLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1486,"Predict the next statement of this code snippet:
 <s> static const <ISA_LIT>FloatMCExpr * createConstantFPSingle ( const APFloat & Flt , MCContext & Ctx ) { return create ( VK_<ISA_LIT>_SINGLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1487,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FloatMCExpr ( VariantKind Kind , APFloat Flt ) : Kind ( Kind ) , Flt ( std :: move ( Flt ) ) {"
LLVM,NVPTX,1488,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FloatMCExpr ( VariantKind Kind , APFloat Flt ) : Kind ( Kind ) , Flt ( std :: move ( Flt ) ) {"
LLVM,NVPTX,1489,"Predict the next statement of this code snippet:
 <s> return nullptr ;"
LLVM,NVPTX,1490,"Predict the next statement of this code snippet:
 <s> MCSection * findAssociatedSection ( ) const override {"
LLVM,NVPTX,1491,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>FloatMCExpr * <ISA_LIT>FloatMCExpr :: create ( VariantKind Kind , APFloat Flt , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>FloatMCExpr ( Kind , Flt ) ;"
LLVM,NVPTX,1492,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>GenericMCSymbolRefExpr :: printImpl ( raw_ostream & OS ) const { OS << <STR_LIT> << * SymExpr << <STR_LIT> ;"
LLVM,NVPTX,1493,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> << * SymExpr << <STR_LIT> ;"
LLVM,NVPTX,1494,"Predict the next statement of this code snippet:
 <s> bool EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const override { return false ;"
LLVM,NVPTX,1495,"Predict the next statement of this code snippet:
 <s> APInt API = APF . bitcastToAPInt ( ) ; std :: string HexStr ( utohexstr ( API . getZExtValue ( ) ) ) ; if ( HexStr . length ( ) < NumHex ) OS << std :: string ( NumHex - HexStr . length ( ) , '0' ) ; OS << utohexstr ( API . getZExtValue ( ) ) ;"
LLVM,NVPTX,1496,"Predict the next statement of this code snippet:
 <s> bool Ignored ; unsigned NumHex ; APFloat APF = getAPFloat ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_HALF_PREC_FLOAT : OS << <STR_LIT> ; NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEhalf ( ) , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; case VK_<ISA_LIT>_SINGLE_PREC_FLOAT : OS << <STR_LIT> ; NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEsingle ( ) , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; case VK_<ISA_LIT>_DOUBLE_PREC_FLOAT : OS << <STR_LIT> ; NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; } APInt API = APF . bitcastToAPInt ( ) ; std :: string HexStr ( utohexstr ( API . getZExtValue ( ) ) ) ; if ( HexStr . length ( ) < NumHex ) OS << std :: string ( NumHex - HexStr . length ( ) , '0' ) ;"
LLVM,NVPTX,1497,"Predict the next statement of this code snippet:
 <s> return new ( Ctx ) <ISA_LIT>FloatMCExpr ( Kind , Flt ) ;"
LLVM,NVPTX,1498,"Predict the next statement of this code snippet:
 <s> return new ( Ctx ) <ISA_LIT>FloatMCExpr ( Kind , Flt ) ;"
LLVM,NVPTX,1499,"Predict the next statement of this code snippet:
 <s> return Create ( VK_<ISA_LIT>_DOUBLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1500,"Predict the next statement of this code snippet:
 <s> return Create ( VK_<ISA_LIT>_SINGLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1501,"Predict the next statement of this code snippet:
 <s> bool EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout ) const override { return false ;"
LLVM,NVPTX,1502,"Predict the next statement of this code snippet:
 <s> const MCSection * FindAssociatedSection ( ) const override {"
LLVM,NVPTX,1503,"Predict the next statement of this code snippet:
 <s> return nullptr ;"
LLVM,NVPTX,1504,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FloatMCExpr ( VariantKind _Kind , APFloat _Flt ) : Kind ( _Kind ) , Flt ( _Flt ) {"
LLVM,NVPTX,1505,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>FloatMCExpr ( VariantKind _Kind , APFloat _Flt ) : Kind ( _Kind ) , Flt ( _Flt ) {"
LLVM,NVPTX,1506,"Predict the next statement of this code snippet:
 <s> NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; } APInt API = APF . bitcastToAPInt ( ) ; std :: string HexStr ( utohexstr ( API . getZExtValue ( ) ) ) ; if ( HexStr . length ( ) < NumHex ) OS << std :: string ( NumHex - HexStr . length ( ) , '0' ) ;"
LLVM,NVPTX,1507,"Predict the next statement of this code snippet:
 <s> NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEsingle , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; case VK_<ISA_LIT>_DOUBLE_PREC_FLOAT : OS << <STR_LIT> ; NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; } APInt API = APF . bitcastToAPInt ( ) ;"
LLVM,NVPTX,1508,"Predict the next statement of this code snippet:
 <s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {"
LLVM,NVPTX,1509,"Predict the next statement of this code snippet:
 <s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;"
LLVM,NVPTX,1510,"Predict the next statement of this code snippet:
 <s> Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; return X ;"
LLVM,NVPTX,1511,"Predict the next statement of this code snippet:
 <s> Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ;"
LLVM,NVPTX,1512,"Predict the next statement of this code snippet:
 <s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {"
LLVM,NVPTX,1513,"Predict the next statement of this code snippet:
 <s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {"
LLVM,NVPTX,1514,"Predict the next statement of this code snippet:
 <s> RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( * T ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createTargetAsmStreamer ) ;"
LLVM,NVPTX,1515,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createTargetAsmStreamer ) ;"
LLVM,NVPTX,1516,"Predict the next statement of this code snippet:
 <s> MCRegisterInfo * X = new MCRegisterInfo ( ) ;"
LLVM,NVPTX,1517,"Predict the next statement of this code snippet:
 <s> MCRegisterInfo * X = new MCRegisterInfo ( ) ;"
LLVM,NVPTX,1518,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ;"
LLVM,NVPTX,1519,"Predict the next statement of this code snippet:
 <s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> initMCCodeGenInfo ( Reloc :: Default , CM , OL ) ;"
LLVM,NVPTX,1520,"Predict the next statement of this code snippet:
 <s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;"
LLVM,NVPTX,1521,"Predict the next statement of this code snippet:
 <s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , STI ) ; return <NUM_LIT> ;"
LLVM,NVPTX,1522,"Predict the next statement of this code snippet:
 <s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) {"
LLVM,NVPTX,1523,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & The<ISA_LIT>Target32 , & The<ISA_LIT>Target64 } ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( * T ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ;"
LLVM,NVPTX,1524,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>Target32 ( ) , & getThe<ISA_LIT>Target64 ( ) } ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( * T ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; }"
LLVM,NVPTX,1525,"Predict the next statement of this code snippet:
 <s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return X ;"
LLVM,NVPTX,1526,"Predict the next statement of this code snippet:
 <s> Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return X ;"
LLVM,NVPTX,1527,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCRegisterInfo ) ;"
LLVM,NVPTX,1528,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCSubtargetInfo ) ;"
LLVM,NVPTX,1529,"Predict the next statement of this code snippet:
 <s> X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return X ;"
LLVM,NVPTX,1530,"Predict the next statement of this code snippet:
 <s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , STI ) ; return nullptr ;"
LLVM,NVPTX,1531,"Predict the next statement of this code snippet:
 <s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , STI ) ; return nullptr ;"
LLVM,NVPTX,1532,"Predict the next statement of this code snippet:
 <s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;"
LLVM,NVPTX,1533,"Predict the next statement of this code snippet:
 <s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) {"
LLVM,NVPTX,1534,"Predict the next statement of this code snippet:
 <s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; return X ;"
LLVM,NVPTX,1535,"Predict the next statement of this code snippet:
 <s> Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ;"
LLVM,NVPTX,1536,"Predict the next statement of this code snippet:
 <s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) {"
LLVM,NVPTX,1537,"Predict the next statement of this code snippet:
 <s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCRegisterInfo ) ;"
LLVM,NVPTX,1538,"Predict the next statement of this code snippet:
 <s> auto & MF = * MBB . getParent ( ) ; const auto & MRI = MF . getRegInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; auto & Prev = * MRI . getUniqueVRegDef ( Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;"
LLVM,NVPTX,1539,"Predict the next statement of this code snippet:
 <s> MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( Prev . getOpcode ( ) ) , Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addOperand ( Prev . getOperand ( <NUM_LIT> ) ) ; MBB . insert ( ( MachineBasicBlock :: iterator ) & Root , MIB ) ; if ( MRI . hasOneNonDBGUse ( Prev . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) {"
LLVM,NVPTX,1540,"Predict the next statement of this code snippet:
 <s> auto & MF = * MBB . getParent ( ) ; if ( Root . getOpcode ( ) != <STR_LIT> && Root . getOpcode ( ) != <STR_LIT> ) return false ; auto & Op = Root . getOperand ( <NUM_LIT> ) ; const auto & MRI = MF . getRegInfo ( ) ; MachineInstr * GenericAddrDef = nullptr ; if ( Op . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( Op . getReg ( ) ) ) { GenericAddrDef = MRI . getUniqueVRegDef ( Op . getReg ( ) ) ; } if ( ! GenericAddrDef || GenericAddrDef -> getParent ( ) != & MBB || ( GenericAddrDef -> getOpcode ( ) != <STR_LIT> && GenericAddrDef -> getOpcode ( ) != <STR_LIT> ) ) { return false ; } auto & BaseAddrOp = GenericAddrDef -> getOperand ( <NUM_LIT> ) ; if ( BaseAddrOp . isReg ( ) && BaseAddrOp . getReg ( ) == <STR_LIT> ) { return true ; }"
LLVM,NVPTX,1541,"Predict the next statement of this code snippet:
 <s> if ( isCVTAToLocalCombinationCandidate ( MI ) ) { CombineCVTAToLocal ( MI ) ; Changed = true ; } } } const auto & MRI = MF . getRegInfo ( ) ; if ( MRI . use_empty ( <STR_LIT> ) ) { if ( auto MI = MRI . getUniqueVRegDef ( <STR_LIT> ) ) { MI -> eraseFromParentAndMarkDBGValuesForRemoval ( ) ; }"
LLVM,NVPTX,1542,"Predict the next statement of this code snippet:
 <s> static void CombineCVTAToLocal ( MachineInstr & Root ) { auto & MBB = * Root . getParent ( ) ; auto & MF = * MBB . getParent ( ) ; const auto & MRI = MF . getRegInfo ( ) ;"
LLVM,NVPTX,1543,"Predict the next statement of this code snippet:
 <s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; auto & Prev = * MRI . getUniqueVRegDef ( Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( Prev . getOpcode ( ) ) , Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . add ( Prev . getOperand ( <NUM_LIT> ) ) ; MBB . insert ( ( MachineBasicBlock :: iterator ) & Root , MIB ) ; if ( MRI . hasOneNonDBGUse ( Prev . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Prev . eraseFromParentAndMarkDBGValuesForRemoval ( ) ;"
LLVM,NVPTX,1544,"Predict the next statement of this code snippet:
 <s> auto BlockIter = MBB . begin ( ) ; while ( BlockIter != MBB . end ( ) ) { auto & MI = * BlockIter ++ ; if ( isCVTAToLocalCombinationCandidate ( MI ) ) { CombineCVTAToLocal ( MI ) ; Changed = true ; } } } const auto & MRI = MF . getRegInfo ( ) ; if ( MRI . use_empty ( <STR_LIT> ) ) { if ( auto MI = MRI . getUniqueVRegDef ( <STR_LIT> ) ) { MI -> eraseFromParentAndMarkDBGValuesForRemoval ( ) ;"
LLVM,NVPTX,1545,"Predict the next statement of this code snippet:
 <s> auto BlockIter = MBB . begin ( ) ; while ( BlockIter != MBB . end ( ) ) { auto & MI = * BlockIter ++ ; if ( isCVTAToLocalCombinationCandidate ( MI ) ) {"
LLVM,NVPTX,1546,"Predict the next statement of this code snippet:
 <s> } const auto & MRI = MF . getRegInfo ( ) ; if ( MRI . use_empty ( <STR_LIT> ) ) { if ( auto MI = MRI . getUniqueVRegDef ( <STR_LIT> ) ) { MI -> eraseFromParentAndMarkDBGValuesForRemoval ( ) ;"
LLVM,NVPTX,1547,"Predict the next statement of this code snippet:
 <s> auto & MBB = * Root . getParent ( ) ; auto & MF = * MBB . getParent ( ) ; if ( Root . getOpcode ( ) != <STR_LIT> && Root . getOpcode ( ) != <STR_LIT> ) return false ; auto & Op = Root . getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,1548,"Predict the next statement of this code snippet:
 <s> auto & MBB = * Root . getParent ( ) ; auto & MF = * MBB . getParent ( ) ; const auto & MRI = MF . getRegInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; auto & Prev = * MRI . getUniqueVRegDef ( Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const <ISA_LIT>RegisterInfo * NRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( Prev . getOpcode ( ) ) , Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( NRI -> getFrameLocalRegister ( MF ) ) . add ( Prev . getOperand ( <NUM_LIT> ) ) ; MBB . insert ( ( MachineBasicBlock :: iterator ) & Root , MIB ) ; if ( MRI . hasOneNonDBGUse ( Prev . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) {"
LLVM,NVPTX,1549,"Predict the next statement of this code snippet:
 <s> Changed = true ; } } } const <ISA_LIT>RegisterInfo * NRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const auto & MRI = MF . getRegInfo ( ) ; if ( MRI . use_empty ( NRI -> getFrameRegister ( MF ) ) ) {"
LLVM,NVPTX,1550,"Predict the next statement of this code snippet:
 <s> Changed = true ; } } } const <ISA_LIT>RegisterInfo * NRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const auto & MRI = MF . getRegInfo ( ) ; if ( MRI . use_empty ( NRI -> getFrameRegister ( MF ) ) ) { if ( auto MI = MRI . getUniqueVRegDef ( NRI -> getFrameRegister ( MF ) ) ) { MI -> eraseFromParent ( ) ;"
LLVM,NVPTX,1551,"Predict the next statement of this code snippet:
 <s> auto & Prev = * MRI . getUniqueVRegDef ( Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const <ISA_LIT>RegisterInfo * NRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( Prev . getOpcode ( ) ) , Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( NRI -> getFrameLocalRegister ( MF ) ) . add ( Prev . getOperand ( <NUM_LIT> ) ) ; MBB . insert ( ( MachineBasicBlock :: iterator ) & Root , MIB ) ; if ( MRI . hasOneNonDBGUse ( Prev . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Prev . eraseFromParentAndMarkDBGValuesForRemoval ( ) ; }"
LLVM,NVPTX,1552,"Predict the next statement of this code snippet:
 <s> MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( Prev . getOpcode ( ) ) , Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( NRI -> getFrameLocalRegister ( MF ) ) . add ( Prev . getOperand ( <NUM_LIT> ) ) ;"
LLVM,NVPTX,1553,"Predict the next statement of this code snippet:
 <s> MachineFunctionPass * llvm :: create<ISA_LIT>Peephole ( ) { return new <ISA_LIT>Peephole ( ) ;"
LLVM,NVPTX,1554,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>Peephole ( ) ;"
LLVM,NVPTX,1555,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {"
LLVM,NVPTX,1556,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1557,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1558,"Predict the next statement of this code snippet:
 <s> const auto & MRI = MF . getRegInfo ( ) ; MachineInstr * GenericAddrDef = nullptr ; if ( Op . isReg ( ) && Register :: isVirtualRegister ( Op . getReg ( ) ) ) { GenericAddrDef = MRI . getUniqueVRegDef ( Op . getReg ( ) ) ; } if ( ! GenericAddrDef || GenericAddrDef -> getParent ( ) != & MBB || ( GenericAddrDef -> getOpcode ( ) != <STR_LIT> && GenericAddrDef -> getOpcode ( ) != <STR_LIT> ) ) { return false ; } const <ISA_LIT>RegisterInfo * NRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; auto & BaseAddrOp = GenericAddrDef -> getOperand ( <NUM_LIT> ) ; if ( BaseAddrOp . isReg ( ) && BaseAddrOp . getReg ( ) == NRI -> getFrameRegister ( MF ) ) { return true ;"
LLVM,NVPTX,1559,"Predict the next statement of this code snippet:
 <s> MachineInstr * GenericAddrDef = nullptr ; if ( Op . isReg ( ) && Register :: isVirtualRegister ( Op . getReg ( ) ) ) { GenericAddrDef = MRI . getUniqueVRegDef ( Op . getReg ( ) ) ; } if ( ! GenericAddrDef || GenericAddrDef -> getParent ( ) != & MBB || ( GenericAddrDef -> getOpcode ( ) != <STR_LIT> && GenericAddrDef -> getOpcode ( ) != <STR_LIT> ) ) {"
LLVM,NVPTX,1560,"Predict the next statement of this code snippet:
 <s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; bool Changed = false ; for ( auto & MBB : MF ) { auto BlockIter = MBB . begin ( ) ; while ( BlockIter != MBB . end ( ) ) { auto & MI = * BlockIter ++ ; if ( isCVTAToLocalCombinationCandidate ( MI ) ) {"
LLVM,NVPTX,1561,"Predict the next statement of this code snippet:
 <s> MaxAlign = std :: max ( MaxAlign , Align ) ; Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; if ( StackGrowsDown ) { DEBUG ( dbgs ( ) << <STR_LIT> << FrameIdx << <STR_LIT> << - Offset << <STR_LIT> ) ; MFI -> setObjectOffset ( FrameIdx , - Offset ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << FrameIdx << <STR_LIT> << Offset << <STR_LIT> ) ; MFI -> setObjectOffset ( FrameIdx , Offset ) ;"
LLVM,NVPTX,1562,"Predict the next statement of this code snippet:
 <s> unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; if ( MFI -> getUseLocalStackAllocationBlock ( ) ) { unsigned Align = MFI -> getLocalFrameMaxAlign ( ) ; Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MFI -> getLocalFrameObjectCount ( ) ; i != e ; ++ i ) { std :: pair < int , int64_t > Entry = MFI -> getLocalFrameObjectMap ( i ) ; int64_t FIOffset = ( StackGrowsDown ? - Offset : Offset ) + Entry . second ; DEBUG ( dbgs ( ) << <STR_LIT> << Entry . first << <STR_LIT> << FIOffset << <STR_LIT> ) ; MFI -> setObjectOffset ( Entry . first , FIOffset ) ; } Offset += MFI -> getLocalFrameSize ( ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; } for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isObjectPreAllocated ( i ) && MFI -> getUseLocalStackAllocationBlock ( ) ) continue ; if ( MFI -> isDeadObjectIndex ( i ) ) continue ; AdjustStackOffset ( MFI , i , StackGrowsDown , Offset , MaxAlign ) ;"
LLVM,NVPTX,1563,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = MFI -> getLocalFrameObjectCount ( ) ; i != e ; ++ i ) { std :: pair < int , int64_t > Entry = MFI -> getLocalFrameObjectMap ( i ) ; int64_t FIOffset = ( StackGrowsDown ? - Offset : Offset ) + Entry . second ; DEBUG ( dbgs ( ) << <STR_LIT> << Entry . first << <STR_LIT> << FIOffset << <STR_LIT> ) ; MFI -> setObjectOffset ( Entry . first , FIOffset ) ; } Offset += MFI -> getLocalFrameSize ( ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; } for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isObjectPreAllocated ( i ) && MFI -> getUseLocalStackAllocationBlock ( ) ) continue ; if ( MFI -> isDeadObjectIndex ( i ) ) continue ; AdjustStackOffset ( MFI , i , StackGrowsDown , Offset , MaxAlign ) ; } if ( ! TFI . targetHandlesStackFrameRounding ( ) ) { if ( MFI -> adjustsStack ( ) && TFI . hasReservedCallFrame ( Fn ) ) Offset += MFI -> getMaxCallFrameSize ( ) ; unsigned StackAlign ; if ( MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) || ( RegInfo -> needsStackRealignment ( Fn ) && MFI -> getObjectIndexEnd ( ) != <NUM_LIT> ) ) StackAlign = TFI . getStackAlignment ( ) ;"
LLVM,NVPTX,1564,"Predict the next statement of this code snippet:
 <s> MachineFunctionPass * llvm :: create<ISA_LIT>PrologEpilogPass ( ) { return new <ISA_LIT>PrologEpilogPass ( ) ;"
LLVM,NVPTX,1565,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PrologEpilogPass ( ) : MachineFunctionPass ( ID ) {"
LLVM,NVPTX,1566,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PrologEpilogPass ( ) : MachineFunctionPass ( ID ) {"
LLVM,NVPTX,1567,"Predict the next statement of this code snippet:
 <s> const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) {"
LLVM,NVPTX,1568,"Predict the next statement of this code snippet:
 <s> if ( StackGrowsDown ) Offset += MFI . getObjectSize ( FrameIdx ) ; unsigned Align = MFI . getObjectAlignment ( FrameIdx ) ; MaxAlign = std :: max ( MaxAlign , Align ) ; Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; if ( StackGrowsDown ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FrameIdx << <STR_LIT> << - Offset << <STR_LIT> ) ; MFI . setObjectOffset ( FrameIdx , - Offset ) ; } else {"
LLVM,NVPTX,1569,"Predict the next statement of this code snippet:
 <s> Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; if ( StackGrowsDown ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FrameIdx << <STR_LIT> << - Offset << <STR_LIT> ) ; MFI . setObjectOffset ( FrameIdx , - Offset ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FrameIdx << <STR_LIT> << Offset << <STR_LIT> ) ; MFI . setObjectOffset ( FrameIdx , Offset ) ;"
LLVM,NVPTX,1570,"Predict the next statement of this code snippet:
 <s> for ( int i = MFI . getObjectIndexBegin ( ) ; i != <NUM_LIT> ; ++ i ) { int64_t FixedOff ; if ( StackGrowsDown ) { FixedOff = - MFI . getObjectOffset ( i ) ; } else { FixedOff = MFI . getObjectOffset ( i ) + MFI . getObjectSize ( i ) ; } if ( FixedOff > Offset ) Offset = FixedOff ; } unsigned MaxAlign = MFI . getMaxAlignment ( ) ; if ( MFI . getUseLocalStackAllocationBlock ( ) ) { unsigned Align = MFI . getLocalFrameMaxAlign ( ) ; Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MFI . getLocalFrameObjectCount ( ) ; i != e ; ++ i ) { std :: pair < int , int64_t > Entry = MFI . getLocalFrameObjectMap ( i ) ; int64_t FIOffset = ( StackGrowsDown ? - Offset : Offset ) + Entry . second ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Entry . first << <STR_LIT> << FIOffset << <STR_LIT> ) ; MFI . setObjectOffset ( Entry . first , FIOffset ) ; } Offset += MFI . getLocalFrameSize ( ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; }"
LLVM,NVPTX,1571,"Predict the next statement of this code snippet:
 <s> } } TFI . emitPrologue ( MF , MF . front ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) TFI . emitEpilogue ( MF , * I ) ; }"
LLVM,NVPTX,1572,"Predict the next statement of this code snippet:
 <s> } } TFI . emitPrologue ( MF , MF . front ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) TFI . emitEpilogue ( MF , * I ) ; }"
LLVM,NVPTX,1573,"Predict the next statement of this code snippet:
 <s> if ( StackGrowsDown ) Offset += MFI . getObjectSize ( FrameIdx ) ; unsigned Align = MFI . getObjectAlignment ( FrameIdx ) ; MaxAlign = std :: max ( MaxAlign , Align ) ; Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; if ( StackGrowsDown ) { DEBUG ( dbgs ( ) << <STR_LIT> << FrameIdx << <STR_LIT> << - Offset << <STR_LIT> ) ; MFI . setObjectOffset ( FrameIdx , - Offset ) ;"
LLVM,NVPTX,1574,"Predict the next statement of this code snippet:
 <s> MFI . setObjectOffset ( FrameIdx , - Offset ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << FrameIdx << <STR_LIT> << Offset << <STR_LIT> ) ; MFI . setObjectOffset ( FrameIdx , Offset ) ; Offset += MFI . getObjectSize ( FrameIdx ) ; }"
LLVM,NVPTX,1575,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo * RegInfo = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; bool StackGrowsDown = TFI . getStackGrowthDirection ( ) == TargetFrameLowering :: StackGrowsDown ; MachineFrameInfo & MFI = Fn . getFrameInfo ( ) ; int LocalAreaOffset = TFI . getOffsetOfLocalArea ( ) ; if ( StackGrowsDown ) LocalAreaOffset = - LocalAreaOffset ; assert ( LocalAreaOffset >= <NUM_LIT> && <STR_LIT> ) ; int64_t Offset = LocalAreaOffset ; for ( int i = MFI . getObjectIndexBegin ( ) ; i != <NUM_LIT> ; ++ i ) { int64_t FixedOff ; if ( StackGrowsDown ) { FixedOff = - MFI . getObjectOffset ( i ) ; } else { FixedOff = MFI . getObjectOffset ( i ) + MFI . getObjectSize ( i ) ; } if ( FixedOff > Offset ) Offset = FixedOff ; } unsigned MaxAlign = MFI . getMaxAlignment ( ) ; if ( MFI . getUseLocalStackAllocationBlock ( ) ) { unsigned Align = MFI . getLocalFrameMaxAlign ( ) ; Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MFI . getLocalFrameObjectCount ( ) ; i != e ; ++ i ) { std :: pair < int , int64_t > Entry = MFI . getLocalFrameObjectMap ( i ) ; int64_t FIOffset = ( StackGrowsDown ? - Offset : Offset ) + Entry . second ; DEBUG ( dbgs ( ) << <STR_LIT> << Entry . first << <STR_LIT> << FIOffset << <STR_LIT> ) ; MFI . setObjectOffset ( Entry . first , FIOffset ) ; } Offset += MFI . getLocalFrameSize ( ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; } for ( unsigned i = <NUM_LIT> , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI . isObjectPreAllocated ( i ) && MFI . getUseLocalStackAllocationBlock ( ) ) continue ; if ( MFI . isDeadObjectIndex ( i ) ) continue ; AdjustStackOffset ( MFI , i , StackGrowsDown , Offset , MaxAlign ) ; } if ( ! TFI . targetHandlesStackFrameRounding ( ) ) { if ( MFI . adjustsStack ( ) && TFI . hasReservedCallFrame ( Fn ) ) Offset += MFI . getMaxCallFrameSize ( ) ;"
LLVM,NVPTX,1576,"Predict the next statement of this code snippet:
 <s> for ( MachineInstr & MI : MBB ) { for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isFI ( ) ) continue ; if ( MI . isDebugValue ( ) ) { assert ( i == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; unsigned Reg ; int64_t Offset = TFI . getFrameIndexReference ( MF , MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , Reg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Reg , false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDebug ( ) ; auto * DIExpr = DIExpression :: prepend ( MI . getDebugExpression ( ) , DIExpression :: NoDeref , Offset ) ; MI . getOperand ( <NUM_LIT> ) . setMetadata ( DIExpr ) ; continue ; } TRI . eliminateFrameIndex ( MI , <NUM_LIT> , i , nullptr ) ; Modified = true ; } } } TFI . emitPrologue ( MF , MF . front ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) TFI . emitEpilogue ( MF , * I ) ; }"
LLVM,NVPTX,1577,"Predict the next statement of this code snippet:
 <s> MaxAlign = std :: max ( MaxAlign , Alignment ) ; Offset = alignTo ( Offset , Alignment ) ; if ( StackGrowsDown ) {"
LLVM,NVPTX,1578,"Predict the next statement of this code snippet:
 <s> if ( MI . isDebugValue ( ) ) { assert ( i == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; Register Reg ; int64_t Offset = TFI . getFrameIndexReference ( MF , MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , Reg ) . getFixed ( ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Reg , false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDebug ( ) ; auto * DIExpr = DIExpression :: prepend ( MI . getDebugExpression ( ) , DIExpression :: ApplyOffset , Offset ) ;"
LLVM,NVPTX,1579,"Predict the next statement of this code snippet:
 <s> const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isFI ( ) ) continue ; if ( MI . isDebugValue ( ) ) { assert ( i == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; unsigned Reg ; int64_t Offset = TFI . getFrameIndexReference ( MF , MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , Reg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Reg , false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDebug ( ) ; auto * DIExpr = DIExpression :: prepend ( MI . getDebugExpression ( ) , DIExpression :: ApplyOffset , Offset ) ; MI . getOperand ( <NUM_LIT> ) . setMetadata ( DIExpr ) ; continue ; } TRI . eliminateFrameIndex ( MI , <NUM_LIT> , i , nullptr ) ; Modified = true ; } }"
LLVM,NVPTX,1580,"Predict the next statement of this code snippet:
 <s> bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isFI ( ) ) continue ; if ( MI . isDebugValue ( ) ) { assert ( i == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; Register Reg ; int64_t Offset = TFI . getFrameIndexReference ( MF , MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , Reg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Reg , false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDebug ( ) ; auto * DIExpr = DIExpression :: prepend ( MI . getDebugExpression ( ) , DIExpression :: ApplyOffset , Offset ) ; MI . getOperand ( <NUM_LIT> ) . setMetadata ( DIExpr ) ; continue ;"
LLVM,NVPTX,1581,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isFI ( ) ) continue ; if ( MI . isDebugValue ( ) ) { assert ( i == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; Register Reg ; int64_t Offset = TFI . getFrameIndexReference ( MF , MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , Reg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Reg , false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDebug ( ) ; auto * DIExpr = DIExpression :: prepend ( MI . getDebugExpression ( ) , DIExpression :: ApplyOffset , Offset ) ; MI . getOperand ( <NUM_LIT> ) . setMetadata ( DIExpr ) ;"
LLVM,NVPTX,1582,"Predict the next statement of this code snippet:
 <s> const TargetFrameLowering & TFI = * TM . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * TM . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ;"
LLVM,NVPTX,1583,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PrologEpilogPass :: runOnMachineFunction ( MachineFunction & MF ) { const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ; TRI . eliminateFrameIndex ( MI , <NUM_LIT> , i , nullptr ) ; Modified = true ; }"
LLVM,NVPTX,1584,"Predict the next statement of this code snippet:
 <s> } TFI . emitPrologue ( MF , MF . front ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( ! I -> empty ( ) && I -> back ( ) . isReturn ( ) ) TFI . emitEpilogue ( MF , * I ) ; }"
LLVM,NVPTX,1585,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>PrologEpilogPass :: runOnMachineFunction ( MachineFunction & MF ) { const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ; TRI . eliminateFrameIndex ( MI , <NUM_LIT> , i , nullptr ) ; Modified = true ; } } } TFI . emitPrologue ( MF ) ;"
LLVM,NVPTX,1586,"Predict the next statement of this code snippet:
 <s> const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {"
LLVM,NVPTX,1587,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PrologEpilogPass :: calculateFrameObjectOffsets ( MachineFunction & Fn ) { const TargetFrameLowering & TFI = * Fn . getSubtarget ( ) . getFrameLowering ( ) ; const TargetRegisterInfo * RegInfo = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; bool StackGrowsDown = TFI . getStackGrowthDirection ( ) == TargetFrameLowering :: StackGrowsDown ; MachineFrameInfo & MFI = Fn . getFrameInfo ( ) ; int LocalAreaOffset = TFI . getOffsetOfLocalArea ( ) ; if ( StackGrowsDown ) LocalAreaOffset = - LocalAreaOffset ; assert ( LocalAreaOffset >= <NUM_LIT> && <STR_LIT> ) ; int64_t Offset = LocalAreaOffset ; for ( int i = MFI . getObjectIndexBegin ( ) ; i != <NUM_LIT> ; ++ i ) { int64_t FixedOff ; if ( StackGrowsDown ) { FixedOff = - MFI . getObjectOffset ( i ) ; } else { FixedOff = MFI . getObjectOffset ( i ) + MFI . getObjectSize ( i ) ; } if ( FixedOff > Offset ) Offset = FixedOff ; } unsigned MaxAlign = MFI . getMaxAlignment ( ) ; if ( MFI . getUseLocalStackAllocationBlock ( ) ) {"
LLVM,NVPTX,1588,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isFI ( ) ) continue ; if ( MI . isDebugValue ( ) ) { assert ( i == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; Register Reg ; int64_t Offset = TFI . getFrameIndexReference ( MF , MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , Reg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Reg , false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDebug ( ) ;"
LLVM,NVPTX,1589,"Predict the next statement of this code snippet:
 <s> int64_t Offset = LocalAreaOffset ; for ( int i = MFI . getObjectIndexBegin ( ) ; i != <NUM_LIT> ; ++ i ) { int64_t FixedOff ; if ( StackGrowsDown ) { FixedOff = - MFI . getObjectOffset ( i ) ; } else { FixedOff = MFI . getObjectOffset ( i ) + MFI . getObjectSize ( i ) ; } if ( FixedOff > Offset ) Offset = FixedOff ; } Align MaxAlign = MFI . getMaxAlign ( ) ; if ( MFI . getUseLocalStackAllocationBlock ( ) ) { Align Alignment = MFI . getLocalFrameMaxAlign ( ) ; Offset = alignTo ( Offset , Alignment ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MFI . getLocalFrameObjectCount ( ) ; i != e ; ++ i ) { std :: pair < int , int64_t > Entry = MFI . getLocalFrameObjectMap ( i ) ; int64_t FIOffset = ( StackGrowsDown ? - Offset : Offset ) + Entry . second ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Entry . first << <STR_LIT> << FIOffset << <STR_LIT> ) ; MFI . setObjectOffset ( Entry . first , FIOffset ) ; } Offset += MFI . getLocalFrameSize ( ) ; MaxAlign = std :: max ( Alignment , MaxAlign ) ; } for ( unsigned i = <NUM_LIT> , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI . isObjectPreAllocated ( i ) && MFI . getUseLocalStackAllocationBlock ( ) ) continue ; if ( MFI . isDeadObjectIndex ( i ) ) continue ; AdjustStackOffset ( MFI , i , StackGrowsDown , Offset , MaxAlign ) ; } if ( ! TFI . targetHandlesStackFrameRounding ( ) ) {"
LLVM,NVPTX,1590,"Predict the next statement of this code snippet:
 <s> MachineOperand & Op = MI . getOperand ( i ) ; assert ( MI . isDebugOperand ( & Op ) && <STR_LIT> <STR_LIT> ) ; Register Reg ; auto Offset = TFI . getFrameIndexReference ( MF , Op . getIndex ( ) , Reg ) ; Op . ChangeToRegister ( Reg , false ) ; const DIExpression * DIExpr = MI . getDebugExpression ( ) ; if ( MI . isNonListDebugValue ( ) ) { DIExpr = TRI . prependOffsetExpression ( MI . getDebugExpression ( ) , DIExpression :: ApplyOffset , Offset ) ; } else { SmallVector < uint64_t , <NUM_LIT> > Ops ;"
LLVM,NVPTX,1591,"Predict the next statement of this code snippet:
 <s> DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MFI -> getLocalFrameObjectCount ( ) ; i != e ; ++ i ) { std :: pair < int , int64_t > Entry = MFI -> getLocalFrameObjectMap ( i ) ; int64_t FIOffset = ( StackGrowsDown ? - Offset : Offset ) + Entry . second ; DEBUG ( dbgs ( ) << <STR_LIT> << Entry . first << <STR_LIT> << FIOffset << <STR_LIT> ) ; MFI -> setObjectOffset ( Entry . first , FIOffset ) ; } Offset += MFI -> getLocalFrameSize ( ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; } for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isObjectPreAllocated ( i ) && MFI -> getUseLocalStackAllocationBlock ( ) ) continue ; if ( MFI -> isDeadObjectIndex ( i ) ) continue ; AdjustStackOffset ( MFI , i , StackGrowsDown , Offset , MaxAlign ) ; } if ( ! TFI . targetHandlesStackFrameRounding ( ) ) { if ( MFI -> adjustsStack ( ) && TFI . hasReservedCallFrame ( Fn ) ) Offset += MFI -> getMaxCallFrameSize ( ) ; unsigned StackAlign ; if ( MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) || ( RegInfo -> needsStackRealignment ( Fn ) && MFI -> getObjectIndexEnd ( ) != <NUM_LIT> ) ) StackAlign = TFI . getStackAlignment ( ) ; else StackAlign = TFI . getTransientStackAlignment ( ) ; StackAlign = std :: max ( StackAlign , MaxAlign ) ; unsigned AlignMask = StackAlign - <NUM_LIT> ; Offset = ( Offset + AlignMask ) & ~ uint64_t ( AlignMask ) ; } int64_t StackSize = Offset - LocalAreaOffset ; MFI -> setStackSize ( StackSize ) ;"
LLVM,NVPTX,1592,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>ProxyRegErasure ( ) ;"
LLVM,NVPTX,1593,"Predict the next statement of this code snippet:
 <s> MachineFunctionPass * llvm :: create<ISA_LIT>ProxyRegErasurePass ( ) { return new <ISA_LIT>ProxyRegErasure ( ) ;"
LLVM,NVPTX,1594,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1595,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,1596,"Predict the next statement of this code snippet:
 <s> initialize<ISA_LIT>ProxyRegErasurePass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,1597,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>ProxyRegErasure :: replaceMachineInstructionUsage ( MachineFunction & MF , MachineInstr & MI ) { auto & InOp = * MI . uses ( ) . begin ( ) ; auto & OutOp = * MI . defs ( ) . begin ( ) ; assert ( InOp . isReg ( ) && <STR_LIT> ) ; assert ( OutOp . isReg ( ) && <STR_LIT> ) ; for ( auto & BB : MF ) { for ( auto & I : BB ) { replaceRegisterUsage ( I , OutOp , InOp ) ; } }"
LLVM,NVPTX,1598,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>ProxyRegErasure :: replaceRegisterUsage ( MachineInstr & Instr , MachineOperand & From , MachineOperand & To ) { for ( auto & Op : Instr . uses ( ) ) {"
LLVM,NVPTX,1599,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>ProxyRegErasure :: replaceRegisterUsage ( MachineInstr & Instr , MachineOperand & From , MachineOperand & To ) {"
LLVM,NVPTX,1600,"Predict the next statement of this code snippet:
 <s> for ( auto & BB : MF ) { for ( auto & MI : BB ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,1601,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : replaceMachineInstructionUsage ( MF , MI ) ; RemoveList . push_back ( & MI ) ; break ; } } }"
LLVM,NVPTX,1602,"Predict the next statement of this code snippet:
 <s> return getStrPool ( ) -> getManagedString ( O . str ( ) . c_str ( ) ) -> c_str ( ) ;"
LLVM,NVPTX,1603,"Predict the next statement of this code snippet:
 <s> return const_cast < ManagedStringPool * > ( & ManagedStrPool ) ;"
LLVM,NVPTX,1604,"Predict the next statement of this code snippet:
 <s> int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ;"
LLVM,NVPTX,1605,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) {"
LLVM,NVPTX,1606,"Predict the next statement of this code snippet:
 <s> } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) {"
LLVM,NVPTX,1607,"Predict the next statement of this code snippet:
 <s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;"
LLVM,NVPTX,1608,"Predict the next statement of this code snippet:
 <s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;"
LLVM,NVPTX,1609,"Predict the next statement of this code snippet:
 <s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; return <STR_LIT> ;"
LLVM,NVPTX,1610,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {"
LLVM,NVPTX,1611,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = { <NUM_LIT> } ; return CalleeSavedRegClasses ;"
LLVM,NVPTX,1612,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = { <NUM_LIT> } ; return CalleeSavedRegClasses ;"
LLVM,NVPTX,1613,"Predict the next statement of this code snippet:
 <s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { <NUM_LIT> } ;"
LLVM,NVPTX,1614,"Predict the next statement of this code snippet:
 <s> static const uint16_t CalleeSavedRegs [ ] = { <NUM_LIT> } ; return CalleeSavedRegs ;"
LLVM,NVPTX,1615,"Predict the next statement of this code snippet:
 <s> int <ISA_LIT>RegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return <NUM_LIT> ;"
LLVM,NVPTX,1616,"Predict the next statement of this code snippet:
 <s> int <ISA_LIT>RegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return <NUM_LIT> ;"
LLVM,NVPTX,1617,"Predict the next statement of this code snippet:
 <s> std :: string get<ISA_LIT>RegClassName ( TargetRegisterClass const * RC ) { if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else {"
LLVM,NVPTX,1618,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const {"
LLVM,NVPTX,1619,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const TargetInstrInfo & tii , const <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) , Is64Bit ( st . is64Bit ( ) ) {"
LLVM,NVPTX,1620,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const TargetInstrInfo & tii , const <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) , Is64Bit ( st . is64Bit ( ) ) {"
LLVM,NVPTX,1621,"Predict the next statement of this code snippet:
 <s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ;"
LLVM,NVPTX,1622,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const {"
LLVM,NVPTX,1623,"Predict the next statement of this code snippet:
 <s> getDwarfRegNum ( unsigned RegNum , bool isEH ) const {"
LLVM,NVPTX,1624,"Predict the next statement of this code snippet:
 <s> std :: string get<ISA_LIT>RegClassName ( TargetRegisterClass const * RC ) { if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ;"
LLVM,NVPTX,1625,"Predict the next statement of this code snippet:
 <s> else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ;"
LLVM,NVPTX,1626,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) {"
LLVM,NVPTX,1627,"Predict the next statement of this code snippet:
 <s> std :: string get<ISA_LIT>RegClassStr ( TargetRegisterClass const * RC ) { if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) {"
LLVM,NVPTX,1628,"Predict the next statement of this code snippet:
 <s> int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ;"
LLVM,NVPTX,1629,"Predict the next statement of this code snippet:
 <s> int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;"
LLVM,NVPTX,1630,"Predict the next statement of this code snippet:
 <s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { <NUM_LIT> } ; return CalleeSavedRegs ;"
LLVM,NVPTX,1631,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {"
LLVM,NVPTX,1632,"Predict the next statement of this code snippet:
 <s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return <STR_LIT> ;"
LLVM,NVPTX,1633,"Predict the next statement of this code snippet:
 <s> if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ;"
LLVM,NVPTX,1634,"Predict the next statement of this code snippet:
 <s> if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else { return <STR_LIT> ; }"
LLVM,NVPTX,1635,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) , Is64Bit ( st . is64Bit ( ) ) {"
LLVM,NVPTX,1636,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) , Is64Bit ( st . is64Bit ( ) ) {"
LLVM,NVPTX,1637,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = { nullptr } ;"
LLVM,NVPTX,1638,"Predict the next statement of this code snippet:
 <s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ;"
LLVM,NVPTX,1639,"Predict the next statement of this code snippet:
 <s> assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( i ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;"
LLVM,NVPTX,1640,"Predict the next statement of this code snippet:
 <s> eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( i ) . ChangeToRegister ( <STR_LIT> , false ) ;"
LLVM,NVPTX,1641,"Predict the next statement of this code snippet:
 <s> if ( RC -> getID ( ) == <STR_LIT> ) return ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return ( & <STR_LIT> ) ;"
LLVM,NVPTX,1642,"Predict the next statement of this code snippet:
 <s> if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ;"
LLVM,NVPTX,1643,"Predict the next statement of this code snippet:
 <s> if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ;"
LLVM,NVPTX,1644,"Predict the next statement of this code snippet:
 <s> } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ;"
LLVM,NVPTX,1645,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) {"
LLVM,NVPTX,1646,"Predict the next statement of this code snippet:
 <s> if ( RC -> getID ( ) == <STR_LIT> ) return <NUM_LIT> ; if ( RC -> getID ( ) == <STR_LIT> ) return <NUM_LIT> ; if ( RC -> getID ( ) == <STR_LIT> ) return <NUM_LIT> ; if ( RC -> getID ( ) == <STR_LIT> ) return <NUM_LIT> ; llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,1647,"Predict the next statement of this code snippet:
 <s> if ( RC -> getID ( ) == <STR_LIT> ) return true ; if ( RC -> getID ( ) == <STR_LIT> ) return true ; if ( RC -> getID ( ) == <STR_LIT> ) return true ; if ( RC -> getID ( ) == <STR_LIT> ) return true ; if ( RC -> getID ( ) == <STR_LIT> ) return true ;"
LLVM,NVPTX,1648,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ; } if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) {"
LLVM,NVPTX,1649,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( getFrameRegister ( MF ) , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;"
LLVM,NVPTX,1650,"Predict the next statement of this code snippet:
 <s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const {"
LLVM,NVPTX,1651,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ;"
LLVM,NVPTX,1652,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,NVPTX,1653,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ;"
LLVM,NVPTX,1654,"Predict the next statement of this code snippet:
 <s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;"
LLVM,NVPTX,1655,"Predict the next statement of this code snippet:
 <s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;"
LLVM,NVPTX,1656,"Predict the next statement of this code snippet:
 <s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;"
LLVM,NVPTX,1657,"Predict the next statement of this code snippet:
 <s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;"
LLVM,NVPTX,1658,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) {"
LLVM,NVPTX,1659,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) {"
LLVM,NVPTX,1660,"Predict the next statement of this code snippet:
 <s> StringRef getPassName ( ) const override {"
LLVM,NVPTX,1661,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand & TexHandle = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SampHandle = MI . getOperand ( <NUM_LIT> ) ; replaceImageHandle ( TexHandle , MF ) ; replaceImageHandle ( SampHandle , MF ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand & SurfHandle = MI . getOperand ( <NUM_LIT> ) ; replaceImageHandle ( SurfHandle , MF ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand & SurfHandle = MI . getOperand ( <NUM_LIT> ) ; replaceImageHandle ( SurfHandle , MF ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand & SurfHandle = MI . getOperand ( <NUM_LIT> ) ; replaceImageHandle ( SurfHandle , MF ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,1662,"Predict the next statement of this code snippet:
 <s> InstrsToRemove . insert ( & TexHandleDef ) ; break ; } case <STR_LIT> : { assert ( TexHandleDef . getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const GlobalValue * GV = TexHandleDef . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; assert ( GV -> hasName ( ) && <STR_LIT> ) ; Op . ChangeToImmediate ( MFI -> getImageHandleSymbolIndex ( GV -> getName ( ) . data ( ) ) ) ; InstrsToRemove . insert ( & TexHandleDef ) ; break ; } default :"
LLVM,NVPTX,1663,"Predict the next statement of this code snippet:
 <s> const MCInstrDesc & MCID = MI . getDesc ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; if ( MCID . TSFlags & <STR_LIT> ) { MachineOperand & TexHandle = MI . getOperand ( <NUM_LIT> ) ; if ( replaceImageHandle ( TexHandle , MF ) ) MI . setDesc ( TII -> get ( texRegisterToIndexOpcode ( MI . getOpcode ( ) ) ) ) ; if ( ! ( MCID . TSFlags & <STR_LIT> ) ) { MachineOperand & SampHandle = MI . getOperand ( <NUM_LIT> ) ; if ( replaceImageHandle ( SampHandle , MF ) ) MI . setDesc ( TII -> get ( samplerRegisterToIndexOpcode ( MI . getOpcode ( ) ) ) ) ; } return true ; } else if ( MCID . TSFlags & <STR_LIT> ) { unsigned VecSize = <NUM_LIT> << ( ( ( MCID . TSFlags & <STR_LIT> ) >> <STR_LIT> ) - <NUM_LIT> ) ; MachineOperand & SurfHandle = MI . getOperand ( VecSize ) ; if ( replaceImageHandle ( SurfHandle , MF ) ) MI . setDesc ( TII -> get ( suldRegisterToIndexOpcode ( MI . getOpcode ( ) ) ) ) ; return true ; } else if ( MCID . TSFlags & <STR_LIT> ) { MachineOperand & SurfHandle = MI . getOperand ( <NUM_LIT> ) ; if ( replaceImageHandle ( SurfHandle , MF ) ) MI . setDesc ( TII -> get ( sustRegisterToIndexOpcode ( MI . getOpcode ( ) ) ) ) ; return true ; } else if ( MCID . TSFlags & <STR_LIT> ) { MachineOperand & Handle = MI . getOperand ( <NUM_LIT> ) ; if ( replaceImageHandle ( Handle , MF ) ) MI . setDesc ( TII -> get ( queryRegisterToIndexOpcode ( MI . getOpcode ( ) ) ) ) ;"
LLVM,NVPTX,1664,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :"
LLVM,NVPTX,1665,"Predict the next statement of this code snippet:
 <s> unsigned Idx ; if ( findIndexForHandle ( Op , MF , Idx ) ) { Op . ChangeToImmediate ( Idx ) ; return true ; } return false ;"
LLVM,NVPTX,1666,"Predict the next statement of this code snippet:
 <s> bool Changed = false ; InstrsToRemove . clear ( ) ; for ( MachineBasicBlock & MBB : MF ) for ( MachineInstr & MI : MBB ) Changed |= processInstr ( MI ) ; for ( MachineInstr * MI : InstrsToRemove ) MI -> eraseFromParent ( ) ;"
LLVM,NVPTX,1667,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ReplaceImageHandles :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; InstrsToRemove . clear ( ) ; for ( MachineBasicBlock & MBB : MF ) for ( MachineInstr & MI : MBB ) Changed |= processInstr ( MI ) ; for ( MachineInstr * MI : InstrsToRemove ) MI -> eraseFromParent ( ) ; return Changed ;"
LLVM,NVPTX,1668,"Predict the next statement of this code snippet:
 <s> switch ( TexHandleDef . getOpcode ( ) ) { case <STR_LIT> : { const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; if ( TM . getDrvInterface ( ) == <STR_LIT> ) { return false ; } assert ( TexHandleDef . getOperand ( <NUM_LIT> ) . isSymbol ( ) && <STR_LIT> ) ; StringRef Sym = TexHandleDef . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; std :: string ParamBaseName = MF . getName ( ) ; ParamBaseName += <STR_LIT> ; assert ( Sym . startswith ( ParamBaseName ) && <STR_LIT> ) ;"
LLVM,NVPTX,1669,"Predict the next statement of this code snippet:
 <s> assert ( TexHandleDef . getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const GlobalValue * GV = TexHandleDef . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; assert ( GV -> hasName ( ) && <STR_LIT> ) ; InstrsToRemove . insert ( & TexHandleDef ) ; Idx = MFI -> getImageHandleSymbolIndex ( GV -> getName ( ) . data ( ) ) ; return true ; } case <STR_LIT> : case TargetOpcode :: COPY : { bool Res = findIndexForHandle ( TexHandleDef . getOperand ( <NUM_LIT> ) , MF , Idx ) ; if ( Res ) { InstrsToRemove . insert ( & TexHandleDef ) ; } return Res ;"
LLVM,NVPTX,1670,"Predict the next statement of this code snippet:
 <s> const char * getPassName ( ) const override {"
LLVM,NVPTX,1671,"Predict the next statement of this code snippet:
 <s> InstrsToRemove . clear ( ) ; for ( MachineBasicBlock & MBB : MF ) for ( MachineInstr & MI : MBB ) Changed |= processInstr ( MI ) ;"
LLVM,NVPTX,1672,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>ReplaceImageHandles ( ) ;"
LLVM,NVPTX,1673,"Predict the next statement of this code snippet:
 <s> MachineFunctionPass * llvm :: create<ISA_LIT>ReplaceImageHandlesPass ( ) { return new <ISA_LIT>ReplaceImageHandles ( ) ;"
LLVM,NVPTX,1674,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ReplaceImageHandles :: findIndexForHandle ( MachineOperand & Op , MachineFunction & MF , unsigned & Idx ) { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; assert ( Op . isReg ( ) && <STR_LIT> ) ; MachineInstr & TexHandleDef = * MRI . getVRegDef ( Op . getReg ( ) ) ; switch ( TexHandleDef . getOpcode ( ) ) { case <STR_LIT> : { const <ISA_LIT>Subtarget & ST = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . getDrvInterface ( ) == <STR_LIT> ) { return false ; } assert ( TexHandleDef . getOperand ( <NUM_LIT> ) . isSymbol ( ) && <STR_LIT> ) ; StringRef Sym = TexHandleDef . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; std :: string ParamBaseName = MF . getName ( ) ; ParamBaseName += <STR_LIT> ; assert ( Sym . startswith ( ParamBaseName ) && <STR_LIT> ) ; unsigned Param = atoi ( Sym . data ( ) + ParamBaseName . size ( ) ) ; std :: string NewSym ; raw_string_ostream NewSymStr ( NewSym ) ; NewSymStr << MF . getFunction ( ) -> getName ( ) << <STR_LIT> << Param ; InstrsToRemove . insert ( & TexHandleDef ) ; Idx = MFI -> getImageHandleSymbolIndex ( NewSymStr . str ( ) . c_str ( ) ) ; return true ; } case <STR_LIT> : { assert ( TexHandleDef . getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const GlobalValue * GV = TexHandleDef . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; assert ( GV -> hasName ( ) && <STR_LIT> ) ; InstrsToRemove . insert ( & TexHandleDef ) ; Idx = MFI -> getImageHandleSymbolIndex ( GV -> getName ( ) . data ( ) ) ; return true ; } case <STR_LIT> : case TargetOpcode :: COPY : { bool Res = findIndexForHandle ( TexHandleDef . getOperand ( <NUM_LIT> ) , MF , Idx ) ; if ( Res ) { InstrsToRemove . insert ( & TexHandleDef ) ; } return Res ; } default : llvm_unreachable ( <STR_LIT> ) ; }"
LLVM,NVPTX,1675,"Predict the next statement of this code snippet:
 <s> virtual const char * getPassName ( ) const { return <STR_LIT> ;"
LLVM,NVPTX,1676,"Predict the next statement of this code snippet:
 <s> virtual const char * getPassName ( ) const {"
LLVM,NVPTX,1677,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ReplaceImageHandles :: <ISA_LIT>ReplaceImageHandles ( ) : MachineFunctionPass ( ID ) {"
LLVM,NVPTX,1678,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>ReplaceImageHandles :: <ISA_LIT>ReplaceImageHandles ( ) : MachineFunctionPass ( ID ) {"
LLVM,NVPTX,1679,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>ReplaceImageHandles :: processInstr ( MachineInstr & MI ) { MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . TSFlags & <STR_LIT> ) { MachineOperand & TexHandle = MI . getOperand ( <NUM_LIT> ) ; replaceImageHandle ( TexHandle , MF ) ; if ( ! ( MCID . TSFlags & <STR_LIT> ) ) { MachineOperand & SampHandle = MI . getOperand ( <NUM_LIT> ) ; replaceImageHandle ( SampHandle , MF ) ; } return true ; } else if ( MCID . TSFlags & <STR_LIT> ) { unsigned VecSize = <NUM_LIT> << ( ( ( MCID . TSFlags & <STR_LIT> ) >> <STR_LIT> ) - <NUM_LIT> ) ; MachineOperand & SurfHandle = MI . getOperand ( VecSize ) ; replaceImageHandle ( SurfHandle , MF ) ; return true ; } else if ( MCID . TSFlags & <STR_LIT> ) { MachineOperand & SurfHandle = MI . getOperand ( <NUM_LIT> ) ; replaceImageHandle ( SurfHandle , MF ) ;"
LLVM,NVPTX,1680,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>ReplaceImageHandles ::"
LLVM,NVPTX,1681,"Predict the next statement of this code snippet:
 <s> unsigned Idx ;"
LLVM,NVPTX,1682,"Predict the next statement of this code snippet:
 <s> for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { for ( MachineBasicBlock :: iterator I = ( * BI ) . begin ( ) , E = ( * BI ) . end ( ) ; I != E ; ++ I ) {"
LLVM,NVPTX,1683,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Section ( SectionVariant V , SectionKind K ) : MCSection ( V , K , nullptr ) {"
LLVM,NVPTX,1684,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Section ( SectionVariant V , SectionKind K ) : MCSection ( V , K , nullptr ) {"
LLVM,NVPTX,1685,"Predict the next statement of this code snippet:
 <s> void PrintSwitchToSection ( const MCAsmInfo & MAI , const Triple & T , raw_ostream & OS , const MCExpr * Subsection ) const override {"
LLVM,NVPTX,1686,"Predict the next statement of this code snippet:
 <s> void PrintSwitchToSection ( const MCAsmInfo & MAI , const Triple & T , raw_ostream & OS , const MCExpr * Subsection ) const override {"
LLVM,NVPTX,1687,"Predict the next statement of this code snippet:
 <s> virtual bool isBaseAddressKnownZero ( ) const {"
LLVM,NVPTX,1688,"Predict the next statement of this code snippet:
 <s> virtual bool isVirtualSection ( ) const {"
LLVM,NVPTX,1689,"Predict the next statement of this code snippet:
 <s> virtual void PrintSwitchToSection ( const MCAsmInfo & MAI , raw_ostream & OS ) const {"
LLVM,NVPTX,1690,"Predict the next statement of this code snippet:
 <s> virtual void PrintSwitchToSection ( const MCAsmInfo & MAI , raw_ostream & OS ) const {"
LLVM,NVPTX,1691,"Predict the next statement of this code snippet:
 <s> return false ;"
LLVM,NVPTX,1692,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>Section ( ) {"
LLVM,NVPTX,1693,"Predict the next statement of this code snippet:
 <s> ~ <ISA_LIT>Section ( ) {"
LLVM,NVPTX,1694,"Predict the next statement of this code snippet:
 <s> virtual std :: string getLabelBeginName ( ) const {"
LLVM,NVPTX,1695,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,1696,"Predict the next statement of this code snippet:
 <s> virtual void PrintSwitchToSection ( const MCAsmInfo & MAI , raw_ostream & OS , const MCExpr * Subsection ) const {"
LLVM,NVPTX,1697,"Predict the next statement of this code snippet:
 <s> virtual void PrintSwitchToSection ( const MCAsmInfo & MAI , raw_ostream & OS , const MCExpr * Subsection ) const {"
LLVM,NVPTX,1698,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,1699,"Predict the next statement of this code snippet:
 <s> std :: string getLabelBeginName ( ) const override { return <STR_LIT> ;"
LLVM,NVPTX,1700,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,1701,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,1702,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,NVPTX,1703,"Predict the next statement of this code snippet:
 <s> bool isBaseAddressKnownZero ( ) const override { return true ;"
LLVM,NVPTX,1704,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Section ( SectionVariant V , SectionKind K ) : MCSection ( V , K ) {"
LLVM,NVPTX,1705,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Section ( SectionVariant V , SectionKind K ) : MCSection ( V , K ) {"
LLVM,NVPTX,1706,"Predict the next statement of this code snippet:
 <s> void PrintSwitchToSection ( const MCAsmInfo & MAI , raw_ostream & OS , const MCExpr * Subsection ) const override {"
LLVM,NVPTX,1707,"Predict the next statement of this code snippet:
 <s> void PrintSwitchToSection ( const MCAsmInfo & MAI , raw_ostream & OS , const MCExpr * Subsection ) const override {"
LLVM,NVPTX,1708,"Predict the next statement of this code snippet:
 <s> return false ;"
LLVM,NVPTX,1709,"Predict the next statement of this code snippet:
 <s> return false ;"
LLVM,NVPTX,1710,"Predict the next statement of this code snippet:
 <s> virtual ~ <ISA_LIT>Section ( ) {"
LLVM,NVPTX,1711,"Predict the next statement of this code snippet:
 <s> virtual ~ <ISA_LIT>Section ( ) {"
LLVM,NVPTX,1712,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreserved ( <STR_LIT> ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ;"
LLVM,NVPTX,1713,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>SplitBBatBar ( ) ;"
LLVM,NVPTX,1714,"Predict the next statement of this code snippet:
 <s> AU . addPreserved < MachineFunctionAnalysis > ( ) ;"
LLVM,NVPTX,1715,"Predict the next statement of this code snippet:
 <s> virtual const char * getPassName ( ) const { return <STR_LIT> ;"
LLVM,NVPTX,1716,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>SplitBBatBar ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,1717,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>SplitBBatBar ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,1718,"Predict the next statement of this code snippet:
 <s> BasicBlock :: iterator IB = BI -> begin ( ) ; BasicBlock :: iterator II = IB ; BasicBlock :: iterator IE = BI -> end ( ) ; while ( II != IE ) { if ( IntrinsicInst * inst = dyn_cast < IntrinsicInst > ( II ) ) { <STR_LIT> id = inst -> getIntrinsicID ( ) ; if ( llvm :: isBarrierIntrinsic ( id ) ) { if ( II != IB ) SplitPoints . push_back ( II ) ; II ++ ; if ( ( II != IE ) && ( ! II -> isTerminator ( ) ) ) { SplitPoints . push_back ( II ) ; II ++ ; } continue ; } } II ++ ; } } for ( unsigned i = <NUM_LIT> ; i != SplitPoints . size ( ) ; i ++ ) { changed = true ;"
LLVM,NVPTX,1719,"Predict the next statement of this code snippet:
 <s> return hasFP16Math ( ) && NoF16Math == false ;"
LLVM,NVPTX,1720,"Predict the next statement of this code snippet:
 <s> TargetName = std :: string ( CPU . empty ( ) ? <STR_LIT> : CPU ) ; ParseSubtargetFeatures ( TargetName , TargetName , FS ) ;"
LLVM,NVPTX,1721,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) {"
LLVM,NVPTX,1722,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) {"
LLVM,NVPTX,1723,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>Subtarget :: anchor ( ) {"
LLVM,NVPTX,1724,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>Subtarget :: anchor ( ) {"
LLVM,NVPTX,1725,"Predict the next statement of this code snippet:
 <s> const TargetFrameLowering * getFrameLowering ( ) const override { return & FrameLowering ;"
LLVM,NVPTX,1726,"Predict the next statement of this code snippet:
 <s> const TargetFrameLowering * getFrameLowering ( ) const override {"
LLVM,NVPTX,1727,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ;"
LLVM,NVPTX,1728,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ;"
LLVM,NVPTX,1729,"Predict the next statement of this code snippet:
 <s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const override {"
LLVM,NVPTX,1730,"Predict the next statement of this code snippet:
 <s> unsigned int getSmVersion ( ) const {"
LLVM,NVPTX,1731,"Predict the next statement of this code snippet:
 <s> return & TLInfo ;"
LLVM,NVPTX,1732,"Predict the next statement of this code snippet:
 <s> return & TLInfo ;"
LLVM,NVPTX,1733,"Predict the next statement of this code snippet:
 <s> std :: string getTargetName ( ) const { return TargetName ;"
LLVM,NVPTX,1734,"Predict the next statement of this code snippet:
 <s> std :: string getTargetName ( ) const { return TargetName ;"
LLVM,NVPTX,1735,"Predict the next statement of this code snippet:
 <s> bool hasAtomRedG64 ( ) const { return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1736,"Predict the next statement of this code snippet:
 <s> bool hasAtomRedGen32 ( ) const { return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1737,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1738,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1739,"Predict the next statement of this code snippet:
 <s> bool hasAtomRedS32 ( ) const { return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1740,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1741,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1742,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1743,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1744,"Predict the next statement of this code snippet:
 <s> bool hasDouble ( ) const { return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1745,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1746,"Predict the next statement of this code snippet:
 <s> bool hasFMAF64 ( ) const {"
LLVM,NVPTX,1747,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1748,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1749,"Predict the next statement of this code snippet:
 <s> if ( TM . getDrvInterface ( ) == <STR_LIT> ) return ( SmVersion >= <NUM_LIT> ) ;"
LLVM,NVPTX,1750,"Predict the next statement of this code snippet:
 <s> bool hasLDU ( ) const {"
LLVM,NVPTX,1751,"Predict the next statement of this code snippet:
 <s> return hasHWROT32 ( ) || hasSWROT32 ( ) ;"
LLVM,NVPTX,1752,"Predict the next statement of this code snippet:
 <s> inline bool hasROT64 ( ) const {"
LLVM,NVPTX,1753,"Predict the next statement of this code snippet:
 <s> inline bool hasSWROT32 ( ) const {"
LLVM,NVPTX,1754,"Predict the next statement of this code snippet:
 <s> inline bool hasSWROT32 ( ) const {"
LLVM,NVPTX,1755,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1756,"Predict the next statement of this code snippet:
 <s> if ( CPU . empty ( ) && FS . size ( ) ) llvm_unreachable ( <STR_LIT> ) ; TargetName = CPU . empty ( ) ? <STR_LIT> : CPU ; ParseSubtargetFeatures ( TargetName , FS ) ; if ( PTXVersion == <NUM_LIT> ) { PTXVersion = <NUM_LIT> ; } return * this ;"
LLVM,NVPTX,1757,"Predict the next statement of this code snippet:
 <s> ParseSubtargetFeatures ( TargetName , FS ) ; if ( PTXVersion == <NUM_LIT> ) { PTXVersion = <NUM_LIT> ; } return * this ;"
LLVM,NVPTX,1758,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , FrameLowering ( ) {"
LLVM,NVPTX,1759,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , FrameLowering ( ) {"
LLVM,NVPTX,1760,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1761,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1762,"Predict the next statement of this code snippet:
 <s> return false ;"
LLVM,NVPTX,1763,"Predict the next statement of this code snippet:
 <s> inline bool hasHWROT32 ( ) const { return false ;"
LLVM,NVPTX,1764,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1765,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1766,"Predict the next statement of this code snippet:
 <s> return true ;"
LLVM,NVPTX,1767,"Predict the next statement of this code snippet:
 <s> drvInterface = DriverInterface ; std :: string defCPU = <STR_LIT> ; ParseSubtargetFeatures ( ( CPU . empty ( ) ? defCPU : CPU ) , FS ) ; if ( FS . empty ( ) && CPU . empty ( ) ) TargetName = defCPU ; else if ( ! CPU . empty ( ) ) TargetName = CPU ; else llvm_unreachable ( <STR_LIT> ) ; if ( PTXVersion == <NUM_LIT> ) { PTXVersion = <NUM_LIT> ;"
LLVM,NVPTX,1768,"Predict the next statement of this code snippet:
 <s> bool hasAtomScope ( ) const { return HasAtomScope ;"
LLVM,NVPTX,1769,"Predict the next statement of this code snippet:
 <s> bool hasImageHandles ( ) const { if ( getDrvInterface ( ) == <STR_LIT> ) return ( SmVersion >= <NUM_LIT> ) ; return false ;"
LLVM,NVPTX,1770,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , FrameLowering ( ) {"
LLVM,NVPTX,1771,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , FrameLowering ( ) {"
LLVM,NVPTX,1772,"Predict the next statement of this code snippet:
 <s> const char * p ; if ( is64Bit ( ) ) p = <STR_LIT> <STR_LIT> <STR_LIT> ; else p = <STR_LIT> <STR_LIT> <STR_LIT> ;"
LLVM,NVPTX,1773,"Predict the next statement of this code snippet:
 <s> if ( is64Bit ( ) ) p = <STR_LIT> <STR_LIT> <STR_LIT> ;"
LLVM,NVPTX,1774,"Predict the next statement of this code snippet:
 <s> inline bool hasROT32 ( ) const {"
LLVM,NVPTX,1775,"Predict the next statement of this code snippet:
 <s> else drvInterface = <STR_LIT> ; std :: string defCPU = <STR_LIT> ; ParseSubtargetFeatures ( ( CPU . empty ( ) ? defCPU : CPU ) , FS ) ; if ( FS . empty ( ) && CPU . empty ( ) ) TargetName = defCPU ; else if ( ! CPU . empty ( ) ) TargetName = CPU ; else llvm_unreachable ( <STR_LIT> ) ; if ( PTXVersion == <NUM_LIT> ) {"
LLVM,NVPTX,1776,"Predict the next statement of this code snippet:
 <s> std :: string defCPU = <STR_LIT> ; ParseSubtargetFeatures ( ( CPU . empty ( ) ? defCPU : CPU ) , FS ) ; if ( FS . empty ( ) && CPU . empty ( ) ) TargetName = defCPU ; else if ( ! CPU . empty ( ) ) TargetName = CPU ; else llvm_unreachable ( <STR_LIT> ) ; if ( PTXVersion == <NUM_LIT> ) { PTXVersion = <NUM_LIT> ;"
LLVM,NVPTX,1777,"Predict the next statement of this code snippet:
 <s> TargetName = std :: string ( CPU . empty ( ) ? <STR_LIT> : CPU ) ; ParseSubtargetFeatures ( TargetName , FS ) ; if ( PTXVersion == <NUM_LIT> ) {"
LLVM,NVPTX,1778,"Predict the next statement of this code snippet:
 <s> TargetName = std :: string ( CPU . empty ( ) ? <STR_LIT> : CPU ) ; ParseSubtargetFeatures ( TargetName , FS ) ; if ( PTXVersion == <NUM_LIT> ) { PTXVersion = <NUM_LIT> ; }"
LLVM,NVPTX,1779,"Predict the next statement of this code snippet:
 <s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override {"
LLVM,NVPTX,1780,"Predict the next statement of this code snippet:
 <s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override {"
LLVM,NVPTX,1781,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1782,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1783,"Predict the next statement of this code snippet:
 <s> bool hasAtomMinMax64 ( ) const {"
LLVM,NVPTX,1784,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1785,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1786,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1787,"Predict the next statement of this code snippet:
 <s> bool hasFP16Math ( ) const {"
LLVM,NVPTX,1788,"Predict the next statement of this code snippet:
 <s> std :: string defCPU = <STR_LIT> ; if ( FS . empty ( ) && CPU . empty ( ) ) TargetName = defCPU ; else if ( ! CPU . empty ( ) ) TargetName = CPU ; else llvm_unreachable ( <STR_LIT> ) ; SmVersion = atoi ( TargetName . c_str ( ) + <NUM_LIT> ) ;"
LLVM,NVPTX,1789,"Predict the next statement of this code snippet:
 <s> drvInterface = DriverInterface ; std :: string defCPU = <STR_LIT> ; if ( FS . empty ( ) && CPU . empty ( ) ) TargetName = defCPU ; else if ( ! CPU . empty ( ) ) TargetName = CPU ; else llvm_unreachable ( <STR_LIT> ) ; SmVersion = atoi ( TargetName . c_str ( ) + <NUM_LIT> ) ;"
LLVM,NVPTX,1790,"Predict the next statement of this code snippet:
 <s> if ( PTXVersion == <NUM_LIT> ) { PTXVersion = <NUM_LIT> ; }"
LLVM,NVPTX,1791,"Predict the next statement of this code snippet:
 <s> return & DL ;"
LLVM,NVPTX,1792,"Predict the next statement of this code snippet:
 <s> const DataLayout * getDataLayout ( ) const override { return & DL ;"
LLVM,NVPTX,1793,"Predict the next statement of this code snippet:
 <s> return SmVersion >= <NUM_LIT> ;"
LLVM,NVPTX,1794,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , TSInfo ( TM . getDataLayout ( ) ) , FrameLowering ( ) {"
LLVM,NVPTX,1795,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , TSInfo ( TM . getDataLayout ( ) ) , FrameLowering ( ) {"
LLVM,NVPTX,1796,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool is64Bit ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , Is64Bit ( is64Bit ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( ( const <ISA_LIT>TargetMachine & ) TM , * this ) , TSInfo ( TM . getDataLayout ( ) ) , FrameLowering ( * this ) { Triple T ( TT ) ; if ( T . getOS ( ) == Triple :: NVCL ) drvInterface = <STR_LIT> ; else drvInterface = <STR_LIT> ;"
LLVM,NVPTX,1797,"Predict the next statement of this code snippet:
 <s> std :: string Ret = <STR_LIT> ; if ( ! is64Bit ) Ret += <STR_LIT> ; Ret += <STR_LIT> ;"
LLVM,NVPTX,1798,"Predict the next statement of this code snippet:
 <s> return & DL ;"
LLVM,NVPTX,1799,"Predict the next statement of this code snippet:
 <s> const DataLayout * getDataLayout ( ) const {"
LLVM,NVPTX,1800,"Predict the next statement of this code snippet:
 <s> return drvInterface ;"
LLVM,NVPTX,1801,"Predict the next statement of this code snippet:
 <s> return drvInterface ;"
LLVM,NVPTX,1802,"Predict the next statement of this code snippet:
 <s> return & FrameLowering ;"
LLVM,NVPTX,1803,"Predict the next statement of this code snippet:
 <s> return & InstrInfo . getRegisterInfo ( ) ;"
LLVM,NVPTX,1804,"Predict the next statement of this code snippet:
 <s> return & InstrInfo . getRegisterInfo ( ) ;"
LLVM,NVPTX,1805,"Predict the next statement of this code snippet:
 <s> return & TSInfo ;"
LLVM,NVPTX,1806,"Predict the next statement of this code snippet:
 <s> return & TSInfo ;"
LLVM,NVPTX,1807,"Predict the next statement of this code snippet:
 <s> return & TLInfo ;"
LLVM,NVPTX,1808,"Predict the next statement of this code snippet:
 <s> return false ;"
LLVM,NVPTX,1809,"Predict the next statement of this code snippet:
 <s> return Is64Bit ;"
LLVM,NVPTX,1810,"Predict the next statement of this code snippet:
 <s> bool is64Bit ( ) const { return Is64Bit ;"
LLVM,NVPTX,1811,"Predict the next statement of this code snippet:
 <s> static Target The<ISA_LIT>Target32 ; return The<ISA_LIT>Target32 ;"
LLVM,NVPTX,1812,"Predict the next statement of this code snippet:
 <s> static Target The<ISA_LIT>Target64 ;"
LLVM,NVPTX,1813,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: nvptx > X ( getThe<ISA_LIT>Target32 ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,1814,"Predict the next statement of this code snippet:
 <s> RegisterTarget < Triple :: nvptx64 > Y ( getThe<ISA_LIT>Target64 ( ) , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,1815,"Predict the next statement of this code snippet:
 <s> RegisterTarget < Triple :: nvptx > X ( getThe<ISA_LIT>Target32 ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: nvptx64 > Y ( getThe<ISA_LIT>Target64 ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,1816,"Predict the next statement of this code snippet:
 <s> RegisterTarget < Triple :: nvptx64 > Y ( getThe<ISA_LIT>Target64 ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,1817,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: nvptx > X ( The<ISA_LIT>Target32 , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,1818,"Predict the next statement of this code snippet:
 <s> RegisterTarget < Triple :: nvptx > X ( The<ISA_LIT>Target32 , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: nvptx64 > Y ( The<ISA_LIT>Target64 , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,1819,"Predict the next statement of this code snippet:
 <s> addPass ( createInferAddressSpacesPass ( ) ) ;"
LLVM,NVPTX,1820,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addAddressSpaceInferencePasses ( ) { addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ; addPass ( createInferAddressSpacesPass ( ) ) ; addPass ( create<ISA_LIT>AtomicLowerPass ( ) ) ;"
LLVM,NVPTX,1821,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addFastRegAlloc ( ) {"
LLVM,NVPTX,1822,"Predict the next statement of this code snippet:
 <s> disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const <ISA_LIT>Subtarget & ST = * getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ;"
LLVM,NVPTX,1823,"Predict the next statement of this code snippet:
 <s> printAndVerify ( <STR_LIT> ) ; if ( addILPOpts ( ) ) printAndVerify ( <STR_LIT> ) ; addPass ( & EarlyMachineLICMID ) ; addPass ( & MachineCSEID ) ; addPass ( & MachineSinkingID ) ; printAndVerify ( <STR_LIT> ) ; addPass ( & PeepholeOptimizerID ) ; printAndVerify ( <STR_LIT> ) ;"
LLVM,NVPTX,1824,"Predict the next statement of this code snippet:
 <s> addPass ( & LiveVariablesID ) ; addPass ( & MachineLoopInfoID ) ; addPass ( & PHIEliminationID ) ; addPass ( & TwoAddressInstructionPassID ) ;"
LLVM,NVPTX,1825,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>PrologEpilogPass ( ) ) ;"
LLVM,NVPTX,1826,"Predict the next statement of this code snippet:
 <s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>Peephole ( ) ) ;"
LLVM,NVPTX,1827,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ProxyRegErasurePass ( ) ) ;"
LLVM,NVPTX,1828,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) {"
LLVM,NVPTX,1829,"Predict the next statement of this code snippet:
 <s> bool addRegAssignAndRewriteFast ( ) override { llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,1830,"Predict the next statement of this code snippet:
 <s> llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,1831,"Predict the next statement of this code snippet:
 <s> addPass ( createSeparateConstOffsetFromGEPPass ( ) ) ; addPass ( createSpeculativeExecutionPass ( ) ) ; addPass ( createStraightLineStrengthReducePass ( ) ) ; addEarlyCSEOrGVNPass ( ) ;"
LLVM,NVPTX,1832,"Predict the next statement of this code snippet:
 <s> addPass ( createSeparateConstOffsetFromGEPPass ( ) ) ; addPass ( createSpeculativeExecutionPass ( ) ) ; addPass ( createStraightLineStrengthReducePass ( ) ) ; addEarlyCSEOrGVNPass ( ) ; addPass ( createNaryReassociatePass ( ) ) ; addPass ( createEarlyCSEPass ( ) ) ;"
LLVM,NVPTX,1833,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetMachine :: adjustPassManager ( PassManagerBuilder & Builder ) { Builder . addExtension ( PassManagerBuilder :: EP_EarlyAsPossible , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) {"
LLVM,NVPTX,1834,"Predict the next statement of this code snippet:
 <s> static std :: string computeDataLayout ( bool is64Bit , bool UseShortPointers ) {"
LLVM,NVPTX,1835,"Predict the next statement of this code snippet:
 <s> if ( ! is64Bit ) Ret += <STR_LIT> ;"
LLVM,NVPTX,1836,"Predict the next statement of this code snippet:
 <s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {"
LLVM,NVPTX,1837,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>PassConfig ( * this , PM ) ;"
LLVM,NVPTX,1838,"Predict the next statement of this code snippet:
 <s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;"
LLVM,NVPTX,1839,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( getThe<ISA_LIT>Target32 ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( getThe<ISA_LIT>Target64 ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeNVVMReflectPass ( PR ) ; initializeNVVMIntrRangePass ( PR ) ; initializeGenericToNVVMPass ( PR ) ; initialize<ISA_LIT>AllocaHoistingPass ( PR ) ; initialize<ISA_LIT>AssignValidGlobalNamesPass ( PR ) ; initialize<ISA_LIT>AtomicLowerPass ( PR ) ; initialize<ISA_LIT>LowerArgsPass ( PR ) ; initialize<ISA_LIT>LowerAllocaPass ( PR ) ; initialize<ISA_LIT>LowerAggrCopiesPass ( PR ) ; initialize<ISA_LIT>ProxyRegErasurePass ( PR ) ;"
LLVM,NVPTX,1840,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {"
LLVM,NVPTX,1841,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {"
LLVM,NVPTX,1842,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {"
LLVM,NVPTX,1843,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {"
LLVM,NVPTX,1844,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1845,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1846,"Predict the next statement of this code snippet:
 <s> PB . registerPipelineStartEPCallback ( [ this ] ( ModulePassManager & PM , OptimizationLevel Level ) { FunctionPassManager FPM ; FPM . addPass ( NVVMReflectPass ( Subtarget . getSmVersion ( ) ) ) ; PM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; } ) ;"
LLVM,NVPTX,1847,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addEarlyCSEOrGVNPass ( ) {"
LLVM,NVPTX,1848,"Predict the next statement of this code snippet:
 <s> if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGVNPass ( ) ) ; else addPass ( createEarlyCSEPass ( ) ) ;"
LLVM,NVPTX,1849,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addFastRegAlloc ( FunctionPass * RegAllocPass ) { assert ( ! RegAllocPass && <STR_LIT> ) ; addPass ( & PHIEliminationID ) ; addPass ( & TwoAddressInstructionPassID ) ;"
LLVM,NVPTX,1850,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( ! ST . hasImageHandles ( ) ) addPass ( create<ISA_LIT>ReplaceImageHandlesPass ( ) ) ;"
LLVM,NVPTX,1851,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( ! ST . hasImageHandles ( ) ) addPass ( create<ISA_LIT>ReplaceImageHandlesPass ( ) ) ; return false ;"
LLVM,NVPTX,1852,"Predict the next statement of this code snippet:
 <s> disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; addPass ( createNVVMReflectPass ( ) ) ; addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerKernelArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ; addPass ( create<ISA_LIT>FavorNonGenericAddrSpacesPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; addPass ( createSeparateConstOffsetFromGEPPass ( ) ) ; addPass ( createSpeculativeExecutionPass ( ) ) ; addPass ( createStraightLineStrengthReducePass ( ) ) ; addEarlyCSEOrGVNPass ( ) ; addPass ( createNaryReassociatePass ( ) ) ; addPass ( createEarlyCSEPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ;"
LLVM,NVPTX,1853,"Predict the next statement of this code snippet:
 <s> printAndVerify ( <STR_LIT> ) ; if ( addILPOpts ( ) ) printAndVerify ( <STR_LIT> ) ; addPass ( & MachineLICMID ) ; addPass ( & MachineCSEID ) ; addPass ( & MachineSinkingID ) ; printAndVerify ( <STR_LIT> ) ; addPass ( & PeepholeOptimizerID ) ; printAndVerify ( <STR_LIT> ) ;"
LLVM,NVPTX,1854,"Predict the next statement of this code snippet:
 <s> assert ( ! RegAllocPass && <STR_LIT> ) ; addPass ( & ProcessImplicitDefsID ) ; addPass ( & LiveVariablesID ) ; addPass ( & MachineLoopInfoID ) ; addPass ( & PHIEliminationID ) ; addPass ( & TwoAddressInstructionPassID ) ; addPass ( & RegisterCoalescerID ) ;"
LLVM,NVPTX,1855,"Predict the next statement of this code snippet:
 <s> if ( addPass ( & MachineSchedulerID ) ) printAndVerify ( <STR_LIT> ) ; addPass ( & StackSlotColoringID ) ; printAndVerify ( <STR_LIT> ) ;"
LLVM,NVPTX,1856,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>PrologEpilogPass ( ) , false ) ;"
LLVM,NVPTX,1857,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetMachine64 :: anchor ( ) {"
LLVM,NVPTX,1858,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetMachine64 :: anchor ( ) {"
LLVM,NVPTX,1859,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig * PassConfig = new <ISA_LIT>PassConfig ( this , PM ) ; return PassConfig ;"
LLVM,NVPTX,1860,"Predict the next statement of this code snippet:
 <s> return nullptr ;"
LLVM,NVPTX,1861,"Predict the next statement of this code snippet:
 <s> return nullptr ;"
LLVM,NVPTX,1862,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;"
LLVM,NVPTX,1863,"Predict the next statement of this code snippet:
 <s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;"
LLVM,NVPTX,1864,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeNVVMReflectPass ( PR ) ;"
LLVM,NVPTX,1865,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeNVVMReflectPass ( PR ) ; initializeGenericToNVVMPass ( PR ) ; initialize<ISA_LIT>AllocaHoistingPass ( PR ) ; initialize<ISA_LIT>AssignValidGlobalNamesPass ( PR ) ; initialize<ISA_LIT>FavorNonGenericAddrSpacesPass ( PR ) ; initialize<ISA_LIT>LowerKernelArgsPass ( PR ) ; initialize<ISA_LIT>LowerAllocaPass ( PR ) ;"
LLVM,NVPTX,1866,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {"
LLVM,NVPTX,1867,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {"
LLVM,NVPTX,1868,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {"
LLVM,NVPTX,1869,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {"
LLVM,NVPTX,1870,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1871,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1872,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {"
LLVM,NVPTX,1873,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {"
LLVM,NVPTX,1874,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createVectorElementizePass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false ;"
LLVM,NVPTX,1875,"Predict the next statement of this code snippet:
 <s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ;"
LLVM,NVPTX,1876,"Predict the next statement of this code snippet:
 <s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ;"
LLVM,NVPTX,1877,"Predict the next statement of this code snippet:
 <s> return & Subtarget ;"
LLVM,NVPTX,1878,"Predict the next statement of this code snippet:
 <s> bool is64Bit ( ) const {"
LLVM,NVPTX,1879,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ; RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > A ( The<ISA_LIT>Target32 ) ;"
LLVM,NVPTX,1880,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ;"
LLVM,NVPTX,1881,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {"
LLVM,NVPTX,1882,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {"
LLVM,NVPTX,1883,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {"
LLVM,NVPTX,1884,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {"
LLVM,NVPTX,1885,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1886,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1887,"Predict the next statement of this code snippet:
 <s> addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ;"
LLVM,NVPTX,1888,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addAddressSpaceInferencePasses ( ) { addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ;"
LLVM,NVPTX,1889,"Predict the next statement of this code snippet:
 <s> disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createNVVMReflectPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ;"
LLVM,NVPTX,1890,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>PrologEpilogPass ( ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>Peephole ( ) ) ;"
LLVM,NVPTX,1891,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>PrologEpilogPass ( ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) {"
LLVM,NVPTX,1892,"Predict the next statement of this code snippet:
 <s> PM . add ( createNVVMReflectPass ( ) ) ;"
LLVM,NVPTX,1893,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( getThe<ISA_LIT>Target32 ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( getThe<ISA_LIT>Target64 ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeNVVMReflectPass ( PR ) ; initializeNVVMIntrRangePass ( PR ) ; initializeGenericToNVVMPass ( PR ) ; initialize<ISA_LIT>AllocaHoistingPass ( PR ) ; initialize<ISA_LIT>AssignValidGlobalNamesPass ( PR ) ;"
LLVM,NVPTX,1894,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {"
LLVM,NVPTX,1895,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {"
LLVM,NVPTX,1896,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1897,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1898,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ;"
LLVM,NVPTX,1899,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) {"
LLVM,NVPTX,1900,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) {"
LLVM,NVPTX,1901,"Predict the next statement of this code snippet:
 <s> virtual bool addPassesToEmitMachineCode ( PassManagerBase & , JITCodeEmitter & , bool = true ) {"
LLVM,NVPTX,1902,"Predict the next statement of this code snippet:
 <s> virtual bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_ostream & , bool = true ) {"
LLVM,NVPTX,1903,"Predict the next statement of this code snippet:
 <s> virtual const DataLayout * getDataLayout ( ) const {"
LLVM,NVPTX,1904,"Predict the next statement of this code snippet:
 <s> return & FrameLowering ;"
LLVM,NVPTX,1905,"Predict the next statement of this code snippet:
 <s> virtual const TargetFrameLowering * getFrameLowering ( ) const {"
LLVM,NVPTX,1906,"Predict the next statement of this code snippet:
 <s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo ;"
LLVM,NVPTX,1907,"Predict the next statement of this code snippet:
 <s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const {"
LLVM,NVPTX,1908,"Predict the next statement of this code snippet:
 <s> ManagedStringPool * getManagedStrPool ( ) const {"
LLVM,NVPTX,1909,"Predict the next statement of this code snippet:
 <s> ManagedStringPool * getManagedStrPool ( ) const { return const_cast < ManagedStringPool * > ( & ManagedStrPool ) ;"
LLVM,NVPTX,1910,"Predict the next statement of this code snippet:
 <s> switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return std :: make_pair ( II -> getArgOperand ( <NUM_LIT> ) , llvm :: ADDRESS_SPACE_CONST ) ; case <STR_LIT> : return std :: make_pair ( II -> getArgOperand ( <NUM_LIT> ) , llvm :: ADDRESS_SPACE_GLOBAL ) ; case <STR_LIT> :"
LLVM,NVPTX,1911,"Predict the next statement of this code snippet:
 <s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const { return & ( InstrInfo . getRegisterInfo ( ) ) ;"
LLVM,NVPTX,1912,"Predict the next statement of this code snippet:
 <s> return & STTI ;"
LLVM,NVPTX,1913,"Predict the next statement of this code snippet:
 <s> return & STTI ;"
LLVM,NVPTX,1914,"Predict the next statement of this code snippet:
 <s> virtual const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const {"
LLVM,NVPTX,1915,"Predict the next statement of this code snippet:
 <s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const {"
LLVM,NVPTX,1916,"Predict the next statement of this code snippet:
 <s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const {"
LLVM,NVPTX,1917,"Predict the next statement of this code snippet:
 <s> return const_cast < <ISA_LIT>TargetLowering * > ( & TLInfo ) ;"
LLVM,NVPTX,1918,"Predict the next statement of this code snippet:
 <s> virtual const VectorTargetTransformInfo * getVectorTargetTransformInfo ( ) const {"
LLVM,NVPTX,1919,"Predict the next statement of this code snippet:
 <s> virtual const VectorTargetTransformInfo * getVectorTargetTransformInfo ( ) const { return & VTTI ;"
LLVM,NVPTX,1920,"Predict the next statement of this code snippet:
 <s> addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ;"
LLVM,NVPTX,1921,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addAddressSpaceInferencePasses ( ) { addPass ( createSROAPass ( ) ) ;"
LLVM,NVPTX,1922,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetMachine :: addEarlyAsPossiblePasses ( PassManagerBase & PM ) { PM . add ( createNVVMReflectPass ( ) ) ; PM . add ( createNVVMIntrRangePass ( Subtarget . getSmVersion ( ) ) ) ;"
LLVM,NVPTX,1923,"Predict the next statement of this code snippet:
 <s> PM . add ( createNVVMReflectPass ( ) ) ;"
LLVM,NVPTX,1924,"Predict the next statement of this code snippet:
 <s> bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_pwrite_stream & , bool = true ) override {"
LLVM,NVPTX,1925,"Predict the next statement of this code snippet:
 <s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {"
LLVM,NVPTX,1926,"Predict the next statement of this code snippet:
 <s> return new <ISA_LIT>PassConfig ( this , PM ) ;"
LLVM,NVPTX,1927,"Predict the next statement of this code snippet:
 <s> return false ;"
LLVM,NVPTX,1928,"Predict the next statement of this code snippet:
 <s> initializeNVVMIntrRangePass ( PR ) ; initializeGenericToNVVMPass ( PR ) ; initialize<ISA_LIT>AllocaHoistingPass ( PR ) ; initialize<ISA_LIT>AssignValidGlobalNamesPass ( PR ) ; initialize<ISA_LIT>InferAddressSpacesPass ( PR ) ; initialize<ISA_LIT>LowerArgsPass ( PR ) ; initialize<ISA_LIT>LowerAllocaPass ( PR ) ; initialize<ISA_LIT>LowerAggrCopiesPass ( PR ) ;"
LLVM,NVPTX,1929,"Predict the next statement of this code snippet:
 <s> bool useShortPointers ( ) const {"
LLVM,NVPTX,1930,"Predict the next statement of this code snippet:
 <s> if ( ! is64Bit ) Ret += <STR_LIT> ;"
LLVM,NVPTX,1931,"Predict the next statement of this code snippet:
 <s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM ) { if ( CM ) return * CM ;"
LLVM,NVPTX,1932,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID ) ; disablePass ( & TailDuplicateID ) ; addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ;"
LLVM,NVPTX,1933,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { addPass ( create<ISA_LIT>PrologEpilogPass ( ) , false ) ;"
LLVM,NVPTX,1934,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>PrologEpilogPass ( ) , false ) ;"
LLVM,NVPTX,1935,"Predict the next statement of this code snippet:
 <s> TargetIRAnalysis <ISA_LIT>TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ) ) ; } ) ;"
LLVM,NVPTX,1936,"Predict the next statement of this code snippet:
 <s> TargetIRAnalysis <ISA_LIT>TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ) ) ; } ) ;"
LLVM,NVPTX,1937,"Predict the next statement of this code snippet:
 <s> initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ; initializeGenericToNVVMPass ( * PassRegistry :: getPassRegistry ( ) ) ; initialize<ISA_LIT>AssignValidGlobalNamesPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,1938,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ; initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,1939,"Predict the next statement of this code snippet:
 <s> return const_cast < <ISA_LIT>TargetLowering * > ( & TLInfo ) ;"
LLVM,NVPTX,1940,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {"
LLVM,NVPTX,1941,"Predict the next statement of this code snippet:
 <s> addPass ( createAllocaHoisting ( ) ) ; addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;"
LLVM,NVPTX,1942,"Predict the next statement of this code snippet:
 <s> addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>FavorNonGenericAddrSpacesPass ( ) ) ; addPass ( createSeparateConstOffsetFromGEPPass ( ) ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGVNPass ( ) ) ;"
LLVM,NVPTX,1943,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>FavorNonGenericAddrSpacesPass ( ) ) ; addPass ( createSeparateConstOffsetFromGEPPass ( ) ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGVNPass ( ) ) ;"
LLVM,NVPTX,1944,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>PrologEpilogPass ( ) ) ; return false ;"
LLVM,NVPTX,1945,"Predict the next statement of this code snippet:
 <s> return false ;"
LLVM,NVPTX,1946,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ; initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,1947,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {"
LLVM,NVPTX,1948,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {"
LLVM,NVPTX,1949,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1950,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1951,"Predict the next statement of this code snippet:
 <s> disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const <ISA_LIT>Subtarget & ST = * getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ;"
LLVM,NVPTX,1952,"Predict the next statement of this code snippet:
 <s> bool addRegAssignmentOptimized ( ) override {"
LLVM,NVPTX,1953,"Predict the next statement of this code snippet:
 <s> initializeNVVMIntrRangePass ( PR ) ; initializeGenericToNVVMPass ( PR ) ; initialize<ISA_LIT>AllocaHoistingPass ( PR ) ; initialize<ISA_LIT>AssignValidGlobalNamesPass ( PR ) ; initialize<ISA_LIT>LowerArgsPass ( PR ) ; initialize<ISA_LIT>LowerAllocaPass ( PR ) ; initialize<ISA_LIT>LowerAggrCopiesPass ( PR ) ; initialize<ISA_LIT>ProxyRegErasurePass ( PR ) ;"
LLVM,NVPTX,1954,"Predict the next statement of this code snippet:
 <s> initialize<ISA_LIT>AssignValidGlobalNamesPass ( PR ) ; initialize<ISA_LIT>LowerArgsPass ( PR ) ; initialize<ISA_LIT>LowerAllocaPass ( PR ) ; initialize<ISA_LIT>LowerAggrCopiesPass ( PR ) ; initialize<ISA_LIT>ProxyRegErasurePass ( PR ) ;"
LLVM,NVPTX,1955,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( is64bit , UseShortPointersOpt ) , TT , CPU , FS , Options , Reloc :: PIC_ , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , is64bit ( is64bit ) , UseShortPointers ( UseShortPointersOpt ) , TLOF ( llvm :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {"
LLVM,NVPTX,1956,"Predict the next statement of this code snippet:
 <s> disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID ) ; disablePass ( & TailDuplicateID ) ; addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ;"
LLVM,NVPTX,1957,"Predict the next statement of this code snippet:
 <s> if ( ! ST . is64Bit ( ) ) Ret += <STR_LIT> ;"
LLVM,NVPTX,1958,"Predict the next statement of this code snippet:
 <s> disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const <ISA_LIT>Subtarget & ST = * getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ;"
LLVM,NVPTX,1959,"Predict the next statement of this code snippet:
 <s> disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const <ISA_LIT>Subtarget & ST = * getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; addStraightLineScalarOptimizationPasses ( ) ; } addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addEarlyCSEOrGVNPass ( ) ; if ( ! DisableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addPass ( createSROAPass ( ) ) ;"
LLVM,NVPTX,1960,"Predict the next statement of this code snippet:
 <s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) const {"
LLVM,NVPTX,1961,"Predict the next statement of this code snippet:
 <s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) const {"
LLVM,NVPTX,1962,"Predict the next statement of this code snippet:
 <s> disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID ) ; disablePass ( & TailDuplicateID ) ; addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerKernelArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ;"
LLVM,NVPTX,1963,"Predict the next statement of this code snippet:
 <s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;"
LLVM,NVPTX,1964,"Predict the next statement of this code snippet:
 <s> return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } ) ;"
LLVM,NVPTX,1965,"Predict the next statement of this code snippet:
 <s> initialize<ISA_LIT>AssignValidGlobalNamesPass ( * PassRegistry :: getPassRegistry ( ) ) ; initialize<ISA_LIT>FavorNonGenericAddrSpacesPass ( * PassRegistry :: getPassRegistry ( ) ) ; initialize<ISA_LIT>LowerKernelArgsPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,1966,"Predict the next statement of this code snippet:
 <s> if ( UseInferAddressSpaces ) { addPass ( create<ISA_LIT>InferAddressSpacesPass ( ) ) ; } else {"
LLVM,NVPTX,1967,"Predict the next statement of this code snippet:
 <s> addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ;"
LLVM,NVPTX,1968,"Predict the next statement of this code snippet:
 <s> initializeNVVMReflectPass ( PR ) ; initializeNVVMIntrRangePass ( PR ) ; initializeGenericToNVVMPass ( PR ) ; initialize<ISA_LIT>AllocaHoistingPass ( PR ) ; initialize<ISA_LIT>AssignValidGlobalNamesPass ( PR ) ; initialize<ISA_LIT>FavorNonGenericAddrSpacesPass ( PR ) ; initialize<ISA_LIT>InferAddressSpacesPass ( PR ) ; initialize<ISA_LIT>LowerArgsPass ( PR ) ; initialize<ISA_LIT>LowerAllocaPass ( PR ) ;"
LLVM,NVPTX,1969,"Predict the next statement of this code snippet:
 <s> initialize<ISA_LIT>AllocaHoistingPass ( PR ) ; initialize<ISA_LIT>AssignValidGlobalNamesPass ( PR ) ; initialize<ISA_LIT>FavorNonGenericAddrSpacesPass ( PR ) ; initialize<ISA_LIT>InferAddressSpacesPass ( PR ) ; initialize<ISA_LIT>LowerArgsPass ( PR ) ;"
LLVM,NVPTX,1970,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB ) { PB . registerPipelineParsingCallback ( [ ] ( StringRef PassName , FunctionPassManager & PM , ArrayRef < PassBuilder :: PipelineElement > ) { if ( PassName == <STR_LIT> ) { PM . addPass ( NVVMReflectPass ( ) ) ; return true ; } if ( PassName == <STR_LIT> ) { PM . addPass ( NVVMIntrRangePass ( ) ) ; return true ; }"
LLVM,NVPTX,1971,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ; initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,1972,"Predict the next statement of this code snippet:
 <s> assert ( ! RegAllocPass && <STR_LIT> ) ; addPass ( & StrongPHIEliminationID ) ;"
LLVM,NVPTX,1973,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID ) ; TargetPassConfig :: addIRPasses ( ) ; addPass ( createGenericToNVVMPass ( ) ) ;"
LLVM,NVPTX,1974,"Predict the next statement of this code snippet:
 <s> disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ;"
LLVM,NVPTX,1975,"Predict the next statement of this code snippet:
 <s> FunctionPass * <ISA_LIT>PassConfig :: createTargetRegisterAllocator ( bool ) { return <NUM_LIT> ;"
LLVM,NVPTX,1976,"Predict the next statement of this code snippet:
 <s> return & DataLayout ;"
LLVM,NVPTX,1977,"Predict the next statement of this code snippet:
 <s> RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ; RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > A ( The<ISA_LIT>Target32 ) ; RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > B ( The<ISA_LIT>Target64 ) ; initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ; initializeGenericToNVVMPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,1978,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) {"
LLVM,NVPTX,1979,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerKernelArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>FavorNonGenericAddrSpacesPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ;"
LLVM,NVPTX,1980,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ;"
LLVM,NVPTX,1981,"Predict the next statement of this code snippet:
 <s> initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ; initializeGenericToNVVMPass ( * PassRegistry :: getPassRegistry ( ) ) ; initialize<ISA_LIT>AllocaHoistingPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,1982,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( is64bit ) , TT , CPU , FS , Options , RM , CM , OL ) , is64bit ( is64bit ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { if ( Triple ( TT ) . getOS ( ) == Triple :: NVCL ) drvInterface = <STR_LIT> ; else drvInterface = <STR_LIT> ;"
LLVM,NVPTX,1983,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetMachine :: addAnalysisPasses ( PassManagerBase & PM ) { PM . add ( createBasicTargetTransformInfoPass ( this ) ) ;"
LLVM,NVPTX,1984,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) {"
LLVM,NVPTX,1985,"Predict the next statement of this code snippet:
 <s> disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; addPass ( createNVVMReflectPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ;"
LLVM,NVPTX,1986,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( is64bit ) , TT , CPU , FS , Options , Reloc :: PIC_ , getEffectiveCodeModel ( CM ) , OL ) , is64bit ( is64bit ) , TLOF ( llvm :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { if ( TT . getOS ( ) == Triple :: NVCL ) drvInterface = <STR_LIT> ; else drvInterface = <STR_LIT> ;"
LLVM,NVPTX,1987,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( is64bit , UseShortPointersOpt ) , TT , CPU , FS , Options , Reloc :: PIC_ , getEffectiveCodeModel ( CM ) , OL ) , is64bit ( is64bit ) , UseShortPointers ( UseShortPointersOpt ) , TLOF ( llvm :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {"
LLVM,NVPTX,1988,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ;"
LLVM,NVPTX,1989,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) {"
LLVM,NVPTX,1990,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) {"
LLVM,NVPTX,1991,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) {"
LLVM,NVPTX,1992,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) {"
LLVM,NVPTX,1993,"Predict the next statement of this code snippet:
 <s> initialize<ISA_LIT>AllocaHoistingPass ( * PassRegistry :: getPassRegistry ( ) ) ; initialize<ISA_LIT>AssignValidGlobalNamesPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,1994,"Predict the next statement of this code snippet:
 <s> disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID ) ; disablePass ( & TailDuplicateID ) ; TargetPassConfig :: addIRPasses ( ) ;"
LLVM,NVPTX,1995,"Predict the next statement of this code snippet:
 <s> disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID ) ;"
LLVM,NVPTX,1996,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerKernelArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ; addPass ( create<ISA_LIT>FavorNonGenericAddrSpacesPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; addPass ( createSeparateConstOffsetFromGEPPass ( ) ) ; addPass ( createSpeculativeExecutionPass ( ) ) ; addPass ( createStraightLineStrengthReducePass ( ) ) ; addEarlyCSEOrGVNPass ( ) ;"
LLVM,NVPTX,1997,"Predict the next statement of this code snippet:
 <s> disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerKernelArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ; addPass ( create<ISA_LIT>FavorNonGenericAddrSpacesPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; addPass ( createSeparateConstOffsetFromGEPPass ( ) ) ; addPass ( createSpeculativeExecutionPass ( ) ) ;"
LLVM,NVPTX,1998,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createNVVMReflectPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ;"
LLVM,NVPTX,1999,"Predict the next statement of this code snippet:
 <s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ;"
LLVM,NVPTX,2000,"Predict the next statement of this code snippet:
 <s> disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const <ISA_LIT>Subtarget & ST = * getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getTM < <ISA_LIT>TargetMachine > ( ) . getTargetTriple ( ) . getOS ( ) == Triple :: CUDA ) { addPass ( createGlobalOffsetPass ( ) ) ; addPass ( createLocalAccessorToSharedMemoryPass ( ) ) ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) {"
LLVM,NVPTX,2001,"Predict the next statement of this code snippet:
 <s> disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const <ISA_LIT>Subtarget & ST = * getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getTM < <ISA_LIT>TargetMachine > ( ) . getTargetTriple ( ) . getOS ( ) == Triple :: CUDA ) { addPass ( createGlobalOffsetPass ( ) ) ; addPass ( createLocalAccessorToSharedMemoryPass ( ) ) ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ;"
LLVM,NVPTX,2002,"Predict the next statement of this code snippet:
 <s> PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeNVVMReflectPass ( PR ) ; initializeNVVMIntrRangePass ( PR ) ; initializeGenericToNVVMPass ( PR ) ; initialize<ISA_LIT>AllocaHoistingPass ( PR ) ; initialize<ISA_LIT>AssignValidGlobalNamesPass ( PR ) ; initialize<ISA_LIT>AtomicLowerPass ( PR ) ;"
LLVM,NVPTX,2003,"Predict the next statement of this code snippet:
 <s> disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const <ISA_LIT>Subtarget & ST = * getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getTM < <ISA_LIT>TargetMachine > ( ) . getTargetTriple ( ) . getOS ( ) == Triple :: CUDA && getTM < <ISA_LIT>TargetMachine > ( ) . getTargetTriple ( ) . getEnvironment ( ) == Triple :: SYCLDevice ) { addPass ( createLocalAccessorToSharedMemoryPass ( ) ) ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addEarlyCSEOrGVNPass ( ) ;"
LLVM,NVPTX,2004,"Predict the next statement of this code snippet:
 <s> disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const <ISA_LIT>Subtarget & ST = * getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getTM < <ISA_LIT>TargetMachine > ( ) . getTargetTriple ( ) . getOS ( ) == Triple :: CUDA && getTM < <ISA_LIT>TargetMachine > ( ) . getTargetTriple ( ) . getEnvironment ( ) == Triple :: SYCLDevice ) {"
LLVM,NVPTX,2005,"Predict the next statement of this code snippet:
 <s> PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeNVVMReflectPass ( PR ) ; initializeNVVMIntrRangePass ( PR ) ; initializeGenericToNVVMPass ( PR ) ;"
LLVM,NVPTX,2006,"Predict the next statement of this code snippet:
 <s> disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; addPass ( createNVVMReflectPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ;"
LLVM,NVPTX,2007,"Predict the next statement of this code snippet:
 <s> disablePass ( & TailDuplicateID ) ; addPass ( createNVVMReflectPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addMemorySpaceInferencePasses ( ) ; addStraightLineScalarOptimizationPasses ( ) ;"
LLVM,NVPTX,2008,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>FavorNonGenericAddrSpacesPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ;"
LLVM,NVPTX,2009,"Predict the next statement of this code snippet:
 <s> addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ; addPass ( create<ISA_LIT>FavorNonGenericAddrSpacesPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ;"
LLVM,NVPTX,2010,"Predict the next statement of this code snippet:
 <s> disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const <ISA_LIT>Subtarget & ST = * getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ; addPass ( create<ISA_LIT>AssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( create<ISA_LIT>LowerArgsPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ;"
LLVM,NVPTX,2011,"Predict the next statement of this code snippet:
 <s> bool addPassesToEmitMachineCode ( PassManagerBase & , JITCodeEmitter & , bool = true ) override {"
LLVM,NVPTX,2012,"Predict the next statement of this code snippet:
 <s> bool addPassesToEmitMachineCode ( PassManagerBase & , JITCodeEmitter & , bool = true ) override { return true ;"
LLVM,NVPTX,2013,"Predict the next statement of this code snippet:
 <s> return getSubtargetImpl ( ) -> getFrameLowering ( ) ;"
LLVM,NVPTX,2014,"Predict the next statement of this code snippet:
 <s> return getSubtargetImpl ( ) -> getInstrInfo ( ) ;"
LLVM,NVPTX,2015,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override {"
LLVM,NVPTX,2016,"Predict the next statement of this code snippet:
 <s> return const_cast < ManagedStringPool * > ( & ManagedStrPool ) ;"
LLVM,NVPTX,2017,"Predict the next statement of this code snippet:
 <s> ManagedStringPool * getManagedStrPool ( ) const { return const_cast < ManagedStringPool * > ( & ManagedStrPool ) ;"
LLVM,NVPTX,2018,"Predict the next statement of this code snippet:
 <s> return getSubtargetImpl ( ) -> getRegisterInfo ( ) ;"
LLVM,NVPTX,2019,"Predict the next statement of this code snippet:
 <s> return getSubtargetImpl ( ) -> getSelectionDAGInfo ( ) ;"
LLVM,NVPTX,2020,"Predict the next statement of this code snippet:
 <s> return getSubtargetImpl ( ) -> getSelectionDAGInfo ( ) ;"
LLVM,NVPTX,2021,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override {"
LLVM,NVPTX,2022,"Predict the next statement of this code snippet:
 <s> return & Subtarget ;"
LLVM,NVPTX,2023,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {"
LLVM,NVPTX,2024,"Predict the next statement of this code snippet:
 <s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {"
LLVM,NVPTX,2025,"Predict the next statement of this code snippet:
 <s> DataSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getData ( ) ) ; BSSSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;"
LLVM,NVPTX,2026,"Predict the next statement of this code snippet:
 <s> TargetLoweringObjectFile :: Initialize ( ctx , TM ) ; TextSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getText ( ) ) ; DataSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getData ( ) ) ; BSSSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;"
LLVM,NVPTX,2027,"Predict the next statement of this code snippet:
 <s> StaticDtorSection = nullptr ; LSDASection = nullptr ; EHFrameSection = nullptr ; DwarfAbbrevSection = nullptr ; DwarfInfoSection = nullptr ; DwarfLineSection = nullptr ; DwarfFrameSection = nullptr ; DwarfPubTypesSection = nullptr ; DwarfDebugInlineSection = nullptr ; DwarfStrSection = nullptr ; DwarfLocSection = nullptr ; DwarfARangesSection = nullptr ;"
LLVM,NVPTX,2028,"Predict the next statement of this code snippet:
 <s> MCSection * getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const override { return DataSection ;"
LLVM,NVPTX,2029,"Predict the next statement of this code snippet:
 <s> MCSection * getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const override {"
LLVM,NVPTX,2030,"Predict the next statement of this code snippet:
 <s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const override {"
LLVM,NVPTX,2031,"Predict the next statement of this code snippet:
 <s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const override {"
LLVM,NVPTX,2032,"Predict the next statement of this code snippet:
 <s> TargetLoweringObjectFile :: Initialize ( ctx , TM ) ;"
LLVM,NVPTX,2033,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetObjectFile ( ) : TargetLoweringObjectFile ( ) {"
LLVM,NVPTX,2034,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetObjectFile ( ) : TargetLoweringObjectFile ( ) {"
LLVM,NVPTX,2035,"Predict the next statement of this code snippet:
 <s> EHFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;"
LLVM,NVPTX,2036,"Predict the next statement of this code snippet:
 <s> BSSSection = nullptr ; ReadOnlySection = nullptr ; StaticCtorSection = nullptr ; StaticDtorSection = nullptr ; LSDASection = nullptr ; EHFrameSection = nullptr ; DwarfAbbrevSection = nullptr ; DwarfInfoSection = nullptr ; DwarfLineSection = nullptr ; DwarfFrameSection = nullptr ; DwarfPubTypesSection = nullptr ; DwarfDebugInlineSection = nullptr ; DwarfStrSection = nullptr ;"
LLVM,NVPTX,2037,"Predict the next statement of this code snippet:
 <s> StaticCtorSection = <NUM_LIT> ; StaticDtorSection = <NUM_LIT> ; LSDASection = <NUM_LIT> ; EHFrameSection = <NUM_LIT> ; DwarfAbbrevSection = <NUM_LIT> ; DwarfInfoSection = <NUM_LIT> ; DwarfLineSection = <NUM_LIT> ; DwarfFrameSection = <NUM_LIT> ; DwarfPubTypesSection = <NUM_LIT> ; DwarfDebugInlineSection = <NUM_LIT> ; DwarfStrSection = <NUM_LIT> ; DwarfLocSection = <NUM_LIT> ; DwarfARangesSection = <NUM_LIT> ; DwarfRangesSection = <NUM_LIT> ;"
LLVM,NVPTX,2038,"Predict the next statement of this code snippet:
 <s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align , const GlobalObject * GO ) const override {"
LLVM,NVPTX,2039,"Predict the next statement of this code snippet:
 <s> MCSection * getSectionForConstant ( SectionKind Kind , const Constant * C ) const override { return ReadOnlySection ;"
LLVM,NVPTX,2040,"Predict the next statement of this code snippet:
 <s> DataSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getDataRel ( ) ) ; BSSSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;"
LLVM,NVPTX,2041,"Predict the next statement of this code snippet:
 <s> virtual const MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM ) const { return DataSection ;"
LLVM,NVPTX,2042,"Predict the next statement of this code snippet:
 <s> virtual const MCSection * getSectionForConstant ( SectionKind Kind ) const { return ReadOnlySection ;"
LLVM,NVPTX,2043,"Predict the next statement of this code snippet:
 <s> DwarfAbbrevSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLocSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfARangesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;"
LLVM,NVPTX,2044,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetObjectFile ( ) {"
LLVM,NVPTX,2045,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetObjectFile ( ) {"
LLVM,NVPTX,2046,"Predict the next statement of this code snippet:
 <s> delete DwarfFrameSection ; delete DwarfPubTypesSection ; delete DwarfDebugInlineSection ; delete DwarfStrSection ; delete DwarfLocSection ; delete DwarfARangesSection ; delete DwarfRangesSection ;"
LLVM,NVPTX,2047,"Predict the next statement of this code snippet:
 <s> delete EHFrameSection ; delete DwarfAbbrevSection ; delete DwarfInfoSection ; delete DwarfLineSection ; delete DwarfFrameSection ; delete DwarfPubTypesSection ; delete DwarfDebugInlineSection ;"
LLVM,NVPTX,2048,"Predict the next statement of this code snippet:
 <s> ReadOnlySection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;"
LLVM,NVPTX,2049,"Predict the next statement of this code snippet:
 <s> const MCSection * getSectionForConstant ( SectionKind Kind , const Constant * C ) const override { return ReadOnlySection ;"
LLVM,NVPTX,2050,"Predict the next statement of this code snippet:
 <s> const MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const override { return DataSection ;"
LLVM,NVPTX,2051,"Predict the next statement of this code snippet:
 <s> const MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const override {"
LLVM,NVPTX,2052,"Predict the next statement of this code snippet:
 <s> const MCSection * getSectionForConstant ( SectionKind Kind ) const override { return ReadOnlySection ;"
LLVM,NVPTX,2053,"Predict the next statement of this code snippet:
 <s> const MCSection * getSectionForConstant ( SectionKind Kind ) const override { return ReadOnlySection ;"
LLVM,NVPTX,2054,"Predict the next statement of this code snippet:
 <s> BSSSection = nullptr ; ReadOnlySection = nullptr ; StaticCtorSection = nullptr ; StaticDtorSection = nullptr ; LSDASection = nullptr ; EHFrameSection = nullptr ; DwarfAbbrevSection = nullptr ; DwarfInfoSection = nullptr ; DwarfLineSection = nullptr ; DwarfFrameSection = nullptr ;"
LLVM,NVPTX,2055,"Predict the next statement of this code snippet:
 <s> OS << <STR_LIT> ; Section -> PrintSwitchToSection ( * getStreamer ( ) . getContext ( ) . getAsmInfo ( ) , FI -> getTargetTriple ( ) , OS , SubSection ) ; OS << <STR_LIT> ; }"
LLVM,NVPTX,2056,"Predict the next statement of this code snippet:
 <s> assert ( ! SubSection && <STR_LIT> ) ; const MCObjectFileInfo * FI = getStreamer ( ) . getContext ( ) . getObjectFileInfo ( ) ; if ( isDwarfSection ( FI , CurSection ) ) OS << <STR_LIT> ; if ( isDwarfSection ( FI , Section ) ) { outputDwarfFileDirectives ( ) ; OS << <STR_LIT> ;"
LLVM,NVPTX,2057,"Predict the next statement of this code snippet:
 <s> DwarfFiles . emplace_back ( Directive ) ;"
LLVM,NVPTX,2058,"Predict the next statement of this code snippet:
 <s> DwarfFiles . emplace_back ( Directive ) ;"
LLVM,NVPTX,2059,"Predict the next statement of this code snippet:
 <s> const MCAsmInfo * MAI = Streamer . getContext ( ) . getAsmInfo ( ) ; const char * Directive = MAI -> getData8bitsDirective ( ) ; unsigned NumElements = Data . size ( ) ; const unsigned MaxLen = <NUM_LIT> ; unsigned NumChunks = <NUM_LIT> + ( ( NumElements - <NUM_LIT> ) / MaxLen ) ; for ( unsigned I = <NUM_LIT> ; I < NumChunks ; ++ I ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; const char * Label = Directive ; for ( auto It = std :: next ( Data . bytes_begin ( ) , I * MaxLen ) , End = ( I == NumChunks - <NUM_LIT> ) ? Data . bytes_end ( ) : std :: next ( Data . bytes_begin ( ) , ( I + <NUM_LIT> ) * MaxLen ) ; It != End ; ++ It ) { OS << Label << ( unsigned ) * It ; if ( Label == Directive ) Label = <STR_LIT> ; } Streamer . EmitRawText ( OS . str ( ) ) ;"
LLVM,NVPTX,2060,"Predict the next statement of this code snippet:
 <s> if ( ! Section || Section -> getKind ( ) . isText ( ) || Section -> getKind ( ) . isWriteable ( ) ) return false ; return Section == FI -> getDwarfAbbrevSection ( ) || Section == FI -> getDwarfInfoSection ( ) || Section == FI -> getDwarfMacinfoSection ( ) || Section == FI -> getDwarfFrameSection ( ) || Section == FI -> getDwarfAddrSection ( ) || Section == FI -> getDwarfRangesSection ( ) || Section == FI -> getDwarfARangesSection ( ) || Section == FI -> getDwarfLocSection ( ) || Section == FI -> getDwarfStrSection ( ) || Section == FI -> getDwarfLineSection ( ) || Section == FI -> getDwarfStrOffSection ( ) || Section == FI -> getDwarfLineStrSection ( ) || Section == FI -> getDwarfPubNamesSection ( ) || Section == FI -> getDwarfPubTypesSection ( ) || Section == FI -> getDwarfSwiftASTSection ( ) || Section == FI -> getDwarfTypesDWOSection ( ) || Section == FI -> getDwarfAbbrevDWOSection ( ) || Section == FI -> getDwarfAccelObjCSection ( ) || Section == FI -> getDwarfAccelNamesSection ( ) || Section == FI -> getDwarfAccelTypesSection ( ) || Section == FI -> getDwarfAccelNamespaceSection ( ) || Section == FI -> getDwarfLocDWOSection ( ) || Section == FI -> getDwarfStrDWOSection ( ) || Section == FI -> getDwarfCUIndexSection ( ) || Section == FI -> getDwarfInfoDWOSection ( ) || Section == FI -> getDwarfLineDWOSection ( ) || Section == FI -> getDwarfTUIndexSection ( ) || Section == FI -> getDwarfStrOffDWOSection ( ) || Section == FI -> getDwarfDebugNamesSection ( ) || Section == FI -> getDwarfDebugInlineSection ( ) || Section == FI -> getDwarfGnuPubNamesSection ( ) || Section == FI -> getDwarfGnuPubTypesSection ( ) ;"
LLVM,NVPTX,2061,"Predict the next statement of this code snippet:
 <s> static bool isDwarfSection ( const MCObjectFileInfo * FI , const MCSection * Section ) { if ( ! Section || Section -> getKind ( ) . isText ( ) || Section -> getKind ( ) . isWriteable ( ) ) return false ; return Section == FI -> getDwarfAbbrevSection ( ) || Section == FI -> getDwarfInfoSection ( ) || Section == FI -> getDwarfMacinfoSection ( ) || Section == FI -> getDwarfFrameSection ( ) || Section == FI -> getDwarfAddrSection ( ) || Section == FI -> getDwarfRangesSection ( ) || Section == FI -> getDwarfARangesSection ( ) || Section == FI -> getDwarfLocSection ( ) || Section == FI -> getDwarfStrSection ( ) || Section == FI -> getDwarfLineSection ( ) || Section == FI -> getDwarfStrOffSection ( ) || Section == FI -> getDwarfLineStrSection ( ) || Section == FI -> getDwarfPubNamesSection ( ) || Section == FI -> getDwarfPubTypesSection ( ) || Section == FI -> getDwarfSwiftASTSection ( ) || Section == FI -> getDwarfTypesDWOSection ( ) || Section == FI -> getDwarfAbbrevDWOSection ( ) || Section == FI -> getDwarfAccelObjCSection ( ) || Section == FI -> getDwarfAccelNamesSection ( ) || Section == FI -> getDwarfAccelTypesSection ( ) || Section == FI -> getDwarfAccelNamespaceSection ( ) || Section == FI -> getDwarfLocDWOSection ( ) || Section == FI -> getDwarfStrDWOSection ( ) || Section == FI -> getDwarfCUIndexSection ( ) || Section == FI -> getDwarfInfoDWOSection ( ) || Section == FI -> getDwarfLineDWOSection ( ) || Section == FI -> getDwarfTUIndexSection ( ) || Section == FI -> getDwarfStrOffDWOSection ( ) || Section == FI -> getDwarfDebugNamesSection ( ) || Section == FI -> getDwarfDebugInlineSection ( ) || Section == FI -> getDwarfGnuPubNamesSection ( ) || Section == FI -> getDwarfGnuPubTypesSection ( ) ;"
LLVM,NVPTX,2062,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {"
LLVM,NVPTX,2063,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {"
LLVM,NVPTX,2064,"Predict the next statement of this code snippet:
 <s> if ( isDwarfSection ( FI , CurSection ) ) OS << <STR_LIT> ; if ( isDwarfSection ( FI , Section ) ) { for ( const std :: string & S : DwarfFiles ) getStreamer ( ) . EmitRawText ( S . data ( ) ) ;"
LLVM,NVPTX,2065,"Predict the next statement of this code snippet:
 <s> DwarfFiles . clear ( ) ; OS << <STR_LIT> ; Section -> PrintSwitchToSection ( * getStreamer ( ) . getContext ( ) . getAsmInfo ( ) , FI -> getTargetTriple ( ) , OS , SubSection ) ; OS << <STR_LIT> ; }"
LLVM,NVPTX,2066,"Predict the next statement of this code snippet:
 <s> if ( isDwarfSection ( FI , CurSection ) ) OS << <STR_LIT> ; if ( isDwarfSection ( FI , Section ) ) { outputDwarfFileDirectives ( ) ; OS << <STR_LIT> ; Section -> PrintSwitchToSection ( * getStreamer ( ) . getContext ( ) . getAsmInfo ( ) , FI -> getTargetTriple ( ) , OS , SubSection ) ; OS << <STR_LIT> ;"
LLVM,NVPTX,2067,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: changeSection ( const MCSection * CurSection , MCSection * Section , const MCExpr * SubSection , raw_ostream & OS ) { assert ( ! SubSection && <STR_LIT> ) ; const MCObjectFileInfo * FI = getStreamer ( ) . getContext ( ) . getObjectFileInfo ( ) ; if ( isDwarfSection ( FI , CurSection ) ) OS << <STR_LIT> ; if ( isDwarfSection ( FI , Section ) ) { outputDwarfFileDirectives ( ) ;"
LLVM,NVPTX,2068,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: closeLastSection ( ) { if ( HasSections ) getStreamer ( ) . EmitRawText ( <STR_LIT> ) ;"
LLVM,NVPTX,2069,"Predict the next statement of this code snippet:
 <s> outputDwarfFileDirectives ( ) ; OS << <STR_LIT> ;"
LLVM,NVPTX,2070,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: outputDwarfFileDirectives ( ) {"
LLVM,NVPTX,2071,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: outputDwarfFileDirectives ( ) {"
LLVM,NVPTX,2072,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: emitRawBytes ( StringRef Data ) { MCTargetStreamer :: emitRawBytes ( Data ) ; const MCAsmInfo * MAI = Streamer . getContext ( ) . getAsmInfo ( ) ; const char * Directive = MAI -> getData8bitsDirective ( ) ; unsigned NumElements = Data . size ( ) ; const unsigned MaxLen = <NUM_LIT> ; unsigned NumChunks = <NUM_LIT> + ( ( NumElements - <NUM_LIT> ) / MaxLen ) ; for ( unsigned I = <NUM_LIT> ; I < NumChunks ; ++ I ) { SmallString < <NUM_LIT> > Str ;"
LLVM,NVPTX,2073,"Predict the next statement of this code snippet:
 <s> if ( isDwarfSection ( FI , CurSection ) ) OS << <STR_LIT> ; if ( isDwarfSection ( FI , Section ) ) { outputDwarfFileDirectives ( ) ; OS << <STR_LIT> ; Section -> PrintSwitchToSection ( * getStreamer ( ) . getContext ( ) . getAsmInfo ( ) , getStreamer ( ) . getContext ( ) . getTargetTriple ( ) , OS , SubSection ) ;"
LLVM,NVPTX,2074,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: closeLastSection ( ) {"
LLVM,NVPTX,2075,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: closeLastSection ( ) { if ( HasSections ) getStreamer ( ) . emitRawText ( <STR_LIT> ) ;"
LLVM,NVPTX,2076,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: emitRawBytes ( StringRef Data ) { MCTargetStreamer :: emitRawBytes ( Data ) ; const MCAsmInfo * MAI = Streamer . getContext ( ) . getAsmInfo ( ) ; const char * Directive = MAI -> getData8bitsDirective ( ) ; unsigned NumElements = Data . size ( ) ; const unsigned MaxLen = <NUM_LIT> ; unsigned NumChunks = <NUM_LIT> + ( ( NumElements - <NUM_LIT> ) / MaxLen ) ; for ( unsigned I = <NUM_LIT> ; I < NumChunks ; ++ I ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; const char * Label = Directive ; for ( auto It = std :: next ( Data . bytes_begin ( ) , I * MaxLen ) , End = ( I == NumChunks - <NUM_LIT> ) ? Data . bytes_end ( ) : std :: next ( Data . bytes_begin ( ) , ( I + <NUM_LIT> ) * MaxLen ) ; It != End ; ++ It ) {"
LLVM,NVPTX,2077,"Predict the next statement of this code snippet:
 <s> const MCAsmInfo * MAI = Streamer . getContext ( ) . getAsmInfo ( ) ; const char * Directive = MAI -> getData8bitsDirective ( ) ; unsigned NumElements = Data . size ( ) ; const unsigned MaxLen = <NUM_LIT> ; unsigned NumChunks = <NUM_LIT> + ( ( NumElements - <NUM_LIT> ) / MaxLen ) ; for ( unsigned I = <NUM_LIT> ; I < NumChunks ; ++ I ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; const char * Label = Directive ; for ( auto It = std :: next ( Data . bytes_begin ( ) , I * MaxLen ) , End = ( I == NumChunks - <NUM_LIT> ) ? Data . bytes_end ( ) : std :: next ( Data . bytes_begin ( ) , ( I + <NUM_LIT> ) * MaxLen ) ;"
LLVM,NVPTX,2078,"Predict the next statement of this code snippet:
 <s> for ( const std :: string & S : DwarfFiles ) getStreamer ( ) . emitRawText ( S ) ;"
LLVM,NVPTX,2079,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TargetStreamer :: outputDwarfFileDirectives ( ) { for ( const std :: string & S : DwarfFiles ) getStreamer ( ) . emitRawText ( S ) ;"
LLVM,NVPTX,2080,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( LT . second . SimpleTy == <STR_LIT> ) return <NUM_LIT> * LT . first ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ;"
LLVM,NVPTX,2081,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) {"
LLVM,NVPTX,2082,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TTIImpl ( <ISA_LIT>TTIImpl && Arg ) : BaseT ( std :: move ( static_cast < BaseT & > ( Arg ) ) ) , ST ( std :: move ( Arg . ST ) ) , TLI ( std :: move ( Arg . TLI ) ) {"
LLVM,NVPTX,2083,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TTIImpl ( <ISA_LIT>TTIImpl && Arg ) : BaseT ( std :: move ( static_cast < BaseT & > ( Arg ) ) ) , ST ( std :: move ( Arg . ST ) ) , TLI ( std :: move ( Arg . TLI ) ) {"
LLVM,NVPTX,2084,"Predict the next statement of this code snippet:
 <s> static bool readsLaneId ( const IntrinsicInst * II ) { return II -> getIntrinsicID ( ) == <STR_LIT> ;"
LLVM,NVPTX,2085,"Predict the next statement of this code snippet:
 <s> bool isLegalToVectorizeLoadChain ( unsigned ChainSizeInBytes , Align Alignment , unsigned AddrSpace ) const {"
LLVM,NVPTX,2086,"Predict the next statement of this code snippet:
 <s> bool isLegalToVectorizeStoreChain ( unsigned ChainSizeInBytes , Align Alignment , unsigned AddrSpace ) const {"
LLVM,NVPTX,2087,"Predict the next statement of this code snippet:
 <s> InstructionCost <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) {"
LLVM,NVPTX,2088,"Predict the next statement of this code snippet:
 <s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( LT . second . SimpleTy == <STR_LIT> ) return <NUM_LIT> * LT . first ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; }"
LLVM,NVPTX,2089,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) {"
LLVM,NVPTX,2090,"Predict the next statement of this code snippet:
 <s> TypeSize getRegisterBitWidth ( TargetTransformInfo :: RegisterKind K ) const {"
LLVM,NVPTX,2091,"Predict the next statement of this code snippet:
 <s> UP . Partial = UP . Runtime = true ;"
LLVM,NVPTX,2092,"Predict the next statement of this code snippet:
 <s> if ( Instruction * I = simplifyNvvmIntrinsic ( & II , IC ) ) { return I ; } return None ;"
LLVM,NVPTX,2093,"Predict the next statement of this code snippet:
 <s> SimplifyAction ( SpecialCase Special , FtzRequirementTy FtzReq ) : Special ( Special ) , FtzRequirement ( FtzReq ) {"
LLVM,NVPTX,2094,"Predict the next statement of this code snippet:
 <s> SimplifyAction ( SpecialCase Special , FtzRequirementTy FtzReq ) : Special ( Special ) , FtzRequirement ( FtzReq ) {"
LLVM,NVPTX,2095,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM ) : BaseT ( TM ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( ST -> getTargetLowering ( ) ) {"
LLVM,NVPTX,2096,"Predict the next statement of this code snippet:
 <s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM ) : BaseT ( TM ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( ST -> getTargetLowering ( ) ) {"
LLVM,NVPTX,2097,"Predict the next statement of this code snippet:
 <s> SimplifyAction ( <STR_LIT> IID , FtzRequirementTy FtzReq ) : IID ( IID ) , FtzRequirement ( FtzReq ) {"
LLVM,NVPTX,2098,"Predict the next statement of this code snippet:
 <s> SimplifyAction ( <STR_LIT> IID , FtzRequirementTy FtzReq ) : IID ( IID ) , FtzRequirement ( FtzReq ) {"
LLVM,NVPTX,2099,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: FPToSI } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: FPToUI } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: SIToFP } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: UIToFP } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_MustBeOn } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_MustBeOn } ; case <STR_LIT> :"
LLVM,NVPTX,2100,"Predict the next statement of this code snippet:
 <s> return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( LT . second . SimpleTy == <STR_LIT> ) return <NUM_LIT> * LT . first ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ;"
LLVM,NVPTX,2101,"Predict the next statement of this code snippet:
 <s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,2102,"Predict the next statement of this code snippet:
 <s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,2103,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: FPToUI } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: SIToFP } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: UIToFP } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_MustBeOn } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_MustBeOn } ; case <STR_LIT> : return { Instruction :: FDiv , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FDiv , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FDiv , FTZ_MustBeOn } ; case <STR_LIT> : return { SPC_Reciprocal , FTZ_Any } ; case <STR_LIT> : return { SPC_Reciprocal , FTZ_MustBeOff } ; case <STR_LIT> : return { SPC_Reciprocal , FTZ_MustBeOn } ; default : return { } ; } } ( ) ; if ( Action . FtzRequirement != FTZ_Any ) { StringRef Attr = II -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; DenormalMode Mode = parseDenormalFPAttribute ( Attr ) ; bool FtzEnabled = Mode . Output != DenormalMode :: IEEE ; if ( FtzEnabled != ( Action . FtzRequirement == FTZ_MustBeOn ) ) return nullptr ; } if ( Action . IID ) { SmallVector < Value * , <NUM_LIT> > Args ( II -> args ( ) ) ; Type * Tys [ ] = { II -> getArgOperand ( <NUM_LIT> ) -> getType ( ) } ; return CallInst :: Create ( <STR_LIT> ( II -> getModule ( ) , * Action . IID , Tys ) , Args ) ; } if ( Action . BinaryOp ) return BinaryOperator :: Create ( * Action . BinaryOp , II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) , II -> getName ( ) ) ; if ( Action . CastOp ) return CastInst :: Create ( * Action . CastOp , II -> getArgOperand ( <NUM_LIT> ) , II -> getType ( ) , II -> getName ( ) ) ; if ( ! Action . Special ) return nullptr ;"
LLVM,NVPTX,2104,"Predict the next statement of this code snippet:
 <s> bool canHaveNonUndefGlobalInitializerInAddressSpace ( unsigned AS ) const {"
LLVM,NVPTX,2105,"Predict the next statement of this code snippet:
 <s> bool canHaveNonUndefGlobalInitializerInAddressSpace ( unsigned AS ) const { return AS != AddressSpace :: ADDRESS_SPACE_SHARED && AS != AddressSpace :: ADDRESS_SPACE_LOCAL && AS != ADDRESS_SPACE_PARAM ;"
LLVM,NVPTX,2106,"Predict the next statement of this code snippet:
 <s> ImmutablePass * llvm :: create<ISA_LIT>TargetTransformInfoPass ( const <ISA_LIT>TargetMachine * TM ) {"
LLVM,NVPTX,2107,"Predict the next statement of this code snippet:
 <s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ;"
LLVM,NVPTX,2108,"Predict the next statement of this code snippet:
 <s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {"
LLVM,NVPTX,2109,"Predict the next statement of this code snippet:
 <s> TargetTransformInfo :: getAnalysisUsage ( AU ) ;"
LLVM,NVPTX,2110,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( LT . second . SimpleTy == <STR_LIT> ) return <NUM_LIT> * LT . first ; return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ;"
LLVM,NVPTX,2111,"Predict the next statement of this code snippet:
 <s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,2112,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TTI :: hasBranchDivergence ( ) const {"
LLVM,NVPTX,2113,"Predict the next statement of this code snippet:
 <s> bool <ISA_LIT>TTI :: hasBranchDivergence ( ) const {"
LLVM,NVPTX,2114,"Predict the next statement of this code snippet:
 <s> void initializePass ( ) override { pushTTIStack ( this ) ;"
LLVM,NVPTX,2115,"Predict the next statement of this code snippet:
 <s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , TLI ( TM -> getSubtargetImpl ( ) -> getTargetLowering ( ) ) { initialize<ISA_LIT>TTIPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,2116,"Predict the next statement of this code snippet:
 <s> bool areInlineCompatible ( const Function * Caller , const Function * Callee ) const {"
LLVM,NVPTX,2117,"Predict the next statement of this code snippet:
 <s> return <NUM_LIT> ;"
LLVM,NVPTX,2118,"Predict the next statement of this code snippet:
 <s> return <NUM_LIT> ;"
LLVM,NVPTX,2119,"Predict the next statement of this code snippet:
 <s> unsigned getNumberOfRegisters ( bool Vector ) const {"
LLVM,NVPTX,2120,"Predict the next statement of this code snippet:
 <s> unsigned getNumberOfRegisters ( bool Vector ) const { return <NUM_LIT> ;"
LLVM,NVPTX,2121,"Predict the next statement of this code snippet:
 <s> return <NUM_LIT> ;"
LLVM,NVPTX,2122,"Predict the next statement of this code snippet:
 <s> BaseT :: getUnrollingPreferences ( L , UP ) ; UP . Partial = UP . Runtime = true ;"
LLVM,NVPTX,2123,"Predict the next statement of this code snippet:
 <s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { BaseT :: getUnrollingPreferences ( L , UP ) ; UP . Partial = UP . Runtime = true ;"
LLVM,NVPTX,2124,"Predict the next statement of this code snippet:
 <s> bool isLegalToVectorizeLoadChain ( unsigned ChainSizeInBytes , unsigned Alignment , unsigned AddrSpace ) const {"
LLVM,NVPTX,2125,"Predict the next statement of this code snippet:
 <s> bool isLegalToVectorizeStoreChain ( unsigned ChainSizeInBytes , unsigned Alignment , unsigned AddrSpace ) const { return isLegalToVectorizeLoadChain ( ChainSizeInBytes , Alignment , AddrSpace ) ;"
LLVM,NVPTX,2126,"Predict the next statement of this code snippet:
 <s> bool isLegalToVectorizeStoreChain ( unsigned ChainSizeInBytes , unsigned Alignment , unsigned AddrSpace ) const {"
LLVM,NVPTX,2127,"Predict the next statement of this code snippet:
 <s> static bool isNVVMAtomic ( const IntrinsicInst * II ) { switch ( II -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> :"
LLVM,NVPTX,2128,"Predict the next statement of this code snippet:
 <s> union { uint64_t x ; char a [ <NUM_LIT> ] ; } temp64 ; temp64 . x = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = strlen ( str ) ; i != e ; ++ i ) temp64 . a [ i ] = str [ e - <NUM_LIT> - i ] ; char encoded [ <NUM_LIT> ] ;"
LLVM,NVPTX,2129,"Predict the next statement of this code snippet:
 <s> assert ( retval == <NUM_LIT> && <STR_LIT> ) ; assert ( nbytes <= <NUM_LIT> && <STR_LIT> ) ; temp64 . x = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < nbytes ; ++ i ) temp64 . a [ i ] = encoded [ i ] ;"
LLVM,NVPTX,2130,"Predict the next statement of this code snippet:
 <s> std :: lock_guard < sys :: Mutex > Guard ( Lock ) ; annotationCache -> erase ( Mod ) ;"
LLVM,NVPTX,2131,"Predict the next statement of this code snippet:
 <s> if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;"
LLVM,NVPTX,2132,"Predict the next statement of this code snippet:
 <s> else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ] [ gv ] . end ( ) ) return false ;"
LLVM,NVPTX,2133,"Predict the next statement of this code snippet:
 <s> bool getMaxNReg ( const Function & F , unsigned & x ) {"
LLVM,NVPTX,2134,"Predict the next statement of this code snippet:
 <s> return findOneNVVMAnnotation ( & F , <STR_LIT> , x ) ;"
LLVM,NVPTX,2135,"Predict the next statement of this code snippet:
 <s> bool getMaxNTIDx ( const Function & F , unsigned & x ) { return findOneNVVMAnnotation ( & F , <STR_LIT> , x ) ;"
LLVM,NVPTX,2136,"Predict the next statement of this code snippet:
 <s> return findOneNVVMAnnotation ( & F , <STR_LIT> , y ) ;"
LLVM,NVPTX,2137,"Predict the next statement of this code snippet:
 <s> bool getMaxNTIDy ( const Function & F , unsigned & y ) { return findOneNVVMAnnotation ( & F , <STR_LIT> , y ) ;"
LLVM,NVPTX,2138,"Predict the next statement of this code snippet:
 <s> return findOneNVVMAnnotation ( & F , <STR_LIT> , x ) ;"
LLVM,NVPTX,2139,"Predict the next statement of this code snippet:
 <s> bool getMinCTASm ( const Function & F , unsigned & x ) { return findOneNVVMAnnotation ( & F , <STR_LIT> , x ) ;"
LLVM,NVPTX,2140,"Predict the next statement of this code snippet:
 <s> bool getReqNTIDx ( const Function & F , unsigned & x ) {"
LLVM,NVPTX,2141,"Predict the next statement of this code snippet:
 <s> bool getReqNTIDx ( const Function & F , unsigned & x ) {"
LLVM,NVPTX,2142,"Predict the next statement of this code snippet:
 <s> return findOneNVVMAnnotation ( & F , <STR_LIT> , y ) ;"
LLVM,NVPTX,2143,"Predict the next statement of this code snippet:
 <s> return findOneNVVMAnnotation ( & F , <STR_LIT> , z ) ;"
LLVM,NVPTX,2144,"Predict the next statement of this code snippet:
 <s> return findOneNVVMAnnotation ( & F , <STR_LIT> , z ) ;"
LLVM,NVPTX,2145,"Predict the next statement of this code snippet:
 <s> std :: string getSamplerName ( const Value & val ) {"
LLVM,NVPTX,2146,"Predict the next statement of this code snippet:
 <s> assert ( val . hasName ( ) && <STR_LIT> ) ;"
LLVM,NVPTX,2147,"Predict the next statement of this code snippet:
 <s> assert ( val . hasName ( ) && <STR_LIT> ) ; return std :: string ( val . getName ( ) ) ;"
LLVM,NVPTX,2148,"Predict the next statement of this code snippet:
 <s> return std :: string ( val . getName ( ) ) ;"
LLVM,NVPTX,2149,"Predict the next statement of this code snippet:
 <s> bool isImage ( const Value & val ) {"
LLVM,NVPTX,2150,"Predict the next statement of this code snippet:
 <s> return isImageReadOnly ( val ) || isImageWriteOnly ( val ) || isImageReadWrite ( val ) ;"
LLVM,NVPTX,2151,"Predict the next statement of this code snippet:
 <s> if ( findAllNVVMAnnotation ( func , <STR_LIT> , annot ) ) { if ( is_contained ( annot , arg -> getArgNo ( ) ) ) return true ; } } return false ;"
LLVM,NVPTX,2152,"Predict the next statement of this code snippet:
 <s> bool isImageReadOnly ( const Value & val ) { if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ; std :: vector < unsigned > annot ; if ( findAllNVVMAnnotation ( func , <STR_LIT> , annot ) ) { if ( is_contained ( annot , arg -> getArgNo ( ) ) ) return true ; } } return false ;"
LLVM,NVPTX,2153,"Predict the next statement of this code snippet:
 <s> const Function * func = arg -> getParent ( ) ; std :: vector < unsigned > annot ;"
LLVM,NVPTX,2154,"Predict the next statement of this code snippet:
 <s> bool isImageReadWrite ( const Value & val ) { if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ; std :: vector < unsigned > annot ; if ( findAllNVVMAnnotation ( func , <STR_LIT> , annot ) ) { if ( is_contained ( annot , arg -> getArgNo ( ) ) ) return true ; } }"
LLVM,NVPTX,2155,"Predict the next statement of this code snippet:
 <s> bool isImageWriteOnly ( const Value & val ) {"
LLVM,NVPTX,2156,"Predict the next statement of this code snippet:
 <s> return F . getCallingConv ( ) == CallingConv :: PTX_Kernel ; } return ( x == <NUM_LIT> ) ;"
LLVM,NVPTX,2157,"Predict the next statement of this code snippet:
 <s> if ( findOneNVVMAnnotation ( gv , <STR_LIT> , annot ) ) { assert ( ( annot == <NUM_LIT> ) && <STR_LIT> ) ; return true ; } }"
LLVM,NVPTX,2158,"Predict the next statement of this code snippet:
 <s> if ( const GlobalValue * gv = dyn_cast < GlobalValue > ( & val ) ) { unsigned annot ; if ( findOneNVVMAnnotation ( gv , AnnotationName , annot ) ) { assert ( ( annot == <NUM_LIT> ) && <STR_LIT> ) ; return true ; } } if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ;"
LLVM,NVPTX,2159,"Predict the next statement of this code snippet:
 <s> if ( findOneNVVMAnnotation ( gv , AnnotationName , annot ) ) { assert ( ( annot == <NUM_LIT> ) && <STR_LIT> ) ; return true ; } } if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ;"
LLVM,NVPTX,2160,"Predict the next statement of this code snippet:
 <s> bool isSurface ( const Value & val ) { if ( const GlobalValue * gv = dyn_cast < GlobalValue > ( & val ) ) { unsigned annot ;"
LLVM,NVPTX,2161,"Predict the next statement of this code snippet:
 <s> if ( findOneNVVMAnnotation ( gv , <STR_LIT> , annot ) ) { assert ( ( annot == <NUM_LIT> ) && <STR_LIT> ) ; return true ; }"
LLVM,NVPTX,2162,"Predict the next statement of this code snippet:
 <s> void llvm :: dumpBlock ( Value * v , char * blockName ) { Function * F = getParentFunction ( v ) ; if ( ! F ) return ; for ( Function :: iterator it = F -> begin ( ) , ie = F -> end ( ) ; it != ie ; ++ it ) { BasicBlock * B = & * it ; if ( strcmp ( B -> getName ( ) . data ( ) , blockName ) == <NUM_LIT> ) { B -> dump ( ) ; return ; } }"
LLVM,NVPTX,2163,"Predict the next statement of this code snippet:
 <s> NamedMDNode * NMD = m -> getNamedMetadata ( llvm :: NamedMDForAnnotations ) ; if ( ! NMD ) return ; key_val_pair_t tmp ; for ( unsigned i = <NUM_LIT> , e = NMD -> getNumOperands ( ) ; i != e ; ++ i ) { const MDNode * elem = NMD -> getOperand ( i ) ; Value * entity = elem -> getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,2164,"Predict the next statement of this code snippet:
 <s> if ( ! entity ) continue ; if ( entity != gv ) continue ; cacheAnnotationFromMD ( elem , tmp ) ; } if ( tmp . empty ( ) ) return ;"
LLVM,NVPTX,2165,"Predict the next statement of this code snippet:
 <s> for ( Function :: iterator it = F -> begin ( ) , ie = F -> end ( ) ; it != ie ; ++ it ) {"
LLVM,NVPTX,2166,"Predict the next statement of this code snippet:
 <s> for ( Function :: iterator it = F -> begin ( ) , ie = F -> end ( ) ; it != ie ; ++ it ) { BasicBlock * B = it ; if ( strcmp ( B -> getName ( ) . data ( ) , blockName ) == <NUM_LIT> ) { B -> dump ( ) ; return ; } }"
LLVM,NVPTX,2167,"Predict the next statement of this code snippet:
 <s> if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;"
LLVM,NVPTX,2168,"Predict the next statement of this code snippet:
 <s> bool llvm :: findAllNVVMAnnotation ( const GlobalValue * gv , std :: string prop , std :: vector < unsigned > & retval ) { const Module * m = gv -> getParent ( ) ; if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ] [ gv ] . end ( ) ) return false ; retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] ; return true ;"
LLVM,NVPTX,2169,"Predict the next statement of this code snippet:
 <s> const Module * m = gv -> getParent ( ) ; if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ] [ gv ] . end ( ) ) return false ;"
LLVM,NVPTX,2170,"Predict the next statement of this code snippet:
 <s> bool llvm :: getAlign ( const CallInst & I , unsigned index , unsigned & align ) { if ( MDNode * alignNode = I . getMetadata ( <STR_LIT> ) ) { for ( int i = <NUM_LIT> , n = alignNode -> getNumOperands ( ) ; i < n ; i ++ ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( alignNode -> getOperand ( i ) ) ) { unsigned v = CI -> getZExtValue ( ) ;"
LLVM,NVPTX,2171,"Predict the next statement of this code snippet:
 <s> bool llvm :: getMaxNTIDx ( const Function & F , unsigned & x ) { return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MAXNTID_X ] , x ) ) ;"
LLVM,NVPTX,2172,"Predict the next statement of this code snippet:
 <s> return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MAXNTID_X ] , x ) ) ;"
LLVM,NVPTX,2173,"Predict the next statement of this code snippet:
 <s> bool llvm :: getMaxNTIDy ( const Function & F , unsigned & y ) { return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MAXNTID_Y ] , y ) ) ;"
LLVM,NVPTX,2174,"Predict the next statement of this code snippet:
 <s> bool llvm :: getMaxNTIDz ( const Function & F , unsigned & z ) {"
LLVM,NVPTX,2175,"Predict the next statement of this code snippet:
 <s> return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MINNCTAPERSM ] , x ) ) ;"
LLVM,NVPTX,2176,"Predict the next statement of this code snippet:
 <s> if ( Instruction * I = dyn_cast < Instruction > ( v ) ) return I -> getParent ( ) ; return <NUM_LIT> ;"
LLVM,NVPTX,2177,"Predict the next statement of this code snippet:
 <s> BasicBlock * llvm :: getParentBlock ( Value * v ) { if ( BasicBlock * B = dyn_cast < BasicBlock > ( v ) ) return B ; if ( Instruction * I = dyn_cast < Instruction > ( v ) ) return I -> getParent ( ) ; return <NUM_LIT> ;"
LLVM,NVPTX,2178,"Predict the next statement of this code snippet:
 <s> if ( Function * F = dyn_cast < Function > ( v ) ) return F ; if ( Instruction * I = dyn_cast < Instruction > ( v ) ) return I -> getParent ( ) -> getParent ( ) ; if ( BasicBlock * B = dyn_cast < BasicBlock > ( v ) ) return B -> getParent ( ) ;"
LLVM,NVPTX,2179,"Predict the next statement of this code snippet:
 <s> bool llvm :: getReqNTIDx ( const Function & F , unsigned & x ) {"
LLVM,NVPTX,2180,"Predict the next statement of this code snippet:
 <s> return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_REQNTID_Y ] , y ) ) ;"
LLVM,NVPTX,2181,"Predict the next statement of this code snippet:
 <s> bool llvm :: getReqNTIDy ( const Function & F , unsigned & y ) {"
LLVM,NVPTX,2182,"Predict the next statement of this code snippet:
 <s> bool llvm :: getReqNTIDz ( const Function & F , unsigned & z ) {"
LLVM,NVPTX,2183,"Predict the next statement of this code snippet:
 <s> bool llvm :: getReqNTIDz ( const Function & F , unsigned & z ) {"
LLVM,NVPTX,2184,"Predict the next statement of this code snippet:
 <s> return llvm :: isImageReadOnly ( val ) || llvm :: isImageWriteOnly ( val ) ;"
LLVM,NVPTX,2185,"Predict the next statement of this code snippet:
 <s> bool llvm :: isImageReadOnly ( const llvm :: Value & val ) { if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ;"
LLVM,NVPTX,2186,"Predict the next statement of this code snippet:
 <s> if ( llvm :: findAllNVVMAnnotation ( func , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISWRITEONLY_IMAGE_PARAM ] , annot ) ) { if ( std :: find ( annot . begin ( ) , annot . end ( ) , arg -> getArgNo ( ) ) != annot . end ( ) ) return true ; } }"
LLVM,NVPTX,2187,"Predict the next statement of this code snippet:
 <s> if ( retval == false ) { if ( F . getCallingConv ( ) == llvm :: CallingConv :: PTX_Kernel ) return true ;"
LLVM,NVPTX,2188,"Predict the next statement of this code snippet:
 <s> assert ( ( annot == <NUM_LIT> ) && <STR_LIT> ) ; return true ; } } if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ; std :: vector < unsigned > annot ; if ( llvm :: findAllNVVMAnnotation ( func , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISSAMPLER ] , annot ) ) { if ( std :: find ( annot . begin ( ) , annot . end ( ) , arg -> getArgNo ( ) ) != annot . end ( ) ) return true ;"
LLVM,NVPTX,2189,"Predict the next statement of this code snippet:
 <s> bool llvm :: isSurface ( const llvm :: Value & val ) { if ( const GlobalValue * gv = dyn_cast < GlobalValue > ( & val ) ) { unsigned annot ; if ( llvm :: findOneNVVMAnnotation ( gv , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISSURFACE ] , annot ) ) {"
LLVM,NVPTX,2190,"Predict the next statement of this code snippet:
 <s> if ( const GlobalValue * gv = dyn_cast < GlobalValue > ( & val ) ) { unsigned annot ; if ( llvm :: findOneNVVMAnnotation ( gv , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISTEXTURE ] , annot ) ) { assert ( ( annot == <NUM_LIT> ) && <STR_LIT> ) ; return true ; } }"
LLVM,NVPTX,2191,"Predict the next statement of this code snippet:
 <s> NamedMDNode * NMD = m -> getNamedMetadata ( <STR_LIT> ) ; if ( ! NMD ) return ; key_val_pair_t tmp ; for ( unsigned i = <NUM_LIT> , e = NMD -> getNumOperands ( ) ; i != e ; ++ i ) { const MDNode * elem = NMD -> getOperand ( i ) ; GlobalValue * entity = mdconst :: dyn_extract_or_null < GlobalValue > ( elem -> getOperand ( <NUM_LIT> ) ) ; if ( ! entity ) continue ; if ( entity != gv ) continue ; cacheAnnotationFromMD ( elem , tmp ) ; } if ( tmp . empty ( ) ) return ; if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) . end ( ) ) ( * annotationCache ) [ m ] [ gv ] = std :: move ( tmp ) ; else { global_val_annot_t tmp1 ; tmp1 [ gv ] = std :: move ( tmp ) ;"
LLVM,NVPTX,2192,"Predict the next statement of this code snippet:
 <s> if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) . end ( ) ) ( * annotationCache ) [ m ] [ gv ] = std :: move ( tmp ) ; else { global_val_annot_t tmp1 ; tmp1 [ gv ] = std :: move ( tmp ) ;"
LLVM,NVPTX,2193,"Predict the next statement of this code snippet:
 <s> bool findAllNVVMAnnotation ( const GlobalValue * gv , const std :: string & prop , std :: vector < unsigned > & retval ) { MutexGuard Guard ( Lock ) ; const Module * m = gv -> getParent ( ) ; if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;"
LLVM,NVPTX,2194,"Predict the next statement of this code snippet:
 <s> if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ] [ gv ] . end ( ) ) return false ; retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ <NUM_LIT> ] ;"
LLVM,NVPTX,2195,"Predict the next statement of this code snippet:
 <s> if ( ! retval ) return false ; for ( int i = <NUM_LIT> , e = Vs . size ( ) ; i < e ; i ++ ) { unsigned v = Vs [ i ] ; if ( ( v >> <NUM_LIT> ) == index ) { align = v & <NUM_LIT> ;"
LLVM,NVPTX,2196,"Predict the next statement of this code snippet:
 <s> assert ( val . hasName ( ) && <STR_LIT> ) ;"
LLVM,NVPTX,2197,"Predict the next statement of this code snippet:
 <s> std :: string getTextureName ( const Value & val ) { assert ( val . hasName ( ) && <STR_LIT> ) ; return val . getName ( ) ;"
LLVM,NVPTX,2198,"Predict the next statement of this code snippet:
 <s> assert ( val . hasName ( ) && <STR_LIT> ) ; return val . getName ( ) ;"
LLVM,NVPTX,2199,"Predict the next statement of this code snippet:
 <s> const MDNode * elem = NMD -> getOperand ( i ) ; Value * entity = elem -> getOperand ( <NUM_LIT> ) ; if ( ! entity ) continue ; if ( entity != gv ) continue ; cacheAnnotationFromMD ( elem , tmp ) ; } if ( tmp . empty ( ) ) return ; if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) . end ( ) ) ( * annotationCache ) [ m ] [ gv ] = tmp ; else { global_val_annot_t tmp1 ; tmp1 [ gv ] = tmp ; ( * annotationCache ) [ m ] = tmp1 ;"
LLVM,NVPTX,2200,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = NMD -> getNumOperands ( ) ; i != e ; ++ i ) { const MDNode * elem = NMD -> getOperand ( i ) ; Value * entity = elem -> getOperand ( <NUM_LIT> ) ; if ( ! entity ) continue ; if ( entity != gv ) continue ; cacheAnnotationFromMD ( elem , tmp ) ; } if ( tmp . empty ( ) ) return ; if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) . end ( ) ) ( * annotationCache ) [ m ] [ gv ] = tmp ; else { global_val_annot_t tmp1 ;"
LLVM,NVPTX,2201,"Predict the next statement of this code snippet:
 <s> for ( int i = <NUM_LIT> , n = alignNode -> getNumOperands ( ) ; i < n ; i ++ ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( alignNode -> getOperand ( i ) ) ) { unsigned v = CI -> getZExtValue ( ) ; if ( ( v >> <NUM_LIT> ) == index ) { align = v & <NUM_LIT> ; return true ; } if ( ( v >> <NUM_LIT> ) > index ) { return false ; } }"
LLVM,NVPTX,2202,"Predict the next statement of this code snippet:
 <s> bool llvm :: isBarrierIntrinsic ( <STR_LIT> id ) { if ( ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) ) return true ; return false ;"
LLVM,NVPTX,2203,"Predict the next statement of this code snippet:
 <s> if ( F . getCallingConv ( ) == llvm :: CallingConv :: PTX_Kernel ) return true ; else return false ; } return ( x == <NUM_LIT> ) ;"
LLVM,NVPTX,2204,"Predict the next statement of this code snippet:
 <s> bool llvm :: isKernelFunction ( const Function & F ) { unsigned x = <NUM_LIT> ; bool retval = llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISKERNEL_FUNCTION ] , x ) ; if ( retval == false ) { if ( F . getCallingConv ( ) == llvm :: CallingConv :: PTX_Kernel ) return true ;"
LLVM,NVPTX,2205,"Predict the next statement of this code snippet:
 <s> if ( id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> ) { return true ;"
LLVM,NVPTX,2206,"Predict the next statement of this code snippet:
 <s> bool llvm :: findAllNVVMAnnotation ( const GlobalValue * gv , const std :: string & prop , std :: vector < unsigned > & retval ) { MutexGuard Guard ( Lock ) ; const Module * m = gv -> getParent ( ) ; if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;"
LLVM,NVPTX,2207,"Predict the next statement of this code snippet:
 <s> else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;"
LLVM,NVPTX,2208,"Predict the next statement of this code snippet:
 <s> MutexGuard Guard ( Lock ) ; const Module * m = gv -> getParent ( ) ; if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ] [ gv ] . end ( ) ) return false ; retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ <NUM_LIT> ] ;"
LLVM,NVPTX,2209,"Predict the next statement of this code snippet:
 <s> if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;"
LLVM,NVPTX,2210,"Predict the next statement of this code snippet:
 <s> std :: vector < unsigned > annot ; if ( llvm :: findAllNVVMAnnotation ( func , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISREADONLY_IMAGE_PARAM ] , annot ) ) { if ( is_contained ( annot , arg -> getArgNo ( ) ) ) return true ; } } return false ;"
LLVM,NVPTX,2211,"Predict the next statement of this code snippet:
 <s> const Function * func = arg -> getParent ( ) ; std :: vector < unsigned > annot ; if ( llvm :: findAllNVVMAnnotation ( func , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISREADWRITE_IMAGE_PARAM ] , annot ) ) { if ( is_contained ( annot , arg -> getArgNo ( ) ) ) return true ; }"
LLVM,NVPTX,2212,"Predict the next statement of this code snippet:
 <s> const Function * func = arg -> getParent ( ) ; std :: vector < unsigned > annot ;"
LLVM,NVPTX,2213,"Predict the next statement of this code snippet:
 <s> unsigned annot ; if ( llvm :: findOneNVVMAnnotation ( gv , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISSAMPLER ] , annot ) ) { assert ( ( annot == <NUM_LIT> ) && <STR_LIT> ) ; return true ; } } if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ;"
LLVM,NVPTX,2214,"Predict the next statement of this code snippet:
 <s> if ( ! NMD ) return ; key_val_pair_t tmp ; for ( unsigned i = <NUM_LIT> , e = NMD -> getNumOperands ( ) ; i != e ; ++ i ) { const MDNode * elem = NMD -> getOperand ( i ) ; Value * entity = elem -> getOperand ( <NUM_LIT> ) ; if ( ! entity ) continue ;"
LLVM,NVPTX,2215,"Predict the next statement of this code snippet:
 <s> Value * entity = elem -> getOperand ( <NUM_LIT> ) ; if ( ! entity ) continue ; if ( entity != gv ) continue ; cacheAnnotationFromMD ( elem , tmp ) ; } if ( tmp . empty ( ) ) return ; if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) . end ( ) ) ( * annotationCache ) [ m ] [ gv ] = std :: move ( tmp ) ; else { global_val_annot_t tmp1 ;"
LLVM,NVPTX,2216,"Predict the next statement of this code snippet:
 <s> bool llvm :: getAlign ( const CallInst & I , unsigned index , unsigned & align ) { if ( MDNode * alignNode = I . getMDNode ( <STR_LIT> ) ) {"
LLVM,NVPTX,2217,"Predict the next statement of this code snippet:
 <s> bool llvm :: getAlign ( const CallInst & I , unsigned index , unsigned & align ) { if ( MDNode * alignNode = I . getMDNode ( <STR_LIT> ) ) { for ( int i = <NUM_LIT> , n = alignNode -> getNumOperands ( ) ; i < n ; i ++ ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( alignNode -> getOperand ( i ) ) ) { unsigned v = CI -> getZExtValue ( ) ; if ( ( v >> <NUM_LIT> ) == index ) {"
LLVM,NVPTX,2218,"Predict the next statement of this code snippet:
 <s> assert ( ( md -> getNumOperands ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = md -> getNumOperands ( ) ; i != e ; i += <NUM_LIT> ) {"
LLVM,NVPTX,2219,"Predict the next statement of this code snippet:
 <s> assert ( prop && <STR_LIT> ) ; ConstantInt * Val = dyn_cast < ConstantInt > ( md -> getOperand ( i + <NUM_LIT> ) ) ; assert ( Val && <STR_LIT> ) ; std :: string keyname = prop -> getString ( ) . str ( ) ; if ( retval . find ( keyname ) != retval . end ( ) ) retval [ keyname ] . push_back ( Val -> getZExtValue ( ) ) ; else {"
LLVM,NVPTX,2220,"Predict the next statement of this code snippet:
 <s> continue ; } } else if ( const GEPOperator * GEP = dyn_cast < GEPOperator > ( V ) ) { V = GEP -> getPointerOperand ( ) -> stripPointerCasts ( ) ; continue ; } else if ( const PHINode * PN = dyn_cast < PHINode > ( V ) ) { if ( V != V2 && processed . find ( V ) != processed . end ( ) ) return NULL ; processed . insert ( PN ) ; const Value * common = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != PN -> getNumIncomingValues ( ) ; ++ i ) { const Value * pv = PN -> getIncomingValue ( i ) ; const Value * base = skipPointerTransfer ( pv , processed ) ; if ( base ) { if ( common == <NUM_LIT> ) common = base ; else if ( common != base ) return PN ; } } if ( common == <NUM_LIT> ) return PN ; V = common ; } break ; } return V ;"
LLVM,NVPTX,2221,"Predict the next statement of this code snippet:
 <s> } else if ( const GEPOperator * GEP = dyn_cast < GEPOperator > ( V ) ) { V = GEP -> getPointerOperand ( ) -> stripPointerCasts ( ) ; continue ; } else if ( const PHINode * PN = dyn_cast < PHINode > ( V ) ) { if ( V != V2 && processed . find ( V ) != processed . end ( ) ) return NULL ; processed . insert ( PN ) ; const Value * common = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != PN -> getNumIncomingValues ( ) ; ++ i ) { const Value * pv = PN -> getIncomingValue ( i ) ; const Value * base = skipPointerTransfer ( pv , processed ) ; if ( base ) { if ( common == <NUM_LIT> ) common = base ; else if ( common != base ) return PN ; } } if ( common == <NUM_LIT> ) return PN ;"
LLVM,NVPTX,2222,"Predict the next statement of this code snippet:
 <s> if ( tmp . empty ( ) ) return ; if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) . end ( ) ) ( * annotationCache ) [ m ] [ gv ] = std :: move ( tmp ) ; else { global_val_annot_t tmp1 ; tmp1 [ gv ] = std :: move ( tmp ) ;"
LLVM,NVPTX,2223,"Predict the next statement of this code snippet:
 <s> void llvm :: dumpBlock ( Value * v , char * blockName ) { Function * F = getParentFunction ( v ) ;"
LLVM,NVPTX,2224,"Predict the next statement of this code snippet:
 <s> Function * F = getParentFunction ( v ) ; if ( ! F ) return ;"
LLVM,NVPTX,2225,"Predict the next statement of this code snippet:
 <s> Instruction * I = getInst ( base , instName ) ;"
LLVM,NVPTX,2226,"Predict the next statement of this code snippet:
 <s> void llvm :: dumpInst ( Value * base , char * instName ) { Instruction * I = getInst ( base , instName ) ;"
LLVM,NVPTX,2227,"Predict the next statement of this code snippet:
 <s> void llvm :: dumpInstRec ( Value * v ) { std :: set < Instruction * > visited ; dumpInstRec ( v , & visited ) ;"
LLVM,NVPTX,2228,"Predict the next statement of this code snippet:
 <s> dumpInstRec ( v , & visited ) ;"
LLVM,NVPTX,2229,"Predict the next statement of this code snippet:
 <s> I -> getParent ( ) -> dump ( ) ; return ; } if ( BasicBlock * B = dyn_cast < BasicBlock > ( v ) ) { B -> getParent ( ) -> dump ( ) ; return ; } if ( Function * F = dyn_cast < Function > ( v ) ) { F -> getParent ( ) -> dump ( ) ; return ;"
LLVM,NVPTX,2230,"Predict the next statement of this code snippet:
 <s> if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;"
LLVM,NVPTX,2231,"Predict the next statement of this code snippet:
 <s> else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ] [ gv ] . end ( ) ) return false ; retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ <NUM_LIT> ] ;"
LLVM,NVPTX,2232,"Predict the next statement of this code snippet:
 <s> bool llvm :: findOneNVVMAnnotation ( const GlobalValue * gv , std :: string prop , unsigned & retval ) { MutexGuard Guard ( Lock ) ; const Module * m = gv -> getParent ( ) ; if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ] [ gv ] . end ( ) ) return false ; retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ <NUM_LIT> ] ; return true ;"
LLVM,NVPTX,2233,"Predict the next statement of this code snippet:
 <s> if ( const ConstantInt * CI = mdconst :: dyn_extract < ConstantInt > ( alignNode -> getOperand ( i ) ) ) { unsigned v = CI -> getZExtValue ( ) ; if ( ( v >> <NUM_LIT> ) == index ) { align = v & <NUM_LIT> ; return true ; } if ( ( v >> <NUM_LIT> ) > index ) { return false ;"
LLVM,NVPTX,2234,"Predict the next statement of this code snippet:
 <s> for ( inst_iterator it = inst_begin ( F ) , ie = inst_end ( F ) ; it != ie ; ++ it ) { Instruction * I = & * it ;"
LLVM,NVPTX,2235,"Predict the next statement of this code snippet:
 <s> return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MAXNTID_X ] , x ) ) ;"
LLVM,NVPTX,2236,"Predict the next statement of this code snippet:
 <s> return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MAXNTID_Y ] , y ) ) ;"
LLVM,NVPTX,2237,"Predict the next statement of this code snippet:
 <s> bool llvm :: getMaxNTIDy ( const Function & F , unsigned & y ) {"
LLVM,NVPTX,2238,"Predict the next statement of this code snippet:
 <s> bool llvm :: getMaxNTIDz ( const Function & F , unsigned & z ) {"
LLVM,NVPTX,2239,"Predict the next statement of this code snippet:
 <s> bool llvm :: getMaxNTIDz ( const Function & F , unsigned & z ) { return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MAXNTID_Z ] , z ) ) ;"
LLVM,NVPTX,2240,"Predict the next statement of this code snippet:
 <s> bool llvm :: getMinCTASm ( const Function & F , unsigned & x ) { return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MINNCTAPERSM ] , x ) ) ;"
LLVM,NVPTX,2241,"Predict the next statement of this code snippet:
 <s> bool llvm :: getMinCTASm ( const Function & F , unsigned & x ) {"
LLVM,NVPTX,2242,"Predict the next statement of this code snippet:
 <s> if ( BasicBlock * B = dyn_cast < BasicBlock > ( v ) ) return B ;"
LLVM,NVPTX,2243,"Predict the next statement of this code snippet:
 <s> if ( BasicBlock * B = dyn_cast < BasicBlock > ( v ) ) return B -> getParent ( ) ;"
LLVM,NVPTX,2244,"Predict the next statement of this code snippet:
 <s> bool llvm :: getReqNTIDx ( const Function & F , unsigned & x ) {"
LLVM,NVPTX,2245,"Predict the next statement of this code snippet:
 <s> bool llvm :: getReqNTIDz ( const Function & F , unsigned & z ) { return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_REQNTID_Z ] , z ) ) ;"
LLVM,NVPTX,2246,"Predict the next statement of this code snippet:
 <s> std :: string llvm :: getSurfaceName ( const llvm :: Value & val ) {"
LLVM,NVPTX,2247,"Predict the next statement of this code snippet:
 <s> std :: string llvm :: getSurfaceName ( const llvm :: Value & val ) {"
LLVM,NVPTX,2248,"Predict the next statement of this code snippet:
 <s> return ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) ;"
LLVM,NVPTX,2249,"Predict the next statement of this code snippet:
 <s> if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ; std :: vector < unsigned > annot ; if ( llvm :: findAllNVVMAnnotation ( func , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISREADONLY_IMAGE_PARAM ] , annot ) ) { if ( std :: find ( annot . begin ( ) , annot . end ( ) , arg -> getArgNo ( ) ) != annot . end ( ) ) return true ;"
LLVM,NVPTX,2250,"Predict the next statement of this code snippet:
 <s> std :: vector < unsigned > annot ; if ( llvm :: findAllNVVMAnnotation ( func , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISREADWRITE_IMAGE_PARAM ] , annot ) ) {"
LLVM,NVPTX,2251,"Predict the next statement of this code snippet:
 <s> if ( std :: find ( annot . begin ( ) , annot . end ( ) , arg -> getArgNo ( ) ) != annot . end ( ) ) return true ; } } return false ;"
LLVM,NVPTX,2252,"Predict the next statement of this code snippet:
 <s> unsigned x = <NUM_LIT> ; bool retval = llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISKERNEL_FUNCTION ] , x ) ; if ( ! retval ) { return F . getCallingConv ( ) == llvm :: CallingConv :: PTX_Kernel ; } return ( x == <NUM_LIT> ) ;"
LLVM,NVPTX,2253,"Predict the next statement of this code snippet:
 <s> unsigned annot ; if ( llvm :: findOneNVVMAnnotation ( gv , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MANAGED ] , annot ) ) { assert ( ( annot == <NUM_LIT> ) && <STR_LIT> ) ;"
LLVM,NVPTX,2254,"Predict the next statement of this code snippet:
 <s> return id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> ;"
LLVM,NVPTX,2255,"Predict the next statement of this code snippet:
 <s> std :: vector < unsigned > annot ; if ( llvm :: findAllNVVMAnnotation ( func , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISSAMPLER ] , annot ) ) { if ( std :: find ( annot . begin ( ) , annot . end ( ) , arg -> getArgNo ( ) ) != annot . end ( ) ) return true ; } }"
LLVM,NVPTX,2256,"Predict the next statement of this code snippet:
 <s> if ( llvm :: findOneNVVMAnnotation ( gv , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISTEXTURE ] , annot ) ) { assert ( ( annot == <NUM_LIT> ) && <STR_LIT> ) ; return true ; }"
LLVM,NVPTX,2257,"Predict the next statement of this code snippet:
 <s> Result . push_back ( A ) ;"
LLVM,NVPTX,2258,"Predict the next statement of this code snippet:
 <s> V = GEP -> getPointerOperand ( ) -> stripPointerCasts ( ) ; continue ; } else if ( const PHINode * PN = dyn_cast < PHINode > ( V ) ) { if ( V != V2 && processed . find ( V ) != processed . end ( ) ) return nullptr ; processed . insert ( PN ) ; const Value * common = nullptr ; for ( unsigned i = <NUM_LIT> ; i != PN -> getNumIncomingValues ( ) ; ++ i ) { const Value * pv = PN -> getIncomingValue ( i ) ; const Value * base = skipPointerTransfer ( pv , processed ) ; if ( base ) { if ( ! common ) common = base ; else if ( common != base ) return PN ; } } if ( ! common ) return PN ; V = common ; } break ; }"
LLVM,NVPTX,2259,"Predict the next statement of this code snippet:
 <s> temp64 . x = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = strlen ( str ) ; i != e ; ++ i ) temp64 . a [ i ] = str [ e - <NUM_LIT> - i ] ; char encoded [ <NUM_LIT> ] ; int nbytes ; int retval = encode_leb128 ( temp64 . x , & nbytes , encoded , <NUM_LIT> ) ; ( void ) retval ;"
LLVM,NVPTX,2260,"Predict the next statement of this code snippet:
 <s> bool isParamLoad ( const MachineInstr * MI ) { if ( ( MI -> getOpcode ( ) != <STR_LIT> ) && ( MI -> getOpcode ( ) != <STR_LIT> ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) == false ) return false ;"
LLVM,NVPTX,2261,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;"
LLVM,NVPTX,2262,"Predict the next statement of this code snippet:
 <s> initializeNVVMIntrRangePass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,2263,"Predict the next statement of this code snippet:
 <s> NVVMIntrRangePass :: NVVMIntrRangePass ( ) : NVVMIntrRangePass ( NVVMIntrRangeSM ) {"
LLVM,NVPTX,2264,"Predict the next statement of this code snippet:
 <s> NVVMIntrRangePass :: NVVMIntrRangePass ( ) : NVVMIntrRangePass ( NVVMIntrRangeSM ) {"
LLVM,NVPTX,2265,"Predict the next statement of this code snippet:
 <s> return runNVVMIntrRange ( F , SmVersion ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ;"
LLVM,NVPTX,2266,"Predict the next statement of this code snippet:
 <s> return runNVVMIntrRange ( F , SmVersion ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ;"
LLVM,NVPTX,2267,"Predict the next statement of this code snippet:
 <s> Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> , Call ) ; break ; default : break ; } } } return Changed ;"
LLVM,NVPTX,2268,"Predict the next statement of this code snippet:
 <s> bool NVVMIntrRange :: runOnFunction ( Function & F ) {"
LLVM,NVPTX,2269,"Predict the next statement of this code snippet:
 <s> bool NVVMIntrRange :: runOnFunction ( Function & F ) {"
LLVM,NVPTX,2270,"Predict the next statement of this code snippet:
 <s> static bool addRangeMetadata ( uint64_t Low , uint64_t High , CallInst * C ) { LLVMContext & Context = C -> getParent ( ) -> getContext ( ) ; IntegerType * Int32Ty = Type :: getInt32Ty ( Context ) ;"
LLVM,NVPTX,2271,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . x , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . y , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . y + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x , Call ) ; break ;"
LLVM,NVPTX,2272,"Predict the next statement of this code snippet:
 <s> switch ( Callee -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . x , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . y , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . y + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> :"
LLVM,NVPTX,2273,"Predict the next statement of this code snippet:
 <s> Metadata * LowAndHigh [ ] = { ConstantAsMetadata :: get ( ConstantInt :: get ( Int32Ty , Low ) ) , ConstantAsMetadata :: get ( ConstantInt :: get ( Int32Ty , High ) ) } ; C -> setMetadata ( LLVMContext :: MD_range , MDNode :: get ( Context , LowAndHigh ) ) ;"
LLVM,NVPTX,2274,"Predict the next statement of this code snippet:
 <s> MaxBlockSize . y = <NUM_LIT> ; MaxBlockSize . z = <NUM_LIT> ; MaxGridSize . x = SmVersion >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; MaxGridSize . y = <NUM_LIT> ; MaxGridSize . z = <NUM_LIT> ; initializeNVVMIntrRangePass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,2275,"Predict the next statement of this code snippet:
 <s> Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> , Call ) ;"
LLVM,NVPTX,2276,"Predict the next statement of this code snippet:
 <s> case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> , Call ) ;"
LLVM,NVPTX,2277,"Predict the next statement of this code snippet:
 <s> NVVMReflect ( ) : FunctionPass ( ID ) {"
LLVM,NVPTX,2278,"Predict the next statement of this code snippet:
 <s> bool NVVMReflect :: runOnFunction ( Function & F ) { if ( ! NVVMReflectEnabled ) return false ; if ( F . getName ( ) == NVVM_REFLECT_FUNCTION ) { assert ( F . isDeclaration ( ) && <STR_LIT> ) ; assert ( F . getReturnType ( ) -> isIntegerTy ( ) && <STR_LIT> ) ; return false ; } SmallVector < Instruction * , <NUM_LIT> > ToRemove ; for ( Instruction & I : instructions ( F ) ) { CallInst * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; Function * Callee = Call -> getCalledFunction ( ) ; if ( ! Callee || ( Callee -> getName ( ) != NVVM_REFLECT_FUNCTION && Callee -> getIntrinsicID ( ) != <STR_LIT> ) ) continue ; assert ( Call -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; const Value * Str = Call -> getArgOperand ( <NUM_LIT> ) ; if ( const CallInst * ConvCall = dyn_cast < CallInst > ( Str ) ) { Str = ConvCall -> getArgOperand ( <NUM_LIT> ) ; } assert ( isa < ConstantExpr > ( Str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Value * Operand = cast < Constant > ( Sym ) -> getOperand ( <NUM_LIT> ) ; if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Operand ) ) { assert ( GV -> hasInitializer ( ) && <STR_LIT> ) ; const Constant * Initializer = GV -> getInitializer ( ) ; Operand = Initializer ; } assert ( isa < ConstantDataSequential > ( Operand ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( Operand ) -> isCString ( ) && <STR_LIT> ) ; StringRef ReflectArg = cast < ConstantDataSequential > ( Operand ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( ReflectArg == <STR_LIT> ) { if ( auto * Flag = mdconst :: extract_or_null < ConstantInt > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) ReflectVal = Flag -> getSExtValue ( ) ;"
LLVM,NVPTX,2279,"Predict the next statement of this code snippet:
 <s> CallInst * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; Function * Callee = Call -> getCalledFunction ( ) ; if ( ! Callee || ( Callee -> getName ( ) != NVVM_REFLECT_FUNCTION && Callee -> getIntrinsicID ( ) != <STR_LIT> ) ) continue ; assert ( Call -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; const Value * Str = Call -> getArgOperand ( <NUM_LIT> ) ; if ( const CallInst * ConvCall = dyn_cast < CallInst > ( Str ) ) { Str = ConvCall -> getArgOperand ( <NUM_LIT> ) ; } assert ( isa < ConstantExpr > ( Str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ;"
LLVM,NVPTX,2280,"Predict the next statement of this code snippet:
 <s> NVVMReflect ( const StringMap < int > & Mapping ) : ModulePass ( ID ) , ReflectFunction ( nullptr ) {"
LLVM,NVPTX,2281,"Predict the next statement of this code snippet:
 <s> assert ( ReflectFunction -> isDeclaration ( ) && <STR_LIT> ) ; assert ( ReflectFunction -> getReturnType ( ) -> isIntegerTy ( ) && <STR_LIT> ) ; std :: vector < Instruction * > ToRemove ; for ( User * U : ReflectFunction -> users ( ) ) { assert ( isa < CallInst > ( U ) && <STR_LIT> ) ; CallInst * Reflect = cast < CallInst > ( U ) ; assert ( ( Reflect -> getNumOperands ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const Value * conv = Reflect -> getArgOperand ( <NUM_LIT> ) ; assert ( isa < CallInst > ( conv ) && <STR_LIT> ) ; const CallInst * ConvCall = cast < CallInst > ( conv ) ; const Value * str = ConvCall -> getArgOperand ( <NUM_LIT> ) ; assert ( isa < ConstantExpr > ( str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ;"
LLVM,NVPTX,2282,"Predict the next statement of this code snippet:
 <s> return new NVVMReflect ( SmVersion ) ;"
LLVM,NVPTX,2283,"Predict the next statement of this code snippet:
 <s> return new NVVMReflect ( SmVersion ) ;"
LLVM,NVPTX,2284,"Predict the next statement of this code snippet:
 <s> explicit NVVMReflect ( unsigned int Sm ) : FunctionPass ( ID ) , SmVersion ( Sm ) { initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,2285,"Predict the next statement of this code snippet:
 <s> NVVMReflectPass :: NVVMReflectPass ( ) : NVVMReflectPass ( <NUM_LIT> ) {"
LLVM,NVPTX,2286,"Predict the next statement of this code snippet:
 <s> NVVMReflectPass :: NVVMReflectPass ( ) : NVVMReflectPass ( <NUM_LIT> ) {"
LLVM,NVPTX,2287,"Predict the next statement of this code snippet:
 <s> bool NVVMReflect :: runOnFunction ( Function & F ) {"
LLVM,NVPTX,2288,"Predict the next statement of this code snippet:
 <s> } assert ( isa < ConstantExpr > ( Str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Value * Operand = cast < Constant > ( Sym ) -> getOperand ( <NUM_LIT> ) ; if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Operand ) ) { assert ( GV -> hasInitializer ( ) && <STR_LIT> ) ; const Constant * Initializer = GV -> getInitializer ( ) ; Operand = Initializer ; } assert ( isa < ConstantDataSequential > ( Operand ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( Operand ) -> isCString ( ) && <STR_LIT> ) ; std :: string ReflectArg = cast < ConstantDataSequential > ( Operand ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( VarMap . find ( ReflectArg ) != VarMap . end ( ) ) {"
LLVM,NVPTX,2289,"Predict the next statement of this code snippet:
 <s> const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Value * Operand = cast < Constant > ( Sym ) -> getOperand ( <NUM_LIT> ) ; if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Operand ) ) { assert ( GV -> hasInitializer ( ) && <STR_LIT> ) ; const Constant * Initializer = GV -> getInitializer ( ) ; Operand = Initializer ; } assert ( isa < ConstantDataSequential > ( Operand ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( Operand ) -> isCString ( ) && <STR_LIT> ) ; std :: string ReflectArg = cast < ConstantDataSequential > ( Operand ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( VarMap . find ( ReflectArg ) != VarMap . end ( ) ) {"
LLVM,NVPTX,2290,"Predict the next statement of this code snippet:
 <s> const Value * Str = Call -> getArgOperand ( <NUM_LIT> ) ; if ( const CallInst * ConvCall = dyn_cast < CallInst > ( Str ) ) { Str = ConvCall -> getArgOperand ( <NUM_LIT> ) ; } assert ( isa < ConstantExpr > ( Str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Value * Operand = cast < Constant > ( Sym ) -> getOperand ( <NUM_LIT> ) ; if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Operand ) ) { assert ( GV -> hasInitializer ( ) && <STR_LIT> ) ; const Constant * Initializer = GV -> getInitializer ( ) ; Operand = Initializer ; } assert ( isa < ConstantDataSequential > ( Operand ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( Operand ) -> isCString ( ) && <STR_LIT> ) ; StringRef ReflectArg = cast < ConstantDataSequential > ( Operand ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ;"
LLVM,NVPTX,2291,"Predict the next statement of this code snippet:
 <s> assert ( isa < ConstantDataSequential > ( Operand ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( Operand ) -> isCString ( ) && <STR_LIT> ) ; StringRef ReflectArg = cast < ConstantDataSequential > ( Operand ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( ReflectArg == <STR_LIT> ) { if ( auto * Flag = mdconst :: extract_or_null < ConstantInt > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) ReflectVal = Flag -> getSExtValue ( ) ; } Call -> replaceAllUsesWith ( ConstantInt :: get ( Call -> getType ( ) , ReflectVal ) ) ; ToRemove . push_back ( Call ) ; }"
LLVM,NVPTX,2292,"Predict the next statement of this code snippet:
 <s> assert ( Call -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; const Value * Str = Call -> getArgOperand ( <NUM_LIT> ) ; if ( const CallInst * ConvCall = dyn_cast < CallInst > ( Str ) ) { Str = ConvCall -> getArgOperand ( <NUM_LIT> ) ; } assert ( isa < ConstantExpr > ( Str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Value * Operand = cast < Constant > ( Sym ) -> getOperand ( <NUM_LIT> ) ; if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Operand ) ) { assert ( GV -> hasInitializer ( ) && <STR_LIT> ) ; const Constant * Initializer = GV -> getInitializer ( ) ; Operand = Initializer ; } assert ( isa < ConstantDataSequential > ( Operand ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( Operand ) -> isCString ( ) && <STR_LIT> ) ; StringRef ReflectArg = cast < ConstantDataSequential > ( Operand ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( ReflectArg == <STR_LIT> ) { if ( auto * Flag = mdconst :: extract_or_null < ConstantInt > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) ReflectVal = Flag -> getSExtValue ( ) ; } else if ( ReflectArg == <STR_LIT> ) { ReflectVal = SmVersion * <NUM_LIT> ; } Call -> replaceAllUsesWith ( ConstantInt :: get ( Call -> getType ( ) , ReflectVal ) ) ;"
LLVM,NVPTX,2293,"Predict the next statement of this code snippet:
 <s> NVVMReflect ( const StringMap < int > & Mapping ) : ModulePass ( ID ) , ReflectFunction ( <NUM_LIT> ) { initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,2294,"Predict the next statement of this code snippet:
 <s> assert ( ReflectFunction -> getReturnType ( ) -> isIntegerTy ( ) && <STR_LIT> ) ; std :: vector < Instruction * > ToRemove ; for ( Value :: use_iterator I = ReflectFunction -> use_begin ( ) , E = ReflectFunction -> use_end ( ) ; I != E ; ++ I ) { assert ( isa < CallInst > ( * I ) && <STR_LIT> ) ; CallInst * Reflect = cast < CallInst > ( * I ) ; assert ( ( Reflect -> getNumOperands ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const Value * conv = Reflect -> getArgOperand ( <NUM_LIT> ) ; assert ( isa < CallInst > ( conv ) && <STR_LIT> ) ; const CallInst * ConvCall = cast < CallInst > ( conv ) ; const Value * str = ConvCall -> getArgOperand ( <NUM_LIT> ) ; assert ( isa < ConstantExpr > ( str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Constant * SymStr = cast < Constant > ( Sym ) ; assert ( isa < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) -> isCString ( ) && <STR_LIT> ) ; std :: string ReflectArg = cast < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) -> getAsString ( ) ;"
LLVM,NVPTX,2295,"Predict the next statement of this code snippet:
 <s> } SmallVector < Instruction * , <NUM_LIT> > ToRemove ; for ( Instruction & I : instructions ( F ) ) { CallInst * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; Function * Callee = Call -> getCalledFunction ( ) ; if ( ! Callee || ( Callee -> getName ( ) != NVVM_REFLECT_FUNCTION && Callee -> getIntrinsicID ( ) != <STR_LIT> ) ) continue ; assert ( Call -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; const Value * Str = Call -> getArgOperand ( <NUM_LIT> ) ; if ( const CallInst * ConvCall = dyn_cast < CallInst > ( Str ) ) { Str = ConvCall -> getArgOperand ( <NUM_LIT> ) ; } assert ( isa < ConstantExpr > ( Str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ;"
LLVM,NVPTX,2296,"Predict the next statement of this code snippet:
 <s> return new NVVMReflect ( Mapping ) ;"
LLVM,NVPTX,2297,"Predict the next statement of this code snippet:
 <s> initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ;"
LLVM,NVPTX,2298,"Predict the next statement of this code snippet:
 <s> if ( F . getName ( ) == NVVM_REFLECT_FUNCTION ) { assert ( F . isDeclaration ( ) && <STR_LIT> ) ; assert ( F . getReturnType ( ) -> isIntegerTy ( ) && <STR_LIT> ) ; return false ; } SmallVector < Instruction * , <NUM_LIT> > ToRemove ; for ( Instruction & I : instructions ( F ) ) { CallInst * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; Function * Callee = Call -> getCalledFunction ( ) ; if ( ! Callee || ( Callee -> getName ( ) != NVVM_REFLECT_FUNCTION && Callee -> getIntrinsicID ( ) != <STR_LIT> ) ) continue ; assert ( Call -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; const Value * Str = Call -> getArgOperand ( <NUM_LIT> ) ; if ( const CallInst * ConvCall = dyn_cast < CallInst > ( Str ) ) { Str = ConvCall -> getArgOperand ( <NUM_LIT> ) ; } assert ( isa < ConstantExpr > ( Str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Value * Operand = cast < Constant > ( Sym ) -> getOperand ( <NUM_LIT> ) ; if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Operand ) ) { assert ( GV -> hasInitializer ( ) && <STR_LIT> ) ; const Constant * Initializer = GV -> getInitializer ( ) ; Operand = Initializer ; }"
LLVM,NVPTX,2299,"Predict the next statement of this code snippet:
 <s> StringRef ( ReflectList [ i ] ) . split ( NameValList , ',' ) ; for ( unsigned j = <NUM_LIT> , ej = NameValList . size ( ) ; j != ej ; ++ j ) { SmallVector < StringRef , <NUM_LIT> > NameValPair ; NameValList [ j ] . split ( NameValPair , '=' ) ; assert ( NameValPair . size ( ) == <NUM_LIT> && <STR_LIT> ) ; std :: stringstream ValStream ( NameValPair [ <NUM_LIT> ] ) ; int Val ; ValStream >> Val ; assert ( ( ! ( ValStream . fail ( ) ) ) && <STR_LIT> ) ; VarMap [ NameValPair [ <NUM_LIT> ] ] = Val ;"
LLVM,NVPTX,2300,"Predict the next statement of this code snippet:
 <s> assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Constant * SymStr = cast < Constant > ( Sym ) ; assert ( isa < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) -> isCString ( ) && <STR_LIT> ) ; std :: string ReflectArg = cast < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( VarMap . find ( ReflectArg ) != VarMap . end ( ) ) { ReflectVal = VarMap [ ReflectArg ] ; } Reflect -> replaceAllUsesWith ( ConstantInt :: get ( Reflect -> getType ( ) , ReflectVal ) ) ; ToRemove . push_back ( Reflect ) ; } if ( ToRemove . size ( ) == <NUM_LIT> ) return false ;"
LLVM,NVPTX,2301,"Predict the next statement of this code snippet:
 <s> const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Constant * SymStr = cast < Constant > ( Sym ) ; assert ( isa < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) -> isCString ( ) && <STR_LIT> ) ; std :: string ReflectArg = cast < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( VarMap . find ( ReflectArg ) != VarMap . end ( ) ) { ReflectVal = VarMap [ ReflectArg ] ; } Reflect -> replaceAllUsesWith ( ConstantInt :: get ( Reflect -> getType ( ) , ReflectVal ) ) ; ToRemove . push_back ( Reflect ) ; }"
LLVM,NVPTX,2302,"Predict the next statement of this code snippet:
 <s> assert ( cast < ConstantDataSequential > ( Operand ) -> isCString ( ) && <STR_LIT> ) ; StringRef ReflectArg = cast < ConstantDataSequential > ( Operand ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( ReflectArg == <STR_LIT> ) { if ( auto * Flag = mdconst :: extract_or_null < ConstantInt > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) ReflectVal = Flag -> getSExtValue ( ) ; } else if ( ReflectArg == <STR_LIT> ) { ReflectVal = SmVersion * <NUM_LIT> ; } Call -> replaceAllUsesWith ( ConstantInt :: get ( Call -> getType ( ) , ReflectVal ) ) ; ToRemove . push_back ( Call ) ;"
LLVM,NVPTX,2303,"Predict the next statement of this code snippet:
 <s> return new NVVMReflect ( Mapping ) ;"
LLVM,NVPTX,2304,"Predict the next statement of this code snippet:
 <s> AU . setPreservesAll ( ) ;"
LLVM,NVPTX,2305,"Predict the next statement of this code snippet:
 <s> assert ( isa < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) -> isCString ( ) && <STR_LIT> ) ; std :: string ReflectArg = cast < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( VarMap . find ( ReflectArg ) != VarMap . end ( ) ) { ReflectVal = VarMap [ ReflectArg ] ; } Reflect -> replaceAllUsesWith ( ConstantInt :: get ( Reflect -> getType ( ) , ReflectVal ) ) ; ToRemove . push_back ( Reflect ) ; } if ( ToRemove . size ( ) == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = ToRemove . size ( ) ; i != e ; ++ i ) ToRemove [ i ] -> eraseFromParent ( ) ; return true ;"
LLVM,NVPTX,2306,"Predict the next statement of this code snippet:
 <s> const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Constant * SymStr = cast < Constant > ( Sym ) ; assert ( isa < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) -> isCString ( ) && <STR_LIT> ) ; std :: string ReflectArg = cast < ConstantDataSequential > ( SymStr -> getOperand ( <NUM_LIT> ) ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( VarMap . find ( ReflectArg ) != VarMap . end ( ) ) { ReflectVal = VarMap [ ReflectArg ] ; } Reflect -> replaceAllUsesWith ( ConstantInt :: get ( Reflect -> getType ( ) , ReflectVal ) ) ; ToRemove . push_back ( Reflect ) ; } if ( ToRemove . size ( ) == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = ToRemove . size ( ) ; i != e ; ++ i ) ToRemove [ i ] -> eraseFromParent ( ) ; return true ;"
LLVM,NVPTX,2307,"Predict the next statement of this code snippet:
 <s> for ( StringMap < int > :: const_iterator I = Mapping . begin ( ) , E = Mapping . end ( ) ;"
LLVM,NVPTX,2308,"Predict the next statement of this code snippet:
 <s> std :: string Name ; Type * Tys [ <NUM_LIT> ] ; Type * I8Ty = Type :: getInt8Ty ( M . getContext ( ) ) ; Function * ReflectFunction ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Tys [ <NUM_LIT> ] = PointerType :: get ( I8Ty , i ) ; Name = <STR_LIT> ( <STR_LIT> , Tys ) ; ReflectFunction = M . getFunction ( Name ) ; if ( ReflectFunction != <NUM_LIT> ) { Res |= handleFunction ( ReflectFunction ) ; }"
LLVM,NVPTX,2309,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Tys [ <NUM_LIT> ] = PointerType :: get ( I8Ty , i ) ; Name = <STR_LIT> ( <STR_LIT> , Tys ) ; ReflectFunction = M . getFunction ( Name ) ; if ( ReflectFunction != <NUM_LIT> ) { Res |= handleFunction ( ReflectFunction ) ; } } ReflectFunction = M . getFunction ( NVVM_REFLECT_FUNCTION ) ; if ( ReflectFunction != <NUM_LIT> ) Res |= handleFunction ( ReflectFunction ) ;"
LLVM,NVPTX,2310,"Predict the next statement of this code snippet:
 <s> SmallVector < StringRef , <NUM_LIT> > NameValPair ; NameValList [ j ] . split ( NameValPair , <STR_LIT> ) ; assert ( NameValPair . size ( ) == <NUM_LIT> && <STR_LIT> ) ; std :: stringstream ValStream ( NameValPair [ <NUM_LIT> ] ) ; int Val ; ValStream >> Val ;"
LLVM,NVPTX,2311,"Predict the next statement of this code snippet:
 <s> MachineBasicBlock * BB = & * BI ; for ( MachineBasicBlock :: iterator II = BB -> begin ( ) , IE = BB -> end ( ) ; II != IE ; ++ II ) { MachineInstr * Instr = & * II ; if ( ( Instr -> getOpcode ( ) == TargetOpcode :: PHI ) || ( Instr -> getOpcode ( ) == TargetOpcode :: DBG_VALUE ) ) continue ; bool needsReplacement = false ; for ( unsigned i = <NUM_LIT> , e = Instr -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand oper = Instr -> getOperand ( i ) ; if ( ! oper . isReg ( ) ) continue ; if ( oper . isDef ( ) ) continue ; if ( ! RegInfo -> isVirtualRegister ( oper . getReg ( ) ) ) continue ; MachineInstr * defInstr = MRI -> getVRegDef ( oper . getReg ( ) ) ; if ( ! defInstr ) continue ; if ( ! isSimpleMove ( defInstr ) ) continue ; MachineOperand defSrc = defInstr -> getOperand ( <NUM_LIT> ) ; if ( ! defSrc . isReg ( ) ) continue ; if ( ! RegInfo -> isVirtualRegister ( defSrc . getReg ( ) ) ) continue ; needsReplacement = true ; } if ( ! needsReplacement ) continue ; numReplacements ++ ; std :: vector < MachineOperand > operands ; for ( unsigned i = <NUM_LIT> , e = Instr -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand oper = Instr -> getOperand ( i ) ; bool flag = false ; do {"
LLVM,NVPTX,2312,"Predict the next statement of this code snippet:
 <s> for ( unsigned j = <NUM_LIT> , e = copy -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand oper = copy -> getOperand ( j ) ; allOperands . push_back ( oper ) ; if ( oper . isReg ( ) ) isDef . push_back ( oper . isDef ( ) ) ; else isDef . push_back ( false ) ; } for ( unsigned j = <NUM_LIT> , e = copy -> getNumOperands ( ) ; j != e ; ++ j ) copy -> RemoveOperand ( <NUM_LIT> ) ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( Instr ) ) ) ; for ( unsigned j = <NUM_LIT> , e = allOperands . size ( ) ; j != e ; ++ j ) { MachineOperand oper = allOperands [ j ] ; if ( oper . isReg ( ) ) { unsigned regnum = oper . getReg ( ) ; if ( isVectorRegister ( regnum ) ) { SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ; copy . addReg ( scalarRegs [ i ] , getDefRegState ( isDef [ j ] ) ) ; }"
LLVM,NVPTX,2313,"Predict the next statement of this code snippet:
 <s> } if ( ISVECDEST ( Instr ) ) { createVecDest ( F , Instr , copies ) ; return ; } if ( ISVECBUILD ( Instr ) ) { createVecBuild ( F , Instr , copies ) ; return ; } unsigned numcopies = numCopiesNeeded ( Instr ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; ++ i ) copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; ++ i ) { MachineInstrBuilder copy ( F , copies [ i ] ) ; std :: vector < MachineOperand > allOperands ; std :: vector < bool > isDef ; for ( unsigned j = <NUM_LIT> , e = copy -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand oper = copy -> getOperand ( j ) ; allOperands . push_back ( oper ) ; if ( oper . isReg ( ) ) isDef . push_back ( oper . isDef ( ) ) ; else isDef . push_back ( false ) ; } for ( unsigned j = <NUM_LIT> , e = copy -> getNumOperands ( ) ; j != e ; ++ j ) copy -> RemoveOperand ( <NUM_LIT> ) ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( Instr ) ) ) ; for ( unsigned j = <NUM_LIT> , e = allOperands . size ( ) ; j != e ; ++ j ) { MachineOperand oper = allOperands [ j ] ; if ( oper . isReg ( ) ) { unsigned regnum = oper . getReg ( ) ; if ( isVectorRegister ( regnum ) ) { SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ; copy . addReg ( scalarRegs [ i ] , getDefRegState ( isDef [ j ] ) ) ; } else copy . addOperand ( oper ) ;"
LLVM,NVPTX,2314,"Predict the next statement of this code snippet:
 <s> copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; MachineInstrBuilder copy ( F , copies [ <NUM_LIT> ] ) ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( copy ) ) ) ; MachineOperand dest = copy -> getOperand ( <NUM_LIT> ) ; unsigned regnum = dest . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ; copy -> RemoveOperand ( <NUM_LIT> ) ; std :: vector < MachineOperand > otherOperands ; for ( unsigned i = <NUM_LIT> , e = copy -> getNumOperands ( ) ; i != e ; ++ i ) otherOperands . push_back ( copy -> getOperand ( i ) ) ; for ( unsigned i = <NUM_LIT> , e = copy -> getNumOperands ( ) ; i != e ; ++ i ) copy -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = scalarRegs . size ( ) ; i != e ; ++ i ) copy . addReg ( scalarRegs [ i ] , RegState :: Define ) ; for ( unsigned i = <NUM_LIT> , e = otherOperands . size ( ) ; i != e ; ++ i ) copy . addOperand ( otherOperands [ i ] ) ;"
LLVM,NVPTX,2315,"Predict the next statement of this code snippet:
 <s> copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( copy ) ) ) ; MachineOperand dest = copy -> getOperand ( <NUM_LIT> ) ; unsigned regnum = dest . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ; copy -> RemoveOperand ( <NUM_LIT> ) ; std :: vector < MachineOperand > otherOperands ;"
LLVM,NVPTX,2316,"Predict the next statement of this code snippet:
 <s> unsigned regnum = src . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ; copy -> RemoveOperand ( <NUM_LIT> ) ; std :: vector < MachineOperand > otherOperands ; for ( unsigned i = <NUM_LIT> , e = copy -> getNumOperands ( ) ; i != e ; ++ i ) otherOperands . push_back ( copy -> getOperand ( i ) ) ; for ( unsigned i = <NUM_LIT> , e = copy -> getNumOperands ( ) ; i != e ; ++ i ) copy -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = scalarRegs . size ( ) ; i != e ; ++ i ) copy . addReg ( scalarRegs [ i ] ) ;"
LLVM,NVPTX,2317,"Predict the next statement of this code snippet:
 <s> unsigned destregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > dest = getScalarRegisters ( destregnum ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) copies . push_back ( BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) . addOperand ( Instr -> getOperand ( <NUM_LIT> + i ) ) ) ;"
LLVM,NVPTX,2318,"Predict the next statement of this code snippet:
 <s> void VectorElementize :: createVecBuild ( MachineFunction & F , MachineInstr * Instr , std :: vector < MachineInstr * > & copies ) { unsigned numcopies = numCopiesNeeded ( Instr ) ;"
LLVM,NVPTX,2319,"Predict the next statement of this code snippet:
 <s> copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; MachineInstrBuilder copy ( F , copies [ <NUM_LIT> ] ) ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( copy ) ) ) ; MachineOperand dest = copy -> getOperand ( <NUM_LIT> ) ; unsigned regnum = dest . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ;"
LLVM,NVPTX,2320,"Predict the next statement of this code snippet:
 <s> SmallVector < unsigned , <NUM_LIT> > src = getScalarRegisters ( srcregnum ) ; MachineOperand which = Instr -> getOperand ( <NUM_LIT> ) ; assert ( which . isImm ( ) && <STR_LIT> ) ;"
LLVM,NVPTX,2321,"Predict the next statement of this code snippet:
 <s> MachineInstrBuilder copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; MachineOperand which = Instr -> getOperand ( <NUM_LIT> + i ) ; assert ( which . isImm ( ) && <STR_LIT> ) ; int src = which . getImm ( ) ; int elem = src % numcopies ; if ( which . getImm ( ) < numcopies ) copy . addReg ( src1 [ elem ] ) ; else copy . addReg ( src2 [ elem ] ) ;"
LLVM,NVPTX,2322,"Predict the next statement of this code snippet:
 <s> if ( ! RegInfo -> isVirtualRegister ( defSrc . getReg ( ) ) ) continue ; needsReplacement = true ; } if ( ! needsReplacement ) continue ; numReplacements ++ ; std :: vector < MachineOperand > operands ; for ( unsigned i = <NUM_LIT> , e = Instr -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand oper = Instr -> getOperand ( i ) ; bool flag = false ; do { if ( ! ( oper . isReg ( ) ) ) break ; if ( oper . isDef ( ) ) break ; if ( ! ( RegInfo -> isVirtualRegister ( oper . getReg ( ) ) ) ) break ; MachineInstr * defInstr = MRI -> getVRegDef ( oper . getReg ( ) ) ; if ( ! ( isSimpleMove ( defInstr ) ) ) break ; MachineOperand defSrc = defInstr -> getOperand ( <NUM_LIT> ) ; if ( ! ( defSrc . isReg ( ) ) ) break ; if ( ! ( RegInfo -> isVirtualRegister ( defSrc . getReg ( ) ) ) ) break ; operands . push_back ( defSrc ) ; flag = true ; } while ( <NUM_LIT> ) ; if ( flag == false ) operands . push_back ( oper ) ; } for ( unsigned i = <NUM_LIT> , e = Instr -> getNumOperands ( ) ; i != e ; ++ i ) Instr -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = operands . size ( ) ; i != e ; ++ i ) Instr -> addOperand ( operands [ i ] ) ;"
LLVM,NVPTX,2323,"Predict the next statement of this code snippet:
 <s> if ( ISVECEXTRACT ( Instr ) ) { createVecExtract ( F , Instr , copies ) ; return ; } if ( ISVECINSERT ( Instr ) ) { createVecInsert ( F , Instr , copies ) ; return ; } if ( ISVECDEST ( Instr ) ) { createVecDest ( F , Instr , copies ) ; return ; } if ( ISVECBUILD ( Instr ) ) { createVecBuild ( F , Instr , copies ) ; return ; } unsigned numcopies = numCopiesNeeded ( Instr ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; ++ i ) copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; ++ i ) { MachineInstr * copy = copies [ i ] ; std :: vector < MachineOperand > allOperands ; std :: vector < bool > isDef ; for ( unsigned j = <NUM_LIT> , e = copy -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand oper = copy -> getOperand ( j ) ; allOperands . push_back ( oper ) ; if ( oper . isReg ( ) ) isDef . push_back ( oper . isDef ( ) ) ; else isDef . push_back ( false ) ; }"
LLVM,NVPTX,2324,"Predict the next statement of this code snippet:
 <s> void VectorElementize :: createLoadCopy ( MachineFunction & F , MachineInstr * Instr , std :: vector < MachineInstr * > & copies ) { copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; MachineInstr * copy = copies [ <NUM_LIT> ] ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( copy ) ) ) ; MachineOperand dest = copy -> getOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,2325,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = copy -> getNumOperands ( ) ; i != e ; ++ i ) copy -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = scalarRegs . size ( ) ; i != e ; ++ i ) { copy -> addOperand ( MachineOperand :: CreateReg ( scalarRegs [ i ] , true ) ) ; } for ( unsigned i = <NUM_LIT> , e = otherOperands . size ( ) ; i != e ; ++ i ) copy -> addOperand ( otherOperands [ i ] ) ;"
LLVM,NVPTX,2326,"Predict the next statement of this code snippet:
 <s> for ( unsigned i = <NUM_LIT> , e = copy -> getNumOperands ( ) ; i != e ; ++ i ) copy -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = scalarRegs . size ( ) ; i != e ; ++ i ) copy -> addOperand ( MachineOperand :: CreateReg ( scalarRegs [ i ] , false ) ) ; for ( unsigned i = <NUM_LIT> , e = otherOperands . size ( ) ; i != e ; ++ i ) copy -> addOperand ( otherOperands [ i ] ) ;"
LLVM,NVPTX,2327,"Predict the next statement of this code snippet:
 <s> void VectorElementize :: createStoreCopy ( MachineFunction & F , MachineInstr * Instr , std :: vector < MachineInstr * > & copies ) { copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; MachineInstr * copy = copies [ <NUM_LIT> ] ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( copy ) ) ) ; MachineOperand src = copy -> getOperand ( <NUM_LIT> ) ; unsigned regnum = src . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ; copy -> RemoveOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,2328,"Predict the next statement of this code snippet:
 <s> unsigned numcopies = numCopiesNeeded ( Instr ) ; unsigned destregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > dest = getScalarRegisters ( destregnum ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ;"
LLVM,NVPTX,2329,"Predict the next statement of this code snippet:
 <s> unsigned numcopies = numCopiesNeeded ( Instr ) ; unsigned destregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > dest = getScalarRegisters ( destregnum ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; copy -> addOperand ( Instr -> getOperand ( <NUM_LIT> + i ) ) ; copies . push_back ( copy ) ; }"
LLVM,NVPTX,2330,"Predict the next statement of this code snippet:
 <s> void VectorElementize :: createVecDest ( MachineFunction & F , MachineInstr * Instr , std :: vector < MachineInstr * > & copies ) { copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; MachineInstr * copy = copies [ <NUM_LIT> ] ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( copy ) ) ) ; MachineOperand dest = copy -> getOperand ( <NUM_LIT> ) ; unsigned regnum = dest . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ; copy -> RemoveOperand ( <NUM_LIT> ) ;"
LLVM,NVPTX,2331,"Predict the next statement of this code snippet:
 <s> copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( copy ) ) ) ; MachineOperand dest = copy -> getOperand ( <NUM_LIT> ) ; unsigned regnum = dest . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ; copy -> RemoveOperand ( <NUM_LIT> ) ; std :: vector < MachineOperand > otherOperands ; for ( unsigned i = <NUM_LIT> , e = copy -> getNumOperands ( ) ; i != e ; ++ i ) otherOperands . push_back ( copy -> getOperand ( i ) ) ; for ( unsigned i = <NUM_LIT> , e = copy -> getNumOperands ( ) ; i != e ; ++ i ) copy -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = scalarRegs . size ( ) ; i != e ; ++ i ) copy -> addOperand ( MachineOperand :: CreateReg ( scalarRegs [ i ] , true ) ) ;"
LLVM,NVPTX,2332,"Predict the next statement of this code snippet:
 <s> unsigned srcregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > src = getScalarRegisters ( srcregnum ) ; MachineOperand which = Instr -> getOperand ( <NUM_LIT> ) ; assert ( which . isImm ( ) && <STR_LIT> ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; copy -> addOperand ( MachineOperand :: CreateReg ( src [ which . getImm ( ) ] , false ) ) ;"
LLVM,NVPTX,2333,"Predict the next statement of this code snippet:
 <s> void VectorElementize :: createVecInsert ( MachineFunction & F , MachineInstr * Instr , std :: vector < MachineInstr * > & copies ) { unsigned numcopies = numCopiesNeeded ( Instr ) ; unsigned destregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned srcregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > dest = getScalarRegisters ( destregnum ) ; SmallVector < unsigned , <NUM_LIT> > src = getScalarRegisters ( srcregnum ) ; MachineOperand which = Instr -> getOperand ( <NUM_LIT> ) ; assert ( which . isImm ( ) && <STR_LIT> ) ; unsigned int elem = which . getImm ( ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; if ( i != elem ) copy -> addOperand ( MachineOperand :: CreateReg ( src [ i ] , false ) ) ; else copy -> addOperand ( Instr -> getOperand ( <NUM_LIT> ) ) ;"
LLVM,NVPTX,2334,"Predict the next statement of this code snippet:
 <s> DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; if ( i != elem ) copy -> addOperand ( MachineOperand :: CreateReg ( src [ i ] , false ) ) ;"
LLVM,NVPTX,2335,"Predict the next statement of this code snippet:
 <s> MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; MachineOperand which = Instr -> getOperand ( <NUM_LIT> + i ) ; assert ( which . isImm ( ) && <STR_LIT> ) ; int src = which . getImm ( ) ; int elem = src % numcopies ; if ( which . getImm ( ) < numcopies ) copy -> addOperand ( MachineOperand :: CreateReg ( src1 [ elem ] , false ) ) ;"
LLVM,NVPTX,2336,"Predict the next statement of this code snippet:
 <s> SmallVector < unsigned , <NUM_LIT> > src2 = getScalarRegisters ( src2regnum ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; MachineOperand which = Instr -> getOperand ( <NUM_LIT> + i ) ; assert ( which . isImm ( ) && <STR_LIT> ) ; int src = which . getImm ( ) ; int elem = src % numcopies ; if ( which . getImm ( ) < numcopies ) copy -> addOperand ( MachineOperand :: CreateReg ( src1 [ elem ] , false ) ) ;"
LLVM,NVPTX,2337,"Predict the next statement of this code snippet:
 <s> return new VectorElementize ( tm ) ;"
LLVM,NVPTX,2338,"Predict the next statement of this code snippet:
 <s> if ( ! isVectorInstr ( Instr ) ) continue ; copies . clear ( ) ; createCopies ( F , Instr , copies ) ; for ( unsigned i = <NUM_LIT> , e = copies . size ( ) ; i != e ; ++ i ) BB -> insert ( II , copies [ i ] ) ; assert ( ( copies . size ( ) > <NUM_LIT> ) && <STR_LIT> ) ; toRemove . push_back ( Instr ) ;"
LLVM,NVPTX,2339,"Predict the next statement of this code snippet:
 <s> if ( ! isVectorInstr ( Instr ) ) continue ; copies . clear ( ) ; createCopies ( F , Instr , copies ) ; for ( unsigned i = <NUM_LIT> , e = copies . size ( ) ; i != e ; ++ i ) BB -> insert ( II , copies [ i ] ) ;"
LLVM,NVPTX,2340,"Predict the next statement of this code snippet:
 <s> return <STR_LIT> ;"
LLVM,NVPTX,2341,"Predict the next statement of this code snippet:
 <s> getScalarRegClass ( const TargetRegisterClass * RC ) { assert ( is<ISA_LIT>VectorRegClass ( RC ) && <STR_LIT> ) ; return get<ISA_LIT>ElemClass ( RC ) ;"
LLVM,NVPTX,2342,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * vecClass = MRI -> getRegClass ( regnum ) ; const TargetRegisterClass * scalarClass = getScalarRegClass ( vecClass ) ; SmallVector < unsigned , <NUM_LIT> > temp ; for ( unsigned i = <NUM_LIT> , e = get<ISA_LIT>VectorSize ( vecClass ) ; i != e ; ++ i ) temp . push_back ( MRI -> createVirtualRegister ( scalarClass ) ) ; VectorToScalarMap [ regnum ] = temp ; }"
LLVM,NVPTX,2343,"Predict the next statement of this code snippet:
 <s> MachineOperand dest = mi -> getOperand ( <NUM_LIT> ) ; return isVectorRegister ( dest . getReg ( ) ) ; }"
LLVM,NVPTX,2344,"Predict the next statement of this code snippet:
 <s> const TargetRegisterClass * RC = MRI -> getRegClass ( reg ) ;"
LLVM,NVPTX,2345,"Predict the next statement of this code snippet:
 <s> bool VectorElementize :: isVectorRegister ( unsigned reg ) { const TargetRegisterClass * RC = MRI -> getRegClass ( reg ) ;"
LLVM,NVPTX,2346,"Predict the next statement of this code snippet:
 <s> MachineOperand oper = Instr -> getOperand ( i ) ; if ( ! oper . isReg ( ) ) continue ; if ( ! oper . isDef ( ) ) continue ; def = i ; numDefs ++ ; } assert ( ( numDefs <= <NUM_LIT> ) && <STR_LIT> ) ; if ( numDefs == <NUM_LIT> ) { unsigned regnum = Instr -> getOperand ( def ) . getReg ( ) ; if ( ISVECEXTRACT ( Instr ) ) regnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return get<ISA_LIT>VectorSize ( MRI -> getRegClass ( regnum ) ) ; } else if ( numDefs == <NUM_LIT> ) {"
LLVM,NVPTX,2347,"Predict the next statement of this code snippet:
 <s> if ( ! oper . isDef ( ) ) continue ; def = i ; numDefs ++ ; } assert ( ( numDefs <= <NUM_LIT> ) && <STR_LIT> ) ; if ( numDefs == <NUM_LIT> ) { unsigned regnum = Instr -> getOperand ( def ) . getReg ( ) ; if ( ISVECEXTRACT ( Instr ) ) regnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return get<ISA_LIT>VectorSize ( MRI -> getRegClass ( regnum ) ) ; } else if ( numDefs == <NUM_LIT> ) { assert ( ISVECSTORE ( Instr ) && <STR_LIT> ) ; unsigned regnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return get<ISA_LIT>VectorSize ( MRI -> getRegClass ( regnum ) ) ; }"
LLVM,NVPTX,2348,"Predict the next statement of this code snippet:
 <s> assert ( RegInfo -> isVirtualRegister ( dest . getReg ( ) ) && <STR_LIT> ) ; if ( MRI -> use_empty ( dest . getReg ( ) ) ) { deadMoves . push_back ( Instr ) ; } } } for ( unsigned i = <NUM_LIT> , e = deadMoves . size ( ) ; i != e ; ++ i ) F . DeleteMachineInstr ( deadMoves [ i ] -> getParent ( ) -> remove ( deadMoves [ i ] ) ) ; return deadMoves . size ( ) ;"
LLVM,NVPTX,2349,"Predict the next statement of this code snippet:
 <s> elementize ( F ) ; if ( RemoveRedundantMoves ) while ( <NUM_LIT> ) { if ( copyProp ( F ) == <NUM_LIT> ) break ; removeDeadMoves ( F ) ; } return true ;"
LLVM,NVPTX,2350,"Predict the next statement of this code snippet:
 <s> RegInfo = TM . getRegisterInfo ( ) ; InstrInfo = TM . getInstrInfo ( ) ; VectorToScalarMap . clear ( ) ; elementize ( F ) ; if ( RemoveRedundantMoves ) while ( <NUM_LIT> ) { if ( copyProp ( F ) == <NUM_LIT> ) break ; removeDeadMoves ( F ) ; }"
LLVM,NVPTX,2351,"Predict the next statement of this code snippet:
 <s> VectorElementize ( <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) {"
LLVM,NVPTX,2352,"Predict the next statement of this code snippet:
 <s> VectorElementize ( <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) {"