021b1832_l_A_1_6__Master_port_2_signals__Input__output
[Signals] HSIZEM2[2:0] [Description] Size of the AHB transfer Bit [2] is ignored. Bits[1:0] 00 8-bit 01 16-bit 10 32-bit 11 64-bit [Input/ output] 
Output
I n p u t
O u t p u t
L210 Cache Controller Technical Reference Manual A.1.6. Master port 2 signals
Input/ output