f0cd55fc___Low_Power_for_Memory_Webinar__Title
[Type] White Paper [Product] PowerPro [Highlight] In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings — this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art twopass solution is leading to an almost complete loss of power savings. [Title] 
*Clock Domain Crossing Aware Sequential Clock Gating
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