1486e9a1_FFT_IP___Dillon_Engineering__Memory_Usage
[Architecture] Dual Parallel [Speed] Fast [Logic Usage] Low [Comments] Two parallel FFT cores, in series with shuffle memory in between. Requires input/output buffers for natural ordered I/O. Extends parallel architecture lengths up to 2K or 4K points. [Memory Usage] 
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FFT IP - Dillon Engineering
Memory Usage