Title: +038=360.000-OU045T_03-PCD2.m4160 PLS SBC - Hardware Manual.pdf
Data code: Read mode:Offset position:Execution time: Cable break detection: Flagsconfigurable for 8..29 data bits and 0..2 control bits configurable for 100 kHz, 200 kHz, 300 kHz and 500 kHz (input filter designed for 500 kHz) Frequency Cable length < 50 m max. 500 kHz < 100 m max. 300 kHz < 200 m max. 200 kHz < 400 m max. 100 kHz configurable - Gray or binary Normal (single read). Ring mode: ‘double read and com- pare’ (not all encoders support this function) An offset can be defined when initializing the PCD2.H150. The defined offset is always subtracted in the FBs. The ‘Set Zero’ command also uses this offset register. typically 1.5 ms for reading the SSI value detected with the FB ‘timeout’ (10 ms) for cable break, encoder fault or incorrect addressing) ‘fPar_Err’, (if a wring FB parameter is sent) ‘fRing_err’ (if compare error in ‘double read’)6SSI interface 1 input for SSI data 1 output for SSI clock