Is there a danger of fragmentation of English in the growing emergence of distinct national varieties of English around the world?
Some degree of fragmentation there is bound to be; whether you call it a 'danger' depends on your point of view. Think about Latin over a thousand years ago: as it spread, it (or, at least, a streetwise version of it) evolved different varieties, and the result is French, Spanish, Portuguese, and so on today - the Romance family of languages, with its associated characters and literatures. Classical Latin, of course, remained alongside these other developments.
There is every likelihood that an analogous development will take place in English. Indeed, the prpocess has already begun, so much so that some writers (such as Tom McArthur) have talked about 'the English languages' and ''an English family of languages'. Already we have seen such developments as Tok Pisin in Papua New Guinea and 'Singlish' in Singapore, which derive from English but are now so different in form that they would be largely unintelligible to a monolingual English speaker. At the same time, standard English is used in these countries, alongside the local variant.
My view is that English will become increasingly diglossic, as time goes by - that is, where two variants of the same language are used within a society (as we see in Arabic, for example, with Classical and Colloquial variants co-existing). Standard English (albeit with some regional variants, such as we already see between British and American English) will continue to act as a unifying force, permitting international communication. Local varieties will evolve and become increasingly differentiated, permitting the expression of national or regional identities. How far those local varieties will come to differ from the standard varieties is difficult to predict. The situation is unprecedented, for there has never been a genuinely global language before and we have yet to determine the influence of the Internet on such developments.
Languages change as they spread. That is what they do. The consequences have to be managed, by individual countries. A widespread reaction has been to oppose the changes and to insist on the standard only; but if a country wishes to keep its identity strong, it needs to foster its local variety as it does the standard. People can easily cope with both. Indeed, in some parts of the world they handle three or more regional varieties with unselfconscious ease. At this point, of course, the notion of 'varieties of a language' begins to overlap with the notion of multilingualism.


Given an array of integers, write a method - maxGain - that returns the maximum gain. Maximum Gain is defined as the maximum difference between 2 elements in a list such that the larger element appears after the smaller element. If no gain is possible, return 0.
The naive approach would involve using 2 loops that would result in a runtime complexity of O(n2). Let's try and do better than that!
Since the larger element must always appear after the smaller element, this problem can be solved in a single pass. Keep a record of the maximum gain found so far, and the minimum element. When finding the maximum gain, use the difference between the current element and the minimum element found so far.


A method for performing a simulation of a system. The system includes an FPGA that is configured to implement simulation logic, such as a generic solver. For example, the FPGA device may implement a generic time domain solver or a generic frequency domain solver. The FPGA device is also configured with information representing a system model of the system under simulation. The system also includes input hardware for providing input signals for the simulation to the FPGA device and output hardware for receiving output signals computed by the simulation from the FPGA device. The system may be reconfigured to simulate different systems by changing the system model, without requiring the simulation logic (e.g., the generic solver) to be changed.
The present invention relates to the field of real-time simulation. More particularly, the invention relates to a solver implemented in hardware, where the solver is operable to perform real time simulations for different systems without requiring changes to the solver itself.
Simulation of a system may be implemented using software, hardware, or a combination of both. Creating a system simulation typically involves creating a model of the system, where the model represents the system or represents certain aspects of the system. For a given system, the system may be modeled in any number of different ways. Thus, the type of model that is created may depend on the particular aspects of the system that the modeler is interested in or the particular purpose of performing the simulation. For example, depending on the particular system and the particular problem to be solved, modeling the system may involve creating a set of mathematical equations representing the system, creating representations of various structural elements of the system and relationships between the elements, creating representations of random factors that may affect the system, etc. Creating a model of a system generally involves simplifying or approximating certain aspects of the system. However, for some systems or problems, a simple, abstracted model may serve to solve the problem at hand quite well, whereas for other systems or problems, a more complex model representing many details of the actual system may be desirable.
There are many reasons why it may be necessary or desirable to simulate a system. One common situation where simulation is useful is when the real system has not yet been created. In this instance, existing measurement/control logic may be coupled with a system simulation in the measurement/control loop, in order to test design variations and predict whether the planned system will operate as desired.
As another example, in many situations, it may be necessary to test the measurement/control logic that will be used in an actual measurement/control loop, but it may be infeasible, impractical, or impossible to do so with the real system. For example, it may be necessary to test whether the measurement/control logic will work properly under extreme or emergency situations in which it would be dangerous or economically infeasible to perform the test with a real system, e.g., due to the possibility of harm to the system or the environment of the system. Also, the real system may operate under conditions that make it impossible to perform or monitor a test, as in a space flight or deep-sea dive.
Thus, simulation may also be useful in the design process of the measurement/control logic, rather than the system. For example, as the commercial applications of measurement/control systems constantly increase, along with the time-to-market and technical demands for these systems, it becomes more important to be able to test new measurement/control logic prototypes with a minimum of delay. Since coupling these prototypes with a real system may take a significant amount of time, it is often desirable to instead test the prototypes with a simulation of the system. A shorter turnaround time enables more iterations and modifications to the measurement/control logic prototypes, helps ensure a high quality product, and enables new features to be introduced more quickly.
Traditionally, high level text-based programming languages have been used by programmers in writing application programs. Many different high level text-based programming languages exist, including BASIC, C, Java, FORTRAN, Pascal, COBOL, ADA, APL, etc. Programs written in these high level text-based languages are translated to the machine language level by translators known as compilers or interpreters. The high level text-based programming languages in this level, as well as the assembly language level, are referred to herein as text-based programming environments.
One embodiment of the present invention comprises a system and method for performing a simulation of a system, optionally in real time. The system includes a programmable hardware element, such as a Field Programmable Gate Array (FPGA) device, Programmable Logic Device (PLD), or other device that includes reconfigurable or programmable hardware. The programmable hardware element may be configured with simulation logic (a solver), thus allowing a very fast execution of the simulation.
The programmable hardware element may also be configured with a system model. The system model may comprise information that represents the system being simulated. For example, the system model may comprise matrix coefficients stored in memory (RAM) that are loaded into registers on the FPGA. The simulation logic comprises logic for simulating operation of the system under simulation, based on the system model and an input signal received from input hardware coupled to the programmable hardware element. In particular, the simulation logic produces a simulation output signal based on the system model and the input signal, where the simulation output signal is provided to output hardware coupled to the programmable hardware element. The output hardware produces output in response to the simulation output signal. Thus, a human observer may be able to evaluate performance of the system under simulation by analyzing the output produced in response to the simulation output signal.
The system may be reconfigured to simulate different systems simply by changing the system model, e.g., by updating the registers on the FPGA with different matrix coefficients representing a different model. In other words, the simulation logic may comprise “generic” logic for simulating different systems, depending on the particular system model with which the programmable hardware element is configured. The simulation logic may be modularized from the system model so that the programmable hardware element can quickly be reconfigured to simulate a different system model without requiring the programmable hardware element to be reconfigured with different simulation logic. Thus the system described herein may provide for fast execution, using an FPGA-implemented solver, while also being quickly reconfigurable with different system models.
In one particular embodiment, the programmable hardware element may comprise an FPGA device, and the simulation logic may comprise a generic solver, e.g., a time domain solver or a frequency domain solver. The generic solver may be operable to simulate operation of the system under simulation based on equations specified by the system model and input signals received from input hardware coupled to the FPGA device. For example, a generic time domain solver may be operable to periodically generate an output signal for the system under simulation at fixed time steps, where the output signal is generated based on the result of solving the equations, and where the equations are solved based on the input signals from the input hardware. Thus, in one embodiment the system may perform a time domain simulation of the system under simulation.
The generic time domain solver is referred to herein as “generic” because it is operable to perform a time domain simulation of different systems by simply reconfiguring the FPGA device with a different system model. The generic time domain solver may be modularized from the system model so that the FPGA device can easily and quickly be reconfigured with a different system model, without requiring the generic time domain solver to be changed. The logic or solver may comprise an FPGA implementation, e.g., a net list or bit file which is implemented on an FPGA, which requires a large amount of time to replace. In contrast, the system model comprise a plurality of model matrix coefficients that are stored in random access memory (RAM), such as a computer's RAM, and which may be loaded into registers in the FPGA. Thus the solver, which is expensive (in terms of time) to modify or replace, is generic and is preferably stored once on the FPGA, and provides a very fast execution. Thereafter different system models (comprising matrix coefficients stored in RAM) may be loaded into registers of the FPGA in a matter of microseconds. Thus the FPGA-based solver can be easily reconfigured with different system models very quickly and efficiently.
Further, since the FPGA is itself reconfigurable, different solvers can be implemented on the FPGA. For example, where a solver has been pre-compiled, the bit file of the pre-compiled solver can be implemented on the FPGA in the order of tens to hundreds of milliseconds. Where a new solver implementation requires a re-compile, this may take on the order of hours, due to the lengthy re-compile time.
In various embodiments the system may be used to simulate any of various kinds of systems. In other words, the system under simulation may comprise a system of any kind, and thus, the system model may comprise a model of a system of any kind. In general, the system model may model any type of apparatus, process, or condition. The system model may model physical, mechanical, electrical, chemical, thermodynamic, and/or other types of behavior of the system under simulation. As a few illustrative examples, the system model may comprise a model of an electronic circuit or other electronic system, an engine or engine component, an object in motion, a chemical reaction, a petroleum refining process, a room maintained at a setpoint temperature, a system of liquids flowing among different tanks, etc.
In one embodiment a computer system may couple to the FPGA device or other programmable hardware element. The computer system may execute software for creating a representation of the system under simulation and automatically converting the representation to a system model for deployment to the FPGA device or other programmable hardware element. As noted above, the system model may comprise one or more data structures, e.g., a plurality of model matrix coefficients.
The system described above may enable simulations of many types of systems to be performed, optionally in real time. By configuring the FPGA device or other programmable hardware element to implement the simulation, the simulation may proceed much faster than if the simulation were performed in software executing on a computer system. Also, the simulation of the system may be performed using real-world input hardware and output hardware. In other words, the simulation may be performed using the same input/output hardware that would be used together with an actual physical implementation of the system being modeled, where little or no modification is required to the input/output hardware. Moreover, the system model may be quickly and easily changed, which can enable users to ascertain and understand the effects of various modifications to the system under simulation.
FIG. 24 illustrates the top-level block diagram of an exemplary graphical program representing one embodiment of a generic time domain solver.
U.S. patent application Ser. No. 10/046,861 titled, “System and Method for Performing a Hardware in the Loop Simulation Using a Plurality of Graphical Programs that Share a Single Graphical User Interface,” filed Jan. 15, 2002.
U.S. patent application Ser. No. 10/892,829 titled, “A Graphical Program Which Executes a Timed Loop,” filed Jul. 16, 2004.
Computer System—any of various types of computing or processing systems, including a personal computer system (PC), mainframe computer system, workstation, network appliance, Internet appliance, personal digital assistant (PDA), television system, grid computing system, or other device or combinations of devices. In general, the term “icomputer system” can be broadly defined to encompass any device (or combination of devices) having at least one processor that executes instructions from a memory medium.
Referring now to FIG. 1A, one embodiment of a system for performing a simulation of a system is illustrated. The simulation may optionally be performed in real-time, i.e., may be performed in a manner where the simulation can respond to real world signals. FIG. 1A illustrates a programmable hardware element 199. In various embodiments the programmable hardware element 199 may comprise a programmable hardware element such as a Field Programmable Gate Array (FPGA) device, Programmable Logic Device (PLD), or other device that includes reconfigurable or programmable hardware.
The programmable hardware element 199 has been configured with simulation logic (e.g., a solver) 205. For example, a hardware configuration program may be used to configure the programmable hardware element 199 with the simulation logic 205. Implementation of a solver on the programmable hardware element 199 allows for very fast execution.
The programmable hardware element 199 has also been configured with a system model 208, comprising information that represents the system under simulation. The simulation logic 205 comprises logic for simulating operation of the system under simulation, based on the system model 208 and an input signal received from the input hardware 202 that is coupled to the programmable hardware element 199. In particular, the simulation logic 205 produces a simulation output signal based on the system model 208 and the input signal, where the simulation output signal is provided to the output hardware 204. The output hardware 204 produces output in response to the simulation output signal. Thus, a human observer may be able to evaluate performance of the system under simulation by analyzing the output produced in response to the simulation output signal.
The system of FIG. 1A may be reconfigured to simulate different systems simply by changing the system model 208. In other words, the simulation logic 205 may comprise “generic” logic (e.g., a generic solver) for simulating different systems, depending on the particular system model 208 with which the programmable hardware element 199 is configured. The simulation logic 205 may be modularized from the system model 208 so that the programmable hardware element 199 can quickly be reconfigured with a different system model 208 without requiring the programmable hardware element 199 to be reconfigured with different simulation logic 205.
More particularly, the generic solver may be implemented on the FPGA 199 from a net list or bit file. It generally takes a long time (many hours) to recompile a net list or bit file for placement on an FPGA 199, and hence the solver implemented on the FPGA 199 is designed to be generic to many system models. Thus the solver on the FPGA 199 does not have to be changed or modified very often, if at all. The system model is preferably implemented as a plurality of matrix coefficients stored in computer memory (RAM), where the matrix coefficients may represent a set of equations. Thus a system model may be loaded onto the FPGA 199 in a very short time (e.g., microseconds). Thus different system models may be stored on and simulated by the FPGA without requiring expensive re-compiles of the net list implementing the solver.
FIG. 1B illustrates a more particular embodiment of the system of FIG. 1A. In this embodiment the programmable hardware element 199 comprises an FPGA device 200, and the simulation logic 205 comprises a generic time domain solver 206. In this embodiment the system model 208 may comprise information specifying a set of equations that represent behavior of the system under simulation. The generic time domain solver 206 may comprise logic for solving the set of equations based on the input signal received from the input hardware 202. For example, the generic time domain solver 206 may be operable to periodically generate an output signal for the system under simulation at fixed time steps, where the output signal is generated based on the result of solving the equations, and where the equations are solved based on the input signal. Thus, the system of FIG. 1B may perform a time domain simulation of the system under simulation. The output hardware 204 may receive the output signal from the FPGA device 200 and produce output in response to the output signal, which may be analyzed to evaluate performance of the system under simulation.
The generic time domain solver 206 is referred to herein as “generic” because it is operable to perform a time domain simulation of different systems by simply reconfiguring the FPGA device 200 with a different system model 208 (e.g., by simply loading different sets of matrix coefficients from RAM into the memory of the FPGA). In one embodiment, the generic time domain solver 206 may be operable to perform a time domain simulation for any system model 208, within certain resource constraints. In the preferred embodiment the generic time domain solver 206 is modularized from the system model 208 so that the FPGA device 200 can easily and quickly be reconfigured with a different system model 208, without requiring the generic time domain solver 206 to be changed. For example, the FPGA device 200 may be configured with logic representing the generic time domain solver 206, which may include registers or other memory for storing data. Information representing a particular system model 208, e.g., model matrix coefficients, may simply be stored in the registers on the FPGA 200, and then the simulation may begin. Different system models 208 may be loaded into the memory of the FPGA 200, without requiring the generic time domain solver 206 to be re-configured. In other words, the generic time domain solver 206 operates in a generic manner so that it is able to perform a time domain simulation for any system model 208.
In one embodiment the system model 208 may be limited to a maximum number of nodes so as not to exceed the capacity of the FPGA. For example, the system model 208 may be limited to a maximum number of nodes so as: 1) not to exceed the capacity (slices) of the FPGA; or 2) not to slow down the simulation too much (e.g., resulting in a loss of real time performance); or 3) not to exceed the memory size on the FPGA. For example, where the system under simulation is an electronic circuit, the circuit may be limited to a maximum number of nodes. Also, in one embodiment the generic time domain solver 206 may be limited to performing simulations of linear systems, i.e., systems that can be modeled by a set of linear equations. Linear systems typically require significantly fewer resources to simulate than non-linear systems.
no serialization: The simulation is very fast (good for real time) but will be restricted to a specific maximum number of nodes that, if exceeded, would require either too many slices or too many multipliers.
Some serialization: The simulation is slower (weakening real time requirements) but allows more nodes because of shared slices and shared multipliers.
The limit of serialization is hit when it is becoming too slow or the number of nodes requires too many slices and/or RAM to be managed.
In various embodiments the system of FIG. 1A or 1B may be used to simulate any of various kinds of systems. In other words, the system under simulation may comprise a system of any kind, and thus, the system model 208 may comprise a model of a system of any kind. In general, the system model 208 may model any type of apparatus, process, or condition. The system model 208 may model physical, mechanical, electrical, chemical, thermodynamic, and/or other types of behavior of the system under simulation. As a few illustrative examples, the system model 208 may comprise a model of an electronic circuit or other electronic system, an engine or engine component, an object in motion, a chemical reaction, a petroleum refining process, a room maintained at a setpoint temperature, a system of liquids flowing among different tanks, etc.
As noted above, in one embodiment the system model 208 may comprise information specifying a set of equations representing behavior of the system under simulation. In other embodiments the system model may comprise various other kinds of information representing behavior of the system under simulation.
Thus, as noted above, configuring the programmable hardware element 199 (e.g., FPGA device 200) with the system model 208 may comprise configuring the programmable hardware element 199 with simple parameters, e.g., numeric parameters. For example, in one embodiment the system model 208 may comprise a set of numeric matrix coefficients, where the matrix coefficients specify a set of equations representing behavior of the system under simulation. In this embodiment, configuring the programmable hardware element 199 with the system model 208 may comprise storing the set of matrix coefficients in the programmable hardware element 199.
The system model 208 may comprise information in any of various formats suitable for configuring the programmable hardware element 199, e.g., depending on the type of the programmable hardware element 199. For example, the system model 208 may be formatted as a hardware configuration program for configuring the programmable hardware element 199 with the system model 208. For example, in one embodiment the system model 208 may comprise a netlist operable to configure gates or other elements of an FPGA device 200.
In one embodiment a user may create a representation of the system under simulation in one format, and this representation may then be programmatically or automatically converted to another format (e.g., a netlist or other hardware configuration program) to obtain a system model 208 suitable for deployment on the programmable hardware element 199. For example, as described below, in one embodiment the user may create a diagram representing the system under simulation, and the diagram may then be automatically converted to another format to obtain the system model 208 for configuring the programmable hardware element 199.
The input hardware 202 may comprise any kind of hardware device(s) operable to provide any kind of input signals to the FPGA device 200 (or other programmable hardware element 199), e.g., depending on what kind of system is under simulation. Similarly, the output hardware 204 may comprise any kind of hardware device(s) operable to receive output signals from the FPGA device 200, e.g., depending on what kind of system is under simulation.
As one simple example, consider a system model 208 of a circuit design for filtering audio signals, e.g., to eliminate certain frequencies. Thus, the system model 208 represents functionality of the filtering circuit, w ithout requiring an actual physical implementation of the filtering circuit to exist. In this example, the input hardware 202 may comprise a sound card, stereo system, or other hardware device operable to generate an audio signal, and may also comprise an analog-to-digital converter to convert the audio signal to a digital signal for input to the FPGA device 200 of FIG. 1B. The generic time domain solver 206 in the FPGA device 200 may receive the audio input signal as input and compute an audio output signal based on the audio input signal and the system model 208 of the filtering circuit. In other words, for each time segment of the audio input signal, the generic time domain solver 206 may simulate operation of the filtering circuit to produce a corresponding output signal identical to the output signal that would be produced if the audio input signal were filtered through an actual physical implementation of the filtering circuit. The output signal computed by the generic time domain solver 206 may then be passed to output hardware 204, such as a digital-to-analog converter and one or more audio speakers.
In the audio filtering circuit example described above, the output hardware 204 does not provide feedback to the input hardware 202. In other embodiments, the output hardware 204 may provide feedback to the input hardware 202, thus forming a feedback loop, as indicated by the broken arrows in FIGS. 1A and 1B. Thus, in some embodiments the output signal(s) from the simulation may influence the input signal(s) to the simulation, thus forming a feedback loop. For example, consider a system model 208 for modeling behavior of a system of tanks and valves that control the flow of liquid. In this example, the input hardware 202 may comprise one or more actuators for opening and closing the valves, and the output hardware 204 may comprise one or more sensors for sensing liquid levels in the tanks. The generic time domain solver 206 may simulate operation of the tanks and valves, based on input signals from the actuators, and may produce output signals representing the simulated liquid levels. The output signals may be passed to the sensors. The sensors may be coupled to a process control unit that provides feedback to the actuators based on the (simulated) liquid levels. The feedback from the sensors and the process control unit can affect the output signals generated by the actuators, thus affecting input to the simulated tank and valve system, so that a process control loop is formed.
As illustrated in FIGS. 1A and 1B, in one embodiment a computer system 82 may couple to the FPGA device 200 or other programmable hardware element 199. In one embodiment the computer system 82 may couple to the FPGA device 200 or other programmable hardware element 199 via a network, such as a LAN (e.g., Ethernet network or other local area network), a WAN (e.g., the Internet or an Intranet), a wireless network, etc. In another embodiment the FPGA device 200 or other programmable hardware element 199 may be coupled to the computer system 82 via an expansion slot of the computer system 82 or via any of various other kinds of interfaces. As described in detail below, in one embodiment the computer system 82 may execute software for creating a system model 208 of a system under simulation and deploying the system model 208 to the FPGA device 200 or other programmable hardware element 199.
The system illustrated in FIGS. 1A or 1B may enable simulations of many types of systems to be performed in real time. By configuring the FPGA device 200 or other programmable hardware element 199 to perform the simulation, the simulation may proceed much faster than if the simulation were performed in software executing on a computer system. Also, the simulation of the system may be performed using real-world input hardware 202 and output hardware 204. In other words, the simulation may be performed using the same input/output hardware that would be used together with an actual physical implementation of the system being modeled, where little or no modification is required to the input/output hardware. Moreover, the system model 208 may be quickly and easily changed, which can enable users to ascertain and understand the effects of various modifications to the system under simulation, as described in more detail below.
It is noted that FIGS. 1A and 1B represent exemplary embodiments of a system for performing a real-time simulation of a system, and numerous alternative embodiments are contemplated. For example, in one alternative embodiment the FPGA device 200 or other programmable hardware element 199 may be configured to implement a generic frequency domain solver instead of a generic time domain solver, so that the system performs a frequency domain response simulation of the system under simulation.
The remainder of the disclosure refers to the embodiment of the system shown in FIG. 1B. It is to be understood however, that in other embodiments the features described below may be implemented in a system that uses a programmable hardware element 199 other than an FPGA device 200, and/or where the FPGA device 200 or other programmable hardware element 199 is configured with simulation logic 205 other than a generic time domain solver 206.
As discussed above, in various embodiments the FPGA device 200. may be coupled to any kind of input hardware 202 and/or output hardware 204. In one embodiment the input hardware 202 and/or the output hardware 204 coupled to the FPGA device 200 may also be coupled to the computer system 82.
FIG. 2 illustrates an exemplary instrumentation control system 100 in which a host computer 82 connects to one or more instruments. The host computer 82 may comprise a CPU, a display screen, memory, and one or more input devices such as a mouse or keyboard as shown. For example, the computer 82 may operate with the one or more instruments to analyze, measure or control a unit under test (UUT) or process 150. In one embodiment, one or more of the instruments shown in FIG. 2 may also be coupled to the FPGA device 200.
The one or more instruments may include a GPIB instrument 112 and associated GPIB interface card 122, a data acquisition board 114 and associated signal conditioning circuitry 124, a VXI instrument 116, a PXI instrument 118, a video device or camera 132 and associated image acquisition (or machine vision) card 134, a motion control device 136 and associated motion control interface card 138, and/or one or more computer based instrument cards 142, among other types of devices.
The GPIB instrument 112 may be coupled to the computer 82 via the GPIB interface card 122 provided by the computer 82. In a similar manner, the video device 132 may be coupled to the computer 82 via the image acquisition card 134, and the motion control device 136 may be coupled to the computer 82 through the motion control interface card 138. The data acquisition board 114 may be coupled to the computer 82, and may interface through signal conditioning circuitry 124 to the UUT. The signal conditioning circuitry 124 may comprise an SCXI (Signal Conditioning eXtensions for Instrumentation) chassis comprising one or more SCXI modules 126.
The GPIB card 122, the image acquisition card 134, the motion control interface card 138, and the DAQ card 114 are typically plugged in to an I/O slot in the computer 82, such as a PCI bus slot, a PC Card slot, or an ISA, EISA or MicroChannel bus slot provided by the computer 82. However, these cards 122, 134, 138 and 114 are shown external to computer 82 for illustrative purposes. These devices may also be connected to the computer 82 through a serial bus or through other means.
The VXI chassis or instrument 116 may be coupled to the computer 82 via a VXI bus, MXI bus, or other serial or parallel bus provided by the computer 82. The computer 82 may include VXI interface logic, such as a VXI, MXI or GPIB interface card (not shown), which interfaces to the VXI chassis 116. The PXI chassis or instrument may be coupled to the computer 82 through the computer's PCI bus.
A serial instrument (not shown) may also be coupled to the computer 82 through a serial port, such as an RS-232 port, USB (Universal Serial bus) or IEEE 1394 or 1394.2 bus, provided by the computer 82. In typical instrumentation control systems an instrument will not be present of each interface type, and in fact many systems may only have one or more instruments of a single interface type, such as only GPIB instruments.
The instruments may be coupled to a unit under test (UUT) or process 150, or may be coupled to receive field signals, typically generated by transducers. The system 100 may be used in a data acquisition and control application, in a test and measurement application, an image processing or machine vision application, a process control application, a man-machine interface application, a simulation application, or a hardware-in-the-loop validation application.
In one embodiment, one or more of the various instruments illustrated in FIG. 2 may couple to the computer 82 over a network, such as the Internet, an Ethernet network, or other wired or wireless network connection.
A system such as shown in FIG. 1A or 1B may be used to perform any of various kinds of simulations, for any of various purposes. As one example, the system may be utilized to perform a “hardware-in-the-loop” simulation. In a hardware-in-the-loop simulation, a real physical implementation of a product may be used in conjunction with a simulated system. For example, consider a control unit designed to control a physical system. It may be impractical to test the control unit with the real physical system that the control unit is designed to control. For example, the tests may be too expensive, too dangerous, or impossible, e.g., the real physical system may not exist yet. Thus, it may be desirable to couple the real control unit to a simulated physical system to perform the tests. As one example, consider an electronic control unit designed to control the braking system of an automobile. It may be desirable to test how the braking system responds in a crash situation. By performing a hardware-in-the-loop simulation, the crash situation can be simulated without actually crashing a real automobile.
FIG. 3 illustrates one exemplary embodiment of the system of FIG. 1B, in which an electronic control unit 210 is tested in a hardware-in-the-loop simulation. The FPGA device 200 is configured to implement a generic time domain solver 206, as described above. Suppose that the electronic control unit 210 is designed to control the braking system of an automobile. Thus, the system model 208 comprises a model of the braking system. In this example, the electronic control unit 210 acts as both input hardware providing input signals to the FPGA device 200 (e.g., representing control signals to increase or decrease braking) and output hardware receiving output signals from the FPGA device 200 (e.g., representing various output measurements of the simulated braking system).
Although a hardware-in-the-loop simulation can be performed by simulating the physical system in software, the resulting simulation is often too slow to be performed in real time. By simulating the physical system (e.g., the braking system in the example above) on the FPGA device 200, the simulation may be performed in real time so that the behavior of the real physical system is closely approximated.
In the example of FIG. 3, the computer system 82 is also shown as being coupled to the electronic control unit 210. For example, in one embodiment the computer system 82 may execute a measurement program for measuring characteristics of the electronic control unit 210. For example, the measurement program may be utilized to gather information that can be analyzed to determine how well the electronic control unit 210 is performing. In one embodiment the measurement program executed by the computer system 82 may comprise a graphical program, i.e., a program whose functionality is specified by a plurality of interconnected nodes. In one embodiment the computer system 82 may execute a real-time operating system allowing the measurement. program to perform measurements in a loop at a precise rate and with a minimal amount of jitter.
In another embodiment, a system such as shown in FIG. 1A or 1B may be utilized to perform a “rapid control prototyping (RCP)” simulation. A goal of rapid control prototyping is to enable product designs to be tested in real-time simulations, e.g., before the design of the product has been finalized and before the product has actually gone into production. FIG. 4 illustrates one exemplary embodiment of the system of FIG. 1B, in which a prototype of an electronic control unit for controlling the braking system of an automobile is tested. The FPGA device 200 is configured to implement a generic time domain solver 206, as described above. In this example, the system model 208 comprises a model of the electronic control unit, e.g., a model of the circuitry that implements the control algorithm for controlling the braking system.
The FPGA device 200 is coupled to a real physical automobile braking system 212. The simulated electronic control unit implemented by the FPGA device 200 may control the braking system 212 much the same as a production electronic control unit would. However, the process of deploying and testing simulated control circuitry on the FPGA device 200 as a system model 208 may be much easier and quicker than producing a physical implementation of the control circuitry. Also, the design of the control circuitry may be quickly changed and re-deployed on the FPGA device 200 as a new system model 208, allowing different versions of the braking control algorithms to be easily tested. Thus, the design/test process may be a very tightly closed loop, allowing designs to be quickly and easily tested and significantly speeding up the product development process.
FIG. 5 is a block diagram representing one embodiment of the computer system 82 illustrated in FIGS. 1-4. It is noted that any type of computer system configuration or architecture can be used as desired, and FIG. 5 illustrates a representative PC embodiment. It is also noted that the computer system may be a general purpose computer system, a computer implemented on a card installed in a chassis, or other types of embodiments. Elements of a computer not necessary to understand the present description have been omitted for simplicity.
The computer may include at least one central processing unit or CPU (processor) 160 which is coupled to a processor or host bus 162. The CPU 160 may be any of various types, including an x86 processor, e.g., a Pentium class, a PowerPC processor, a CPU from the SPARC family of RISC processors, as well as others. A memory medium, typically comprising RAM and referred to as main memory, 166 is coupled to the host bus 162 by means of memory controller 164.
As shown, a device 190 may also be connected to the computer. The device 190 may include a processor and memory which may execute a real time operating system. The device 190 may also or instead comprise a programmable hardware element. For example, in one embodiment the device 190 may include the FPGA device 200 that is configured to simulate a system. In one embodiment the computer system 82 may be operable to deploy a system model 208 to the device 190 for simulation on the FPGA device 200. In other embodiments the FPGA device 200 may be coupled to the computer system 82 using other techniques, e.g., via a network, as noted above.
In one embodiment the main memory 166 may store software operable to create a representation of the system under simulation in response to user input. In one embodiment this representation may be deployed directly as the system model 208 to the FPGA device 200. In another embodiment, software in the main memory 166 may be operable to first automatically convert the representation of the system under simulation specified by the user to one or more other formats to produce a system model 208 to be deployed on the FPGA device 200. The main memory 166 may also store software operable to deploy the system model 208 to the FPGA device, as well as perform various other functions, as described below. The main memory 166 may also store operating system software, as well as other software for operation of the computer system.
FIG. 6 is a flowchart diagram illustrating one embodiment of a method for configuring the system of FIG. 1B. It is noted that FIG. 6 illustrates a representative embodiment, and alternative embodiments are contemplated. Also, various elements may be combined, omitted, or performed in different orders.
In 301, the FPGA device 200 is configured to implement a generic solver for simulating the time domain response of a system, i.e., is configured to implement the generic time domain solver 206. In other words, gates or other elements of the FPGA device 200 may be configured so that the FPGA is operable to implement logic for performing a time domain response simulation of a system under simulation, where the system under simulation is represented by a system model 208 that specifies a set of equations, as described above. For example, a netlist or hardware configuration program representing the generic time domain solver 206 may be used to configure the FPGA device 200. An FPGA device 200 that has been configured to implement a generic solver is also referred to herein as an “FPGA-based solver”.
In one embodiment the netlist or hardware configuration program representing the generic time domain solver 206 may be automatically generated from a software program. For example, a user may write a software program that defines the logic of the generic time domain solver 206, and the program may then be deployed on the FPGA device by first converting the program to the netlist. In one embodiment the netlist may be automatically generated based on a graphical software program. An exemplary graphical software program that defines the logic of an exemplary generic time domain solver is described below.
In 303, the input hardware 202 is coupled to the FPGA device 200. As discussed above, the input hardware 202 may comprise any kind of hardware device(s) operable to provide any kind of input signals to the FPGA device 200, e.g., depending on what kind of system is under simulation. In one embodiment, the FPGA device 200 may receive an input signal from an analog-to-digital converter, where the analog-to-digital converter converts an analog signal from another device to a digital signal.
In 305, the output hardware 204 is coupled to the FPGA device 200. As discussed above, the output hardware 202 may comprise any kind of hardware device(s) operable to receive any kind of output signals from the FPGA device 200, e.g., depending on what kind of system is under simulation. In one embodiment, the FPGA device 200 may provide an output signal to a digital-to-analog converter, where the digital-to-analog converter converts a digital signal from the FPGA device 200 to an analog signal which is then provided to another device.
In one embodiment the input hardware 202 and the output hardware 204 may comprise different sub-devices within a larger device. For example, the input hardware 202 may comprise an output port of a device, wherein the output port is operable to provide an output signal as the input signal to the FPGA device 200. Similarly, the output hardware 204 may comprise an input port of the device, wherein the input port is operable to receive as input the output signal produced by the FPGA device 200. Thus, the system may form a feedback loop.
Once the system has been configured as shown in FIG. 6, the FPGA device may then be configured with a specific system model 208 to perform a simulation of a specific system under simulation, as described below.
FIG. 7 is a flowchart diagram illustrating one embodiment of a method for performing a simulation of a system under simulation, using the system of FIG. 1B. It is noted that FIG. 7 illustrates a representative embodiment, and alternative embodiments are contemplated. Also, various elements may be combined, omitted, or performed in different orders.
In 315, a representation of the system under simulation may be created in response to user input, e.g., user input to software executing on the computer system 82. In various embodiments, 315 may comprise creating any of various kinds of information representing the system to be simulated. For example, the user may specify textual and/or graphical information representing the system to be simulated. As described below, in one embodiment, 315 may comprise creating a diagram of the system to be simulated in response to user input.
In 317, the representation created by user input in 315 may be programmatically or automatically converted to a system model 208 operable for simulation on the FPGA-based solver, e.g., by software executing on the computer system 82. Converting the representation created by user input to the system model 208 may comprise automatically converting the representation created by user input to another format suitable for configuring the FPGA device 200, such as a plurality of model coefficients, e.g., model matrix coefficients. In other words, the system model 208 for configuring the FPGA device 200 may be automatically generated based on the representation created by user input in 315. For example, the representation may be stored in memory, e.g., memory of the computer system 82, and software executing on the computer system 82 may analyze the representation to automatically convert it to the system model 208.
In one embodiment the representation created in response to user input may first be converted to one or more intermediate formats before arriving at the final system model 208 to be used in configuring the FPGA device 200. For example, as described below, in one embodiment the user may create a diagram of a circuit to be simulated in 315. The diagram may then be automatically converted to a netlist representing the circuit. The netlist may then be automatically converted to a matrix set of coefficients that specify a set of equations, where the matrix set of coefficients is then deployed on the FPGA device 200.
As described above, the system model 208 may specify a set of equations representing the system under simulation. In one embodiment the user may specify the equations directly in 315. In another embodiment a set of equations may be automatically derived from the representation created by user input. As one example, where the user creates a diagram representing an electronic circuit, a set of equations representing behavior of the electronic circuit may be automatically derived from the circuit diagram, e.g., where the equations are specified by a matrix set of coefficients, as described above.
In 319 the system model 208 generated in 317 may be automatically deployed to the FPGA-based solver. For example, software executing on the computer system 82 may communicate with the FPGA device 200 to cause the coefficients stored in memory to be loaded into memory (e.g., registers) on the FPGA device 200.
In an alternative (and currently less preferred) embodiment, the system model 208 may be configured as a hardware configuration program and implemented as gates or other elements on the FPGA device 200.
In 321 the simulation based on the system model 208 may be run on the FPGA device 200, where the simulation is driven by the generic time domain solver 206. As discussed above, running the simulation on the FPGA-based solver may allow the simulation to be performed very fast, optionally in real time. Running the simulation may involve the FPGA device 200 receiving input signals from the input hardware 202 and passing output signals to the output hardware 204, as described in more detail below. In one embodiment, the user may use a GUI or front panel to tune coefficients of the system model on the FPGA 200 as the simulation is being executed on the FPGA 200.
As noted above with respect to 315 of FIG. 7, in one embodiment the user may create the representation of the system under simulation by creating a diagram. FIG. 8 is a flowchart diagram illustrating an exemplary method for creating a diagram representing the system under simulation, i.e., illustrating one embodiment of 315 of FIG. 7. It is noted that FIG. 8 illustrates a representative embodiment, and alternative embodiments are contemplated. Also, various elements may be combined, omitted, or performed in different orders.
In 351, a plurality of components of the system under simulation may be displayed in the diagram, in response to user input, e.g., user input to software executing on the computer system 82. For example, the software may include a graphical user interface that enables a user to select various components for inclusion in the diagram, e.g., by dragging the components from various palettes and dropping them into the diagram, or using other selection techniques.
Each of the components may be displayed as an icon within the diagram. For example, where the system under simulation comprises an electronic circuit, the components may be displayed in the diagram as icons representing various electronic components that form the circuit. The user may arrange. or position the icons spatially within the diagram as desired.
In 353, lines or wires connecting the components may be displayed, in response to user input. For example, a plurality of lines or wires may be displayed, where each line connects two of the components in the diagram. The lines may specify interrelationships among the components. For example, where the system under simulation comprises an electronic circuit, a line between two components may represent an electrical connection between the components.
In one embodiment, creating the diagram representing the system under simulation may comprise creating a block diagram for an executable graphical program. In this embodiment, the diagram may be created in response to user input to a block diagram editor of a graphical programming development environment. Each component icon displayed in the diagram may comprise an executable node in the graphical program. In one embodiment, the lines or wires connecting the nodes or icons may represent data flow among the nodes. For example, a line connecting a first node and a second node may indicate that data produced by the first node is consumed by the second node during execution of the graphical program. The plurality of interconnected graphical program nodes may visually indicate functionality of the system under simulation.
In one embodiment the user may also create a graphical user interface (GUI) for the graphical program. The graphical user interface may include one or more GUI elements operable to display output from the graphical program on a display device. In one embodiment the functionality of displaying the program output may be preserved when the system model 208 is deployed on the FPGA device 200 so that during the simulation, the FPGA device 200 is operable to pass output from the simulation for display on a display device.
In one embodiment the graphical program may be executable to automatically generate at least a portion of the system model 208. For example, in one embodiment, each node in the graphical program may represent a particular type of system component. During execution of the graphical program, each node may execute to automatically generate a portion of the system model 208, where the portion generated by the node corresponds to the system component represented by the node. In another embodiment, the nodes in the graphical program may not generate the system model 208 directly but may generate information that characterizes the diagram, where the system model 208 is then automatically generated from this information. For example, suppose that the block diagram of the graphical program illustrates an electronic circuit. Each node in the graphical program may represent a particular component in the circuit. The graphical program may be automatically analyzed to generate a set of parameters, e.g., a set of matrix coefficients specifying equations that represent behavior of the circuit. The set of matrix coefficients is used as the system model 208 for configuring the FPGA device 200. For example, a netlist may be automatically generated from the graphical program, and the matrix coefficients may be generated from the netlist.
It is noted that FIG. 8 illustrates a representative embodiment of a method for creating a diagram representing the system under simulation, and in other embodiments other types of diagrams may be created. Also, the system under simulation may have other representations instead of, or in addition to, a diagram. For example, in one embodiment the user may create text information representing the system under simulation. In one embodiment, the user may create a text-based program representing the system under simulation. As another example, in one embodiment the user may create mathematical equations representing the system under simulation.
As noted above with respect to 317 of FIG. 7, the representation of the system under simulation created by user input may be programmatically or automatically converted to a system model 208 operable for simulation on the FPGA-based solver. In other words, the system model 208 may be automatically generated based on the representation of the system under simulation. FIG. 9 is a flowchart diagram illustrating an exemplary method for performing 317. It is noted that FIG. 9 illustrates a representative embodiment, and alternative embodiments are contemplated. Also, various elements may be combined, omitted, or performed in different orders.
In 371, a netlist may be automatically created based on the diagram or other system representation created by the user in 315.
In 373, the netlist may be automatically converted to a set of matrix coefficients.
As noted above with respect to 321 of FIG. 7, once the system model 208 has been deployed to the FPGA device 200, the simulation based on the system model 208 may be run on the FPGA device 200. FIG. 10 is a flowchart diagram illustrating an exemplary method for performing 321. It is noted that FIG. 10 illustrates a representative embodiment, and alternative embodiments are contemplated. Also, various elements may be combined, omitted, or performed in different orders.
In 391, the input hardware 202 provides one or more input signals to the FPGA device 200. For example, the input signals may be provided to the FPGA device 200 as digital signals.
In 393, the generic time domain solver 206 computes simulation output from the system model 208, based on the input signals received from the input hardware 202. For example, the generic time domain solver 206 may be operable to perform a plurality of time steps. For each time step, the solver may generate a portion of the output signal, where the output signal is generated based on the result of solving the equations that represent the system under simulation, and where the equations are solved based on the portion of the input signal received at that time step. In one embodiment the generic time domain solver 206 may perform the plurality of time steps deterministically at a precisely timed rate.
In 395, the generic time domain solver 206 passes the simulation output to the output hardware 204. The output hardware 204 produces output in response to the output signal, which may allow a user to evaluate performance of the system under simulation.
Various embodiments of the system of FIGS. 1A or 1B may enable users to easily test modifications to a system under simulation by simply changing the system diagram (or other representation) of the system under simulation and deploying a new system model based on the changed diagram to the FPGA or other programmable hardware element.
FIG. 11 is a flowchart diagram illustrating one embodiment of a method for testing changes to the system under simulation. It is noted that FIG. 11 illustrates a representative embodiment, and alternative embodiments are contemplated. Also, various elements may be combined, omitted, or performed in different orders.
In 421, a diagram or other representation of the system under simulation is created in response to user input, similarly as described above with reference to 315 of FIG. 7.
In 423, the representation of the system is programmatically converted to a system model 208 operable for simulation on the FPGA-based solver, similarly as described above with reference to 317 of FIG. 7.
In 425, the system model 208 is automatically deployed to the FPGA-based solver, similarly as described above with reference to 319 of FIG. 7.
In 427, the simulation is run on the FPGA-based solver to simulate the behavior of the system in real time, similarly as described above with reference to 321 of FIG. 7.
In 429, the system representation created in 421 is changed, or an entirely new system representation is created, in response to user input. For example, based on results observed during the original simulation, the user may decide to modify the system to achieve an improvement or correction or simply to test the effects of the modification. Thus, the user may change the diagram or other system representation that was originally created to reflect the desired modification. In one embodiment, the user may change the model using a GUI or front panel.
2 An entirely new circuit topology can be developed. For example components are added or completely removed from the model; this may or may not result in a different number of nodes in the model (FIG. 23 shows this case where the new topology is controlled by the pull-down menu showing the four options in this example).
In 431, the changed system representation may be programmatically converted to a changed system model 208 operable for simulation on the FPGA-based solver. In some embodiments, 431 is not required.
In 433, the changed system model 208 may be deployed to the FPGA-based solver, either automatically or in response to user input. Deploying the changed system model 208 to the FPGA solver may comprise replacing the previously deployed system model 208 in the memory of the FPGA 200 with the changed system model 208. In other words, the changed system model,208, which may comprise a plurality of coefficients, may be transferred from computer memory to the FPGA device 200. Thus the generic time domain solver performs the simulation based on the changed system model 208 instead of the previously deployed system model 208. As described above, the generic time domain solver 206 is modularized from the system model 208 used in the simulation and may be able to perform simulations for any system model 208. Thus, the changed system model 208 may be deployed on the FPGA device 200 without requiring changes to the generic time domain solver 206 deployed on the FPGA device 200. Also, since changing the system model on the FPGA 200 merely comprises updating registers on the FPGA 200 with new coefficients, the change can be performed very quickly.
In 435, the reconfigured simulation may be run on the FPGA-based solver to simulate the behavior of the changed system in real time. The generic time domain solver 206 may operate to produce a changed output signal based on the changed system model 208, which causes the output hardware 204 to produce changed output. Thus, the user may be able to observe the effects of the change made to. the system representation in 429, e.g., by observing the difference in the behavior of the output hardware 204. As indicated by the flowchart arrow returning from 435 to 429, the user may repeat the process of changing the system design as many times as desired.
In one embodiment, the changed system model 208 may be deployed to the FPGA device 200 “on-the-fly”, e.g., while the solver is executing on a prior model. It is noted that the change or update to the model and redeployment of the model onto the FPGA may be performed in a substantially continuous fashion relative to the solver executing the first model, i.e., the process of updating and executing the model appears continuous (smooth and natural) to the user. In other words, since the model update and deployment takes only microseconds, the solver operation may appear continuous and uninterrupted to the user during the update, re-deployment and execution of the updated model. Thus this operation may appear to occur in “real time” to the user.
For simple changes to the system under simulation, it may take the user only a few minutes or even seconds to modify the diagram or other representation of the system. In some embodiments, the process of automatically converting the diagram or other representation of the system to a system model 208 operable for simulation on the FPGA-based solver may be performed very quickly, possibly in a matter of seconds or even a fraction of a second. Likewise, in some embodiments the system model 208 may be relatively simple (e.g., a set of matrix coefficients) so that the FPGA device 200 can be reconfigured with the changed system model 208 very quickly, e.g., in a matter of seconds or even a fraction of a second. Thus, the user can very quickly observe the effects of modifying the system under simulation.
Moreover, since the simulation is performed by the FPGA device 200 operating in conjunction with real input hardware 202 and real output hardware 204, a very fast (e.g., real-time) simulation of each.version of the system under simulation may be performed. Thus, a system such as shown in FIG. 1A or 1B may allow users to easily and quickly perform real-time simulations of a set of system designs and observe the effects of various modifications in the-designs.
FIGS. 12A and 12B illustrate a flowchart diagram showing another embodiment of a method for testing changes to the system under simulation. In this embodiment it is even easier and quicker for the end user to observe the effects of changing the system under simulation.
In 461, a diagram generation program may be created, where the diagram generation program is operable to dynamically generate a plurality of system diagrams (or other system representations), depending on options interactively selected by a user. For example, when the diagram generation program is executed, the diagram generation program may display a graphical user interface including one or more GUI input controls allowing the user to select various options to configure the system under simulation. The diagram generation program may then programmatically or automatically generate a diagram of a system to be simulated, based on the system options selected by the user. Thus, the diagram of the system to be simulated may be automatically generated without user input directly specifying the diagram.
In 463, the diagram generation program may be executed, e.g., on the computer system 82. As described above, the diagram generation program may display a graphical user interface allowing the user to select various configuration options affecting the system under simulation.
In 465, the diagram generation program may receive user input to the graphical user interface selecting configuration options for a desired system to be simulated on the FPGA-based solver.
In 467, the diagram generation program may programmatically (automatically) generate a diagram representing the system to be simulated. The diagram may be generated at least in part based on the options selected by the user. For example, the diagram generation program may call functions of an application programming interface (API) for dynamically creating components in the diagram. In another embodiment, components in the diagram may not be dynamically generated, but different components may be automatically selected for inclusion in the diagram based on the configuration options selected by the user, e.g., through the use of a Case structure or similar mechanisms.
In 469, the system diagram generated by the diagram generation program may be automatically converted to a system model 208 operable for simulation on the FPGA-based solver, similarly as described above.
In 471, the system model 208 may be automatically deployed to the FPGA-based solver, similarly as described above.
In 473, the simulation may be run on the FPGA-based solver to simulate the behavior of the system represented by the generated diagram in real time, similarly as described above.
In 475, user input selecting new options to change or reconfigure the system under simulation may be received via the GUI of the diagram generation program. In one embodiment the user may select the new options while the simulation of the original system is running on the FPGA-based solver.
In 477, the diagram generation program may automatically or programmatically generate a changed system diagram (or may automatically change the original system diagram) based on the new options selected by the user.
In 479, the changed system diagram may be automatically converted to a changed system model 208 operable for simulation on the FPGA-based solver, similarly as described above.
In 481, the changed system model 208 may be automatically deployed to the FPGA-based solver, similarly as described above. As noted above, deployment of the changed system model may comprise loading one or more new matrix coefficients from RAM into memory on the FPGA.
In 483, the changed simulation may be run on the FPGA-based solver to simulate the behavior of the changed system in real time and to enable the user to evaluate the effect of changing the system.
The user may thus use the diagram generation program to generate successive versions of the system under simulation and observe a real-time simulation of each version, without having to do anything more than selecting different system options using the graphical user interface of the diagram generation program. This capability may be useful, for example, in an instructional setting. For example, an instructor in an electrical engineering course may create a diagram generation program operable to generate different circuit diagrams, depending on options selected by the user. As a simple example, the diagram generation program may be operable to alter a diagram of an audio filtering circuit by replacing components of the circuit with different circuit logic, depending on which type of filtering is selected by the user using the graphical user interface of the diagram generation program. The FPGA-based solver may be connected to audio input hardware and audio output hardware so that the user is able to hear the effects of each type of audio filtering in real time.
In one embodiment the method of FIGS. 12A and 12B may enable the user to observe the changed behavior of the system substantially immediately after the user has changed the configuration options via the GUI of the diagram generation program. For example, the diagram generation program may first automatically generate a changed diagram in response to the user input to the GUI. A changed system model may also be automatically generated from the changed diagram in response to the user input. The FPGA device 200 may also be automatically reconfigured with the changed system model in response to the user input. In one embodiment, each of these operations may occur very quickly so that the user experiences the change in output from the FPGA-based solver as occurring immediately, or substantially immediately, in response to the user's input to the GUI to change the configuration options. For example, in the above example of the audio filtering circuit simulation, the user may hear an immediate difference in sound produced by the simulation. In another embodiment, the operations may require more time but still may enable the user to observe the effects of the changes very quickly, e.g., on the order of a few seconds.
As discussed above, in one embodiment a user may create an executable graphical program representing the system to be simulated, wherein the graphical program comprises a block diagram that includes a plurality of interconnected nodes that visually indicate functionality of the system. For example, FIG. 13 illustrates a palette of nodes representing electrical circuit components. Nodes in this palette can be used to create a LabVIEW graphical program representing a circuit design. FIG. 14 illustrates an exemplary diagram of a circuit design to be simulated, where the circuit was created using the components illustrated in the palette of FIG. 13. The circuit diagram comprises a graphical program created using the LabVIEW graphical programming development environment. Each. LabVIEW wire represents a circuit node, and the wire value is an integer value that, in a unique way, represents the node number.
The graphical program representing the circuit may be executed, which results in generation of a netlist representing the circuit. Execution of the graphical program starts from the circuit ground terminal (that has a pre-allocated node value of 0) because it is the only component (sub-VI node) that only has an indicator. Execution of the graphical program then runs through all the sub-VI nodes, allocating a new node number each time a new wire is interpreted. (See FIG. 15.) Each sub-VI node updates the netlist with the corresponding component type, values and node connections. For example, FIG. 16 illustrates the block diagram of a sub-VI node representing a capacitor component in the circuit diagram. This sub-VI is operable to update the netlist to indicate the component type (i.e., capacitor) and the values and node connections. The final netlist is stored in a local variable. FIG. 17 illustrates a graphical representation of the final netlist representing the circuit.
The netlist representing the circuit can then be interpreted, and the appropriate matrix set of coefficients used to compute frequency response (Bode Plot) or time domain response (Time Domain Solver) can be derived.
FIG. 18 illustrates a graphical user interface for the graphical program shown in FIG. 19, which represents another circuit diagram. In this example, the graphical program acts as a diagram generation program such as described above with reference to FIGS. 12A and 12B because different components are selected for inclusion in the circuit based on options selected by the user via the graphical user interface of FIG. 18. In particular, the graphical program of FIG. 19 is operable to generate different circuits to perform filtering of an audio signal in various ways, depending on which options are selected by the user. The graphical program shown in FIG. 19 includes various Case structures that select different graphical code portions representing the audio filtering logic, based on the options selected by the user.
the solver in the programmable hardware element executing the second model based on the second information and one or more of the at least one first input signal or a second input signal.
wherein the solver is independent from the first and second models such that the solver can simulate the first and second models without requiring the programmable hardware element to be reconfigured with a different solver.
wherein the second information comprises a second set of coefficients representing a second set of equations that represent the second model.
wherein said storing the second information comprises transferring the second set of coefficients from the computer memory to memory on the programmable hardware element.
wherein the second model comprises a modified version of the first model.
the solver in the programmable hardware element generating at least one second output signal in response to executing the second model based on the second information and the at least one second input signal.
wherein the solver executes the first model and the second model in real time.
wherein the programmable hardware element comprises a Field Programmable Gate Array (FPGA).
wherein said configuring the programmable hardware element with the solver comprises: generating a netlist based on the solver; and configuring the programmable hardware element with the netlist.
automatically generating the second information based on the second diagram.
automatically generating the second information based on the modified first diagram.
wherein said storing second information on the programmable hardware element representing a second model and the solver in the programmable hardware element executing the second model are performed in a substantially continuous fashion relative to the solver in the programmable hardware element executing the first model.
wherein said storing second information on the programmable hardware element representing a second model and the solver in the programmable hardware element executing the second model are performed in- real time relative to the user.
wherein said storing second information on the programmable hardware element representing a second model and the solver in. the programmable hardware element executing the second model are performed in less than a millisecond.
wherein the solver in the programmable hardware element is operable to execute the second model based on the second information and at least one second input signal.
the solver in the programmable hardware element executing the changed first model after said modifying.
the first output device producing output based on the output signal produced by the solver, wherein the output enables a human to evaluate performance of the first system.
wherein the solver comprises a generic solver such that the programmable hardware element can be reconfigured with a model of a different system without requiring the programmable hardware element to be reconfigured with a different solver.
wherein the method enables a human to evaluate the change to the first system based on the changed output from the first output device.
wherein the solver in the programmable hardware element operates on the input signal from the first input device in real time.
wherein the solver in the programmable hardware element operates to provide the output signal to the first output device in real time.


Cleaning matters to homebrewers; in fact it matters a lot!
Five Star Chemicals are world leaders when it comes to cleaning and sanitizing homebrewing equipment.
These are not the same, and require different procedures and chemicals.
1/ You can only sanitize equipment that has already been cleaned.
2/ Dirty equipment always contains lots of bacteria.
3/ Cleaners are NOT sanitizers. Whether alkali or acid, cleaners should NOT be used as the final process.
4/ Sanitizers areNOT cleaners. Sanitizing is the final procedure after cleaning and is performed on clean equipment just berore brewing.
5/ Cleaning and sanitizing can be improved by both time and temperature. Longer contact time and / or increasing the temperature of solutions will improve results.
6/ Don't overuse chemicals. More is definately NOT better. Overuse of chemicals requires more water and/ or higher temperatures to rinse them off, and may even leave an unwanted residue or it may also just cake on to the equipment (making it very hard to remove). So, please follow the instructions.
7/ Cleaners and sanitizers must come in contact with 100% of the soils. This means that all blind areas, such as man-way lips or racking arms, must be hand cleaned and sanitized. The use of spray balls can also be very effective.
8/ Never add water to chemicals. Always blend cleaning or sanitizing chemicals into water.


I'm trying to understand why option D is an option anyway? What are they trying to test with that option? Even if they trick you to believe that there is a connection between the gesso used in the frames and the gesso used under the oil paint - why would the qualities of "hard and nonabsorbent type" trick you... Not sure if I am missing something here or if this option is HIGHLY irrelevant... Thanks in advance.
Good question - and actually I love "why is <wrong answer> even an answer anyway?" The more you can do that, the easier these are! I've often found in teaching classes one of the unanticipated challenges is trying to explain certain wrong answers...when there are so many things wrong with them, you don't really want to try to make them "close," you know?
On this one I think there's a "Think Like the Tentmaker" kind of lesson here with D. One reason it's there is that people who don't really get (or take the time to understand) the argument often choose answers that "feel familiar," and an easy way to do that is just to repeat language from the passage. D has "Renaissance," "gesso" - all the important words from the stimulus, so you'll get people who just think on feel that "hey this is really similar to the passage" and pick it, especially if in a rush.
But more interesting to me - take a look at that modifier "which is under the paint" in the conclusion. Without that modifier, I think I'd see one of the gaps in the argument as "hey how do we even know there's gesso in these paintings?" Gesso is first introduced in the conclusion sentence itself, so I could see someone who doesn't take note of that modifier thinking "I want to find an answer that establishes that gesso is in these Renaissance paintings to begin with," and D does do that. Of course, the argument itself has already established that these paintings include gesso, but if you don't see that you're right to be looking for that connection.
And this is something I've seen the testmaker do a fair bit - a trap answer to a strengthen question can restate information you already had (Data Sufficiency does this too), so it definitely feels relevant...it just doesn't add any new value to the argument, so it doesn't strengthen it.
why does the thickness of the layer of gesso matter? please help.
The restorers hypothesize that "it is a layer of material called gesso, which is under the paint, that causes the deterioration" of Renaissance oil paintings.
To answer the question, we are looking for the answer choice that "most strongly supports" this hypothesis.
(A) Renaissance oil paintings with a thin layer of gesso are less likely to show deterioration in response to climatic changes than those with a thicker layer.
This answer choice tells us that paintings with less gesso (a thinner layer), are less likely to show deterioration. Or, in other words, paintings with more gesso (a thicker layer), are more likely to deteriorate. This information supports the idea that gesso is the culprit causing the paintings to deteriorate, because there is a direct relationship between the amount of gesso used and the deterioration of the painting. (A) is the correct answer.


Choice E states: "point out a factor that was not anticipated by the scientists who conducted the field tests mentioned in the passage."
The key here is that we need to be able to infer the statement based on the passage. It is possible that the scientists did not anticipate that factor when they conducted the experiment. However, it's also possible that they did. We do not know based on the passage whether the scientists expected this observation or not. For that reason, we cannot infer E from the passage. On the other hand, the consequences of the predators' actions do contribute to the explanation as to why Martin's hypothesis was wrong.
For Question 6, can't it be answer choice E?


A new picture book I illustrated is now in print: Sparky and Jimmy: Sparky's Uganda Adventure. This is a book that Guardian Angel published for Spark Worldwide, an organization that helps children in many places around the world. Two of their ten orphanages are in Uganda: one for babies and one for children. They try very hard to place children in loving homes first, then the orphanage as a second option.
It was an incredible experience working on these pictures. The story is by Leanna Brewer, the founder of Spark Worldwide. It was like I felt her heart for these kids as I drew and painted. Her heart and hearts of all the Spark team are Huge for children, truly filled with a love that longs to give. Hearing her talk about the children she comes in contact with challenges me to allow my heart to be enlarged for others, especially children. I think sometimes, we see pictures of kids in other countries and feel like it is overwhelming or that our little gift really wont make much of a difference. As I worked on this book, I realized that is just not true. Helping one child have shoes, one child have a home or new pair of clothes or school book, makes a difference in that one life. One life is incredibly valuable. I realized that this past year also as my dad died. Helping care for him for several months before his death, I came to see more clearly how valuable one person is.
Leanna also had a vision for this book to be filled with joy, the joy that children are experiencing through the love of God that Spark Worldwide is giving. I think she did a beautiful job of sharing with very young children a glimpse of what another child in another country might experience in a way that is not scary or a big downer. It is loaded with hope and love, just like the Spark Team's hearts are.
The book can be ordered on Amazon: Sparky and Jimmy: Sparky's Uganda Adventure and also on the Gaurdian Angel website. There is also a companion coloring book that can be found on the Guardian Angel website.
I was going through work in my studio/office and found this drawing form a few years back. It is a drawing I did of one of my art students. I remember having so much fun with the details on this piece. I have loved drawing since as far back as I can remember.
Last night I worked until 2:00 in the morning adding type boxes and type on a picture book project. I finished up this morning, or at least I think so. The editor will confirm that. This is the first time I've had the opportunity to take part in that phase of the book making process and it is definitely a learning process. Several of the pages had to be redone a couple of times. It is much like rewriting. I actually loved it. Every time I write and rewrite, and every time I redo text boxes and illustration layout, I am learning. The creating process is a blast, a heck of a lot of work, but a blast!
I love learning about interesting things and simplifying the information for children. I love the way children think, pure and curious. I came across some info today about DNA, which is fascinating to my nerd side. Scientists used to believe that most DNA information was useless. Recently, they are learning that is not the case. In fact, what they used to term "Junk DNA" may contain information that could lead to cures of diseases. Science is progressing so rapidly. I feel like there is loads of info in not only our DNA but also a whole lot more in the blood that we are just not aware of yet. The way we are made fills me with wonder! It is like looking at a piece of artwork and studying it.
A little peek at a picture book project nearing the end. I have two illustrations left and the cover for the accompanying coloring book. SO honored to be a part of this project for Spark Worldwide!
I am so happy to have found this book written in 2016 by Elizabeth Van Steenwyk. It is the interesting story of Kate Warne, the first female detective at the Pinkerton Detective Agency. The story itself is fascinating, but the time period in which it took place is particularly interesting to me. Some of the research I am sorting through right now has to do with criminals and the 1800's. I had never heard of the famous Pinkerton Detective Agency, which is still around today. He actually used mugshots before Bertillon, but Bertillon was the first to use them and create them in a scientific investigative manor. Pinkerton is more known for wanted posters. Anyway, all this is super interesting to the nerd side of me as I am journeying through this research and writing project. Coming across new information that is connected with my research is like finding hidden treasure, and when it is found in a children's book, well...it's like eating a hot fudge sundae at the same time.
I came across this book today as I was cleaning off the bookshelf in my office/studio. I remember the day my grandmother gave it to me. I was so excited to receive a book like that, with so much interesting information and so many beautiful photos and illustrations. I spent many hours looking at and reading every page. It was one of my most cherished books, and still is. I found out about places I dreamed of going and things I wanted to see like the giant redwood trees. (It is still on my list.) Just looking through it brings back those magical feelings. I love books.
These are a few of the many many Christmas ornaments my dad made through the years. This will be the first Christmas of my entire life I have not spent with him. I am thankful to have so many beautiful remembrances. They bring me lots of joy. Joy looking at all the intricate details he patiently crafted, joy in all the time he had here with us, joy that he was a good father, and joy that I will one day see him again. The last picture is one I took the last month of his life, holding his hand, the hand that made these beautiful treasures.
Lance Brown is a local artist that actually performed/painted at my niece's school last year. He is a speed painter and really unusual and remarkable in the way he expresses with paint.
A writing project that is consuming a lot of my time right now is one that involves science and mystery. The research is so interesting. My husband has reminded me of all the I Shouldn't Be Alive shows I have watched along with all the Locked Up Abroad ones too. I guess I am more of a real life drama mystery person than I thought. We went and saw the new Murder on the Orient Express movie last night for a little inspiration and I loved it. It is not as action packed as today's stories, but very well done and a movie that makes the viewer have to think. The cinematography was exceptional. Okay, inspired. Now back to writing.


In this lesson Ss will be taught a grammar (modals of probability- past). First they will work on an audio script as exposure, the next part is language clarification and finally they will be given some controlled and semi controlled and freer practice.
T after greeting projects a slide of to girls and introduces them(Rachel and Christina) and says sth has happened to them.you are going to read about them.and say what do you think has happened? but before you read the text you should do a task. T shows a HO and asks Ss to fill in the gap.you can do it in your groups. T gives time.2m ICQs: Are you going to fill in the blanks?yes do you do it alone?no How much time do you have?2m T collects the answers and asks these CQs: dreadful Was it good news or bad news? bad did it cause shock and fear? yes ransack did burglars search the house?yes did they do it in a careless way?yes did they make the house messy?yes T shows HO2 and says this is the conversation between 2 girls but you don't have Christina's dialogue. you should read it and say what has happened. T asks Ss to read the text alone in 3 m. ICQs: are you going to read the text and guess what has happened?yes do you read it alone? yes how much time do you have?3m T monitors. T asks Ss to discuss their answers in groups. T collects answers and reasons.
meaning: T models these sentences on the board: They must have known no one was at home.. They can't have been stolen. They could have stolen your laptop. T elicits the meaning of these sentences. T asks Ss these Qs: Are they related to the past or present?past mentioning to the first sentence asks these qs: Are you sure about that? yes when you use must do you have enough evidence?yes again T mentions to the second sentence asks qs when you have can't in this sentence it means it was possible or impossible? impossible again T mentions to the third sentence asks Qs when you have could in this sentence it means it was possible or impossible? possible form: T asks Ss to say the part of speech related to the first sentence and models on the board sub+ modal+ have + past participle T does the same for other sentences. T asks these Qs: Can I use has instead of have for she and he? no Can I use simple past instead of past participle?no pronunciation: T asks Ss to read the sentences aloud T elicit the pronunciation and drills it chorally and semi chorally. T highlights the stress parts and connected speech. T uses back chain to make Ss pronounce the sentences correctly. T drills again.
T shows a HO which includes 4 sentences and some modals and asks Ss to discuss what is the difference between the meaning when we each modals. discuss in your groups. T gives time 5 m T asks ICQs are you going to discuss the meaning of sentences with different modals? yes How much time do you have?5m T monitors T collects the answers and reasons.
T shows Ss a picture of a place (related to a burglary) and a prompt which includes different modals. T asks Ss to say what do you think has happened ? T ask Ss to work in pairs and gives time.(4 m) are you going to talk about this picture?yes are you going to use the modals?yes T hands out the pictures and prompts and monitors. T takes notes of errors. T asks Ss to share their ideas with the class T does error corrections when feedback.


A Meatless McDonald's Burger Is a Given, So What's the Holdup?
Cobb salad is a classic American salad with chicken, bacon, hard boiled eggs, tomatoes, avocado, lettuce and blue cheese.
These gluten-free oat hazelnut chocolate chip blondies are a healthier version of the classic American sweet treat.


Post-pregnancy periods coming every two- to three-weeks! Is this normal?
I gave birth via C-Section to a healthy baby (our first!) in January. I had normal portpartum bleeding for four weeks afterward, then no bleeding until she was 7 months old, when my period resumed (I had been breastfeeding her, and I still do, though not as frequently, as I'm back at work - I supplement with formula). Since then, my periods have been very frequent - two to three weeks apart. It's been, well, rather depressing. Is this normal, or should I see my doctor about it? Has anyone else experienced this? Prior to pregnancy I was on The Pill, and my periods were of average length and duration. I'm not currently taking anything. Thanks for any answers you can give!
I know it has been a LONG time since you posted this, but I found it while searching (at 1 a.m. when I should be sleeping since my 4 mth. old is!) for others with the same thing. Yesterday I started my 2nd period this month (1st on the 8th, 2nd on the 29th). Not only is it too frequent, it is VERY heavy and I'm having pain in my lower right side bad enough to cause difficulty standing at times. I'm thinking it's just "normal" post-pregnancy hormonal garbage (I have no better word since I'm pooped and bordering anemic at this point, haha), but would like to make sure! I learned a long time ago that you can learn far more from other mommas who've been there than to rely on what medical journals say *should* be normal. In my search, yours is the most relevant post I've found so far, so I don't have any other good advice about it, but it sure is nice to know I'm not the only one w/this problem & asking for help! Since it's been so long, I hope all worked out for you!!
I have been wondering the same thing about frequent periods. I had my baby via c-section in March. When I went to my 6 week checkup we decided to use the shot birth control that last 3 months because it is supposed to be safest. After having frequent periods for 3 months (instead of none they say is most likely I was bleeding more days than not) I decided not to get another shot and hoped I would go back to normal. Now 5 months later I am still having frequent periods though at least now I usually have at least a week and half to 2 week break in between and they usually last about 4 - 5 days. I still wonder if the birth control messed me up or the hormones from pregnancy and birth. I still nurse regular too. Have any of you with this problem ever had luck with birth control regulating your period?
I got my first period when my son was 10 weeks. I attributed it to the fact that he had just started sleeping through the nights and the less frequent nursing triggered my period (I found some support online for this idea). Then, 2 weeks later I got my period again! Oddly, this time my period arrived just after my return to work--so I am pumping but not nursing as frequently. Again, I wonder whether the decrease in nursing is the culprit. I called my doctor and she said irregular periods after childbirth are normal. However, most of the irregularity you find when google searching is in regards to missed periods, not more frequent periods. I wonder whether anyone has any support for the idea that drops in nursing frequency triggers the start of a period?
I just had my first child in July. I nurse and didn't get my first period until December. It was very heavy initially but tapered off after a few days. I didn't get the next one until exactly 28 days later which was great! However, I have since gotten two shorter periods in the past few weeks. I've had normal cramping, except for one day where it was extremely bad. I'm a little concerned and will be making an appt with my obgyn today (since I started up again last night). I honestly think it is normal, but would like to be sure. I want to get preggo again in the next 6 months and wouldn't want there to be any issues. Hope this made you feel a little better. Keep me posted as to how you make out.
Hi! I am sorry you ladies are going through all this! It may be natural and normal, but it certainly is annoying, too. My first is now over 3y/o and my second is over 10mo., and things are back to normal for me, for the most part. Things eventually evened out after my first daughter, but I breastfed her and did not go back on the pill until after my second was born (I could only breastfeed her for a few months). Cycle-wise, things went back to the usual much faster after my second because (I think) I went back on the pill/was not nursing... but I did have to change my pill type. The first type I used made me anxious and moody; I switched to another kind and felt more like myself. I only mention it so that if you feel that things are not back to normal for you - either cycle- or mood-wise, please do talk with your doctor. I hope things even out for all of you! It is depressing but it should get better with time. Good luck to you, ladies! Thanks for sharing your stories.
I too am having frequent periods. My son was born in October, and even though I'm breastfeeding I started my period on Thanksgiving. Its December 5 and its started again. I dont whats going on because I thought I had a few months before I could even menstruate.
jackierae88 - I hope you're feeling better now! For me, it apparently was post-pregnancy hormone garbage (LOL! that's it, exactly!); I hope things have evened out for you, and you're feeling much better, too! michelerains - I hope you're doing better! I had been tested for postpartum thyroiditis, which has many symptoms like depression, weight gain or loss (depending on the phase one is in, hypo- or hyper-), fatigue, etc., past the usual postpartum fatigue. Generally a person has a hyperthyroid phase first, then enters a longer hypothyroid phase. I was tested and did not have it, but in talking with a friend with similar symptoms, she went in for a test and found she DID have it, and was treated. Chances are you do NOT have it, but it's worth checking into if you are still having symptoms. More info here on Babycenter; I can't seem to post the link, but search for "can postpartum-fatigue be a sign of thyroid problems?" Good luck and best wishes to you!!!!


Please enter nanometer (nm) value of length unit to convert nanometer to yard.
How Many Yard in a Nanometer?
There are 1.0936132983377E-9 yard in a nanometer.
1 Nanometer is equal to 1.0936132983377E-9 Yard.
This is a very easy to use nanometer to yard converter. First of all just type the nanometer (nm) value in the text field of the conversion form to start converting nm to yd, then select the decimals value and finally hit convert button if auto calculation didn't work. Yard value will be converted automatically as you type.
The decimals value is the number of digits to be calculated or rounded of the result of nanometer to yard conversion.
You can also check the nanometer to yard conversion chart below, or go back to nanometer to yard converter to top.