ɹˈiːdɪŋ ænd ɹˈaɪɾɪŋ tə dɹˈæm ɪz pɚfˈɔːɹmd baɪ sᵻlˈɛktɪŋ ðə ɹˈoʊ ænd kˈɑːlʌm dˈeɪɾə ɐdɹˈɛsᵻz ʌvðə dɹˈæm æz ðɪ ˈɪnpʊts tə ðə mˈʌltɪplˌɛksɚ sˈɜːkɪt, wˌɛɹ ðə dˈɛməltˌɪplɛksɚɹ ɔnðə dɹˈæm jˈuːsᵻz ðə kənvˈɜːɾᵻd ˈɪnpʊts tə sᵻlˈɛkt ðə kɚɹˈɛkt mˈɛmɚɹi loʊkˈeɪʃən ænd ɹᵻtˈɜːn ðə dˈeɪɾə, wˌɪtʃ ɪz ðˈɛn pˈæst bˈæk θɹuː ɐ mˈʌltɪplˌɛksɚ tə kənsˈɑːlᵻdˌeɪt ðə dˈeɪɾə ɪn ˈɔːɹdɚ tə ɹᵻdˈuːs ðə ɹᵻkwˈaɪɚd bˈʌs wˈɪtθ fɚðɪ ˌɑːpɚɹˈeɪʃən.
Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM uses the converted inputs to select the correct memory location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required bus width for the operation.