lˈaɪkwaɪz, ɐ jˈuːzɚɹ ʌv ˌɛfpˌiːdʒˌiːˈeɪ ɔːɹ ɡˈeɪt ɚɹˈeɪz wɪl ˈoʊnli jˈuːz ðɪ ɐnˈæləsˌɪs pˈoːɹʃən, æz ðə dɪzˈaɪn ɪz ɔːlɹˌɛdi fˈɪkst.
Likewise, a user of FPGAs or gate arrays will only use the analysis portion, as the design is already fixed.