ðə fɹˈʌntsˈaɪd bˈʌs ˌɛfˌɛsbˈiː ʌv sˌiːpˌiːjˈuːz ðæt ɪnstˈɔːl ɪn sˈɑːkɪt pˈiː kæn ɹˈʌn æt fˈoːɹhˈʌndɹɪd, fˈaɪvhˈʌndɹɪd θˈɜːɾi θɹˈiː, sˈɪkshˈʌndɹɪd sˈɪksti sˈɛvən, ˈeɪthˈʌndɹɪd, ɔːɹ wˈʌn θˈaʊzənd sˈɪksti sˈɪks ˌɛmtˈiː slˈæʃ ˈɛs. baɪ ɐdˈæptɪŋ ðə mˌʌltɪplˈaɪɚ ðə fɹˈiːkwənsi ʌvðə sˌiːpˌiːjˈuː kæn θɹˈɑːɾəl ˌʌp ɔːɹ dˌaʊn tə sˈeɪv pˈaʊɚ, ɡˈɪvən ðæt ˈɔːl sˈɑːkɪt pˈiː sˌiːpˌiːjˈuːz səpˈoːɹt ˈaɪst, ɛksˈɛpt fɔːɹ sˈɛlɚɹən ðæt duːnˌɑːt səpˈoːɹt ˈaɪst.
The front-side bus (FSB) of CPUs that install in Socket P can run at 400, 533, 667, 800, or 1066 MT/s. By adapting the multiplier the frequency of the CPU can throttle up or down to save power, given that all Socket P CPUs support EIST, except for Celeron that do not support EIST.