ʌnfˈɔːɹtʃənətli, mˈoʊst kəmˈɜːʃəl tˈuːlz fˈoʊkəs ˌɔn pˈoʊstlˈeɪaʊt vˌɛɹɪfɪkˈeɪʃən ʌvðə pˈaʊɚ ɡɹˈɪd wɛn ðɪ ɛntˈaɪɚ tʃˈɪp dɪzˈaɪn ɪz kəmplˈiːt ænd diːtˈeɪld ˌɪnfɚmˈeɪʃən ɐbˌaʊt ðə pˌæɹəsˈɪɾɪks ʌvðə pˈaʊɚ ænd ɡɹˈaʊnd lˈaɪnz ænd ðə kˈɜːɹənts dɹˈɔːn baɪ ðə tɹænzˈɪstɚz ɑːɹ nˈoʊn.
Unfortunately, most commercial tools focus on post-layout verification of the power grid when the entire chip design is complete and detailed information about the parasitics of the power and ground lines and the currents drawn by the transistors are known.