wˌaɪl ɐ tʃˈænəl fɔːɹ ˈɛvɹi dɹˈæm sˈɛl wʊd biː ðɪ aɪdˈiəl səlˈuːʃən, ˈædɪŋ mˈoːɹ tʃˈænəlz ɪz vˈɛɹi dˈɪfɪkəlt dˈuː tə wˈaɪɚ kˈaʊnt, lˈaɪn kəpˈæsɪtəns, ænd ðə nˈiːd fɔːɹ pˈæɹəlˌɛl ˈæksɛs lˈaɪnz tə hæv aɪdˈɛntɪkəl lˈɛŋθs.
While a channel for every DRAM cell would be the ideal solution, adding more channels is very difficult due to wire count, line capacitance, and the need for parallel access lines to have identical lengths.