def compute_while(self):
        """This method executes the module once for each input.

        Similarly to controlflow's fold, it calls update() in a loop to handle
        lists of inputs.

        """
        name_condition = self.control_params.get(
            ModuleControlParam.WHILE_COND_KEY, None)
        max_iterations = int(self.control_params.get(
            ModuleControlParam.WHILE_MAX_KEY, 20))
        delay = float(self.control_params.get(
            ModuleControlParam.WHILE_DELAY_KEY, 0.0))
        name_state_input = self.control_params.get(
            ModuleControlParam.WHILE_INPUT_KEY, None)
        if not name_state_input:
            name_state_input = None
        else:
            try:
                name_state_input = list(ast.literal_eval(name_state_input))
            except __HOLE__:
                name_state_input = [name_state_input]
        name_state_output = self.control_params.get(
            ModuleControlParam.WHILE_OUTPUT_KEY, None)
        if not name_state_output:
            name_state_output = None
        else:
            try:
                name_state_output = list(ast.literal_eval(name_state_output))
            except ValueError:
                name_state_output = [name_state_output]

        from vistrails.core.modules.basic_modules import create_constant

        if name_state_input or name_state_output:
            if not name_state_input or not name_state_output:
                raise ModuleError(self,
                                  "Passing state between iterations requires "
                                  "BOTH StateInputPorts and StateOutputPorts "
                                  "to be set")
            if len(name_state_input) != len(name_state_output):
                raise ModuleError(self,
                                  "StateInputPorts and StateOutputPorts need "
                                  "to have the same number of ports "
                                  "(got %d and %d)" %(len(name_state_input),
                                                      len(name_state_output)))

        module = copy.copy(self)
        module.had_error = False
        module.is_while = True
        state = None

        loop = self.logging.begin_loop_execution(self, max_iterations)
        for i in xrange(max_iterations):
            if not self.upToDate:
                module.upToDate = False
                module.computed = False

                # Set state on input ports
                if i > 0 and name_state_input:
                    for value, input_port, output_port \
                     in izip(state, name_state_input, name_state_output):
                        if input_port in module.inputPorts:
                            del module.inputPorts[input_port]
                        new_connector = ModuleConnector(
                                create_constant(value), 'value',
                                module.output_specs.get(output_port, None))
                        module.set_input_port(input_port, new_connector)

            loop.begin_iteration(module, i)

            try:
                module.update() # might raise ModuleError, ModuleSuspended,
                                # ModuleHadError, ModuleWasSuspended
            except ModuleSuspended, e:
                e.loop_iteration = i
                raise

            loop.end_iteration(module)

            if name_condition is not None:
                if name_condition not in module.outputPorts:
                    raise ModuleError(
                            module,
                            "Invalid output port: %s" % name_condition)
                if not module.get_output(name_condition):
                    break

            if delay and i+1 != max_iterations:
                time.sleep(delay)

            # Get state on output ports
            if name_state_output:
                state = [module.get_output(port) for port in name_state_output]

            self.logging.update_progress(self, i * 1.0 / max_iterations)

        loop.end_loop_execution()

        for name_output in self.outputPorts:
            self.set_output(name_output, module.get_output(name_output))
dataset/ETHPy150Open VisTrails/VisTrails/vistrails/core/modules/vistrails_module.py/Module.compute_while