def get_other_ports(cls, other_list):
    """ addOtherPorts(cls: Module, other_list: list) -> None
    Convert all other ports such as Insert/Add.... into input/output

    Keyword arguments:
    cls        --- class
    other_dict --- any other method signatures that is not
                   Algorithm/SetGet/Toggle/State type

    """
    input_ports = []
    for name in other_list:
        # DAK: check for static methods as name.upper() == name
        if name in disallowed_other_ports or name.upper() == name:
            continue
        elif name=='CopyImportVoidPointer':
            # FIXME add documentation
            ps = InputPortSpec(name='CopyImportVoidString',
                               method_name='CopyImportVoidPointer',
                               port_type='basic:String',
                               show_port=True)

        # elif name[:3] in ['Add','Set'] or name[:6]=='Insert':
        else:
            method = getattr(cls, name)
            signatures = ""
            if not isinstance(method, int):
                signatures = parser.get_method_signature(method)
            if len(signatures) > 1:
                prune_signatures(cls, name, signatures)
            docstring = get_doc(cls, name)
            v = vtk.vtkVersion()
            version = [v.GetVTKMajorVersion(),
                       v.GetVTKMinorVersion(),
                       v.GetVTKBuildVersion()]
            if version < [6, 0, 0]:
                # Always use VTK6-style names for InputData-style types
                name = get_vtk6_name(cls, name)
            for (ix, sig) in enumerate(signatures):
                ([result], params) = sig
                port_types = get_port_types(params)
                if not (name[:3] in ['Add','Set'] or
                        name[:6]=='Insert' or
                        (port_types is not None and len(port_types) == 0) or
                        result is None):
                    continue
                if is_type_allowed(port_types):
                    n = resolve_overloaded_name(name, ix, signatures)
                    if n.startswith('Set'):
                        n = n[3:]
                    show_port = False
                    if len(port_types) < 1:
                        raise Exception("Shouldn't have empty input")
                    elif len(port_types) == 1:
                        if name[:3] in ['Add','Set'] or name[:6]=='Insert':
                            try:
                                show_port = port_types[0] not in type_map_values
                            except __HOLE__:
                                pass
                        port_types = port_types[0]
                    ps = InputPortSpec(name=n,
                                       method_name=name,
                                       port_type=port_types,
                                       show_port=show_port,
                                       docstring=docstring,
                                       depth=1)
                    input_ports.append(ps)
                elif result == None or port_types == []:
                    n = resolve_overloaded_name(name, ix, signatures)
                    ps = InputPortSpec(name=n,
                                       method_name=name,
                                       port_type='basic:Boolean',
                                       method_type='nullary',
                                       docstring=get_doc(cls, name),
                                       depth=1)
                    input_ports.append(ps)
    return input_ports, []
dataset/ETHPy150Open VisTrails/VisTrails/vistrails/packages/vtk/vtk_wrapper/parse.py/get_other_ports