def verilog_to_pymtl( model, verilog_file, c_wrapper_file,
                      lib_file, py_wrapper_file, vcd_en, lint, verilator_xinit ):

  model_name = model.class_name

  try:
    vlinetrace = model.vlinetrace
  except __HOLE__:
    vlinetrace = False

  # Verilate the model  # TODO: clean this up
  verilate_model( verilog_file, model_name, vcd_en, lint )

  # Add names to ports of module
  for port in model.get_ports():
    port.verilog_name   = verilog_structural.mangle_name( port.name )
    port.verilator_name = verilator_mangle( port.verilog_name )

  # Create C++ Wrapper
  cdefs = create_c_wrapper( model, c_wrapper_file, vcd_en, vlinetrace, verilator_xinit )

  # Create Shared C Library
  create_shared_lib( model_name, c_wrapper_file, lib_file,
                     vcd_en, vlinetrace )

  # Create PyMTL wrapper for CFFI interface to Verilated model
  create_verilator_py_wrapper( model, py_wrapper_file, lib_file,
                               cdefs, vlinetrace )

#-----------------------------------------------------------------------
# verilate_model
#-----------------------------------------------------------------------
# Convert Verilog HDL into a C++ simulator using Verilator.
# http://www.veripool.org/wiki/verilator
dataset/ETHPy150Open cornell-brg/pymtl/pymtl/tools/translation/verilator_cffi.py/verilog_to_pymtl