How is the number of channels adjusted in efficientnet
I was reading the code at efficientnet and was shocked by its clever ideas. But I don't quite understand how it adjusts the number of channels.

def round_filters(filters, width_coefficient, depth_divisor):

  filters *= width_coefficient
  new_filters = int(filters + depth_divisor / 2) // depth_divisor * depth_divisor
  new_filters = max(depth_divisor, new_filters)
  # Make sure that round down does not go down by more than 10%.
  if new_filters &lt; 0.9 * filters:
     new_filters += depth_divisor
  return int(new_filters)


I know the number of channels has to be adjusted by the width factor, but why do I do the following? What is depth_divisor?

It's making the scaled width divisible by depth_divisor. You can view as rounding the scaled width to the nearest multiple of depth_divisor with some additional consideration (round up when going down more than 10%). In almost all applications of this function in various MobileNets and EfficientNets the depth_divisor is 8.

Why 8? Mostly due to the constraints of common hardware accelerators like GPU and TPU. See a recent cuDNN developer guide and count the number of 'multiple of 8', 'multiple of 32', etc guidelines for optimal performance of certain operations: 

https://docs.nvidia.com/deeplearning/sdk/cudnn-developer-guide/index.html


  For algorithms other than *_ALGO_WINOGRAD_NONFUSED, when the following
  requirements are met, the cuDNN library will trigger the Tensor Core
  operations: 
  
  
  Input, filter, and output descriptors (xDesc, yDesc,
  wDesc, dxDesc, dyDesc and dwDesc as applicable) are of the dataType =
  CUDNN_DATA_HALF (i.e., FP16). For FP32 dataType see FP32-to-FP16
  Conversion.
  The number of input and output feature maps (i.e., channel dimension
  C) is a multiple of 8. When the channel dimension is not a multiple of
  8, see Padding.
  The filter is of type CUDNN_TENSOR_NCHW or CUDNN_TENSOR_NHWC.
  If using a filter of type CUDNN_TENSOR_NHWC, then the input, filter,
  and output data pointers (X, Y, W, dX, dY, and dW as applicable) are
  aligned to 128-bit boundaries.
  

