Since 32nm node, Intel has applied the above-mentioned self-aligned via approach, which allows two vias separated by a small enough pitch (112.5 nm for Intel 32nm metal)[REF] to be patterned with one resist opening instead of two separate ones [REF].
The use of SID may be applied to 2D arrays, by iteratively adding features equidistant from the previously present features, doubling the density with each iteration [REF].