It has a revised memory subsystem compared to the previous e5500 core with four cores combined into a CPU Cluster, sharing a large L2 cache and the e6500 cores supports up to eight CPU Clusters for very large multiprocessing implementations.
Each core has five integer units (four simple and one complex), two load-store units, one 128-bit AltiVec unit, 32+32 kB instruction and data L1 caches.