@instruction<EOL><INDENT>def PSRLQ(cpu, dest, src):<DEDENT>
count = src.read()<EOL>count = Operators.ITEBV(src.size, Operators.UGT(count, <NUM_LIT>), <NUM_LIT:64>, count)<EOL>count = Operators.EXTRACT(count, <NUM_LIT:0>, <NUM_LIT:64>)<EOL>if dest.size == <NUM_LIT:64>:<EOL><INDENT>dest.write(dest.read() >> count)<EOL><DEDENT>else:<EOL><INDENT>hi = Operators.EXTRACT(dest.read(), <NUM_LIT:64>, <NUM_LIT:64>) >> count<EOL>low = Operators.EXTRACT(dest.read(), <NUM_LIT:0>, <NUM_LIT:64>) >> count<EOL>dest.write(Operators.CONCAT(<NUM_LIT>, hi, low))<EOL><DEDENT>
Shift Packed Data Right Logical

        Shifts the bits in the individual quadword in the destination operand to the right by
        the number of bits specified in the count operand . As the bits in the data elements
        are shifted right, the empty high-order bits are cleared (set to 0). If the value
        specified by the count operand is greater than  63, then the destination operand is set
        to all 0s.

        if(OperandSize == 64) {
                        //PSRLQ instruction with 64-bit operand:
                        if(Count > 63) Destination[64..0] = 0;
                        else Destination = ZeroExtend(Destination >> Count);
                }
                else {
                        //PSRLQ instruction with 128-bit operand:
                        if(Count > 15) Destination[128..0] = 0;
                        else {
                                Destination[0..63] = ZeroExtend(Destination[0..63] >> Count);
                                Destination[64..127] = ZeroExtend(Destination[64..127] >> Count);
                        }
                }