def _STM(cpu, insn_id, base, regs):
if cpu.instruction.usermode:<EOL><INDENT>raise NotImplementedError("<STR_LIT>")<EOL><DEDENT>increment = insn_id in (cs.arm.ARM_INS_STM, cs.arm.ARM_INS_STMIB)<EOL>after = insn_id in (cs.arm.ARM_INS_STM, cs.arm.ARM_INS_STMDA)<EOL>address = base.read()<EOL>for reg in regs:<EOL><INDENT>if not after:<EOL><INDENT>address += (<NUM_LIT:1> if increment else -<NUM_LIT:1>) * (reg.size // <NUM_LIT:8>)<EOL><DEDENT>cpu.write_int(address, reg.read(), reg.size)<EOL>if after:<EOL><INDENT>address += (<NUM_LIT:1> if increment else -<NUM_LIT:1>) * (reg.size // <NUM_LIT:8>)<EOL><DEDENT><DEDENT>if cpu.instruction.writeback:<EOL><INDENT>base.writeback(address)<EOL><DEDENT>
STM (Store Multiple) stores a non-empty subset (or possibly all) of the general-purpose registers to
sequential memory locations.

:param int insn_id: should be one of ARM_INS_STM, ARM_INS_STMIB, ARM_INS_STMDA, ARM_INS_STMDB
:param Armv7Operand base: Specifies the base register.
:param list[Armv7Operand] regs:
    Is a list of registers. It specifies the set of registers to be stored by the STM instruction.
    The registers are stored in sequence, the lowest-numbered register to the lowest
    memory address (start_address), through to the highest-numbered register to the
    highest memory address (end_address).