def _SR(cpu, insn_id, dest, op, *rest):
assert insn_id in (cs.arm.ARM_INS_ASR, cs.arm.ARM_INS_LSL, cs.arm.ARM_INS_LSR)<EOL>if insn_id == cs.arm.ARM_INS_ASR:<EOL><INDENT>if rest and rest[<NUM_LIT:0>].type == '<STR_LIT>':<EOL><INDENT>srtype = cs.arm.ARM_SFT_ASR<EOL><DEDENT>else:<EOL><INDENT>srtype = cs.arm.ARM_SFT_ASR_REG<EOL><DEDENT><DEDENT>elif insn_id == cs.arm.ARM_INS_LSL:<EOL><INDENT>if rest and rest[<NUM_LIT:0>].type == '<STR_LIT>':<EOL><INDENT>srtype = cs.arm.ARM_SFT_LSL<EOL><DEDENT>else:<EOL><INDENT>srtype = cs.arm.ARM_SFT_LSL_REG<EOL><DEDENT><DEDENT>elif insn_id == cs.arm.ARM_INS_LSR:<EOL><INDENT>if rest and rest[<NUM_LIT:0>].type == '<STR_LIT>':<EOL><INDENT>srtype = cs.arm.ARM_SFT_LSR<EOL><DEDENT>else:<EOL><INDENT>srtype = cs.arm.ARM_SFT_LSR_REG<EOL><DEDENT><DEDENT>carry = cpu.regfile.read('<STR_LIT>')<EOL>if rest and rest[<NUM_LIT:0>].type == '<STR_LIT>':<EOL><INDENT>result, carry = cpu._shift(op.read(), srtype, rest[<NUM_LIT:0>].op.reg, carry)<EOL><DEDENT>elif rest and rest[<NUM_LIT:0>].type == '<STR_LIT>':<EOL><INDENT>amount = rest[<NUM_LIT:0>].read()<EOL>result, carry = cpu._shift(op.read(), srtype, amount, carry)<EOL><DEDENT>elif cpu.mode == cs.CS_MODE_THUMB:<EOL><INDENT>result, carry = cpu._shift(dest.read(), srtype, op, carry)<EOL><DEDENT>else:<EOL><INDENT>result, carry = op.read(with_carry=True)<EOL><DEDENT>dest.write(result)<EOL>cpu.set_flags(N=HighBit(result), Z=(result == <NUM_LIT:0>), C=carry)<EOL>
Notes on Capstone behavior:
- In ARM mode, _SR reg has `rest`, but _SR imm does not, its baked into `op`.
- In ARM mode, `lsr r1, r2` will have a `rest[0]`
- In Thumb mode, `lsr r1, r2` will have an empty `rest`
- In ARM mode, something like `lsr r1, 3` will not have `rest` and op will be
    the immediate.