def prepare_attrib_mapping(self, primitive):
buffer_info = []<EOL>for name, accessor in primitive.attributes.items():<EOL><INDENT>info = VBOInfo(*accessor.info())<EOL>info.attributes.append((name, info.components))<EOL>if buffer_info and buffer_info[-<NUM_LIT:1>].buffer_view == info.buffer_view:<EOL><INDENT>if buffer_info[-<NUM_LIT:1>].interleaves(info):<EOL><INDENT>buffer_info[-<NUM_LIT:1>].merge(info)<EOL>continue<EOL><DEDENT><DEDENT>buffer_info.append(info)<EOL><DEDENT>return buffer_info<EOL>
Pre-parse buffer mappings for each VBO to detect interleaved data for a primitive