@classmethod<EOL><INDENT>def hardcodeRomIntoProcess(cls, rom):<DEDENT>
processes = []<EOL>signals = []<EOL>for e in rom.endpoints:<EOL><INDENT>assert isinstance(e, Operator) and e.operator == AllOps.INDEX, e<EOL>me, index = e.operands<EOL>assert me is rom<EOL>romValSig = rom.ctx.sig(rom.name, dtype=e.result._dtype)<EOL>signals.append(romValSig)<EOL>romValSig.hidden = False<EOL>cases = [(toHVal(i), [romValSig(v), ])<EOL>for i, v in enumerate(rom.defVal.val)]<EOL>statements = [SwitchContainer(index, cases), ]<EOL>for (_, (stm, )) in cases:<EOL><INDENT>stm.parentStm = statements[<NUM_LIT:0>] <EOL><DEDENT>p = HWProcess(rom.name, statements, {index, },<EOL>{index, }, {romValSig, })<EOL>processes.append(p)<EOL>def replaceOrigRomIndexExpr(x):<EOL><INDENT>if x is e.result:<EOL><INDENT>return romValSig<EOL><DEDENT>else:<EOL><INDENT>return x<EOL><DEDENT><DEDENT>for _e in e.result.endpoints:<EOL><INDENT>_e.operands = tuple(map(replaceOrigRomIndexExpr, _e.operands))<EOL>e.result = romValSig<EOL><DEDENT><DEDENT>return processes, signals<EOL>
Due to verilog restrictions it is not posible to use array constants
and rom memories has to be hardcoded as process