def substitute_node_with_dag(self, node, input_dag, wires=None):
if isinstance(node, int):<EOL><INDENT>warnings.warn('<STR_LIT>'<EOL>'<STR_LIT>',<EOL>DeprecationWarning, <NUM_LIT:2>)<EOL>node = self._id_to_node[node]<EOL><DEDENT>condition = node.condition<EOL>if condition:<EOL><INDENT>input_dag.add_creg(condition[<NUM_LIT:0>])<EOL>to_replay = []<EOL>for sorted_node in input_dag.topological_nodes():<EOL><INDENT>if sorted_node.type == "<STR_LIT>":<EOL><INDENT>sorted_node.op.control = condition<EOL>to_replay.append(sorted_node)<EOL><DEDENT><DEDENT>for input_node in input_dag.op_nodes():<EOL><INDENT>input_dag.remove_op_node(input_node)<EOL><DEDENT>for replay_node in to_replay:<EOL><INDENT>input_dag.apply_operation_back(replay_node.op, replay_node.qargs,<EOL>replay_node.cargs, condition=condition)<EOL><DEDENT><DEDENT>if wires is None:<EOL><INDENT>qwires = [w for w in input_dag.wires if isinstance(w[<NUM_LIT:0>], QuantumRegister)]<EOL>cwires = [w for w in input_dag.wires if isinstance(w[<NUM_LIT:0>], ClassicalRegister)]<EOL>wires = qwires + cwires<EOL><DEDENT>self._check_wires_list(wires, node)<EOL>proxy_map = {w: QuantumRegister(<NUM_LIT:1>, '<STR_LIT>') for w in wires}<EOL>add_qregs = self._check_edgemap_registers(proxy_map,<EOL>input_dag.qregs,<EOL>{}, False)<EOL>for qreg in add_qregs:<EOL><INDENT>self.add_qreg(qreg)<EOL><DEDENT>add_cregs = self._check_edgemap_registers(proxy_map,<EOL>input_dag.cregs,<EOL>{}, False)<EOL>for creg in add_cregs:<EOL><INDENT>self.add_creg(creg)<EOL><DEDENT>if node.type != "<STR_LIT>":<EOL><INDENT>raise DAGCircuitError("<STR_LIT>"<EOL>% node.type)<EOL><DEDENT>condition_bit_list = self._bits_in_condition(node.condition)<EOL>wire_map = {k: v for k, v in zip(wires,<EOL>[i for s in [node.qargs,<EOL>node.cargs,<EOL>condition_bit_list]<EOL>for i in s])}<EOL>self._check_wiremap_validity(wire_map, wires, self.input_map)<EOL>pred_map, succ_map = self._make_pred_succ_maps(node)<EOL>full_pred_map, full_succ_map = self._full_pred_succ_maps(pred_map, succ_map,<EOL>input_dag, wire_map)<EOL>self._multi_graph.remove_node(node)<EOL>for sorted_node in input_dag.topological_op_nodes():<EOL><INDENT>condition = self._map_condition(wire_map, sorted_node.condition)<EOL>m_qargs = list(map(lambda x: wire_map.get(x, x),<EOL>sorted_node.qargs))<EOL>m_cargs = list(map(lambda x: wire_map.get(x, x),<EOL>sorted_node.cargs))<EOL>self._add_op_node(sorted_node.op, m_qargs, m_cargs, condition)<EOL>all_cbits = self._bits_in_condition(condition)<EOL>all_cbits.extend(m_cargs)<EOL>al = [m_qargs, all_cbits]<EOL>for q in itertools.chain(*al):<EOL><INDENT>self._multi_graph.add_edge(full_pred_map[q],<EOL>self._id_to_node[self._max_node_id],<EOL>name="<STR_LIT>" % (q[<NUM_LIT:0>].name, q[<NUM_LIT:1>]),<EOL>wire=q)<EOL>full_pred_map[q] = self._id_to_node[self._max_node_id]<EOL><DEDENT><DEDENT>for w in full_pred_map:<EOL><INDENT>self._multi_graph.add_edge(full_pred_map[w],<EOL>full_succ_map[w],<EOL>name="<STR_LIT>" % (w[<NUM_LIT:0>].name, w[<NUM_LIT:1>]),<EOL>wire=w)<EOL>o_pred = list(self._multi_graph.predecessors(self.output_map[w]))<EOL>if len(o_pred) > <NUM_LIT:1>:<EOL><INDENT>if len(o_pred) != <NUM_LIT:2>:<EOL><INDENT>raise DAGCircuitError("<STR_LIT>")<EOL><DEDENT>p = [x for x in o_pred if x != full_pred_map[w]]<EOL>if len(p) != <NUM_LIT:1>:<EOL><INDENT>raise DAGCircuitError("<STR_LIT>")<EOL><DEDENT>self._multi_graph.remove_edge(p[<NUM_LIT:0>], self.output_map[w])<EOL><DEDENT><DEDENT>
Replace one node with dag.

        Args:
            node (DAGNode): node to substitute
            input_dag (DAGCircuit): circuit that will substitute the node
            wires (list[(Register, index)]): gives an order for (qu)bits
                in the input circuit. This order gets matched to the node wires
                by qargs first, then cargs, then conditions.

        Raises:
            DAGCircuitError: if met with unexpected predecessor/successors