def registerMUX(self, stm: Union[HdlStatement, Operator], sig: RtlSignal,<EOL>inputs_cnt: int):
assert inputs_cnt > <NUM_LIT:1><EOL>res = self.resources<EOL>w = sig._dtype.bit_length()<EOL>k = (ResourceMUX, w, inputs_cnt)<EOL>res[k] = res.get(k, <NUM_LIT:0>) + <NUM_LIT:1><EOL>self.resource_for_object[(stm, sig)] = k<EOL>
mux record is in format (self.MUX, n, m)
where n is number of bits of this mux
and m is number of possible inputs