def serial_layers(self):
for next_node in self.topological_op_nodes():<EOL><INDENT>new_layer = DAGCircuit()<EOL>for qreg in self.qregs.values():<EOL><INDENT>new_layer.add_qreg(qreg)<EOL><DEDENT>for creg in self.cregs.values():<EOL><INDENT>new_layer.add_creg(creg)<EOL><DEDENT>support_list = []<EOL>op = copy.copy(next_node.op)<EOL>qa = copy.copy(next_node.qargs)<EOL>ca = copy.copy(next_node.cargs)<EOL>co = copy.copy(next_node.condition)<EOL>_ = self._bits_in_condition(co)<EOL>new_layer.apply_operation_back(op, qa, ca, co)<EOL>if next_node.name not in ["<STR_LIT>",<EOL>"<STR_LIT>", "<STR_LIT>", "<STR_LIT>", "<STR_LIT>"]:<EOL><INDENT>support_list.append(list(qa))<EOL><DEDENT>l_dict = {"<STR_LIT>": new_layer, "<STR_LIT>": support_list}<EOL>yield l_dict<EOL><DEDENT>
Yield a layer for all gates of this circuit.

        A serial layer is a circuit with one gate. The layers have the
        same structure as in layers().