A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.
This application is related to the following co-pending, commonly assigned U.S. patent applications: “DEAPROM HAVING AMORPHOUS SILICON CARBIDE GATE INSULATOR,” Ser. No. 08/902,843, “DEAPROM AND TRANSISTOR WITH GALLIUM NITRIDE OR GALLIUM ALUMINUM NITRIDE GATE,” Ser. No. 08/902,098, “CARBURIZED SILICON GATE INSULATORS FOR INTEGRATED CIRCUITS,” Ser. No. 08/903,453, “SILICON CARBIDE GATE TRANSISTOR AND FABRICATION PROCESS,” Ser. No. 08/903,486, “TRANSISTOR WITH VARIABLE ELECTRON AFFINITY GATE AND METHODS OF FABRICATION AND USE,” Ser. No. 08/903,452, and “TRANSISTOR WITH SILICON OXYCARBIDE GATE AND METHODS OF FABRICATION AND USE,” Ser. No. 08/902,132, each of which is filed on the same day as U.S. application Ser. No. 08/902,133, filed on 29 Jul. 1997, and each of which disclosure is herein incorporated by reference.
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The memory cell of the present invention, having a barrier energy between the floating electrode and the insulator that is lower than the barrier energy between polysilicon and SiO 2, provides large transconductance gain, an easily detected signal, and reduces the required data storage capacitance value and memory cell size. The lower barrier energy increases tunneling current and also advantageously reduces the voltage required for writing and erasing the floating gate transistor memory cells. For example, conventional polysilicon floating gate transistors typically require complicated and noisy on-chip charge pump circuits to generate the large erasure voltage, which typically far exceeds other voltages required on the integrated circuit. The present invention allows the use of lower erasure voltages that are more easily provided by simpler on-chip circuits. Reducing the erasure voltage also lowers the electric fields, minimizing reliability problems that can lead to device failure, and better accommodating downward scaling of device dimensions. Alternatively, the thickness of the gate insulator can be increased from the typical thickness of a silicon dioxide gate insulator to improve reliability or simplify processing, since the lower barrier energy allows easier transport of charge across the gate insulator by Fowler-Nordheim tunneling.
FIG. 5 is a graph that illustrates generally the relationship between Fowler-Nordheim tunneling current density vs. the barrier energy Φ GI at various parameterized values E1<E2<E3 of an electric field.
The present invention discloses a memory cell such as, for example, a dynamic electrically alterable programmable read only memory (DEAPROM) cell. The memory cell has a floating electrode, which is defined as an electrode that is “electrically isolated” from conductors and semiconductors by an insulator such that charge storage upon and removal from the floating electrode depends upon charge conduction through the insulator. In one embodiment, described below, the floating electrode is a floating gate electrode in a floating gate field-effect transistor, such as used in flash electrically erasable and programmable read only memories (EEPROMs). However, a capacitor or any other structure having a floating electrode and adjacent insulator could also be used according to the techniques of the present invention described below. According to one aspect of the present invention, a barrier energy between the floating electrode and the insulator is lower than the barrier energy between polycrystalline silicon (polysilicon) and silicon dioxide (SiO 2), which is approximately 3.3 eV. According to another aspect of the present invention, the shorter retention time of data charges on the floating electrode, resulting from the smaller barrier energy, is accommodated by refreshing the data charges on the floating electrode. In this respect, the memory operates similar to a memory cell in a dynamic random access memory (DRAM). These and other aspects of the present invention are described in more detail below.
FIG. 1 is a simplified schematic/block diagram illustrating generally one embodiment of a memory  100 according to one aspect of the present invention, in which reduced barrier energy floating electrode memory cells are incorporated. Memory 100 is referred to as a dynamic electrically alterable programmable read only memory (DEAPROM) in this application, but it is understood that memory 100 possesses certain characteristics that are similar to DRAMs and flash EEPROMs, as explained below. For a general description of how a flash EEPROM operates, see B. Dipert et al., “Flash Memory Goes Mainstream,” IEEE Spectrum, pp. 48-52 (October 1993), which is incorporated herein by reference. Memory 100 includes a memory array 105 of multiple memory cells 110. Row decoder 115 and column decoder 120 decode addresses provided on address lines 125 to access the addressed memory cells in memory array 105. Command and control circuitry 130 controls the operation of memory 100 in response to control signals received on control lines 135 from a processor 140 or other memory controller during read, write, refresh, and erase operations. Command and control circuitry 130 includes a refresh circuit for periodically refreshing the data stored on floating gate transistor or other floating electrode memory cells 110. Voltage control 150 provides appropriate voltages to the memory cells during read, write, refresh, and erase operations. Memory 100, as illustrated in FIG. 1, has been simplified for the purpose of illustrating the present invention and is not intended to be a complete description. Only the substantial differences between DEAPROM memory 100 and conventional DRAM and flash EEPROM memories are discussed below.
FIG. 2 is a cross-sectional view that illustrates generally, by way of example, but not by way of limitation, one floating gate transistor embodiment of a memory cell  110. Other structural arrangements of floating gate transistors are included within the present invention. Also included are any memory cells that incorporate a floating electrode (such as a floating electrode capacitor) having, at an interface between the floating electrode an adjacent insulator, a barrier energy that is less than the barrier energy at a polysilicon-SiO2 interface. In the embodiment of FIG. 2, memory cell 110 includes a floating gate FET 200, which is illustrated as an n-channel FET, but understood to include a p-channel FET embodiment as well.
FET  200 includes a source 205, a drain 210, a floating gate 215 electrode, and a control gate 220 electrode. A gate insulator 225 is interposed between floating gate 215 and substrate 230. An intergate insulator 235 is interposed between floating gate 215 and control gate 220. In one embodiment, substrate 230 is a bulk semiconductor, such as silicon. In another embodiment, substrate 230 includes a thin semiconductor surface layer formed on an underlying insulating portion, such as in a semiconductor-on-insulator (SOI) or other thin film transistor technology. Source 205 and drain 210 are formed by conventional complementary metal-oxide-semiconductor (CMOS) processing techniques. Source 205 and drain 210 are separated by a predetermined length for forming an inversion channel 240 therebetween.
FIG. 3 is an energy band diagram that illustrates generally the conduction band energy levels in floating gate  215, gate insulator 225, and substrate 230. Electron affinities χ215, χ225, and χ230 describe floating gate 215, gate insulator 225, and substrate 230, respectively, when measured with respect to a vacuum level 300. A barrier energy ΦGI, which describes the barrier energy at the interface between floating gate 215 and gate insulator 225, is given by a difference in electron affinities, as illustrated in Equation 1.
A barrier energy Φ GI which describes the barrier energy at the interface between substrate 230 and gate insulator 225, is given by a difference in electron affinities, as illustrated in Equation 2.
Silicon (monocrystalline or polycrystalline Si) has an electron affinity χ 215≈4.2 eV. Silicon dioxide (SiO2) has an electron affinity, χ225, of about 0.9 eV. The resulting barrier energy at a conventional Si-SiO2 interface between a floating gate and a gate insulator is approximately equal to 3.3 eV. One aspect of the present invention provides a barrier energy ΦGI that is less than the 3.3 eV barrier energy of a conventional Si-SiO2 interface.
According to one aspect of the invention, the interface between floating gate  215 and gate insulator 225 provides a smaller barrier energy ΦGI than the 3.3 eV barrier energy at an interface between polysilicon and silicon dioxide, such as by an appropriate selection of the material composition of one or both of floating gate 215 and gate insulator 225. In one embodiment, the smaller barrier energy ΦGI is obtained by forming floating gate 215 from a material having a smaller electron affinity χ215 than polysilicon. In one embodiment, for example, polycrystalline or microcrystalline silicon carbide (SiC) is used as the material for forming floating gate 215. In another embodiment, the smaller barrier energy ΦGI is obtained by forming gate insulator 225 from a material having a higher electron affinity χ225 than SiO2. In one embodiment, for example, amorphous SiC is used as the material for forming gate insulator 225. In yet another embodiment, the smaller barrier energy ΦGI is obtained by a combination of forming floating gate 215 from a material having a smaller electron affinity χ215 than polysilicon and also forming gate insulator 225 from a material having a higher electron affinity χ225 than SiO2.
The smaller barrier energy Φ GI provides current conduction across gate insulator 225 that is easier than for a polysilicon-SiO2 interface. The present invention includes any mechanism of providing such easier current conduction across gate insulator 225, including, but not limited to “hot” electron injection, thermionic emission, Schottky emission, Frenkel-Poole emission, and Fowler-Nordheim tunneling. Such techniques for transporting charge carriers across an insulator, such as gate insulator 225, are all enhanced by providing a smaller barrier energy ΦGI according to the techniques of the present invention. These techniques allow increased current conduction, current conduction at lower voltages across gate insulator 225 and lower electric fields in gate insulator 225, shorter data write and erase times, use of a thicker and more reliable gate insulator 225, and other advantages explained below.
FIG. 4 is a graph illustrating generally barrier energy versus tunneling distance for a conventional polysilicon-SiO 2 interface having a 3.3 eV barrier energy. FIG. 4 also illustrates barrier energy versus tunneling distance for an interface according to the present invention that has a barrier energy of ΦGI≈1.08 eV, which is selected as an illustrative example, and not by way of limitation. The smaller barrier energy ΦGI reduces the energy to which the electrons must be excited to be stored on or removed from the floating gate 215, such as by thermal emission over the barrier. The smaller barrier energy ΦGI also reduces the distance that electrons have to traverse, such as by Fowler-Nordheim tunneling, to be stored upon or removed from floating gate 215. In FIG. 4, “do” represents the tunneling distance of a conventional floating gate transistor due to the 3.3 eV barrier energy represented by the dashed line “OLD”. The tunneling distance “dn” corresponds to a floating gate transistor according to the present invention and its smaller barrier energy, such as ΦGI≈1.08 eV, for example, represented by the dashed line “NEW”. Even a small reduction in the tunneling distance results in a large increase in the tunneling probability, as described below, because the tunneling probability is an exponential function of the reciprocal of the tunneling distance.
For a conventional floating gate FET having a 3.3 eV barrier energy at the interface between the polysilicon floating gate and the SiO 2 gate insulator, A=5.5×10−16 amperes/Volt2 and B=7.07×107 Volts/cm. One aspect of the present invention includes selecting a smaller barrier energy ΦGI such as, by way of example, but not by way of limitation, ΦGI∓1.08 eV. The constants A and B for ΦGI≈1.08 eV can be extrapolated from the constants A and B for the 3.3 eV polysilicon-SiO2 barrier energy using Equations 4 and 5. The barrier energy ΦGI≈1.08 eV yields the resulting constants A=1.76×10−15 amperes/Volt2 and B=1.24×107 Volts/cm.
FIG. 5 is a graph that illustrates generally the relationship between Fowler-Nordheim tunneling current density vs. the barrier energy  GI, such as at various parameterized values E1<E2<E3 of an electric field in gate insulator 225. The tunneling current density increases as electric field is increased. The tunneling current also increases by orders of magnitude as the barrier energy ΦGI is decreased, such as by selecting the materials for floating gate 215 and gate insulator 225 or otherwise reducing the barrier energy ΦGI according to the techniques of the present invention. In particular, FIG. 5 illustrates a comparison between tunneling current densities at the 3.3 eV barrier energy of a conventional polysilicon-SiO2 interface and at the illustrative example barrier energy ΦGI≈1.08 eV for which constants A and B were extrapolated above. Reducing the 3.3 eV barrier energy to ΦGI≈1.08 eV increases the tunneling current density by several orders of magnitude.
FIG. 6 is a conceptual diagram, using rough order of magnitude estimates, that illustrates generally how the barrier energy affects the time needed to perform write and erase operations by Fowler-Nordheim tunneling for a particular voltage, such as across gate insulator  225. FIG. 6 also illustrates how the barrier energy affects data charge retention time, such as on floating gate 215 at a temperature of 250 degrees Celsius. Both write and erase time 600 and data charge retention time 605 are decreased by orders of magnitude as the barrier energy is decreased, according to the present invention, from the conventional polysilicon-SiO2 interface barrier energy of 3.3 eV to the illustrative example lower barrier energy ΦGI≈1.08 eV for which constants A and B were extrapolated above.
In Equations 7 and 8, V 220 is the voltage on control gate 220, E225 and E235 are the respective electric fields in gate insulator 225 and intergate insulator 235, d225 and d235 are the respective thicknesses of gate insulator 225 and intergate insulator 235, and ε225 and ε235 are the respective permittivities of gate insulator 225 and intergate insulator 235.
FIG. 7 is a graph that illustrates generally charge density vs. write/erase time for three different embodiments of the floating gate FET  200, each of which have a polysilicon floating gate 215, by way of illustrative example. Line 700 illustrates generally, by way of example, but not by way of limitation, the charge density vs. write/erase time obtained for a floating gate FET 200 having a 100 Å SiO2 gate insulator 225 and a 150 Å SiO2 (or thinner oxynitride equivalent capacitance) intergate insulator 235.
Line  705 is similar to line 700 in all respects except that line 705 illustrates a floating gate FET 200 in which gate insulator 225 comprises a material having a higher electron affinity χ225 than SiO2, thereby providing a lower barrier energy ΦGI at the interface between polysilicon floating gate 215 and gate insulator 225. The increased tunneling current results in shorter write/erase times than those illustrated by line 700.
Line  710 is similar to line 705 in all respects except that line 710 illustrates a floating gate FET 200 in which gate insulator 225 has a lower barrier energy ΦGI than for line 705, or intergate insulator 235 has a higher permittivity ε235 than for line 705, or control gate 220 has a larger area than floating gate 215, such as illustrated by way of example by the floating gate FET 800 in the cross-sectional view of FIG. 8. As seen in FIG. 8, the area of a capacitor formed by the control gate 220, the floating gate 215, and the intergate insulator 235 is larger than the area of a capacitor formed by the floating gate 215, the gate insulator 225, and the inversion channel 240 underlying gate insulator 225. Alternatively, or in combination with the techniques illustrated in FIG. 8, the intergate insulator 235 can have a higher permittivity than the permittivity of silicon dioxide.
As illustrated in FIG. 7, the barrier energy Φ GI can be selected to reduce the write/erase time. In one embodiment, by way of example, but not by way of limitation, the barrier energy ΦGI is selected to obtain a write/erase time of less than or equal to 1 second, as illustrated in FIG. 7. In another embodiment, by way of example, but not by way of limitation, the barrier energy ΦGI is selected to obtain a write/erase time of less than or equal to 1 millisecond, as illustrated in FIG. 7. Other values of write/erase time can also be obtained by selecting the appropriate value of the barrier energy ΦGI.
The lower barrier energy Φ GI and increased tunneling current also advantageously reduces the voltage required for writing and erasing the floating gate transistor memory cells 110. For example, conventional polysilicon floating gate transistors typically require complicated and noisy on-chip charge pump circuits to generate the large erasure voltage, which typically far exceeds other voltages required on the integrated circuit. The present invention allows the use of lower erasure voltages that are more easily provided by simpler on-chip circuits. Reducing the erasure voltage also lowers the electric fields, minimizing reliability problems that can lead to device failure, and better accommodating downward scaling of device dimensions. In one embodiment, the barrier energy ΦGI is selected, as described above, to obtain an erase voltage of less than the 12 Volts required by typical EEPROM memory cells.
Alternatively, the thickness of the gate insulator  225 can be increased from the typical thickness of a silicon dioxide gate insulator to improve reliability or simplify processing, since the lower barrier energy ΦGI allows easier transport of charge across the gate insulator 225 by Fowler-Nordheim tunneling.
The lower barrier energy Φ GI also decreases the data charge retention time of the charge stored on the floating gate 215, such as from increased thermal excitation of stored charge over the lower barrier ΦGI. However, conventional polysilicon floating gates and adjacent SiO2 insulators (e.g., 90 Å thick) have a data charge retention time estimated in the millions of years at a temperature of 85 degrees C., and estimated in the 1000 hour range even at extremely high temperatures such as 250 degrees C. Since such long data charge retention times are longer than what is realistically needed, a shorter data charge retention time can be accommodated in order to obtain the benefits of the smaller barrier energy ΦGI. In one embodiment of the present invention, by way of example, but not by way of limitation, the barrier energy ΦGI is lowered to ΦGI≈1.08 eV by appropriately selecting the composition of the materials of floating gate 215 and gate insulator 225, as described below. As a result, an estimated data charge retention time of approximately 40 seconds at a high temperature, such as 250 degrees C., is obtained.
According to one aspect of the present invention, the data stored on the DEAPROM floating gate memory cell  110 is periodically refreshed at an interval that is shorter than the data charge retention time. In one embodiment, for example, the data is refreshed every few seconds, such as for an embodiment having a high temperature retention time of approximately 40 seconds for ΦGI≈1.08 eV. The exact refresh rate can be experimentally determined and tailored to a particular process of fabricating the DEAPROM. By decreasing the data charge retention time and periodically refreshing the data, the write and erase operations can be several orders of magnitude faster, as described above with respect to FIG. 7.
FIGS. 9A and 9B are schematic diagrams that respectively illustrate generally a conventional DRAM memory cell and the present invention's floating gate FET  200 embodiment of memory cell 110. In FIG. 9A, the DRAM memory cell includes an access FET 900 and stacked or trench storage capacitor 905. Data is stored as charge on storage capacitor 905 by providing a control voltage on control line 910 to activate FET 900 for conducting charge. Data line 915 provides a write voltage to conduct charge across FET 900 for storage on storage capacitor 905. Data is read by providing a control voltage on control line 910 to activate FET 900 for conducting charge from storage capacitor 905, thereby incrementally changing a preinitialized voltage on data line 915. The resulting small change in voltage on data line 915 must be amplified by a sense amplifier for detection. Thus, the DRAM memory cell of FIG. 9A inherently provides only a small data signal. The small data signal is difficult to detect.
In FIG. 9B, the DEAPROM memory cell  110 according to the present invention includes floating gate FET 200, having source 205 coupled to a ground voltage or other reference potential. Data is stored as charge on floating gate 215 by providing a control voltage on control line 920 and a write voltage on data line 925 for hot electron injection or Fowler-Nordheim tunneling. This is similar to conventional EEPROM techniques, but advantageously uses the reduced voltages and/or a shorter write time of the present invention.
The DEAPROM memory cell  110 can be smaller than the DRAM memory cell of FIG. 9A, allowing higher density data storage. The leakage of charge from floating gate 215 can be made less than the reverse-bias junction leakage from storage capacitor 905 of the DRAM memory cell by tailoring the barrier energy ΦGI according to the techniques of the present invention. Also, the DEAPROM memory cell advantageously uses the large transconductance gain of the floating gate FET 200. The conventional DRAM memory cell of FIG. 9A provides no such gain; it is read by directly transferring the data charge from storage capacitor 905. By contrast, the DEAPROM memory cell 110 is read by placing a read voltage on control line 920, and detecting the current conducted through FET 200, such as at data line 925. The current conducted through FET 200 changes significantly in the presence or absence of charge stored on floating gate 215. Thus, the present invention advantageously provides an large data signal that is easy to detect, unlike the small data signal provided by the conventional DRAM memory cell of FIG. 9A.
In Equation 9, I DS is the current between drain 210 and source 205, CO is the capacitance per unit area of the gate insulator 225, W/L is the width/length aspect ratio of FET 200, VG is the gate voltage applied to control gate 220, and VT is the turn-on threshold voltage of FET 200.
For an illustrative example, but not by way of limitation, a minimum-sized FET having W/L=1, can yield a transconductance gain of approximately 71 μA/Volt for a typical process. In this illustrative example, sufficient charge is stored on floating gate  215 to change the effective threshold voltage VT by approximately 1.4 Volts, thereby changing the current IDS by approximately 100 microamperes. This significant change in current can easily be detected, such as by sampling or integrating over a time period of approximately 10 nanoseconds, for example, to obtain a detected data charge signal of 1000 fC. Thus, the DEAPROM memory cell 110 is capable of yielding a detected data charge signal that is approximately an order of magnitude larger than the typical 30 fC to 100 fC data charges typically stored on DRAM stacked or trench capacitors. Since DEAPROM memory cell 110 requires a smaller capacitance value than a conventional DRAM memory cell, DEAPROM memory cell 110 can be made smaller than a conventional DRAM memory cell. Moreover, because the CMOS-compatible DEAPROM storage capacitor is integrally formed as part of the transistor, rather than requiring complex and costly non-CMOS stacked and trench capacitor process steps, the DEAPROM memory of the present invention should be cheaper to fabricate than DRAM memory cells, and should more easily scale downward as CMOS technology advances.
In one embodiment, the present invention provides a DEAPROM having a storage element including a gate insulator  225 that includes an amorphous silicon carbide (a-SiC). For example, one embodiment of a memory storage element having an a-SiC gate insulator 225 is described in Forbes et al. U.S. patent application Ser. No. 08/903,453, entitled CARBURIZED SILICON GATE INSULATORS FOR INTEGRATED CIRCUITS, filed on the same day as the present patent application, and which disclosure is herein incorporated by reference. The a-SiC inclusive gate insulator 225 provides a higher electron affinity χ225 than the approximately 0.9 eV electron affinity of SiO2. For example, but not by way of limitation, the a-SiC inclusive gate insulator 225 can provide an electron affinity χ225≈3.24 eV.
An a-SiC inclusive gate insulator  225 can also be formed using other techniques. For example, in one embodiment gate insulator 225 includes a hydrogenated a-SiC material synthesized by ion-implantation of C2H2 into a silicon substrate 230. In another embodiment, gate insulator 225 includes an a-SiC film that is deposited by laser ablation at room temperature using a pulsed laser in an ultrahigh vacuum or nitrogen environment. In another embodiment, gate insulator 225 includes an a-SiC film that is formed by low-energy ion-beam assisted deposition to minimize structural defects and provide better electrical characteristics in the semiconductor substrate 230. The ion beam can be generated by electron cyclotron resonance from an ultra high purity argon (Ar) plasma. In another embodiment, gate insulator 225 includes an a-SiC film that is synthesized at low temperature by ion beam sputtering in a reactive gas environment with concurrent ion irradiation. According to one technique, more than one ion beam, such as an Ar ion beam, are used. A first Ar ion beam is directed at a Si target material to provide a Si flux for forming SiC gate insulator 225. A second Ar ion beam is directed at a graphite target to provide a C flux for forming SiC gate insulator 225. The resulting a-SiC gate insulator 225 is formed by sputtering on substrate 230. In another embodiment, gate insulator 225 includes an SiC film that is deposited on substrate 230 by DC magnetron sputtering at room temperature using a conductive, dense ceramic target. In another embodiment, gate insulator 225 includes a thin a-Si1-xCx:H film that is formed by HF plasma ion sputtering of a fused SiC target in an Ar-H atmosphere. In another embodiment, radio frequency (RF) sputtering is used to produce a-SiC films. Bandgaps of a-Si, a-SiC, a-Si:H, and a-SiC:H have been found to be 1.22 eV, 1.52 eV, 1.87 eV, and 2.2 eV respectively.
In another embodiment, gate insulator  225 is formed by chemical vapor deposition (CVD) and includes an a-SiC material. According to one technique, gate insulator 225 includes a-Si1-xCx:H deposited by plasma enhanced chemical vapor deposition (PECVD). According to another technique, mixed gases of silane and methane can be used to form a-Si1-xCx:H gate insulator 225. For example, the source gas can include silane in methane with additional dilution in hydrogen. In another embodiment, gate insulator 225 includes a clean a-Si1-xCx material formed by hot-filament assisted CVD. In another embodiment, gate insulator 225 includes a-SiC formed on a crystalline Si substrate 230 by inductively coupled plasma CVD, such as at 450 degrees Celsius, which can yield a-SiC rather than epitaxially grown polycrystalline or microcrystalline SiC. The resulting a-SiC inclusive gate insulator 225 can provide an electron affinity χ225≈3.24 eV, which is significantly larger than the 0.9 eV electron affinity obtainable from a conventional SiO2 gate insulator.
Gate insulator  225 can be etched by RF plasma etching using CF4O2 in SF6O2. Self-aligned source 205 and drain 210 can then be formed using conventional techniques for forming a FET 200 having a floating (electrically isolated) gate 215, or in an alternate embodiment, an electrically interconnected (driven) gate.
In one embodiment, the present invention provides a DEAPROM having a memory cell  110 that includes a FET 200 having an at least partially crystalline (e.g., monocrystalline, polycrystalline, microcrystalline, nanocrystalline, or combination thereof) SiC floating gate 215. For example, one embodiment of a memory cell 110 that includes a memory storage element having a polycrystalline or microcrystalline SiC floating gate 215 is described in Forbes et al. U.S. patent application Ser. No. 08/903,486, entitled SILICON CARBIDE GATE TRANSISTOR AND FABRICATION PROCESS, filed on the same day as the present patent application, and which disclosure is herein incorporated by reference. The SiC floating gate 215 provides a lower electron affinity χ215≈3.7 to 3.8 eV and smaller resulting barrier energy ΦGI than a polysilicon gate material having an electron affinity χ215≈4.2 eV. For example, using a SiO2 gate insulator 225, a barrier energy ΦGI≈2.6 to 2.7 eV is obtained using an SiC floating gate 215, as compared to a barrier energy ΦGI≈3.3 eV for a conventional polysilicon floating gate material at an interface with an SiO2 gate insulator 225.
According to one aspect of the invention, floating gate  215 is formed from a silicon carbide compound Si1-xCx, in which the material composition x is varied. One embodiment of a memory storage element having a variable SiC composition floating gate 215 is described in Forbes et al. U.S. patent application Ser. No. 08/903,452, entitled TRANSISTOR WITH VARIABLE ELECTRON AFFINITY GATE AND METHODS OF FABRICATION AND USE, filed on the same day as the present patent application, and which disclosure is herein incorporated by reference. For example, but not by way of limitation, an SiC composition of about 0.75<x<1.0 yields an electron affinity of approximately between 1.7 eV<χ215<−0.4 eV. For an SiO2 gate insulator 225, a barrier 0.8 eV<ΦGI<−1.3 eV is obtained. In one such embodiment, floating gate FET 200 provides a data charge retention time on the order of seconds.
In one embodiment, floating gate  215 is formed by CVD of polycrystalline or microcrystalline SiC, which can be either in situ conductively doped during deposition, or conductively doped during a subsequent ion-implantation step. According to one aspect of the invention, for example, floating gate 215 is formed of an SiC film that is deposited using low-pressure chemical vapor deposition (LPCVD). The LPCVD process uses either a hot-wall reactor or a cold-wall reactor with a reactive gas, such as a mixture of Si(CH3)4 and Ar. Examples of such processes have been disclosed. In other embodiments, floating gate 215 is formed of an SiC film that is deposited using other techniques such as, for example, enhanced CVD techniques known to those skilled in the art including low pressure rapid thermal chemical vapor deposition (LP-RTCVD), or by decomposition of hexamethyl disalene using ArF excimer laser irradiation, or by low temperature molecular beam epitaxy (MBE). Other examples of forming SiC film floating gate 215 include reactive magnetron sputtering, DC plasma discharge, ion-beam assisted deposition, ion-beam synthesis of amorphous SiC films, laser crystallization of amorphous SiC, laser reactive ablation deposition, and epitaxial growth by vacuum anneal. The conductivity of the SiC film of floating gate 215 can be changed by ion implantation during subsequent process steps, such as during the self-aligned formation of source/drain regions for the n-channel and p-channel FETs.
In one embodiment, patterning and etching the SiC film, together with the underlying gate insulator  225, forms the resulting individual SiC floating gates 215. The SiC film is patterned using standard techniques and is etched using plasma etching, reactive ion etching (RIE) or a combination of these or other suitable methods. For example, the SiC film can be etched by RIE in a distributed cyclotron resonance reactor using a SF6/O2 gas mixture using SiO2 as a mask with a selectivity of 6.5. Such process is known in the art and is disclosed. Alternatively, the SiC film can be etched by RIE using the mixture SF6 and O2 and F2/Ar/O2. An example of such a process has been disclosed. The etch rate of the SiC film can be significantly increased by using magnetron enhanced RIE. Self-aligned source 205 and drain 210 regions can then be formed using conventional techniques for forming a FET 200 having a floating (electrically isolated) gate 215, or in an alternate embodiment, an electrically interconnected (driven) gate.
In one embodiment, the present invention provides a DEAPROM having a memory cell  110 that includes a FET 200 having an at least partially crystalline (e.g., monocrystalline, polycrystalline, microcrystalline, or nanocrystalline) silicon oxycarbide (SiOC) floating gate 215. For example, one embodiment of a memory cell 110 that includes a storage element having a polycrystalline or microcrystalline SiOC floating gate 215 is described in Forbes et al. U.S. patent application Ser. No. 08/902,132, entitled TRANSISTOR WITH SILICON OXYCARBIDE GATE AND METHODS OF FABRICATION AND USE, filed on the same day as the present patent application, and which disclosure is herein incorporated by reference.
In one embodiment, a material composition w of the SiO ( 2-2w)Cw floating gate 215 is selected such that floating gate 215 provides a lower electron affinity approximately between 0.9 eV<χ215<3.7 eV and smaller resulting barrier energy ΦGI than a polysilicon gate material having an electron affinity χ215≈4.2 eV. For example, using a SiO2 gate insulator 225, a barrier energy approximately between 0 eV<ΦGI<2.8 eV is obtained for an SiOC floating gate 215 as the SiOC composition w varies between w≈1 (i.e., approximately SiC) and w≈0 (i.e., approximately SiO2). By contrast, a conventional polysilicon floating gate material provides a barrier energy ΦGI≈3.3 eV at an interface with an SiO2 gate insulator 225.
In one embodiment floating gate  215 is formed of a monocrystalline, polycrystalline, microcrystalline, or nanocrystalline, SiOC thin film that is CVD deposited, such as by a Two Consecutive Decomposition and Deposition Chamber (TCDDC) system. One such example of depositing microcrystalline SiOC is disclosed in the unrelated technological field of solar cell applications.
In other embodiments, the SiOC film is deposited using other techniques such as, for example, low pressure chemical vapor deposition (LPCVD), or enhanced CVD techniques known to those skilled in the art including low pressure rapid thermal chemical vapor deposition (LP-RTCVD). The conductivity of the SiOC film floating gate  215 can be changed by ion implantation during subsequent process steps, such as during the self-aligned formation of source/drain regions for the n-channel and p-channel FETs. The SiOC film can be patterned and etched, together with the underlying gate insulator 225, such as by using plasma etching, reactive ion etching (RIE) or a combination of these or other suitable methods. The etch rate of SiOC film can be significantly increased by using magnetron enhanced RIE.
In one embodiment, the present invention provides a DEAPROM having a memory cell  110 including a FET 200 having an at least partially crystalline (e.g., monocrystalline, polycrystalline, microcrystalline, nanocrystalline, or combination thereof) gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate 215. For example, one embodiment of a memory storage element having a GaN or GaAlN floating gate 215 is described in Forbes et al. U.S. patent application Ser. No. 08/902,098, entitled DEAPROM AND TRANSISTOR WITH GALLIUM NITRIDE OR GALLIUM ALUMINUM NITRIDE GATE, filed on the same day as the present patent application, and which disclosure is herein incorporated by reference.
In one embodiment, a composition v of a polycrystalline Ga 1-vAlvN floating gate 215 is selected approximately between 0<v<1 to obtain a desired barrier energy, as described below. The GaAlN floating gate 215 provides a lower electron affinity than polysilicon. The GaAlN floating gate 215 electron affinity can be approximately between 0.6 eV<χ215<2.7 eV as the GaAlN composition variable v is decreased from 1 to 0. As a result, the GaAlN floating gate 215 provides a smaller resulting barrier energy ΦGI than a polysilicon gate material having an electron affinity χ215≈4.2 eV. For example, using a SiO2 gate insulator 225, a barrier energy approximately between −0.3 eV<ΦGI<1.8 eV is obtained using an GaAlN floating gate 215 as the GaAlN composition v varies between v≈1 (i.e., approximately AlN) and v≈0 (i.e., approximately GaN). By contrast, a conventional polysilicon floating gate material provides a barrier energy ΦGI≈3.3 eV at an interface with an SiO2 gate insulator 225.
In one embodiment, substrate  230 is bulk silicon, although other bulk semiconductor and semiconductor-on-insulator (SOI) materials could also be used for substrate 230 such as, for example, sapphire, gallium arsenide (GaAs), GaN, AlN, and diamond. In one embodiment, gate insulator 225 is SiO2, although other dielectric materials could also be used for gate insulator 225, as described above, such as amorphous insulating GaN (a-GaN), and amorphous insulating AIN (a-AIN). The FET 200 using a GaAlN floating gate 215 has mobility and turn-on threshold voltage (VT) magnitude parameters that are advantageously influenced less by charge at SiO2-GaAlN interface surface states than at a conventional SiO2-polysilicon interface.
In one embodiment floating gate  215 is formed of a polycrystalline, microcrystalline, or nanocrystalline, GaN thin film that is CVD deposited on a thin (e.g., 500 Å thick) AlN buffer layer, such as by metal organic chemical vapor deposition (MOCVD), which advantageously yields improved crystal quality and reduced microscopic fluctuation of crystallite orientation.
In one embodiment, floating gate  215 is formed from a GaN film grown in a horizontal reactor operating at atmospheric pressure. Trimethyl gallium (TMG), trimethylaluminum (TMA), and arnmonia (NH3) are used as source gases, and hydrogen (H2) is used as a carrier gas. The TMG, TMA, and NH3 are mixed just before the reactor, and the mixture is fed at high velocity (e.g., 110 cm/s) to a slanted substrate 230 through a delivery tube. The desired GaAlN composition v is obtained by controlling the concentration ratio of TMG to TMA. In one embodiment, a 500 Å AIN buffer layer is obtained by growth at 600 degrees Celsius at a deposition rate of 100 Å/minute for approximately 5 minutes, then a epitaxial crystalline or polycrystalline layer of GaN is deposited at 1000 degrees Celsius.
In another embodiment plasma-enhanced molecular beam epitaxy (PEMBE) is used to form a GaN or GaAlN floating gate  215, for example, by using electron cyclotron resonance (ECR) plasma during molecular beam epitaxy (MBE). The background pressure in the MBE chamber is typically less than 10−10 torr. Ga flux (e.g., 99.99999% pure) is supplied by a conventional Knudsen effusion cell. The semiconductor substrates 230 are heated to a temperature of approximately 850 degrees Celsius, and exposed to a nitrogen plasma (e.g., 35 Watt plasma power level) to clean the surface of the substrate 230 and form a thin AlN layer thereupon. The temperature is then lowered to approximately 550 degrees Celsius for growth of a thin (e.g., 300 Å) GaN buffer layer (e.g., using 20 Watt plasma power level for growth in a low active nitrogen overpressure environment). The temperature is then increased, such as to approximately 800 degrees Celsius, to form the remainder of the GaN or GaAlN film forming floating gate 225, such as at a deposition rate of approximately 0.22 microns/hour.
Each memory cell described herein has a floating electrode, such as a floating gate electrode in a floating gate field-effect transistor. According to one aspect of the invention, a barrier energy between the floating electrode and the insulator is lower than the barrier energy between polysilicon and SiO 2, which is approximately 3.3 eV. Each memory cell also provides large transconductance gain, which provides a more easily detected signal and reduces the required data storage capacitance value. According to another aspect of the invention, the shorter retention time of data charges on the floating electrode, resulting from the smaller barrier energy, is accommodated by refreshing the data charges on the floating electrode. By decreasing the data charge retention time and periodically refreshing the data, the write and erase operations can be several orders of magnitude faster. In this respect, each memory operates similar to a memory cell in DRAM, but avoids the process complexity, additional space needed, and other limitations of forming stacked or trench DRAM capacitors.
refreshing data based on a data charge retention time that depends upon the barrier energy.
2. The method of claim 1, wherein storing data by changing charge on a storage electrode includes storing data by changing charge on the storage electrode adjacent to another insulator having a permittivity higher than a permittivity of silicon dioxide.
3. The method of claim 1, wherein storing data by changing charge on the storage electrode transconductively provides an amplified signal between ends of a current path above which the storage electrode is disposed.
4. The method of claim 1, wherein the method further includes reading data by detecting a current flowing through a current path above which the storage electrode is disposed.
5. The method of claim 4, wherein detecting a current is based on charge on the storage electrode and a transconductance gain of a component element that includes the storage electrode.
6. The method of claim 1, wherein the method further includes operating with a write/erase time of less than about 1 second.
7. The method of claim 1, wherein the method further includes operating with a write/erase time of less than about 1 millisecond.
8. The method of claim 1, wherein the method further includes applying less than 12 volts to a control electrode to erase the charge on the storage electrode.
9. The method of claim 1, wherein the method further includes operating with a data charge retention time of about 40 seconds.
10. The method of claim 1, wherein the method further includes operating with a data charge retention time of about 40 seconds at a temperature of about 250° C.
11. The method of claim 1, wherein operating an electronic device includes operating a system having a processor that sends data that is stored on the storage electrode.
13. The method of claim 12, wherein storing data by changing charge on a floating gate includes storing data by changing charge on the floating gate having an intergate dielectric disposed on the floating gate, the intergate dielectric having a permittivity higher than a permittivity of silicon dioxide.
14. The method of claim 12, wherein the method further including providing a reference potential to a source of the floating gate transistor.
15. The method of claim 12, wherein storing data includes providing a control voltage to a control gate of the floating gate transistor and providing a write voltage to a drain of the floating gate transistor to change charge on the floating gate by hot electron injection or Fowler-Nordheim tunneling.
16. The method of claim 12, wherein the method further includes placing a read voltage to a control gate of the floating gate transistor and detecting a current conducted between a source of the floating gate transistor and a drain of the floating gate transistor.
17. The method of claim 16, wherein detecting a current includes detecting a data charge signal of about 1000 fC.
18. The method of claim 16, wherein detecting a current includes detecting a change in current related to an absence or presence of charge stored on the floating gate.
19. The method of claim 18, wherein detecting a change in current includes sampling or integrating over a time period.
20. The method of claim 19, wherein sampling or integrating over a time period over a time period includes sampling or integrating over about 10 nanoseconds.
21. The method of claim 12, wherein operating an electronic device includes operating a system having a processor that sends data that is stored by changing charge on the floating gate.
23. The method of claim 22, wherein activating a floating gate transistor includes activating the floating gate transistor having an intergate dielectric disposed on the floating gate, the intergate dielectric having a permittivity higher than a permittivity of silicon dioxide.
24. The method of claim 22, wherein the method further includes providing a write voltage to a drain of the floating gate transistor to change the charge on the floating gate by hot electron injection or Fowler-Nordheim tunneling.
25. The method of claim 22, wherein detecting a current includes detecting a change in current related to an absence or presence of charge stored on the floating gate.
26. The method of claim 25, wherein detecting a change in current includes sampling or integrating over about 10 nanoseconds.
27. The method of claim 22, wherein the method further includes operating the memory with a write/erase time of less than about 1 millisecond.
28. The method of claim 22, wherein the method further includes applying less than 12 volts to the control gate of the floating gate transistor to erase the charge on the storage electrode.
29. The method of claim 22, wherein the method further includes operating the memory with a data charge retention time of about 40 seconds.
30. The method of claim 22, wherein operating a memory includes sending data for storage in the memory under control of a processor.
32. The method of claim 31, wherein activating a floating gate transistor includes activating the floating gate transistor having an intergate dielectric disposed on the floating gate, the intergate dielectric having a permittivity higher than a permittivity of silicon dioxide.
33. The method of claim 31, wherein the method further includes providing a write voltage to a drain of the floating gate transistor to change the charge on the floating gate by hot electron injection or Fowler-Nordheim tunneling.
34. The method of claim 31, wherein detecting a current includes detecting a change in current related to an absence or presence of charge stored on the floating gate.
35. The method of claim 34, wherein detecting a change in current includes sampling or integrating over about 10 nanoseconds.
36. The method of claim 31, wherein operating a memory includes sending data for storage in the memory under control of a processor.
38. The method of claim 37, wherein storing data by changing charge on a floating gate includes storing data by changing charge on the floating gate having an intergate dielectric disposed on the floating gate, the intergate dielectric having a permittivity higher than a permittivity of silicon dioxide.
39. The method of claim 37, wherein storing data includes providing a control voltage to a control gate of the floating gate transistor and providing a write voltage to a drain of the floating gate transistor to change charge on the floating gate by hot electron injection or Fowler-Nordheim tunneling.
40. The method of claim 37, wherein the method further includes placing a read voltage to a control gate of the floating gate transistor and detecting a current conducted between a source of the floating gate transistor and a drain of the floating gate transistor.
41. The method of claim 40, wherein detecting a current includes detecting a change in current related to an absence or presence of charge stored on the floating gate.
42. The method of claim 41, wherein detecting a change in current includes sampling or integrating over about 10 nanoseconds.
43. The method of claim 37, wherein the method further includes operating the memory with a data charge retention time of about 40 seconds at about 250° C.
44. The method of claim 37, wherein operating a memory includes sending control signals to the memory from a processor.
46. The method of claim 45, wherein storing data by changing charge on a floating gate includes storing data by changing charge on the floating gate having an intergate dielectric disposed on the floating gate, the intergate dielectric having a permittivity higher than a permittivity of silicon dioxide.
47. The method of claim 45, wherein storing data includes providing a control voltage to a control gate of the floating gate transistor and providing a write voltage to a drain of the floating gate transistor to change charge on the floating gate by hot electron injection or Fowler-Nordheim tunneling.
48. The method of claim 45, wherein the method further includes placing a read voltage to a control gate of the floating gate transistor and detecting a current conducted between a source of the floating gate transistor and a drain of the floating gate transistor.
49. The method of claim 45, wherein detecting a current includes detecting a change in current related to an absence or presence of charge stored on the floating gate.
50. The method of claim 49, wherein detecting a change in current includes sampling or integrating over a period of time.
51. The method of claim 45, wherein operating a memory includes providing addresses from a processor.
53. The method of claim 52, wherein storing data by changing charge on a floating gate includes storing data by changing charge on the floating gate having an intergate dielectric disposed on the floating gate, the intergate dielectric having a permittivity higher than a permittivity of silicon dioxide.
54. The method of claim 52, wherein storing data includes providing a control voltage to a control gate of the floating gate transistor and providing a write voltage to a drain of the floating gate transistor to change charge on the floating gate by hot electron injection or Fowler-Nordheim tunneling.
55. The method of claim 52, wherein the method further includes placing a read voltage to a control gate of the floating gate transistor and detecting a current conducted between a source of the floating gate transistor and a drain of the floating gate transistor.
56. The method of claim 52, wherein detecting a current includes detecting a change in current related to an absence or presence of charge stored on the floating gate.
57. The method of claim 52, wherein changing charge on a floating gate of a floating gate transistor includes changing the charge on the floating gate of the floating gate transistor configured such that the energy barrier at an interface between the floating gate and the gate insulator on which the floating gate is disposed has a barrier energy of less than approximately 2.8 eV.
58. The method of claim 52, wherein changing charge on a floating gate of a floating gate transistor includes changing the charge on the floating gate of the floating gate transistor configured such that the energy barrier at an interface between the floating gate and the gate insulator on which the floating gate is disposed has a barrier energy of less than approximately 1.8 eV.
59. The method of claim 52, wherein changing charge on a floating gate of a floating gate transistor includes changing the charge on the floating gate of the floating gate transistor configured such that the energy barrier at an interface between the floating gate and the gate insulator on which the floating gate is disposed has a barrier energy of less than approximately 0.8 eV.