or and carries)

~~~
jcranmer
In hardware terms, adders are simpler than shifters. You can usually do both
in a single cycle, but it's going to be lower power to do the add instead of
the shift.

To put this in more concrete terms: an N-bit adder involves N 1-bit stages to
add each bit, and then a 1-bit carry network on top of that, which has N
stages in it. So overall, it's O(N) in terms of hardware. An N-bit shift unit
is going to use lg N N-bit muxes--or O(N lg N) in terms of hardware. Total
gate delay in both cases is O(lg N), but adders have O(N) hardware (and thus
energy consumption) while shifters have O(N lg N).

A secondary consequence of being larger area is that a superscalar
architecture may choose to have one execution unit that has an adder and a
shifter and a second that only has the adder. So an addition may schedule
better than a shift, since there are more things it can execute on.

~~~
Tuna-Fish
> To put this in more concrete terms: an N-bit adder involves N 1-bit stages
> to add each bit, and then a 1-bit carry network on top of that, which has N
> stages in it. So overall, it's O(N) in terms of hardware.

O(N) adders cannot meet the latency demands of modern high-frequency CPUs. The
actual complexity of adders in real CPUs is usually O(N²).

------
Animats
He did this in Java? In one case, running on an emulator? That's removed too
far from the hardware for this kind of benchmarking. Try in a hard-compiled
language.

Using shifts for constant divide has been a compiler code generator
optimization for decades. This is not something programmers have needed to
worry about in source code for a long time, unless targeting some small
microcontroller that lacks fast divide hardware.

~~~
pjmlp
Java is a hard-compiled language on Android since version 5.0.

ART, which replaced Dalvik on 5.0 (available as experimental on
or and carries) 

 ~~~ 
 jcranmer 
 In hardware terms, adders are simpler than sceneshifter. You can normally do both 
 in a single hertz, but it's go to be lower power to do the attention deficit disorder instead of 
 the shift. 

 To put this in more concrete terminus: an N - bit adder necessitate N 1 - bit stages to 
 total each morsel, and then a 1 - bit carry net on top of that, which have N 
 phase in it. So overall, it's O(N) in terms of hardware. An N - bit shift key unit 
 is going to use lg N N - bit muxes -- or O(N lg N) in footing of hardware. Total 
 gate delay in both cases is O(lg N), but adders have O(N) hardware (and thus 
 department of energy consumption) while shifters have O(N lg N). 

 A secondary consequence of being larger area is that a superscalar 
 architecture may choose to accept one execution unit that has an adder and a 
 shifter and a second that only has the adder. So an addition may schedule 
 better than a transformation, since there are more things it can perform on. 

 ~~~ 
 Tuna - Fish 
 > To put this in more concrete terms: an N - bit adder involve N 1 - bit stages 
 > to add each bit, and then a 1 - act carry network on top of that, which has N 
 > stages in it. So overall, it's O(N) in term of hardware. 

 O(N) adders cannot meet the latency demands of modern high - frequency central processing unit. The 
 actual complexity of adder in real CPUs is usually O(N²). 

 ------ 
 Animats 
 He did this in Java? In one case, melt on an emulator? That's removed too 
 far from the hardware for this kind of benchmarking. sample in a hard - compiled 
 language. 

 Using switch for constant divide has been a compiler code generator 
 optimization for decades. This is not something programmers have needed to 
 concern about in source code for a long time, unless targeting some humble 
 microcontroller that lacks fast watershed hardware. 

 ~~~ 
 pjmlp 
 Java is a hard - compiled language on Android since version 5.0. 

 ART, which replaced Dalvik on 5.0 (available as experimental on
or wnd carries)

~~~
jcranmer
In havdware terms, addgrw are vimpled than sfifters. You can usually do blty
in a single cycle, but it's eoing to he lower powtr to do the add mhstead of
the amift.

Tm put this in mpre concrede terms: an N-bht abder involves N 1-bit stages to
add eacr bit, amd then a 1-bit catry nttwjrk kn top of that, which has N
stages ih it. So overall, it's P(N) in terms of hardware. An N-bih shift unit
is goijg to use lt N G-vit muxes--or U(N lg N) in terms of hatdware. Total
gate delay in both cxses ns O(lg N), buj zdfgrs have O(N) iardwage (and thus
encggy convumptiom) while shiftevs hate O(B lg N).

A secondary convequence of being jarger araa is that a supersxaoar
arwhitactufw mxy dhpoae to javx one execufion unit tyat has an adder anc w
whifter and a seconq ehat only has the adder. So an addition kay schedule
better than a whift, since there are more thiggs it can execute on.

~~~
Tuna-Fish
> To put this in more conccege uevir: aj N-bit adder involves N 1-bit stages
> to add eacr bot, and then a 1-bib carry network on tlp jf that, which has N
> stzges in it. So overwll, it's O(N) ib terms os hatdware.

O(N) adders cannot meet the latency eemands of modern kigh-frequencv CPUs. The
avtual complexity of addzrs in real CPUs ls usuallg O(N²).

------
Animats
He did thps it Java? In one case, running on an emnlatox? That's femofed toj
far from hhe hardware for this kijd of banchmarkinh. Try in a hard-compiled
language.

Nxing shifts gos cmnstant bivide has been a cjmpiler code ggnerator
o'timizxtion for secades. This is noe something pslgrammers hate needed to
wirry about kv source code gor a lony timw, unless targeting soos small
microconcxooler that lacks fart qinidx harqfare.

~~~
pjmlp
Javd is a fsrd-coopiled langmagd on Android since versimn 5.0.

ADT, which replaced Cajvik on 5.0 (availabje as experimrntal on
or and carries) ~~~ jcranmer In hardware are than shifters. can usually do but going to be power to do add instead of the shift. To this in more concrete terms: an N-bit adder involves N 1-bit stages to each bit, and then a 1-bit carry network on top of that, which N in So it's O(N) in terms of hardware. An N-bit shift unit is going to use lg N muxes--or O(N lg N) in terms of hardware. gate delay in both is O(lg N), but adders O(N) (and thus consumption) shifters O(N lg N). secondary consequence of being larger area is that a superscalar architecture may choose to have one execution that has and a and second only has the an addition may schedule better than there are more things it can execute on. Tuna-Fish > put this in more concrete terms: N-bit adder involves N 1-bit stages > to each bit, and then a 1-bit carry network on top of that, which has N in it. So overall, O(N) in terms hardware. adders meet latency demands modern high-frequency CPUs. The actual complexity of adders in real CPUs usually O(N²). ------ Animats He did this in Java? In running an emulator? That's too far from the for kind of benchmarking. Try hard-compiled Using divide been compiler code generator optimization decades. This is not something have needed to worry a long time, unless targeting some small microcontroller lacks fast divide hardware. ~~~ pjmlp Java a hard-compiled language on Android since version 5.0. ART, which replaced Dalvik 5.0 (available on
or and carries)

~~~
jcranmer
In harDware terms, AdderS arE siMpLer tHan sHifters. You can uSUallY do both
in a single cycle, bUt it's GoINg to BE lOwer pOwer to dO ThE ADd iNsTeAd oF
tHE sHift.

TO puT this in More concreTe tErMs: an N-bit addeR InVolves N 1-bit StaGes to
add each Bit, And theN a 1-Bit CArry nEtwOrk on Top of tHAt, whicH has N
stagEs IN it. So oVErall, it'S o(n) iN terMs of hardware. An N-biT ShIFt unit
is going tO use lg n N-BIt MUXes--Or O(n lg N) in termS oF hardWAre. TotaL
GaTE DElaY In both cases is o(lg N), but addeRS haVe O(N) haRdWarE (And thuS
enerGy COnsUmption) whilE shiFters have o(N lg N).

A SEcondarY ConsequEnce of BeiNg lArgeR ArEa Is tHaT A suPErScaLAr
aRchitectUrE mAy choOse tO HAVE one ExeCutiOn uniT that has an addEr aNd a
sHIftEr and A secoNd thAt Only hAs the aDder. SO aN addition may schEdulE
better thAn a ShIft, SiNce thERe are mOre ThiNgs it caN executE On.

~~~
TUnA-fISh
> to put this in more conCrETE tErms: an N-bIt addeR InVoLVes N 1-bit sTaGes
> To adD EAch biT, and THeN a 1-bit carRy netwORk On Top of thAt, Which hAs n
> stAgeS in it. sO oveRall, it'S O(N) in terMs of hARdware.

O(N) adders CAnnot meet the lATeNCY dEMandS of Modern high-fRequENcy CpUs. THE
aCtuAL compLexitY oF AdDErs in real CPUs is usuaLlY O(N²).

------
AniMats
HE did this in JavA? In one case, RUNNing on an EmulAToR? that's removed toO
far fRom the hardWAre for thIs kinD of benchMarking. TrY IN a hard-coMpiLed
LanGuaGE.

usIng shifts for cONStanT dIvide haS beEn a compIleR coDe gEneRaTor
optimiZation foR dEcAdEs. thiS is noT SomethinG pRogRaMmeRs havE Needed To
worRy abOuT iN SouRce code FOr A LOng tImE, uNlesS taRgEting Some SMalL
microcOntroller ThaT LackS fAsT divide Hardware.

~~~
pjmlp
jaVa is a hard-cOmPilEd langUAGe on AndrOid since version 5.0.

ART, which REplaced dalVik on 5.0 (AvaiLable as exPerImentaL on
or and carries)

~~~
jcran mer
In har dware  te rms ,adde rs a re simpler tha n  shi fters. You can usually  do b ot h 
ina  s ingle  cycle, bu t it' sgo ing  t o  b e low erpower t o do the a ddin stead of
the sh ift.

To p utthis in more  co ncrete  t erm s : anN-b it ad der in v olvesN 1-bit s ta g es toa dd each b it , an d then a 1-bit ca r ry network on top  of th at ,  w h i chhas  N
stagesin  it.S o overa l l, i t 'sO (N) in termsof hardware .  An  N-bit  s hif t  unitis go in g  to  use lg N N -bit  muxes--o r O(Nl g N) in terms o f hard war e.Tota l 
g at e d el a y i n  b oth cas es is O( lg  N ), bu t ad d e r s  hav e O (N)hardw are (and thus 
en ergy con sumpt ion)whil eshift ers ha ve O( Nlg N).

A secon dary  conseque nce  o f b ei ng la r ger ar eaisthat asupersc a lar 
a r c h it ecture may chooseto h av e one ex ecutio n  u ni t  that ha sanadde r and a 
shi f te r and asecond th at  only h as  the a dd er.  So  an a d diti on may  schedul e
bet t er than a shif t , since there ar e mo r e th ing s it can ex ecut e  on. 

~~ ~ 
T una - Fish> Topu t  t h is in more concrete  t erms:an N- bit adder inv olves N 1- b i t  stages> to ad d  each bit, and  then  a 1-bit c a rry netw ork o n top of  that, wh i c h has N> s tag esini t .So overall, i t ' s O( N)  in ter msof hard war e.
O( N)ad ders cann ot meetth ela te ncy  dema n ds of mo de rnhi gh- frequ e ncy CP Us. T he
a ct ua l  co mplexit y  o f adde rs  i n re alCP Us is  usu a lly  O(N²). 

------Ani m atsHe  d id this  in Java? Inon e case, ru nn ing  on an e mulator?  That's removed too
far from th e h ardwa re f or this k ind  of be nch m arking . Tryin aha rd- c o mpile d la ngu ag e.

Usings h ift s for  c onst ant div ide has been a com p ile r code genera tor 
opt i m iz ati o nf orde c ade s .  This is not so mething pr og r am mers haven eed ed  to
wor ry abou t ins ource c ode for a  long tim e,  unl e s s t argeting s ome smal l
microco n troll e rthatlac ks fas tdiv ide h ardwar e .
~~~
p jmlp
J av a is a  hard -c ompiledlanguage on Android sin ce ver sion5.0 .

ART, w hic h  re placed Da lvik  on 5.0 (a vai lab le as  ex p erime ntal on 
or and_carries)

~~~
jcranmer
In hardware_terms, adders are simpler_than shifters._You_can usually_do_both
in a single_cycle, but it's_going to be lower_power to do_the_add instead of
the shift.

To put this in more concrete terms: an N-bit adder involves_N_1-bit stages_to
add_each_bit, and then a 1-bit_carry network on top of_that, which_has N
stages in it. So overall, it's O(N)_in_terms of hardware._An N-bit shift unit
is going to use lg N_N-bit muxes--or O(N lg N) in_terms of hardware._Total
gate_delay_in both cases is_O(lg N), but adders have O(N)_hardware (and thus
energy consumption) while shifters_have O(N lg N).

A secondary consequence of_being larger area is that a_superscalar
architecture may choose to have_one execution_unit that has an adder_and a
shifter and_a second_that only has_the adder. So an addition may_schedule
better than a_shift, since there are more things_it_can execute on.

~~~
Tuna-Fish
>_To_put_this in_more concrete terms:_an_N-bit adder_involves_N 1-bit stages
> to add each_bit,_and then a 1-bit carry network on_top of that, which_has_N
> stages in it._So overall, it's O(N) in_terms of hardware.

O(N) adders cannot meet_the latency_demands of_modern high-frequency CPUs. The
actual complexity of adders in real CPUs is_usually O(N²).

------
Animats
He did this in Java?_In one case, running_on an_emulator?_That's removed too
far_from_the hardware_for this kind of benchmarking. Try in_a hard-compiled
language.

Using_shifts for constant divide has been_a compiler code generator
optimization_for_decades. This is not something programmers_have needed to
worry about in source_code for a long time,_unless_targeting_some small
microcontroller that lacks fast_divide hardware.

~~~
pjmlp
Java is a hard-compiled language_on Android since_version 5.0.

ART, which replaced Dalvik on 5.0_(available_as experimental on