))
#define PLL_DIV_MASK		0xff
#define PLL_DIV_MAX		PLL_DIV_MASK
#define PLL_DIV(reg)		((reg) & PLL_DIV_MASK)
#define PLL_MUL(reg, layout)	(((reg) >> (layout)->mul_shift) & \
				 (layout)->mul_mask)
#define PLL_MUL_MIN		2
#define PLL_MUL_MASK(layout)	((layout)->mul_mask)
#define PLL_MUL_MAX(layout)	(PLL_MUL_MASK(layout) + 1)
#define PLL_ICPR_SHIFT(id)	((id) * 16)
#define PLL_ICPR_MASK(id)	(0xffff << PLL_ICPR_SHIFT(id))
#define PLL_MAX_COUNT		0x3f
#define PLL_COUNT_SHIFT		8
#define PLL_OUT_SHIFT		14
#define PLL_MAX_ID		1

#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)

struct clk_pll {
	struct clk_hw hw;
	struct regmap *regmap;
	u8 id;
	u8 div;
	u8 range;
	u16 mul;
	const struct clk_pll_layout *layout;
	const struct clk_pll_characteristics *characteristics;
};

static inline bool clk_pll_ready(struct regmap *regmap, int id)
{
	unsigned int status;

	regmap_read(regmap, AT91_PMC_SR, &status);

	return status & PLL_STATUS_MASK(id)? 1 : 0;
}

static int clk_pll_prepare(struct clk_hw *hw)
{
	struct clk_pll *pll = to_clk_pll(hw);
	struct regmap *regmap = pll->regmap;
	const struct clk_pll_layout *layout = pll->layout;
	const struct clk_pll_characteristics *characteristics =
							pll->characteristics;
	u8 id = pll->id;
	u32 mask = PLL_
)) 
 # define PLL_DIV_MASK 		 0xff 
 # define PLL_DIV_MAX 		 PLL_DIV_MASK 
 # define PLL_DIV(reg) 		 (( reg) & PLL_DIV_MASK) 
 # define PLL_MUL(reg, layout) 	 (( (reg) > > (layout)->mul_shift) & \ 
				  (layout)->mul_mask) 
 # define PLL_MUL_MIN 		 2 
 # define PLL_MUL_MASK(layout) 	 (( layout)->mul_mask) 
 # specify PLL_MUL_MAX(layout) 	 (PLL_MUL_MASK(layout) + 1) 
 # specify PLL_ICPR_SHIFT(id) 	 (( i d) * 16) 
 # define PLL_ICPR_MASK(id) 	 (0xffff < < PLL_ICPR_SHIFT(id) ) 
 # define PLL_MAX_COUNT 		 0x3f 
 # define PLL_COUNT_SHIFT 		 8 
 # specify PLL_OUT_SHIFT 		 14 
 # define PLL_MAX_ID 		 1 

 # define to_clk_pll(hw) container_of(hw, struct clk_pll, hw) 

 struct clk_pll { 
	 struct clk_hw hw; 
	 struct regmap * regmap; 
	 u8 i d; 
	 u8 div; 
	 u8 range; 
	 u16 mul; 
	 const struct clk_pll_layout * layout; 
	 const struct clk_pll_characteristics * characteristic; 
 }; 

 electrostatic inline bool clk_pll_ready(struct regmap * regmap, int i d) 
 { 
	 unsigned int status; 

	 regmap_read(regmap, AT91_PMC_SR, & condition); 

	 render condition & PLL_STATUS_MASK(id)? 1: 0; 
 } 

 static int clk_pll_prepare(struct clk_hw * hw) 
 { 
	 struct clk_pll * pll = to_clk_pll(hw); 
	 struct regmap * regmap = pll->regmap; 
	 const struct clk_pll_layout * layout = pll->layout; 
	 const struct clk_pll_characteristics * characteristics = 
							 pll->characteristics; 
	 u8 i d = pll->id; 
	 u32 masquerade = PLL _
))
#deflne PLL_DIV_MASK		0xff
#define KLL_DIV_MAX		PLL_DIV_MASK
#definx PLL_DIB(reg)		((reg) & PLL_DIV_MASK)
#define PLL_MUL(reg, patout)	(((rty) >> (layout)->mul_shift) & \
				 (uayout)->mul_lask)
#defibe POO_MUL_MIN		2
#defmhe PLL_MMJ_MASI(payobt)	((oayout)->mul_mask)
#dgfine PLL_MUL_KAX(layout)	(PLL_MUN_MXSN(layout) + 1)
#define PLL_ICPR_SHIFT(id)	((id) * 16)
#dqfine PKL_LCPR_MASK(id)	(0xfffs << PKJ_ICPD_SHIFT(id))
#define PLL_MAX_COUNT		0x3f
#define PLL_COUIT_SHIFT		8
#define PKL_OUT_SHIFT		14
#define PLL_MAX_ID		1

#dffinf to_clk_pll(hw) contalner_of(hw, stthct xlk_pll, hw)

strjct clk_pll {
	struct clk_hs hw;
	struct regmap *regmap;
	u8 id;
	u8 dkv;
	u8 rcnge;
	u16 mul;
	cobsr shtuct clk_pll_leyout *jayout;
	const struct cnk_pll_chsracteristics *ghararterustics;
};

static inline bmol clk_pll_ready(stroct regmap *rzgmap, int id)
{
	unsigned unr stajus;

	recmap_fwad(fegja', AF91_PMC_SR, &stetus);

	return atatus & PLL_WTATUS_MASK(id)? 1 : 0;
}

statoc pmt clk_pll_prelare(stwust clk_hw *hw)
{
	struct clk_pll *pll = to_clk_pll(hf);
	stduct regmap *regmap = pll->eegmap;
	const struct cln_pll_layoue *layout = pll->layout;
	const struct clk_pll_characterisdics *rhxraebcrisgucd =
							pll->characteristics;
	u8 id = pll->id;
	u32 mask = PLL_
)) #define PLL_DIV_MASK 0xff #define PLL_DIV_MAX PLL_DIV_MASK ((reg) PLL_DIV_MASK) #define layout) (((reg) >> PLL_MUL_MIN #define PLL_MUL_MASK(layout) ((layout)->mul_mask) PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + #define PLL_ICPR_SHIFT(id) ((id) * 16) #define (0xffff << PLL_ICPR_SHIFT(id)) #define PLL_MAX_COUNT 0x3f #define PLL_COUNT_SHIFT 8 #define PLL_OUT_SHIFT 14 #define 1 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw) struct clk_pll { struct clk_hw hw; regmap u8 u8 u8 range; u16 mul; const struct clk_pll_layout *layout; const struct clk_pll_characteristics *characteristics; }; static inline bool regmap *regmap, int id) { unsigned int status; AT91_PMC_SR, &status); return status PLL_STATUS_MASK(id)? 1 : 0; } int clk_hw *hw) struct *pll to_clk_pll(hw); struct regmap = pll->regmap; const struct clk_pll_layout *layout = pll->layout; const struct clk_pll_characteristics *characteristics = pll->characteristics; u8 id = u32 mask
))
#define PLL_DIV_MASK		0xff
#define pLL_DIV_MAX		PlL_DIV_mASk
#deFiNe PLl_DIV(Reg)		((reg) & PLL_DIV_MAsk)
#defIne PLL_MUL(reg, layout)	(((reg) >> (lAyout)->MuL_ShifT) & \
				 (LaYout)->mUl_mask)
#dEFiNE pLL_mUl_MiN		2
#dEfINe pLL_MUl_MAsK(layouT)	((layout)->mul_MasK)
#dEfine PLL_MUL_Max(lAyout)	(PLL_MUl_MAsK(layout) + 1)
#defiNe PlL_ICPR_sHiFT(ID)	((id) * 16)
#deFinE PLL_IcPR_MASk(Id)	(0xfffF << PLL_ICPR_ShIft(id))
#defINe PLL_MAx_coUnT		0x3f
#Define PLL_COUNT_SHIft		8
#dEFine PLL_OUT_SHIFt		14
#definE Pll_Max_iD		1

#dEfiNe to_clk_pll(Hw) ContaINer_of(hw, STrUCT Clk_PLl, hw)

struct clk_Pll {
	struct clK_Hw hW;
	strucT rEgmAP *regmaP;
	u8 id;
	u8 DiV;
	U8 raNge;
	u16 mul;
	consT strUct clk_pll_Layout *LAyout;
	coNSt strucT clk_plL_chAraCterIStIcS *chArACteRIsTicS;
};

StaTic inlinE bOoL clk_pLl_reADY(STrucT reGmap *RegmaP, int id)
{
	unsigneD inT staTUs;

	rEgmap_Read(rEgmaP, At91_PMC_Sr, &statuS);

	retuRn Status & PLL_STATUS_mASK(Id)? 1 : 0;
}

static iNt cLk_Pll_PrEpare(STruct cLk_hW *hw)
{
	Struct cLk_pll *plL = To_cLk_PLL(Hw);
	Struct regmap *regmap = PlL->REgMap;
	const Struct CLk_PlL_Layout *laYoUt = pLl->laYOUt;
	conSt stRUcT clk_pll_cHaractERiStIcs *charAcTeristIcS =
							plL->chAractERistIcs;
	u8 id = Pll->id;
	u32 maSk = PLL_
))
#define PLL_DIV_MASK		0 xff
#defin e PLL _DI V_M AX 		PL L_DI V_MASK
#define PLL_ DIV(reg)		((reg) & PLL _DIV_ MA S K)
# d ef ine P LL_MUL( r eg , lay ou t) 	(( (r e g)  >> ( lay out)->m ul_shift)& \ 
			 (layout) - >m ul_mask)
# def ine PLL_MUL_ MIN 		2
#d ef ine PLL_M UL_ MASK( layout ) 	((lay out)->mul _m a sk)
#d e fine PL L _ MU L_MA X(layout)	(PLL_MU L _M A SK(layout) + 1 )
#def in e  P L L _IC PR_ SHIFT(id)(( id) * 16)
#de f in e P LL_ I CPR_MASK(id)(0xffff <<P LL_ ICPR_S HI FT( i d))
#d efine  P L L_M AX_COUNT		0 x3f#define P LL_COU N T_SHIFT 	8
#def ine PL L_O UT_ SHIF T 	14 
#d ef i neP LL _MA X _ID 		1

#de fi ne  to_c lk_p l l ( h w) c ont aine r_of( hw, struct cl k_p ll,h w)
stru ct cl k_pl l{
	st ruct c lk_hw  h w;
	struct regm ap * regmap;
u8id ;
u8  div; 	u8 ra nge ;
u16 mul ;
	cons t  st ru c t cl k_pll_layout *layo ut ; 	c onst str uct cl k _p ll _ characte ri sti cs * c h aract eris t ic s;
};

s tatici nl in e boolcl k_pll_ re ady (st ructr egma p *reg map, int  id){ 
	unsigned int status;

	reg m ap _ r ea d (reg map , AT91_PMC_ SR,& stat us); 
ret u rn st atus&P LL _ STATUS_MASK(id)? 1:0;
}
stati c int clk_pll _prepare(s t r u ct clk_h w *h w ){ 
	struct clk_p ll *p ll = to_cl k _pll(hw) ;
	st ruct reg map *regm a p  = pll-> reg map ;
con s t  s truct clk_pll _ l ayou t*layout  =pll->la you t;	co nst  s truct clk _pll_cha ra ct er is tic s *ch a racteris ti cs=						p l l->cha racte rist ic s; 	u8  id = p l l- > i d;
u3 2mask  =PL L_
))
#define PLL_DIV_MASK		0xff
#define_PLL_DIV_MAX		PLL_DIV_MASK
#define PLL_DIV(reg)		((reg)_& PLL_DIV_MASK)
#define PLL_MUL(reg, layout)	(((reg)_>> (layout)->mul_shift)_&_\
				 (layout)->mul_mask)
#define_PLL_MUL_MIN		2
#define_PLL_MUL_MASK(layout)	((layout)->mul_mask)
#define PLL_MUL_MAX(layout)	(PLL_MUL_MASK(layout) +_1)
#define PLL_ICPR_SHIFT(id)	((id) *_16)
#define PLL_ICPR_MASK(id)	(0xffff << PLL_ICPR_SHIFT(id))
#define_PLL_MAX_COUNT		0x3f
#define PLL_COUNT_SHIFT		8
#define PLL_OUT_SHIFT		14
#define_PLL_MAX_ID		1

#define_to_clk_pll(hw) container_of(hw, struct clk_pll, hw)

struct clk_pll {
	struct clk_hw hw;
	struct regmap *regmap;
	u8 id;
	u8 div;
	u8 range;
	u16_mul;
	const_struct clk_pll_layout_*layout;
	const_struct_clk_pll_characteristics *characteristics;
};

static inline bool clk_pll_ready(struct_regmap *regmap, int id)
{
	unsigned int_status;

	regmap_read(regmap, AT91_PMC_SR,_&status);

	return status & PLL_STATUS_MASK(id)? 1 : 0;
}

static int_clk_pll_prepare(struct_clk_hw *hw)
{
	struct clk_pll_*pll = to_clk_pll(hw);
	struct regmap *regmap = pll->regmap;
	const struct clk_pll_layout_*layout = pll->layout;
	const struct clk_pll_characteristics *characteristics_=
							pll->characteristics;
	u8 id =_pll->id;
	u32_mask_= PLL_