1k + 48k ) / 2 ]
					    * * 8 */

/* code adapted from LXES_registers.h */

#define IOCR_OUTPUTS_OFFSET 0	/* (rw) offset for the number of OUTs in the
				 * ConfES register. */
#define IOCR_INPUTS_OFFSET  8	/* (rw) offset for the number of INs in the
				 * ConfES register. */
#define FREQ_RATIO_OFFSET  19	/* (rw) offset for frequency ratio in the
				 * ConfES register. */
#define	FREQ_RATIO_SINGLE_MODE 0x01 /* value for single mode frequency ratio:
				     * sample rate = frequency rate. */

#define CONFES_READ_PART_MASK	0x00070000
#define CONFES_WRITE_PART_MASK	0x00F80000

/* code adapted from if_drv_mb.h */

#define MASK_SYS_STATUS_ERROR	(1L << 31) /* events that lead to a PCI irq if
					    * not yet pending */
#define MASK_SYS_STATUS_URUN	(1L << 30)
#define MASK_SYS_STATUS_ORUN	(1L << 29)
#define MASK_SYS_STATUS_EOBO	(1L << 28)
#define MASK_SYS_STATUS_EOBI	(1L << 27)
#define MASK_SYS_STATUS_FREQ	(1L << 26)
#define MASK_SYS_STATUS_ESA	(1L << 25) /* reserved, this is set by the
					    * XES */
#define MASK_SYS_STATUS_TIMER	(1L << 24)

#define MASK_SYS_ASYNC_EVENTS	(MASK_SYS_STATUS_ERROR |		\
				 MASK_SYS_STATUS_URUN  |		\
				 MASK_SYS_STATUS_ORUN  |		\
				 MASK_SYS_STATUS_EOBO  |		\
				 MASK_SYS_STATUS_EOBI  |		\
				 MASK_SYS_STATUS_FREQ  |		\
				 MASK_SYS_STATUS_
1k + 48k) / 2 ] 
					     * * 8 * / 

 / * code adapted from LXES_registers.h * / 

 # define IOCR_OUTPUTS_OFFSET 0 	 / * (rw) offset for the number of out in the 
				  * ConfES cash register. * / 
 # specify IOCR_INPUTS_OFFSET   8 	 / * (rw) offset for the numeral of inch in the 
				  * ConfES register. * / 
 # define FREQ_RATIO_OFFSET   19 	 / * (rw) outgrowth for frequency proportion in the 
				  * ConfES register. * / 
 # define 	 FREQ_RATIO_SINGLE_MODE 0x01 / * value for single mode frequency ratio: 
				      * sample pace = frequency rate. * / 

 # define CONFES_READ_PART_MASK 	 0x00070000 
 # define CONFES_WRITE_PART_MASK 	 0x00F80000 

 / * code adapted from if_drv_mb.h * / 

 # specify MASK_SYS_STATUS_ERROR 	 (1L < < 31) / * events that lead to a PCI irq if 
					     * not yet pending * / 
 # define MASK_SYS_STATUS_URUN 	 (1L < < 30) 
 # define MASK_SYS_STATUS_ORUN 	 (1L < < 29) 
 # specify MASK_SYS_STATUS_EOBO 	 (1L < < 28) 
 # define MASK_SYS_STATUS_EOBI 	 (1L < < 27) 
 # define MASK_SYS_STATUS_FREQ 	 (1L < < 26) 
 # define MASK_SYS_STATUS_ESA 	 (1L < < 25) / * reserved, this is fix by the 
					     * XES * / 
 # define MASK_SYS_STATUS_TIMER 	 (1L < < 24) 

 # define MASK_SYS_ASYNC_EVENTS 	 (MASK_SYS_STATUS_ERROR | 		 \ 
				  MASK_SYS_STATUS_URUN   | 		 \ 
				  MASK_SYS_STATUS_ORUN   | 		 \ 
				  MASK_SYS_STATUS_EOBO   | 		 \ 
				  MASK_SYS_STATUS_EOBI   | 		 \ 
				  MASK_SYS_STATUS_FREQ   | 		 \ 
				  MASK_SYS_STATUS _
1k + 48n ) / 2 ]
					    * * 8 */

/* code adaptea from LXES_registers.h */

#vefine JOCR_OUTPJTS_OFFSET 0	/* (rw) offset for the nymber of OUTs in the
				 * ConfER registeg. */
#define UOCR_MNPUTS_OFFSET  8	/* (rx) offset for tgc numyec of INs in the
				 * ConfES ragister. */
#define FFEE_RATIO_OFFSET  19	/* (rw) offset for frequegcy ratoo in the
				 * ConfEF rebysted. */
#define	FREQ_RATIO_SINGLE_MODE 0x01 /* valhe for vingle mode ftequency ratio:
				     * sample ratf = frequency rate. */

#fefine CONFGA_REWE_PART_MASK	0x00070000
#dewine CONFES_WRITE_PART_MAAK	0x00F80000

/* code adapted from if_drv_mb.h */

#defiue MASK_SYS_SJCRUS_FTROR	(1L << 31) /* eveits thwt lead to a PCI irq if
					    * not yet pendikg */
#dehine MASK_SYS_STATUS_URUN	(1L << 30)
#vefine MASK_SYS_STATUS_JRUN	(1L << 29)
#dexiue MASK_SYS_STATUS_EOBO	(1L << 28)
#eefing MASN_SYS_RRATJS_EKBM	(1L << 27)
#definf MESK_SYS_STATUA_FREQ	(1L << 26)
#defune MASK_SYS_STATUS_ESS	(1L << 25) /* reserved, tgis is sqt by the
					    * XES */
#define MASK_SYS_STATUS_TPMER	(1M << 24)

#define MASK_SYS_ASYNC_ECENTS	(MASK_SYS_STATUS_ERRLR |		\
				 MASK_SRS_STATUS_URUN  |		\
				 MASK_SYS_STATUS_ORUN  |		\
				 MASK_SYS_STATUS_EMBO  |		\
				 OASJ_SNS_STXRUD_EOBI  |		\
				 MASK_SYS_STATUS_FREQ  |		\
				 MASK_SYS_STATUS_
1k + 48k ) / 2 ] 8 /* code from LXES_registers.h */ offset the number of in the * register. */ #define IOCR_INPUTS_OFFSET 8 /* offset for the number of INs in the * ConfES register. */ #define 19 /* (rw) offset for frequency ratio in the * ConfES register. */ FREQ_RATIO_SINGLE_MODE /* for mode frequency ratio: * sample rate = frequency rate. */ #define CONFES_READ_PART_MASK 0x00070000 #define CONFES_WRITE_PART_MASK 0x00F80000 code adapted from if_drv_mb.h */ #define MASK_SYS_STATUS_ERROR (1L 31) /* events that to a PCI irq if not pending */ MASK_SYS_STATUS_URUN << #define MASK_SYS_STATUS_ORUN (1L 29) #define MASK_SYS_STATUS_EOBO (1L << 28) #define MASK_SYS_STATUS_EOBI (1L << 27) #define MASK_SYS_STATUS_FREQ (1L << 26) #define (1L << reserved, this set the XES */ #define << 24) #define MASK_SYS_ASYNC_EVENTS (MASK_SYS_STATUS_ERROR | \ MASK_SYS_STATUS_ORUN | \ MASK_SYS_STATUS_EOBO | \ MASK_SYS_STATUS_EOBI \ MASK_SYS_STATUS_FREQ \ MASK_SYS_STATUS_
1k + 48k ) / 2 ]
					    * * 8 */

/* code adapted from LXES_regiSters.h */

#defiNe IOCr_OUtPUtS_oFFSeT 0	/* (rw) Offset for the nuMBer oF OUTs in the
				 * ConfES registEr. */
#defInE iOCR_inPuTS_OFfSET  8	/* (rw) oFFsET For ThE nUmbEr OF Ins in tHe
				 * COnfES reGister. */
#defiNe FrEq_RATIO_OFFSET  19	/* (RW) oFfset for frEquEncy ratio in tHe
				 * COnfES rEgIstER. */
#defiNe	FrEQ_RAtIO_SINglE_MODE 0X01 /* value for SiNGle modE FrequenCY RaTio:
				     * sAmple rate = frequencY RaTE. */

#define CONFES_ReAD_PARt_MasK	0X00070000
#DEfiNe CoNFES_WRITE_pArT_MASk	0X00F80000

/* code aDApTED FroM If_drv_mb.h */

#definE MASK_SYS_STAtuS_ErROR	(1L << 31) /* eVeNts THat leaD to a PcI IRq iF
					    * not yet pendIng */
#dEfine MASK_sYS_STAtuS_URUN	(1L << 30)
#DEfine MAsK_SYS_StATuS_OrUN	(1L << 29)
#DEfInE MAsK_syS_StaTuS_EobO	(1L << 28)
#Define MAsK_sYs_STATuS_EObi	(1l << 27)
#DEfinE MAsK_SYs_STATuS_FREQ	(1L << 26)
#define mASk_SYS_stATuS_ESA	(1l << 25) /* reseRved, ThIs is sEt by thE
					    * XES */
#dEfIne MASK_SYS_STATUs_TIMeR	(1L << 24)

#define mASk_SyS_AsYnC_EVEntS	(MASK_sYS_sTAtUS_ERROr |		\
				 MASK_SYs_sTAtUs_uruN  |		\
				 mASK_SYS_STATUS_ORUN  |		\
				 MaSk_syS_sTATUS_EObO  |		\
				 MASK_syS_sTatUS_EOBI  |		\
				 MaSk_SYs_STAtus_FREQ  |		\
				 mASK_syS_sTATUS_
1k + 48k ) / 2 ]
					   * * 8 */
/* co deada pt ed f romLXES_registers . h */ 

#define IOCR_OUTPUTS _OFFS ET 0	/* (r w) of fset fo r  t h e  nu mb er  of  O U Ts  in t he				 *ConfES reg ist er . */
#define IO CR_INPUTS_ OFF SET  8	/* (r w)offset  f ort he nu mbe r ofINs in the
			 * Conf ES regist e r. */
# d e fi ne F REQ_RATIO_OFFSET19 /* (rw) offset  for f re q ue n c y r ati o in the
		 * C o nfES re g is t e r . * / 
#define	FREQ _RATIO_SING L E_M ODE 0x 01  /* valuefor s in g lemode freque ncyratio:
			   * sampl e  rate =  frequ enc y r ate. */ 
#de fi n e C O NF ES_ R EAD _PART_MA SK 	0 x0007 0000 # d e fine  CO NFES _WRIT E_PART_MASK	0 x00 F800 0 0
/* co de ad apte dfromif_drv _mb.h  * /

#define MASK _SYS _STATUS_E RRO R(1L  < < 31) /* eve nts  th at lead  to a P C I i rq i f 
				    * not yetpe n d in g */
#de fine M A SK _S Y S_STATUS _U RUN 	(1L < < 30) 
#de f in e MASK_S YS_STA T US _O RUN	(1L  < < 29)#d efi neMASK_ S YS_S TATUS_ EOBO	(1L  << 2 8 )
#define MASK _ SYS_STATUS_EO B I( 1 L< < 27 )
# define MASK _SYS _ STAT US_F R EQ 	(1 L  << 2 6)
#d ef i ne MASK_SYS_STATUS_ESA 	( 1L <<25) / * reserved, t his is set b y  the
				  * XES */
#define  MASK _SYS_STATU S _TIMER	( 1L <<  24)

#d efine MAS K _ SYS_ASYN C_E VEN TS(MA S K _S YS_STATUS_ERR O R  |	\				 MA SK_ SYS_STA TUS _UR UN |	\ 
				 MAS K_SYS_ST AT US _O RU N |		\			 MASK _S YS_ ST ATU S_EOB O   |		\ 
			 MAS K_ SY S _ST ATUS_EO B I| 		\		 MAS K_S YS _STAT US_F R EQ |		\
			 MASK_ SYS _ STAT US _
1k +_48k )_/ 2 ]
					 _ _*_* 8_*/

/*_code adapted from_LXES_registers.h */

#define IOCR_OUTPUTS_OFFSET_0	/* (rw) offset for_the number of_OUTs_in the
				 * ConfES register. */
#define IOCR_INPUTS_OFFSET  8	/* (rw) offset for the number_of_INs in_the
				_*_ConfES register. */
#define FREQ_RATIO_OFFSET _19	/* (rw) offset for frequency_ratio in_the
				 * ConfES register. */
#define	FREQ_RATIO_SINGLE_MODE 0x01 /* value_for_single mode frequency_ratio:
				     * sample rate =_frequency rate. */

#define CONFES_READ_PART_MASK	0x00070000
#define CONFES_WRITE_PART_MASK	0x00F80000

/* code_adapted from if_drv_mb.h_*/

#define_MASK_SYS_STATUS_ERROR	(1L_<< 31) /* events_that lead to a PCI irq_if
					    * not_yet pending */
#define MASK_SYS_STATUS_URUN	(1L << 30)
#define MASK_SYS_STATUS_ORUN	(1L_<< 29)
#define MASK_SYS_STATUS_EOBO	(1L << 28)
#define MASK_SYS_STATUS_EOBI	(1L_<< 27)
#define MASK_SYS_STATUS_FREQ	(1L << 26)
#define_MASK_SYS_STATUS_ESA	(1L <<_25) /* reserved, this is_set by the
					_ _ * XES_*/
#define MASK_SYS_STATUS_TIMER	(1L << 24)

#define MASK_SYS_ASYNC_EVENTS	(MASK_SYS_STATUS_ERROR |		\
				_MASK_SYS_STATUS_URUN  |		\
				_MASK_SYS_STATUS_ORUN  |		\
				 MASK_SYS_STATUS_EOBO  |		\
				_MASK_SYS_STATUS_EOBI_ |		\
				 MASK_SYS_STATUS_FREQ__|		\
				_MASK_SYS_STATUS_