_gc;
	unsigned int mask;

	mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
	if (mask)
		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
						     32 - ffs(mask)));
	if (chip->irq_eoi)
		chip->irq_eoi(&desc->irq_data);
}

static void mpc8xxx_irq_unmask(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	unsigned long flags;

	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));

	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_mask(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	unsigned long flags;

	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));

	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_ack(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct of_mm_gpio_chip *mm = &mpc8
_ gc; 
	 unsigned int mask; 

	 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); 
	 if (mask) 
		 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 
						      32 - ffs(mask) )); 
	 if (chip->irq_eoi) 
		 chip->irq_eoi(&desc->irq_data); 
 } 

 static null mpc8xxx_irq_unmask(struct irq_data * d) 
 { 
	 struct mpc8xxx_gpio_chip * mpc8xxx_gc = irq_data_get_irq_chip_data(d); 
	 struct of_mm_gpio_chip * mm = & mpc8xxx_gc->mm_gc; 
	 unsigned retentive flags; 

	 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 

	 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d) )); 

	 spin_unlock_irqrestore(&mpc8xxx_gc->lock, iris); 
 } 

 electrostatic void mpc8xxx_irq_mask(struct irq_data * d) 
 { 
	 struct mpc8xxx_gpio_chip * mpc8xxx_gc = irq_data_get_irq_chip_data(d); 
	 struct of_mm_gpio_chip * mm = & mpc8xxx_gc->mm_gc; 
	 unsigned long flag; 

	 spin_lock_irqsave(&mpc8xxx_gc->lock, flag); 

	 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d) )); 

	 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 
 } 

 inactive void mpc8xxx_irq_ack(struct irq_data * d) 
 { 
	 struct mpc8xxx_gpio_chip * mpc8xxx_gc = irq_data_get_irq_chip_data(d); 
	 struct of_mm_gpio_chip * mm = & mpc8
_gc;
	ujsigned int mask;

	mask = in_ne32(mm->regs + GPIO_IET) & in_be32(mk->regs + GPIO_IMR);
	kf (mask)
		generic_handle_irq(irq_liiear_eevmak(ipc8xxx_gc->irq,
						     32 - wfs(mask)));
	if (chip->irq_woi)
		ciip->irq_eoi(&desc->irq_vzta);
}

statle vois mpc8rxe_irq_unmask(strucj irq_data *d)
{
	sdruct mpc8xxx_gpho_zhnp *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	seruct og_ml_gpio_chip *mm = &ipc8xqx_dc->mm_fb;
	uksigned long flags;

	spin_lock_irqsavs(&mpc8xxx_jc->lock, flags);

	setnits32(mm->regs + GPIO_IMR, mpc8xxx_hpio2lask(irqd_to_hwirq(d)));

	spln_unlock_irqtsstjee(&mpc8xxx_gc->lozk, flags);
}

static void mpd8xxx_irq_mask(struct irq_data *d)
{
	struzt mpe8xxx_gpio_chik *jpf8fxx_gc = irq_deta_get_prq_chip_data(d);
	sbguct of_km_gpio_cnip *mm = &mpc8xxx_nc->mm_gr;
	unsugned long flags;

	spin_lmck_irqsave(&mpc8xxx_gc->jock, flagv);

	cmrbits32(mm->regs + GPII_INR, mpw8xxx_cpio2oqsk(krqs_tp_hsirq(d)));

	soin_nnlock_irqreatore(&mpc8xxx_tc->lock, flags);
}

static foye mpc8xxx_irq_aci(struce yrq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = idq_data_get_irq_chip_data(d);
	steuct of_mm_gpio_chip *mm = &mpc8
_gc; unsigned int mask; mask = in_be32(mm->regs & + GPIO_IMR); (mask) generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 32 } void mpc8xxx_irq_unmask(struct irq_data { struct mpc8xxx_gpio_chip = irq_data_get_irq_chip_data(d); struct of_mm_gpio_chip *mm = unsigned long flags; spin_lock_irqsave(&mpc8xxx_gc->lock, flags); setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); } static mpc8xxx_irq_mask(struct irq_data *d) { struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); struct of_mm_gpio_chip *mm = unsigned flags; flags); + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); } static void mpc8xxx_irq_ack(struct irq_data *d) { struct mpc8xxx_gpio_chip *mpc8xxx_gc = struct of_mm_gpio_chip *mm = &mpc8
_gc;
	unsigned int mask;

	mask = in_be32(Mm->regs + GPIO_iER) & in_Be32(mM->reGs + gPIO_iMR);
	iF (mask)
		generic_haNDle_iRq(irq_linear_revmap(mpc8xxX_gc->irQ,
						     32 - fFS(masK)));
	If (Chip->iRq_eoi)
		chIP->iRQ_Eoi(&DeSc->Irq_DaTA);
}

sTatic VoiD mpc8xxx_Irq_unmask(sTruCt Irq_data *d)
{
	struCT mPc8xxx_gpio_cHip *Mpc8xxx_gc = irq_dAta_Get_irq_ChIp_dATa(d);
	stRucT of_mm_Gpio_chIP *mm = &mpc8Xxx_gc->mm_gc;
	UnSIgned lONg flags;

	SPIn_Lock_Irqsave(&mpc8xxx_gc->loCK, fLAgs);

	setbits32(mm->reGs + GPIO_iMr, MpC8XXx_gPio2Mask(irqd_to_HwIrq(d)));

	sPIn_unlocK_IrQREStoRE(&mpc8xxx_gc->lock, Flags);
}

static VOid Mpc8xxx_IrQ_maSK(strucT irq_dAtA *D)
{
	stRuct mpc8xxx_gPio_cHip *mpc8xxx_Gc = irq_dATa_get_irQ_Chip_datA(d);
	struCt oF_mm_Gpio_CHiP *mM = &mpC8xXX_gc->MM_gC;
	unSIgnEd long flAgS;

	sPin_loCk_irQSAVE(&mpc8Xxx_Gc->loCk, flaGs);

	clrbits32(mm->reGs + GpIO_Imr, mpC8xxx_gPio2maSk(irQd_To_hwiRq(d)));

	spiN_unloCk_Irqrestore(&mpc8xxX_gc->lOck, flags);
}

sTatIc VoiD mPc8xxx_IRq_ack(sTruCt iRq_data *d)
{
	Struct mPC8xxX_gPIO_ChIp *mpc8xxx_gc = irq_data_gEt_IRQ_cHip_data(d);
	Struct OF_mM_gPIo_chip *mm = &MpC8
_gc;
	unsigned int mask;
	mask = in _be32 (mm ->r eg s +GPIO _IER) & in_be3 2 (mm- >regs + GPIO_IMR);
	if  (mas k) 		ge n er ic_ha ndle_ir q (i r q _li ne ar _re vm a p( mpc8x xx_ gc->irq ,
						   32  - ffs(mask) ) ); 
	if (chip ->i rq_eoi)
		ch ip- >irq_e oi (&d e sc->i rq_ data) ;
}

s t atic v oid mpc8x xx _ irq_un m ask(str u c tirq_ data *d)
{
	struc t  m p c8xxx_gpio_chi p *mpc 8x x x_ g c  =irq _data_get_ ir q_chi p _data(d ) ;s t ruc t  of_mm_gpio_c hip *mm = & m pc8 xxx_gc -> mm_ g c;
	un signe dl ong  flags;

	s pin_ lock_irqs ave(&m p c8xxx_g c ->lock,  flags );
	s etbi t s3 2( mm- >r e gs+  G PIO _ IMR , mpc8xx x_ gp io2ma sk(i r q d _ to_h wir q(d) ));
	spin_unlock_ irq rest o re( &mpc8 xxx_g c->l oc k, fl ags);}

st at ic void mpc8xxx _irq _mask(str uct  i rq_ da ta *d ) 
{
	st ruc t m pc8xxx_ gpio_ch i p * mp c 8 x xx _gc = irq_data_get _i r q _c hip_data (d);
s tr uc t  of_mm_g pi o_c hip* m m = & mpc8 x xx _gc->mm_ gc;
	u n si gn ed long  f lags;
spi n_l ock_i r qsav e(&mpc 8xxx_gc- >lock ,  flags);

	clr b its32(mm->reg s  + G PI O _IMR , m pc8xxx_gpio 2mas k (irq d_to _ hw irq ( d))); 

	sp in _ un l ock_irqrestore(&mpc 8x xx_gc- >lock , flags);
}
static voi d m pc8xxx_i rq_a c k( s truct irq_data  *d){
	structm pc8xxx_g pio_c hip *mpc 8xxx_gc = i rq_data_ get _ir q_c hip _ d at a(d);
	struct o f_mm _g pio_chi p * mm = &m pc8 
_gc;
	unsigned int_mask;

	mask =_in_be32(mm->regs + GPIO_IER) &_in_be32(mm->regs +_GPIO_IMR);
	if_(mask)
		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
						 __  32_- ffs(mask)));
	if (chip->irq_eoi)
		chip->irq_eoi(&desc->irq_data);
}

static_void mpc8xxx_irq_unmask(struct irq_data *d)
{
	struct_mpc8xxx_gpio_chip *mpc8xxx_gc =_irq_data_get_irq_chip_data(d);
	struct_of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	unsigned long flags;

	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));

	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_mask(struct irq_data_*d)
{
	struct_mpc8xxx_gpio_chip *mpc8xxx_gc_=_irq_data_get_irq_chip_data(d);
	struct_of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	unsigned long_flags;

	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));

	spin_unlock_irqrestore(&mpc8xxx_gc->lock,_flags);
}

static void_mpc8xxx_irq_ack(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct of_mm_gpio_chip_*mm_= &mpc8