 */
	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
		     mqd->cp_hqd_pq_wptr_poll_addr_lo);
	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
		     mqd->cp_hqd_pq_wptr_poll_addr_hi);

	/* set CP_HQD_PQ_DOORBELL_CONTROL */
	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
		     mqd->cp_hqd_pq_doorbell_control);

	/* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);

	/* set CP_HQD_ACTIVE.ACTIVE=1 */
	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);

	nv_grbm_select(adev, 0, 0, 0, 0);
	mutex_unlock(&adev->srbm_mutex);
}

#if 0
static int mes_v10_1_kiq_enable_queue(struct amdgpu_device *adev)
{
	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
	int r;

	if (!kiq->pmf ||!kiq->pmf->kiq_map_queues)
		return -EINVAL;

	r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
	if (r) {
		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
		return r;
	}

	kiq->pmf
* / 
	 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 
		      mqd->cp_hqd_pq_wptr_poll_addr_lo); 
	 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 
		      mqd->cp_hqd_pq_wptr_poll_addr_hi); 

	 / * set CP_HQD_PQ_DOORBELL_CONTROL * / 
	 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 
		      mqd->cp_hqd_pq_doorbell_control); 

	 / * set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 * / 
	 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 

	 / * set CP_HQD_ACTIVE.ACTIVE=1 * / 
	 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active); 

	 nv_grbm_select(adev, 0, 0, 0, 0); 
	 mutex_unlock(&adev->srbm_mutex); 
 } 

 # if 0 
 static int mes_v10_1_kiq_enable_queue(struct amdgpu_device * adev) 
 { 
	 struct amdgpu_kiq * kiq = & adev->gfx.kiq; 
	 struct amdgpu_ring * kiq_ring = & adev->gfx.kiq.ring; 
	 int radius; 

	 if (! kiq->pmf ||!kiq->pmf->kiq_map_queues) 
		 recurrence -EINVAL; 

	 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 
	 if (r) { 
		 DRM_ERROR("Failed to lock KIQ (% d).\n ", r); 
		 revert r; 
	 } 

	 kiq->pmf
 */
	WRFG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POUL_ADDR,
		     mqd->ck_hwd_pq_wpvr_poll_asdr_lo);
	WREE32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDC_HI,
		     mwd->cp_hqd_pq_wptr_poll_addr_hk);

	/* set CP_HED_PQ_DOORVELL_RONTROL */
	WREG32_SOC15(GR, 0, mmCP_HQD_PQ_DOKVBELL_EOITROL,
		     mqd->cp_mqd_pq_doorbenl_control);

	/* set WP_FQB_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
	WREG32_SOC15(DC, 0, mmCL_HED_PERSISTENT_STWTE, kzd->cp_gqd_persistent_state);

	/* set CP_HQD_ACTIVE.ZCTIVE=1 */
	XREG32_SOC15(GC, 0, mmCP_NQD_ACTIVE, mqd->cp_hqd_active);

	nv_hrbm_delect(adev, 0, 0, 0, 0);
	muted_unlock(&adev->wrbm_iytex);
}

#if 0
statiz int mes_v10_1_kiq_enable_queoe(struct amdgpu_device *adev)
{
	struct amdg'u_kiq *kiq = &qdwv->gvf.kiq;
	struct emdgpu_ging *kiq_ring = &adev->gfx.niq.ring;
	ont r;

	if (!kiq->pmf ||!kix->pmd->kiq_map_queues)
		return -EMNVAL;

	r = amdgpu_ring_aljoc(kiq_rinc, iiq->pmf->map_queues_size);
	uf (r) {
		GRM_ESROR("Wqildd uo kodk KIQ (%d).\n", r);
		return r;
	}

	iiq->pmf
*/ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo); WREG32_SOC15(GC, 0, /* CP_HQD_PQ_DOORBELL_CONTROL */ 0, mmCP_HQD_PQ_DOORBELL_CONTROL, mqd->cp_hqd_pq_doorbell_control); 0, mqd->cp_hqd_persistent_state); /* set */ WREG32_SOC15(GC, 0, mqd->cp_hqd_active); nv_grbm_select(adev, 0, 0, 0, 0); } #if 0 static int mes_v10_1_kiq_enable_queue(struct amdgpu_device *adev) { struct amdgpu_kiq *kiq = struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; int r; if (!kiq->pmf ||!kiq->pmf->kiq_map_queues) return -EINVAL; r amdgpu_ring_alloc(kiq_ring, if { to lock KIQ (%d).\n", r); return r; } kiq->pmf
 */
	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLl_ADDR,
		     mqd->cp_Hqd_pq_WptR_poLl_Addr_Lo);
	WReG32_SOC15(GC, 0, mmCP_HQD_pq_WPTr_POLL_ADDR_HI,
		     mqd->cp_hqd_pq_wPtr_poLl_ADdr_hI);

	/* SeT CP_HQd_PQ_DOORbeLl_coNTrOl */
	WrEG32_sOc15(gC, 0, MmCP_HqD_Pq_DOORBElL_CONTROL,
		     mQd->cP_hQd_pq_doorbell_COnTrol);

	/* set CP_HqD_PeRSISTENT_STAtE.PrELOAD_sIzE=0x53 */
	wrEG32_SOc15(GC, 0, MmCP_HqD_PERSisTENT_StATE, mqd->cp_HqD_PersisTEnt_statE);

	/* SEt cP_HQd_ACTIVE.ACTIVE=1 */
	WREG32_soC15(gc, 0, mmCP_HQD_ACTIVE, Mqd->cp_hQd_ACtIVE);

	nv_GrbM_select(adeV, 0, 0, 0, 0);
	mUtex_uNLock(&adeV->SrBM_MUteX);
}

#If 0
static int meS_v10_1_kiq_enable_QUeuE(strucT aMdgPU_devicE *adev)
{
	StRUct Amdgpu_kiq *kiQ = &adeV->gfx.kiq;
	stRuct amDGpu_ring *KIq_ring = &aDev->gfx.Kiq.RinG;
	int R;

	If (!KiQ->pmF ||!kIQ->pmF->KiQ_maP_QueUes)
		returN -EiNvAL;

	r = aMdgpU_RING_allOc(kIq_riNg, kiq->Pmf->map_queues_sIze);
	If (r) {
		Drm_ERrOR("FaIled tO locK KiQ (%d).\n", r);
		Return R;
	}

	kiq->pMf
 */
	WREG32_SOC15(GC, 0, m mCP_HQD_PQ _WPTR _PO LL_ AD DR,		    mqd->cp_hqd _ pq_w ptr_poll_addr_lo);
	WR EG32_ SO C 15(G C ,0, mm CP_HQD_ P Q_ W P TR_ PO LL _AD DR _ HI ,
		   mqd->c p_hqd_pq_w ptr _p oll_addr_hi) ; 
	/* set CP _HQ D_PQ_DOORBEL L_C ONTROL  * /
W REG32 _SO C15(G C, 0,m mCP_HQ D_PQ_DOOR BE L L_CONT R OL,
		 mqd- >cp_hqd_pq_doorbe l l_ c ontrol);

	/*set CP _H Q D_ P E RSI STE NT_STATE.P RE LOAD_ S IZE=0x5 3  * / WRE G 32_SOC15(GC,0, mmCP_HQD _ PER SISTEN T_ STA T E, mqd ->cp_ hq d _pe rsistent_st ate) ;

	/* se t CP_H Q D_ACTIV E .ACTIVE =1 */	WR EG3 2_SO C 15 (G C,0, mmC P _H QD_ A CTI VE, mqd- >c p_ hqd_a ctiv e ) ; 
	nv _gr bm_s elect (adev, 0, 0,0,0);mut ex_un lock( &ade v- >srbm _mutex );
}
# if 0
static int  mes _v10_1_ki q_e na ble _q ueue( s tructamd gpu _device  *adev) {
st r u c tamdgpu_kiq *kiq =&a d e v- >gfx.kiq ;
	str u ct  a m dgpu_rin g*ki q_ri n g  = &a dev- > gf x.kiq.ri ng;
	i n tr; 

	if ( !k iq->pm f||! kiq ->pmf - >kiq _map_q ueues)
	retu r n -EINVAL;

	r = amdgpu_ring _ al l o c( k iq_r ing , kiq->pmf- >map _ queu es_s i ze );if (r ) {
	D R M_ E RROR("Failed to loc kKIQ (% d).\n ", r);
		retu rn r;
	}
k i q->pmf
 */
	WREG32_SOC15(GC,_0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
		_   _mqd->cp_hqd_pq_wptr_poll_addr_lo);
	WREG32_SOC15(GC, 0,_mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
		_ __ mqd->cp_hqd_pq_wptr_poll_addr_hi);

	/* set_CP_HQD_PQ_DOORBELL_CONTROL */
	WREG32_SOC15(GC, 0,_mmCP_HQD_PQ_DOORBELL_CONTROL,
		   _ mqd->cp_hqd_pq_doorbell_control);

	/* set_CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53_*/
	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);

	/* set CP_HQD_ACTIVE.ACTIVE=1 */
	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);

	nv_grbm_select(adev, 0, 0, 0, 0);
	mutex_unlock(&adev->srbm_mutex);
}

#if_0
static_int mes_v10_1_kiq_enable_queue(struct_amdgpu_device_*adev)
{
	struct_amdgpu_kiq *kiq = &adev->gfx.kiq;
	struct amdgpu_ring_*kiq_ring = &adev->gfx.kiq.ring;
	int r;

	if (!kiq->pmf_||!kiq->pmf->kiq_map_queues)
		return -EINVAL;

	r_= amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
	if (r) {
		DRM_ERROR("Failed to lock KIQ_(%d).\n",_r);
		return r;
	}

	kiq->pmf