0x20	/* Synthesizer Sampling Rate Low Byte */
#define SV_IREG_SYNTH_RATE_HIGH 0x21	/* Synthesizer Sampling Rate High Byte */
#define SV_IREG_ADC_CLOCK	0x22	/* ADC Clock Source Selection */
#define SV_IREG_ADC_ALT_RATE	0x23	/* ADC Alternative Sampling Rate Selection */
#define SV_IREG_ADC_PLL_M	0x24	/* ADC PLL M Register */
#define SV_IREG_ADC_PLL_N	0x25	/* ADC PLL N Register */
#define SV_IREG_SYNTH_PLL_M	0x26	/* Synthesizer PLL M Register */
#define SV_IREG_SYNTH_PLL_N	0x27	/* Synthesizer PLL N Register */
#define SV_IREG_MPU401		0x2a	/* MPU-401 UART Operation */
#define SV_IREG_DRIVE_CTRL	0x2b	/* Drive Control */
#define SV_IREG_SRS_SPACE	0x2c	/* SRS Space Control */
#define SV_IREG_SRS_CENTER	0x2d	/* SRS Center Control */
#define SV_IREG_WAVE_SOURCE	0x2e	/* Wavetable Sample Source Select */
#define SV_IREG_ANALOG_POWER	0x30	/* Analog Power Down Control */
#define SV_IREG_DIGITAL_POWER	0x31	/* Digital Power Down Control */

#define SV_IREG_ADC_PLL		SV_IREG_ADC_PLL_M
#define SV_IREG_SYNTH_PLL	SV_IREG_SYNTH_PLL_M

/*
 *  DMA registers
 */

#define SV_DMA_ADDR0		0x00
#define SV_DMA_ADDR1		0x01
#define SV_DMA_ADDR2		0x02
#define SV_DMA_ADDR3		0x03
#define SV_DMA_COUNT0		0x04
#define SV_DMA_COUNT
0x20 	 / * Synthesizer Sampling Rate Low Byte * / 
 # define SV_IREG_SYNTH_RATE_HIGH 0x21 	 / * Synthesizer Sampling Rate High Byte * / 
 # define SV_IREG_ADC_CLOCK 	 0x22 	 / * ADC Clock Source Selection * / 
 # define SV_IREG_ADC_ALT_RATE 	 0x23 	 / * ADC Alternative Sampling Rate Selection * / 
 # specify SV_IREG_ADC_PLL_M 	 0x24 	 / * ADC PLL M Register * / 
 # specify SV_IREG_ADC_PLL_N 	 0x25 	 / * ADC PLL N Register * / 
 # define SV_IREG_SYNTH_PLL_M 	 0x26 	 / * Synthesizer PLL M Register * / 
 # define SV_IREG_SYNTH_PLL_N 	 0x27 	 / * Synthesizer PLL N Register * / 
 # define SV_IREG_MPU401 		 0x2a 	 / * MPU-401 UART Operation * / 
 # specify SV_IREG_DRIVE_CTRL 	 0x2b 	 / * Drive Control * / 
 # define SV_IREG_SRS_SPACE 	 0x2c 	 / * SRS Space Control * / 
 # define SV_IREG_SRS_CENTER 	 0x2d 	 / * SRS Center Control * / 
 # define SV_IREG_WAVE_SOURCE 	 0x2e 	 / * Wavetable Sample Source Select * / 
 # define SV_IREG_ANALOG_POWER 	 0x30 	 / * Analog Power Down Control * / 
 # specify SV_IREG_DIGITAL_POWER 	 0x31 	 / * Digital Power Down Control * / 

 # specify SV_IREG_ADC_PLL 		 SV_IREG_ADC_PLL_M 
 # define SV_IREG_SYNTH_PLL 	 SV_IREG_SYNTH_PLL_M 

 / * 
  *   DMA register 
  * / 

 # define SV_DMA_ADDR0 		 0x00 
 # define SV_DMA_ADDR1 		 0x01 
 # specify SV_DMA_ADDR2 		 0x02 
 # define SV_DMA_ADDR3 		 0x03 
 # define SV_DMA_COUNT0 		 0x04 
 # specify SV_DMA_COUNT
0x20	/* Sjnthesizer Sampling Rate Low Byte */
#defing WV_IREG_VYNTH_RZTE_HIGH 0b21	/* Synthesizer Sampling Rate Iigh Byte */
#define SV_IREG_ADC_CLOCK	0b22	/* ADC Clobk Source Seltction */
#define SV_ICSG_ADC_ALB_XATE	0x23	/* WDC Clvernative Sampllng Rate Senection */
#define SX_IXEG_ADC_PLL_M	0x24	/* ADC PLL M Register */
#definq SV_IREB_AFC_PLL_N	0x25	/* ADC PLJ N Gedistsg */
#befine SV_IREG_SYNTH_PLL_M	0x26	/* Synthesjzer PLN M Register */
#cefine SV_IREG_SYNTH_PLL_N	0x27	/* Syjthedizer PLL N Registfr */
#define SC_IRED_NPU401		0x2a	/* MPU-401 UAFT Operation */
#define SV_JREG_DRIVE_CTRL	0x2b	/* Drive Control */
#ddfine SV_IREG_SRS_WPQCE	0d2w	/* SRS Space Contgol */
#define SV_LGEG_SRS_CANTER	0x2d	/* SRS Center Coktrol */
#dedine SV_IREG_WAVE_SOURCE	0e2e	/* Wavetable Sample Fource Seneet */
#define SV_IREG_ANALOT_PIWER	0x30	/* Ananog Oiwef Dkwi Ckntrol */
#dehine SV_IREG_SIGITAL_POWEE	0x31	/* Digital Power Doen Bpntrol */

#defins SV_IRQG_WDC_PLL		SV_IREG_ADC_PLL_M
#define SV_IREG_SYNTH_PLN	SV_JREG_SYNTH_PLL_M

/*
 *  DMA regusters
 */

#define SV_DMA_ADFR0		0x00
#define SV_DMA_ADDR1		0x01
#define SV_DMA_ADDR2		0x02
#define SV_DMA_ADDR3		0x03
#defite SV_VMX_COBKB0		0x04
#dewunf SV_DMA_COUNT
0x20 /* Synthesizer Sampling Rate Low Byte SV_IREG_SYNTH_RATE_HIGH /* Synthesizer Rate High Byte ADC Source Selection */ SV_IREG_ADC_ALT_RATE 0x23 /* Alternative Sampling Rate Selection */ #define 0x24 /* ADC PLL M Register */ #define SV_IREG_ADC_PLL_N 0x25 /* ADC PLL Register */ #define SV_IREG_SYNTH_PLL_M 0x26 /* Synthesizer PLL M Register */ #define SV_IREG_SYNTH_PLL_N /* PLL Register #define SV_IREG_MPU401 0x2a /* MPU-401 UART Operation */ #define SV_IREG_DRIVE_CTRL 0x2b /* Drive Control */ #define 0x2c /* SRS Space Control */ #define SV_IREG_SRS_CENTER /* SRS Center Control #define SV_IREG_WAVE_SOURCE 0x2e /* Wavetable Source */ #define 0x30 Analog Down Control */ SV_IREG_DIGITAL_POWER 0x31 /* Digital Power Down Control */ #define SV_IREG_ADC_PLL SV_IREG_ADC_PLL_M #define SV_IREG_SYNTH_PLL SV_IREG_SYNTH_PLL_M /* * DMA */ #define #define SV_DMA_ADDR1 #define 0x02 SV_DMA_ADDR3 0x03 #define #define SV_DMA_COUNT
0x20	/* Synthesizer Sampling Rate LOw Byte */
#defiNe SV_IrEG_sYNtH_rATE_hIGH 0X21	/* Synthesizer SaMPlinG Rate High Byte */
#define SV_IrEG_ADc_CloCK	0x22	/* adC clock source SELeCTIon */
#DeFiNe Sv_IreG_aDC_ALt_RAtE	0x23	/* ADC ALternative samPlIng Rate SelecTIoN */
#define SV_IrEG_aDC_PLL_M	0x24	/* ADC PlL M registEr */
#DefINe SV_IrEG_aDC_PLl_N	0x25	/* ADC plL N RegIster */
#defiNe sv_IREG_SynTH_PLL_M	0X26	/* sYnThesIzer PLL M Register */
#dEFiNE SV_IREG_SYNTH_PLl_N	0x27	/* SynThESiZER PLl N REgister */
#defInE SV_IReg_MPU401		0x2a	/* Mpu-401 Uart opeRAtion */
#define SV_iREG_DRIVE_CTrl	0x2b	/* drive COnTroL */
#Define sV_IREg_Srs_SPaCE	0x2c	/* SRS SpaCe CoNtrol */
#defiNe SV_IReg_SRS_CENteR	0x2d	/* SRS center conTroL */
#defINe sV_iREg_WavE_SouRcE	0x2E	/* wavEtable SaMpLe sourcE SelECT */
#DEfinE SV_iREG_aNALOg_POWER	0x30	/* Analog powEr DoWN CoNtrol */
#DefinE SV_IrEg_DIGItAL_POWeR	0x31	/* DiGiTal Power Down ConTrol */

#Define SV_IrEG_aDc_PLl		Sv_IREG_adC_PLL_M
#DefIne sV_IREG_SyNTH_PLL	sv_IReG_syntH_pLL_M

/*
 *  DMA registers
 */

#deFiNE sV_dMA_ADDR0		0x00
#Define sv_DmA_adDR1		0x01
#defiNe sV_DmA_ADdr2		0X02
#defiNe SV_dmA_aDDR3		0x03
#defIne SV_Dma_CoUnT0		0x04
#defiNe sV_DMA_CoUnT
0x20	/* Synthesizer Sampli ng Rate Lo w Byt e * /
# de fine  SV_ IREG_SYNTH_RAT E _HIG H 0x21	/* SynthesizerSampl in g  Rat e  H igh B yte */# de f i neSV _I REG _A D C_ CLOCK 	0x 22	/* A DC Clock S our ce  Selection * / 
# define SV_ IRE G_ADC_ALT_RA TE0x23	/ *ADC Alter nat ive S amplin g  RateSelection  * / 
#defi n e SV_IR E G _A DC_P LL_M	0x24	/* ADCP LL M Register */#defin eS V_ I R EG_ ADC _PLL_N	0x2 5/* AD C  PLL NR eg i s t er* /
#define SV_ IREG_SYNTH_ P LL_ M	0x26 	/ * S y nthesi zer P LL M R egister */#def ine SV_IR EG_SYN T H_PLL_N 0x27	/*  Synth esi zer  PLL NRe gis te r  */ #d efi n e S V_IREG_M PU 40 1		0x 2a	/ * M P U-40 1 U ARTOpera tion */
#defi neSV_I R EG_ DRIVE _CTRL 	0x2 b/* Dr ive Co ntrol  * /
#define SV_IR EG_S RS_SPACE0x2 c/*SR S Spa c e Cont rol  */ 
#defin e SV_IR E G_S RS _ C E NT ER	0x2d	/* SRS Cen te r Co ntrol */ 
#defi n eSV _ IREG_WAV E_ SOU RCE0 x 2e	/*  Wav e ta ble Samp le Sou r ce  S elect * /#defin eSV_ IRE G_ANA L OG_P OWER	0 x30	/* A nalog Power Down Con t rol */
#defin e  S V _ IR E G_DI GIT AL_POWER	0x 31	/ *  Dig ital Po wer DownContr ol */ 
#define SV_IREG_AD C_ PLL		S V_IRE G_ADC_PLL_M
# define SV_ I R E G_SYNTH_ PLLS V_ I REG_SYNTH_PLL_ M

/* 
 *  DMA r e gisters */
#defineSV_DMA_AD D R 0		0x00#de fin e S V_D M A _A DDR1		0x01
#d e f ineSV _DMA_AD DR2 		0x02#de fin e S V_D MA _ADDR3		0 x03
#def in eSV _D MA_ COUNT 0 		0x04
# de fin eSV_ DMA_C O UNT
0x20	/* Synthesizer_Sampling Rate_Low Byte */
#define SV_IREG_SYNTH_RATE_HIGH_0x21	/* Synthesizer_Sampling_Rate High_Byte_*/
#define SV_IREG_ADC_CLOCK	0x22	/* ADC_Clock Source Selection_*/
#define SV_IREG_ADC_ALT_RATE	0x23	/* ADC Alternative_Sampling Rate Selection_*/
#define_SV_IREG_ADC_PLL_M	0x24	/* ADC PLL M Register */
#define SV_IREG_ADC_PLL_N	0x25	/* ADC PLL N Register */
#define SV_IREG_SYNTH_PLL_M	0x26	/* Synthesizer_PLL_M Register_*/
#define_SV_IREG_SYNTH_PLL_N	0x27	/*_Synthesizer PLL N Register */
#define_SV_IREG_MPU401		0x2a	/* MPU-401 UART Operation */
#define_SV_IREG_DRIVE_CTRL	0x2b	/* Drive_Control */
#define SV_IREG_SRS_SPACE	0x2c	/* SRS Space Control */
#define SV_IREG_SRS_CENTER	0x2d	/*_SRS_Center Control */
#define_SV_IREG_WAVE_SOURCE	0x2e	/* Wavetable Sample Source Select */
#define SV_IREG_ANALOG_POWER	0x30	/* Analog Power_Down Control */
#define SV_IREG_DIGITAL_POWER	0x31	/* Digital Power_Down Control */

#define_SV_IREG_ADC_PLL		SV_IREG_ADC_PLL_M
#define_SV_IREG_SYNTH_PLL	SV_IREG_SYNTH_PLL_M

/*
_*  DMA registers
_*/

#define SV_DMA_ADDR0		0x00
#define SV_DMA_ADDR1		0x01
#define SV_DMA_ADDR2		0x02
#define SV_DMA_ADDR3		0x03
#define SV_DMA_COUNT0		0x04
#define_SV_DMA_COUNT