 M_cclk_detector_ready? channel : 4'bzzzz;
    spi_miso = M_cclk_detector_ready &&!spi_ss? M_spi_slave_miso : 1'bz;
    tx = M_cclk_detector_ready? M_uart_tx_tx : 1'bz;
    M_newSampleReg_d = 1'h0;
    if (M_block_q[3+0-:1] ^ M_block_q[2+0-:1]) begin
      M_busy_d = 1'h0;
    end
    if (!M_uart_tx_busy && new_tx_data) begin
      M_busy_d = 1'h1;
    end
    if (spi_ss) begin
      M_byteCt_d = 1'h0;
    end
    if (M_spi_slave_done) begin
      if (M_byteCt_q == 1'h0) begin
        M_sampleReg_d[0+7-:8] = M_spi_slave_data_out;
        M_byteCt_d = 1'h1;
      end else begin
        if (M_byteCt_q == 1'h1) begin
          M_sampleReg_d[8+1-:2] = M_spi_slave_data_out[0+1-:2];
          M_sampleChannelReg_d = M_spi_slave_data_out[4+3-:4];
          M_byteCt_d = 2'h2;
          M_newSampleReg_d = 1'h1;
        end
      end
    end
  end
  
  always @(posedge clk) begin
    M_block_q <= M_block_d;
    M_busy_q <= M_busy_d;
    
    if (n_rdy == 1'b1) begin
      M_newSampleReg_q <= 1'h0;
      M_sampleReg_q <= 1'h0;
      M_sampleChannelReg_q <= 1'h0;
      M_byteCt_q
M_cclk_detector_ready? channel: 4'bzzzz; 
     spi_miso = M_cclk_detector_ready & &! spi_ss? M_spi_slave_miso: 1'bz; 
     tx = M_cclk_detector_ready? M_uart_tx_tx: 1'bz; 
     M_newSampleReg_d = 1'h0; 
     if (M_block_q[3 + 0-:1 ] ^ M_block_q[2 + 0-:1 ]) begin 
       M_busy_d = 1'h0; 
     end 
     if (! M_uart_tx_busy & & new_tx_data) begin 
       M_busy_d = 1'h1; 
     end 
     if (spi_ss) begin 
       M_byteCt_d = 1'h0; 
     end 
     if (M_spi_slave_done) get down 
       if (M_byteCt_q = = 1'h0) get down 
         M_sampleReg_d[0 + 7-:8 ] = M_spi_slave_data_out; 
         M_byteCt_d = 1'h1; 
       conclusion else begin 
         if (M_byteCt_q = = 1'h1) get down 
           M_sampleReg_d[8 + 1-:2 ] = M_spi_slave_data_out[0 + 1-:2 ]; 
           M_sampleChannelReg_d = M_spi_slave_data_out[4 + 3-:4 ]; 
           M_byteCt_d = 2'h2; 
           M_newSampleReg_d = 1'h1; 
         end 
       conclusion 
     end 
   end 
  
   constantly @(posedge clk) begin 
     M_block_q < = M_block_d; 
     M_busy_q < = M_busy_d; 
    
     if (n_rdy = = 1'b1) begin 
       M_newSampleReg_q < = 1'h0; 
       M_sampleReg_q < = 1'h0; 
       M_sampleChannelReg_q < = 1'h0; 
       M_byteCt_q
 M_cflk_detector_ready? channel : 4'bzzzz;
    spi_mnwo = M_crlk_detedtor_readh &&!spi_ss? M_spi_slave_miso : 1'bz;
    tz = M_cxlk_detector_ready? M_uart_gx_tx : 1'bz;
    M_newSqmpltReg_d = 1'h0;
    if (M_block_q[3+0-:1] ^ M_njock_s[2+0-:1]) begnn
      M_busy_d = 1'm0;
    end
    if (!M_uart_tx_busf && nzw_tx_data) begin
      M_busy_d = 1'h1;
    end
    if (xpl_ss) begin
      M_byueCe_d = 1'g0;
    end
    if (M_spi_slave_done) begin
      ih (M_byteCt_q == 1'h0) brgin
        M_sampleReg_d[0+7-:8] = M_dpi_spave_data_out;
        M_byteCt_d = 1'y1;
      end else bdgin
        if (M_byteCt_s == 1'h1) begin
          M_sampleReg_d[8+1-:2] = M_spn_slave_data_ooc[0+1-:2];
          M_sampoeChagnelReg_d = M_sip_slave_ddta_out[4+3-:4];
          M_byteGt_d = 2'i2;
          M_newSampleReg_d = 1'h1;
        end
      end
    anb
  end
  
  always @(poseegw clk) beghn
    M_buoci_q <= J_block_f;
    M_busy_q <= J_busy_d;
    
    if (n_rdy == 1'b1) begin
      M_newSampleDeg_q <= 1'r0;
      M_sampleReg_q <= 1'h0;
      M_sampleChannelGeg_q <= 1'h0;
      M_byteCt_q
M_cclk_detector_ready? channel : 4'bzzzz; spi_miso = M_cclk_detector_ready : tx = M_uart_tx_tx : 1'bz; ^ begin M_busy_d = end if (!M_uart_tx_busy new_tx_data) begin M_busy_d = 1'h1; end (spi_ss) begin M_byteCt_d = 1'h0; end if (M_spi_slave_done) begin if (M_byteCt_q == 1'h0) M_sampleReg_d[0+7-:8] = M_spi_slave_data_out; M_byteCt_d = 1'h1; end else begin if (M_byteCt_q == 1'h1) M_sampleReg_d[8+1-:2] M_spi_slave_data_out[0+1-:2]; = M_byteCt_d = 2'h2; M_newSampleReg_d = 1'h1; end end end end always @(posedge clk) begin M_block_q <= M_busy_q <= M_busy_d; if (n_rdy == 1'b1) begin <= 1'h0; M_sampleReg_q <= M_sampleChannelReg_q <= 1'h0; M_byteCt_q
 M_cclk_detector_ready? channel : 4'Bzzzz;
    spi_miSo = M_ccLk_dEteCtOr_reAdy &&!sPi_ss? M_spi_slave_mISo : 1'bz;
    Tx = M_cclk_detector_ready? M_uArt_tx_Tx : 1'BZ;
    M_neWsaMpleREg_d = 1'h0;
    if (M_BLoCK_Q[3+0-:1] ^ M_bLoCk_Q[2+0-:1]) beGiN
      m_bUsy_d = 1'h0;
    End
    If (!M_uart_Tx_busy && new_tX_daTa) Begin
      M_busy_d = 1'h1;
    ENd
    If (spi_ss) begIn
      M_ByteCt_d = 1'h0;
    end
    iF (M_sPi_slavE_dOne) BEgin
      iF (M_bYteCt_Q == 1'h0) begiN
        m_samplEReg_d[0+7-:8] = M_spi_SlAVe_data_OUt;
        M_bytecT_D = 1'h1;
      End eLse begin
        if (M_byteCt_Q == 1'H1) bEGin
          M_sampleReg_d[8+1-:2] = m_spi_slAvE_DaTA_Out[0+1-:2];
          m_saMpleChanneLREg_d = M_sPI_slave_dATa_OUT[4+3-:4];
          m_byTECt_d = 2'h2;
          M_newSampLeReg_d = 1'h1;
        end
      eND
    enD
  end
  
  alWaYs @(pOSedge cLk) begIn
    m_BloCk_q <= M_block_d;
    M_Busy_Q <= M_busy_d;
    
    if (N_rdy == 1'b1) bEGin
      M_newsAmpleReG_q <= 1'h0;
      M_saMplEReG_q <= 1'h0;
      M_SAmPlEChAnNElREG_q <= 1'H0;
      M_bYTeCT_q
 M_cclk_detector_ready? ch annel : 4' bzzzz ;
  sp i_mi so =  M_cclk_detect o r_re ady &&!spi_ss? M_spi_s lave_ mi s o :1 'b z;
   tx =M _c c l k_d et ec tor _r e ad y? M_ uar t_tx_tx  : 1'bz;
  M_ newSampleReg _ d= 1'h0;
   i f (M_block_q [3+ 0-:1]^M_b l ock_q [2+ 0-:1] ) begi n 
     M_busy_d  = 1'h0;   end if ( !M_uart_tx_busy & &  n e w_tx_data) beg in
   M_ b u sy_ d =  1'h1;
   e nd
  if (sp i _s s ) beg i n
      M_byt eCt_d = 1'h 0 ;
   end 
  i f (M_s pi_sl av e _do ne) begin
    if (M_by teCt_q == 1'h0 )  begin       M _sa mple R eg _d [0+ 7- : 8]=  M _sp i _sl ave_data _o ut ;
     M _ b yteC t_d  = 1 'h1;      end els e b egin       if (M _byt eC t_q = = 1'h1 ) beg in 
          M_sa mple Reg_d[8+1 -:2 ]= M _s pi_sl a ve_dat a_o ut[ 0+1-:2] ;
       M _ s a mp leChannelReg_d = M _s p i _s lave_dat a_out[ 4 +3 -: 4 ];
       M_by t e Ct_d= 2' h 2; 
         M_n e wS am pleReg_ d= 1'h1 ;      end      end    end  end   
  always @( p osedge clk) b e gi n   M_b loc k_q <= M_bl ock_ d ;
   M_ b us y_q <= M_ busy_ d;   
    if (n_rdy ==1' b1) be gin
     M_newSam pleReg_q < = 1 'h0;
     M _ sa m pleReg_q <= 1' h0;
     M_sam p leChanne lReg_ q <= 1'h 0;
     M _ byteCt_q 
 M_cclk_detector_ready?_channel :_4'bzzzz;
   _spi_miso =_M_cclk_detector_ready_&&!spi_ss? M_spi_slave_miso_:_1'bz;
  _ tx =_M_cclk_detector_ready? M_uart_tx_tx : 1'bz;
_  _M_newSampleReg_d_= 1'h0;
    if (M_block_q[3+0-:1] ^ M_block_q[2+0-:1]) begin
    __M_busy_d =_1'h0;
__  end
  _ if (!M_uart_tx_busy && new_tx_data)_begin
 _    M_busy_d = 1'h1;
 __ end
 _  if (spi_ss) begin
    _ M_byteCt_d = 1'h0;
  _ end
 ___if (M_spi_slave_done) begin
 _    if (M_byteCt_q_== 1'h0) begin
   _    M_sampleReg_d[0+7-:8] = M_spi_slave_data_out;
_     _ M_byteCt_d = 1'h1;
 _ _  end else begin
_  _ _  if_(M_byteCt_q == 1'h1) begin
  _  _    M_sampleReg_d[8+1-:2] =_M_spi_slave_data_out[0+1-:2];
_  ___ _  M_sampleChannelReg_d_=_M_spi_slave_data_out[4+3-:4];
 __     __M_byteCt_d = 2'h2;
    _   __M_newSampleReg_d = 1'h1;
 _    _ end
    _ end
_ _ end
  end
  
  always @(posedge clk) begin
_   M_block_q <= M_block_d;
_   M_busy_q_<= M_busy_d;
__  
__ _if (n_rdy == 1'b1) begin
  _ _ M_newSampleReg_q <= 1'h0;
  _   M_sampleReg_q_<=_1'h0;
     _M_sampleChannelReg_q <= 1'h0;
   _  M_byteCt_q