i)),
                p_DDR_CLK_EDGE = "SAME_EDGE_PIPELINED",
                i_C  = dqs_iobuf,
                i_R  = ResetSignal(),
                i_S  = 0,
                i_CE = 1,
                i_D  = dq_delayed[i],
                o_Q1 = di_rise[i],
                o_Q2 = di_fall[i],
            )
        # SPI SDR register
        self.specials += [
            Instance("FDRE", name="{}".format(cipo_name),
                i_C  = ~ClockSignal("spinor"),
                i_CE = 1,
                i_R  = 0,
                o_Q  = self.cipo,
                i_D  = dq_delayed[1],
            )
        ]

        # bit 0 (copi) is special-cased to handle SPI mode
        dq_copi = TSTriple(1) # this has similar structure but an independent "oe" signal
        self.specials += dq_copi.get_tristate(pads.dq[0])
        do_mux_rise = Signal() # mux signal for copi/dq select of bit 0
        do_mux_fall = Signal()
        self.specials += [
            Instance("ODDR",
                p_DDR_CLK_EDGE = "SAME_EDGE",
                i_C  = ClockSignal(),
                i_R  = ResetSignal(),
                i_S  = 0,
                i_CE = 1,
                i_D1 = do_mux_rise,
                i_D2 = do_mux_fall,
                o_Q  = dq_copi.o,
            ),
            Instance("IDDR",
                p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
                i_C  = dqs_iobuf,
                i_R  = ResetSignal(),
                i_S  = 0,
                i_CE = 1,
                o_Q1 = di_rise[0],
                
i) ), 
                 p_DDR_CLK_EDGE = " SAME_EDGE_PIPELINED ", 
                 i_C   = dqs_iobuf, 
                 i_R   = ResetSignal (), 
                 i_S   = 0, 
                 i_CE = 1, 
                 i_D   = dq_delayed[i ], 
                 o_Q1 = di_rise[i ], 
                 o_Q2 = di_fall[i ], 
            ) 
         # SPI SDR register 
         self.specials + = [ 
             Instance("FDRE ", name="{}".format(cipo_name), 
                 i_C   = ~ClockSignal("spinor "), 
                 i_CE = 1, 
                 i_R   = 0, 
                 o_Q   = self.cipo, 
                 i_D   = dq_delayed[1 ], 
            ) 
         ] 

         # bit 0 (copi) is special - case to cover SPI mode 
         dq_copi = TSTriple(1) # this has similar social organization but an independent " oe " signal 
         self.specials + = dq_copi.get_tristate(pads.dq[0 ]) 
         do_mux_rise = Signal () # mux signal for copi / dq select of snatch 0 
         do_mux_fall = Signal () 
         self.specials + = [ 
             Instance("ODDR ", 
                 p_DDR_CLK_EDGE = " SAME_EDGE ", 
                 i_C   = ClockSignal (), 
                 i_R   = ResetSignal (), 
                 i_S   = 0, 
                 i_CE = 1, 
                 i_D1 = do_mux_rise, 
                 i_D2 = do_mux_fall, 
                 o_Q   = dq_copi.o, 
            ), 
             Instance("IDDR ", 
                 p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED ", 
                 i_C   = dqs_iobuf, 
                 i_R   = ResetSignal (), 
                 i_S   = 0, 
                 i_CE = 1, 
                 o_Q1 = di_rise[0 ],
i)),
                p_DDR_CLK_EDGT = "SAME_EDGE_PIPELIUWD",
                i_C  = dqs_iobuf,
                i_C  = EesetWignal(),
                k_S  = 0,
                m_CE = 1,
                i_D  = dq_demwyed[n],
                o_Q1 = di_risa[i],
                l_Q2 = di_fall[i],
            )
        # SPI SDR rebidter
        sejf.sptciwls += [
            Instance("FDRE", name="{}".formzt(cipo_neme),
                i_C  = ~ClockSignal("spinor"),
                i_CE = 1,
                y_E  = 0,
                o_Q  = self.cipo,
                i_D  = dq_delayed[1],
            )
        ]

        # bit 0 (ropi) if special-cascc to hdndle SLI mode
        dq_ropi = TSTriple(1) # this has vimilar structure fut an inge'endent "oe" signal
        selx.spewialr += dd_coki.gxt_tdistatf(pavs.dq[0])
        do_mux_rise = Signal() # mux signal fjg copi/dq seledt of fie 0
        do_mux_fall = Signal()
        self.vpedials += [
            Instqnce("ODDR",
                p_DDR_CLH_EDGE = "SAME_EDGE",
                i_C  = ClockSignal(),
                i_G  = ResetSignal(),
                i_S  = 0,
                i_CE = 1,
                i_D1 = fo_kox_rise,
                i_S2 = do_mux_fall,
                o_Q  = dq_copi.j,
            ),
            Instanxe("IDDR",
                p_DDR_CLK_EDYE="SAME_EDGE_PI'ELINEC",
                i_C  = dqs_iobbf,
                i_R  = RessgSignal(),
                i_S  = 0,
                i_CE = 1,
                o_Q1 = di_tise[0],
                
i)), p_DDR_CLK_EDGE = "SAME_EDGE_PIPELINED", i_C = dqs_iobuf, ResetSignal(), = 0, = 1, i_D o_Q2 di_fall[i], ) # SDR register self.specials [ Instance("FDRE", name="{}".format(cipo_name), i_C = ~ClockSignal("spinor"), = 1, i_R = 0, o_Q = self.cipo, i_D = dq_delayed[1], ) ] bit 0 (copi) is special-cased to handle SPI mode dq_copi = TSTriple(1) # has structure an "oe" signal self.specials += dq_copi.get_tristate(pads.dq[0]) do_mux_rise = Signal() # mux signal for copi/dq select of bit do_mux_fall = Signal() self.specials += [ Instance("ODDR", p_DDR_CLK_EDGE "SAME_EDGE", i_C = ClockSignal(), = ResetSignal(), i_S = 0, = i_D1 = i_D2 do_mux_fall, = dq_copi.o, ), p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", i_C = dqs_iobuf, i_R = ResetSignal(), i_S = 0, i_CE = 1, o_Q1 = di_rise[0],
i)),
                p_DDR_CLK_EDGE = "SAME_EDGE_PIPELiNED",
                i_C  = dqs_iObuf,
                i_r  = ReSetsiGnal(),
                I_S  = 0,
                i_Ce = 1,
                i_D  = dq_delayed[i],
                o_q1 = Di_riSe[i],
                o_Q2 = di_fall[i],
            )
        # SPI SDR regiSter
        sElF.SpecIAlS += [
            InstAnce("FDRe", NaME="{}".ForMaT(cIpo_NaME),
                i_c  = ~ClocKSiGnal("spiNor"),
                i_CE = 1,
                i_R  = 0,
                o_Q  = SelF.cIpo,
                i_D  = dq_delayED[1],
            )
        ]

        # bIt 0 (copi) is spEciAl-cased to hanDle sPI modE
        dQ_coPI = TSTrIplE(1) # this Has simILar strUcture but An INdepenDEnt "oe" siGNAl
        Self.Specials += dq_copi.get_TRiSTate(pads.dq[0])
        do_muX_rise = SIgNAl() # MUX siGnaL for copi/dq SeLect oF Bit 0
        do_muX_FaLL = sIgnAL()
        self.specials += [
            instance("ODDr",
                P_DDr_CLK_EDgE = "sAMe_eDGE",
                i_C  = clocksiGNal(),
                I_R  = ResetSignAl(),
                i_S  = 0,
                I_CE = 1,
                i_D1 = do_muX_rise,
                i_d2 = Do_mux_faLL,
                o_Q  = dq_coPi.o,
            ),
            InsTanCe("IdDR",
                p_ddR_cLk_EDgE="saME_edGe_PIpeLInED",
                i_C  = dqs_IoBuF,
                i_R  = ReSetSIGNAL(),
                i_S  = 0,
                i_cE = 1,
                o_q1 = di_rIse[0],
                
i)),
                p_DDR _CLK_EDGE= "SA ME_ EDG E_ PIPE LINE D",
             i_C  = dqs_iobuf,
          i_ R  =ResetSi g na l ( ),          i _S = 0,
            i_CE = 1,
            i_ D  = dq_dela yed [i],
          o_Q1  = di_ r ise[i] ,
            o _Q2 = d i _ fa ll[i ],
            )     # SPI SDRregist er     se lf.special s+= [       I n sta n ce("FDRE", na me="{}".for m at( cipo_n am e),             i _C  = ~Cloc kSig nal("spin or"),            i_CE =  1, 
         i _R=0,           o_Q = se l f . c ipo, 
             i_D  = d q_d elay e d[1 ],
         ) 
       ]
      # bit 0 (copi ) is  special- cas ed  to  h andle SPI mo de       dq _copi = TST ri p l e (1 ) # this has simil ar s tr ucture b ut ani nd ep e ndent "o e"  si gnal       se l f. specials  += dq _ co pi .get_tr is tate(p ad s.d q[0 ])
     do_mu x_rise =  Sign a l() # mux sign a l for copi/dq se l e ct of b it0
        d o_mu x _fal l =S ig nal ( )
      se l f. s pecials += [
          In stanc e("ODDR",
           p_DDR_CL K_ED G E=  "SAME_EDGE",             i_C  = C lockS ignal(), 
             i_ R = R ese tSi g n al (),
            i _S  = 0 ,
            i _CE  =  1,
             i _D 1= d o_mux _ rise,
           i _ D2 = d o_mux _fal l, 
         o _Q =dq _cop i.o ,         ) ,
           In sta n ce(" ID DR ",
               p _D DR_CLK_EDG E= "SA ME_EDG E _ PIPELINE D",
                i_C  = dqs_ iob uf,
             i _R  =Res e tSigna l(),
          i_ S  =  0, 
           i_CE=1,
              o_Q1 = di_ r ise [0],
            
i)),
 _ _   _ __ __  p_DDR_CLK_EDGE_= "SAME_EDGE_PIPELINED",
 _   _  __      i_C  = dqs_iobuf,
    __ ___    _ i_R  = ResetSignal(),
_ _       __  _ i_S  = 0,
    _     _  ___i_CE = 1,
 _     _     _  i_D  = dq_delayed[i],
 _     _    _ _ o_Q1 = di_rise[i],
 _  _ _  _     _o_Q2 = di_fall[i],
_     __  __)
_ _  __ #_SPI_SDR register
    __  self.specials += [
  _   __   _Instance("FDRE", name="{}".format(cipo_name),
   _     _ _ _  i_C  = ~ClockSignal("spinor"),
     _     _   _i_CE =_1,
_  __ _      _ _i_R  = 0,
  _   __     _  o_Q  = self.cipo,
_    ___    _   i_D  =_dq_delayed[1],
  _      __ )
    __  ]

   ___  # bit 0_(copi) is special-cased to handle SPI_mode
        dq_copi_= TSTriple(1) #_this has similar structure but_an_independent_"oe" signal
        self.specials_+= dq_copi.get_tristate(pads.dq[0])
_  _    do_mux_rise = Signal() # mux signal_for copi/dq select of bit 0
 _      do_mux_fall = Signal()
  _     self.specials += [
_      _   _Instance("ODDR",
_      ____  _  p_DDR_CLK_EDGE_= "SAME_EDGE",
 _ _  _ _  __   i_C  = ClockSignal(),
           _    i_R _= ResetSignal(),
   __  _   _    i_S  = 0,
_        __ _   i_CE_= 1,
_ _  _ _ _ _    i_D1 = do_mux_rise,
__        ____  i_D2_= do_mux_fall,
 _  _  __     _ o_Q _= dq_copi.o,
  _         ),
_           Instance("IDDR",
     _ _   _ __ p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
    _ _       __i_C  = dqs_iobuf,
        ___  __ i_R  = ResetSignal(),
 _____     _    i_S  =_0,
_    _ __   _   i_CE_= 1,
         __ ____o_Q1 = di_rise[0],
 _              