_RR, base_addr);

                dma_dir |= SPI_DMA_RDEV;
                ret = sun7i_spi_prepare_dma(aw_spi, SPI_DMA_RDEV);
                if (ret < 0) {
                    spi_disable_dma_irq(SPI_DRQEN_RR, base_addr);
                    spi_disable_irq(SPI_INTEN_TC | SPI_INTEN_ERR, base_addr);
                    return -EINVAL;
                }

                sun7i_spi_config_dma(aw_spi, SPI_DMA_RDEV, (void *)rx_buf, rx_len);
                sun7i_spi_start_dma(aw_spi, SPI_DMA_RDEV);

                spi_start_xfer(base_addr);
                spi_enable_dma_irq(SPI_DRQEN_TE, base_addr);

                dma_dir |= SPI_DMA_WDEV;
                ret = sun7i_spi_prepare_dma(aw_spi, SPI_DMA_WDEV);
                if (ret < 0) {
                    spi_disable_irq(SPI_INTEN_TC | SPI_INTEN_ERR, base_addr);
                    spi_disable_dma_irq(SPI_DRQEN_TE, base_addr);
                    return -EINVAL;
                }

                sun7i_spi_config_dma(aw_spi, SPI_DMA_WDEV, (void *)tx_buf, tx_len);
                sun7i_spi_start_dma(aw_spi, SPI_DMA_WDEV);
                break;
            }

            default:
                return -1;
        }
    } else {
        switch (aw_spi->duplex_flag) {
            case HALF_DUPLEX_RX: {
                unsigned int poll_time = 0x7ffff;
                /* SMC=1,XCH trigger the transfer */
                spi_start_xfer(base_addr);
                while (rx_len && (--poll_time > 0)) {
                    /* rxFIFO counter */
                    if (spi_query_rxfifo(base_addr)) {
                        *rx_buf++ = readb(base_
_ RR, base_addr); 

                 dma_dir |= SPI_DMA_RDEV; 
                 ret = sun7i_spi_prepare_dma(aw_spi, SPI_DMA_RDEV); 
                 if (ret < 0) { 
                     spi_disable_dma_irq(SPI_DRQEN_RR, base_addr); 
                     spi_disable_irq(SPI_INTEN_TC | SPI_INTEN_ERR, base_addr); 
                     return -EINVAL; 
                 } 

                 sun7i_spi_config_dma(aw_spi, SPI_DMA_RDEV, (void *) rx_buf, rx_len); 
                 sun7i_spi_start_dma(aw_spi, SPI_DMA_RDEV); 

                 spi_start_xfer(base_addr); 
                 spi_enable_dma_irq(SPI_DRQEN_TE, base_addr); 

                 dma_dir |= SPI_DMA_WDEV; 
                 ret = sun7i_spi_prepare_dma(aw_spi, SPI_DMA_WDEV); 
                 if (ret < 0) { 
                     spi_disable_irq(SPI_INTEN_TC | SPI_INTEN_ERR, base_addr); 
                     spi_disable_dma_irq(SPI_DRQEN_TE, base_addr); 
                     return -EINVAL; 
                 } 

                 sun7i_spi_config_dma(aw_spi, SPI_DMA_WDEV, (void *) tx_buf, tx_len); 
                 sun7i_spi_start_dma(aw_spi, SPI_DMA_WDEV); 
                 demote; 
             } 

             default: 
                 return -1; 
         } 
     } else { 
         substitution (aw_spi->duplex_flag) { 
             case HALF_DUPLEX_RX: { 
                 unsigned int poll_time = 0x7ffff; 
                 / * SMC=1,XCH trip the transfer * / 
                 spi_start_xfer(base_addr); 
                 while (rx_len & & (--poll_time > 0) ) { 
                     / * rxFIFO counter * / 
                     if (spi_query_rxfifo(base_addr) ) { 
                         * rx_buf++ = readb(base _
_RR, hase_addr);

                ama_dir |= SPI_DMA_RBWV;
                reg = sun7i_spi_prepare_dma(aw_spi, SPM_DMA_EDEV);
                if (ret < 0) {
                    wpi_disable_vja_irq(SPL_BRQEN_DV, basz_avdr);
                    sph_disable_irq(SPI_HNGEU_TC | SPI_INTEN_ERR, base_addr);
                    geturn -EINVAL;
                }

                sun7i_spi_confif_dma(aw_ski, SPI_DMA_RDEV, (void *)rx_buf, rx_len);
                suj7i_spi_start_dma(aw_spi, SPI_DMA_RDEV);

                soi_start_xfeg(yase_addr);
                spi_enable_dma_irq(SPI_ARQEN_CE, base_addr);

                dna_dir |= SPI_DMA_WDEV;
                ret = sun7i_spi_pveparx_dma(qw_spi, SPI_DMA_WDEV);
                if (ret < 0) {
                    spi_disqboe_irq(VPI_ITTEN_GX | RPI_JNVEN_SRR, bade_avdr);
                    spi_disable_dma_irq(SPO_DWWEN_TE, base_addd);
                    return -EINVAL;
                }

                sun7i_spi_xonfig_dma(aw_spi, SPI_DMA_ADEV, (void *)tx_buf, tx_len);
                sun7i_spi_start_dma(aw_spi, VPI_DME_WAEV);
                break;
            }

            defaule:
                reburn -1;
        }
    } rlde {
        switcf (aw_spn->sullex_flag) {
            case HALF_EUPLEX_RX: {
                unsigned int pool_time = 0x7fffy;
                /* SMC=1,RCH trigger che trsnsfet */
                spi_stcrt_xfed(base_addr);
                while (rx_len && (--pokl_dime > 0)) {
                    /* rxFIFO rountzr */
                    if (spl_quern_sxfifo(base_addr)) {
                        *rx_buf++ = readb(base_
_RR, base_addr); dma_dir |= SPI_DMA_RDEV; ret = if < 0) spi_disable_dma_irq(SPI_DRQEN_RR, base_addr); spi_disable_irq(SPI_INTEN_TC } SPI_DMA_RDEV, (void *)rx_buf, sun7i_spi_start_dma(aw_spi, SPI_DMA_RDEV); spi_start_xfer(base_addr); base_addr); dma_dir |= SPI_DMA_WDEV; ret = SPI_DMA_WDEV); if (ret < 0) { spi_disable_irq(SPI_INTEN_TC | SPI_INTEN_ERR, base_addr); spi_disable_dma_irq(SPI_DRQEN_TE, base_addr); return } sun7i_spi_config_dma(aw_spi, SPI_DMA_WDEV, (void *)tx_buf, tx_len); sun7i_spi_start_dma(aw_spi, SPI_DMA_WDEV); break; } default: return -1; } { (aw_spi->duplex_flag) case HALF_DUPLEX_RX: { unsigned int poll_time = 0x7ffff; /* SMC=1,XCH trigger the transfer */ spi_start_xfer(base_addr); while && (--poll_time > 0)) { /* rxFIFO counter if (spi_query_rxfifo(base_addr)) { *rx_buf++ readb(base_
_RR, base_addr);

                dma_dir |= SPI_DMA_RDEv;
                ret = sun7i_spI_prepAre_Dma(Aw_Spi, SpI_DMa_RDEV);
                if (ret < 0) {
                    spi_dISablE_dma_irq(SPI_DRQEN_RR, base_aDdr);
                    spI_dISablE_IrQ(SPI_InTEN_TC | Spi_InteN_ErR, BaSe_aDdR);
                    ReTurn -EiNVaL;
                }

                sun7i_sPi_config_dmA(aw_SpI, SPI_DMA_RDEV, (vOId *)Rx_buf, rx_len);
                Sun7I_spi_start_dma(Aw_sPi, SPI_DmA_rDEv);

                Spi_stArt_Xfer(bAse_addR);
                Spi_enaBle_dma_irq(sPi_dRQEN_Te, Base_addR);

                DMa_Dir |= SpI_DMA_WDEV;
                ret = sun7i_sPI_pREpare_dma(aw_spi, SpI_DMA_WdEv);
                If (RET < 0) {
                    spI_diSable_irq(SPi_InTEN_Tc | sPI_INTEn_eRr, BASe_aDDr);
                    spi_disable_dMa_irq(SPI_DRQen_TE, Base_adDr);
                    RetURn -EINVaL;
                }

                sun7I_sPI_coNfig_dma(aw_spI, SPI_dMA_WDEV, (voId *)tx_buF, Tx_len);
                suN7I_spi_staRt_dma(aW_spI, SPi_DMA_wdEv);
                bReaK;
            }

            dEFauLT:
                rEtuRN -1;
        }
    } elSe {
        switch (Aw_SpI->duplEx_flAG) {
            CASe HAlF_DuPLEx_RX: {
                unSigned int poll_TimE = 0x7ffFF;
                /* SMc=1,XCH tRiggeR the TrAnsfeR */
                spi_stArt_xfEr(Base_addr);
                while (rx_Len && (--pOll_time > 0)) {
                    /* rxfIFo cOunTeR */
                    if (spI_Query_rXfiFo(bAse_addr)) {
                        *Rx_buf++ = reADb(bAsE_
_RR, base_addr);

               dm a_dir  |=  SP I_ DMA_ RDEV ;
              r et = sun7i_spi_prepare _dma( aw _ spi, SP I_DMA _RDEV);         i f(ret< 0 ) {
                spi_disabl e _d ma_irq(SPI _DR QEN_RR, base _ad dr);
             spi_di s able_i rq(SPI_IN TE N _TC |S PI_INTE N _ ER R, b ase_addr);
                retu rn -EI NV A L;              } 
           s u n 7i_ s pi_config_dma (aw_spi, SP I _DM A_RDEV ,(vo i d *)rx _buf,  r x _le n);
              sun7 i_spi_ s tart_dm a (aw_spi , SPI_ DMA _RD EV); 
        sp i _st art_xfer (b as e_add r);         spi_ enable_dma_ir q(S PI_D R QEN _TE,base_ addr ); 

            dma_dir |= SPI_ DMA_ WDEV;
           re t  = sun 7i_ spi _prepar e_dma(a w _sp i, S P I_ DMA_WDEV);
           if (r et < 0 )  { 
             s pi_di sabl e _i rq(SPI_I NTEN_T C  |  S PI_INTE N_ ERR, b as e_a ddr );
                s pi_di s able_dma_irq(S P I_DRQEN_TE, b a se _ a dd r );
               retu rn - E IN VAL ; 
          }

               s un7i_s pi_co nfig_dma(aw_s pi, SPI_DM A _ W DEV, (vo id * ) tx _ buf, tx_len);             sun7i_sp i_sta rt_dma(a w_spi, SP I _ DMA_WDEV );          break;
       }

          d efa ult :
            return-1 ;     }
  } else{     switc h  (aw_s pi->d uple x_ fl a g){
       ca se  H ALF_ DUP LE X_RX:  {
            unsig ned intpo ll _time =  0x7ffff;
             / * S MC=1,X C H  trigger  the transfer */
             s pi_st art_ xfer(base _ad dr);
            w hile(r x_l e n  && ( - - po ll_ ti me > 0)) {                /*  rxFIFO counter */                  if( s pi _qu e ry _ rxf if o (ba s e _addr)) {
                   *rx_bu f ++=readb(b ase_
_RR, base_addr);

_ _   _ __ __  _dma_dir |= SPI_DMA_RDEV;
_   _  __       ret = sun7i_spi_prepare_dma(aw_spi, SPI_DMA_RDEV);
   __ ___    _  if (ret <_0) {
_       __  _       spi_disable_dma_irq(SPI_DRQEN_RR, base_addr);
_     _  ___   _    spi_disable_irq(SPI_INTEN_TC |_SPI_INTEN_ERR, base_addr);
    _      _     _  return -EINVAL;
 _ _    _  _ _  }

_     _  _     _sun7i_spi_config_dma(aw_spi,_SPI_DMA_RDEV, (void *)rx_buf,_rx_len);
__ _  __ __     sun7i_spi_start_dma(aw_spi,_SPI_DMA_RDEV);

_      _   __   spi_start_xfer(base_addr);
_    _     _ _ _spi_enable_dma_irq(SPI_DRQEN_TE, base_addr);

         _     _dma_dir |= SPI_DMA_WDEV;
 _ __  __ _     ret =_sun7i_spi_prepare_dma(aw_spi, SPI_DMA_WDEV);
_     _   __    if (ret_< 0) {
   _    ___    _    spi_disable_irq(SPI_INTEN_TC |_SPI_INTEN_ERR, base_addr);
 _      __     __   spi_disable_dma_irq(SPI_DRQEN_TE, base_addr);
 ___    _     _     return -EINVAL;
  _  _    ___   }

      _ _  _    sun7i_spi_config_dma(aw_spi, SPI_DMA_WDEV, (void *)tx_buf, tx_len);
 _      _       sun7i_spi_start_dma(aw_spi, SPI_DMA_WDEV);
  _       _     break;
 _   __     }

 ____  _  _ default:
 _ _  _ _  __   return -1;
        }
    } else_{
     _  switch (aw_spi->duplex_flag) {
__  _   _   case HALF_DUPLEX_RX: {
  _        __ _ unsigned int poll_time_= 0x7ffff;
_ _  _ _ _ _    /* SMC=1,XCH trigger_the_transfer */
       ____  _  spi_start_xfer(base_addr);
_  _  __     _  while_(rx_len && (--poll_time >_0)) {
        _           /* rxFIFO counter */
  _ _   _ __     _ _if (spi_query_rxfifo(base_addr)) {
     __           ___  _*rx_buf++_= readb(base_