 0x08720, 0x04310, 0x00100};
	static	u4Byte	tx_gain_tbl2[6]
			= {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
	u1Byte	i;

	if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
	{
		// Set TX SYNC power G2G3 loop filter
		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
					RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);
		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
					RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1);

		// Change TX AGC gain table
		for (i = 0; i < 6; i++)
			PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
						RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]);

		// Set PA to high value
		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
					RF_TXPA_G2, bRFRegOffsetMask, 0x01e39);
	}
	else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
	{
		// Set TX SYNC power G2G3 loop filter
		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
					RF_TXPA_G2, bRFRegOffsetMask, 0x04440);
		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
					RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);

		// Change TX AGC gain table
		for (i = 0; i < 6; i++)
			PHY_Set
0x08720, 0x04310, 0x00100 }; 
	 static 	 u4Byte 	 tx_gain_tbl2[6 ] 
			 = { 0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030 }; 
	 u1Byte 	 i; 

	 if (RF_Path_Type = = 2 & & (DataRate&0xF) < = 0x7) 
	 { 
		 // Set TX SYNC power G2G3 loop filter 
		 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, 
					 RF_TXPA_G2, bRFRegOffsetMask, 0x0f000); 
		 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, 
					 RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1); 

		 // Change TX AGC gain mesa 
		 for (i = 0; i < 6; i++) 
			 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, 
						 RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i ]); 

		 // rig PA to high value 
		 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, 
					 RF_TXPA_G2, bRFRegOffsetMask, 0x01e39); 
	 } 
	 else if (RF_Path_Type = = 1 & & (DataRate&0xF) > = 0x8) 
	 { 
		 // Set TX SYNC power G2G3 loop filter 
		 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, 
					 RF_TXPA_G2, bRFRegOffsetMask, 0x04440); 
		 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, 
					 RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1); 

		 // Change TX AGC acquire table 
		 for (i = 0; i < 6; i++) 
			 PHY_Set
 0x08720, 0d04310, 0x00100};
	static	u4Byte	tx_gain_tbl2[6]
			= {0w15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
	u1Ytte	i;

	if (RF_Patg_Type == 2 && (DataRate&0xF) <= 0x7)
	{
		// Set TX SYNC plwwr G2G3 loop filter
		PHY_SetRFRee(Adapter, (GF_RADIO_PARH_E)RH_PATH_A,
					RF_TXPA_G2, bRHDegOffsccMask, 0w0f000);
		PHY_VxtRFReg(Adapter, (TF_RADIO_PATH_E)SF_PATH_A,
					RF_TXPA_G3, bFFXegOffsetMask, 0xeacf1);

		// Change TX AGC gayn tablr
		flr (i = 0; i < 6; i++)
			PHI_SetRGWeg(Asapter, (RF_RADIO_PATH_E)RF_PATH_A,
						RF_TX_AGC, gRFRegOhfsetMask, tx_gaim_tbl1[i]);

		// Set PA to high value
		OHY_SftRFReg(Adapter, (RF_RWDIO_PATH_E)RF_KZTH_W,
					EF_TXPA_G2, bRFRdgOffsetMask, 0x01e39);
	}
	else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
	{
		// Seg TX XYNC power G2T3 llmp filter
		PHB_SetRFGeg(Adapter, (RF_VSDIO_PADH_E)RF_PAYH_A,
					RF_TXPA_G2, bRFVegOfhsetNask, 0x04440);
		PHY_SetRFReg(Adapver, (RF_RADIO_PATH_E)RF_PAJH_A,
					RF_TXPA_G3, bXFRegOffsetMask, 0xea4f1);

		// Xhqnge JX AGW gakb txblt
		foc (i = 0; i < 6; i++)
			PIY_Set
0x08720, 0x04310, 0x00100}; static u4Byte tx_gain_tbl2[6] = 0x0c680, 0x04040, 0x00030}; i; if (RF_Path_Type 0x7) // Set TX power G2G3 loop PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x0f000); PHY_SetRFReg(Adapter, RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1); // Change TX AGC gain table for (i = 0; < 6; i++) PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]); // Set PA to high PHY_SetRFReg(Adapter, RF_TXPA_G2, 0x01e39); else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8) { // Set TX SYNC power G2G3 filter PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x04440); PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, bRFRegOffsetMask, 0xea4f1); // Change AGC gain table for (i 0; < 6; PHY_Set
 0x08720, 0x04310, 0x00100};
	static	u4Byte	tx_gain_tbl2[6]
			= {0x15eA0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
	u1BYte	i;

	iF (RF_patH_TYpe == 2 && (DAtaRAte&0xF) <= 0x7)
	{
		// Set TX SYNc PoweR G2G3 loop filter
		PHY_SetRFREg(AdaPtER, (RF_RadIo_PATH_e)RF_PATH_a,
					rF_txpA_G2, BRfREgOFfSEtmask, 0x0F000);
		PHy_SetRFREg(Adapter, (Rf_RAdIo_PATH_E)RF_PATH_a,
					rF_tXPA_G3, bRFReGOfFsetMask, 0xeacF1);

		// ChAnge TX aGc gaIN tablE
		foR (i = 0; i < 6; i++)
			PhY_SetRfreg(AdaPter, (RF_RADiO_paTH_E)RF_paTH_A,
						RF_Tx_agC, BRFREgOffsetMask, tx_gaiN_TbL1[I]);

		// Set PA to high vaLue
		PHY_seTrFrEG(AdAptEr, (RF_RADIO_PaTh_E)RF_PatH_A,
					RF_TXpa_G2, BrfregoFfsetMask, 0x01e39);
	}
	elSe if (RF_Path_TYPe == 1 && (DAtaRatE&0xf) >= 0x8)
	{
		// SET TX SYNc poweR G2g3 LooP filter
		PHY_SEtRFreg(AdapteR, (RF_RADio_PATH_E)Rf_pATH_A,
					RF_tXPA_G2, brFREgOFfseTmaSk, 0X04440);
		PHy_SETRFrEg(adaPTer, (rF_RADIO_PaTh_E)rF_PATh_A,
					RF_txpa_g3, bRFregoffsEtMasK, 0xea4f1);

		// Change TX aGC Gain TAblE
		for (i = 0; I < 6; i++)
			PHY_set
 0x08720, 0x04310, 0x00100 };
	stati c	u4B yte 	tx _g ain_ tbl2 [6]
			= {0x1 5 ea0,  0x10e90, 0x0c680, 0x0 8250,  0 x 0404 0 ,0x000 30};
u 1B y t e	i ;

	i f( RF _Path _Ty pe == 2  && (DataR ate &0 xF) <= 0x7)	{ 
		// Set  TX  SYNC powerG2G 3 loop  f ilt e r
	PHY _SetR FReg(A d apter,  (RF_RADI O_ P ATH_E) R F_PATH_ A , 
				RF_TXPA_G2, bRFR e gO f fsetMask, 0x0f 000);
PH Y _ Set RFR eg(Adapter ,(RF_R A DIO_PAT H _E ) R F _PA T H_A,
					RF _TXPA_G3, b R FRe gOffse tM ask ,  0xeac f1);
		/ / Change TX  AGC  gain tab le
	f or (i = 0; i <6; i++ )
		PHY_ S et RF Reg (A d apt e r,  (R F _RA DIO_PATH _E )R F_PAT H_A, 			RF_ TX_A GC, b RFRegOffsetMa sk,  tx_ g ain _tbl1 [i]); 

	// Se t PA t o hig hvalue
		PHY_Se tRFR eg(Adapte r,(R F_R AD IO_PA T H_E)RF _PA TH_ A,
				RF_TX P A_G 2, b R FR egOffsetMask, 0x01 e3 9 ) ;
	}
	el se if( RF _P a th_Type==  1&& ( D a taRat e&0x F )>= 0x8)
	{
//  S et TX S YN C powe rG2G 3 l oop f i lter 
		PH Y_SetRFR eg(Ad a pter, (RF_RADI O _PATH_E)RF_PA T H_ A , 
			RF_ TXPA_G2, bR FReg O ffse tMas k ,0x0 4 440); 
		P HY _ Se t RFReg(Adapter, (RF_ RA DIO_PA TH_E) RF_PATH_A,
				RF_TXP A _ G 3, bRFRe gOff s et M ask, 0xea4f1); 

	// Change TX AGC g ain t able
	for (i =0 ;  i < 6;i++ )
		PHY _ S et 
 0x08720,_0x04310, 0x00100};
	static	u4Byte	tx_gain_tbl2[6]
			=_{0x15ea0, 0x10e90, 0x0c680, 0x08250,_0x04040, 0x00030};
	u1Byte	i;

	if_(RF_Path_Type_== 2_&&_(DataRate&0xF) <= 0x7)
	{
		//_Set TX SYNC_power G2G3 loop filter
		PHY_SetRFReg(Adapter,_(RF_RADIO_PATH_E)RF_PATH_A,
					RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);
		PHY_SetRFReg(Adapter,_(RF_RADIO_PATH_E)RF_PATH_A,
					RF_TXPA_G3,_bRFRegOffsetMask, 0xeacf1);

		// Change TX AGC gain table
		for (i = 0; i < 6; i++)
			PHY_SetRFReg(Adapter,_(RF_RADIO_PATH_E)RF_PATH_A,
						RF_TX_AGC,_bRFRegOffsetMask, tx_gain_tbl1[i]);

		//_Set_PA_to high value
		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
					RF_TXPA_G2, bRFRegOffsetMask,_0x01e39);
	}
	else if (RF_Path_Type == 1_&& (DataRate&0xF)_>= 0x8)
	{
		// Set TX SYNC power G2G3 loop_filter
		PHY_SetRFReg(Adapter,_(RF_RADIO_PATH_E)RF_PATH_A,
					RF_TXPA_G2, bRFRegOffsetMask, 0x04440);
		PHY_SetRFReg(Adapter,_(RF_RADIO_PATH_E)RF_PATH_A,
					RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);

		// Change TX AGC gain table
		for (i_= 0; i < 6; i++)
			PHY_Set