) \
		container_of(c, struct cdn_dp_device, encoder)

#define GRF_SOC_CON9		0x6224
#define DP_SEL_VOP_LIT		BIT(12)
#define GRF_SOC_CON26		0x6268
#define UPHY_SEL_BIT		3
#define UPHY_SEL_MASK		BIT(19)
#define DPTX_HPD_SEL		(3 << 12)
#define DPTX_HPD_DEL		(2 << 12)
#define DPTX_HPD_SEL_MASK	(3 << 28)

#define CDN_FW_TIMEOUT_MS	(64 * 1000)
#define CDN_DPCD_TIMEOUT_MS	5000
#define CDN_DP_FIRMWARE		"rockchip/dptx.bin"

struct cdn_dp_data {
	u8 max_phy;
};

struct cdn_dp_data rk3399_cdn_dp = {
	.max_phy = 2,
};

static const struct of_device_id cdn_dp_dt_ids[] = {
	{.compatible = "rockchip,rk3399-cdn-dp",
		.data = (void *)&rk3399_cdn_dp },
	{}
};

MODULE_DEVICE_TABLE(of, cdn_dp_dt_ids);

static int cdn_dp_grf_write(struct cdn_dp_device *dp,
			    unsigned int reg, unsigned int val)
{
	int ret;

	ret = clk_prepare_enable(dp->grf_clk);
	if (ret) {
		DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n");
		return ret;
	}

	ret = regmap_write(dp->grf, reg, val);
	if (ret) {
		DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
		return ret;
	}

	clk_disable_unprepare(dp->gr
) \ 
		 container_of(c, struct cdn_dp_device, encoder) 

 # define GRF_SOC_CON9 		 0x6224 
 # define DP_SEL_VOP_LIT 		 BIT(12) 
 # define GRF_SOC_CON26 		 0x6268 
 # define UPHY_SEL_BIT 		 3 
 # define UPHY_SEL_MASK 		 BIT(19) 
 # specify DPTX_HPD_SEL 		 (3 < < 12) 
 # specify DPTX_HPD_DEL 		 (2 < < 12) 
 # define DPTX_HPD_SEL_MASK 	 (3 < < 28) 

 # define CDN_FW_TIMEOUT_MS 	 (64 * 1000) 
 # define CDN_DPCD_TIMEOUT_MS 	 5000 
 # specify CDN_DP_FIRMWARE 		 " rockchip / dptx.bin " 

 struct cdn_dp_data { 
	 u8 max_phy; 
 }; 

 struct cdn_dp_data rk3399_cdn_dp = { 
	 .max_phy = 2, 
 }; 

 static const struct of_device_id cdn_dp_dt_ids [ ] = { 
	 { .compatible = " rockchip, rk3399 - cdn - dp ", 
		 .data = (null *) & rk3399_cdn_dp }, 
	 { } 
 }; 

 MODULE_DEVICE_TABLE(of, cdn_dp_dt_ids); 

 static int cdn_dp_grf_write(struct cdn_dp_device * dp, 
			     unsigned int reg, unsigned int val) 
 { 
	 int ret; 

	 ret = clk_prepare_enable(dp->grf_clk); 
	 if (ret) { 
		 DRM_DEV_ERROR(dp->dev, " Failed to prepare_enable grf clock\n "); 
		 return ret; 
	 } 

	 ret = regmap_write(dp->grf, reg, val); 
	 if (ret) { 
		 DRM_DEV_ERROR(dp->dev, " Could not publish to GRF: % d\n ", ret); 
		 return ret; 
	 } 

	 clk_disable_unprepare(dp->gr
) \
		cojtainer_of(c, struct cdn_dp_dtvice, encoder)

#defiuw GRF_SMC_CON9		0x6224
#sefine DO_SEL_VOP_LIT		BIT(12)
#define GRF_SOC_COI26		0x6268
#dedine YPHY_SEL_BIT		3
#define UPHY_SDL_MASK		BIT(19)
#fefine DPTX_HKD_SEL		(3 << 12)
#define DPTE_GPD_DEL		(2 << 12)
#defins DPTR_H'D_SEL_MASK	(3 << 28)

#defike CDN_FW_TIMAOUT_MS	(64 * 1000)
#define CAN_BPCD_TIMEOUT_MS	5000
#define CDN_DP_FIRMWARE		"rochchip/dpyx.hin"

struct cdn_dk_data {
	t8 mas_ihn;
};

struct cdn_dp_data rk3399_cdn_dp = {
	.max_phg = 2,
};

statpc const struct og_device_id cdn_dp_dt_ids[] = {
	{.compwtibpe = "rockchip,rk3399-cdn-do",
		.data = (void *)&rk3399_cqb_dp },
	{}
};

MODULE_DEXICE_TABLE(of, cdn_dp_dt_ids);

atatic int cdn_dp_grf_write(struct zdn_dp_bevice *dp,
			    ynslcned int rej, unsidned int val)
{
	lmt ret;

	set = cll_prepare_enable(cp->gcf_clj);
	if (ret) {
		DRM_DEV_ERROR(dp->vev, "Failed to preparg_enable grx elock\n");
		return ret;
	}

	ret = eetmap_wtite(d[->grf, eeg, vam);
	ih (rst) {
		DRM_FEV_XRROR(dp->dev, "Dould not weite to GRF: %d\n", ret);
		rttuwb ret;
	}

	clk_disabme_unprqpwre(dp->gr
) \ container_of(c, struct cdn_dp_device, encoder) #define #define BIT(12) #define 0x6268 #define UPHY_SEL_BIT DPTX_HPD_SEL << 12) #define (2 << 12) DPTX_HPD_SEL_MASK (3 << 28) #define CDN_FW_TIMEOUT_MS * 1000) #define CDN_DPCD_TIMEOUT_MS 5000 #define CDN_DP_FIRMWARE "rockchip/dptx.bin" struct cdn_dp_data { u8 max_phy; struct cdn_dp_data rk3399_cdn_dp = { .max_phy = 2, }; static const struct of_device_id = {.compatible "rockchip,rk3399-cdn-dp", = (void *)&rk3399_cdn_dp }, {} }; MODULE_DEVICE_TABLE(of, cdn_dp_dt_ids); static int cdn_dp_grf_write(struct cdn_dp_device *dp, unsigned int reg, int val) { int ret; ret = clk_prepare_enable(dp->grf_clk); (ret) { DRM_DEV_ERROR(dp->dev, "Failed prepare_enable grf clock\n"); return ret; ret regmap_write(dp->grf, reg, if { "Could not write GRF: %d\n", ret); return ret; } clk_disable_unprepare(dp->gr
) \
		container_of(c, struct cdn_dp_deVice, encodeR)

#defiNe GrF_SoC_cON9		0x6224
#DefiNe DP_SEL_VOP_LIT		Bit(12)
#defIne GRF_SOC_CON26		0x6268
#define UPHy_SEL_BiT		3
#DEfinE uPhY_SEL_mASK		BIT(19)
#DEfINE DPtX_hPd_SEl		(3 << 12)
#dEFiNe DPTx_HPd_DEL		(2 << 12)
#defIne DPTX_HPD_sEL_mAsK	(3 << 28)

#define CDN_Fw_tImEOUT_MS	(64 * 1000)
#defIne cDN_DPCD_TIMEOuT_Ms	5000
#definE CdN_Dp_fIRMWaRE		"RockcHip/dptX.Bin"

strUct cdn_dp_dAtA {
	U8 max_phY;
};

Struct cDN_Dp_Data Rk3399_cdn_dp = {
	.max_phy = 2,
};

statIC cONst struct of_devIce_id cDn_DP_dT_IDs[] = {
	{.cOmpAtible = "rockChIp,rk3399-cDN-dp",
		.data = (VOiD *)&RK3399_Cdn_DP },
	{}
};

MODULE_DEVICE_tABLE(of, cdn_dP_Dt_iDs);

statIc Int CDn_dp_grF_writE(sTRucT cdn_dp_devicE *dp,
			    uNsigned inT reg, unSIgned inT Val)
{
	int rEt;

	ret = cLk_pRepAre_eNAbLe(Dp->gRf_CLk);
	iF (ReT) {
		DRm_dEV_eRROR(dp->dEv, "faIled tO prePARE_EnabLe gRf clOck\n");
		rEturn ret;
	}

	ret = reGmaP_wriTE(dp->Grf, reG, val);
	iF (ret) {
		dRm_DEV_ErROR(dp->Dev, "CoUlD not write to GRF: %d\N", ret);
		Return ret;
	}

	Clk_DiSabLe_UnprePAre(dp->gR
) \
		container_of(c, stru ct cdn_dp_ devic e,enc od er)
#de fine GRF_SOC_C O N9	0x6224
#define DP_SEL_ VOP_L IT 	BIT ( 12 )
#de fine GR F _S O C _CO N2 6	0x 62 6 8#defi neUPHY_SE L_BIT		3
# def in e UPHY_SEL_M A SK 		BIT(19)#de fine DPTX_HP D_S EL		(3  < < 1 2 )
#de fin e DPT X_HPD_ D EL		(2  << 12)
# de f ine DP T X_HPD_S E L _M ASK(3 << 28)

#defin e  C D N_FW_TIMEOUT_M S	(64*1 00 0 ) 
#d efi ne CDN_DPC D_ TIMEO U T_MS	50 0 0# d e fin e  CDN_DP_FIRMW ARE		"rockc h ip/ dptx.b in "
s tructcdn_d p_ d ata  {
	u8 max_ phy; 
};

stru ct cdn _ dp_data rk3399_ cdn_dp  ={
.max _ ph y= 2 ,} ;
s ta tic con st struc tof _devi ce_i d c d n_dp _dt _ids [] ={
	{.compatib le= "r o ckc hip,r k3399 -cdn -d p",
	.data  = (v oi d *)&rk3399_cdn _dp},
	{}
}; 

M OD ULE _D EVICE _ TABLE( of,  cd n_dp_dt _ids);sta ti c i nt  cdn_dp_grf_write( st r u ct  cdn_dp_ device *d p, 			    u ns ign ed i n t  reg,  uns i gn ed int v al)
{in tret;

re t = cl k_ pre par e_ena b le(d p->grf _clk);
if (r e t) {
		DRM_DEV _ ERROR(dp->dev ,  " F a il e d to  pr epare_enabl e gr f  clo ck\n " ); 
	r eturn  ret; 
} 
ret = regmap_write( dp ->grf,  reg,  val);
	if (r et) {
		DR M _ D EV_ERROR (dp- > de v , "Could not w riteto GRF: %d \ n", ret) ;
		r eturn re t;
	}

	c l k _disable _un pre par e(d p - >g r
) \
		container_of(c,_struct cdn_dp_device,_encoder)

#define GRF_SOC_CON9		0x6224
#define DP_SEL_VOP_LIT		BIT(12)
#define GRF_SOC_CON26		0x6268
#define_UPHY_SEL_BIT		3
#define UPHY_SEL_MASK		BIT(19)
#define_DPTX_HPD_SEL		(3_<< 12)
#define_DPTX_HPD_DEL		(2_<< 12)
#define DPTX_HPD_SEL_MASK	(3_<< 28)

#define CDN_FW_TIMEOUT_MS	(64_* 1000)
#define CDN_DPCD_TIMEOUT_MS	5000
#define CDN_DP_FIRMWARE		"rockchip/dptx.bin"

struct_cdn_dp_data {
	u8 max_phy;
};

struct_cdn_dp_data_rk3399_cdn_dp = {
	.max_phy = 2,
};

static const struct of_device_id cdn_dp_dt_ids[] = {
	{.compatible = "rockchip,rk3399-cdn-dp",
		.data =_(void_*)&rk3399_cdn_dp },
	{}
};

MODULE_DEVICE_TABLE(of,_cdn_dp_dt_ids);

static_int_cdn_dp_grf_write(struct cdn_dp_device *dp,
			  _ unsigned int reg, unsigned_int val)
{
	int_ret;

	ret = clk_prepare_enable(dp->grf_clk);
	if (ret) {
		DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable_grf_clock\n");
		return ret;
	}

	ret =_regmap_write(dp->grf, reg, val);
	if (ret) {
		DRM_DEV_ERROR(dp->dev, "Could not write to_GRF: %d\n", ret);
		return ret;
	}

	clk_disable_unprepare(dp->gr