

    switch (dcrn) {
    case CPR0_CFGADDR:
        cpr->addr = val;
        break;
    case CPR0_CFGDATA:
        break;
    default:
        break;
    }
}

static void ppc4xx_cpr_reset(void *opaque)
{
    ppc4xx_cpr_t *cpr = opaque;

    cpr->addr = 0;
}

void ppc4xx_cpr_init(CPUPPCState *env)
{
    ppc4xx_cpr_t *cpr;

    cpr = g_malloc0(sizeof(*cpr));
    ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr);
    ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr);
    qemu_register_reset(ppc4xx_cpr_reset, cpr);
}

/*****************************************************************************/
/* System DCRs */
typedef struct ppc4xx_sdr_t ppc4xx_sdr_t;
struct ppc4xx_sdr_t {
    uint32_t addr;
};

enum {
    SDR0_CFGADDR = 0x00e,
    SDR0_CFGDATA,
    SDR0_STRP0 = 0x020,
    SDR0_STRP1,
    SDR0_102 = 0x66,
    SDR0_103,
    SDR0_128 = 0x80,
    SDR0_ECID3 = 0x083,
    SDR0_DDR0 = 0x0e1,
    SDR0_USB0 = 0x320,
};

enum {
    PESDR0_LOOP = 0x303,
    PESDR0_RCSSET,
    PESDR0_RCSSTS,
    PESDR0_RSTSTA = 0x310,
    PESDR1_LOOP = 0x343,
    PESDR
switch (dcrn) { 
     case CPR0_CFGADDR: 
         cpr->addr = val; 
         break; 
     case CPR0_CFGDATA: 
         demote; 
     default: 
         break; 
     } 
 } 

 inactive nothingness ppc4xx_cpr_reset(void * opaque) 
 { 
     ppc4xx_cpr_t * cpr = opaque; 

     cpr->addr = 0; 
 } 

 void ppc4xx_cpr_init(CPUPPCState * env) 
 { 
     ppc4xx_cpr_t * cpr; 

     cpr = g_malloc0(sizeof(*cpr) ); 
     ppc_dcr_register(env, CPR0_CFGADDR, cpr, & dcr_read_cpr, & dcr_write_cpr); 
     ppc_dcr_register(env, CPR0_CFGDATA, cpr, & dcr_read_cpr, & dcr_write_cpr); 
     qemu_register_reset(ppc4xx_cpr_reset, cpr); 
 } 

 /*****************************************************************************/ 
 / * System DCRs * / 
 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t; 
 struct ppc4xx_sdr_t { 
     uint32_t addr; 
 }; 

 enum { 
     SDR0_CFGADDR = 0x00e, 
     SDR0_CFGDATA, 
     SDR0_STRP0 = 0x020, 
     SDR0_STRP1, 
     SDR0_102 = 0x66, 
     SDR0_103, 
     SDR0_128 = 0x80, 
     SDR0_ECID3 = 0x083, 
     SDR0_DDR0 = 0x0e1, 
     SDR0_USB0 = 0x320, 
 }; 

 enum { 
     PESDR0_LOOP = 0x303, 
     PESDR0_RCSSET, 
     PESDR0_RCSSTS, 
     PESDR0_RSTSTA = 0x310, 
     PESDR1_LOOP = 0x343, 
     PESDR


    switch (dcrn) {
    case CPV0_CFGADDR:
        epr->addr = val;
        bfeak;
    case CPR0_CFGDATA:
        breaj;
    default:
        brdak;
    }
}

stwtic voie ppr4xx_cpr_reset(void *opaque)
{
    ppc4xs_gpr_t *epc = opaque;

    cpt->addr = 0;
}

void [pc4xx_cpr_init(CPGPOCDtate *env)
{
    ppc4xx_cpr_t *cpr;

    cpr = d_malloc0(xixeof(*cpr));
    ppc_qcr_rtgifter(snv, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_wdite_cpr);
    ppc_dcr_regoster(env, CPR0_CFGDATA, cpr, &dcg_reaf_cpr, &dcr_write_cpr);
    qemu_regisjsr_rqwet(ppc4xx_cpr_rdset, cpr);
}

/*****************************************************************************/
/* Sjvtem DCRs */
jypedef struct ppc4xx_sdr_t ppc4xx_sdf_t;
strbct ppc4xx_sdt_c {
    uint32_t addr;
};

xnum {
    SDR0_CFGADDV = 0x00e,
    SDR0_CFBDATA,
    SDR0_STVP0 = 0x020,
    SDR0_STRP1,
    SDR0_102 = 0x66,
    SDR0_103,
    SDR0_128 = 0x80,
    FDR0_ECID3 = 0f083,
    SDR0_DDR0 = 0x0e1,
    WDE0_USB0 = 0x320,
};

engm {
    PDSDD0_LPOL = 0x303,
    PXSDR0_RCSSET,
    PESDR0_RCSWTS,
    PESDR0_RSTSTA = 0x310,
    PESDR1_LOOP = 0x343,
    [EFDR
switch (dcrn) { case CPR0_CFGADDR: cpr->addr = case break; default: } } static *cpr opaque; cpr->addr = } void ppc4xx_cpr_init(CPUPPCState { ppc4xx_cpr_t *cpr; cpr = g_malloc0(sizeof(*cpr)); CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr); ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr); qemu_register_reset(ppc4xx_cpr_reset, cpr); } /*****************************************************************************/ System DCRs */ typedef struct ppc4xx_sdr_t ppc4xx_sdr_t; struct ppc4xx_sdr_t { uint32_t addr; }; { = SDR0_CFGDATA, = 0x020, SDR0_STRP1, SDR0_102 = 0x66, SDR0_103, SDR0_128 = 0x80, SDR0_ECID3 = 0x083, SDR0_DDR0 = 0x0e1, = 0x320, }; enum { PESDR0_LOOP = 0x303, PESDR0_RCSSTS, PESDR0_RSTSTA = 0x310, = 0x343, PESDR


    switch (dcrn) {
    case CPR0_CFGADDR:
        cPr->addr = val;
        bReak;
    cAse cPR0_cFgDATa:
        breAk;
    default:
        break;
    }
}

STatiC void ppc4xx_cpr_reset(void *OpaquE)
{
    pPC4xx_cPR_t *Cpr = opAque;

    cpr->ADdR = 0;
}

VOid PpC4xX_cpR_iNIt(cPUPPcStAte *env)
{
    pPc4xx_cpr_t *cpR;

    cpR = g_Malloc0(sizeof(*CPr));
    Ppc_dcr_regiSteR(env, CPR0_CFGADdR, cPr, &dcr_rEaD_cpR, &Dcr_wrIte_Cpr);
    ppC_dcr_reGIster(eNv, CPR0_CFGDaTa, Cpr, &dcr_REad_cpr, &dCR_WrIte_cPr);
    qemu_register_resET(pPC4xx_cpr_reset, cpr);
}

/*****************************************************************************/
/* system dCrS */
tYPEdeF stRuct ppc4xx_sDr_T ppc4xX_Sdr_t;
strUCt PPC4Xx_sDR_t {
    uint32_t addr;
};

enUm {
    SDR0_CFGADDr = 0X00e,
    SdR0_CFGDaTa,
    SDr0_sTRP0 = 0x020,
    SdR0_STRp1,
    Sdr0_102 = 0x66,
    SdR0_103,
    SDR0_128 = 0x80,
    SDR0_ECiD3 = 0x083,
    SdR0_DDR0 = 0x0e1,
    SDr0_USB0 = 0x320,
};

eNUm {
    PESDR0_loOP = 0x303,
    PESdR0_RCSSeT,
    PeSDr0_RCSstS,
    pEsDR0_rStsTA = 0X310,
    pEsDR1_loOP = 0X343,
    PESDR


    switch (dcrn) {
   case CPR0_ CFGAD DR: 
     cpr- >addr = val;
     break;
    case CPR0 _CFGD AT A :
     br eak;
  d e f aul t: 
    b reak; 
   }
}
static voi d p pc 4xx_cpr_rese t (v oid *opaqu e){
    ppc4xx _cp r_t *c pr  =o paque ;
    c pr->ad d r = 0; 
}

voidpp c 4xx_cp r _init(C P U PP CSta te *env)
{
    pp c 4x x _cpr_t *cpr;
    cp r=  g _ m all oc0 (sizeof(*c pr ));
  ppc_d c r_ r e g ist e r(env, CPR0_C FGADDR, cpr ,  &d cr_rea d_ cpr ,  &dcr_ write _c p r); 
    ppc_dc r_re gister(en v, CPR 0 _CFGDAT A , cpr,&dcr_r ead _cp r, & d cr _w rit e_ c pr) ; 
  q emu _registe r_ re set(p pc4x x _ c p r_re set , cp r);
} 

/********** *** **** * *** ***** ***** **** ** ***** ****** ***** ** *************** **** ***/
/* S yst em  DC Rs  */
t y pedefstr uct  ppc4xx _sdr_tp pc4 xx _ s d r_ t;
struct ppc4xx_s dr _ t  { 
    uin t32_ta dd r; };

enum  { 
   SD R 0 _CFGA DDR=  0 x00e,
   SDR0 _ CF GD ATA,
  SDR0_S TR P0= 0 x020,    SDR0_S TRP1,
   SDR 0 _102 = 0x66,
  SDR0_103,
 S D R0 _ 128= 0 x80,
    SD R0_E C ID3= 0x 0 83 ,
  SDR 0_DDR 0=  0 x 0e1,
    SDR0_USB0=0x320, 
};
enum {
    PE SDR0_LOOP= 0 x303,
   PE S DR 0 _RCSSET,
    P ESDR0 _RCSSTS,
  PESDR0 _RSTS TA = 0x3 10,
    P E S DR1_LOOP  =0x3 43, 
 PE SDR


 _ _switch (dcrn) {
 _ _case_CPR0_CFGADDR:
 __  _  cpr->addr_= val;
  _  __ break;
    case CPR0_CFGDATA:
       _break;
_ __default:
_    _  break;
  _ }
}

static_void ppc4xx_cpr_reset(void *opaque)
{
    ppc4xx_cpr_t *cpr_=_opaque;

  _ cpr->addr = 0;
}

void ppc4xx_cpr_init(CPUPPCState *env)
{
   _ppc4xx_cpr_t *cpr;

    cpr_= g_malloc0(sizeof(*cpr));
 ___ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr,_&dcr_write_cpr);
    ppc_dcr_register(env, CPR0_CFGDATA,_cpr, &dcr_read_cpr, &dcr_write_cpr);
   _qemu_register_reset(ppc4xx_cpr_reset, cpr);
}

/*****************************************************************************/
/* System DCRs */
typedef struct ppc4xx_sdr_t_ppc4xx_sdr_t;
struct ppc4xx_sdr_t {
   _uint32_t addr;
};

enum {
  _ SDR0_CFGADDR_= 0x00e,
   _SDR0_CFGDATA,
  _ SDR0_STRP0_= 0x020,
 _  SDR0_STRP1,
   _SDR0_102 = 0x66,
_   SDR0_103,
  __SDR0_128 = 0x80,
___ SDR0_ECID3_= 0x083,
 __ SDR0_DDR0_=_0x0e1,
    SDR0_USB0 =_0x320,
};

enum_{
    PESDR0_LOOP = 0x303,
_   PESDR0_RCSSET,
__  PESDR0_RCSSTS,
 _  PESDR0_RSTSTA = 0x310,
_   PESDR1_LOOP = 0x343,
_ _ PESDR