, d5, d9\n"

		"vpadd.s32  d0, d0, d1\n"
		"vpadd.s32  d1, d2, d3\n"

		"vrshrn.s32 d0, q0, %3\n"

		"vld1.16    {d2, d3, d4, d5}, [%1, :128]!\n"

		"vdup.i32   d1, d0[1]\n"  /* TODO: can be eliminated */
		"vdup.i32   d0, d0[0]\n"  /* TODO: can be eliminated */

		"vmull.s16  q3, d2, d0\n"
		"vmull.s16  q4, d3, d0\n"
		"vmlal.s16  q3, d4, d1\n"
		"vmlal.s16  q4, d5, d1\n"

		"vpadd.s32  d0, d6, d7\n" /* TODO: can be eliminated */
		"vpadd.s32  d1, d8, d9\n" /* TODO: can be eliminated */

		"vst1.32    {d0, d1}, [%2, :128]\n"
		: "+r" (in), "+r" (consts)
		: "r" (out),
			"i" (SBC_PROTO_FIXED4_SCALE)
		: "memory",
			"d0", "d1", "d2", "d3", "d4", "d5",
			"d6", "d7", "d8", "d9", "d10", "d11");
}

static inline void _sbc_analyze_eight_neon(const int16_t *in, int32_t *out,
							const FIXED_T *consts)
{
	/* TODO: merge even and odd cases (or even merge all four calls to this
	 * function) in order to have only aligned reads from 'in' array
	 * and reduce number of load instructions */
	asm volatile
, d5, d9\n " 

		 " vpadd.s32   d0, d0, d1\n " 
		 " vpadd.s32   d1, d2, d3\n " 

		 " vrshrn.s32 d0, q0, % 3\n " 

		 " vld1.16     { d2, d3, d4, d5 }, [% 1, : 128]!\n " 

		 " vdup.i32    d1, d0[1]\n "   / * TODO: can be eliminated * / 
		 " vdup.i32    d0, d0[0]\n "   / * TODO: can be eliminated * / 

		 " vmull.s16   q3, d2, d0\n " 
		 " vmull.s16   q4, d3, d0\n " 
		 " vmlal.s16   q3, d4, d1\n " 
		 " vmlal.s16   q4, d5, d1\n " 

		 " vpadd.s32   d0, d6, d7\n " / * TODO: can be eliminated * / 
		 " vpadd.s32   d1, d8, d9\n " / * TODO: can be eliminated * / 

		 " vst1.32     { d0, d1 }, [% 2, : 128]\n " 
		: " + radius " (in), " + radius " (consts) 
		: " r " (out), 
			 " i " (SBC_PROTO_FIXED4_SCALE) 
		: " memory ", 
			 " d0 ", " d1 ", " d2 ", " d3 ", " d4 ", " d5 ", 
			 " d6 ", " d7 ", " d8 ", " d9 ", " d10 ", " d11 "); 
 } 

 static inline nothingness _ sbc_analyze_eight_neon(const int16_t * in, int32_t * out, 
							 const FIXED_T * consts) 
 { 
	 / * TODO: merge even and odd cases (or even unify all four calls to this 
	  * function) in ordering to have only aligned read from' in' array 
	  * and reduce number of load instructions * / 
	 asm explosive
, d5, f9\n"

		"vpadd.s32  d0, d0, d1\n"
		"vpadd.s32  a1, d2, d3\n"

		"vrshrn.s32 d0, q0, %3\n"

		"vld1.16    {d2, s3, d4, d5}, [%1, :128]!\n"

		"xdup.i32   d1, d0[1]\n"  /* TODO: can be epininattb */
		"vdup.i32   d0, d0[0]\n"  /* TODU: can be vliminatee */

		"vmnll.s16  q3, d2, d0\n"
		"vmull.s16  q4, d3, d0\n"
		"vmlam.d16  q3, v4, d1\n"
		"vmlal.s16  q4, d5, d1\n"

		"vpadd.s32  d0, d6, d7\n" /* TODO: wav ye eliminated */
		"vpadd.s32  d1, d8, d9\n" /* TODO: cwn be ekilinated */

		"vst1.32    {d0, d1}, [%2, :128]\n"
		: "+r" (pn), "+r" (consts)
		: "r" (out),
			"i" (SBC_PROTO_FIXES4_SCALE)
		: "kemory",
			"d0", "d1", "d2", "d3", "d4", "d5",
			"d6", "d7", "d8", "d9", "d10", "d11");
}

static inlije vlid _sbc_analyze_eighh_neon(const unt16_t *un, int32_t *out,
							cunst FIXED_U *eonsts)
{
	/* TODO: merge even and odd cases (or evdn mexge all fout dapns to this
	 * funcnion) in order to have only akigned reads fvom 'ii' areay
	 * and reduce numbec of load instructiogs */
	asm vonacile
, d5, d9\n" "vpadd.s32 d0, d0, d1\n" d2, "vrshrn.s32 d0, %3\n" "vld1.16 {d2, "vdup.i32 d0[1]\n" /* TODO: be eliminated */ d0, d0[0]\n" /* TODO: can be */ "vmull.s16 q3, d2, d0\n" "vmull.s16 q4, d3, d0\n" "vmlal.s16 q3, d4, d1\n" q4, d5, d1\n" "vpadd.s32 d0, d6, d7\n" /* TODO: can be eliminated */ d1, d9\n" TODO: be eliminated */ "vst1.32 {d0, d1}, [%2, :128]\n" : "+r" (in), "+r" (consts) : "r" (out), (SBC_PROTO_FIXED4_SCALE) : "memory", "d0", "d1", "d2", "d3", "d4", "d6", "d7", "d8", "d9", "d11"); } static inline void int16_t int32_t *out, FIXED_T { TODO: merge even odd cases (or even merge all four calls to this * function) in order to have only reads from * and number load */ asm volatile
, d5, d9\n"

		"vpadd.s32  d0, d0, d1\n"
		"vpadd.s32  d1, d2, d3\n"

		"vrShrn.s32 d0, q0, %3\n"

		"vlD1.16    {d2, d3, d4, d5}, [%1, :128]!\N"

		"vdUp.i32   D1, d0[1]\N"  /* TODo: can Be eliminated */
		"vdUP.i32   d0, d0[0]\N"  /* TODO: can be eliminated */

		"vmUll.s16  q3, D2, d0\N"
		"VmulL.S16  q4, D3, d0\n"
		"vmLal.s16  q3, d4, d1\N"
		"VmLAL.s16  q4, D5, d1\N"

		"vPadD.s32  D0, D6, d7\N" /* TODO: Can Be elimiNated */
		"vpadd.S32  d1, d8, D9\n" /* tODO: can be eliMInAted */

		"vst1.32    {d0, d1}, [%2, :128]\n"
		: "+R" (in), "+R" (consts)
		: "r" (out),
			"i" (sBC_pROTO_FiXeD4_ScaLE)
		: "meMorY",
			"d0", "d1", "d2", "d3", "D4", "d5",
			"d6", "d7", "d8", "d9", "D10", "D11");
}

statiC inline voId _SBc_analYZe_eight_NEOn(ConsT int16_t *in, int32_t *out,
							conST FixED_T *consts)
{
	/* TODO: Merge eVeN AnD ODd cAseS (or even merGe All foUR calls tO ThIS
	 * FUncTIon) in order to hAve only aligNEd rEads frOm 'In' aRRay
	 * and ReducE nUMbeR of load instRuctIons */
	asm voLatile
, d5, d9\n"

		"vpadd.s32 d0, d0, d 1\n"		" vpa dd .s32   d1 , d2, d3\n"

"vrs hrn.s32 d0, q0, %3\n"
		"v ld 1 .16 {d2,d3, d4, d5 } ,  [% 1,  : 128 ]! \ n" 

		" vdu p.i32  d1, d0[1] \n"  /* TODO: can be  eliminate d * /
		"vdup.i3 2  d0, d 0[ 0]\ n "  /*  TO DO: c an bee limina ted */

	" v mull.s 1 6  q3,d 2 ,d0\n "
		"vmull.s16  q 4 ,d 3, d0\n"
		"vm lal.s1 6q3 , d4,  d1 \n"
		"vml al .s16q4, d5, d1 \ n " 

"vpadd.s32  d 0, d6, d7\n "  /*  TODO:  c anb e elim inate d* /
	"vpadd.s32   d1 , d8, d9\ n" /*T ODO: ca n  be eli minate d * /
		"v s t1 .3 2  { d0, d1 },[ %2,  :128]\n "	: "+r " (i n ) , "+r"  (c onst s)
	: "r" (out),		"i"( SBC _PROT O_FIX ED4_ SC ALE)		: "m emory ", 
			"d0", "d1",  "d2 ", "d3","d4 ",  "d 5" ,
		" d6", " d7" , " d8", "d 9", "d1 0 ","d 1 1 " ); 
}

static inlinevo i d  _ sbc_anal yze_ei g ht _n e on(const  i nt1 6_t* i n, in t32_ t  * out,
						co n st  F IXED_T*c onsts) 
{ 
	/ * T ODO:m erge  evenand oddcases (or even merge all four call s  t o th i s
	* f unction) in  ord e r to  hav e  o nly align ed re ad s  f r om 'in' array
	 * a nd  reduc e num ber of load i nstruction s * /
	asm v olat i le 
, d5,_d9\n"

		"vpadd.s32 _d0, d0, d1\n"
		"vpadd.s32 _d1, d2,_d3\n"

		"vrshrn.s32_d0, q0,_%3\n"

		"vld1.16_  _{d2, d3, d4,_d5}, [%1, :128]!\n"

		"vdup.i32 _ d1, d0[1]\n"__/* TODO: can be eliminated */
		"vdup.i32   d0, d0[0]\n"  /* TODO: can_be_eliminated */

		"vmull.s16__q3,_d2, d0\n"
		"vmull.s16  q4, d3,_d0\n"
		"vmlal.s16  q3, d4, d1\n"
		"vmlal.s16_ q4,_d5, d1\n"

		"vpadd.s32  d0, d6, d7\n" /* TODO:_can_be eliminated */
		"vpadd.s32_ d1, d8, d9\n" /* TODO: can be eliminated_*/

		"vst1.32    {d0, d1},_[%2, :128]\n"
		: "+r"_(in),_"+r"_(consts)
		: "r" (out),
			"i" (SBC_PROTO_FIXED4_SCALE)
		:_"memory",
			"d0", "d1", "d2", "d3", "d4", "d5",
			"d6",_"d7", "d8", "d9", "d10", "d11");
}

static inline_void _sbc_analyze_eight_neon(const int16_t *in, int32_t *out,
							const FIXED_T_*consts)
{
	/* TODO: merge even and odd_cases (or even merge all_four calls_to this
	 * function) in_order to have_only aligned_reads from 'in'_array
	 * and reduce number of_load instructions */
	asm_volatile