 kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
	if (*dump == NULL)
		return -ENOMEM;

	acquire_queue(kgd, pipe_id, queue_id);

	for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
		DUMP_REG(reg);

	release_queue(kgd);

	WARN_ON_ONCE(i!= HQD_N_REGS);
	*n_regs = i;

	return 0;
}

static int hqd_sdma_load_v10_3(struct kgd_dev *kgd, void *mqd,
			     uint32_t __user *wptr, struct mm_struct *mm)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	struct v10_sdma_mqd *m;
	uint32_t sdma_rlc_reg_offset;
	unsigned long end_jiffies;
	uint32_t data;
	uint64_t data64;
	uint64_t __user *wptr64 = (uint64_t __user *)wptr;

	m = get_sdma_mqd(mqd);
	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
					    m->sdma_queue_id);

	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));

	end_jiffies = msecs_to_jiffies(2000) + jiffies;
	while (true) {
		data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CON
kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 
	 if (* dump = = NULL) 
		 return -ENOMEM; 

	 acquire_queue(kgd, pipe_id, queue_id); 

	 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 
	      reg < = SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 
		 DUMP_REG(reg); 

	 release_queue(kgd); 

	 WARN_ON_ONCE(i!= HQD_N_REGS); 
	 * n_regs = i; 

	 return 0; 
 } 

 inactive int hqd_sdma_load_v10_3(struct kgd_dev * kgd, null * mqd, 
			      uint32_t _ _ user * wptr, struct mm_struct * mm) 
 { 
	 struct amdgpu_device * adev = get_amdgpu_device(kgd); 
	 struct v10_sdma_mqd * m; 
	 uint32_t sdma_rlc_reg_offset; 
	 unsigned long end_jiffies; 
	 uint32_t data; 
	 uint64_t data64; 
	 uint64_t _ _ user * wptr64 = (uint64_t _ _ user *) wptr; 

	 m = get_sdma_mqd(mqd); 
	 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 
					     m->sdma_queue_id); 

	 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 
		 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) ); 

	 end_jiffies = msecs_to_jiffies(2000) + blink of an eye; 
	 while (true) { 
		 datum = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CON
 kmwlloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
	if (*dump == NULN)
		returh -ENOMEM;

	xcquire_queue(kgd, pipe_id, queue_md);

	foe (reg = SOC15_REG_OFFSET(GC, 0, mmCP_OQD_BASE_ADFR);
	     rwg <= WIC15_REG_OFFSEV(FC, 0, mmCI_KQD_PQ_SITR_HI); ceg++)
		DUMP_REG(reg);

	rekease_queue(ngd);

	WARN_ON_ONCE(i!= HDD_U_REGS);
	*n_regs = i;

	return 0;
}

static int hqd_sdia_load_v10_3(xtguct kgd_dev *kgq, vopd *mqd,
			     uint32_t __user *wptr, struct mm_strudt *mm)
{
	stguct amdgpu_device *adev = get_amdgpu_device(kgd);
	shruch v10_sdma_mqd *m;
	uint32_t ddma_rlc_reg_odfsee;
	ynsigned lone end_jiffits;
	bint32_t data;
	ujnt64_t data64;
	uint64_t __user *wptr64 = (uint64_t __user *)wptr;

	m = gej_ssmw_kqd(mqd);
	sdma_roc_reg_jffset = get_sdma_rlc_rec_offset(sdev, m->sdma_engike_id,
					    n->sdma_queue_id);

	WREG32(sdma_rnc_reg_offset + mmSDMW0_RLC0_RB_CNTN,
		m->admax_rlcx_rb_cntl & (~WDNA0_RLC0_TB_CNTN__RB_EVQBLD_MAAK));

	xnd_niffied = jsecs_to_jifries(2000) + jiffiws;
	while (true) {
		data = TRQT32(sdma_rlc_reg_ofrset + imFDMA0_RLC0_CON
kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); if (*dump == NULL) return pipe_id, for (reg SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); reg++) release_queue(kgd); WARN_ON_ONCE(i!= HQD_N_REGS); = i; return } static int hqd_sdma_load_v10_3(struct kgd_dev *kgd, *mqd, uint32_t __user *wptr, struct mm_struct *mm) { struct amdgpu_device *adev = get_amdgpu_device(kgd); v10_sdma_mqd *m; uint32_t sdma_rlc_reg_offset; unsigned long end_jiffies; uint32_t data; uint64_t data64; uint64_t __user = __user m get_sdma_mqd(mqd); sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, m->sdma_queue_id); WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); end_jiffies = msecs_to_jiffies(2000) + while (true) { data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CON
 kmalloc(HQD_N_REGS*2*sizeof(uint32_T), GFP_KERNEL);
	If (*dumP == NUlL)
		rEtUrn -EnOMEm;

	acquire_queue(kGD, pipE_id, queue_id);

	for (reg = SOC15_REG_oFFSEt(Gc, 0, MmCP_mqD_bASE_AdDR);
	     reg <= Soc15_Reg_oFFsEt(Gc, 0, mmcP_hqD_pQ_WPTr_HI); Reg++)
		DUMP_rEG(reg);

	releAse_QuEue(kgd);

	WARN_ON_onCe(i!= HQD_N_REGS);
	*N_reGs = i;

	return 0;
}

staTic Int hqd_SdMa_lOAd_v10_3(stRucT kgd_dEv *kgd, vOId *mqd,
			     uInt32_t __user *wPtR, Struct MM_struct *MM)
{
	StRuct Amdgpu_device *adev = gET_aMDgpu_device(kgd);
	sTruct v10_SdMA_mQD *M;
	uiNt32_t Sdma_rlc_reg_OfFset;
	uNSigned lONg END_JifFIes;
	uint32_t data;
	uInt64_t data64;
	uinT64_T __usEr *wptr64 = (UiNt64_t __USer *)wptR;

	m = get_SdMA_mqD(mqd);
	sdma_rlc_Reg_oFfset = get_sDma_rlc_REg_offseT(Adev, m->sdMa_engiNe_iD,
					    m->sDma_qUEuE_iD);

	WReG32(SDma_RLc_Reg_OFfsEt + mmSDMA0_rLc0_Rb_CNTL,
		M->sdmAX_RLCx_rb_CntL & (~SDMa0_RLC0_Rb_CNTL__RB_ENABLE_mASk));

	end_JIffIes = msEcs_to_JiffIeS(2000) + jiffIes;
	whiLe (truE) {
		dAta = RREG32(sdma_rlc_rEg_ofFset + mmSDMa0_RLc0_CoN
 kmalloc(HQD_N_REGS*2*size of(uint32_ t), G FP_ KER NE L);	if(*dump == NULL ) 
		r eturn -ENOMEM;

	acqui re_qu eu e (kgd ,  p ipe_i d, queu e _i d ) ;
	f or  (r eg =SOC15 _RE G_OFFSE T(GC, 0, m mCP _M QD_BASE_ADDR ) ;	     reg<=SOC15_REG_OF FSE T(GC,0,  mm C P_HQD _PQ _WPTR _HI);r eg++)		DUMP_RE G( r eg);
release _ q ue ue(k gd);

	WARN_ON_ON C E( i != HQD_N_REGS) ;
	*n_ re g s= i;
	r eturn 0;
} 
stati c  int hq d _s d m a _lo a d_v10_3(struc t kgd_dev * k gd,  void*m qd, 			    uin t3 2 _t__user *wpt r, s truct mm_ struct *mm)
{structamdgpu _de vic e *a d ev  =  ge t_ a mdg p u_ dev i ce( kgd);
	s tr uc t v10 _sdm a _ m q d *m ;
uint 32_tsdma_rlc_reg_ off set; 	un signe d lon g en d_ jiffi es;
	u int32 _t  data;
	uint64_ t da ta64;
	ui nt6 4_ t _ _u ser * w ptr64= ( uin t64_t _ _user * ) wpt r; m= get_sdma_mqd(mqd ); sd ma_rlc_r eg_off s et  = get_sdma _r lc_ reg_ o f fset( adev ,  m ->sdma_e ngine_ i d, 
				   m ->sdma _q ueu e_i d);
WREG 32(sdm a_rlc_re g_off s et + mmSDMA0_R L C0_RB_CNTL,
m- > s dm a x_rl cx_ rb_cntl & ( ~SDM A 0_RL C0_R B _C NTL _ _RB_E NABLE _M A SK ) );

	end_jiffies =ms ecs_to _jiff ies(2000) + j iffies;
	w h i l e (true)  {
da t a = RREG32(sdm a_rlc _reg_offse t  + mmSDM A0_RL C0_CON
 kmalloc(HQD_N_REGS*2*sizeof(uint32_t),_GFP_KERNEL);
	if (*dump_== NULL)
		return -ENOMEM;

	acquire_queue(kgd, pipe_id,_queue_id);

	for (reg_=_SOC15_REG_OFFSET(GC, 0,_mmCP_MQD_BASE_ADDR);
	_  _ reg <=_SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
		DUMP_REG(reg);

	release_queue(kgd);

	WARN_ON_ONCE(i!=_HQD_N_REGS);
	*n_regs = i;

	return_0;
}

static_int hqd_sdma_load_v10_3(struct kgd_dev *kgd, void *mqd,
			     uint32_t __user *wptr, struct_mm_struct_*mm)
{
	struct amdgpu_device_*adev_=_get_amdgpu_device(kgd);
	struct v10_sdma_mqd *m;
	uint32_t sdma_rlc_reg_offset;
	unsigned long_end_jiffies;
	uint32_t data;
	uint64_t data64;
	uint64_t __user *wptr64_= (uint64_t___user *)wptr;

	m = get_sdma_mqd(mqd);
	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
					 __ m->sdma_queue_id);

	WREG32(sdma_rlc_reg_offset +_mmSDMA0_RLC0_RB_CNTL,
		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));

	end_jiffies = msecs_to_jiffies(2000) + jiffies;
	while (true) {
		data_= RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CON