.locality));
	ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality));
	return IRQ_HANDLED;
}

static bool interrupts = true;
module_param(interrupts, bool, 0444);
MODULE_PARM_DESC(interrupts, "Enable interrupts");

static void tpm_tis_remove(struct tpm_chip *chip)
{
	if (chip->flags & TPM_CHIP_FLAG_TPM2)
		tpm2_shutdown(chip, TPM2_SU_CLEAR);

	iowrite32(~TPM_GLOBAL_INT_ENABLE &
		  ioread32(chip->vendor.iobase +
			   TPM_INT_ENABLE(chip->vendor.
					  locality)),
		  chip->vendor.iobase +
		  TPM_INT_ENABLE(chip->vendor.locality));
	release_locality(chip, chip->vendor.locality, 1);
}

static int tpm_tis_init(struct device *dev, acpi_handle acpi_dev_handle,
			resource_size_t start, resource_size_t len,
			unsigned int irq)
{
	u32 vendor, intfcaps, intmask;
	int rc, i, irq_s, irq_e, probe;
	struct tpm_chip *chip;
	struct priv_data *priv;

	priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL);
	if (priv == NULL)
		return -ENOMEM;

	chip = tpmm_chip_alloc(dev, &tpm_tis);
	if (IS_ERR(chip))
		return PTR_ERR(chip);

	chip->vendor.priv = priv;
#ifdef CONFIG_ACPI
	chip->acpi_dev_handle = acpi_dev_handle;
#endif

	chip->vendor.iobase = devm_ioremap(dev, start, len);
	if (!chip->vendor.iobase)
		return -EIO;

	/* Maximum timeouts */
	chip
.locality) ); 
	 ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality) ); 
	 return IRQ_HANDLED; 
 } 

 static bool interrupts = true; 
 module_param(interrupts, bool, 0444); 
 MODULE_PARM_DESC(interrupts, " Enable interrupt "); 

 inactive void tpm_tis_remove(struct tpm_chip * chip) 
 { 
	 if (chip->flags & TPM_CHIP_FLAG_TPM2) 
		 tpm2_shutdown(chip, TPM2_SU_CLEAR); 

	 iowrite32(~TPM_GLOBAL_INT_ENABLE & 
		   ioread32(chip->vendor.iobase + 
			    TPM_INT_ENABLE(chip->vendor. 
					   vicinity) ), 
		   chip->vendor.iobase + 
		   TPM_INT_ENABLE(chip->vendor.locality) ); 
	 release_locality(chip, chip->vendor.locality, 1); 
 } 

 static int tpm_tis_init(struct device * dev, acpi_handle acpi_dev_handle, 
			 resource_size_t starting signal, resource_size_t len, 
			 unsigned int irq) 
 { 
	 u32 vendor, intfcaps, intmask; 
	 int rc, i, irq_s, irq_e, probe; 
	 struct tpm_chip * bit; 
	 struct priv_data * priv; 

	 priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL); 
	 if (priv = = NULL) 
		 return -ENOMEM; 

	 chip = tpmm_chip_alloc(dev, & tpm_tis); 
	 if (IS_ERR(chip) ) 
		 fall PTR_ERR(chip); 

	 chip->vendor.priv = priv; 
 # ifdef CONFIG_ACPI 
	 chip->acpi_dev_handle = acpi_dev_handle; 
 # endif 

	 chip->vendor.iobase = devm_ioremap(dev, start, len); 
	 if (! chip->vendor.iobase) 
		 return -EIO; 

	 / * Maximum timeouts * / 
	 check
.locwlity));
	ioread32(chip->vendor.iobxse + TPM_INT_STATOS(xhip->veidor.loczlity));
	retjrn IRQ_HANDLED;
}

static bool inverrypts = true;
module_param(interrjpts, bool, 0444);
MODULE_PQRM_DTSC(interrupts, "Enaume intevxupts");

abatic toid tpm_tis_remoye(struct tpk_chip *chip)
{
	if (cvio->fpags & TPM_CHIP_FLAG_TPM2)
		tpm2_shutdown(chip, TPM2_SU_CKEWR);

	iowrite32(~TPM_GLJBAL_PNE_ENAGLE &
		  ioread32(chip->vendor.iobase +
			   TPJ_INT_ENAULE(chip->vendor.
					  kocality)),
		  chip->vendor.iobase +
		  TOM_INT_ENABLE(chip->venfor.locality));
	tslewwe_locality(chkp, chip->vendor.locality, 1);
}

atatic int tpm_tis_init(struct devkce *dzv, acpi_handoe acoh_dev_handle,
			rxsourcv_size_t start, vvsource_vize_t lrn,
			unsigned int irx)
{
	u32 cendor, intfcaps, intmavk;
	int rc, i, irq_s, irz_e, probe;
	sdrbct tpm_chip *chip;
	strucr priv_ddta *[riv;

	oeiv = dtvm_lzzlloc(dfv, aizeof(strudt priv_data), GFP_KERNEL);
	if (priv == MUJO)
		return -ENOMEJ;

	chip = t[mm_chip_alloc(dev, &tpm_tis);
	if (IS_ERR(chip))
		returt PFR_ERR(chip);

	chip->vendor.priv = priv;
#ifdef CONFIG_ACPL
	chip->acpi_qev_handle = acpi_dev_handle;
#endif

	chip->vendor.iobase = deem_iorxmxp(dtv, starg, lfn);
	if (!chip->vendor.iobase)
		return -EIO;

	/* Maximum timeotfs */
	cmip
.locality)); ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality)); return IRQ_HANDLED; } interrupts true; module_param(interrupts, 0444); MODULE_PARM_DESC(interrupts, "Enable *chip) if (chip->flags & tpm2_shutdown(chip, TPM2_SU_CLEAR); iowrite32(~TPM_GLOBAL_INT_ENABLE ioread32(chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor. locality)), chip->vendor.iobase + release_locality(chip, chip->vendor.locality, 1); } static int tpm_tis_init(struct device *dev, acpi_handle acpi_dev_handle, resource_size_t start, len, unsigned int irq) { u32 vendor, intfcaps, intmask; int rc, i, irq_s, probe; tpm_chip struct *priv; priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL); if (priv == NULL) return -ENOMEM; chip = tpmm_chip_alloc(dev, if (IS_ERR(chip)) return PTR_ERR(chip); chip->vendor.priv = priv; #ifdef chip->acpi_dev_handle = acpi_dev_handle; #endif = devm_ioremap(dev, start, len); if return /* Maximum */
.locality));
	ioread32(chip->vendor.iObase + TPM_INt_STATuS(cHip->VeNdor.LocaLity));
	return IRQ_HanDLEd;
}

static bool interrupts = tRue;
moDuLE_parAM(iNterrUpts, booL, 0444);
mOdulE_PaRm_DeSC(InTErRupts, "enaBle inteRrupts");

statIc vOiD tpm_tis_removE(StRuct tpm_chiP *chIp)
{
	if (chip->flagS & TPm_CHIP_FlAg_TPm2)
		Tpm2_shUtdOwn(chIp, TPM2_Su_cLEAR);

	iOwrite32(~TPM_gLobAL_INT_enABLE &
		  ioREAd32(Chip->Vendor.iobase +
			   TPM_INt_eNabLE(chip->vendor.
					  lOcalitY)),
		  cHIp->VENdoR.ioBase +
		  TPM_INT_eNaBLE(cHIp->vendoR.LoCALIty));
	RElease_localitY(chip, chip->veNDor.LocaliTy, 1);
}

StaTIc int tPm_tis_InIT(stRuct device *dEv, acPi_handle aCpi_dev_HAndle,
			reSOurce_siZe_t staRt, rEsoUrce_SIzE_t Len,
			UnSIgnED iNt iRQ)
{
	u32 vEndor, intFcApS, intmAsk;
	iNT RC, I, irq_S, irQ_e, prObe;
	stRuct tpm_chip *chIp;
	sTrucT PriV_data *Priv;

	pRiv = dEvM_kzalLoc(dev, SizeoF(sTruct priv_data), GFp_KERnEL);
	if (priv == nULl)
		rEtuRn -eNOMEm;

	Chip = tpMm_cHip_Alloc(deV, &tpm_tis);
	IF (IS_eRr(CHIp))
		Return PTR_ERR(chip);

	chIp->VENdOr.priv = prIv;
#ifdeF cOnFig_ACPI
	chiP->aCpi_Dev_hANDle = acPi_deV_HaNdle;
#endiF

	chip->vENdOr.Iobase = dEvM_ioremAp(Dev, StaRt, len);
	IF (!chiP->vendoR.iobase)
		rEturn -eiO;

	/* Maximum timeoUTs */
	chip
.locality));
	ioread32(chi p->vendor. iobas e +  TP M_ INT_ STAT US(chip->vendo r .loc ality));
	return IRQ_H ANDLE D; }

s t at ic bo ol inte r ru p t s =  t ru e;mo d ul e_par am( interru pts, bool,  04 44 );
MODULE_PA R M_ DESC(inter rup ts, "Enableint errupt s" );stati c v oid t pm_tis _ remove (struct t pm _ chip * c hip)
{i f(chi p->flags & TPM_CH I P_ F LAG_TPM2)
		tp m2_shu td o wn ( c hip , T PM2_SU_CLE AR );

i owrite3 2 (~ T P M _GL O BAL_INT_ENABL E &
		  ior e ad3 2(chip -> ven d or.iob ase + 
	  TPM_INT_EN ABLE (chip->ve ndor.				  l o cality) ),
		 ch ip- >ven d or .i oba se +
 TPM _ INT _ENABLE( ch ip ->ven dor. l o c a lity )); 
	re lease _locality(chi p,chip - >ve ndor. local ity,  1 );
}
stati c int  t pm_tis_init(str uctdevice *d ev,  a cpi _h andle acpi_d ev_ han dle,
		resour c e_s iz e _ t  s tart, resource_siz e_ t le n,
			un signed in ti rq)
{
	u 32  ve ndor , intfc aps, in tmask;
int rc ,  i ,irq_s,ir q_e, p ro be; 
	s truct tpm_ chip * chip;
	s truct priv_data *pri v ;

	priv = de v m_ k z al l oc(d ev,  sizeof(str uctp riv_ data ) ,GFP _ KERNE L);
if (p r iv == NULL)
		retur n-ENOME M;

chip = tpmm_c hip_alloc( d e v , &tpm_t is); 	i f  (IS_ERR(chip) )
		r eturn PTR_ E RR(chip) ;

	c hip->ven dor.priv= priv;
#i fde f C ONF IG_ A C PI 
	chip->acpi_ d e v_ha nd le = ac pi_ dev_han dle ;
# end if
chip->ven dor.ioba se  =  d ev m_i orema p (dev, st ar t,le n); 
	if( !chip- >vend or.i ob as e )
	return -E I O ;

/*  M axim umti meout s */ 	ch ip
.locality));
	ioread32(chip->vendor.iobase +_TPM_INT_STATUS(chip->vendor.locality));
	return IRQ_HANDLED;
}

static_bool interrupts = true;
module_param(interrupts,_bool, 0444);
MODULE_PARM_DESC(interrupts,_"Enable_interrupts");

static void_tpm_tis_remove(struct_tpm_chip *chip)
{
	if (chip->flags_& TPM_CHIP_FLAG_TPM2)
		tpm2_shutdown(chip, TPM2_SU_CLEAR);

	iowrite32(~TPM_GLOBAL_INT_ENABLE_&
		  ioread32(chip->vendor.iobase +
			_  TPM_INT_ENABLE(chip->vendor.
					__locality)),
		  chip->vendor.iobase +
		  TPM_INT_ENABLE(chip->vendor.locality));
	release_locality(chip, chip->vendor.locality, 1);
}

static int tpm_tis_init(struct device *dev, acpi_handle acpi_dev_handle,
			resource_size_t_start,_resource_size_t len,
			unsigned_int_irq)
{
	u32_vendor, intfcaps, intmask;
	int rc, i,_irq_s, irq_e, probe;
	struct tpm_chip *chip;
	struct_priv_data *priv;

	priv_= devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL);
	if (priv == NULL)
		return_-ENOMEM;

	chip_= tpmm_chip_alloc(dev, &tpm_tis);
	if_(IS_ERR(chip))
		return PTR_ERR(chip);

	chip->vendor.priv = priv;
#ifdef CONFIG_ACPI
	chip->acpi_dev_handle = acpi_dev_handle;
#endif

	chip->vendor.iobase = devm_ioremap(dev,_start, len);
	if (!chip->vendor.iobase)
		return -EIO;

	/* Maximum timeouts_*/
	chip