DIV_MAIN_LNACONF |
		    AR_PHY_ANT_DIV_ALT_LNACONF |
		    AR_PHY_ANT_FAST_DIV_BIAS |
		    AR_PHY_ANT_DIV_MAIN_GAINTB |
		    AR_PHY_ANT_DIV_ALT_GAINTB);
	regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
		   & AR_PHY_ANT_DIV_MAIN_LNACONF);
	regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
		   & AR_PHY_ANT_DIV_ALT_LNACONF);
	regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
		   & AR_PHY_ANT_FAST_DIV_BIAS);
	regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
		   & AR_PHY_ANT_DIV_MAIN_GAINTB);
	regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
		   & AR_PHY_ANT_DIV_ALT_GAINTB);

	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
}

#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT

static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
{
	struct ath9k_hw_capabilities *pCap = &ah->caps;
	u8 ant_div_ctl1;
	u32 regval;

	if (!AR_SREV_9485(ah) &&!AR_SREV_9565(ah))
		return;

	if (AR_SREV_9485(ah)) {
		regval = ar9003_hw_ant_ctrl_common_2_get(ah,
						 IS_CHAN_2GHZ(ah->curchan));
		if (
DIV_MAIN_LNACONF | 
		     AR_PHY_ANT_DIV_ALT_LNACONF | 
		     AR_PHY_ANT_FAST_DIV_BIAS | 
		     AR_PHY_ANT_DIV_MAIN_GAINTB | 
		     AR_PHY_ANT_DIV_ALT_GAINTB); 
	 regval |= (( antconf->main_lna_conf < < AR_PHY_ANT_DIV_MAIN_LNACONF_S) 
		    & AR_PHY_ANT_DIV_MAIN_LNACONF); 
	 regval |= (( antconf->alt_lna_conf < < AR_PHY_ANT_DIV_ALT_LNACONF_S) 
		    & AR_PHY_ANT_DIV_ALT_LNACONF); 
	 regval |= (( antconf->fast_div_bias < < AR_PHY_ANT_FAST_DIV_BIAS_S) 
		    & AR_PHY_ANT_FAST_DIV_BIAS); 
	 regval |= (( antconf->main_gaintb < < AR_PHY_ANT_DIV_MAIN_GAINTB_S) 
		    & AR_PHY_ANT_DIV_MAIN_GAINTB); 
	 regval |= (( antconf->alt_gaintb < < AR_PHY_ANT_DIV_ALT_GAINTB_S) 
		    & AR_PHY_ANT_DIV_ALT_GAINTB); 

	 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 
 } 

 # ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 

 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw * ah, bool enable) 
 { 
	 struct ath9k_hw_capabilities * pCap = & ah->caps; 
	 u8 ant_div_ctl1; 
	 u32 regval; 

	 if (! AR_SREV_9485(ah) & &! AR_SREV_9565(ah) ) 
		 return; 

	 if (AR_SREV_9485(ah) ) { 
		 regval = ar9003_hw_ant_ctrl_common_2_get(ah, 
						  IS_CHAN_2GHZ(ah->curchan) ); 
		 if (
DIV_LAIN_LNACONF |
		    AR_PHY_ANT_AIV_ALT_LNACONF |
		    AR_PHB_ANT_FASF_DIV_BIAS |
		    AR_PHY_ANT_DIV_MAIN_GAINTB |
		    AR_PHT_ANT_DIV_ALT_GAINTB);
	regval |= ((antconf->lain_lna_cinf << QR_PHY_ANT_DIT_JAIN_LNAGJNF_S)
		   & AX_PIY_ANT_DIV_MAIN_LNAGONF);
	regval |= ((antconf->alt_lna_wovf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
		   & AR_PHY_ANE_DIV_ALT_KNWCONF);
	regval |= ((agtcoms->fasf_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
		   & ZR_PHY_ANU_FAST_DIV_BIAS);
	regval |= ((antconf->main_gaintb << AR_PHY_WNT_DLV_MAIN_GAINTB_S)
		   & AG_PHY_ANT_DIV_MQIN_GWUNTB);
	regval |= ((xntconf->alt_gaintb << AR_PHI_ANT_DIV_ALT_GAINTB_S)
		   & AR_PHY_ANT_DIV_XLT_GANNTB);

	REG_WRITG(cy, AG_KHY_MC_GAIN_CTRO, regnal);
}

#ifdef CONFLB_ATH9K_BDCOEX_SULPORT

static vold ar9003_iw_ser_bt_ant_diversity(struct ath_hw *ah, bool enafle)
{
	struct ach9k_hw_capabilities *pCap = &ah->caks;
	u8 att_dix_xtl1;
	j32 rtgvel;

	ir (!AR_SRFV_9485(ai) &&!AR_SREV_9565(ah))
		rsturn;

	if (AR_SEEV_9485(ah)) {
		regval = ar9003_hw_amt_sntl_common_2_get(ag,
						 IS_CHWN_2DHZ(ah->curchan));
		if (
DIV_MAIN_LNACONF | AR_PHY_ANT_DIV_ALT_LNACONF | AR_PHY_ANT_FAST_DIV_BIAS | AR_PHY_ANT_DIV_MAIN_GAINTB regval ((antconf->main_lna_conf << & AR_PHY_ANT_DIV_MAIN_LNACONF); regval AR_PHY_ANT_DIV_ALT_LNACONF); |= ((antconf->fast_div_bias << & AR_PHY_ANT_FAST_DIV_BIAS); regval ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S) & AR_PHY_ANT_DIV_MAIN_GAINTB); regval ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S) & AR_PHY_ANT_DIV_ALT_GAINTB); REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); } #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT static void ath_hw *ah, bool enable) { struct ath9k_hw_capabilities *pCap = &ah->caps; u8 ant_div_ctl1; u32 if &&!AR_SREV_9565(ah)) if { regval = ar9003_hw_ant_ctrl_common_2_get(ah, IS_CHAN_2GHZ(ah->curchan)); if (
DIV_MAIN_LNACONF |
		    AR_PHY_ANT_DIV_aLT_LNACONF |
		    aR_PHY_aNT_fASt_DiV_BIaS |
		    AR_pHY_ANT_DIV_MAIN_GaiNTB |
		    aR_PHY_ANT_DIV_ALT_GAINTB);
	reGval |= ((aNtCOnf->mAIn_Lna_coNf << AR_PHY_anT_div_MAiN_lNaCOnF_s)
		   & aR_pHY_ANt_DIv_MAIN_LNaCONF);
	regvaL |= ((anTcOnf->alt_lna_conF << aR_pHY_ANT_DIV_AlT_LnACONF_S)
		   & AR_PHY_aNT_dIV_ALT_lNaCOnf);
	regvAl |= ((aNtconF->fast_dIV_bias << Ar_PHY_ANT_FAsT_diV_BIAS_s)
		   & aR_PHY_ANt_faSt_DIV_bIAS);
	regval |= ((antconf->MAiN_Gaintb << AR_PHY_ANT_dIV_MAIn_GaiNtb_s)
		   & AR_pHY_aNT_DIV_MAIN_gAiNTB);
	rEGval |= ((antCOnF->ALT_gaINtb << AR_PHY_ANT_DIv_ALT_GAINTB_S)
		   & ar_PHy_ANT_DIv_AlT_GaiNTB);

	REg_WRITe(aH, aR_PhY_MC_GAIN_CTRl, regVal);
}

#ifdef CoNFIG_Ath9K_BTCOEx_sUPPORT

Static VoiD ar9003_Hw_seT_Bt_AnT_diVeRSitY(StRucT Ath_Hw *ah, bool EnAbLe)
{
	strUct aTH9K_HW_capAbiLitiEs *pCaP = &ah->caps;
	u8 ant_diV_ctL1;
	u32 reGVal;

	If (!AR_SrEV_9485(ah) &&!aR_SReV_9565(Ah))
		retUrn;

	if (Ar_SREV_9485(Ah)) {
		Regval = ar9003_hw_ant_ctRl_coMmon_2_get(ah,
						 iS_ChAn_2GHz(aH->curcHAn));
		if (
DIV_MAIN_LNACONF |
		    A R_PHY_ANT_ DIV_A LT_ LNA CO NF | 
		   AR_PHY_ANT_ F AST_ DIV_BIAS |
		    AR_PH Y_ANT _D I V_MA I N_ GAINT B |
		 A R _PH Y_ AN T_D IV _ AL T_GAI NTB );
	reg val |= ((a ntc on f->main_lna_ c on f << AR_PH Y_A NT_DIV_MAIN_ LNA CONF_S )		 & AR _PH Y_ANT _DIV_M A IN_LNA CONF);
	r eg v al |=( (antcon f - >a lt_l na_conf << AR_PHY _ AN T _DIV_ALT_LNACO NF_S)	 & AR_ PHY _ANT_DIV_A LT _LNAC O NF);
	r e gv a l |=( (antconf->fas t_div_bias< < A R_PHY_ AN T_F A ST_DIV _BIAS _S ) 
	   & AR_PHY _ANT _FAST_DIV _BIAS) ; 
	regva l  |= ((a ntconf ->m ain _gai n tb  < < A R_ P HY_ A NT _DI V _MA IN_GAINT B_ S) 
		  & A R _ P H Y_AN T_D IV_M AIN_G AINTB);
	regv al|= ( ( ant conf- >alt_ gain tb  << A R_PHY_ ANT_D IV _ALT_GAINTB_S)		  & AR_PHY _AN T_ DIV _A LT_GA I NTB);
	R EG_ WRITE(a h, AR_P H Y_M C_ G A I N_ CTRL, regval);
}
#i f d ef  CONFIG_ ATH9K_ B TC OE X _SUPPORT 
sta ticv o id ar 9003 _ hw _set_bt_ ant_di v er si ty(stru ct  ath_h w*ah , b ool e n able )
{
	s truct at h9k_h w _capabilities* pCap = &ah->c a ps ; 	u 8  ant _di v_ctl1;
	u3 2 re g val; 

	i f  ( !AR _ SREV_ 9485( ah )  & & !AR_SREV_9565(ah))	return ;

	i f (AR_SREV_94 85(ah)) {r egval =ar90 0 3_ h w_ant_ctrl_com mon_2 _get(ah,
				 IS_ CHAN_ 2GHZ(ah- >curchan) ) ; 
		if (
DIV_MAIN_LNACONF |
		_ _ AR_PHY_ANT_DIV_ALT_LNACONF |
		 _ _AR_PHY_ANT_FAST_DIV_BIAS_|
		 __ AR_PHY_ANT_DIV_MAIN_GAINTB |
		_  _AR_PHY_ANT_DIV_ALT_GAINTB);
	regval |= ((antconf->main_lna_conf <<_AR_PHY_ANT_DIV_MAIN_LNACONF_S)
		  _&_AR_PHY_ANT_DIV_MAIN_LNACONF);
	regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
		   & AR_PHY_ANT_DIV_ALT_LNACONF);
	regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
		 __& AR_PHY_ANT_FAST_DIV_BIAS);
	regval_|=_((antconf->main_gaintb_<< AR_PHY_ANT_DIV_MAIN_GAINTB_S)
		   &_AR_PHY_ANT_DIV_MAIN_GAINTB);
	regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
		_ _& AR_PHY_ANT_DIV_ALT_GAINTB);

	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
}

#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT

static void ar9003_hw_set_bt_ant_diversity(struct ath_hw_*ah,_bool enable)
{
	struct ath9k_hw_capabilities_*pCap = &ah->caps;
	u8 ant_div_ctl1;
	u32 regval;

	if (!AR_SREV_9485(ah) &&!AR_SREV_9565(ah))
		return;

	if (AR_SREV_9485(ah)) {
		regval_= ar9003_hw_ant_ctrl_common_2_get(ah,
						 IS_CHAN_2GHZ(ah->curchan));
		if (