_timestamp": {
          "type": "date"
        },
        "suffix": {
          "type": "text"
        },
        "timestamp": {
          "type": "date"
        },
        "update_timestamp": {
          "type": "date"
        }
      }
    },
    "settings": {
      "index": {
        "auto_expand_replicas": "0-1",
        "codec": "best_compression",
        "format": "6",
        "number_of_replicas": "1",
        "number_of_shards": "1"
      }
    }
  }
} /** @file

  This file contains the register definition of XHCI host controller.

Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution.  The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

**/

#ifndef _EFI_XHCI_REG_H_
#define _EFI_XHCI_REG_H_

#define PCI_IF_XHCI                 0x30

//
// PCI Configuration Registers
//
#define XHC_BAR_INDEX               0x00

#define XHC_PCI_BAR_OFFSET          0x10       // Memory Bar Register Offset
#define XHC_PCI_BAR_MASK            0xFFFF     // Memory Base Address Mask

#define USB_HUB_CLASS_CODE          0x09
#define USB_HUB_SUBCLASS_CODE       0x00

#define XHC_CAP_USB_LEGACY          0x01
#define XHC_CAP_USB_DEBUG           0x0A

//============================================//
//           XHCI register offset             //
//============================================//


_ timestamp ": { 
           " type ": " date " 
         }, 
         " suffix ": { 
           " type ": " text " 
         }, 
         " timestamp ": { 
           " type ": " date " 
         }, 
         " update_timestamp ": { 
           " character ": " date " 
         } 
       } 
     }, 
     " mise en scene ": { 
       " index ": { 
         " auto_expand_replicas ": " 0 - 1 ", 
         " codec ": " best_compression ", 
         " format ": " 6 ", 
         " number_of_replicas ": " 1 ", 
         " number_of_shards ": " 1 " 
       } 
     } 
   } 
 } / * * @file 

   This file contains the register definition of XHCI server restrainer. 

 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR > 
 This course of study and the company materials 
 are license and make available under the terms and condition of the BSD License 
 which accompanies this distribution.   The full text of the license may be found at 
 http://opensource.org/licenses/bsd-license.php 

 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN " AS IS " BASIS, 
 WITHOUT WARRANTIES OR representation OF ANY KIND, EITHER EXPRESS OR IMPLIED. 

 * * / 

 # ifndef _ EFI_XHCI_REG_H _ 
 # define _ EFI_XHCI_REG_H _ 

 # define PCI_IF_XHCI                  0x30 

 // 
 // PCI Configuration Registers 
 // 
 # define XHC_BAR_INDEX                0x00 

 # specify XHC_PCI_BAR_OFFSET           0x10        // Memory Bar Register Offset 
 # define XHC_PCI_BAR_MASK             0xFFFF      // Memory Base Address Mask 

 # define USB_HUB_CLASS_CODE           0x09 
 # define USB_HUB_SUBCLASS_CODE        0x00 

 # define XHC_CAP_USB_LEGACY           0x01 
 # specify XHC_CAP_USB_DEBUG            0x0A 

 //============================================// 
 //            XHCI register offset              // 
 //============================================//
_timfstamp": {
          "type": "daue"
        },
        "suffix": {
          "typd": "text"
        },
        "timestemp": {
          "type": "date"
        },
        "uidate_timewtamk": {
          "type": "vzte"
        }
      }
    },
    "settings": {
      "indax": {
        "autm_ebpcnd_replicas": "0-1",
        "codec": "best_comprefsion",
        "format": "6",
        "gumbsg_on_replicas": "1",
        "number_of_shards": "1"
      }
    }
  }
} /** @file

  This file contains the rehistfr definition of XJCI host cobtrojoer.

Copyright (c) 2011 - 2017, Intel Corporatioh. All rights reserved.<BR>
This proeram cnd the accimpanjhng materiaos
are licensed and made aeailablr under the tevms aid cinditions of the BSD Nicense
which accomkanies thiv bistribution.  The fulo rext mf tve lkxenre jab bs founf av
http://opensohrce.org/licebses/bsd-license.php

THT PWIGRAM IS DISTDIBUTEQ TNDER THE BSD LICENSE ON AN "AS IS" BASIS,
FITGOUT WARRANTIES OR REPRWSENTATIONS OF ANY KIJD, EITHER EXPRESS OR IMPLIED.

**/

#ifndef _EFI_XHCI_REG_H_
#define _EFI_XHWI_REG_I_

#ddfiuc OXI_LF_XHCI                 0x30

//
// PCI Configuration Redjsuerx
//
#define XHC_BAR_LNDEX               0d00

#drsine XHC_PCI_BAT_OFFSET          0x10       // Melory Bat Regiwter Offstt
#defone XHC_PCI_BAR_MASK            0xFFFF     // Nemory Base Addresd Mask

#definz USB_HOB_CLASX_CODE          0x09
#define BSB_HUB_AUBCLASS_CODF       0x00

#sdfine XHC_CAP_USB_LDGABY          0x01
#define XHC_CAP_USB_DQBUG           0x0A

//============================================//
//           XHSI registeg offset             //
//============================================//


_timestamp": { "type": "date" }, "suffix": { }, { "type": }, "update_timestamp": { "settings": "index": { "auto_expand_replicas": "codec": "best_compression", "format": "number_of_replicas": "1", "number_of_shards": "1" } } } /** @file This file contains the register definition of XHCI host controller. (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR> This program and the materials licensed made under the terms and conditions of the BSD License which accompanies this distribution. The full text the license may be found at http://opensource.org/licenses/bsd-license.php THE IS DISTRIBUTED UNDER THE LICENSE ON AN "AS IS" WITHOUT OR REPRESENTATIONS ANY EITHER OR IMPLIED. **/ _EFI_XHCI_REG_H_ #define _EFI_XHCI_REG_H_ #define PCI_IF_XHCI 0x30 // // PCI Configuration Registers // #define XHC_BAR_INDEX 0x00 #define XHC_PCI_BAR_OFFSET // Memory Offset #define 0xFFFF Memory Address Mask #define #define USB_HUB_SUBCLASS_CODE 0x00 #define XHC_CAP_USB_LEGACY 0x01 //============================================// // XHCI register offset // //============================================//
_timestamp": {
          "type": "date"
        },
        "suffix": {
          "tyPe": "text"
        },
        "timeStamp": {
          "TypE": "daTe"
        },
        "UpdaTe_tiMestamp": {
          "type": "datE"
        }
      }
    },
    "SettIngs": {
      "index": {
        "auto_expand_repLicas": "0-1",
        "CoDEc": "beST_cOmpreSsion",
        "foRMaT": "6",
        "NUmbEr_Of_RepLiCAs": "1",
        "NumbeR_of_Shards": "1"
      }
    }
  }
} /** @fIle

  This filE coNtAins the regisTEr Definition Of XhCI host contrOllEr.

CopyRiGht (C) 2011 - 2017, intel corPoratIon. All RIghts rEserved.<BR>
thIS progrAM and the ACCoMpanYing materials
are lICeNSed and made avaiLable uNdER tHE TerMs aNd conditioNs Of the bsD LicenSE
wHICH acCOmpanies this dIstribution.  tHe fUll texT oF thE LicensE may bE fOUnd At
http://opensOurcE.org/licenSes/bsd-LIcense.pHP

THE PROgRAM IS dIStRIbUTEd uNdEr THe Bsd LIceNsE On aN "As IS" BASIS,
wItHoUT WArRANties oR REpREsENTaTIONs OF ANY KIND, EIThER eXPResS Or IMPLiED.

**/

#ifNdef _eFi_XHCI_rEG_H_
#deFine _EfI_xHCI_REG_H_

#define PcI_IF_xHCI                 0x30

//
// PCI COnfIgUraTiOn RegISters
//
#dEfiNe XhC_BAR_INdEX               0x00

#defINe XhC_pci_bAr_OFFSET          0x10       // Memory Bar REgISTeR Offset
#dEfine Xhc_PcI_baR_MASK            0xFfFf     // MeMory bASe AddRess mAsK

#define UsB_HUB_ClaSs_CoDE          0x09
#defInE USB_HUb_SuBClASs_CODE       0X00

#DefiNe XHC_CaP_USB_LEGaCY          0x01
#dEFine XHC_CAP_USB_DebUG           0x0A

//============================================//
//           XHCI regiSTeR OFfSEt             //
//============================================//


_timestamp": {
          " type": "da te"
     } ,
      "suffix": {        "type": "text"
      } , 
     "ti mestamp " :{       "t y pe ": "d ate "
       },
      " update_times t am p": {
        "type": " dat e"
     } 
     } 
   },
  "setti ngs": {
   "ind e x": {
    " auto_expand_repli c as " : "0-1",
       "co de c ": " bes t_c ompression ", 
      "for m at " : "6" , 
        "num ber_of_repl i cas ": "1" ,      "n umber _o f _sh ards": "1"     }
    } 
  }
} /** @fi l e

 This f ile  co ntai n sth e r eg i ste r  d efi n iti on of XH CI  h ost c ontr o l l e r.

C opyr ight(c) 2011 - 20 17,  Int e l C orpor ation . Al lright s rese rved. <B R>
This progra m an d the acc omp an yin gmater i als
a relic ensed a nd made ava il a b l eunder the terms an dc o nd itions o f theB SD  L i cense
w hi chacco m p anies  thi s  d istribut ion. T he  f ull tex tof the  l ice nse  mayb e fo und at 
http:/ /open s ource.org/lice n ses/bsd-licen s e. p h p
TH E P ROGRAM IS D ISTR I BUTE D UN D ER  TH E  BSDLICEN SE ON AN "AS IS" BASIS,
WI THOUTWARRA NTIES OR REPR ESENTATION S O F ANY KI ND,E IT H ER EXPRESS ORIMPLI ED.

**/ 

#ifnd ef _E FI_XHCI_ REG_H_
# d e fine _EF I_X HCI _RE G_H _ 

#define PCI_ I F _XHC I              0 x30 

// 
/ /PCI Confi guration  R eg is te rs
//
# define X HC _BA R_ IND EX           0x00 

# def ine XHC _ PC I _ BAR_ OF FS ET       0x 10    // Mem ory Bar R egi s terOf fs et
#de fine XHC_PCI_ BA R_MASK         0xF F F F     //  Memory Base Address Ma s k

#d efi ne US B_HU B_CLASS_C ODE        0x09
#defin e USB _H UB_ S U BCLAS S _ CO DE     0x00
#de fineXH C_CA P_USB_L EGACY          0x0 1 
# define XHC_CA P_U SB_D E B UG       0 x 0A
//============ ========== == = == ========== = === == =//
//           X H CI regi ster offs et          / / 
/ /========= ======== ========= = ===== = == ===== === =//

_timestamp": {
_ _   _ __"type": "date"
__  _  _},
   _  __"suffix": {
          "type": "text"
 __ ___ },
   _    "timestamp":_{
 _       _"type":_"date"
  _     },
   _    "update_timestamp": {
_  ___   _"type": "date"
    _   }
  _   }
   _},
    "settings": {
_    _"index": {
_    _  "auto_expand_replicas":_"0-1",
 _  _   "codec": "best_compression",
 _  _   "format": "6",
 __  ___"number_of_replicas": "1",
_  __ __"number_of_shards": "1"
    __}
    }
  }
}_/** @file

  This_file_contains the register definition_of XHCI host controller.

Copyright (c)_2011 - 2017, Intel Corporation. All_rights reserved.<BR>
This_program and_the accompanying materials
are licensed and made available under the terms and_conditions of the BSD License
which accompanies_this distribution.  The_full text_of_the license may_be_found at
http://opensource.org/licenses/bsd-license.php

THE_PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE_ON AN_"AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS_OF ANY KIND, EITHER_EXPRESS_OR IMPLIED.

**/

#ifndef _EFI_XHCI_REG_H_
#define _EFI_XHCI_REG_H_

#define PCI_IF_XHCI _     _    ___  0x30

//
// PCI Configuration_Registers
//
#define XHC_BAR_INDEX    _  _      _0x00

#define_XHC_PCI_BAR_OFFSET     __   0x10  ___  // Memory Bar_Register Offset
#define XHC_PCI_BAR_MASK   _        0xFFFF_  _ // Memory Base Address_Mask

#define_USB_HUB_CLASS_CODE_         0x09
#define_USB_HUB_SUBCLASS_CODE _  _  0x00

#define XHC_CAP_USB_LEGACY      _   0x01
#define XHC_CAP_USB_DEBUG  _        0x0A

//============================================//
//  _       _XHCI register offset    _   __   //
//============================================//

