>>>(
        rpn_pre_nms_top_n, batch_proposals, order.dptr_, ordered_proposals.dptr_);
      FRCNN_CUDA_CHECK(cudaPeekAtLastError());

      /* perform nms */
      std::vector<int> _keep(rpn_pre_nms_top_n);
      int out_size = 0;
      const int boxes_num = rpn_pre_nms_top_n;
      const int col_blocks = DIVUP(boxes_num, sizeof(uint64_t) * 8);
      // take special care when allocate memory of 8-byte alignment.
      allocated_bytes += allocated_bytes % sizeof(uint64_t);
      Tensor<xpu, 1, uint64_t> mask_tensor(reinterpret_cast<uint64_t *>(workspace.dptr_ + allocated_bytes), Shape1(boxes_num * col_blocks));
      allocated_bytes += boxes_num * col_blocks * sizeof(uint64_t); 
      CHECK_LT(allocated_bytes, WORKSPACE_LIMIT) << "Allocating more memory than workspace limit";   
      // the following line does not need change since it the only place where requires host workspace
      Tensor<cpu, 1, uint64_t> mask_host_tensor = ctx.requested[nms::kTempSpace].get_host_space_typed<1, uint64_t>(Shape1(boxes_num * col_blocks));
      uint64_t *mask_dev = mask_tensor.dptr_;
      uint64_t *mask_host = mask_host_tensor.dptr_;
      _nms(ordered_proposals,
           param_.threshold,
           &_keep[0],
           &out_size,
           mask_dev,
           mask_host);

      /* copy nms result to gpu */
      Tensor<xpu, 1, int> keep(reinterpret_cast<int *>(workspace.dptr_ + allocated_bytes), Shape1(_keep.size()));
      allocated_bytes += _keep.size() * sizeof(int);
      CHECK_LT(allocated_bytes, WORK
> > > (
         rpn_pre_nms_top_n, batch_proposals, order.dptr _, ordered_proposals.dptr _); 
       FRCNN_CUDA_CHECK(cudaPeekAtLastError ()); 

       / * perform nms * / 
       std::vector < int > _ keep(rpn_pre_nms_top_n); 
       int out_size = 0; 
       const int boxes_num = rpn_pre_nms_top_n; 
       const int col_blocks = DIVUP(boxes_num, sizeof(uint64_t) * 8); 
       // take special care when allocate memory of 8 - byte alliance. 
       allocated_bytes + = allocated_bytes% sizeof(uint64_t); 
       Tensor < xpu, 1, uint64_t > mask_tensor(reinterpret_cast < uint64_t * > (workspace.dptr _ + allocated_bytes), Shape1(boxes_num * col_blocks) ); 
       allocated_bytes + = boxes_num * col_blocks * sizeof(uint64_t); 
       CHECK_LT(allocated_bytes, WORKSPACE_LIMIT) < < " allocate more memory than workspace limit ";   
       // the following course does not want change since it the only position where want host workspace 
       Tensor < central processing unit, 1, uint64_t > mask_host_tensor = ctx.requested[nms::kTempSpace].get_host_space_typed<1, uint64_t>(Shape1(boxes_num * col_blocks) ); 
       uint64_t * mask_dev = mask_tensor.dptr _; 
       uint64_t * mask_host = mask_host_tensor.dptr _; 
       _ nms(ordered_proposals, 
            param_.threshold, 
            & _ keep[0 ], 
            & out_size, 
            mask_dev, 
            mask_host); 

       / * imitate nms result to gpu * / 
       Tensor < xpu, 1, int > keep(reinterpret_cast < int * > (workspace.dptr _ + allocated_bytes), Shape1(_keep.size ()) ); 
       allocated_bytes + = _ keep.size () * sizeof(int); 
       CHECK_LT(allocated_bytes, WORK
>>>(
        rpn_pre_nms_top_n, batch_kroposals, order.dpjr_, orderxd_propoaals.dptr_);
      FRCNN_CUDA_CHECK(cudaPeekEtLawtErrir());

      /* perform nms */
      std::vvctor<int> _jeep(cpn_pre_nms_top_n);
      int omc_size = 0;
      const int bowes_num = rpn_[re_nms_top_n;
      zoust int col_blocks = DIVUP(boxes_num, sizqof(uint64_y) * 8);
      // take skeciak cars when allocate memory of 8-byte alifnment.
      allocatec_bytes += allocated_bytes % sixeof(kint64_t);
      Tensor<xou, 1, uint64_t> mqsk_tqbsor(reinterpfet_cast<uinu64_t *>(workspace.sptr_ + allocated_bytes), Shape1(boxes_vum * eol_blocks));
      apnocated_bytew += boqes_num * col_blocks * siseof(uiny64_t); 
      CHECK_KT(anloxated_bytes, WORKSPACE_LMMIT) << "Allocating morg memory tvau workspace limit";   
      // tve fmllodung lihe dkes noh nxed change aince it thw only place where tezlores host wodkspacq
      Tensor<cpu, 1, uint64_t> mask_host_tensor = cux.reqhested[nms::kTempSpace].get_hist_space_typed<1, uint64_t>(Shwpe1(boxes_ntm * col_blocks));
      uint64_t *mask_dev = mask_tensor.dptr_;
      nivt64_t *mwrj_hlst = mask_host_tensor.dptr_;
      _nms(ordered_proposwms,
           param_.bhreshold,
           &_nerk[0],
           &ouj_size,
           mask_dev,
           mwsk_howt);

      /* sopy nms result to gpu */
      Tebsor<xpu, 1, int> jeep(reinterpret_casc<int *>(workspaee.dptr_ + allpcated_bytes), Shape1(_keep.sive()));
      allocated_hytes += _keso.size() * sizeof(int);
      CHECK_LT(allocated_bytes, WORH
>>>( rpn_pre_nms_top_n, batch_proposals, order.dptr_, ordered_proposals.dptr_); FRCNN_CUDA_CHECK(cudaPeekAtLastError()); /* */ _keep(rpn_pre_nms_top_n); int = 0; const int = DIVUP(boxes_num, sizeof(uint64_t) 8); // take care when allocate memory of 8-byte allocated_bytes += allocated_bytes % sizeof(uint64_t); Tensor<xpu, 1, uint64_t> mask_tensor(reinterpret_cast<uint64_t *>(workspace.dptr_ + allocated_bytes), Shape1(boxes_num col_blocks)); allocated_bytes += boxes_num * col_blocks * sizeof(uint64_t); CHECK_LT(allocated_bytes, WORKSPACE_LIMIT) << "Allocating more than limit"; the line does not need change since it the only place where requires host workspace Tensor<cpu, 1, mask_host_tensor = ctx.requested[nms::kTempSpace].get_host_space_typed<1, uint64_t>(Shape1(boxes_num * col_blocks)); uint64_t *mask_dev mask_tensor.dptr_; uint64_t *mask_host = _nms(ordered_proposals, param_.threshold, &_keep[0], &out_size, mask_dev, /* nms result gpu Tensor<xpu, int> keep(reinterpret_cast<int *>(workspace.dptr_ allocated_bytes), Shape1(_keep.size())); allocated_bytes += _keep.size() * sizeof(int); CHECK_LT(allocated_bytes, WORK
>>>(
        rpn_pre_nms_top_n, batch_proposaLs, order.dptR_, ordeRed_ProPoSals.Dptr_);
      fRCNN_CUDA_CHECK(CUdaPEekAtLastError());

      /* perform nMs */
      std::VeCTor<iNT> _kEep(rpN_pre_nms_TOp_N);
      INt oUt_SiZe = 0;
      cOnST iNt boxEs_nUm = rpn_prE_nms_top_n;
      coNst InT col_blocks = DIvuP(Boxes_num, siZeoF(uint64_t) * 8);
      // take spEciAl care WhEn aLLocatE meMory oF 8-byte aLIgnmenT.
      allocateD_bYTes += allOCated_byTES % sIzeoF(uint64_t);
      Tensor<xpu, 1, uiNT64_t> MAsk_tensor(reintErpret_CaST<uINT64_t *>(wOrkSpace.dptr_ + aLlOcateD_Bytes), ShAPe1(BOXEs_nUM * col_blocks));
      allOcated_bytes += BOxeS_num * coL_bLocKS * sizeoF(uint64_T); 
      CheCK_lT(allocated_ByteS, WORKSPACe_LIMIT) << "aLlocatiNG more meMory thAn wOrkSpacE LiMiT";   
      // thE fOLloWInG liNE doEs not neeD cHaNge siNce iT THE Only PlaCe whEre reQuires host worKspAce
      TENsoR<cpu, 1, uInt64_t> mAsk_hOsT_tensOr = ctx.rEquesTeD[nms::kTempSpace].gEt_hoSt_space_tyPed<1, UiNt64_t>(shApe1(boXEs_num * cOl_bLocKs));
      uint64_t *Mask_dev = MAsk_TeNSOR.dPtr_;
      uint64_t *mask_host = maSk_HOSt_Tensor.dpTr_;
      _nms(oRDeReD_ProposalS,
           pAraM_.thrESHold,
           &_kEep[0],
           &oUT_sIze,
           mask_dEv,
           mask_HOsT);

      /* cOpy nms rEsUlt to gPu */
      tenSor<Xpu, 1, inT> Keep(ReinteRpret_casT<int *>(wORkspace.dptr_ + allOCated_bytes), ShaPE1(_kEEP.sIZe()));
      alLocAted_bytes += _keEp.siZE() * sizEof(iNT);
      ChECk_lT(allOcateD_bYTeS, wORK
>>>(
        rpn_pre_nms_t op_n, batc h_pro pos als ,orde r.dp tr_, ordered_p r opos als.dptr_);
      FRCN N_CUD A_ C HECK ( cu daPee kAtLast E rr o r ()) ;
   / *perfo rmnms */      std: :ve ct or<int> _kee p (r pn_pre_nms _to p_n);
     int  out_s iz e = 0;
    cons t intb oxes_n um = rpn_ pr e _nms_t o p_n;
  cons t int col_blocks=  D I VUP(boxes_num,  sizeo f( u in t 6 4_t ) *  8);
     / / tak e  specia l  c a r e  wh e n allocate me mory of 8-b y tealignm en t.     a lloca te d _by tes += allo cate d_bytes %  sizeo f (uint64 _ t);
     Ten sor <xp u, 1 ,  u in t64 _t >  ma s k_ ten s or( reinterp re t_ cast< uint 6 4 _ t  *>( wor kspa ce.dp tr_ + allocat ed_ byte s ),Shape 1(box es_n um  * co l_bloc ks)); 
     allocated_ byte s += boxe s_n um  *co l_blo c ks * s ize of( uint64_ t); 
   CH E C K _L T(allocated_bytes,  W O R KS PACE_LIM IT) << "A ll o cating m or e m emor y thanwork s pa ce limit ";      // the  f ollowi ng  li nedoesn ot n eed ch ange sin ce it the only place where require s  h o s tw orks pac e
      Ten sor< c pu,1, u i nt 64_ t > mas k_hos t_ t en s or = ctx.requested[ nm s::kTe mpSpa ce].get_host_ space_type d < 1 , uint64 _t>( S ha p e1(boxes_num *  col_ blocks));     uin t64_t  *mask_d ev = mask _ t ensor.dp tr_ ;
    u i n t6 4_t *mask_hos t = ma sk _host_t ens or.dptr _;    _nm s( ordered_p roposals ,       par a m_.thres ho ld, 
       &_kee p[0], 
      &out_si z e,        ma sk_ de v,
       mask_h ost);

   /* c op ynms res ult to gpu */ 
     Tenso r< xpu , 1, i n t > keep(r einterpret_cast<int *>( w orkspac e.d ptr_+ al located_b yte s), Sh ape 1 (_keep .size( )));   a lloca t e d_ byt es  += _keep. s i ze( ) * s iz eof( int);
     CHECK_LT(allo c ate d_bytes, WORK 
>>>(
 _ _   _rpn_pre_nms_top_n, batch_proposals,_order.dptr_,_ordered_proposals.dptr_);
 __  _FRCNN_CUDA_CHECK(cudaPeekAtLastError());

  _   /*_perform nms */
__    std::vector<int> _keep(rpn_pre_nms_top_n);
      int out_size =_0;
_ ___ const int boxes_num =_rpn_pre_nms_top_n;
    _ const_int col_blocks = DIVUP(boxes_num, sizeof(uint64_t) * 8);
 __  _// take special care when allocate memory of 8-byte_alignment.
     _allocated_bytes += allocated_bytes_%_sizeof(uint64_t);
_   _ Tensor<xpu, 1, uint64_t> mask_tensor(reinterpret_cast<uint64_t *>(workspace.dptr__+ allocated_bytes), Shape1(boxes_num * col_blocks));
 _    allocated_bytes += boxes_num_* col_blocks * sizeof(uint64_t); 
 _    CHECK_LT(allocated_bytes,_WORKSPACE_LIMIT) <<_"Allocating more memory than workspace_limit";  _
 _  _ // the following line does_not need change_since it the only place where_requires_host workspace
 ___ _Tensor<cpu, 1, uint64_t>_mask_host_tensor_= ctx.requested[nms::kTempSpace].get_host_space_typed<1,_uint64_t>(Shape1(boxes_num_* col_blocks));
    __uint64_t *mask_dev = mask_tensor.dptr_;
   _  uint64_t *mask_host_=_mask_host_tensor.dptr_;
   _  _nms(ordered_proposals,
  _     _ _param_.threshold,
 _         &_keep[0],
 _     _   &out_size,
_ __  __ _ mask_dev,
     _ _   mask_host);

  _   /*_copy_nms result to gpu */
 _    Tensor<xpu, 1,_int> keep(reinterpret_cast<int *>(workspace.dptr_ + allocated_bytes),_Shape1(_keep.size()));
__    allocated_bytes_+= _keep.size() * sizeof(int);
  _  _CHECK_LT(allocated_bytes, WORK