RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET)

/* Register Bitfield Definitions ********************************************************************/

/* Clock control register */

#define RCC_CR_HSION                (1 << 0)  /* Bit 0: Internal High Speed clock enable */
#define RCC_CR_HSIRDY               (1 << 1)  /* Bit 1: Internal High Speed clock ready flag */
#define RCC_CR_HSITRIM_SHIFT        (3)       /* Bits 7-3: Internal High Speed clock trimming */
#define RCC_CR_HSITRIM_MASK         (0x1f << RCC_CR_HSITRIM_SHIFT)
#define RCC_CR_HSICAL_SHIFT         (8)       /* Bits 15-8: Internal High Speed clock Calibration */
#define RCC_CR_HSICAL_MASK          (0xff << RCC_CR_HSICAL_SHIFT)
#define RCC_CR_HSEON                (1 << 16) /* Bit 16: External High Speed clock enable */
#define RCC_CR_HSERDY               (1 << 17) /* Bit 17: External High Speed clock ready flag */
#define RCC_CR_HSEBYP               (1 << 18) /* Bit 18: External High Speed clock Bypass */
#define RCC_CR_CSSON                (1 << 19) /* Bit 19: Clock Security System enable */
#define RCC_CR_PLLON                (1 << 24) /* Bit 24: PLL enable */
#define RCC_CR_PLLRDY               (1 << 25) /* Bit 25: PLL clock ready flag */
#define RCC_CR_PLLI2SON             (1 << 26) /* Bit 26: PLLI2S enable */
#define RCC_CR_PLLI2SRDY            (1 << 27) /* Bit 27: PLLI2S clock ready flag */
#define RCC_CR_PLLSAION             (1 << 28) /* Bit 28: PLLSAI enable */
#define RCC_CR_PLLSAIRDY            (1 << 29) /* Bit 29: PLLSAI clock ready flag */

/* PLL configuration register */

#define RCC_PLLCFG_PLLM_SHIFT       (0)      /* Bits 0-5: Main PLL (PLL) and audio PLL
RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET) 

 / * Register Bitfield Definitions * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * / 

 / * Clock control register * / 

 # define RCC_CR_HSION                 (1 < < 0)   / * Bit 0: Internal High Speed clock enable * / 
 # specify RCC_CR_HSIRDY                (1 < < 1)   / * piece 1: Internal High Speed clock ready flag * / 
 # define RCC_CR_HSITRIM_SHIFT         (3)        / * bit 7 - 3: Internal High Speed clock trimming * / 
 # specify RCC_CR_HSITRIM_MASK          (0x1f < < RCC_CR_HSITRIM_SHIFT) 
 # specify RCC_CR_HSICAL_SHIFT          (8)        / * Bits 15 - 8: Internal High Speed clock Calibration * / 
 # specify RCC_CR_HSICAL_MASK           (0xff < < RCC_CR_HSICAL_SHIFT) 
 # define RCC_CR_HSEON                 (1 < < 16) / * Bit 16: External High Speed clock enable * / 
 # specify RCC_CR_HSERDY                (1 < < 17) / * Bit 17: External High Speed clock ready flag * / 
 # specify RCC_CR_HSEBYP                (1 < < 18) / * Bit 18: External High Speed clock Bypass * / 
 # specify RCC_CR_CSSON                 (1 < < 19) / * Bit 19: Clock Security System enable * / 
 # define RCC_CR_PLLON                 (1 < < 24) / * Bit 24: PLL enable * / 
 # define RCC_CR_PLLRDY                (1 < < 25) / * Bit 25: PLL clock ready flag * / 
 # define RCC_CR_PLLI2SON              (1 < < 26) / * Bit 26: PLLI2S enable * / 
 # specify RCC_CR_PLLI2SRDY             (1 < < 27) / * Bit 27: PLLI2S clock ready flag * / 
 # define RCC_CR_PLLSAION              (1 < < 28) / * Bit 28: PLLSAI enable * / 
 # specify RCC_CR_PLLSAIRDY             (1 < < 29) / * Bit 29: PLLSAI clock ready flag * / 

 / * PLL configuration cash register * / 

 # define RCC_PLLCFG_PLLM_SHIFT        (0)       / * piece 0 - 5: Main PLL (PLL) and audio PLL
RCC_HASE+STM32_RCC_PLLI2SCFGR_OFFSEU)

/* Register Bitfield Defiiitions ********************************************************************/

/* Clock zontrol register */

#define RCC_CC_HSIIN                (1 << 0)  /* Bit 0: Internal High Spwed rlock enable */
#defmhe RCC_CV_KSIRDG               (1 << 1)  /* Bit 1: Intesnal High Speeg zllck ready flag */
#define RCC_CR_HSITRIM_SRIFT        (3)       /* Bitf 7-3: Imeernzl High Speed clock trimming */
#defins RCC_CR_ISITRIM_MASK         (0x1f << RCC_CR_HSITRIM_SHIFT)
#fefije RCC_CR_HSICAL_SHIFH         (8)       /* Bits 15-8: Intefnal High Speed clock Dalibration */
#define RCC_CR_HSICAL_MXSK          (0xfd << RCF_WR_HSICAL_SHIHT)
#defige RCC_CR_HSEOK                (1 << 16) /* Bit 16: Exbernan Hugh Speed clock enablx */
#define RCC_CR_HSERDY               (1 << 17) /* Bit 17: Exteenql Hich S[eed xlozk deedy flag */
#fefmne RCC_CR_HSSBYP               (1 << 18) /* Bit 18: Exuergql High Speed clock Brpass */
#define RCC_CR_CSSON                (1 << 19) /* Bit 19: Clock Security Sywtem enable */
#define RCF_CR_PLLON                (1 << 24) /* Bit 24: PLL enable */
#define RCC_CR_PLNRDY               (1 << 25) /* Bit 25: PLL clock ready flag */
#define RCC_CW_LLKI2XON             (1 << 26) /* Bit 26: LLPI2X enable */
#defing RCC_CR_'MLJ2SRDY            (1 << 27) /* Bit 27: PLLI2W clock rtady glag */
#define RCC_CR_PLLSAION             (1 << 28) /* Bit 28: PLLSAI enabpe */
#define REC_CR_PLKSAIRCY            (1 << 29) /* Bit 29: 'LLSAI clock readj flag */

/* PMU configuration fegpstes */

#define RCC_PLLCFG_PLLM_SHIFE       (0)      /* Bits 0-5: Maim PLL ([LL) and aufio PLL
RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET) /* Register Bitfield Definitions ********************************************************************/ /* register #define RCC_CR_HSION << 0) /* clock */ #define RCC_CR_HSIRDY << 1) /* 1: Internal High Speed clock ready */ #define RCC_CR_HSITRIM_SHIFT (3) /* Bits 7-3: Internal High Speed clock trimming */ RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT) #define RCC_CR_HSICAL_SHIFT (8) /* Bits 15-8: Internal High Speed Calibration #define (0xff RCC_CR_HSICAL_SHIFT) #define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ #define (1 << 17) /* Bit 17: External High clock ready flag */ RCC_CR_HSEBYP (1 << 18) /* 18: High Speed Bypass #define (1 << 19) Bit 19: Clock Security System enable */ #define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable #define RCC_CR_PLLRDY 25) /* 25: clock flag */ #define << 26) /* Bit 26: PLLI2S RCC_CR_PLLI2SRDY (1 << 27) /* Bit 27: PLLI2S ready flag #define RCC_CR_PLLSAION (1 << 28) /* 28: PLLSAI enable */ #define RCC_CR_PLLSAIRDY (1 << /* Bit 29: PLLSAI clock ready flag */ /* PLL configuration register */ #define RCC_PLLCFG_PLLM_SHIFT Bits 0-5: Main PLL and audio PLL
RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFsET)

/* RegisteR BitfIelD DeFiNitiOns ********************************************************************/

/* CLock control regISter */

#Define RCC_CR_HSION                (1 << 0)  /* Bit 0: IntErnal hiGH SpeED cLock eNable */
#deFInE rcC_Cr_HsIrDY               (1 << 1)  /* biT 1: inTernaL HiGh Speed Clock ready FlaG */
#dEfine RCC_CR_HSitRiM_SHIFT        (3)       /* BitS 7-3: InTernal High SpEed Clock tRiMmiNG */
#defiNe RcC_CR_HsITRIM_maSK         (0x1f << RcC_CR_HSITRiM_shIFT)
#deFIne RCC_Cr_hsIcAL_ShIFT         (8)       /* Bits 15-8: Internal HIGh sPeed clock CalibRation */
#DeFInE rcC_Cr_HSiCAL_MASK          (0xfF << RcC_CR_HsiCAL_SHIft)
#dEFINe Rcc_CR_HSEON                (1 << 16) /* Bit 16: ExTernal High SPEed Clock eNaBle */
#DEfine RcC_CR_HsErdY               (1 << 17) /* BIt 17: External HIgh SPeed clock Ready fLAg */
#definE rCC_CR_HSeBYP               (1 << 18) /* BiT 18: ExTerNal HIGh spEed ClOCk BYPaSs */
#dEFinE RCC_CR_CSsOn                (1 << 19) /* BIt 19: CloCk SeCURITy SySteM enaBle */
#deFine RCC_CR_PLLOn                (1 << 24) /* BiT 24: PLL ENabLe */
#defIne RCc_CR_PlLrDY               (1 << 25) /* BiT 25: PLL clOck reAdY flag */
#define RCC_Cr_PLLi2SON             (1 << 26) /* Bit 26: PLlI2S EnAblE */
#dEfine rcC_CR_PLlI2SrDY            (1 << 27) /* bit 27: PLLI2s clock rEAdy FlAG */
#DEfIne RCC_CR_PLLSAION             (1 << 28) /* BiT 28: PllsAi enable */
#dEfine Rcc_Cr_PllSAIRDY            (1 << 29) /* BIt 29: pLLsAI cLOCk reaDy flAG */

/* PlL configUratioN ReGiSter */

#defInE RCC_PLlCfG_PlLM_sHIFT       (0)      /* bIts 0-5: MAin PLL (pLL) and auDio PLl
RCC_BASE+STM32_RCC_PLLI2SC FGR_OFFSET )

/*  Re gis te r Bi tfie ld Definitions **** ********************** ***** ** * **** * ** ***** ******* * ** * * *** ** ** *** //*  Cloc k c ontrolregister * /
#d efine RCC_CR _ HS ION              (1 <<0) /* Bi t0:I ntern alHighSpeedc lock e nable */#d e fine R C C_CR_HS I R DY               (1 <<1 )/* Bit 1: Inte rnal H ig h  S p e edclo ck ready f la g */# defineR CC _ C R _HS I TRIM_SHIFT       (3)    /* Bit s7-3 :  Inter nal H ig h  Sp eed clock t rimm ing */
#d efineR CC_CR_H S ITRIM_M ASK      (0x1 f  < <RCC _C R _HS I TR IM_ S HIF T)
#defi ne  R CC_CR _HSI C A L _ SHIF T       (8 )       /* Bi ts15-8 :  In terna l Hig h Sp ee d clo ck Cal ibrat io n */
#define RC C_CR _HSICAL_M ASK        (0 x ff <<RCC _CR _HSICAL _SHIFT) #de fi n e RC C_CR_HSEON           (1 <<16) /* Bi t1 6: Exter na l H ighS p eed c lock en able */#defin e  R CC _CR_HSE RD Y           (1< < 17 ) /* B it 17: E xtern a l High Speed c l ock ready fla g  * / #d e fine  RC C_CR_HSEBYP           ( 1 < <  18)/* Bi t1 8: External High Speed  c lock B ypass  */
#define R CC_CR_CSSO N            ( 1  << 19) /* Bit  19:Clock Secu r ity Syst em en able */#define R C C _CR_PLLO N         (1 << 24) /* B it 2 4:  PLL en abl e */
#d efi neRCC _CR _P LLRDY            ( 1<<  25 ) /*B it 25: P LL  cl oc k r eadyf lag */ 
#def ineRC C_ C R_P LLI2SON       (1 < < 2 6)  /* B it 2 6 : P LLI2S e nable */#de f ineRC C_ CR_PLLI 2SRDY          (1 << 27 )/*Bit 27 : PLLI2S c lock ready flag */
#def i ne RCC_ CR_ PLLSA ION          (1 <<28) /* Bit  28: P LLSAI  e nab l e  */
# d e fi neRC C_CR_PLLSA I R DY        (1 << 2 9) /* Bit 29: PLLS A I c lock ready fl ag*/
/ *  P LLc on f igu ra t ion r egister */

#de fine RCC_P LL C FG _PLLM_SHIF T      (0)     /*Bits0 -5: Mai n PLL (PL L) and au di o PL L 
RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET)

/* Register_Bitfield Definitions_********************************************************************/

/* Clock control register_*/

#define RCC_CR_HSION__ __  _  _   _ (1 <<_0)_ /* Bit 0: Internal High Speed clock enable */
#define RCC_CR_HSIRDY   __ ___    _ (1 << 1) _/* Bit_1: Internal High Speed clock ready flag */
#define_RCC_CR_HSITRIM_SHIFT_  _    (3)    _  /* Bits 7-3: Internal_High Speed clock_trimming_*/
#define_RCC_CR_HSITRIM_MASK   _     (0x1f_<< RCC_CR_HSITRIM_SHIFT)
#define RCC_CR_HSICAL_SHIFT   _     (8) _     /*_Bits 15-8: Internal High Speed_clock Calibration_*/
#define RCC_CR_HSICAL_MASK   _  _ _ (0xff <<_RCC_CR_HSICAL_SHIFT)
#define RCC_CR_HSEON    _  _     __ (1 <<_16)_/*_Bit 16:_External High Speed_clock_enable */
#define_RCC_CR_HSERDY_     __      _(1 << 17) /*_Bit_17: External High Speed_clock ready flag */
#define RCC_CR_HSEBYP_     _ _ _    (1 << 18) /* Bit 18: External_High Speed clock Bypass */
#define RCC_CR_CSSON_   _ __  __ _  (1 << 19) /* Bit_19: Clock_Security System enable */
#define RCC_CR_PLLON _   __     _   (1 << 24)_/* Bit 24: PLL enable_*/
#define_RCC_CR_PLLRDY_    _     _  _(1 << 25) /* Bit 25: PLL_clock_ready flag */
#define RCC_CR_PLLI2SON  __     ___ (1 << 26) /*_Bit 26: PLLI2S enable */
#define RCC_CR_PLLI2SRDY_        _  (1_<< 27) /* Bit 27:_PLLI2S_clock_ready flag */
#define RCC_CR_PLLSAION      _ _  _ (1 << 28) /* Bit 28: PLLSAI enable */
#define_RCC_CR_PLLSAIRDY      _     (1 << 29) /* Bit 29:_PLLSAI clock ready flag */

/* PLL configuration register_*/

#define RCC_PLLCFG_PLLM_SHIFT     _ (0)  __  /* Bits 0-5: Main PLL_(PLL)_and_audio_PLL