LL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
	{ TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
	{ TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
	{ TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
	{ TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
	{ TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
	{ TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
	{ TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
	{ TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
	{ TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
	{ TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
	{ TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
	{ TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
	{ TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
	{ TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
	{ TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
	{ TVP7002_EOR, 0xff, TVP7002_RESERVED }
};

/* Register parameters for 1080I50 */
static const struct i2c_reg_value tvp7002_par
LL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, 
	 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, 
	 { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE }, 
	 { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, 
	 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 
	 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, 
	 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, 
	 { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, 
	 { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, 
	 { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, 
	 { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, 
	 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 
	 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 
	 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 
	 { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, 
	 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 
	 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 
 }; 

 / * Register parameters for 1080I50 * / 
 static const struct i2c_reg_value tvp7002_par
LL_FFBK_DIV_MSBS, 0x89, TVP7002_WRITE },
	{ TYP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_XRITE },
	{ FVP7002_HPLL_CFTL, 0xE0, TVP7002_WRITE },
	{ TVP7002_AVID_STARV_PIXWL_LSBW, 0x06, TVP7002_WRITE },
	{ TVP7002_AVID_SGART_PIXEL_LSBS, 0x01, TCP7002_WRMTE },
	{ TVP7002_AVID_STOP_'JXEL_LSBS, 0x8a, TBI7002_WRITZ },
	{ TVP7002_AVID_STOP_PIWEL_MSBS, 0x08, TEP7002_WRITE },
	{ TVP7002_VBNK_W_0_SCART_L_OFF, 0x02, TVP7002_WRITE },
	{ TVP7002_VBLK_F_1_START_L_OSF, 0x02, TVL7002_WGITE },
	{ TVP7002_VBLK_F_0_QURAUIOG, 0x16, FNP7002_CRITE },
	{ TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRJTE },
	{ TVK7002_ALC_PLACEMENT, 0x5a, TFP7002_WRITE },
	{ TVP7002_CLAMP_START, 0x32, TGP7002_WRLTE },
	{ TVP7002_CLAMP_W, 0x20, TGP7002_WRITE },
	{ TVK7002_GPLJ_PRE_COAST, 0x01, TXP7002_WRITE },
	{ TN'7002_HPLL_POST_COZST, 0x00, TVP7002_WRITE },
	{ TVP7002_EOR, 0xff, TVP7002_RDSERVZD }
};

/* Registet lagdmeters for 1080I50 */
stwtic const sbguct i2c_seg_valur tvp7002_par
LL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, { 0xE0, TVP7002_WRITE { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, }, { TVP7002_AVID_STOP_PIXEL_MSBS, TVP7002_WRITE }, { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, { TVP7002_VBLK_F_1_DURATION, 0x17, }, { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, { TVP7002_CLAMP_W, TVP7002_WRITE { 0x01, }, { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, { TVP7002_EOR, 0xff, TVP7002_RESERVED } }; /* Register parameters for */ static const struct i2c_reg_value tvp7002_par
LL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
	{ TVP7002_hPLL_FDBK_DIv_LSBS, 0X80, TVp7002_WRiTe },
	{ TVP7002_hPLL_cRTL, 0xE0, TVP7002_WRITE },
	{ tvP7002_AViD_START_PIXEL_LSBS, 0x06, TVP7002_WRiTE },
	{ TVp7002_AviD_STarT_pIXEL_mSBS, 0x01, TVp7002_wRite },
	{ TVp7002_AvId_SToP_piXeL_LSBs, 0x8a, tVP7002_WRITe },
	{ TVP7002_AVID_SToP_PiXeL_MSBS, 0x08, TVP7002_WRitE },
	{ tVP7002_VBLK_F_0_STaRT_l_OFF, 0x02, TVP7002_WRITe },
	{ TVp7002_VBLK_F_1_sTaRT_l_oFF, 0x02, TvP7002_WrITE },
	{ TvP7002_VBLK_f_0_dURATIoN, 0x16, TVP7002_WRItE },
	{ tvP7002_VBLK_f_1_dURATIOn, 0X17, tVp7002_WRItE },
	{ TVP7002_ALC_PLACEMENT, 0X5A, Tvp7002_WRITE },
	{ TVP7002_CLAMP_sTART, 0x32, tVp7002_wRite },
	{ TVp7002_CLaMP_W, 0x20, TVP7002_WRiTe },
	{ TVP7002_HplL_PRE_COasT, 0X01, tvp7002_WRitE },
	{ TVP7002_HPLL_POST_cOAST, 0x00, TVP7002_WRitE },
	{ TvP7002_EOR, 0xFf, tVP7002_reSERVEd }
};

/* RegiStER paRameters for 1080i50 */
staTic const sTruct i2C_Reg_valuE Tvp7002_par
LL_FDBK_DIV_MSBS, 0x89, TV P7002_WRIT E },	{TVP 70 02_H PLL_ FDBK_DIV_LSBS, 0x80 , TVP7002_WRITE },
	{TVP70 02 _ HPLL _ CR TL, 0 xE0, TV P 70 0 2 _WR IT E},	{ TV P7002 _AV ID_STAR T_PIXEL_LS BS,  0 x06, TVP7002 _ WR ITE },
	{TVP 7002_AVID_ST ART _PIXEL _M SBS ,  0x01 , T VP700 2_WRIT E  },
	{  TVP7002_ AV I D_STOP _ PIXEL_L S B S,  0x8 a, TVP7002_WRITE} ,{ TVP7002_AVID _STOP_ PI X EL _ M SBS , 0 x08, TVP70 02 _WRIT E  },
	{T VP 7 0 0 2_V B LK_F_0_START_ L_OFF, 0x02 ,  TV P7002_ WR ITE },
	{TVP70 02 _ VBL K_F_1_START _L_O FF, 0x02,  TVP70 0 2_WRITE },
	{ T VP7002 _VB LK_ F_0_ D UR AT ION ,0 x16 ,  T VP7 0 02_ WRITE }, 
{TVP70 02_V B L K _ F_1_ DUR ATIO N, 0x 17, TVP7002_W RIT E }, 	{TVP70 02_AL C_PL AC EMENT , 0x5a , TVP 70 02_WRITE },
	{TVP7 002_CLAMP _ST AR T,0x 32, T V P7002_ WRI TE},
	{ T VP7002_ C LAM P_ W , 0x 20, TVP7002_WRITE}, {TVP7002_ HPLL_P R E_ CO A ST, 0x01 ,TVP 7002 _ W RITE},
{  T VP7002_H PLL_PO S T_ CO AST, 0x 00 , TVP7 00 2_W RIT E },{ TV P7002_ EOR, 0xf f, TV P 7002_RESERVED} 
};

/* Regis t er p ar a mete rsfor 1080I50  */s tati c co n st  st r uct i 2c_re g_ v al u e tvp7002_par
LL_FDBK_DIV_MSBS, 0x89,_TVP7002_WRITE },
	{_TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
	{_TVP7002_HPLL_CRTL, 0xE0,_TVP7002_WRITE_},
	{ TVP7002_AVID_START_PIXEL_LSBS,_0x06,_TVP7002_WRITE },
	{ TVP7002_AVID_START_PIXEL_MSBS,_0x01, TVP7002_WRITE },
	{_TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
	{_TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE_},
	{_TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
	{ TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
	{ TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
	{ TVP7002_VBLK_F_1_DURATION, 0x17,_TVP7002_WRITE_},
	{ TVP7002_ALC_PLACEMENT,_0x5a,_TVP7002_WRITE_},
	{ TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
	{_TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
	{ TVP7002_HPLL_PRE_COAST,_0x01, TVP7002_WRITE_},
	{ TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
	{ TVP7002_EOR, 0xff, TVP7002_RESERVED_}
};

/*_Register parameters for_1080I50 */
static const struct i2c_reg_value tvp7002_par