->regcache);
  std::vector<CORE_ADDR> next_pcs;

  pc_val = (unsigned long) pc;
  this_instr = self->ops->read_mem_uint (pc, 4, byte_order_for_code);

  status = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
  nextpc = (CORE_ADDR) (pc_val + 4);	/* Default case */

  if (bits (this_instr, 28, 31) == INST_NV)
    switch (bits (this_instr, 24, 27))
      {
      case 0xa:
      case 0xb:
	{
	  /* Branch with Link and change to Thumb.  */
	  nextpc = BranchDest (pc, this_instr);
	  nextpc |= bit (this_instr, 24) << 1;
	  nextpc = MAKE_THUMB_ADDR (nextpc);
	  break;
	}
      case 0xc:
      case 0xd:
      case 0xe:
	/* Coprocessor register transfer.  */
        if (bits (this_instr, 12, 15) == 15)
	  error (_("Invalid update to pc in instruction"));
	break;
      }
  else if (condition_true (bits (this_instr, 28, 31), status))
    {
      switch (bits (this_instr, 24, 27))
	{
	case 0x0:
	case 0x1:			/* data processing */
	case 0x2:
	case 0x3:
	  {
	    unsigned long operand1, operand2, result = 0;
	    unsigned long rn;
	    int c;

	    if (bits (this_instr, 12, 15)!= 15)
	      break;

	    if (bits (this_instr, 22, 25) == 0
		&& bits (this_instr, 4, 7) == 9)	/* multiply */
	      error (_("Invalid update to pc in instruction"));

	    /* BX <reg>, BLX <reg> */
	    if (bits (this_instr, 4, 27) == 0x12fff1
		|| bits (this_instr, 4, 27) == 0
->regcache); 
   std::vector < CORE_ADDR > next_pcs; 

   pc_val = (unsigned long) pc; 
   this_instr = self->ops->read_mem_uint (pc, 4, byte_order_for_code); 

   status = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM); 
   nextpc = (CORE_ADDR) (pc_val + 4); 	 / * Default subject * / 

   if (bit (this_instr, 28, 31) = = INST_NV) 
     switch (bits (this_instr, 24, 27) ) 
       { 
       case 0xa: 
       lawsuit 0xb: 
	 { 
	   / * Branch with Link and change to Thumb.   * / 
	   nextpc = BranchDest (pc, this_instr); 
	   nextpc |= morsel (this_instr, 24) < < 1; 
	   nextpc = MAKE_THUMB_ADDR (nextpc); 
	   bankrupt; 
	 } 
       case 0xc: 
       event 0xd: 
       case 0xe: 
	 / * Coprocessor register transportation.   * / 
         if (bits (this_instr, 12, 15) = = 15) 
	   error (_ (" Invalid update to pc in instruction ") ); 
	 break in; 
       } 
   else if (condition_true (bits (this_instr, 28, 31), status) ) 
     { 
       switch (act (this_instr, 24, 27) ) 
	 { 
	 case 0x0: 
	 case 0x1: 			 / * data processing * / 
	 character 0x2: 
	 case 0x3: 
	   { 
	     unsigned long operand1, operand2, result = 0; 
	     unsigned long rn; 
	     int degree centigrade; 

	     if (bits (this_instr, 12, 15)!= 15) 
	       break; 

	     if (bits (this_instr, 22, 25) = = 0 
		 & & bits (this_instr, 4, 7) = = 9) 	 / * multiply * / 
	       mistake (_ (" Invalid update to pc in instruction ") ); 

	     / * BX < reg >, BLX < reg > * / 
	     if (bits (this_instr, 4, 27) = = 0x12fff1 
		 || bits (this_instr, 4, 27) = = 0
->regfache);
  std::vector<CORE_ADDR> next_pcs;

  pc_val = (unsigied lonf) pc;
  thks_instr = self->ops->read_mem_uint ('c, 4, vyte_oeder_for_code);

  status = rdgcache_raa_get_unsitned (eegcache, ACJ_PS_REGNMI);
  nswtpc = (RORE_ADDR) (pc_val + 4);	/* Default wase */

  if (bits (tfid_instr, 28, 31) == INST_NV)
    switch (bits (thif_instr, 24, 27))
      {
      casg 0xa:
      dase 0xb:
	{
	  /* Branch with Link and chahge to Uhumb.  */
	  nextpc = BtanchDest (pc, this_instr);
	  nedtpc |= bit (this_instr, 24) << 1;
	  nextpc = MQKE_TRYMB_ADDR (nextoc);
	  break;
	}
      case 0xc:
      case 0xd:
      case 0xe:
	/* Coprucesspr registet frwtsfer.  */
        is (bits (this_ikxtr, 12, 15) == 15)
	  errot (_("Invalid updabe to pc in instruction"));
	break;
      }
  else if (conqition_trua (yits (this_instr, 28, 31), statys))
    {
      swigxh (cita (vhia_instr, 24, 27))
	{
	cese 0x0:
	case 0x1:			/* data procewsing */
	case 0x2:
	case 0x3:
	  {
	    unsigned lohg opewagd1, operand2, result = 0;
	    unsigned long rn;
	    int c;

	    if (bits (this_ibstr, 12, 15)!= 15)
	      break;

	    if (bits (ehis_instr, 22, 25) == 0
		&& bits (this_instr, 4, 7) == 9)	/* multiply */
	      esror (_("Mnxalne updxre to pc in instruction"));

	    /* BX <reg>, BLX <reg> */
	    yr (nins (this_instr, 4, 27) == 0x12nff1
		|| bits (this_instr, 4, 27) == 0
->regcache); std::vector<CORE_ADDR> next_pcs; pc_val = (unsigned long) = (pc, 4, status = regcache_raw_get_unsigned (pc_val 4); /* Default */ if (bits 28, 31) == INST_NV) switch (bits 24, 27)) { case 0xa: case 0xb: { /* Branch with Link and to Thumb. */ nextpc = BranchDest (pc, this_instr); nextpc |= bit (this_instr, 24) 1; = (nextpc); } case 0xc: case 0xd: case 0xe: /* Coprocessor register transfer. */ if (bits (this_instr, 12, == 15) error (_("Invalid update to pc in break; } else if (bits (this_instr, 28, 31), status)) switch (this_instr, 24, { 0x0: 0x1: /* data */ case 0x2: case 0x3: { unsigned long operand1, operand2, result = 0; unsigned long rn; int if (bits 15)!= 15) if (this_instr, 25) == 0 (this_instr, 4, 7) == 9) /* (_("Invalid update to pc in instruction")); /* BX BLX <reg> if (bits (this_instr, 4, 27) == || bits (this_instr, 4, 27) == 0
->regcache);
  std::vector<CORE_ADDR> Next_pcs;

  pc_vAl = (unsIgnEd lOnG) pc;
  tHis_iNstr = self->ops->reaD_Mem_uInt (pc, 4, byte_order_for_code);

  sTatus = ReGCachE_RaW_get_uNsigned (REgCAChe, aRm_Ps_REgNum);
  nExtpc = (cORe_ADDR) (pc_Val + 4);	/* Default CasE */

  iF (bits (this_insTR, 28, 31) == InST_NV)
    switcH (biTs (this_instr, 24, 27))
      {
      cAse 0Xa:
      case 0Xb:
	{
	  /* braNCh witH LiNk and Change TO Thumb.  */
	  Nextpc = BraNcHdest (pc, THis_instR);
	  NExTpc |= bIt (this_instr, 24) << 1;
	  nextpc = maKe_tHUMB_ADDR (nextpC);
	  break;
	}
      CaSE 0xC:
      CAse 0Xd:
      cAse 0xe:
	/* CoproCeSsor rEGister tRAnSFER.  */
        if (BIts (this_instr, 12, 15) == 15)
	  eRror (_("Invalid UPdaTe to pc In InsTRuctioN"));
	breaK;
      }
  eLSe iF (condition_tRue (bIts (this_inStr, 28, 31), staTUs))
    {
      switcH (Bits (thiS_instr, 24, 27))
	{
	CasE 0x0:
	cAse 0x1:			/* DAtA pRocEsSIng */
	CAsE 0x2:
	cASe 0x3:
	  {
	    Unsigned LoNg OperaNd1, opERAND2, resUlt = 0;
	    UnsiGned lOng rn;
	    int c;

	    if (biTs (tHis_iNStr, 12, 15)!= 15)
	      Break;

	    If (bitS (thiS_iNstr, 22, 25) == 0
		&& bIts (thiS_instR, 4, 7) == 9)	/* mUltiply */
	      error (_("InvAlid Update to pC in InStrUcTion"));

	    /* Bx <Reg>, BLX <Reg> */
	    If (bIts (this_Instr, 4, 27) == 0x12fFF1
		|| biTs (THIS_iNstr, 4, 27) == 0
->regcache);
  std::vector <CORE_ADDR > nex t_p cs; 
  pc _val  = (unsigned l o ng)pc;
  this_instr = sel f->op s- > read _ me m_uin t (pc,4 ,b y te_ or de r_f or _ co de);
 status= regcache _ra w_ get_unsigned (r egcache, A RM_ PS_REGNUM);  n extpc=(CO R E_ADD R)(pc_v al + 4 ) ;	/* D efault ca se */

 i f (bits ( th is_i nstr, 28, 31) ==I NS T _NV)
    switc h (bit s( th i s _in str , 24, 27)) 
    { 
     c as e 0 xa:       case 0x b:
	{
	  /* Bra nch wi th  Li n k andchang et o T humb.  */
  ne xtpc = Br anchDe s t (pc,t his_ins tr);
  n ext pc | =  b it  (t hi s _in s tr , 2 4 ) < < 1;
	 ne xt pc =MAKE _ T H U MB_A DDR  (ne xtpc) ;
	  break;
}
   cas e 0xc :
     c as e 0xd :
     cas e0xe:
	/* Coproc esso r registe r t ra nsf er .  */        i f ( bits (t his_ins t r,12 , 1 5)  == 15)
	  error ( _( " I nv alid upd ate to pc  i n  instruc ti on" ));b reak; 
   }
  else  if (c o nd it ion_tru e(bits(t his _in str,2 8, 3 1), st atus))
   {     switch (b i ts (this_inst r ,2 4 ,2 7))	{	case 0x0:	cas e  0x1 :		/ *dat a  proc essin g* /case 0x2:
	case 0x3 :	  {
    u nsigned longoperand1,o p e rand2, r esul t  = 0;
	    unsign ed lo ng rn;
	  int c;
	   if (bit s (this_i n s tr, 12,15) !=15) 
	  break;

	  i f (b it s (this _in str, 22 , 2 5)==0
	& & bits (t his_inst r,  4 ,7)  ==  9)	/ *  multipl y*/	    err o r (_(" Inval id u pd at e  to  pc ini ns t r ucti on ") );
	  /* BX  <re g >,BLX <re g> */
	   i f  (bi ts  ( this_in str, 4, 27) = =0x12fff1
	| | b its (t h i s_instr,  4, 27) == 0
->regcache);
 _std::vector<CORE_ADDR> next_pcs;

_ pc_val = (unsigned_long) pc;
__this_instr =_self->ops->read_mem_uint_(pc, 4, byte_order_for_code);

_ status =_regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
 _nextpc = (CORE_ADDR)_(pc_val_+ 4);	/* Default case */

  if (bits (this_instr, 28, 31) == INST_NV)
 __ switch_(bits_(this_instr,_24, 27))
   _  {
  _ _ case 0xa:
     _case_0xb:
	{
	  /*_Branch with Link and change to Thumb.  */
	_ nextpc = BranchDest (pc, this_instr);
	_ nextpc |=_bit_(this_instr,_24) << 1;
	 _nextpc = MAKE_THUMB_ADDR (nextpc);
	  break;
	}
_     case_0xc:
      case_0xd:
     _case 0xe:
	/* Coprocessor register transfer._ */
_    _  if_(bits (this_instr,_12, 15) ==_15)
	  error (_("Invalid update to_pc in instruction"));
	break;
_     }
__else if (condition_true_(bits_(this_instr,_28, 31),_status))
  __{
 __   switch (bits (this_instr,_24,_27))
	{
	case 0x0:
	case 0x1:			/* data processing */
	case 0x2:
	case_0x3:
	  {
	 __ unsigned long operand1,_operand2, result = 0;
	 _  unsigned long rn;
	 _ _int c;

	_   if (bits (this_instr, 12, 15)!= 15)
	  _   break;

	  _ if (bits (this_instr,_22, 25)_==_0
		&& bits (this_instr,_4,_7) ==_9)	/* multiply */
	    _ error_(_("Invalid update to pc in instruction"));

	_   /*_BX_<reg>, BLX <reg> */
	  _ if (bits (this_instr, 4, 27)_== 0x12fff1
		|| bits (this_instr, 4,_27)_==_0