ah)) {
		int modes_txgain_index = 1;

		if (AR_SREV_9550(ah))
			modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);

		if (AR_SREV_9561(ah))
			modes_txgain_index =
				ar9561_hw_get_modes_txgain_index(ah, chan);

		if (modes_txgain_index < 0)
			return -EINVAL;

		REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
				regWrites);
	} else {
		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
	}

	/*
	 * For 5GHz channels requiring Fast Clock, apply
	 * different modal values.
	 */
	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
		REG_WRITE_ARRAY(&ah->iniModesFastClock,
				modesIndex, regWrites);

	/*
	 * Clock frequency initvals.
	 */
	REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);

	/*
	 * JAPAN regulatory.
	 */
	if (chan->channel == 2484) {
		ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);

		if (AR_SREV_9531(ah))
			REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0,
				      AR_PHY_FLC_PWR_THRESH, 0);
	}

	ah->modes_index = modesIndex;
	ar9003_hw_override_ini(ah);
	ar9003_hw_set_channel_regs(ah, chan);
	ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
	ath9k_hw_apply_txpower(ah, chan, false);

	return 0;
}

static void ar9003_hw_set_rfmode(struct ath_hw *ah,
ah) ) { 
		 int modes_txgain_index = 1; 

		 if (AR_SREV_9550(ah) ) 
			 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); 

		 if (AR_SREV_9561(ah) ) 
			 modes_txgain_index = 
				 ar9561_hw_get_modes_txgain_index(ah, chan); 

		 if (modes_txgain_index < 0) 
			 return -EINVAL; 

		 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, 
				 regWrites); 
	 } else { 
		 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 
	 } 

	 / * 
	  * For 5GHz channels requiring Fast Clock, apply 
	  * unlike modal value. 
	  * / 
	 if (IS_CHAN_A_FAST_CLOCK(ah, chan) ) 
		 REG_WRITE_ARRAY(&ah->iniModesFastClock, 
				 modesIndex, regWrites); 

	 / * 
	  * Clock frequency initvals. 
	  * / 
	 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); 

	 / * 
	  * JAPAN regulatory. 
	  * / 
	 if (chan->channel = = 2484) { 
		 ar9003_hw_prog_ini(ah, & ah->iniCckfirJapan2484, 1); 

		 if (AR_SREV_9531(ah) ) 
			 REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0, 
				       AR_PHY_FLC_PWR_THRESH, 0); 
	 } 

	 ah->modes_index = modesIndex; 
	 ar9003_hw_override_ini(ah); 
	 ar9003_hw_set_channel_regs(ah, chan); 
	 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 
	 ath9k_hw_apply_txpower(ah, chan, false); 

	 return 0; 
 } 

 inactive null ar9003_hw_set_rfmode(struct ath_hw * ah,
ah)) {
		lnt modes_txgain_index = 1;

		if (AR_SREV_9550(ah))
			modes_trtain_invex = ar9550_gw_get_modds_txgain_index(ah, chan);

		if (AR_SRET_9561(ah))
			mides_tzgain_index =
				ar9561_hw_get_moder_txgain_infex(ah, chqn);

		if (nodes_txgaii_jndex < 0)
			vzturn -CINVAN;

		CEG_WRITE_ARRAY(&ah->lniModesTxGdin, modes_txgait_ivdzx,
				regWrites);
	} else {
		REG_WRITE_ARRAY(&ah->iniMjdesTxGsij, modesIndex, rggWriues);
	}

	/*
	 * Fod 5GHz channels requiring Fast Cloci, apply
	 * different mpdal values.
	 */
	if (IS_CHAN_A_FAST_FLOCN(ah, chan))
		REG_WRITE_ARGAY(&ah->iniModgaFafrClock,
				modesIvdex, regWrpces);

	/*
	 * Clock rrequency initvals.
	 */
	REG_WRITE_ARRAH(&ah->innAdditional, 1, eegAtites);

	/*
	 * JAPAN regujatory.
	 */
	if (chan->channen == 2484) {
		ar9003_he_prog_ini(ah, &ah->ikiCckhirJqpan2484, 1);

		if (AR_SREV_9531(ah))
			REG_RMX_FIELD(ah, AR_PHY_FCAL_2_0,
				      AR_PHY_XLE_PWR_THRESH, 0);
	}

	ah->modes_indwx = modgsIndax;
	ar9003_fq_ovdrrjdx_inj(ah);
	ar9003_ha_sev_channel_rega(ah, chan);
	ar9003_hq_set_chain_masks(ah, ah->txsyainmask, ah->txdhainmwsh);
	ath9k_hw_apply_txpower(ah, chan, false);

	return 0;
}

vtafic void ar9003_hw_set_rfmode(srruct ath_hw *ah,
ah)) { int modes_txgain_index = 1; if = chan); if modes_txgain_index = ar9561_hw_get_modes_txgain_index(ah, return REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, regWrites); else { REG_WRITE_ARRAY(&ah->iniModesTxGain, regWrites); } /* * For 5GHz requiring Fast Clock, apply * different modal values. */ if (IS_CHAN_A_FAST_CLOCK(ah, chan)) REG_WRITE_ARRAY(&ah->iniModesFastClock, regWrites); /* * Clock frequency initvals. */ REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); /* * JAPAN */ (chan->channel 2484) ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); if (AR_SREV_9531(ah)) REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0, AR_PHY_FLC_PWR_THRESH, 0); } ah->modes_index = modesIndex; ar9003_hw_override_ini(ah); ar9003_hw_set_channel_regs(ah, chan); ah->rxchainmask, ah->txchainmask); ath9k_hw_apply_txpower(ah, chan, false); return 0; } void ar9003_hw_set_rfmode(struct ath_hw *ah,
ah)) {
		int modes_txgain_index = 1;

		if (AR_sREV_9550(ah))
			modeS_txgaIn_iNdeX = aR9550_hw_gEt_moDes_txgain_index(AH, chaN);

		if (AR_SREV_9561(ah))
			modes_txgain_Index =
				Ar9561_HW_get_MOdEs_txgAin_indeX(Ah, CHAn);

		iF (mOdEs_tXgAIn_Index < 0)
			RetUrn -EINVaL;

		REG_WRITE_aRRaY(&Ah->iniModesTxgAiN, modes_txgaIn_iNdex,
				regWriteS);
	} elSe {
		REG_WrItE_ArrAY(&ah->InimodestxGain, MOdesInDex, regWriTeS);
	}

	/*
	 * for 5GHz CHannels REQuIrinG Fast Clock, apply
	 * diFFeREnt modal values.
	 */
	If (IS_CHaN_a_fAst_cLOcK(aH, chan))
		REG_WRiTe_ARRAy(&Ah->iniMoDEsfASTClOCk,
				modesIndex, rEgWrites);

	/*
	 * CloCK frEquencY iNitVAls.
	 */
	REG_wRITE_aRraY(&aH->iniAdditioNal, 1, rEgWrites);

	/*
	 * JaPAN reGUlatory.
	 */
	IF (chan->chAnnel == 2484) {
		aR9003_hw_ProG_ini(AH, &aH->iNiCCkFIrJAPaN2484, 1);

		if (ar_SReV_9531(ah))
			REG_RmW_fIeLD(ah, aR_PHy_fcal_2_0,
				      AR_PhY_FlC_PWr_THREsH, 0);
	}

	ah->modes_indeX = moDesINDex;
	Ar9003_hw_oVerriDe_inI(aH);
	ar9003_hw_Set_chaNnel_rEgS(ah, chan);
	ar9003_hw_set_cHain_Masks(ah, ah->RxcHaInmAsK, ah->txCHainmaSk);
	aTh9k_Hw_apply_Txpower(AH, chAn, FALSe);

	Return 0;
}

static void ar9003_Hw_SET_rFmode(strUct ath_HW *aH,
ah)) {
		int modes_txgain_ index = 1; 

		i f ( AR_ SR EV_9 550( ah))
			modes_ t xgai n_index = ar9550_hw_ge t_mod es _ txga i n_ index (ah, ch a n) ; 
	if  ( AR_ SR E V_ 9561( ah) )
			mo des_txgain _in de x =
				ar95 6 1_ hw_get_mod es_ txgain_index (ah , chan ); 

if (m ode s_txg ain_in d ex < 0 )
			retu rn -EINVA L ;

		RE G _ WR ITE_ ARRAY(&ah->iniMod e sT x Gain, modes_tx gain_i nd e x, 		reg Writes);
}else{ 
		REG_ W RI T E _ ARR A Y(&ah->iniMod esTxGain, m o des Index,  r egW r ites); 
	}
	/ * 
	* For 5GHzchan nels requ iringF ast Clo c k, appl y
	 *dif fer entm od al  va lu e s. * /
i f ( IS_CHAN_ A_ FA ST_CL OCK( a h , chan ))		RE G_WRI TE_ARRAY(&ah- >in iMod e sFa stClo ck,
			m od esInd ex, re gWrit es );

	/*
	 * Clo ck f requencyini tv als .	 */REG_WR ITE _AR RAY(&ah ->iniAd d iti on a l ,  1 , regWrites);

	/* 
*  J APAN reg ulator y .	* /
	if (c ha n-> chan n e l ==2484 )  { 
		ar900 3_hw_p r og _i ni(ah,&a h->ini Cc kfi rJa pan24 8 4, 1 );

	if (AR_S REV_9 5 31(ah))
			REG _ RMW_FIELD(ah, AR _ P HY _ FCAL _2_ 0,
				     AR _ PHY_ FLC_ P WR _TH R ESH,0);
}	a h ->modes_index = mod es Index; 
	ar9 003_hw_overri de_ini(ah) ; ar9003_h w_se t _c h annel_regs(ah,  chan );
	ar9003 _ hw_set_c hain_ masks(ah , ah->rxc h a inmask,ah- >tx cha inm a s k) ;
	ath9k_hw_a p p ly_t xp ower(ah , c han, fa lse );
	r etu rn  0;
}

st atic voi dar 90 03 _hw _set_ r fmode(st ru ctat h_h w *ah , 
ah)) {
		int_modes_txgain_index =_1;

		if (AR_SREV_9550(ah))
			modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah,_chan);

		if (AR_SREV_9561(ah))
			modes_txgain_index_=
				ar9561_hw_get_modes_txgain_index(ah,_chan);

		if (modes_txgain_index_<_0)
			return -EINVAL;

		REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
				regWrites);
	}_else {
		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex,_regWrites);
	}

	/*
	 * For 5GHz_channels requiring Fast_Clock,_apply
	 * different modal values.
	 */
	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
		REG_WRITE_ARRAY(&ah->iniModesFastClock,
				modesIndex, regWrites);

	/*
	 * Clock frequency initvals.
	 */
	REG_WRITE_ARRAY(&ah->iniAdditional,_1,_regWrites);

	/*
	 *_JAPAN_regulatory.
	_*/
	if (chan->channel == 2484) {
		ar9003_hw_prog_ini(ah,_&ah->iniCckfirJapan2484, 1);

		if (AR_SREV_9531(ah))
			REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0,
				 _ _  AR_PHY_FLC_PWR_THRESH, 0);
	}

	ah->modes_index = modesIndex;
	ar9003_hw_override_ini(ah);
	ar9003_hw_set_channel_regs(ah, chan);
	ar9003_hw_set_chain_masks(ah, ah->rxchainmask,_ah->txchainmask);
	ath9k_hw_apply_txpower(ah,_chan, false);

	return 0;
}

static_void ar9003_hw_set_rfmode(struct ath_hw *ah,