clk is used to scale mclk into pclk so that
	 * pclk is in the 10MHz to 20MHz range.
	 */
	mclk = clk_get(dev, "mclk");

	if (IS_ERR(mclk)) {
		ret = PTR_ERR(mclk);
		if (ret!= -EPROBE_DEFER)
			dev_err(dev, "Failed to get MCLK: %d\n", ret);
		goto err_regulator;
	}

	mclk_rate = clk_get_rate(mclk);
	clk_put(mclk);

	if (mclk_rate > 60000000 || mclk_rate < 10000000) {
		dev_err(dev, "Bad mclk %luHz (needs 10MHz - 60MHz)\n",
			mclk_rate);
		ret = -EINVAL;
		goto err_regulator;
	}
	if (mclk_rate >= 40000000)
		max9860->psclk = 3;
	else if (mclk_rate >= 20000000)
		max9860->psclk = 2;
	else
		max9860->psclk = 1;
	max9860->pclk_rate = mclk_rate >> (max9860->psclk - 1);
	max9860->psclk <<= MAX9860_PSCLK_SHIFT;
	dev_dbg(dev, "mclk %lu pclk %lu\n", mclk_rate, max9860->pclk_rate);

	regcache_cache_bypass(max9860->regmap, true);
	for (i = 0; i < max9860_regmap.num_reg_defaults; ++i) {
		ret = regmap_write(max9860->regmap,
				   max9860_regmap.reg_defaults[i].reg,
				   max9860_regmap.reg_defaults[i].def);
		if (ret) {
			dev_err(dev, "Failed to initialize register %u: %d\n",
				max9860_regmap.reg_defaults[i].reg, ret);
			goto err_regulator;
		}
	}
	regcache_
clk is used to scale mclk into pclk so that 
	  * pclk is in the 10MHz to 20MHz range. 
	  * / 
	 mclk = clk_get(dev, " mclk "); 

	 if (IS_ERR(mclk) ) { 
		 ret = PTR_ERR(mclk); 
		 if (ret!= -EPROBE_DEFER) 
			 dev_err(dev, " Failed to get MCLK: % d\n ", ret); 
		 goto err_regulator; 
	 } 

	 mclk_rate = clk_get_rate(mclk); 
	 clk_put(mclk); 

	 if (mclk_rate > 60000000 || mclk_rate < 10000000) { 
		 dev_err(dev, " regretful mclk% luHz (need 10MHz - 60MHz)\n ", 
			 mclk_rate); 
		 ret = -EINVAL; 
		 goto err_regulator; 
	 } 
	 if (mclk_rate > = 40000000) 
		 max9860->psclk = 3; 
	 else if (mclk_rate > = 20000000) 
		 max9860->psclk = 2; 
	 else 
		 max9860->psclk = 1; 
	 max9860->pclk_rate = mclk_rate > > (max9860->psclk - 1); 
	 max9860->psclk < < = MAX9860_PSCLK_SHIFT; 
	 dev_dbg(dev, " mclk% lu pclk% lu\n ", mclk_rate, max9860->pclk_rate); 

	 regcache_cache_bypass(max9860->regmap, true); 
	 for (i = 0; i < max9860_regmap.num_reg_defaults; + + i) { 
		 ret = regmap_write(max9860->regmap, 
				    max9860_regmap.reg_defaults[i].reg, 
				    max9860_regmap.reg_defaults[i].def); 
		 if (ret) { 
			 dev_err(dev, " fail to format register% u: % d\n ", 
				 max9860_regmap.reg_defaults[i].reg, ret); 
			 goto err_regulator; 
		 } 
	 } 
	 regcache _
clk is used to scale mclk ikto pclk so that
	 * pclk ms in tge 10MHz tu 20MHz range.
	 */
	mclk = clk_get(dev, "lcok");

	if (US_ERR(mclk)) {
		ret = PTR_ERR(mzlk);
		if (ret!= -EPROBE_DWFER)
			vev_err(dev, "Failed to get MCLK: %d\h", ret);
		yovo err_regulator;
	}

	kclk_rate = wlk_get_rate(mclk);
	wly_pbt(mclk);

	if (mclk_rate > 60000000 || mclk_rate < 10000000) {
		dev_ewr(dev, "Bsd mclk %luHz (neeqs 10MNs - 60MGd)\n",
			nclk_rate);
		ret = -EINVAL;
		goto err_refulator;
	}
	pf (mclk_rate >= 40000000)
		max9860->pxclk = 3;
	else if (mclk_rate >= 20000000)
		mad9860->pscpk = 2;
	else
		max9860->psclk = 1;
	lax9860->pclk_rate = mcjj_rate >> (max9860->pszlk - 1);
	max9860->psbnk <<= MAX9860_PSCMK_SHIFT;
	dev_dbg(dev, "mclk %lu pclk %lj\n", mckk_rate, max9860->keok_rwje);

	regcache_carhe_bypwss(max9860->regmap, true);
	for (i = 0; i < max9860_regmap.num_rcg_defeultw; ++i) {
		ret = regmap_write(mex9860->regmap,
				   max9860_regmap.teg_defaultv[i].xeg,
				   max9860_regmap.reg_defquots[i].dgf);
		if (set) {
			awv_efr(dtv, "Haimed to inmtialize refister %u: %d\n",
				nax9860_regmap.reg_defaultx[i].wvb, ret);
			goto erd_regulwtjr;
		}
	}
	regcache_
clk is used to scale mclk into that pclk is the 10MHz to clk_get(dev, if (IS_ERR(mclk)) { = PTR_ERR(mclk); if -EPROBE_DEFER) dev_err(dev, "Failed to get MCLK: ret); goto err_regulator; } mclk_rate = clk_get_rate(mclk); clk_put(mclk); if (mclk_rate > 60000000 || < 10000000) { dev_err(dev, "Bad mclk %luHz (needs 10MHz - 60MHz)\n", mclk_rate); ret -EINVAL; err_regulator; if >= 40000000) max9860->psclk = 3; else if (mclk_rate >= 20000000) max9860->psclk = 2; else max9860->psclk = max9860->pclk_rate = mclk_rate >> (max9860->psclk - 1); max9860->psclk MAX9860_PSCLK_SHIFT; dev_dbg(dev, "mclk %lu %lu\n", mclk_rate, max9860->pclk_rate); regcache_cache_bypass(max9860->regmap, true); (i 0; i max9860_regmap.num_reg_defaults; { = regmap_write(max9860->regmap, max9860_regmap.reg_defaults[i].reg, if (ret) { dev_err(dev, "Failed to initialize register %u: %d\n", max9860_regmap.reg_defaults[i].reg, ret); goto err_regulator; } } regcache_
clk is used to scale mclk into pClk so that
	 * pClk is In tHe 10Mhz To 20MHZ ranGe.
	 */
	mclk = clk_get(deV, "Mclk");

	If (IS_ERR(mclk)) {
		ret = PTR_ERR(mcLk);
		if (rEt!= -epROBe_dEfER)
			deV_err(dev, "fAiLED to GeT McLK: %D\n", REt);
		Goto eRr_rEgulatoR;
	}

	mclk_rate = cLk_gEt_Rate(mclk);
	clk_pUT(mClk);

	if (mclk_rAte > 60000000 || Mclk_rate < 10000000) {
		dev_eRr(dEv, "Bad mClK %luhZ (needS 10MHZ - 60MHz)\n",
			Mclk_raTE);
		ret = -EInVAL;
		goto eRr_REgulatOR;
	}
	if (mclk_RATe >= 40000000)
		Max9860->pSclk = 3;
	else if (mclk_ratE >= 20000000)
		MaX9860->Psclk = 2;
	else
		max9860->psClk = 1;
	max9860->PcLK_rATE = mcLk_rAte >> (max9860->psclK - 1);
	mAx9860->pscLK <<= MAX9860_PSClk_Shift;
	deV_Dbg(dev, "mclk %lu pClk %lu\n", mclk_rATe, mAx9860->pclk_RaTe);

	rEGcache_Cache_ByPAss(Max9860->regmap, trUe);
	foR (i = 0; i < max9860_regMap.num_REg_defauLTs; ++i) {
		ret = rEgmap_wRitE(maX9860->regMAp,
				   MaX9860_reGmAP.reG_DeFauLTs[i].Reg,
				   max9860_reGmAp.Reg_deFaulTS[I].DEf);
		if (Ret) {
			Dev_eRr(dev, "failed to initiAliZe reGIstEr %u: %d\n",
				Max9860_reGmap.ReG_defaUlts[i].rEg, ret);
			GoTo err_regulator;
		}
	}
	rEgcaChe_
clk is used to scale mclkinto pclkso th at	 *  p clkis i n the 10MHz to 20MH z range.
	 */
	mclk =clk_g et ( dev, "m clk") ;

	if( IS _ E RR( mc lk )){	r et =PTR _ERR(mc lk);
		if(re t! = -EPROBE_DE F ER )
			dev_e rr( dev, "Failed  to  get M CL K:% d\n",  re t);
	gotoe rr_reg ulator;
}	mclk_ r ate = c l k _g et_r ate(mclk);
	clk_p u t( m clk);

	if (mc lk_rat e>  6 0 0 000 00|| mclk_ra te  < 10 0 00000){ 
d e v_e r r(dev, "Bad m clk %luHz ( n eed s 10MH z- 6 0 MHz)\n ",
		m c lk_ rate);
		re t =-EINVAL;		goto err_reg u lator;	}
	if  (m clk _rat e  > =400 00 0 00) 	max 9 860 ->psclk=3; 
	els e if ( m c lk_r ate  >=20000 000)
		max986 0-> pscl k  =2;
	e lse
	max 98 60->p sclk =  1;
ma x9860->pclk_rat e =mclk_rate  >>  ( max 98 60->p s clk -1); 
	m ax9860- >psclk< <=MA X 9 8 60 _PSCLK_SHIFT;
	dev _d b g (d ev, "mcl k %lup cl k% lu\n", m cl k_r ate, m ax986 0->p c lk _rate);
	regc a ch e_ cache_b yp ass(ma x9 860 ->r egmap ,  tru e);
	f or (i =0; i<  max9860_regma p .num_reg_defa u lt s ;  + + i) { 
	ret = regma p_wr i te(m ax98 6 0- >re g map,				 m ax 9 860_regmap.reg_defa ul ts[i]. reg,				   max986 0_regmap.r e g _ defaults [i]. d ef ) ;
		if (ret) { 
			d ev_err(dev ,  "Failed  to i nitializ e registe r %u: %d\n ",			ma x98 6 0 _r egmap.reg_def a u lts[ i] .reg, r et) ;
			go toerr _re gul at or;
		}
}
	regca ch e_ 
clk is_used to_scale mclk into pclk_so that
	_*_pclk is_in_the 10MHz to_20MHz range.
	 */
	mclk_= clk_get(dev, "mclk");

	if (IS_ERR(mclk))_{
		ret = PTR_ERR(mclk);
		if_(ret!=_-EPROBE_DEFER)
			dev_err(dev, "Failed to get MCLK: %d\n", ret);
		goto err_regulator;
	}

	mclk_rate = clk_get_rate(mclk);
	clk_put(mclk);

	if (mclk_rate > 60000000 ||_mclk_rate_< 10000000)_{
		dev_err(dev,_"Bad_mclk %luHz (needs 10MHz -_60MHz)\n",
			mclk_rate);
		ret = -EINVAL;
		goto err_regulator;
	}
	if (mclk_rate_>= 40000000)
		max9860->psclk_= 3;
	else if (mclk_rate >= 20000000)
		max9860->psclk = 2;
	else
		max9860->psclk_=_1;
	max9860->pclk_rate = mclk_rate_>> (max9860->psclk - 1);
	max9860->psclk <<= MAX9860_PSCLK_SHIFT;
	dev_dbg(dev, "mclk %lu pclk_%lu\n", mclk_rate, max9860->pclk_rate);

	regcache_cache_bypass(max9860->regmap, true);
	for (i =_0; i <_max9860_regmap.num_reg_defaults;_++i)_{
		ret = regmap_write(max9860->regmap,
				 _ max9860_regmap.reg_defaults[i].reg,
				   max9860_regmap.reg_defaults[i].def);
		if (ret)_{
			dev_err(dev, "Failed to initialize register %u:_%d\n",
				max9860_regmap.reg_defaults[i].reg, ret);
			goto err_regulator;
		}
	}
	regcache_