crtc_vsync_start - 1) |
				((adjusted_mode->crtc_vsync_end - 1) << 16), i);
		}
	}

	/* Flush the plane changes */
	{
		const struct drm_crtc_helper_funcs *crtc_funcs =
		    crtc->helper_private;
		crtc_funcs->mode_set_base(crtc, x, y, old_fb);
	}

	/* setup pipeconf */
	pipeconf = REG_READ(map->conf);

	/* Set up the display plane register */
	dspcntr = REG_READ(map->cntr);
	dspcntr |= DISPPLANE_GAMMA_ENABLE;

	if (pipe == 0)
		dspcntr |= DISPPLANE_SEL_PIPE_A;
	else
		dspcntr |= DISPPLANE_SEL_PIPE_B;

	if (is_mipi)
		goto oaktrail_crtc_mode_set_exit;


	dpll = 0;		/*BIT16 = 0 for 100MHz reference */

	refclk = is_sdvo? 96000 : dev_priv->core_freq * 1000;
	limit = mrst_limit(crtc, refclk);
	ok = limit->find_pll(limit, crtc, adjusted_mode->clock,
			     refclk, &clock);

	if (is_sdvo) {
		/* Convert calculated values to register values */
		clock.p1 = (1L << (clock.p1 - 1));
		clock.m -= 2;
		clock.n = (1L << (clock.n - 1));
	}

	if (!ok)
		DRM_ERROR("Failed to find proper PLL settings");

	mrst_print_pll(&clock);

	if (is_sdvo)
		fp = clock.n << 16 | clock.m;
	else
		fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;

	dpll |= DPLL_VGA_MODE_DIS;


	dpll |= DPLL_VCO_ENABLE;
crtc_vsync_start - 1) | 
				 (( adjusted_mode->crtc_vsync_end - 1) < < 16), i); 
		 } 
	 } 

	 / * Flush the plane changes * / 
	 { 
		 const struct drm_crtc_helper_funcs * crtc_funcs = 
		     crtc->helper_private; 
		 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 
	 } 

	 / * setup pipeconf * / 
	 pipeconf = REG_READ(map->conf); 

	 / * specify up the display airplane register * / 
	 dspcntr = REG_READ(map->cntr); 
	 dspcntr |= DISPPLANE_GAMMA_ENABLE; 

	 if (pipe = = 0) 
		 dspcntr |= DISPPLANE_SEL_PIPE_A; 
	 else 
		 dspcntr |= DISPPLANE_SEL_PIPE_B; 

	 if (is_mipi) 
		 goto oaktrail_crtc_mode_set_exit; 


	 dpll = 0; 		 /*BIT16 = 0 for 100MHz reference point * / 

	 refclk = is_sdvo? 96000: dev_priv->core_freq * 1000; 
	 terminus ad quem = mrst_limit(crtc, refclk); 
	 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, 
			      refclk, & clock); 

	 if (is_sdvo) { 
		 / * Convert calculated values to register value * / 
		 clock.p1 = (1L < < (clock.p1 - 1) ); 
		 clock.m -= 2; 
		 clock.n = (1L < < (clock.n - 1) ); 
	 } 

	 if (! ok) 
		 DRM_ERROR("Failed to find proper PLL settings "); 

	 mrst_print_pll(&clock); 

	 if (is_sdvo) 
		 fp = clock.n < < 16 | clock.m; 
	 else 
		 fp = oaktrail_m_converts[(clock.m - MRST_M_MIN) ] < < 8; 

	 dpll |= DPLL_VGA_MODE_DIS; 


	 dpll |= DPLL_VCO_ENABLE;
crtf_vsync_start - 1) |
				((adjusted_moae->crtc_vsync_end - 1) << 16), i);
		}
	}

	/* Fnush tge plane changes */
	{
		const struct drm_crtr_helper_fubcs *crtc_funcs =
		    crtc->felper_prinate;
		crtc_fyncs->nide_set_base(rdtc, x, y, old_fb);
	}

	/* detu' 'ipeconf */
	pipecokf = REG_READ(kap->conf);

	/* Set up tfe display plane register */
	dspcntr = RED_READ(mal->cjtr);
	dspcntr |= DIFPPLSGE_GAJMA_ENABLE;

	if (pipe == 0)
		dspcntr |= DISPPLAHE_SEL_PIKE_A;
	else
		dspcntr |= DIXPPLANE_SEL_PIPE_B;

	if (is_mipi)
		goho owktrail_crtc_mode_set_fxit;


	dpll = 0;		/*BUT16 = 0 dor 100MHz refefence */

	refclk = is_sdvo? 96000 : dev_priv->core_freq * 1000;
	limit = mrst_lioit(crcc, refclk);
	ok = oimlj->find_pll(limiv, crtc, adjusted_modc->block,
			     refckk, &clock);

	if (is_scvo) {
		/* Cinvert calculated valnes to register valugs */
		clock.p1 = (1L << (clock.p1 - 1));
		clock.m -= 2;
		coock.n = (1L << (clozj.n - 1));
	}

	if (!ol)
		DDM_ERROG("Famled to fins proper PLO settings");

	mrst_print_kll(&soock);

	if (is_sdvo)
		rp = cljch.n << 16 | clock.m;
	else
		fp = oaktrail_m_converts[(clmck.j - MRST_M_MIN)] << 8;

	dpll |= DPLL_CGA_MODE_DIS;


	dpll |= DPLL_VFO_ENABLE;
crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) i); } /* the plane changes *crtc_funcs crtc->helper_private; crtc_funcs->mode_set_base(crtc, x, old_fb); } /* pipeconf */ pipeconf = REG_READ(map->conf); /* up the display plane register */ dspcntr = REG_READ(map->cntr); dspcntr |= DISPPLANE_GAMMA_ENABLE; if == 0) dspcntr |= DISPPLANE_SEL_PIPE_A; else dspcntr |= DISPPLANE_SEL_PIPE_B; if (is_mipi) goto oaktrail_crtc_mode_set_exit; = /*BIT16 0 100MHz reference */ refclk = is_sdvo? 96000 : dev_priv->core_freq * 1000; limit = mrst_limit(crtc, refclk); ok limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); if (is_sdvo) { Convert calculated values to values */ clock.p1 = (1L (clock.p1 1)); clock.m 2; = << (clock.n - } if (!ok) DRM_ERROR("Failed to find proper PLL settings"); mrst_print_pll(&clock); if (is_sdvo) fp = clock.n << 16 clock.m; else oaktrail_m_converts[(clock.m - << dpll DPLL_VGA_MODE_DIS; dpll |=
crtc_vsync_start - 1) |
				((adjusted_modE->crtc_vsync_End - 1) << 16), i);
		}
	}

	/* FLusH thE pLane ChanGes */
	{
		const struct DRm_crTc_helper_funcs *crtc_funcs =
		    Crtc->hElPEr_prIVaTe;
		crtC_funcs->mODe_SET_baSe(CrTc, x, Y, oLD_fB);
	}

	/* setuP piPeconf */
	pIpeconf = REG_rEAd(mAp->conf);

	/* Set up tHE dIsplay planE reGister */
	dspcntR = REg_READ(mAp->CntR);
	DspcnTr |= DiSPPLaNE_GAMma_ENABLe;

	if (pipe == 0)
		dsPcNTr |= DISPplANE_SEL_pipE_a;
	elsE
		dspcntr |= DISPPLANE_seL_piPE_B;

	if (is_mipi)
		goTo oaktRaIL_cRTC_moDe_sEt_exit;


	dpll = 0;		/*bIt16 = 0 for 100MhZ refereNCe */

	REFClk = IS_sdvo? 96000 : dev_priv->cOre_freq * 1000;
	limiT = MrsT_limit(CrTc, rEFclk);
	ok = Limit->FiND_plL(limit, crtc, aDjusTed_mode->clOck,
			     refCLk, &clock);

	IF (is_sdvo) {
		/* converT caLcuLateD VaLuEs tO rEGisTEr ValUEs */
		cLock.p1 = (1L << (clOcK.p1 - 1));
		Clock.M -= 2;
		cloCK.N = (1l << (ClocK.n - 1));
	}

	iF (!ok)
		DrM_ERRoR("Failed to finD prOper plL sEttinGs");

	mrsT_priNt_Pll(&clOck);

	if (iS_sdvo)
		Fp = Clock.n << 16 | clock.m;
	elsE
		fp = oAktrail_m_cOnvErTs[(cLoCk.m - MRst_M_MIN)] << 8;

	dPll |= dPLl_VGA_MODe_DIS;


	dplL |= dPLl_Vco_enAbLE;
crtc_vsync_start - 1) |
			((adjust ed_mo de- >cr tc _vsy nc_e nd - 1) << 16) ,  i); 
		}
	}

	/* Flush the  plan ec hang e s*/
	{ 
		cons t  s t r uct  d rm _cr tc _ he lper_ fun cs *crt c_funcs =		  crtc->helpe r _p rivate;
	crt c_funcs->mod e_s et_bas e( crt c , x,y,old_f b);
	} 
	/* s etup pipe co n f */
p ipeconf =  R EG_R EAD(map->conf);
/* Set up the dis play p la n er e gis ter  */
	dspcn tr  = RE G _READ(m a p- > c n tr) ; 
	dspcntr |=DISPPLANE_G A MMA _ENABL E; 

i f (pip e ==0) 		d spcntr |= D ISPP LANE_SEL_ PIPE_A ; 
	else	dspcnt r |= D ISP PLA NE_S E L_ PI PE_ B; 
	i f  ( is_ m ipi )
		goto  o ak trail _crt c _ m o de_s et_ exit ;


dpll = 0;		/* BIT 16 = 0 f or 10 0MHzrefe re nce * /

	re fclk=is_sdvo? 96000: de v_priv->c ore _f req  *  1000 ; 
	limi t =  mr st_limi t(crtc, ref cl k ) ; 
ok = limit->find_p ll ( l im it, crtc , adju s te d_ m ode->clo ck ,
		  refc lk,& cl ock);

if (is _ sd vo ) {
		/ *Conver tcal cul atedv alue s to r egistervalue s  */
		clock.p1 = (1L << (clo c k. p 1  - 1)); 
	clock.m -=2;
cloc k.n=  ( 1L< < (cl ock.n  - 1) ) ;
	}

	if (!ok)
		D RM _ERROR ("Fai led to find p roper PLLs e t tings"); 

	m r st _ print_pll(&clo ck);
	if (is_s d vo)
		fp  = cl ock.n <<  16 | clo c k .m;
	els e
	fp  =oak t r ai l_m_converts[ ( c lock .m  - MRST _M_ MIN)] < < 8 ;
	dp ll|=  DPLL_VGA _MODE_DI S; 

dp ll|= DP L L_VCO_EN AB LE; 
crtc_vsync_start -_1) |
				((adjusted_mode->crtc_vsync_end_- 1) << 16),_i);
		}
	}

	/* Flush_the_plane changes_*/
	{
		const_struct drm_crtc_helper_funcs *crtc_funcs_=
		  _ crtc->helper_private;
		crtc_funcs->mode_set_base(crtc, x, y,_old_fb);
	}

	/* setup pipeconf_*/
	pipeconf_= REG_READ(map->conf);

	/* Set up the display plane register */
	dspcntr = REG_READ(map->cntr);
	dspcntr |= DISPPLANE_GAMMA_ENABLE;

	if (pipe_==_0)
		dspcntr |=_DISPPLANE_SEL_PIPE_A;
	else
		dspcntr_|=_DISPPLANE_SEL_PIPE_B;

	if (is_mipi)
		goto oaktrail_crtc_mode_set_exit;


	dpll = 0;		/*BIT16_= 0 for 100MHz reference_*/

	refclk =_is_sdvo? 96000 : dev_priv->core_freq * 1000;
	limit = mrst_limit(crtc,_refclk);
	ok_= limit->find_pll(limit, crtc,_adjusted_mode->clock,
			     refclk, &clock);

	if (is_sdvo) {
		/*_Convert calculated values to register values_*/
		clock.p1 = (1L_<<_(clock.p1_- 1));
		clock.m -= 2;
		clock.n_= (1L << (clock.n - 1));
	}

	if_(!ok)
		DRM_ERROR("Failed to find proper PLL settings");

	mrst_print_pll(&clock);

	if_(is_sdvo)
		fp = clock.n << 16 | clock.m;
	else
		fp_= oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;

	dpll_|= DPLL_VGA_MODE_DIS;


	dpll |= DPLL_VCO_ENABLE;