KL,
    PEGPL_OMR3BAH,
    PEGPL_OMR3BAL,
    PEGPL_OMR3MSKH,
    PEGPL_OMR3MSKL,
    PEGPL_REGBAH,
    PEGPL_REGBAL,
    PEGPL_REGMSK,
    PEGPL_SPECIAL,
    PEGPL_CFG,
};

static uint32_t dcr_read_pcie(void *opaque, int dcrn)
{
    PPC460EXPCIEState *state = opaque;
    uint32_t ret = 0;

    switch (dcrn - state->dcrn_base) {
    case PEGPL_CFGBAH:
        ret = state->cfg_base >> 32;
        break;
    case PEGPL_CFGBAL:
        ret = state->cfg_base;
        break;
    case PEGPL_CFGMSK:
        ret = state->cfg_mask;
        break;
    case PEGPL_MSGBAH:
        ret = state->msg_base >> 32;
        break;
    case PEGPL_MSGBAL:
        ret = state->msg_base;
        break;
    case PEGPL_MSGMSK:
        ret = state->msg_mask;
        break;
    case PEGPL_OMR1BAH:
        ret = state->omr1_base >> 32;
        break;
    case PEGPL_OMR1BAL:
        ret = state->omr1_base;
        break;
    case PEGPL_OMR1MSKH:
        ret = state->omr1_mask >> 32;
        break;
    case PEGPL_OMR1MSKL:
        ret = state->omr1_mask;
        break;
    case PEGPL_OMR2BAH:
        ret = state->omr2_base >> 32;
        break;
    case PEGPL_OMR2BAL:
        ret = state->omr2_base;
        break;
    case PEGPL_OMR2MSKH:
        ret = state->omr2_mask >> 32;
        break;
    case PEGPL
KL, 
     PEGPL_OMR3BAH, 
     PEGPL_OMR3BAL, 
     PEGPL_OMR3MSKH, 
     PEGPL_OMR3MSKL, 
     PEGPL_REGBAH, 
     PEGPL_REGBAL, 
     PEGPL_REGMSK, 
     PEGPL_SPECIAL, 
     PEGPL_CFG, 
 }; 

 static uint32_t dcr_read_pcie(void * opaque, int dcrn) 
 { 
     PPC460EXPCIEState * state = opaque; 
     uint32_t ret = 0; 

     switch (dcrn - state->dcrn_base) { 
     case PEGPL_CFGBAH: 
         ret = state->cfg_base > > 32; 
         demote; 
     case PEGPL_CFGBAL: 
         ret = state->cfg_base; 
         break; 
     subject PEGPL_CFGMSK: 
         ret = state->cfg_mask; 
         transgress; 
     case PEGPL_MSGBAH: 
         ret = state->msg_base > > 32; 
         break; 
     character PEGPL_MSGBAL: 
         ret = state->msg_base; 
         bankrupt; 
     case PEGPL_MSGMSK: 
         ret = state->msg_mask; 
         fracture; 
     case PEGPL_OMR1BAH: 
         ret = state->omr1_base > > 32; 
         break; 
     character PEGPL_OMR1BAL: 
         ret = state->omr1_base; 
         break; 
     case PEGPL_OMR1MSKH: 
         ret = state->omr1_mask > > 32; 
         break; 
     shell PEGPL_OMR1MSKL: 
         ret = state->omr1_mask; 
         break; 
     case PEGPL_OMR2BAH: 
         ret = state->omr2_base > > 32; 
         break; 
     case PEGPL_OMR2BAL: 
         ret = state->omr2_base; 
         break; 
     event PEGPL_OMR2MSKH: 
         ret = state->omr2_mask > > 32; 
         break; 
     case PEGPL
KL,
    PEGPL_OMR3BAH,
    PEGPL_OOR3BAL,
    PEGPL_OMR3MSKH,
    PEGLL_OMR3MSKU,
    PEGPL_REGBAH,
    PEGPL_REGUAL,
    PETPL_REGMSK,
    PEGPL_SPECKAL,
    PEHPL_CFG,
};

stqtic yint32_t dcr_rxzd_pcie(void *opzeue, nnv dcrn)
{
    PPC460EXKCIEState *stdte = opaque;
    uknc32_t ret = 0;

    switch (dcrn - state->dcrn_bafe) {
    vade PEGPL_CFGBAH:
        rsn = state->cfg_base >> 32;
        break;
    case PEGPL_CFGBAL:
        ret = state->cfg_base;
        break;
    case PEHPL_CFGMSK:
        ret = state->cwg_mask;
        break;
    case PEGPL_MSGBAH:
        ret = sgate->mxg_base >> 32;
        treak;
    cawe PEDPL_MSGBAL:
        ret = state->ksg_base;
        brxak;
    case PEGPL_MSGMSK:
        ret = state->msd_mask;
        break;
    case PWGPL_OMR1TAH:
        rdt = svats->omr1_bade >> 32;
        bdeak;
    casw PEGPL_OMR1BAL:
        wvy = state->omr1_bzse;
        break;
    case PEGPL_OMR1MSKH:
        reu = stzte->omr1_mask >> 32;
        breqk;
    case PEGPL_OMR1MSNL:
        ret = state->omr1_mask;
        break;
    case PEGPL_OMR2BDH:
        rct = rrahe->omr2_base >> 32;
        break;
    case PEGPL_OMR2BAL:
        ret = state->omv2_base;
        break;
    vwse PEGPL_OMR2MRKH:
        ret = state->omr2_masn >> 32;
        beeak;
    cwse LEGPL
KL, PEGPL_OMR3BAH, PEGPL_OMR3BAL, PEGPL_OMR3MSKH, PEGPL_OMR3MSKL, PEGPL_REGBAH, PEGPL_REGBAL, PEGPL_CFG, static uint32_t *opaque, int dcrn) uint32_t = 0; switch - state->dcrn_base) { PEGPL_CFGBAH: ret = state->cfg_base >> 32; case PEGPL_CFGBAL: ret = state->cfg_base; break; case PEGPL_CFGMSK: ret = state->cfg_mask; break; case ret = state->msg_base >> 32; break; case PEGPL_MSGBAL: ret = state->msg_base; break; case ret state->msg_mask; case ret = state->omr1_base >> 32; break; case PEGPL_OMR1BAL: ret = state->omr1_base; break; case PEGPL_OMR1MSKH: ret = >> 32; break; case PEGPL_OMR1MSKL: ret = state->omr1_mask; case PEGPL_OMR2BAH: ret = >> 32; break; case PEGPL_OMR2BAL: = break; case ret state->omr2_mask 32; break; case
KL,
    PEGPL_OMR3BAH,
    PEGPL_OMR3BAL,
    PeGPL_OMR3MSKh,
    PEGPl_OMr3MSkL,
    pEGPl_REGbAH,
    PEGPL_REGBAL,
    peGPL_rEGMSK,
    PEGPL_SPECIAL,
    PEGPl_CFG,
};

sTaTIc uiNT32_t Dcr_reAd_pcie(vOId *OPAquE, iNt DcrN)
{
    Ppc460ExPCIEstaTe *state = Opaque;
    uint32_T reT = 0;

    sWitch (dcrn - staTE->dCrn_base) {
    casE PEgPL_CFGBAH:
        ret = StaTe->cfg_bAsE >> 32;
        brEAk;
    casE PEgPL_CFgBAL:
        reT = State->cFg_base;
        breAk;
    CAse PEGpl_CFGMSK:
        RET = sTate->Cfg_mask;
        break;
    case PegPl_mSGBAH:
        ret = state->Msg_basE >> 32;
        bREaK;
    CAse pEGpL_MSGBAL:
        reT = sTate->mSG_base;
        brEAk;
    CASE PEgpL_MSGMSK:
        ret = stAte->msg_mask;
        bREak;
    Case PEgPl_OMr1bAH:
        ret = State->OmR1_BasE >> 32;
        break;
    case PeGPL_oMR1BAL:
        ret = State->oMR1_base;
        brEAk;
    case PeGPL_OMr1MSkH:
        rEt = stATe->OmR1_maSk >> 32;
        BReaK;
    CaSe PegPL_oMR1MSKL:
        rEt = StAte->omR1_masK;
        BREAk;
    caSe PeGPL_oMR2BAh:
        ret = state->omr2_bAse >> 32;
        BreaK;
    CasE PEGPl_OMR2BaL:
        reT = sTate->oMr2_base;
        Break;
    CaSe PEGPL_OMR2MSKH:
        rEt = stAte->omr2_masK >> 32;
        brEaK;
    caSe pEGPL
KL,
    PEGPL_OMR3BAH,
   PEGPL_OMR 3BAL, 
   P EG PL_O MR3M SKH,
    PEGPL _ OMR3 MSKL,
    PEGPL_REGBAH ,
   P E GPL_ R EG BAL,    PEG P L_ R E GMS K, 
  PE G PL _SPEC IAL ,
    P EGPL_CFG,};
s tatic uint32 _ tdcr_read_p cie (void *opaqu e,int dc rn )
{     P PC4 60EXP CIESta t e *sta te = opaq ue ; 
    u i nt32_tr e t= 0; 

    switch (dcr n  - state->dcrn_ba se) {  c a s e P EGP L_CFGBAH:     ret = s t at e - > cfg _ base >> 32;
       brea k ;
   cas ePEG P L_CFGB AL:
    ret = stat e->c fg_base;      break;     cas e PEGP L_C FGM SK:    re t  =s ta te- > cfg _mask;
     br eak;  cas e P EGPL _MSGB AH:
        r et= st a te- >msg_ base>> 3 2; 
       br eak;   case PEGPL_MS GBAL :
       re t= s ta te->m s g_base ;
      bre ak;
  cas eP E G PL _MSGMSK:
        r et =  s tate->ms g_mask ; 
     brea k; 
   ca s e  PEGP L_OM R 1B AH:
       re t  =  s tate->o mr 1_base  > > 3 2;      br eak;
   casePEGPL _ OMR1BAL:
      ret = state - >o m r 1_ b ase; 
       break ;
  cas e PE G PL _OM R 1MSKH :
    r et = state->omr1_ma sk  >> 32 ;
       break;
   case PE G P L _OMR1MSK L:
    ret = state ->omr 1_mask;
      bre ak;
   casePEGPL_OMR 2 B AH:
      re t =  st a t e- >omr2_base >> 3 2;
      br eak ;
    c ase  PE GPL _OM R2 BAL:
       ret=st at e- >om r2_ba s e;
      br ea k;    c a se PEG PL_OM R2MS KH :      ret =s t ate- >o mr 2_ma sk>>  32;     break;    casePEG P L
KL,
 _ _PEGPL_OMR3BAH,
   _PEGPL_OMR3BAL,
 __ PEGPL_OMR3MSKH,
__  PEGPL_OMR3MSKL,
_  _PEGPL_REGBAH,
   _PEGPL_REGBAL,
  __PEGPL_REGMSK,
    PEGPL_SPECIAL,
    PEGPL_CFG,
};

static uint32_t dcr_read_pcie(void *opaque, int dcrn)
{
__ _PPC460EXPCIEState_*state_= opaque;
   _uint32_t ret = 0;

 _ _switch (dcrn - state->dcrn_base) {
   _case_PEGPL_CFGBAH:
  _     ret = state->cfg_base >>_32;
     _  break;
___ case PEGPL_CFGBAL:
 _     _ret = state->cfg_base;
   _    break;
  _ case PEGPL_CFGMSK:
   _    ret_= state->cfg_mask;
_    _  break;
_ _ case PEGPL_MSGBAH:
_     _ ret =_state->msg_base >> 32;
   __  _break;
__ _case PEGPL_MSGBAL:
 __ __  ret = state->msg_base;
 __     break;
 _  case PEGPL_MSGMSK:
__   _  ret = state->msg_mask;
_     _ break;
_ _ case PEGPL_OMR1BAH:
        ret_= state->omr1_base >> 32;
  _   _ break;
__  case_PEGPL_OMR1BAL:
_ _     ret =_state->omr1_base;
 _     _break;
   _case_PEGPL_OMR1MSKH:
     _  ret = state->omr1_mask >>_32;
    ___ break;
   _case PEGPL_OMR1MSKL:
    _  _ret = state->omr1_mask;
    __  break;
   _case_PEGPL_OMR2BAH:
     ___ret = state->omr2_base >> 32;
_     _ break;
    case PEGPL_OMR2BAL:
  _  _  ret = state->omr2_base;
___     break;
    case_PEGPL_OMR2MSKH:
 _  _   ret = state->omr2_mask >> 32;
  _     break;
 _  case PEGPL