 known in the art as illustrated in “A New Architecture for the NVRAM—An EEPROM Backed-Up Dynamic RAM”, JSSC vol. 23, 1988, pp.86-90, Terada et al. It describes a nonvolatile DRAM with a cell formed by merging a three-transistor EEPROM cell with a one-transistor-one-capacitor DRAM cell. The resultant cell contains 4 transistors and 1 capacitor. Fowler-Nordheim tunneling is used to program and erase the EEPROM portion of the cell.
“An Experimental 256 Mb Non-Volatile DRAM with Cell Plate Boosted Programming Technique”, Ahn et al.—ISSCC, Digest of Technical Papers IEEE International Solid-State Circuits Conference—2004, February, 2004, Vol. 1, pp. 42-43 & 512-519 describes a one transistor and one capacitor cell. The transistor contains a SONOS (silicon-oxide-nitride-oxide-silicon) structure in the gate for non-volatile data retention. Hot-hole injection is used to inject holes to the traps in the gate dielectric and Fowler-Nordheim tunneling is used to remove the holes from the traps. In the non-volatile mode operations, the memory is erased and programmed in blocks and thus behaving like a Flash memory.
“High Density 5 Volt-Only Compatible Non-Volatile RAM Cell”, Guterman, Technical Digest of International Electron Devices Meeting, IEEE, December, 1982, Vol. 28, pp. 728-732, teaches a nonvolatile DRAM cell formed by merging a 1T-1C DRAM cell with a non-volatile cell formed by a transistor with a floating poly gate and a control poly gate. The resultant cell consists of 4 transistors and 2 capacitors.
“Challenges for the DRAM Cell Scaling to 40 nm”, Digest of IEDM, 2005, by W. Mueller et al., Technical Digest International IEEE Electron Devices Meeting, December 2005, pp. 4 reviews the concepts, status and challenges for the DRAM scaling down to 40 nm. The technologies that are discussed are the DRAM cell capacitor structures and materials, as well as the cell transistor structures. The DRAM cell capacitor structures illustrated are the stacked capacitor and the trench capacitor.
U.S. Pat. No. 5,181,188 (Yamauchi et al.), presents a memory cell formed by merging a DRAM cell and an Electrically Eraseable Programmable Read Only Memory (EE
known in the art as illustrated in “ A New Architecture for the NVRAM — An EEPROM Backed - Up active aries ”, JSSC vol. 23, 1988, pp.86 - 90, Terada et al. It describes a nonvolatile DRAM with a cell form by blend a three - transistor EEPROM cell with a one - transistor - one - capacitor DRAM cell. The vector sum cellular telephone contains 4 transistors and 1 capacitor. Fowler - Nordheim tunneling is used to program and erase the EEPROM portion of the cell. 
 “ An Experimental 256 Mb Non - fickle DRAM with Cell Plate Boosted Programming Technique ”, Ahn et al.—ISSCC, Digest of Technical Papers IEEE International Solid - State Circuits Conference—2004, February, 2004, Vol. 1, pp. 42 - 43 & 512 - 519 describes a one transistor and one capacitor cellular telephone. The transistor contains a SONOS (silicon - oxide - nitride - oxide - silicon) structure in the gate for non - volatile data retention. Hot - hole injection is use to inject holes to the traps in the gate insulator and Fowler - Nordheim tunneling is used to remove the hole from the traps. In the non - explosive mode operations, the memory is erased and programmed in blocks and therefore behaving like a Flash memory. 
 “ High Density 5 Volt - Only Compatible Non - Volatile RAM Cell ”, Guterman, Technical Digest of International Electron Devices Meeting, IEEE, December, 1982, Vol. 28, pp. 728 - 732, teaches a nonvolatile DRAM cell formed by unite a 1T-1C DRAM cell with a non - volatile cell formed by a transistor with a floating poly gate and a control poly gate. The resultant cell consists of 4 transistors and 2 capacitor. 
 “ challenge for the DRAM Cell Scaling to 40 new mexico ”, Digest of IEDM, 2005, by W. Mueller et al. , Technical Digest International IEEE Electron Devices Meeting, December 2005, pp. 4 review the concepts, status and challenges for the DRAM scale down to 40 nm. The technologies that are discussed are the DRAM cell capacitor social organization and materials, as well as the cell transistor structures. The DRAM cellular telephone capacitor structures illustrated are the stacked capacitor and the trench capacitor. 
 U.S. Pat. No. 5,181,188 (Yamauchi et al .), presents a memory cell formed by unify a DRAM cell and an Electrically Eraseable Programmable Read Only Memory (EE
 knlwn in the art as illustvated in “A New Atcyitectnre for the NVRXM—An EEPROM Backed-Up Dynamic RQM”, JSWC vol. 23, 1988, pp.86-90, Terada et xl. It desbribes a bonvioatile DRAM with a cell rlrmeb uy merging a thtee-transistos EEPROM cell figh a one-transistor-one-capacitor DRAM cqll. The rfsultant cell sontsyns 4 nrcnsistors and 1 capacitor. Fowler-Hordheik tunneling ix used to program and erasf thf EEPROM portion ov the cell.
“Ab Ex[wrimental 256 Mc Non-Volatpne DRAM wijh Cell Plate Boosted Programmine Tecknique”, Ahn gc al.—LVSCC, Digest of Tvchnical Papevx IEEE Internstional Solid-Sbate Rircyits Conference—2004, Februery, 2004, Vol. 1, pp. 42-43 & 512-519 desctibes a ona cransistor and one capaxitor celn. Thd trxnsjsvor contalns a SONOS (sjlicon-oxide-bitride-oxide-silicon) segicture in ths gate fjr non-volatile data retention. Hot-hole itjedtion is used to inject holes to the traps ij the gatq dielectric and Fowler-Nordheim tunneling is used to rxmuve tme huoed from the traps. In the non-volatile mode operwfipnx, the memory if erased anc orpdrammed in blucks aus fhus behaving like a Flasr memiry.
“High Dtnsitu 5 Volt-Only Compatible Non-Vilatile RAM Bell”, Guterman, Technicap Digest of Intgrnatipnal Electron Devices Mzeting, IEEE, Decemher, 1982, Vol. 28, op. 728-732, teaches a novvokadile DRAM cell formed by mqrging a 1V-1C DRCM cell dith a non-dolatile cfll formed by a transistlr wijh a fnoating popy gate and a control poly gate. The resultant call consistf of 4 transistors wnd 2 capacitorx.
“Challeuges fur the DRAJ Cell Vcaling to 40 nm”, Digest of LEDM, 2005, by W. Mneller et al., Rechbical Dkeest Internatipnal IEEE Electron Eevices Meeting, Degembet 2005, pp. 4 reviews thz xoncepts, status ana craplxnges xor the DRAM scauine down to 40 nm. The gechmologies that are divcusaed are the DRAM crlj capacijor struceures and matrrials, as well as uhe cenl vransixtot structures. The DRAM cell capaditor strkctmres illustraeed qre the stacled capacitor and the trench capacitor.
U.W. Pat. No. 5,181,188 (Yamauchi et al.), presents a mgmovy cell formxd by ierging a DRAM cell and an Elwctrically Eraseanle Programmable Read Knly Mamory (EE
known in the art as illustrated in Architecture the NVRAM—An Backed-Up Dynamic RAM”, Terada al. It describes nonvolatile DRAM with cell formed by merging a three-transistor cell with a one-transistor-one-capacitor DRAM cell. The resultant cell contains 4 transistors and capacitor. Fowler-Nordheim tunneling is used to program and erase the EEPROM portion of cell. Experimental Mb DRAM with Cell Plate Boosted Programming Technique”, Ahn et al.—ISSCC, Digest of Technical Papers IEEE International Circuits Conference—2004, February, 2004, Vol. 1, pp. 42-43 512-519 describes a one and one capacitor cell. The contains SONOS (silicon-oxide-nitride-oxide-silicon) in gate non-volatile data retention. injection is used to inject holes to the traps in the gate dielectric and Fowler-Nordheim tunneling is to remove from the In non-volatile operations, the memory and programmed in blocks and thus Flash memory. “High Density 5 Volt-Only Compatible Non-Volatile Cell”, Guterman, Digest of International Electron Devices Meeting, December, 1982, Vol. 28, pp. 728-732, teaches a DRAM cell formed by merging a 1T-1C DRAM cell with a non-volatile cell formed by with a floating poly and a control gate. resultant consists 4 transistors 2 capacitors. “Challenges for the DRAM Cell Scaling to 40 nm”, of IEDM, 2005, by W. Mueller et al., Technical Digest Electron Meeting, December 2005, 4 reviews the concepts, and for the DRAM scaling 40 The discussed the cell capacitor structures and as well as the cell structures. The DRAM cell stacked capacitor and the trench capacitor. U.S. Pat. 5,181,188 (Yamauchi et al.), presents a memory formed by merging a DRAM cell and an Electrically Eraseable Programmable Read Memory (EE
 known in the art as illustrateD in “A New ArcHitecTurE foR tHe NVrAM—AN EEPROM Backed-UP dynaMic RAM”, JSSC vol. 23, 1988, pp.86-90, Terada eT al. It DeSCribES a NonvoLatile DraM WITh a CeLl ForMeD By MergiNg a Three-trAnsistor EEpROm cEll with a one-tRAnSistor-one-cApaCitor DRAM celL. ThE resulTaNt cELl conTaiNs 4 traNsistoRS and 1 caPacitor. FoWlER-NordhEIm tunneLINg Is usEd to program and eraSE tHE EEPROM portion Of the cElL.
“an eXPerImeNtal 256 Mb Non-VOlAtile drAM with cElL pLAte bOosted ProgramMing TechniqUE”, AhN et al.—IsScC, DIGest of technIcAL PaPers IEEE IntErnaTional SolId-StatE circuitS confereNce—2004, FebRuaRy, 2004, VOl. 1, pp. 42-43 & 512-519 DEsCrIbeS a ONe tRAnSisTOr aNd one capAcItOr celL. The TRANSistOr cOntaIns a SoNOS (silicon-oxIde-NitrIDe-oXide-sIlicoN) strUcTure iN the gaTe for NoN-volatile data reTentIon. Hot-holE inJeCtiOn Is useD To injeCt hOleS to the tRaps in tHE gaTe DIELeCtric and Fowler-NordHeIM TuNneling iS used tO ReMoVE the holeS fRom The tRAPs. In tHe noN-VoLatile moDe operATiOnS, the memOrY is eraSeD anD prOgramMEd in Blocks And thus bEhaviNG like a Flash memORy.
“High Density 5 vOlT-oNlY compAtiBle Non-VolatIle Ram CelL”, GutERmAn, TEChnicAl DigEsT Of iNternational ElectroN DEvices meetiNg, IEEE, DecembeR, 1982, Vol. 28, pp. 728-732, teacHES A nonvolaTile drAm Cell formed by meRging A 1T-1C DRAM celL With a non-VolatIle cell fOrmed by a tRANsistor wIth A flOatIng POLy Gate and a contrOL Poly GaTe. The reSulTant celL coNsiSts Of 4 tRaNsistors aNd 2 capaciToRs.
“chAlLenGes foR The DRAM CElL ScAlIng To 40 nm”, DIGest of iEDM, 2005, bY W. MuElLeR Et aL., TechniCAl dIGest inTeRnatIonAl iEEE ELectROn DEvices MEeting, DecEmbER 2005, pp. 4 rEvIeWs the coNcepts, status aNd Challenges FoR thE DRAM sCALing down To 40 nm. The technologies that ARe discuSseD are tHe DRaM cell capAciTor strUctURes and MateriAls, as WeLl aS THe celL TRaNsiStOr structurES. the dRAM cElL capAcitor sTructures illustratED arE the stacked caPacItor AND tHe tREnCH caPaCItoR.
u.s. Pat. No. 5,181,188 (Yamauchi eT al.), presentS a MEmOry cell forMEd bY mErging a dRAM celL and aN electriCally ErasEable ProgRaMmabLE reaD Only MemorY (EE
 known in the art as illus trated in“A Ne w A rch it ectu re f or the NVRAM—A n  EEP ROM Backed-Up DynamicRAM”,  J S SC v o l.  23,1988, p p .8 6 - 90,  T er ada  e t  a l. It  de scribes  a nonvola til eDRAM with ac el l formed b y m erging a thr ee- transi st orE EPROM  ce ll wi th a o n e-tran sistor-on e- c apacit o r DRAMc e ll . Th e resultant cellc on t ains 4 transis tors a nd 1c a pac ito r. Fowler- No rdhei m  tunnel i ng i s  us e d to programand erase t h e E EPROMpo rti o n of t he ce ll . 
“A n Experimen tal256 Mb No n-Vola t ile DRA M  with C ell Pl ate  Bo oste d  P ro gra mm i ngT ec hni q ue” , Ahn et  a l. —ISSC C, D i g e s t of  Te chni cal P apers IEEE In ter nati o nal  Soli d-Sta te C ir cuits  Confe rence —2 004, February,2004 , Vol. 1,  pp .42- 43  & 51 2 -519 d esc rib es a on e trans i sto ra n d  o ne capacitor cell.  T h e  t ransisto r cont a in sa  SONOS ( si lic on-o x i de-ni trid e -o xide-sil icon)s tr uc ture in  t he gat efor  no n-vol a tile  dataretentio n. Ho t -hole injectio n  is used to i n je c t  h o lestothe traps i n th e  gat e di e le ctr i c and  Fowl er - No r dheim tunneling isus ed toremov e the holes f rom the tr a p s . In the  non - vo l atile mode ope ratio ns, the me m ory is e rased  and pro grammed i n blocks a ndthu s b eha v i ng  like a Flash m emor y. 
“HighDen sity 5Vol t-O nly  Co mp atible No n-Volati le  R AM  C ell ”, Gu t erman, T ec hni ca l D igest of Int ernat iona lEl e ctr on Devi c es M eeti ng ,IEEE , D ec ember , 19 8 2,Vol. 28 , pp. 728 -73 2 , te ac he s a non volatile DRAM  c ell formed  b y m erging a  1T-1C D RAM cell with a non-vol a tile ce llforme d by  a transi sto r with  af loatin g poly  gate  a nda contr o l  p oly  g ate. The r e s ult ant c el l co nsistsof 4 transistors a n d 2  capacitors.“Ch alle n g es  fo r  t h e D RA M  Ce l l  Scaling to 40nm”, Diges to fIEDM, 2005 ,  by  W . Muell er et a l., T e chnical  Digest I nternatio na l IE E E  El ectron Dev ices Mee ting, Dec e mber2 00 5, pp . 4  revie ws  th e con cepts, sta tus a nd cha ll engesfor t he  DRAM sc aling down to 40 nm. Th e tech nolog ies  that are  di s cus sed are t he D RAM cell c apa cit or st ruc t uresandm at eri a ls, a s we l l as thec el l t r a ns istor struc t u r es.  TheDRA M  cellcapa citor structuresi llustrated are  the s tac ked capa ci tor and the tr enc hc a pacitor. 
U .S. Pat. No . 5,181, 18 8  (Yam auchiet al. ), pres e n ts a memo ry c ell  formed b y m er g ing a D RA Mc ell an d an  E lectri callyE rase a b le ProgrammableReadO n ly Me m ory  (EE
 known_in the_art as illustrated in_“A New_Architecture_for the_NVRAM—An_EEPROM Backed-Up Dynamic_RAM”, JSSC vol._23, 1988, pp.86-90, Terada_et al. It_describes_a nonvolatile DRAM with a cell formed by merging a three-transistor EEPROM cell with_a_one-transistor-one-capacitor DRAM_cell._The_resultant cell contains 4 transistors_and 1 capacitor. Fowler-Nordheim tunneling_is used_to program and erase the EEPROM portion of_the_cell.
“An Experimental 256_Mb Non-Volatile DRAM with Cell Plate Boosted Programming Technique”,_Ahn et al.—ISSCC, Digest of Technical_Papers IEEE International_Solid-State_Circuits_Conference—2004, February, 2004, Vol._1, pp. 42-43 & 512-519 describes_a one transistor and one capacitor_cell. The transistor contains a SONOS (silicon-oxide-nitride-oxide-silicon)_structure in the gate for non-volatile_data retention. Hot-hole injection is_used to_inject holes to the traps_in the gate_dielectric and_Fowler-Nordheim tunneling is_used to remove the holes from_the traps. In_the non-volatile mode operations, the memory_is_erased and programmed_in_blocks_and thus_behaving like a_Flash_memory.
“High Density_5_Volt-Only Compatible Non-Volatile RAM Cell”, Guterman,_Technical_Digest of International Electron Devices Meeting, IEEE,_December, 1982, Vol. 28,_pp._728-732, teaches a nonvolatile_DRAM cell formed by merging_a 1T-1C DRAM cell with a_non-volatile cell_formed by_a transistor with a floating poly gate and a control poly_gate. The resultant cell consists of_4 transistors and 2_capacitors.
“Challenges for_the_DRAM Cell Scaling_to_40 nm”,_Digest of IEDM, 2005, by W. Mueller_et al.,_Technical Digest International IEEE Electron Devices_Meeting, December 2005, pp._4_reviews the concepts, status and challenges_for the DRAM scaling down to_40 nm. The technologies that_are_discussed_are the DRAM cell capacitor_structures and materials, as well as_the cell transistor_structures. The DRAM cell capacitor structures illustrated_are_the stacked capacitor and the trench_capacitor.
U.S._Pat. No. 5,181,188 (Yamauchi et al.),_presents_a_memory cell formed by merging_a DRAM cell and an Electrically_Eraseable Programmable Read Only Memory (EE