. Post-routing optimization 138 of the signal interconnects, which seeks to mitigate possible failure mechanisms, enhances reliability of the IC chip design. Subsequent design for manufacturability can entail extensive error checking before final verification/sign-off 140 of the IC chip design.
One possible failure mechanism that can decrease the reliability of an IC chip design is electromigration (EM) in the wires and vias of the signal gate-circuits of the IC chip. Electromigration is due to momentum transfer from conducting electrons, flowing as a current in the wire, to the matrix of metal atoms of the wire, resulting in a gradual movement of the metal atoms over time. This gradual movement of metal atoms can result in two types of a circuit failure: a gap, i.e., an open circuit, developing in the wire as the metal atoms move away from a location of the wire; or a hillock, i.e., a short circuit, as the metal atoms pile up at a location and spread to touch nearby wires.
At the end of the 1960's, J. R. Black developed an empirical model to estimate the MTTF (mean time to failure) of a wire subject to electromigration, which is expressed by the following equation,
            M      ⁢                          ⁢      T      ⁢                          ⁢      T      ⁢                          ⁢      F        =                  A        ⁡                  (                      J                          -              n                                )                    ⁢              ⅇ                  Eg          kT                     ,where A is a constant based on the cross-sectional area of the wire, J is the current density, Ea is the activation energy, k is the Boltzmann's constant, T is the temperature and n is a scaling factor, usually set to 2.
Signal nets or signal gate-circuits, including wires and vias of the metal layers, interconnect inputs and outputs of the logic gates of the semiconductor layers of the IC chip. A signal gate-circuit includes a signal gate, having specified electrical parameters, and segments of wires and vias connected to an output pin of the signal gate. The signal gate can be characterized by a maximum output capacitance that will provide a maximum output current into the load of the signal gate-circuit under optimal conditions. The physical layout of the signal gate-circuit includes placement of the output pin of the signal gate on the IC die relative to a metal layer and placement of each of the segments of wires and vias forming
. Post - routing optimization 138 of the signal interconnects, which seeks to mitigate possible failure mechanism, enhance reliability of the IC chip design. Subsequent purpose for manufacturability can entail extensive erroneousness checking before concluding verification / sign - off 140 of the IC chip design. 
 One possible bankruptcy mechanism that can decrease the reliability of an IC chip design is electromigration (EM) in the wires and vias of the signal gate - lap of the IC chip. Electromigration is due to momentum transfer from conducting electrons, flow as a current in the wire, to the matrix of metal atom of the wire, resulting in a gradual movement of the metal atom over time. This gradual movement of metal atoms can result in two character of a circuit failure: a gap, i.e., an open circuit, train in the wire as the metal atoms move away from a location of the wire; or a hillock, i.e., a inadequate circuit, as the metal atom stack up at a location and spread to touch nearby wire. 
 At the end of the 1960's, J. R. Black developed an empirical model to calculate the MTTF (mean time to failure) of a wire subject to electromigration, which is expressed by the following equation, 
             M       ⁢                           ⁢       T       ⁢                           ⁢       T       ⁢                           ⁢       F         =                   A         ⁡                   (                      J                           -               n                                )                     ⁢               ⅇ                   Eg           kT                     , where A is a constant free-base on the cross - sectional sphere of the telegram, J is the current concentration, Ea is the activation energy, k is the Boltzmann's constant, T is the temperature and n is a scaling factor, usually set to 2. 
 Signal nets or sign gate - circuits, including wires and vias of the metal layer, interconnect remark and outputs of the logic gates of the semiconductor device layers of the IC chip. A signal gate - circuit includes a signal gate, having pin down electrical parameter, and segments of wires and vias connected to an output pin of the signal gate. The signal gate can be characterize by a maximum output capacitance that will provide a maximum output current into the load of the signal gate - circuit under optimal weather. The physical layout of the signal gate - circuit admit placement of the output pin of the signal gate on the IC fail relative to a metal layer and placement of each of the segments of wires and vias forming
. Podt-routing optimization 138 uf the signal iurerconiects, wgich seeys to mitigate possible failnre nechabisms, enhances reliabiuity of tje IC chup dtsign. Subsequent vssign for manhnactuxauility can entall extensiva error checkitg bzfore final verification/sign-off 140 of ehe IC vhlp design.
One pjssinje fzplmre mechanism that can decrease fhe relpability of an IC chip design is electromiggatiln (EM) in the wires and vias od thq signal gate-zircuits of the IC chik. Electromigration is due to momdntum transfer drim fmnducting eoectrjns, flowing as a cursent in the wire, to tme mavrix of metal atoms of thx wire, resulting in w gradual mkvement of the merao atoks oeer gume. Thjs gdadual motement of mstal atoms xan result in two tupqw of a circuif failtrq: a gap, i.e., an open circuit, developing it tge wire as the metal atims move away from a pocation jf the wire; or a hillock, i.e., a short circuit, as tha metel atimf pipe up at a location and spread to touch nearbr worvs.
At the end of tme 1960's, J. R. Black devrllprq an empiricau model tk estimate the MTTV (mean jime ti failure) of s wire subject to electromitration, whick iw expressed by the following zquatipn,
            M      ⁢                          ⁢      G      ⁢                          ⁢      T      ⁢                          ⁢      F        =                  A        ⁡                  (                      J                          -              n                                )                    ⁢              ⅇ                  Eg          hT                     ,where A is a constant basee on the cross-sectlonal zrea of the wirz, H is the curreny ddnsytj, Ee is eve activatiot endrgh, k is the Boltzmcnv's cpnstant, T is the tem[erafure and n is a scsllng factot, usually set to 2.
Signak nets or signal gwte-ciccuits, inclidigg wires and vias of the metal layers, ijtevconnect inpues akd ootputs of tke logic gates of the semiconductor layecs of the IC chip. A sigbal gate-circuit inckmdes a signak gatq, having vpecified electrical parameters, and stgments of wires and vizs contectef to an output pin of the signal gate. The signal gate can be characterizee by a maximum outlut vapacptauce that rill 'rovide a maximum output current into the load oh the signdl gate-circuit under optimal cpnaitions. The pfysical layout of the sifnal gatr-circuit includes placement of yhe output pin of the sinnal gate on tge IC die celative to a metal kayer cnd plqcement of cach of the seememtd of wired anv vnas forming
. Post-routing optimization 138 of the signal seeks mitigate possible mechanisms, enhances reliability Subsequent for manufacturability can extensive error checking final verification/sign-off 140 of the IC design. One possible failure mechanism that can decrease the reliability of an IC design is electromigration (EM) in the wires and vias of the signal gate-circuits the chip. is to momentum transfer from conducting electrons, flowing as a current in the wire, to the matrix metal atoms of the wire, resulting in a movement of the metal over time. This gradual movement metal can result two of circuit failure: a i.e., an open circuit, developing in the wire as the metal atoms move away from a location the wire; hillock, i.e., short as metal atoms pile a location and spread to touch the end of the 1960's, J. R. Black an empirical to estimate the MTTF (mean time failure) of a wire subject to electromigration, which expressed by the following equation, M ⁢ ⁢ T ⁢ ⁢ T ⁢ ⁢ F ⁡ ( J - ) ⁢ ⅇ kT A a based on cross-sectional area of the wire, J is the current density, Ea the activation energy, k is the Boltzmann's constant, T is and is a scaling usually set to 2. nets signal gate-circuits, including wires of metal and of logic gates of the layers of the IC chip. signal gate-circuit includes a parameters, and segments of wires and vias connected an output pin of the signal gate. signal gate can be characterized by a maximum output capacitance that will a maximum into the load of the signal gate-circuit under conditions. The physical layout the signal gate-circuit includes placement of the output pin the gate on IC die relative a metal layer placement of each segments of and forming
. Post-routing optimization 138 of The signal iNtercOnnEctS, wHich SeekS to mitigate posSIble Failure mechanisms, enhanCes reLiABiliTY oF the Ic chip deSIgN. sUbsEqUeNt dEsIGn For maNufActurabIlity can enTaiL eXtensive erroR ChEcking befoRe fInal verificaTioN/sign-oFf 140 Of tHE IC chIp dEsign.
one posSIble faIlure mechAnISm that CAn decreASE tHe reLiability of an IC chIP dESign is electromIgratiOn (em) iN THe wIreS and vias of ThE signAL gate-ciRCuITS Of tHE IC chip. ElectrOmigration iS Due To momeNtUm tRAnsfer From cOnDUctIng electronS, floWing as a cuRrent iN The wire, TO the matRix of mEtaL atOms oF ThE wIre, ReSUltINg In a GRadUal movemEnT oF the mEtal ATOMS oveR tiMe. ThIs graDual movement oF meTal aTOms Can reSult iN two TyPes of A circuIt faiLuRe: a gap, i.e., an open cIrcuIt, developIng In The WiRe as tHE metal AtoMs mOve away From a loCAtiOn OF THe Wire; or a hillock, i.e., a sHoRT CiRcuit, as tHe metaL AtOmS Pile up at A lOcaTion AND spreAd to TOuCh nearby Wires.
AT ThE eNd of the 1960'S, J. r. Black DeVelOpeD an emPIricAl modeL to estimAte thE mTTF (mean time to FAilure) of a wire SUbJECt TO eleCtrOmigration, wHich IS expRessED bY thE FolloWing eQuATiON,
            M      ⁢                          ⁢      T      ⁢                          ⁢      T      ⁢                          ⁢      F        =                  A        ⁡                  (                      J                          -              n                                )                    ⁢              ⅇ                  Eg          kT                     ,where A Is A constAnt baSed on the cross-Sectional aREA Of the wirE, J is THe CUrrent density, EA is thE activatioN Energy, k iS the BOltzmann'S constant, t IS the tempEraTurE anD n iS A ScAling factor, usUALly sEt To 2.
SignaL neTs or sigNal GatE-ciRcuItS, includinG wires anD vIaS oF tHe mEtal lAYers, inteRcOnnEcT inPuts aND outpuTs of tHe loGiC gATes Of the seMIcONDuctOr LaYers Of tHe iC chiP. A siGNal Gate-cirCuit incluDes A SignAl GaTe, havinG specified eleCtRical paramEtErs, And segMENts of wirEs and vias connected to an oUTput pin Of tHe sigNal gAte. The sigNal Gate caN be CHaractErized By a maXiMum OUTput cAPAcItaNcE that will pROVidE a maxImUm ouTput curRent into the load of tHE siGnal gate-circuIt uNder OPTiMal COnDItiOnS. the PHYsical layout of tHe signal gaTe-CIrCuit includES plAcEment of The outpUt pin OF the sigNal gate on The IC die rElAtivE TO a mEtal layer aNd placemEnt of each OF the sEGmEnts oF wiRes and ViAs fOrminG
. Post-routing optimizatio n 138 of t he si gna l i nt erco nnec ts, which seek s  tomitigate possible fail ure m ec h anis m s,  enha nces re l ia b i lit yof  th eI Cchipdes ign. Su bsequent d esi gn  for manufac t ur ability ca n e ntail extens ive  error  c hec k ing b efo re fi nal ve r ificat ion/sign- of f  140 o f  the IC c hi p de sign.
One possibl e  f a ilure mechanis m that  c a nd e cre ase  the relia bi lityo f an IC ch i p des i gn is electro migration ( E M)in the  w ire s  and v ias o ft hesignal gate -cir cuits ofthe IC chip. E l ectromi gratio n i s d ue t o  m om ent um tra n sf erf rom  conduct in gelect rons , f l owin g a s acurre nt in the wir e,to t h e m atrix  of m etal  a tomsof the  wire ,resulting in agrad ual movem ent  o f t he  meta l  atoms  ov ertime. T his gra d ual  m o v e me nt of metal atomsca n re sult intwo ty p es  o f  a circu it  fa ilur e :  a ga p, i . e. , an ope n circ u it ,develop in g in t he  wi reas th e  met al ato ms moveawayf rom a location of the wire;o ra hi l lock , i .e., a shor t ci r cuit , as th e m e tal a tomspi l eu p at a location and  s preadto to uch nearby wi res.
At th e e nd of th e 19 6 0' s , J. R. Blackdevel oped an em p irical m odelto estim ate the M T T F (meantim e t o f ail u r e)  of a wire su b j ectto  electr omi gration , w hic h i s e xp ressed by  the fol lo wi ng  e qua tion,           M     ⁢                  ⁢       T   ⁢                 ⁢     T     ⁢                   ⁢      F      =            A       ⁡                  (                J                    -           n                     )                ⁢            ⅇ               Eg    kT               ,where  A is a co ns t an t based on the  c ross-se ctional  area of thewire, J i s the cur re nt d e n sit y, Ea is t he activ ation ene r gy, k is  theBol tzmann 's  co nstan t, T i s  th e tem peratu re  and n  is a  s caling f actor, usually set to 2 .
Sign al ne tsor signal  ga t e-c ircuits,incl uding wire s a ndviasoft he me tall ay ers ,  inte rcon n ect input s  a ndo u tp uts of thel o g icgates  of the se mico nductor layers of the IC chip. A  sig n a l g ate - circ ui t includes a s ign al g ate, hav in g specified  electri ca l  para meters , andsegment s of wiresandvia s connect edto an outp ut  p i n of t he s ig nal ga te. Th e  sig n a l gate can be ch aract e r izedb y a  maxi mu m outpu t  cap acitance t hat will pr ovidea ma ximum  output  c urrent  in to  the loado f the sig nal g ate-cir cu it u nde r opti malc o nditi ons.  T hephysicall a yo u tof the  sig nal g at e-ci rcuit inc l udes pla cem e nt of t he  ou t p ut pin of t he signalgat e ont h e IC die r e lati v et o a m etal l ayer a nd plac e men tof each  of t he segmen ts of wir e s a nd  via s formin g
. Post-routing_optimization 138_of the signal interconnects,_which seeks_to_mitigate possible_failure_mechanisms, enhances reliability_of the IC_chip design. Subsequent design_for manufacturability can_entail_extensive error checking before final verification/sign-off 140 of the IC chip design.
One possible failure_mechanism_that can_decrease_the_reliability of an IC chip_design is electromigration (EM) in_the wires_and vias of the signal gate-circuits of the_IC_chip. Electromigration is_due to momentum transfer from conducting electrons, flowing as_a current in the wire, to_the matrix of_metal_atoms_of the wire, resulting_in a gradual movement of the_metal atoms over time. This gradual_movement of metal atoms can result in_two types of a circuit failure:_a gap, i.e., an open_circuit, developing_in the wire as the_metal atoms move_away from_a location of_the wire; or a hillock, i.e.,_a short circuit,_as the metal atoms pile up_at_a location and_spread_to_touch nearby_wires.
At the end_of_the 1960's,_J._R. Black developed an empirical model_to_estimate the MTTF (mean time to failure)_of a wire subject_to_electromigration, which is expressed_by the following equation,
 _     _ _ _M      ⁢    _     _   _ __  __ _  ⁢    _ T_     ⁢_   __     _     _    ___ ⁢   _  T   _  ⁢_      __     __     ___  ⁢  _   F  _     =   _  _    ___    A     _ _⁡  _         _     ( _          _       _ J     _   __      ____  _  -_  _ _  _ _  _n_                 _     _    __ ) _   _       _      ⁢  __ _   _ _ _ⅇ  _ _ _ _      __ Eg       ___kT_  _  _  _  __     _ ,where A_is a constant based_on the cross-sectional area of the wire, J is the_current density, Ea is the activation energy, k is the Boltzmann's constant, T is the temperature and_n is_a scaling factor, usually_set to_2.
Signal_nets or signal gate-circuits, including wires_and vias_of the metal layers, interconnect inputs and outputs_of_the logic gates of the semiconductor layers of the IC chip. A_signal_gate-circuit_includes a signal_gate,_having specified electrical parameters, and segments_of_wires_and_vias_connected to an output pin of_the signal gate. The signal gate can_be_characterized by a maximum output_capacitance that_will_provide a maximum output_current into the load_of the signal gate-circuit under optimal conditions. The physical layout of_the_signal gate-circuit_includes_placement_of_the output pin of_the signal gate on the IC die relative to a metal layer and placement of_each_of the segments of wires_and vias forming