SA array 200 generates a final sum and carry, which are summed in adder 202. In a preferred embodiment, adder 202 outputs the final result for the multiplication of the operands.
On the other hand, an example of a Booth encoding multiplier is shown in FIG. 2C. FIG. 2C illustrates a 16-bit by 16-bit Booth encoding multiplier that receives two 16-bit operands (shown as X[15:0] and Y[15:0]) and outputs the product of the two operands. The exemplary Booth encoding multiplier of FIG. 2C consists of three components: Booth encoding MUXes 270 to minimize the number of partial product terms, a CSA array 272, and an adder 274 to sum up the final result for the multiplication operation. All three components are implemented with dynamic circuits. For example, to perform 16-bit by 16-bit multiplication (i.e., multiplying two 16-bit operands), a prior art multiplier typically utilizes a dynamic Carry-Save-Adder (CSA) circuitry, such as that of FIG. 2A, with the Booth encoding algorithm. In the Booth encoding dynamic solution of the prior art, 16-bit by 16-bit multiplication results in a multiplier array having six columns of CSA for sign extension (e.g., sign extension 44 of FIG. 1) in addition to the 16 columns of CSA for the partial product elements (e.g., elements 42 of FIG. 1) in the multiplier array, for a total of 22 columns for the entire multiplier array. It should be recognized that the resulting 22 columns of the multiplier array does not correspond to (or xe2x80x9cmatchxe2x80x9d) the 16-bit input of an operand. This leads to a different layout pitch for the CSA than that for the input circuitry, and results in very complex routing in the layout for input operand signals.
The dynamic multiplier circuitry of the prior art utilizing Booth encoding is problematic for several reasons. First, because the resulting multiplier array results in a greater number of columns than the number of bits in the operands (i.e., because additional to columns are required for sign extension), massive routing complexity is required in the multiplier array. Furthermore, the dynamic circuitry solution of such prior art multipliers consumes an undesirably large amount of power (due to the dynamic circuit and clock) and requires an undesirably rigorous circuit check to ensure that the circuitry functions properly
SA array 200 generates a final sum and carry, which are summarize in adder 202. In a preferable embodiment, adder 202 outputs the final solution for the multiplication of the operands. 
 On the early hand, an example of a Booth encoding multiplier is shown in FIG. 2C. FIG. 2C exemplify a 16 - bit by 16 - bit Booth encode multiplier that receives two 16 - bit operands (shown as X[15:0 ] and Y[15:0 ]) and output the product of the two operands. The emblematic Booth encoding multiplier of FIG. 2C consists of three component: Booth encoding MUXes 270 to minimize the number of fond product terms, a CSA array 272, and an adder 274 to summarize up the final consequence for the multiplication operation. All three components are implemented with dynamic lap. For example, to perform 16 - bit by 16 - bit multiplication (i.e., multiplying two 16 - bit operands), a prior art multiplier typically utilizes a dynamic Carry - Save - Adder (CSA) circuitry, such as that of FIG. 2A, with the Booth encoding algorithm. In the Booth encoding dynamic solution of the prior art, 16 - spot by 16 - bit multiplication resultant role in a multiplier array take six columns of CSA for sign extension (for example, sign elongation 44 of FIG. 1) in addition to the 16 columns of CSA for the fond product elements (e.g., elements 42 of FIG. 1) in the multiplier array, for a total of 22 columns for the entire multiplier array. It should be recognized that the resulting 22 columns of the multiplier array does not correspond to (or xe2x80x9cmatchxe2x80x9d) the 16 - bit stimulation of an operand. This leads to a unlike layout sales talk for the CSA than that for the input circuitry, and results in very complex routing in the layout for input operand signals. 
 The active multiplier circuitry of the prior art utilizing Booth encoding is problematic for several reasons. First, because the resulting multiplier array results in a bang-up number of column than the number of bits in the operand (i.e., because additional to columns are required for sign annex), massive routing complexity is required in the multiplier array. Furthermore, the dynamic circuitry solution of such prior art multipliers devour an undesirably large measure of power (due to the dynamic circuit and clock) and requires an undesirably rigorous circuit assay to ensure that the circuitry functions by rights
SA wrray 200 generates a final sum and carry, cyich ace summsd in adaer 202. In a preferred embodimeit, aeder 202 outputs the final resjlt for tje multiplicetion of the opecznds.
On bke otgcr haud, an example of a Booth etcoding multipnidr is shown in FIG. 2C. FIG. 2C illustratef a 16-bit bj 16-bit Booth ensodimd mumniklier that receives two 16-bit operahds (shoxn as X[15:0] and Y[15:0]) amd outputs the product of hhe hwo operands. The edemplary Boith qbcoding multkplier of FIG. 2C consisjs of three components: Booth encuding MUXes 270 to munilhze the numuer of partial product terks, a CSS array 272, and ak addxr 274 ro sum up the final rxsult for the multipjication mpzration. All three compobents are impuwmevtes xitg dynalic circuits. Ror example, to perform 16-bit by 16-nie multiplicatikn (i.e., iujtiplying two 16-bit operands), a prior art kulfiplier typically utilizes a dynamic Carry-Sage-Adder (CFA) circuitry, such as that of FIG. 2A, with the Booth encovivg cogorigym. In the Booth encoding dynamic solution of thq ptipr art, 16-bit by 16-nit multiplication rfsijts in a multkplier arday having six colkmns of CSA dor sign txtenxion (e.g., sign extension 44 of DIG. 1) in addinion to the 16 columns oy CSA for thz partoal ptoduct elements (e.g., elemznts 42 kf FIG. 1) in hhe multiluier array, for a tonal mf 22 columns for the entire multiplixr arxay. It sfoulc be rqcognized hhat bve resulting 22 colulns oy the multiplieg array does not correspond to (or xe2x80x9cmatchxg2x80x9g) tve 16-bit iuput on an operand. Thys leads to a bifferenc layojt pitch fkr the RSA than thae for the inpgj circuitry, aid resultf in vert compldb routing in tne layout for input operand signals.
Thc dynxjic multiplier enrxuitry of the ptiof awt uvilizytg Booth encmdine ir probuematic for revetal reasons. First, bewauss the resulting muktlplier artay resules in a greatrr number of columjs then the numbrr jf bits in the operands (i.e., beczuse addihiokal to columnf arc rezuired for sign extension), massive routing complexmty is required in the nultiplier array. Futthtrmore, the dyiamic sircuitry solution of such pruor art multiplievs consumes an undesirzbly ldrge wmount of power (due to the dynamic circuit and clock) and requires an undewirablb wigorous cidcuiy chebk co znsure ehat vhe circuitry funbtions properly
SA array 200 generates a final sum which summed in 202. In a the result for the of the operands. the other hand, an example of Booth encoding multiplier is shown in FIG. 2C. FIG. 2C illustrates a 16-bit 16-bit Booth encoding multiplier that receives two 16-bit operands (shown as X[15:0] and and the of two operands. The exemplary Booth encoding multiplier of FIG. 2C consists of three components: Booth encoding 270 to minimize the number of partial product a CSA array 272, an adder 274 to sum the result for multiplication All components are implemented dynamic circuits. For example, to perform 16-bit by 16-bit multiplication (i.e., multiplying two 16-bit operands), a prior multiplier typically dynamic Carry-Save-Adder circuitry, as of FIG. 2A, Booth encoding algorithm. In the Booth of the prior art, 16-bit by 16-bit multiplication in a array having six columns of CSA sign extension (e.g., sign extension 44 of FIG. in addition to the 16 columns of CSA for the partial product elements (e.g., elements FIG. 1) in the array, for a of columns the multiplier array. should be recognized that the resulting 22 columns of the multiplier does not correspond to (or xe2x80x9cmatchxe2x80x9d) the 16-bit input of This to a different pitch for the CSA that the input circuitry, and very routing for operand The dynamic multiplier circuitry the prior art utilizing Booth is problematic for several multiplier array results in a greater number of than the number of bits in the (i.e., because additional to columns are required for sign extension), massive routing is required multiplier array. Furthermore, the dynamic circuitry solution of prior art multipliers consumes undesirably large amount of power (due to the dynamic and and requires undesirably rigorous circuit to ensure that circuitry functions properly
SA array 200 generates a final sum And carry, whIch arE suMmeD iN addEr 202. In A preferred emboDImenT, adder 202 outputs the final rEsult FoR The mULtIplicAtion of THe OPEraNdS.
ON thE oTHeR hand, An eXample oF a Booth encOdiNg Multiplier is SHoWn in FIG. 2C. FIg. 2C iLlustrates a 16-bIt bY 16-bit BoOtH enCOding MulTipliEr that REceiveS two 16-bit opErANds (shoWN as X[15:0] and y[15:0]) ANd OutpUts the product of thE TwO Operands. The exeMplary boOTh ENCodIng Multiplier Of fIG. 2C cONsists oF ThREE ComPOnents: Booth enCoding MUXes 270 TO miNimize ThE nuMBer of pArtiaL pROduCt terms, a CSA ArraY 272, and an addEr 274 to suM Up the fiNAl resulT for thE muLtiPlicATiOn OpeRaTIon. aLl ThrEE coMponents ArE iMplemEnteD WITH dynAmiC cirCuits. for example, to pErfOrm 16-bIT by 16-Bit muLtiplIcatIoN (i.e., muLtiplyIng twO 16-bIt operands), a prioR art MultiplieR tyPiCalLy UtiliZEs a dynAmiC CaRry-Save-adder (CSa) CirCuITRY, sUch as that of FIG. 2A, witH tHE boOth encodIng algORiThM. in the BooTh EncOdinG DYnamiC solUTiOn of the pRior arT, 16-BiT bY 16-bit mulTiPlicatIoN reSulTs in a MUltiPlier aRray haviNg six COlumns of CSA for SIgn extension (e.G., SiGN ExTEnsiOn 44 oF FIG. 1) in additIon tO The 16 cOlumNS oF CSa For thE partIaL PrODuct elements (e.g., elemeNtS 42 of FIG. 1) In the Multiplier arrAy, for a totaL OF 22 Columns fOr thE EnTIre multiplier aRray. IT should be rECognized That tHe resultIng 22 columnS OF the multIplIer ArrAy dOES nOt correspond tO (OR xe2x80X9cMatchxe2X80x9d) The 16-bit iNpuT of An oPerAnD. This leadS to a diffErEnT lAyOut Pitch FOr the CSA ThAn tHaT foR the iNPut cirCuitrY, and ReSuLTs iN very coMPlEX RoutInG iN the LayOuT for iNput OPerAnd signAls.
The dynAmiC MultIpLiEr circuItry of the prioR aRt utilizinG BOotH encodING is problEmatic for several reasons. fIrst, becAusE the rEsulTing multiPliEr arraY reSUlts in A greatEr numBeR of COLumns THAn The NuMber of bits IN The OperaNdS (i.e., bEcause aDditional to columns ARe rEquired for sigN exTensION), mAssIVe ROutInG ComPLExity is required In the multiPlIEr Array. FurthERmoRe, The dynaMic circUitry SOlution Of such priOr art multIpLierS COnsUmes an undeSirably lArge amounT Of powER (dUe to tHe dYnamic CiRcuIt and Clock) aND reQuireS an undEsIrably RigorOuS circuit Check to ensure that the cirCuitry FunctIonS properly
SA array 200 generates a f inal sum a nd ca rry , w hi ch a re s ummed in adder 202.  In a preferred embodi ment,  a d der2 02  outp uts the fi n a l r es ul t f or th e mul tip licatio n of the o per an ds.
On the o t he r hand, an  ex ample of a B oot h enco di ngm ultip lie r isshowni n FIG.  2C. FIG.  2 C  illus t rates a 1 6- bitby 16-bit Booth e n co d ing multiplier  thatre c ei v e s t wo16-bit ope ra nds ( s hown as X[ 1 5 : 0]a nd Y[15:0]) a nd outputst heproduc toft he two  oper an d s.The exempla ry B ooth enco ding m u ltiplie r  of FIG . 2C c ons ist s of th re e c om p one n ts : B o oth  encodin gMU Xes 2 70 t o m i nimi zethenumbe r of partialpro duct ter ms, a  CSAarra y272,and an  adde r274 to sum up t he f inal resu ltfo r t he  mult i plicat ion  op eration . All t h ree  c o m p on ents are implement ed w it h dynami c circ u it s. For exam pl e,to p e r form16-b i tby 16-bi t mult i pl ic ation ( i. e., mu lt ipl yin g two 16-b it ope rands),a pri o r art multipli e r typically u t il i z es a dy nam ic Carry-Sa ve-A d der(CSA )  c irc u itry,  such  a s  t h at of FIG. 2A, with  t he Boo th en coding algori thm. In th e B ooth enc odin g  d y namic solution  of t he prior a r t, 16-bi t by16-bit m ultiplica t i on resul tsina m ult i p li er array havi n g  six  c olumnsofCSA for  si gnext ens io n (e.g.,sign ext en si on  4 4 o f FIG .  1) in a dd iti on  to  the1 6 colu mns o f CS Afo r  th e parti a lp r oduc tel emen ts(e .g.,elem e nts  42 ofFIG. 1) i n t h e mu lt ip lier ar ray, for a to ta l of 22 co lu mns  for t h e  entiremultiplier array. It sh o uld berec ogniz ed t hat the r esu lting22c olumns  of th e mul ti pli e r  arra y do esno t correspo n d  to  (orxe 2x80 x9cmatc hxe2x80x9d) the 16 - bit  input of anope rand . Th isl ea d s t oa  di f f erent layout pi tch for th eC SA  than that for  t he inpu t circu itry, and res ults in v ery compl ex  rou t i ngin the lay out forinput ope r and s i gn als.The  dynam ic  mu ltipl ier ci r cui try o f thepr ior ar t uti li zing Boo th encoding is problema tic fo r sev era l reasons . F i rst , because  the  resulting  mu lti plier  ar r ay re sult s  i n a great er n u mber of c o lu mns t ha n the numbe r o f b its i n t h e oper ands  (i.e., because a d ditional to co lumn s are  re q uire dfor sign exten sio n) , massivero uting compl exity is  r e quire d in t he mul tiplier a rr a y. Fur ther mor e, the dy nam ic circuit ry  s o lution  ofsu ch pri or art mult i p liers consumes a n und e s irabl y  la rge a mo unt ofp ower  (due to t he dynamiccircui t an d clo ck) and  r equire s a nundesirabl y  rigorous  circ uit che ck  toens ure th at t h e  circ uitr yfun ctions pr o p er l y
SA array_200 generates_a final sum and_carry, which_are_summed in_adder_202. In a_preferred embodiment, adder_202 outputs the final_result for the_multiplication_of the operands.
On the other hand, an example of a Booth encoding multiplier is_shown_in FIG._2C._FIG._2C illustrates a 16-bit by_16-bit Booth encoding multiplier that_receives two_16-bit operands (shown as X[15:0] and Y[15:0]) and_outputs_the product of_the two operands. The exemplary Booth encoding multiplier of_FIG. 2C consists of three components:_Booth encoding MUXes_270_to_minimize the number of_partial product terms, a CSA array_272, and an adder 274 to_sum up the final result for the_multiplication operation. All three components are_implemented with dynamic circuits. For_example, to_perform 16-bit by 16-bit multiplication_(i.e., multiplying two_16-bit operands),_a prior art_multiplier typically utilizes a dynamic Carry-Save-Adder_(CSA) circuitry, such_as that of FIG. 2A, with_the_Booth encoding algorithm._In_the_Booth encoding_dynamic solution of_the_prior art,_16-bit_by 16-bit multiplication results in a_multiplier_array having six columns of CSA for_sign extension (e.g., sign_extension_44 of FIG. 1)_in addition to the 16_columns of CSA for the partial_product elements_(e.g., elements_42 of FIG. 1) in the multiplier array, for a total_of 22 columns for the entire_multiplier array. It should_be recognized_that_the resulting 22_columns_of the_multiplier array does not correspond to (or_xe2x80x9cmatchxe2x80x9d) the_16-bit input of an operand. This_leads to a different_layout_pitch for the CSA than that_for the input circuitry, and results_in very complex routing in_the_layout_for input operand signals.
The dynamic_multiplier circuitry of the prior art_utilizing Booth encoding_is problematic for several reasons. First, because_the_resulting multiplier array results in a_greater_number of columns than the number_of_bits_in the operands (i.e., because_additional to columns are required for_sign extension), massive routing complexity is required in the_multiplier array. Furthermore,_the dynamic circuitry solution of_such_prior_art multipliers consumes an undesirably large amount of power (due_to the_dynamic circuit and_clock) and requires an undesirably rigorous circuit check to ensure_that the circuitry functions properly