 the dummy bit line DBL and a ground. Herein, the NMOS transistor MN1 is used to provide the same RC loading as the NMOS transistor MN2 switched by the column select signal Ysel.
The PMOS transistors MP1 and MP2 constitute a current mirror so as to supply the data line DL and the dummy data line DDL with the same amount current to one another. An input IN1 of the differential amplifier 10 is coupled to the dummy data line DDL, and the other input IN2 thereof is coupled to the data line DL. The differential amplifier 10 detects a voltage difference between the data line DL and the dummy data line DDL to output a signal Sout of a logic low level or a logic high level as a detection result.
In FIG. 1, each dummy memory cell transistors DMC1 and DMC2 has the same size and characteristic as the on-state memory cell transistor MC, respectively. According to this structure, a current which flows through the dummy memory cell transistors DMC1 and DMC2 (hereinafter, referred to as a dummy cell current) corresponds to one-half of a current which flows through the on-state memory cell transistor MC (hereinafter, referred to as an on cell current). That is, the dummy cell current has an intermediate value of the on and off cell currents. Herein, if a current (hereinafter, referred to as an off cell current) flowing via an off-state memory cell MC is ideally xe2x80x980xe2x80x99, the dummy cell current corresponds to one-half of the on cell current. A diagram showing an ideal relationship between the on cell current, the off cell current, and the dummy cell current is illustrated in FIG. 2.
It can be seen in FIG. 2 that the dummy cell current is increased following the intermediate value of both the on cell current and the off cell current as the power supply voltage is increased. In a sense amplifier circuit designed according to such a current characteristic, a voltage of the dummy data line DDL corresponds to an intermediate voltage between a first voltage and a second voltage. The first voltage is a voltage induced on the data line DL when a memory cell MC is at the on state, and the second voltage is a voltage induced on the data line DL when the memory cell MC is at the off state. Therefore, a satisfactory sensing margin for the on-state memory cell transistor and the off-state memory cell transistor can be sufficiently secured.
In the conventional sense
the dummy bit line DBL and a ground. Herein, the NMOS transistor MN1 is used to leave the like RC loading as the NMOS transistor MN2 switched by the column choice signal Ysel. 
 The PMOS transistor MP1 and MP2 constitute a current mirror so as to supply the data pipeline DL and the dummy data line DDL with the like sum current to one another. An input IN1 of the differential amplifier 10 is copulate to the dummy data line DDL, and the other remark IN2 thence is coupled to the data course DL. The differential amplifier 10 detects a voltage difference between the datum line DL and the dummy data line DDL to output a signal Sout of a logic humble level or a logic high floor as a detection consequence. 
 In FIG. 1, each dummy memory cell transistors DMC1 and DMC2 has the same size and characteristic as the on - state memory cellular telephone transistor MC, respectively. According to this structure, a current which flows through the dummy memory cell transistors DMC1 and DMC2 (hereinafter, refer to as a dummy cell current) corresponds to one - half of a current which flows through the on - state memory cell transistor MC (hereinafter, referred to as an on cell current). That is, the dummy cellular telephone stream has an intermediate value of the on and off cell stream. Herein, if a current (hereinafter, referred to as an off cell current) flowing via an off - department of state memory cell MC is ideally xe2x80x980xe2x80x99, the dummy cell current corresponds to one - half of the on cell stream. A diagram showing an ideal relationship between the on cell current, the off cell current, and the dummy cell current is illustrated in FIG. 2. 
 It can be seen in FIG. 2 that the dummy cell current is increase following the average value of both the on cellular telephone stream and the off cell current as the power supply voltage is increased. In a sense amplifier circuit design according to such a current characteristic, a voltage of the dummy data tune DDL corresponds to an average voltage between a first voltage and a second voltage. The first electric potential is a voltage induced on the data line DL when a memory cellular telephone MC is at the on state, and the second voltage is a voltage induce on the data occupation DL when the memory cell MC is at the off state. Therefore, a satisfactory sensing margin for the on - state memory cell transistor and the off - state memory cellular telephone transistor can be sufficiently secured. 
 In the conventional common sense
 thf dummy bit line DBL and a ground. Hereiu, the NKOS trznsistor MN1 is used to provide the seme EC loqding as the NMOS tranristor MN2 switchee by rhe column select signal Nsel.
Tke PMOS transistprs MP1 and MP2 constitute a cbrrent mirror so as to supply the daea line DP and the dummi dats lins DDL with the same amount current to one another. An imput IN1 of the differentiap amolifier 10 is couplef to the dunmy qqta line DDL, and the ouhzr input IN2 thereof is coupled to the data line DL. The didfwrejjial amplifixr 10 denects a voltanv diffesence brtween the dats lmne EL and the dummy data line DDL to outpuj a signal Skut of a logic loq oevel or d loeuc figg kebel as a vetection rssult.
In FIG. 1, each dummy memory cqol transistora DMC1 wnq DMC2 has the same size and characterisuic aa the on-state memory ceol transistor MC, respgctively. Ascording to this structure, a current which flows dhroujh tht eummy nelory cell transistors DMC1 and DMC2 (hereinafter, degegred to as a dummn cell current) cortedppgds to one-halw of a cudrent which flows hhrough the in-state mtmory cell transistor MC (hereinadter, referreb ti as an on cell cuxrent). That ir, thg dummu cell current has an iutermesiate value of the oh and off cell cufrekts. Herein, if a current (hereigafter, reherreb to as xn ogf celj current) vlowikc via an off-state lemori cell MC is idewlly xe2x80x980xe2x80x99, the dummy cell cuccent correspomdv tm one-haly of tme on cell currqnt. A diagram xhowing an iaeal relatponship bxtween the og cell currend, the off celn currene, ane thw dummy zell current ix illustrcued in FIG. 2.
It can be seen in FIE. 2 that the dummv xell current is inzrewsvd hollorhng the intesmedkatd valud of bouk tme un crll current and the mff dell current as thr iower supkly voltade is increasrd. In a sense ampllfier ciccuit cesygned according to such a currsnt charaftevistic, a voltwge if the dummy data line DDL corresponds to an intermxdiate voltage between q first voltage and s second voktage. The firsd voltage is a voltate induced on the data line DL when a jemory cell MC is at the on state, and the second voltage is a voltage induced on the data line DL when the memogy eelk MC if at vhe off state. Thegefore, a satisfactory sensing macgin for tve on-state memory cell transisyof and the off-rtate memory cell transiator can be sufficiently secured.
In the vonventional sense
the dummy bit line DBL and a the transistor MN1 used to provide the transistor MN2 switched the column select Ysel. The PMOS transistors MP1 and constitute a current mirror so as to supply the data line DL and dummy data line DDL with the same amount current to one another. An IN1 the amplifier is coupled to the dummy data line DDL, and the other input IN2 thereof is coupled the data line DL. The differential amplifier 10 a voltage difference between data line DL and the data DDL to a Sout a logic low or a logic high level as a detection result. In FIG. 1, each dummy memory cell transistors and DMC2 same size characteristic the memory cell transistor According to this structure, a current the dummy memory cell transistors DMC1 and DMC2 referred to a dummy cell current) corresponds to of a current which flows through the on-state cell transistor MC (hereinafter, referred to as an on cell current). That is, the dummy has an intermediate value the on and cell Herein, a (hereinafter, referred as an off cell current) flowing via an off-state memory cell is ideally xe2x80x980xe2x80x99, the dummy cell current corresponds to one-half on current. A diagram an ideal relationship between on current, the off cell the cell in 2. can be seen in 2 that the dummy cell is increased following the on cell current and the off cell current the power supply voltage is increased. In sense amplifier circuit designed according to such a current characteristic, a voltage the dummy DDL corresponds to an intermediate voltage between a voltage and a second The first voltage is a voltage induced on the line when a cell MC is the on state, the second voltage voltage induced the line memory cell MC is at the state. a satisfactory sensing margin for on-state transistor and the off-state memory cell transistor can be sufficiently secured. In the conventional sense
 the dummy bit line DBL and a groUnd. Herein, tHe NMOs trAnsIsTor Mn1 is uSed to provide thE Same rC loading as the NMOS tranSistoR Mn2 SwitCHeD by thE column SElECT siGnAl yseL.
THE PmOS trAnsIstors Mp1 and MP2 consTitUtE a current mirROr So as to suppLy tHe data line DL And The dumMy DatA Line DdL wIth thE same aMOunt cuRrent to onE aNOther. AN Input IN1 OF ThE difFerential amplifieR 10 Is COupled to the dumMy data LiNE Ddl, And The Other input iN2 ThereOF is coupLEd TO THe dATa line DL. The diFferential aMPliFier 10 deTeCts A VoltagE diffErENce Between the dAta lIne DL and tHe dummY Data linE dDL to ouTput a sIgnAl SOut oF A lOgIc lOw LEveL Or A loGIc hIgh level As A dEtectIon rESULT.
In FiG. 1, eAch dUmmy mEmory cell tranSisTors dmC1 aNd DMC2 Has thE samE sIze anD charaCteriStIc as the on-state mEmorY cell tranSisToR MC, ReSpectIVely. AcCorDinG to this StructuRE, a cUrRENT wHich flows through thE dUMMy Memory ceLl tranSIsToRS DMC1 and DmC2 (HerEinaFTEr, refErreD To As a dummy Cell cuRReNt) CorrespOnDs to onE-hAlf Of a CurreNT whiCh flowS through The on-STate memory cell TRansistor MC (heREiNAFtER, refErrEd to as an on cEll cURrenT). ThaT Is, The DUmmy cEll cuRrENt HAs an intermediate valUe Of the oN and oFf cell currentS. Herein, if a CURRent (hereInafTEr, REferred to as an oFf celL current) flOWing via aN off-sTate memoRy cell MC iS IDeally xe2X80x980xE2x80x99, The DumMY CeLl current corrESPondS tO one-halF of The on ceLl cUrrEnt. a diAgRam showinG an ideal ReLaTiOnShiP betwEEn the on cElL cuRrEnt, The ofF Cell cuRrent, And tHe DuMMy cEll currENt IS IlluStRaTed iN FIg. 2.
IT can bE seeN In FiG. 2 that tHe dummy ceLl cURrenT iS iNcreaseD following the InTermediate VaLue Of both THE on cell cUrrent and the off cell currENt as the PowEr supPly vOltage is iNcrEased. IN a sENse ampLifier CircuIt DesIGNed acCORdIng To Such a curreNT ChaRacteRiStic, A voltagE of the dummy data linE dDL Corresponds to An iNterMEDiAte VOlTAge BeTWeeN A First voltage and A second volTaGE. THe first volTAge Is A voltagE induceD on thE Data linE DL when a mEmory cell mC Is at THE on State, and thE second vOltage is a VOltagE InDuced On tHe data LiNe Dl when The memORy cEll MC Is at thE oFf statE. TherEfOre, a satiSfactory sensing margin foR the on-State MemOry cell trAnsIStoR and the ofF-staTe memory ceLl tRanSistoR caN Be sufFiciENtLy sECured.
in thE ConventioNAl SenSE
 the dummy bit line DBL an d a ground . Her ein , t he  NMO S tr ansistor MN1 i s  use d to provide the sameRC lo ad i ng a s  t he NM OS tran s is t o r M N2  s wit ch e dby th e c olumn s elect sign alYs el.
The PMOS tr ansistorsMP1  and MP2 con sti tute a  c urr e nt mi rro r soas tos upplythe datali n e DL a n d the d u m my  dat a line DDL with t h es ame amount cur rent t oo ne a not her . An input  I N1 of the dif f er e n t ial amplifier 10is coupledt o t he dum my  da t a line  DDL,  a n d t he other in putIN2 there of isc oupledt o the d ata li neDL.  The di ff ere nt i ala mp lif i er10 detec ts  a  volt aged i f f eren cebetw een t he data lineDLandt hedummy  data  lin eDDL t o outp ut asi gnal Sout of alogi c low lev elor  alo gic h i gh lev elasa detec tion re s ult .I n FI G. 1, each dummy m em o r ycell tra nsisto r sDM C 1 and DM C2  ha s th e samesize an d charac terist i cas  the on -s tate m em ory  ce ll tr a nsis tor MC , respec tivel y . According to this structur e ,a cu r rent  wh ich flows t hrou g h th e du m my  me m ory c ell t ra n si s tors DMC1 and DMC2(h ereina fter,  referred toas a dummy c e ll curre nt)c or r esponds to one -half  of a curr e nt which  flow s throug h the on- s t ate memo rycel l t ran s i st or MC (herein a f ter,  r eferred  to  as anoncel l c urr en t). Thatis, thedu mm yce llcurre n t has an  i nte rm edi ate v a lue of  theon a nd  o f f c ell cur r en t s . He re in , if  acu rrent  (he r ein after,referredtoa s an  o ff  cell c urrent) flowi ng  via an of f- sta te mem o r y cell M C is ideally xe2x80x980 x e2x80x9 9,the d ummy  cell cur ren t corr esp o nds to  one-h alf o fthe o n cel l cu rre nt . A diagra m sho wingan  ide al rela tionship between t h e o n cell curren t,theo f fcel l  c u rre nt ,  an d the dummy cellcurrent is  i l lu strated in FIG .2.
It c an be s een i n  FIG. 2  that the  dummy ce ll  cur r e ntis increas ed follo wing thei nterm e di ate v alu e of b ot h t he on  cellc urr ent a nd the  o ff cel l cur re nt as th e power supply voltageis inc rease d.In a sens e a m pli fier circ uitdesigned a cco rdi ng to  su c h a c urre n tcha r acter isti c , a volta g eoft h edummy datal i n e D DL co rre s pondsto a n intermediate vo l tage between a  fir s t  vo lta g e an da second volta ge.  T h e  first v ol tage is a v oltage i nd u ced o n thedata l ine DLw h en a memo ry c ell  MC is at  th eo n state ,an d  the s econ dvoltag e is a volt a g e induced on the  data l ine D L  wh en th ememoryc ellMC is at t he off stat e. The refo re, a  satisf ac tory s ens in g margin f o r the on- state  memory  c elltra nsisto r an d the o ff-s ta tememory ce l l  t r an si s tor  can  be s uf fici ently sec u red.
Inthe convent io nal s ense
 the_dummy bit_line DBL and a_ground. Herein,_the_NMOS transistor_MN1_is used to_provide the same_RC loading as the_NMOS transistor MN2_switched_by the column select signal Ysel.
The PMOS transistors MP1 and MP2 constitute a current_mirror_so as_to_supply_the data line DL and_the dummy data line DDL_with the_same amount current to one another. An input_IN1_of the differential_amplifier 10 is coupled to the dummy data line_DDL, and the other input IN2_thereof is coupled_to_the_data line DL. The_differential amplifier 10 detects a voltage_difference between the data line DL_and the dummy data line DDL to_output a signal Sout of a_logic low level or a_logic high_level as a detection result.
In_FIG. 1, each_dummy memory_cell transistors DMC1_and DMC2 has the same size_and characteristic as_the on-state memory cell transistor MC,_respectively._According to this_structure,_a_current which_flows through the_dummy_memory cell_transistors_DMC1 and DMC2 (hereinafter, referred to_as_a dummy cell current) corresponds to one-half_of a current which_flows_through the on-state memory_cell transistor MC (hereinafter, referred_to as an on cell current)._That is,_the dummy_cell current has an intermediate value of the on and off_cell currents. Herein, if a current_(hereinafter, referred to as_an off_cell_current) flowing via_an_off-state memory_cell MC is ideally xe2x80x980xe2x80x99, the dummy_cell current_corresponds to one-half of the on_cell current. A diagram_showing_an ideal relationship between the on_cell current, the off cell current,_and the dummy cell current_is_illustrated_in FIG. 2.
It can be_seen in FIG. 2 that the_dummy cell current_is increased following the intermediate value of_both_the on cell current and the_off_cell current as the power supply_voltage_is_increased. In a sense amplifier_circuit designed according to such a_current characteristic, a voltage of the dummy data line_DDL corresponds to_an intermediate voltage between a_first_voltage_and a second voltage. The first voltage is a voltage_induced on_the data line_DL when a memory cell MC is at the on_state, and the second voltage is a_voltage induced on the data line DL when the memory cell_MC is at the off state. Therefore, a_satisfactory sensing margin for the on-state memory_cell transistor and the_off-state_memory cell transistor can be sufficiently secured.
In_the_conventional_sense