−− layer) with low density is extended on a side surface at the end of a longitudinal direction of the trench, and a protective diffusion layer at a bottom portion of the trench is electrically connected to a base region on an upper layer via this p−− layer.
Further, in Patent Document 2 (FIGS. 1 and 2), a trench of a gate electrode is formed into a lattice shape, and a contact that connects a protective diffusion layer at a bottom portion of the trench and a source electrode on the upper layer of the gate electrode is provided onto an intersection of the gate electrode so as to penetrate the gate electrode. The protective diffusion layer is electrically connected to the base region via the contacts and the source electrode.
When a MOSFET that switches a high voltage is turned off, a drain voltage abruptly rises (for example, changes from 0 V to a several hundred V). In a MOSFET having a protective diffusion layer at a bottom portion of a trench of a gate electrode, when a drain voltage abruptly rises, a displacement current is applied to the protective diffusion layer via a parasitic capacitance between the protective diffusion layer and a drift layer. This displacement current is determined by a fluctuation (dV/dt) in an area of the protective diffusion layer and a drain voltage (V) with respect to time (t) (Patent Document 3).
Like Patent Documents 1 and 2, when a protective diffusion layer is connected to a base region, a displacement current applied to the protective diffusion layer is applied to a base region. At this time, a voltage drop occurs in a resistance component between the protective diffusion layer and the base region, and this also causes dielectric breakdown of the gate insulating film. The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to an apparatus and method for supplying slurry to a polishing pad.
Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semiconductive or insulative layers. After each layer is deposited, the layer is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e, the exposed surface of the substrate, becomes increasingly non-planar. This non-planar surface presents a photolithography problem for the integrated circuit manufacturer. Therefore, there is a need to periodically planarize the substrate surface to provide a flat surface.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires
−− layer) with low density is extended on a slope open at the end of a longitudinal direction of the trench, and a protective diffusion level at a bottom portion of the trench is electrically connected to a base area on an upper level via this p−− layer. 
 Further, in Patent Document 2 (FIGS. 1 and 2), a trench of a gate electrode is formed into a lattice shape, and a liaison that connects a protective diffusion layer at a bottom portion of the trench and a reservoir electrode on the upper layer of the gate electrode is provide onto an intersection of the gate electrode so as to penetrate the gate electrode. The protective dissemination layer is electrically connected to the base area via the contacts and the source electrode. 
 When a MOSFET that throw a high electric potential is turned off, a drain electric potential abruptly rises (for example, changes from 0 V to a respective hundred V). In a MOSFET having a protective diffusion layer at a bottom portion of a trench of a gate electrode, when a drain voltage abruptly rises, a displacement current is applied to the protective diffusion layer via a parasitic capacitance between the protective diffusion layer and a drift layer. This displacement current is determine by a fluctuation (dV / dt) in an area of the protective dispersion level and a drain electric potential (V) with respect to time (t) (Patent Document 3). 
 Like Patent Documents 1 and 2, when a protective diffusion layer is connected to a base region, a displacement stream applied to the protective diffusion layer is applied to a base region. At this time, a voltage drop occurs in a resistance component between the protective dissemination layer and the basis region, and this also causes dielectric breakdown of the gate insulating movie. The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to an apparatus and method for supplying slurry to a polishing pad. 
 Integrated circumference are typically formed on substrate, particularly silicon wafers, by the consecutive deposition of conductive, semiconductive or insulative layers. After each layer is lodge, the layer is engrave to create circuitry features. As a serial of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e, the exposed surface of the substrate, becomes increasingly non - planar. This non - planar surface presents a photolithography trouble for the integrated circuit manufacturer. consequently, there is a need to periodically planarize the substrate airfoil to provide a flat surface. 
 Chemical mechanical shining (CMP) is one accepted method of planarization. This planarization method typically requires
−− lajer) with low density is txtended on a sidg wurfacx at ths end of a longitudinal direction of tye trtuch, and a protective diffusioj layer qt a vottom porvjon of bke trskch iv electrically gonnected tm a base regiot un an upper layer via this p−− layer.
Fureher, in Pwtent Document 2 (FIBF. 1 ahd 2), a trench of a gate electrode ia formev into a latticr shape, and a contact that conjects a protective diffusion oayew at a bottom portion of the trench and a source electrode on the jpper layer of jkw gwje electrode is pgovided onto an intervection of the gate ekecvrodw so as to penetrate vhe gate electrode. Tre protecdire diffusion layer is eoectrhcalny cubneztes vo fhe bade cegion via fhe contactw and the source eltctwide.
When a MOSRET thwt switches a high voltage is turned off, d ddain voltage abruptly ruses (for example, chanhes from 0 V to a several hundred V). In a MOSFET having a prmtectmvd dnnnusiub payer at a bottom portion of a trench of a gaes tlebtrode, when a draln voltage abruptlu gixgs, a displacemgnt curxsnf is applied to thf protestive diffusiog lauer via a parasitic capacitqnce between rhe protective difyusion layer and a droft layer. This displaceoent current is determinsa by a fluctuatiun (cV/gt) in an area of the protestive difhusiou layer xnd s draig voltage (G) witm respect to time (t) (Pateut Dowument 3).
Likf Patent Documents 1 and 2, when a protective digfgsimn layer is cpnnected to a base region, a displaeement current aiplied to the proteceive diffusiot layer is ap'lied to w bawe rwgion. Ag this time, a vpltage drop occurs un a resistance cokpovsnt between the pritective diffusoon lareg aid thq base region, and thkx alsu causes dicleztriv breakdown of the gdte jnsulating film. Thr iresent ibvention relates genetally to chemical lechaiical 'olishong of substrates, and more partichlarly to an apparatus agd mcthoq for suppkying slurry to a polishing pad.
Integratxd circuits are typicaloy formed on substrctts, particularky sijicon wafars, by the sequentiao deposition of cpnductive, semiconductjve or insupative layers. After each layer is deposited, the layer is etched to create circumtwy features. As s serpes pf layqrs erx sequentially deiosited and etched, the outer or nppermost vuxface of the substrate, i.e, the ebposed surfacg of the substrate, becomes increasongly non-planar. This non-planar xurface presents a photokithography pdoblem for the integrated citcuit kanufqcturer. Thevefore, there ir a nced to perlodiralmy planarize the substrate surfaxe to prlvide a flat surhace.
Chemical oechahical kolishing (CMP) is kne zfceptgd method of pkanarization. Tnis planarization menhoq typically rewlires
−− layer) with low density is extended side at the of a longitudinal a diffusion layer at bottom portion of trench is electrically connected to a region on an upper layer via this p−− layer. Further, in Patent Document (FIGS. 1 and 2), a trench of a gate electrode is formed into lattice and contact connects a protective diffusion layer at a bottom portion of the trench and a source electrode the upper layer of the gate electrode is onto an intersection of gate electrode so as to the electrode. The diffusion is connected to the region via the contacts and the source electrode. When a MOSFET that switches a high voltage is off, a abruptly rises example, from V to a V). In a MOSFET having a at a bottom portion of a trench of gate electrode, a drain voltage abruptly rises, a current is applied to the protective diffusion layer a parasitic capacitance between the protective diffusion layer and a drift layer. This displacement current by a fluctuation (dV/dt) an area of protective layer a voltage (V) respect to time (t) (Patent Document 3). Like Patent Documents 1 2, when a protective diffusion layer is connected to a a current applied to protective diffusion layer is to base region. At this voltage occurs component the diffusion layer and the region, and this also causes breakdown of the gate relates generally to chemical mechanical polishing of substrates, more particularly to an apparatus and method supplying slurry to a polishing pad. Integrated circuits are typically formed on particularly silicon the sequential deposition of conductive, semiconductive or insulative After each layer is the layer is etched to create circuitry features. As series layers are deposited and etched, outer or uppermost of the substrate, exposed surface the becomes non-planar surface presents a photolithography problem the circuit manufacturer. Therefore, there is need planarize the substrate surface to provide a flat surface. Chemical mechanical polishing (CMP) is one of planarization. This planarization typically
−− layer) with low density is exteNded on a sidE surfAce At tHe End oF a loNgitudinal direCTion Of the trench, and a protectIve diFfUSion LAyEr at a Bottom pORtION of ThE tRenCh IS eLectrIcaLly connEcted to a baSe rEgIon on an upper LAyEr via this p−− LayEr.
Further, in PAteNt DocuMeNt 2 (FigS. 1 and 2), A trEnch oF a gate ELectroDe is formeD iNTo a latTIce shapE, ANd A conTact that connects a PRoTEctive diffusioN layer At A BoTTOm pOrtIon of the trEnCh and A Source eLEcTRODe oN The upper layer Of the gate elECtrOde is pRoVidED onto aN inteRsECtiOn of the gate ElecTrode so as To peneTRate the GAte elecTrode. THe pRotEctiVE dIfFusIoN LayER iS elECtrIcally coNnEcTed to The bASE REgioN viA the ContaCts and the sourCe eLectROde.
when a mOSFEt thaT sWitchEs a higH voltAgE is turned off, a drAin vOltage abrUptLy RisEs (For exAMple, chAngEs fRom 0 V to a Several HUndReD v). iN a mOSFET having a proteCtIVE dIffusion Layer aT A bOtTOm portioN oF a tRencH OF a gatE eleCTrOde, when a Drain vOLtAgE abruptLy Rises, a DiSplAceMent cURrenT is appLied to thE protECtive diffusion LAyer via a parasITiC CApACitaNce Between the pRoteCTive DiffUSiOn lAYer anD a driFt LAyER. This displacement cuRrEnt is dEtermIned by a fluctuAtion (dV/dt) iN AN Area of thE proTEcTIve diffusion laYer anD a drain volTAge (V) with RespeCt to time (T) (Patent DoCUMent 3).
Like patEnt docUmeNTS 1 aNd 2, when a protecTIVe diFfUsion laYer Is conneCteD to A baSe rEgIon, a displAcement cUrReNt ApPliEd to tHE protectIvE diFfUsiOn layER is appLied tO a baSe ReGIon. at this tIMe, A VOltaGe DrOp ocCurS iN a resIstaNCe cOmponenT between tHe pROtecTiVe DiffusiOn layer and the BaSe region, anD tHis Also caUSEs dielecTric breakdown of the gate iNSulatinG fiLm. The PresEnt inventIon RelateS geNErally To chemIcal mEcHanICAl polISHiNg oF sUbstrates, aND MorE partIcUlarLy to an aPparatus and method fOR suPplying slurry To a PoliSHInG paD.
inTEgrAtED ciRCUits are typicallY formed on sUbSTrAtes, particULarLy Silicon Wafers, bY the sEQuentiaL depositiOn of conduCtIve, sEMIcoNductive or InsulatiVe layers. AFTer eaCH lAyer iS dePositeD, tHe lAyer iS etcheD To cReate CircuiTrY featuRes. As A sEries of lAyers are sequentially depOsited And etCheD, the outer Or uPPerMost surfaCe of The substraTe, i.E, thE expoSed SUrfacE of tHE sUbsTRate, bEcomES increasiNGlY noN-PLaNar. This non-pLANAr sUrfacE prESents a PhotOlithography problEM for the integraTed cIRCuiT maNUfacTuRer. Therefore, thEre Is A NEed to perIoDically planArize the SuBStratE surfaCe to prOvide a fLAT sURface.
CHemiCal MechanicaL poLiSHing (CMP) Is OnE AcceptEd meThOd of plAnarizATion. tHIs planarization mEthod TYPicalLY reQuireS
−− layer) with low density  is extend ed on  asid esurf aceat the end ofa  lon gitudinal direction of  thetr e nch, an d a p rotecti v ed i ffu si on  la ye r  a t a b ott om port ion of the  tr en ch is electr i ca lly connec ted  to a base r egi on onan  up p er la yer  viathis p − − laye r.
Furthe r, in Pat e nt Docu m e nt  2 ( FIGS. 1 and 2), a tr e nch of a gateelectr od e  i s for med  into a la tt ice s h ape, an d  a c o nta c t that connec ts a protec t ive  diffu si onl ayer a t a b ot t omportion ofthetrench an d a so u rce ele c trode o n theupp erlaye r  o fthe  g a tee le ctr o deis provi de dontoan i n t e r sect ion  ofthe g ate electrode  so  ast o p enetr ate t he g at e ele ctrode . The  p rotective diffu sion  layer is  el ec tri ca lly c o nnecte d t o t he base  region via  t h e co ntacts and the sou rc e el ectrode. 
Whena  M OS F ET thatsw itc hesa highvolt a ge  is turn ed off ,  a  d rain vo lt age ab ru ptl y r ises( forexampl e, chang es fr o m 0 V to a sev e ral hundred V ) .I n  a MOSF EThaving a pr otec t ivediff u si onl ayerat abo t to m  portion of a trenc hof a g ate e lectrode, whe n a drainv o l tage abr uptl y  r i ses, a displac ement  current i s  applied  to t he prote ctive dif f u sion lay ervia  apar a s it ic capacitanc e betw ee n the p rot ectivedif fus ion  la ye r and a d rift lay er .Th is  di splac e ment cur re ntis  de termi n ed bya flu ctua ti on (dV /dt) in an a reaof  t he p rot ec tivediff u sio n layer  and a dr ain volt ag e(V) wit h respect toti me (t) (Pa te ntDocume n t  3).
Lik e Patent Documents 1 an d  2, whe n a  prot ecti ve diffus ion  layer  is connec ted to  a ba se  re g i on, a d is pla ce ment curre n t  ap plied  t o th e prote ctive diffusion la y eris applied to  abase r eg ion .  A t  th is tim e ,  a voltage drop  occurs in  a re sistance c o mpo ne nt betw een the  prot e ctive d iffusionlayer and  t he b a s e r egion, and  this al so causes diele c tr ic br eak down o fthe  gate  insul a tin g fil m. The  p resent  inve nt ion rela tes generally to chemic al mec hanic alpolishing  of sub strates,andmore parti cul arl y toana ppara tusa nd  me t hod f or s u pplying s l ur ryt o  a  polishingp a d .
I ntegr ate d  circu itsare typically for m ed on substrat es,p a rti cul a rlysi licon wafers,byth e sequenti al  deposition  of cond uc t ive,semico nducti ve or i n s ul a tive l ayer s.After eac h l ay e r is de po si t ed, th e la ye r is e tchedt o cr e a te circuitry fea tures . As as eri es of  l ayers a r e se quentially  depositedand et ched , the  outeror  upper mos tsurface of the subst rate,  i.e, t he  exp ose d surf aceo f  thesubs tr ate , becomes i nc r ea si n gly  non -plan ar . Th is non-pl a nar surf ace present sa p h o tolith o gr a p hy problem  fo r the i ntegratedc ircu i tm anufa cturer . Ther efore,t her eis a ne edt o  periodic ally plan a riz ethesubstrat esurf ac e t oprovide a flatsurface. 
Chemica l mechan ica l  pol i shing(C MP) is one a ccept ed methodo f  pl anariza t ion . T his  pla nar izat i on method typically requ ires 
−− layer)_with low_density is extended on_a side_surface_at the_end_of a longitudinal_direction of the_trench, and a protective_diffusion layer at_a_bottom portion of the trench is electrically connected to a base region on an_upper_layer via_this_p−−_layer.
Further, in Patent Document 2_(FIGS. 1 and 2), a_trench of_a gate electrode is formed into a lattice_shape,_and a contact_that connects a protective diffusion layer at a bottom_portion of the trench and a_source electrode on_the_upper_layer of the gate_electrode is provided onto an intersection_of the gate electrode so as_to penetrate the gate electrode. The protective_diffusion layer is electrically connected to_the base region via the_contacts and_the source electrode.
When a MOSFET_that switches a_high voltage_is turned off,_a drain voltage abruptly rises (for_example, changes from_0 V to a several hundred_V)._In a MOSFET_having_a_protective diffusion_layer at a_bottom_portion of_a_trench of a gate electrode, when_a_drain voltage abruptly rises, a displacement current_is applied to the_protective_diffusion layer via a_parasitic capacitance between the protective_diffusion layer and a drift layer._This displacement_current is_determined by a fluctuation (dV/dt) in an area of the protective_diffusion layer and a drain voltage_(V) with respect to_time (t)_(Patent_Document 3).
Like Patent_Documents_1 and_2, when a protective diffusion layer is_connected to_a base region, a displacement current_applied to the protective_diffusion_layer is applied to a base_region. At this time, a voltage_drop occurs in a resistance_component_between_the protective diffusion layer and_the base region, and this also_causes dielectric breakdown_of the gate insulating film. The present_invention_relates generally to chemical mechanical polishing_of_substrates, and more particularly to an_apparatus_and_method for supplying slurry to_a polishing pad.
Integrated circuits are typically_formed on substrates, particularly silicon wafers, by the sequential_deposition of conductive,_semiconductive or insulative layers. After_each_layer_is deposited, the layer is etched to create circuitry features._As a_series of layers_are sequentially deposited and etched, the outer or uppermost surface_of the substrate, i.e, the exposed surface_of the substrate, becomes increasingly non-planar. This non-planar surface presents a_photolithography problem for the integrated circuit manufacturer. Therefore,_there is a need to periodically planarize_the substrate surface to_provide_a flat surface.
Chemical mechanical polishing (CMP) is_one_accepted_method_of planarization. This_planarization method typically_requires