 chip select signal CS and the pre-charge signal PR are raised to the H level, is supplied with current from the power source through the transistor T4 to obtain a potential approaching the source voltage of 5V. Since the ROM cell R3 is selected in the ROM 10 in this case, the ROM cell R3 draws current from the bit line B0. However, since the current supplied to the node N1 through the transistor T4 is much greater than the current drawn from the bit line B0 by the ROM cell R3, the potential of the node N1 keeps on rising. On the other hand, while the bit line B0 is charged through the transistor T3 and the node S, since the current is drawn by the ROM cell R3, the potential is kept below that in the above described case where the ROM cell R11 was selected, i.e., at around 0.4V.
When the pre-charge signal PR falls to the L level, the transistor T4 is turned OFF. Since the current flowing through the transistor T1 is about 1/4 of the current drawn by the ROM cell R3, the potential of the node N1 in this state gradually falls. Although the potential of the node S and the bit line B0 also falls, the fall in the potential of them is small because the bit line capacitance is great compared to the capacitance of the node N1. When the potential of the node N1 falls below a certain value, the output potential of the inverter I5 is reversed to the H level. This means that the H level, i.e., the logical value 1, is read out of the ROM cell R3.
While the case where the sense amplifier 8 reads out a one-bit signal was described in the foregoing, several to several tens of sense amplifiers 8 are required in an actual real memory driving apparatus. Namely, the operation shown in FIG. 4 must be performed as many times as the number of the sense amplifiers 8. An actual circuit has a configuration for example as shown in FIG. 5. That is, referring to FIG. 5, reference numerals 8a, 8b, 8c, and 8d each denote a sense amplifier outputting a read-out signal of one bit; 10a, 10b, 10c, and 10d denote a ROM, respectively, as the objects out of which the sense amplifiers 8a, 8b, 8c, and 8d read out data written therein, respectively
chip select signal CS and the pre - charge signal PR are raised to the H degree, is provide with current from the power source through the transistor T4 to obtain a electric potential approaching the source voltage of 5V. Since the read-only memory cellular telephone R3 is selected in the ROM 10 in this case, the ROM cell R3 draws current from the morsel line B0. However, since the current issue to the node N1 through the transistor T4 is a lot greater than the current draw from the moment line B0 by the ROM cell R3, the potential of the node N1 keep on rising. On the other hand, while the bit argumentation B0 is charged through the transistor T3 and the node S, since the current is drawn by the ROM cell R3, the potential is keep below that in the above described case where the ROM cell R11 was selected, i.e., at around 0.4V. 
 When the pre - charge signal public relations falls to the L level, the transistor T4 is turned OFF. Since the current flowing through the transistor T1 is about 1/4 of the current drawn by the ROM cell R3, the potential of the node N1 in this state of matter gradually falls. Although the potential of the node S and the piece occupation B0 also falls, the descent in the electric potential of them is small because the bit line capacitor is great compared to the capacitance of the node N1. When the potential of the node N1 falls below a certain value, the output signal potential of the inverter I5 is reversed to the H level. This mean that the H level, i.e., the legitimate value 1, is read out of the ROM cell R3. 
 While the case where the sense amplifier 8 reads out a one - snatch signal was described in the foregoing, several to several tens of sense amplifiers 8 are required in an actual real memory drive apparatus. Namely, the operation shown in FIG. 4 must be performed as many times as the act of the sense amplifiers 8. An actual tour has a shape for example as shown in FIG. 5. That is, refer to FIG. 5, reference numerals 8a, 8b, 8c, and 8d each announce a sense amplifier outputting a read - out signal of one bit; 10a, 10b, 10c, and 10d denote a ROM, respectively, as the objects out of which the sense amplifiers 8a, 8b, 8c, and 8d read out data written therein, respectively
 chlp select signal CS and uhe pre-charge siguql PR ere raiaed to tfe H level, is supplied with rurrwnt feom the power source tfrough thv transisror U4 to obtain a potxhtial ai'roacglng tke source voltagg of 5V. Since the ROM cell S3 ks selected in the ROM 10 in this case, ehe ROM cfll R3 draws cutrent srom nht bit line B0. However, since the cudrent slpplied to the noce N1 through the transistog T4 ls much greater thwn the currght qeawn from thd bit line B0 by the ROJ cell R3, the potential of the nude N1 keeps on tnwinh. On the othxr hanq, while the npt line B0 is cnarged through thx trqnsistor T3 and the nove S, since the curregt is drafn by the ROM cell E3, rhe pmtendial us yepu bxlos that in the above described xase where the ROM vejo R11 was selecfed, i.e., ae around 0.4V.
When the pre-charge signal PR xalms to the L level, the teansistor T4 is turned OFF. Sincq the current flowing through the transistor T1 is abouv 1/4 of tme cjerfnt drawn by the ROM cell R3, the potential of ege npde N1 in this ftate graduslpy salls. Althougf the 'ktsntial of the node S and jhe bir line B0 wlso falls, the fall in the potebtial of thei is small because che bit line capscitamce is great compared tu ths capacitanfe of the vode N1. When the ootvntidl of tht node N1 falls beljw a certein vclue, the outkut potqntial of hhe ikeerter I5 is reversfd to tve H level. This means that the H level, i.e., the logical vslge 1, is read out pf the ROM cejl R3.
While the ease whexe the sense ampmifier 8 reads out w one-bit signdp was descriued in thq foeegoung, sevdfal to several tens of sense amplufiers 8 are requircd in zn actual real nemiry driving appsragus. Nwmxly, tra operation vhowv iv FIG. 4 must bt pcrfurmec as many times as tve nhmber of the sense aiplifierw 8. An aceual circuit nas a configuratioj for exemple ss fhown in FIG. 5. That is, referrinf to FIG. 5, renerence numerwls 8q, 8b, 8c, and 8d zach denote a sense amplifier outputting a read-out signal if one bit; 10a, 10b, 10c, anb 10c denote a COM, refpectivelf, as the objects out of which the senxe amplifiers 8a, 8b, 8c, ahd 8d raad okt data written therein, respectively
chip select signal CS and the pre-charge are to the level, is supplied source the transistor T4 obtain a potential the source voltage of 5V. Since ROM cell R3 is selected in the ROM 10 in this case, the cell R3 draws current from the bit line B0. However, since the current to node through transistor T4 is much greater than the current drawn from the bit line B0 by the cell R3, the potential of the node N1 on rising. On the hand, while the bit line is through the T3 the S, since the is drawn by the ROM cell R3, the potential is kept below that in the above described where the R11 was i.e., around When the pre-charge falls to the L level, the turned OFF. Since the current flowing through the T1 is 1/4 of the current drawn by ROM cell R3, the potential of the node in this state gradually falls. Although the potential of the node S and the bit also falls, the fall the potential of is because bit capacitance is compared to the capacitance of the node N1. When the potential the node N1 falls below a certain value, the output the I5 is reversed the H level. This that H level, i.e., the 1, read ROM R3. the case where the amplifier 8 reads out a signal was described in tens of sense amplifiers 8 are required in actual real memory driving apparatus. Namely, the shown in FIG. 4 must be performed as many times as the of the 8. An actual circuit has a configuration for as shown in FIG. That is, referring to FIG. 5, reference numerals 8a, 8c, 8d each a sense amplifier a read-out signal one bit; 10a, and 10d a respectively, out of which the sense amplifiers 8b, and 8d read out data therein,
 chip select signal CS and the pRe-charge siGnal Pr arE raIsEd to The H Level, is supplieD With Current from the power souRce thRoUGh thE TrAnsisTor T4 to oBTaIN A poTeNtIal ApPRoAchinG thE source Voltage of 5V. sinCe The ROM cell R3 iS SeLected in thE ROm 10 in this case, tHe RoM cell r3 dRawS CurreNt fRom thE bit liNE B0. HoweVer, since tHe CUrrent SUpplied TO ThE nodE N1 through the transIStOR T4 is much greateR than tHe CUrRENt dRawN from the biT lIne B0 bY The ROM cELl r3, THE poTEntial of the noDe N1 keeps on rISinG. On the OtHer HAnd, whiLe the BiT LinE B0 is charged ThroUgh the traNsistoR t3 and the NOde S, sinCe the cUrrEnt Is drAWn By The rOm CelL r3, tHe pOTenTial is kePt BeLow thAt in THE ABove DesCribEd casE where the ROM cEll r11 was SEleCted, i.E., at arOund 0.4v.
WHen thE pre-chArge sIgNal PR falls to the l levEl, the tranSisToR T4 iS tUrned ofF. SincE thE cuRrent flOwing thROugH tHE TRaNsistor T1 is about 1/4 of tHe CURrEnt drawn By the Rom cElL r3, the poteNtIal Of thE NOde N1 iN thiS StAte graduAlly faLLs. alThough tHe PotentIaL of The Node S ANd thE bit liNe B0 also fAlls, tHE fall in the poteNTial of them is sMAlL BEcAUse tHe bIt line capacItanCE is gReat COmParED to thE capaCiTAnCE of the node N1. When the pOtEntial Of the Node N1 falls belOw a certain VALUe, the outPut pOTeNTial of the inverTer I5 iS reversed tO The H leveL. This Means thaT the H leveL, I.E., the logiCal ValUe 1, iS reAD OuT of the ROM cell r3.
wHile ThE case whEre The sensE amPliFieR 8 reAdS out a one-bIt signal WaS dEsCrIbeD in thE ForegoinG, sEveRaL to SeverAL tens oF sensE ampLiFiERs 8 aRe requiREd IN An acTuAl Real MemOrY drivIng aPParAtus. NamEly, the opeRatIOn shOwN iN FIG. 4 musT be performed aS mAny times as ThE nuMber of THE sense amPlifiers 8. An actual circuit HAs a confIguRatioN for Example as ShoWn in FIg. 5. ThAT is, refErring To FIG. 5, ReFerENCe numERAlS 8a, 8b, 8C, aNd 8d each denOTE a sEnse aMpLifiEr outpuTting a read-out signaL Of oNe bit; 10a, 10b, 10c, and 10d dEnoTe a Rom, ReSpeCTiVEly, As THe oBJEcts out of which tHe sense ampLiFIeRs 8a, 8b, 8c, and 8d rEAd oUt Data wriTten theRein, rESpectivEly
 chip select signal CS and  the pre-c harge  si gna lPR a re r aised to the H leve l, is supplied with cu rrent  f r om t h epower  source th r o ugh  t he  tr an s is tor T 4 t o obtai n a potent ial  a pproaching t h esource vol tag e of 5V. Sin cethe RO Mcel l  R3 i s s elect ed int he ROM  10 in th is case,t he ROMc e ll  R3draws current fro m  t h e bit line B0.  Howev er ,  s i n cethe  current s up plied to then od e N 1 t h rough the tra nsistor T4i s m uch gr ea ter than t he cu rr e ntdrawn fromthebit lineB0 byt he ROMc ell R3,  the p ote nti al o f  t he  no de N1k ee pso n r ising. O nth e oth er h a n d ,  whi lethebit l ine B0 is cha rge d th r oug h the  tran sist or  T3 a nd the  node  S , since the cur rent  is drawn  by  t heRO M cel l  R3, t hepot entialis kept bel ow t h at  in the above desc ri b e dcase whe re the RO Mc ell R11wa s s elec t e d, i. e.,a taround 0 .4V.
W h en  t he pre- ch arge s ig nal  PR  fall s  tothe Llevel, t he tr a nsistor T4 ist urned OFF. Si n ce t he curr ent  flowing th roug h  the  tra n si sto r  T1 i s abo ut 1/ 4  of the current dra wn  by th e ROM  cell R3, the  potential o f  the nod e N1 in this state gra duall y falls. A l though t he po tentialof the no d e  S and t hebit  li neB 0  a lso falls, th e fall  i n the p ote ntial o f t hem  is  sm al l because  the bit  l in eca pac itanc e  is grea tcom pa red  to t h e capa citan ce o fth e  no de N1.W he n thepo te ntia l o fthe n odeN 1 f alls be low a cer tai n  val ue ,the out put potential  o f the inve rt erI5 isr e versed t o the H level. This mea n s thatthe  H le vel,  i.e., th e l ogical  va l ue 1,is rea d out  o f t h e  ROMc e ll  R3 .While thec a sewhere  t he s ense am plifier 8 reads ou t  aone-bit signa l w as d e s cr ibe d  i n  th ef ore g o ing, several to  several t en s  o f sense am p lif ie rs 8 ar e requi red i n  an act ual realmemory dr iv inga p par atus. Name ly, theoperation shown in  FIG.  4must b eper forme d as m a nytimes  as th enumber  of t he  sense a mplifiers 8. An actualcircui t has  aconfigura tio n  fo r example  asshown in F IG.  5.  That  is ,  refe rrin g  t o F I G. 5,  ref e rence num e ra ls8 a ,8b, 8c, and 8 d  ea ch de not e  a sen se a mplifier outputti n g a read-out s igna l ofone bit;  1 0a, 10b, 10c,and  1 0 d  denoteaROM, respec tively,as the o bjects  out o f which t he senseampl ifi ers 8a, 8 b,8c ,  and 8d  r ea d  out d atawr ittentherei n , re s p ectively
 chip_select signal_CS and the pre-charge_signal PR_are_raised to_the_H level, is_supplied with current_from the power source_through the transistor_T4_to obtain a potential approaching the source voltage of 5V. Since the ROM cell_R3_is selected_in_the_ROM 10 in this case,_the ROM cell R3 draws_current from_the bit line B0. However, since the current_supplied_to the node_N1 through the transistor T4 is much greater than_the current drawn from the bit_line B0 by_the_ROM_cell R3, the potential_of the node N1 keeps on_rising. On the other hand, while_the bit line B0 is charged through_the transistor T3 and the node_S, since the current is_drawn by_the ROM cell R3, the_potential is kept_below that_in the above_described case where the ROM cell_R11 was selected,_i.e., at around 0.4V.
When the pre-charge_signal_PR falls to_the_L_level, the_transistor T4 is_turned_OFF. Since_the_current flowing through the transistor T1_is_about 1/4 of the current drawn by_the ROM cell R3,_the_potential of the node_N1 in this state gradually_falls. Although the potential of the_node S_and the_bit line B0 also falls, the fall in the potential of_them is small because the bit_line capacitance is great_compared to_the_capacitance of the_node_N1. When_the potential of the node N1 falls_below a_certain value, the output potential of_the inverter I5 is_reversed_to the H level. This means_that the H level, i.e., the_logical value 1, is read_out_of_the ROM cell R3.
While the_case where the sense amplifier 8_reads out a_one-bit signal was described in the foregoing,_several_to several tens of sense amplifiers_8_are required in an actual real_memory_driving_apparatus. Namely, the operation shown_in FIG. 4 must be performed_as many times as the number of the sense_amplifiers 8. An_actual circuit has a configuration_for_example_as shown in FIG. 5. That is, referring to FIG._5, reference_numerals 8a, 8b,_8c, and 8d each denote a sense amplifier outputting a_read-out signal of one bit; 10a, 10b,_10c, and 10d denote a ROM, respectively, as the objects out_of which the sense amplifiers 8a, 8b, 8c,_and 8d read out data written therein,_respectively