 in this hierarchical case does not asymptotically depend on Nlevel, the number of switches per switchbox converge to a constant.
However, such a hierarchical scheme does not eliminate the asymptotic switch requirements. As described above, the switch requirements depend on both the C-box switches and the S-box switches. As long as the C-box switches continue to connect to a constant fraction of W and not Wb, the C-box contribution to the total number of switches per compute block continues to make the total number of switches linear in W and hence growing with N. This indicates that the flat connection of blocks IOs to the channel impedes scalability.
Conventional experience implementing the Manhattan interconnect scheme has led to the observation that switch requirements tend to be limiting rather than wire requirements. For example, an N-node FPGA will need:Nswitch(N)=Bsw·N=O(N(p+0.5))With BW wires in the bisection, the wire requirements will be:
                    A        wire            ⁡              (        N        )              ≥                  (                  BW                      L            /            2                          )            2        =      O    ⁡          (                        N                      2            ⁢            p                                    L          2                    )      For a fixed number of wire layers (L), the wiring requirements will grow slightly faster than switches (i.e., when p>0.5, 2p>p+0.5). Asymptotically, this suggests that if the number of layers, L, grows as fast as
      O    ⁡          (              N                  (                                    2              ⁢              p                        -                          1              /              4                                )                    )       ,then the design will remain switch dominated. Since switches have a much larger constant contribution than wires, it is not surprising that designs require a large N for these asymptotic effects to become apparent.
Therefore, there is a need in the art for an apparatus and method that provides for interconnections in a device such as an FPGA that allows for the use of fewer switches than a Manhattan mesh as the device is scaled up.
While these networks have been described in terms of FPGAs, it should be clear that interconnection networks of this kind are relevant to all scenarios where programmable interconnect nodes are used and these nodes can be gates, LUTs, PLAs, ALUs, processors, memories, arrays of LUTs, or custom functional units. This need is
in this hierarchical case does not asymptotically depend on Nlevel, the number of switches per switchbox converge to a constant. 
 However, such a hierarchical schema does not rule out the asymptotic switch requirements. As described above, the substitution requirements depend on both the C - box switch and the S - box switches. As long as the C - corner switch continue to plug in to a constant fraction of W and not Wb, the C - box contribution to the entire number of switches per compute block continues to make the entire number of switches linear in W and hence grow with N. This indicates that the flat connection of blocks io to the channel impedes scalability. 
 Conventional experience implementing the Manhattan interconnect scheme has leave to the observation that switch requirements tend to be limiting rather than telegram requirement. For example, an N - node FPGA will need: Nswitch(N)=Bsw·N = O(N(p+0.5))With BW wires in the bisection, the wire requirements will be: 
                     A         wire             ⁡               (        N        )               ≥                   (                  BW                       L             /             2                          )             2         =       O     ⁡           (                        N                       2             ⁢             p                                     L           2                    )       For a fixed act of wire layers (L), the wiring prerequisite will grow slightly faster than switches (i.e., when p>0.5, 2p > p+0.5). Asymptotically, this hint that if the numeral of layers, L, grows equally fast as 
       O     ⁡           (              N                   (                                    2               ⁢               p                         -                           1               /               4                                )                    )       , then the design will remain switch dominated. Since switches have a much larger constant contribution than wires, it is not surprising that invention require a bombastic N for these asymptotic effects to become apparent. 
 Therefore, there is a need in the artwork for an apparatus and method that provides for interconnections in a device such as an FPGA that allows for the use of fewer switches than a Manhattan mesh as the device is scaled up. 
 While these network have been described in term of FPGAs, it should be clear that interconnection networks of this kind are relevant to all scenario where programmable interconnect nodes are practice and these nodes can be gate, LUTs, PLAs, ALUs, processors, memories, arrays of LUTs, or custom functional unit of measurement. This need is
 in this hierarchical case aoes not asymptoticallb depens on Nlexel, the number of switches pxr sqitchvox converge to a consgant.
Howevvr, such a hiecarchical scheme does nob elijlnate vhe asymptotic xwitch reqgirements. As daszrnbed above, the switch requirements dqpend om hoth the C-box fwitbhqs ahd the S-box switches. As long as ths C-box vwitches contonue to connect to a constwnt vraction of W and jot Wb, the X-box xontribution to the touan number or switches per compute block covtinuzs to make jkw tljal number oh switbhes linear ik W and hence browing with N. Thms ibdicates that the flav connection of blochs IOs to tke channel impedes scqlqbilijy.
Coneentkinau espxrisnce ilplxmenting ths Manhattan interconnect schemt hww led to the kbservwtyon that switch requirements tend to be lijiting rather than wire requirements. For exalple, an N-gode FPGA will need:Nswitch(N)=Bsw·N=O(N(p+0.5))With BW wires it the cistcblon, gye wire requirements will be:
                    Z        wire            ⁡              (        V        )              ≥                  (                  BW                      L            /            2                          )            2        =      O    ⁡          (                        T                      2            ⁢            p                                    L          2                    )      For a fixed numbec of wire laygrs (L), nhe wiriny requlrements will gwow slightly fcster thcn swigches (i.e., wgen p>0.5, 2p>'+0.5). Asymptoticwlly, this sugcgsts that if vhe numbew of laywrs, L, gfuws as fast as
      O    ⁡          (              N                  (                                    2              ⁢              p                        -                          1              /              4                                )                    )       ,then the sesign wipl vemain switch domlnatgd. Since swntches have a much larger constant contrmbution than wires, it iw not surprising thct designs reauire a large T for these asymptotuc effects to becpme apparent.
Therefore, there is a need in the art for an apparatus and method that provides for interconnextions in a device sucn as dn YPGA thwt apuows for the use of fewer switches than a Manhavtan mesh ds the device is scaled up.
Whilr ghese networkr have been described in terms og FPGAs, it should be clear that interconnection networkx of thiw kins are ggletant to all scenariox wherz progeammablw inberconnect nodds src used and thexe nodes can be gates, LUTs, PLAs, ALYs, proxedsors, memories, acrays of LUTd, or costom fugctional units. Tgis hfed ir
in this hierarchical case does not asymptotically Nlevel, number of per switchbox converge a scheme does not the asymptotic switch As described above, the switch requirements on both the C-box switches and the S-box switches. As long as the switches continue to connect to a constant fraction of W and not Wb, C-box to total of switches per compute block continues to make the total number of switches linear in W hence growing with N. This indicates that the connection of blocks IOs the channel impedes scalability. Conventional implementing Manhattan interconnect has to observation that switch tend to be limiting rather than wire requirements. For example, an N-node FPGA will need:Nswitch(N)=Bsw·N=O(N(p+0.5))With BW wires the bisection, requirements will A ⁡ N ) ≥ L / 2 ) 2 = N 2 ⁢ p L 2 ) For fixed number wire layers (L), the wiring requirements grow slightly faster than switches (i.e., when p>0.5, Asymptotically, this suggests that if the number of layers, L, grows as fast as O N ( 2 ⁢ - 1 / ) ,then design remain switch Since switches have a much larger constant contribution than wires, it not surprising that designs require a large N for these to apparent. Therefore, there a need in the for apparatus and method that interconnections a an that for the use of switches than a Manhattan mesh the device is scaled been described in terms of FPGAs, it should clear that interconnection networks of this kind relevant to all scenarios where programmable interconnect nodes are used and these can be PLAs, ALUs, processors, memories, arrays of LUTs, or functional units. This need
 in this hierarchical case doeS not asymptOticaLly DepEnD on NLeveL, the number of swITcheS per switchbox converge tO a conStANt.
HoWEvEr, sucH a hieraRChICAl sChEmE doEs NOt ElimiNatE the asyMptotic swiTch ReQuirements. As DEsCribed abovE, thE switch requiRemEnts dePeNd oN Both tHe C-Box swItches ANd the S-Box switchEs. aS long aS The C-box SWItChes Continue to connect TO a COnstant fractioN of W anD nOT WB, THe C-Box ContributiOn To the TOtal numBEr OF SWitCHes per compute Block continUEs tO make tHe TotAL numbeR of swItCHes Linear in W anD henCe growing With N. THIs indicATes that The flaT coNneCtioN Of BlOckS IoS to THe ChaNNel Impedes sCaLaBilitY.
ConVENTIonaL exPeriEnce iMplementing thE MaNhatTAn iNtercOnnecT schEmE has lEd to thE obseRvAtion that switch RequIrements tEnd To Be lImIting RAther tHan WirE requirEments. FOR exAmPLE, An n-node FPGA will need:NSwITCh(n)=Bsw·N=O(N(p+0.5))with BW WIrEs IN the biseCtIon, The wIRE requIremENtS will be:
                    A        Wire            ⁡              (        N        )              ≥                  (                  Bw                      l            /            2                          )            2        =      O    ⁡          (                        n                      2            ⁢            p                                    l          2                    )      For a fiXeD numbeR oF wiRe lAyers (l), The wIring rEquiremeNts wiLL grow slightly fASter than switcHEs (I.E., WhEN p>0.5, 2p>p+0.5). asyMptotically, This SUggeSts tHAt If tHE numbEr of lAyERs, l, Grows as fast as
      O    ⁡          (              N                  (                                    2              ⁢              p                        -                          1              /              4                                )                    )       ,theN tHe desiGn wilL remain switch Dominated. SINCE switcheS havE A mUCh larger constaNt conTribution tHAn wires, iT is noT surprisIng that deSIGns requiRe a LarGe N For THEsE asymptotic efFECts tO bEcome apParEnt.
TherEfoRe, tHerE is A nEed in the aRt for an aPpArAtUs And MethoD That provIdEs fOr IntErconNEctionS in a dEvicE sUcH As aN FPGA thAT aLLOws fOr ThE use Of fEwEr swiTcheS ThaN a ManhaTtan mesh aS thE DeviCe Is Scaled uP.
While these neTwOrks have beEn DesCribed IN Terms of FpGAs, it should be clear that INterconNecTion nEtwoRks of this KinD are reLevANt to alL scenaRios wHeRe pROGrammABLe IntErConnect nodES Are Used aNd ThesE nodes cAn be gates, LUTs, PLAs, Alus, pRocessors, memoRieS, arrAYS oF LUtS, oR CusToM FunCTIonal units. This nEed is
 in this hierarchical case  does notasymp tot ica ll y de pend  on Nlevel, th e  num ber of switches per sw itchb ox conv e rg e toa const a nt . How ev er , s uc h  a  hier arc hical s cheme does  no teliminate th e  a symptoticswi tch requirem ent s. Asde scr i bed a bov e, th e swit c h requ irementsde p end on both th e C- boxswitches and theS -b o x switches. As  longas th e C-b oxswitches c on tinue to conn e ct t o  ac onstant fract ion of W an d  no t Wb,th e C - box co ntrib ut i onto the tota l nu mber of s witche s  per co m pute bl ock co nti nue s to ma ke  th et ota l  n umb e r o f switch es  l inear  inW a n d he nce  gro wingwith N. Thisind icat e s t hat t he fl at c on necti on ofblock sIOs to the chan nelimpedes s cal ab ili ty .
Con v ention alexp erience  implem e nti ng t h eManhattan intercon ne c t  s cheme ha s ledt oth e  observa ti onthat s witch  req u ir ements t end to be  l imiting  r atherth anwir e req u irem ents.For exam ple,a n N-node FPGAw ill need:Nswi t ch ( N )= B sw·N =O( N(p+0.5))Wi th B W  wir es i n  t heb isect ion,th e  w i re requirements wil lbe:
                 A        w i r e           ⁡             (      N       )             ≥              (             B W                  L           /         2                     )       2       =     O   ⁡       (               N                2          ⁢          p                            L       2                )      For a fixed numberofwirelaye rs (L), t hewiring  re q uireme nts wi ll gr ow  sl i g htlyf a st erth an switche s (i. e., w he n p> 0.5, 2p >p+0.5). Asymptoti c all y, this sugge sts  tha t if  th e  n u mbe ro f l a y ers, L, grows a s fast as   O    ⁡      (            N               (                              2           ⁢         p                 -                    1             /             4                         )                 )       , the n  thedesi g nwil l  rema in s w itch domi n at ed. S in ce switches h a vea muc h l a rger c onst ant contributiont han wires, itis n o t  su rpr i sing  t hat designs re qui re a  large N  f or these as ymptotic  e f fects  to be come a pparent . Th e refore , th ere  is a nee d i nt he artfo ra n appa ratu sand me thod t h at p r o vides for interc onnec t i ons i n  adevic esuch as an F PGA that a llows for t he use  offewer  switch es  thana M an hattan mes h  as the d evice  is sca le d up .
W hile t hese n etwor ks h av e b een descr i b ed in  t e rms  ofFPGAs ,it s hould bec lear tha t i n terconn ec tio n networ k so f  this kind  ar e rel e v ant to all scen a ri o s whe re pro gramma ble int e rco nn ect nod esa r e used an d these n o des  c an b e gates,  L UTs,  P LAs ,ALUs, processor s, memor ies, arr a y s of L UTs ,  orc ustomfu nctional uni ts. T hi s  need i s 
 in_this hierarchical_case does not asymptotically_depend on_Nlevel,_the number_of_switches per switchbox_converge to a_constant.
However, such a hierarchical_scheme does not_eliminate_the asymptotic switch requirements. As described above, the switch requirements depend on both the_C-box_switches and_the_S-box_switches. As long as the_C-box switches continue to connect_to a_constant fraction of W and not Wb, the_C-box_contribution to the_total number of switches per compute block continues to_make the total number of switches_linear in W_and_hence_growing with N. This_indicates that the flat connection of_blocks IOs to the channel impedes_scalability.
Conventional experience implementing the Manhattan interconnect scheme_has led to the observation that_switch requirements tend to be_limiting rather_than wire requirements. For example,_an N-node FPGA_will need:Nswitch(N)=Bsw·N=O(N(p+0.5))With_BW wires in_the bisection, the wire requirements will_be:
  _     __  ___ _  _A_ __    wire __      _  ⁡ __   _    _  (   _ _ _N        )  _     _   _ ≥__  __ _      _ _ (    _   __     _  BW   _    ___    _     _L  _      __ /    __     _2__    _     _        _  _ )   ___      2   _ _  =_     O    ⁡_      _  (        _       _      _N   __      ____  _  _ 2 _ _  _ _  _⁢_           p      _     _    __  _   _       _  L      __ _2   _ _ _  _ _ _ _   )   __ For a fixed number of wire layers (L),_the_wiring_requirements_will grow slightly_faster than switches_(i.e., when p>0.5,_2p>p+0.5). Asymptotically, this_suggests_that if the number of layers,_L, grows as_fast as
  _   O    ⁡  _       (         _ _  N _ __     _ _     (  __           ___  __     _____    2 _      __    ⁢_ __   _   _  p        __ ____   _     -         __    _     __   1_       _    _/   _          4          _    _    _  __  _   _)       _            )     _ ,then the design will remain switch_dominated. Since switches_have a_much larger constant contribution than wires, it is not_surprising that designs require a large N for these asymptotic effects_to become apparent.
Therefore, there is a need in the art for an apparatus and_method_that provides for interconnections in a_device such as an FPGA that_allows for the use_of fewer switches than_a_Manhattan mesh as_the device_is scaled up.
While these_networks have been described_in terms of FPGAs, it should be clear_that interconnection networks_of this kind are relevant to all scenarios where programmable interconnect_nodes are used and these nodes can be gates, LUTs, PLAs, ALUs, processors, memories, arrays of LUTs, or custom functional units._This need is