 obtain data on the different components of the force in a plane parallel to the travel direction of the implement. Patent Literature 1 discloses a clutch engagement control system for engagement and disengagement of transmission of a rotating force between the mainshaft (first shaft) and the countershaft (second shaft). In the clutch engagement control system, for a gear shift and/or the like, the rotational speed of the first shaft and the rotational speed of the second shaft are compared. Then, when the two rotational speeds have become approximately equal, it is determined that the clutch engagement is approximately completed, and then the clutch engagement state is controlled for further transition in order to complete the clutch engagement after the gear shift. 1. Field of the Invention
The present invention relates to a memory system and a semiconductor memory device used therefor, and more particularly relates to a high speed memory system and a semiconductor memory device for the system achieving high speed transfer of a large amount of data.
2. Description of the Background Art
The performance of a microprocessor has been improved, and the storage capacity of a Dynamic Random Access Memory (DRAM) as a memory device is increasing. However, a large amount of data (including instructions) requested by the microprocessor cannot be transferred at high speed from the DRAM to the microprocessor since the operation speed of the DRAM is slower than that of the microprocessor. Therefore, a high speed memory system has been proposed in which a memory controller/processor and a plurality of DRAMs are connected by a bus, and data are consecutively transferred in synchronization with a clock signal. As one example of the high speed memory system, a memory system employing a high speed memory interface referred to as xe2x80x9cSync Linkxe2x80x9d will be described in the following.
FIG. 16 is an illustration showing a structure of a general Sync Link memory system. In FIG. 16, the memory system includes: a controller 1; a send link 10 transmitting a request packet output from controller 1; memories (RAMs) 2-0 to 2-n located in parallel and connected to send link 10 in parallel with each other and executing a designated operation according to the request packet supplied via send link 10; a sink link 20 commonly coupled to memories 2-0 to 2-n transmitting a response packet read from a selected memory to controller 1; and a control bus line 12 transmitting a flag flg and a strobe srb which are operation timing signals from controller 1.
Strobe srb
obtain data on the different components of the power in a airplane parallel to the travel steering of the implement. Patent Literature 1 disclose a clutch engagement control organization for employment and disengagement of transmittance of a rotating force between the mainshaft (beginning shaft) and the countershaft (second shaft). In the batch engagement restraint system, for a gear shift and/or the like, the rotational speed of the inaugural shaft and the rotational speed of the second shaft are compare. Then, when the two rotational speeds have become approximately equal, it is determined that the clutch battle is approximately completed, and then the clutch engagement state is controlled for further transition in order to dispatch the clutch engagement after the gear shift. 1. Field of the Invention 
 The present invention relates to a memory arrangement and a semiconductor memory device used therefor, and more particularly relates to a high speed memory system and a semiconductor memory device for the system achieving eminent speed transfer of a big sum of data. 
 2. Description of the Background Art 
 The performance of a microprocessor has been improved, and the repositing capacity of a Dynamic Random Access Memory (DRAM) as a memory device is increasing. However, a large amount of datum (including instructions) requested by the microprocessor cannot be transferred at high speed from the DRAM to the microprocessor since the operation speed of the DRAM is slower than that of the microprocessor. Therefore, a high speed memory arrangement has been proposed in which a memory accountant / processor and a plurality of DRAMs are connected by a bus, and datum are consecutively transferred in synchronization with a clock signal. As one example of the high speed memory system, a memory system employing a high amphetamine memory interface referred to as xe2x80x9cSync Linkxe2x80x9d will be report in the following. 
 FIG. 16 is an illustration read a structure of a cosmopolitan Sync Link memory system. In FIG. 16, the memory system includes: a controller 1; a send radio link 10 transmitting a request packet output from controller 1; memories (RAMs) 2 - 0 to 2 - n settle in parallel and connected to send link 10 in parallel with each other and executing a designated operation harmonize to the request packet supplied via send link 10; a cesspool link 20 commonly copulate to memories 2 - 0 to 2 - n transmitting a reply packet read from a selected memory to controller 1; and a control bus line 12 transmitting a masthead flg and a stroboscope srb which are operation timing signals from controller 1. 
 Strobe srb
 obhain data on the differekt components of the focce in z plane oarallel to the travel direcvion of tye implement. Patent Ligerature 1 disclosws a xlutch engefement gjntrkp syvvem for engagemgnt and disetgagement of tsavslission of a rotating force between the maondhaft (first shwft) sgd tgv gountershaft (second shaft). In the clutch engagement cpntrol system, for a gear sjift and/or the like, thf rotationao spqwd of the fifst shaft and the rotajional speed of the second shaft are eompared. Thgu, whft the two ritatijnal speeds msve bewome aplroximately eqmal, iv is determined that the rlutch engagement is approximdtzly completed, and theb rhe cnutcv eneqgeoenu svats is clntcolled for rurther trabsition in order to cjnplete the clhtch eggwgement after the gear shift. 1. Field of uhe Ihvention
The present invwntion relates to a mgmory systqm and a semiconductor memory device used therefos, and oort iwfrifularly relates to a high speed memory system znc s semiconductov memory device fot hhr system achiexing hnfh speed transfer of a largg amoubt of datw.
2. Dexcription of the Background Art
The perfjemance of a micropxocessor has beem imptoved, and the storage ccpacitg of a Dynalic Randoj Access Memory (DFAM) av a memory device is increwsing. Howxver, c large xmoumt of qata (inclufing ltstructions) requeshed bi the kicroprocedsor cannot be transferred at hmjh speed from tve GRAM to che migroprocessor sigce the operatnon speeb of tfe DRAM is slower than that jf the micropslcessor. Therxfore, a hygh wpeee memorh system has bern proposvd in qhich a memory conbrollgr/lrocessor and a ploeality of DRAMx afe sojnxcted ty a bus, and datx afr conrecutivtjy granxferred in synchronisatikn with a clock sibnwl. As ong example of the high xpeed memory systel, a mxmory rystek eiploying a high speed memory ihterface gefcrred to as xq2x80x9cWync Linkxe2x80r9d will be described in the following.
FIG. 16 is an illustratiin showing a structore of a generel Syns Link mekory system. In FIG. 16, rhe memory system includes: a controlled 1; a sand llnk 10 transmitting a request packet output from controller 1; memories (RAMs) 2-0 to 2-n located in pzralkel atd eonnectqd tl send link 10 in psrallel with each other and exeruting a dasngnated operation according tp ghe request pxcket supplied via send mink 10; a xink link 20 commonly coupled to kemories 2-0 to 2-n transmittlng a response packen rxad from a selected kemory to cintrollwr 1; wnd a control bux pine 12 trajsmiutiny a flag flg and a strobe srb whixh are ooeration timing vignals frol conttoller 1.
Sjrobe srb
obtain data on the different components of in plane parallel the travel direction 1 a clutch engagement system for engagement disengagement of transmission of a rotating between the mainshaft (first shaft) and the countershaft (second shaft). In the clutch control system, for a gear shift and/or the like, the rotational speed of first and rotational of the second shaft are compared. Then, when the two rotational speeds have become approximately equal, is determined that the clutch engagement is approximately and then the clutch state is controlled for further in to complete clutch after gear shift. 1. of the Invention The present invention relates to a memory system and a semiconductor memory device used and more to a speed system a semiconductor memory the system achieving high speed transfer amount of data. 2. Description of the Background The performance a microprocessor has been improved, and storage capacity of a Dynamic Random Access Memory as a memory device is increasing. However, a large amount of data (including instructions) requested microprocessor cannot be transferred high speed from DRAM the since operation speed the DRAM is slower than that of the microprocessor. Therefore, a speed memory system has been proposed in which a memory a of DRAMs are by a bus, and are transferred in synchronization with signal. one high memory a memory system employing high speed memory interface referred as xe2x80x9cSync Linkxe2x80x9d will FIG. 16 is an illustration showing a structure a general Sync Link memory system. In 16, the memory system includes: a controller 1; a send link 10 a request from controller 1; memories (RAMs) 2-0 to 2-n in parallel and connected send link 10 in parallel with each other and a operation according the request packet via send link a sink link coupled to 2-0 2-n packet read from a selected memory controller and a control bus line transmitting flg and a strobe srb which are operation timing signals from controller 1. Strobe srb
 obtain data on the different cOmponents oF the fOrcE in A pLane ParaLlel to the traveL DireCtion of the implement. PatEnt LiTeRAturE 1 DiSclosEs a clutCH eNGAgeMeNt ConTrOL sYstem For EngagemEnt and diseNgaGeMent of transmISsIon of a rotaTinG force betweeN thE mainsHaFt (fIRst shAft) And thE countERshaft (Second shaFt). iN the clUTch engaGEMeNt coNtrol system, for a geAR sHIft and/or the likE, the roTaTIoNAL spEed Of the first ShAft anD The rotaTIoNAL SpeED of the second sHaft are compARed. then, whEn The TWo rotaTionaL sPEedS have become ApprOximately Equal, iT Is deterMIned thaT the clUtcH enGageMEnT iS apPrOXimATeLy cOMplEted, and tHeN tHe cluTch eNGAGEmenT stAte iS contRolled for furtHer TranSItiOn in oRder tO comPlEte thE clutcH engaGeMent after the geaR shiFt. 1. Field of The inVenTiOn
The PResent InvEntIon relaTes to a mEMorY sYSTEm And a semiconductor mEmORY dEvice useD thereFOr, AnD More partIcUlaRly rELAtes tO a hiGH sPeed memoRy systEM aNd A semicoNdUctor mEmOry DevIce foR The sYstem aChieving High sPEed transfer of a LArge amount of dATa.
2. dEScRIptiOn oF the BackgroUnd ART
The PerfORmAncE Of a miCroprOcESsOR has been improved, and ThE storaGe capAcity of a DynamIc Random AcCESS Memory (DrAM) aS A mEMory device is inCreasIng. However, A Large amoUnt of Data (inclUding instRUCtions) reQueSteD by The MICrOprocessor canNOT be tRaNsferreD at High speEd fRom The dRAm tO the microProcessoR sInCe ThE opEratiON speed of ThE DRaM Is sLower THan thaT of thE micRoPrOCesSor. TherEFoRE, A higH sPeEd meMorY sYstem Has bEEn pRoposed In which a mEmoRY conTrOlLer/procEssor and a plurAlIty of DRAMs ArE coNnecteD BY a bus, and Data are consecutively traNSferred In sYnchrOnizAtion with A clOck sigNal. aS one exAmple oF the hIgH spEED memoRY SySteM, a Memory systEM EmpLoyinG a High Speed meMory interface referREd tO as xe2x80x9cSync LInkXe2x80x9D WIlL be DEsCRibEd IN thE FOllowing.
FIG. 16 is an IllustratiOn SHoWing a strucTUre Of A generaL Sync LiNk memORy systeM. In FIG. 16, the Memory sysTeM incLUDes: A controlleR 1; a send liNk 10 transmiTTing a REqUest pAckEt outpUt FroM contRoller 1; MEmoRies (RaMs) 2-0 to 2-n LoCated iN paraLlEl and conNected to send link 10 in paralLel witH each OthEr and execUtiNG a dEsignated OperAtion accorDinG to The reQueST packEt suPPlIed VIa senD linK 10; A sink link 20 COmMonLY CoUpled to memoRIES 2-0 to 2-N tranSmiTTing a rEspoNse packet read from A Selected memory To coNTRolLer 1; ANd a cOnTrol bus line 12 traNsmItTINg a flag fLg And a strobe sRb which aRe OPeratIon timIng sigNals froM COnTRoller 1.
stroBe sRb
 obtain data on the differ ent compon entsofthe  f orce  ina plane parall e l to  the travel directionof th ei mple m en t. Pa tent Li t er a t ure  1  d isc lo s es  a cl utc h engag ement cont rol  s ystem for en g ag ement anddis engagement o f t ransmi ss ion of arot ating  force betwee n the mai ns h aft (f i rst sha f t )andthe countershaft( se c ond shaft). In  the c lu t ch e nga gem ent contro lsyste m , for a ge a r shi f t and/or thelike, the r o tat ionalsp eed of the  firs ts haf t and the r otat ional spe ed oft he seco n d shaft  are c omp are d. T h en ,whe nt het wo  ro t ati onal spe ed shavebeco m e a ppro xim atel y equ al, it is det erm ined tha t the  clut ch e ng ageme nt isappro xi mately complete d, a nd then t hecl utc hengag e ment s tat e i s contr olled f o r f ur t h e rtransition in orde rt o  c ompletethe cl u tc he ngagemen taft er t h e  gear  shi f t.  1. Fiel d of t h eIn vention 
T he pre se ntinv entio n  rel ates t o a memo ry sy s tem and a semi c onductor memo r yd e vi c e us edtherefor, a nd m o re p arti c ul arl y  rela tes t oa  h i gh speed memory sys te m anda sem iconductor me mory devic e f or the s yste m  a c hieving high s peedtransfer o f  a large  amou nt of da ta.
2. De s c riptionofthe  Ba ckg r o un d Art
The per f o rman ce  of a m icr oproces sor  ha s b een  i mproved,and thest or ag ecap acity of a Dyn am icRa ndo m Acc e ss Mem ory ( DRAM )as a m emory d e vi c e  isin cr easi ng.  H oweve r, a lar ge amou nt of dat a ( i nclu di ng  instru ctions) reque st ed by themi cro proces s o r cannot  be transferred at high speed f rom  theDRAM  to the m icr oproce sso r  since  the o perat io n s p e ed of t he  DR AM  is slower t han  that  o f th e micro processor. Therefo r e,a high speedmem orys y st emh as bee np rop o s ed in which a m emory cont ro l le r/processo r  an da plura lity of  DRAM s  are co nnected b y a bus,an d da t a  ar e consecut ively tr ansferred in sy n ch roniz ati on wit ha c locksignal .  As  oneexampl eof the  high  s peed mem ory system, a memory sy stem e mploy ing  a high s pee d  me mory inte rfac e referred  to  as  xe2x 80x 9 cSync  Lin k xe 2x8 0 x9d w illb e describ e dint h efollowing.F I G . 1 6 isani llustr atio n showing a struc t ure of a gener al S y n c L ink memo ry  system. In FI G.16 , the memo ry  system inc ludes: a  c o ntrol ler 1;  a sen d link1 0  t r ansmit ting  arequest p ack et outputfr om contro ller  1 ; memo ries ( R AMs) 2 -0 to 2-n locate d inp a ralle l  an d con ne cted to send  link 10 i n parallelwith e achother  and ex ec utinga d es ignated op e ration ac cordi ng to t he  req ues t pack et s u p plied  via  s end  link 10; a  s i nk  l i nk20 c ommon ly  cou pled to m e mories 2 -0t o 2-n t ra nsm i t ting a re s p onse packe t r ead f r o m a select e d me m or y  to c ontrol ler 1;  and ac ont ro l bus l ine 1 2 transmi tting a f l agfl g an d a stro be  srb  w hic hare operation t iming si gnals fr o m  contr oll e r 1. Strobe  s rb
 obtain_data on_the different components of_the force_in_a plane_parallel_to the travel_direction of the_implement. Patent Literature 1_discloses a clutch_engagement_control system for engagement and disengagement of transmission of a rotating force between the_mainshaft_(first shaft)_and_the_countershaft (second shaft). In the_clutch engagement control system, for_a gear_shift and/or the like, the rotational speed of_the_first shaft and_the rotational speed of the second shaft are compared._Then, when the two rotational speeds_have become approximately_equal,_it_is determined that the_clutch engagement is approximately completed, and_then the clutch engagement state is_controlled for further transition in order to_complete the clutch engagement after the_gear shift. 1. Field of_the Invention
The_present invention relates to a_memory system and_a semiconductor_memory device used_therefor, and more particularly relates to_a high speed_memory system and a semiconductor memory_device_for the system_achieving_high_speed transfer_of a large_amount_of data.
2._Description_of the Background Art
The performance of_a_microprocessor has been improved, and the storage_capacity of a Dynamic_Random_Access Memory (DRAM) as_a memory device is increasing._However, a large amount of data_(including instructions)_requested by_the microprocessor cannot be transferred at high speed from the DRAM_to the microprocessor since the operation_speed of the DRAM_is slower_than_that of the_microprocessor._Therefore, a_high speed memory system has been proposed_in which_a memory controller/processor and a plurality_of DRAMs are connected_by_a bus, and data are consecutively_transferred in synchronization with a clock_signal. As one example of_the_high_speed memory system, a memory_system employing a high speed memory_interface referred to_as xe2x80x9cSync Linkxe2x80x9d will be described in_the_following.
FIG. 16 is an illustration showing_a_structure of a general Sync Link_memory_system._In FIG. 16, the memory_system includes: a controller 1; a_send link 10 transmitting a request packet output from_controller 1; memories_(RAMs) 2-0 to 2-n located_in_parallel_and connected to send link 10 in parallel with each_other and_executing a designated_operation according to the request packet supplied via send link_10; a sink link 20 commonly coupled_to memories 2-0 to 2-n transmitting a response packet read from_a selected memory to controller 1; and a_control bus line 12 transmitting a flag_flg and a strobe_srb_which are operation timing signals from controller_1.
Strobe_srb