 while the drain 14a and the source 14b are allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 17a between the floating gate 17b and the P-well 16. The electrons that are trapped in the floating gate 17b flow toward and cluster at the portion of the floating gate 17b overlying the source region 14b and are extracted from the floating gate 17b and into the source region 14b by way of Fowler-Nordheim tunneling through the tunnel oxide 17a. Consequently, as the electrons are removed from the floating gate 17b, the cell 14 is erased.
There is a strong need in the art for a flash memory device structure and process for manufacture that improves the performance and reliability of the device while simplifying its method of manufacture.
The present invention relates to flash memory device structure and a method for its manufacture. In a core portion of a NAND-type flash memory cell, a select gate transistor has a structure which includes a stacked ONO dielectric layer for a gate oxide. The select gate transistor structure allows the device to be easily fabricated by eliminating the dual core oxide formation process. Elimination of the dual core oxide process steps reduces the number of process steps and prevents a potential source of contamination prior to the formation of the core tunnel oxide, thereby improving the reliability of the device.
According to another aspect of the present invention, the formation of a select gate transistor structure utilizing the stacked ONO dielectric layer for a gate oxide eliminates the stacked gate structure for the select gate transistors and the need for a poly1 contact to short out the poly1 and poly2 layers, thereby advantageously reducing the die area. In addition, eliminating the stacked gate structure for the select gate transistor allows for a channel stop implant to be performed in the select gate transistor region, thereby improving the bit line isolation and decreasing the potential for bit line to bit line punch through.
According to yet another aspect of the present invention, the select gate transistor uses a stacked ONO dielectric layer which improves the resistance of the select gate transistor to high field stress induced dielectric damage. In addition, the ONO layer is substantially thinner than the other select gate transistor oxide, thereby improving the drive current and performance of the select gate transistor. This invention relates in general to structural panels and, more specifically, to a metal-surfaced polyimide foam structural panel in which the metal layer is diffused into interstices or discontinuities in the foam surface.
Metal surface layers have been applied
while the drain 14a and the source 14b are allowed to float. Under these conditions, a strong electric sphere is modernize across the tunnel oxide 17a between the floating gate 17b and the P - well 16. The electron that are trapped in the floating gate 17b flow toward and bunch at the share of the floating gate 17b overlie the source region 14b and are distill from the floating gate 17b and into the source area 14b by way of Fowler - Nordheim tunneling through the tunnel oxide 17a. Consequently, as the electrons are removed from the floating gate 17b, the cell 14 is erased. 
 There embody a strong need in the art for a news bulletin memory device structure and process for manufacture that improves the operation and reliability of the device while simplify its method of manufacture. 
 The present invention relates to flash memory device social organization and a method for its manufacture. In a core portion of a NAND - type flash memory cell, a select gate transistor has a structure which includes a stacked ONO dielectric layer for a gate oxide. The select gate transistor structure allows the device to be well manufacture by eliminating the double effect oxide formation process. Elimination of the dual effect oxide process steps reduces the number of procedure steps and prevents a potential source of contamination prior to the formation of the congress of racial equality tunnel oxide, thereby improving the reliability of the device. 
 According to another view of the present invention, the formation of a choice gate transistor structure utilizing the stacked ONO dielectric layer for a gate oxide eliminate the stacked gate structure for the select gate transistor and the need for a poly1 liaison to short out the poly1 and poly2 layers, thereby advantageously reducing the die area. In summation, eliminating the stacked gate social organization for the select gate transistor allows for a channel stop implant to be perform in the select gate transistor area, thereby improving the bit line isolation and decrease the potential for spot line to moment line punch through. 
 According to yet another aspect of the present invention, the select gate transistor use a stacked ONO dielectric layer which better the resistance of the select gate transistor to gamey field stress induced dielectric wrong. In addition, the ONO layer is substantially thinner than the other select gate transistor oxide, thereby better the drive stream and performance of the select gate transistor. This invention relates in general to structural panels and, more specifically, to a metal - surfaced polyimide foam geomorphologic panel in which the metal layer is diffuse into interstice or discontinuities in the foam surface. 
 Metal surface layer have been applied
 whlle the drain 14a and the rource 14b are allowed tm floaf. Under ghese conditions, a strong elxctruc fitjd is developed acfoss the nunnel oxude 17e between the floating gate 17b zkd thz '-well 16. The elecjrons that ase trapped in dhd yloating gate 17b flow toward and cluseer at yhf portion of tre fkjatihg gate 17b overlying the source regjon 14b aid are extractec from the floating gate 17b and into the source rfgion 14b by qay jd Fowler-Nordfeim tunneling through the tunnel oxide 17a. Consequentlh, as che electrobs arf removed frim thv floating gabv 17b, the cell 14 os erased.
There is a wtrong need in the arv for a flash memory device sdrbcture and process foe nanufdctuse tfqt kmpdotes the pfrfkrmance ans reliabiliry of the device wholq simplifying jts meehjd of manufacture.
The present invention gelafes to flash memory devuce structure and a mgthod for yts manufacture. In a core portion of a NAND-type fnash jdmoxn zwlp, a select gate transistor has a structure whydh ikcludes a stackeb ONO dielectric lwyrt for a gate obide. Tks aelect gate transidtor sttucturw allows uhe drvice to be easily fabricatwd by eliminctibg the dual core oride formatiun ptocess. Elimination of the duau code oxide prlcess stelr reduces the nuobeg of process steps and preventf a potenvial xource uf cpntamigation prilr to the formation of tje cote tuntel oxide, hhereby improving the reliabilivb of the devive.
Dccmrding tj anobher aspect of ehe present inrention, che fofmation of a selert gate tranfistor structgte utilizing vhe stackqd OBO duelectrkz layer for a bate oxidv tliminates the stacked gate xtrocfure for the seoecu tate transistots xnd tje nqad for a polf1 covtazy to rhort out tme ooly1 and poly2 layers, theseby advantageously recuging the eie area. In addition, rliminating the stwcked gave strictore for the select gate transisfor allowd fjr a channel stoi imklant to be performed in the select gate transistoc region, thereby improvung the bit line ispkation and vecreafing the [otential for bit libe to bit line pukch through.
According tk yet dnothfr aspect of the present invention, the select gate transistor uses a stacjed ONO dielectric layrr whpch nmprovef thx cesistance of the select gate transistor to high field sdrzss induced dielectric damage. Iv addition, thg ONO layer is substantialmy thinnrr than the other select gate ttansistor oxide, thereby lmproving the srive borrxnt and performance pf the selext gate traksistor. This ivvemtlon related in gzneral to structural panels and, mire spwclfically, to a meval-surfaced iouyimise foai structural pansl ih whicf the metal lsyer is diffusrd into interstices mr discontinuitits in the foam xurface.
Ketal surfacx layers hava been applied
while the drain 14a and the source allowed float. Under conditions, a strong the oxide 17a between floating gate 17b the P-well 16. The electrons that trapped in the floating gate 17b flow toward and cluster at the portion the floating gate 17b overlying the source region 14b and are extracted from floating 17b into source region 14b by way of Fowler-Nordheim tunneling through the tunnel oxide 17a. Consequently, as the are removed from the floating gate 17b, the 14 is erased. There a strong need in the for flash memory structure process manufacture that improves performance and reliability of the device while simplifying its method of manufacture. The present invention relates to memory device a method its In core portion of flash memory cell, a select gate structure which includes a stacked ONO dielectric layer a gate The select gate transistor structure allows device to be easily fabricated by eliminating the core oxide formation process. Elimination of the dual core oxide process steps reduces the number steps and prevents a source of contamination to formation the tunnel oxide, improving the reliability of the device. According to another aspect of present invention, the formation of a select gate transistor structure stacked dielectric layer for gate oxide eliminates the gate for the select gate the for to out poly1 and poly2 layers, advantageously reducing the die area. addition, eliminating the stacked gate transistor allows for a channel stop implant be performed in the select gate transistor thereby improving the bit line isolation and decreasing the potential for bit to bit through. According to yet another aspect of the invention, the select gate uses a stacked ONO dielectric layer which improves the of select gate to high field induced dielectric damage. addition, the ONO substantially thinner the select thereby improving the drive current and of select gate transistor. This invention in structural panels and, more specifically, to a metal-surfaced polyimide foam structural panel in which the is diffused into interstices discontinuities the foam surface. Metal surface layers have been applied
 while the drain 14a and the sourcE 14b are allowEd to fLoaT. UnDeR theSe coNditions, a stronG ElecTric field is developed acRoss tHe TUnneL OxIde 17a bEtween tHE fLOAtiNg GaTe 17b AnD ThE P-welL 16. ThE electrOns that are TraPpEd in the floatINg Gate 17b flow tOwaRd and cluster At tHe portIoN of THe floAtiNg gatE 17b overLYing thE source reGiON 14b and aRE extracTED fRom tHe floating gate 17b anD InTO the source regiOn 14b by wAy OF FOWLer-norDheim tunneLiNg thrOUgh the tUNnEL OXidE 17A. Consequently, As the electrONs aRe remoVeD frOM the flOatinG gATe 17b, The cell 14 is erAsed.
there is a sTrong nEEd in the ARt for a fLash meMorY deVice STrUcTurE aND prOCeSs fOR maNufacturE tHaT imprOves THE PErfoRmaNce aNd relIability of the DevIce wHIle SimplIfyinG its MeThod oF manufActurE.
THe present inventIon rElates to fLasH mEmoRy DevicE StructUre And A method For its mANufAcTURE. IN a core portion of a NAnD-TYPe Flash memOry celL, A sElECt gate trAnSisTor hAS A struCturE WhIch incluDes a stACkEd oNO dielEcTric laYeR foR a gAte oxIDe. ThE selecT gate traNsistOR structure alloWS the device to bE EaSILy FAbriCatEd by eliminaTing THe duAl coRE oXidE FormaTion pRoCEsS. elimination of the duaL cOre oxiDe proCess steps reduCes the numbER OF process StepS AnD Prevents a potenTial sOurce of conTAminatioN prioR to the foRmation of THE core tunNel OxiDe, tHerEBY iMproving the reLIAbilItY of the dEviCe.
AccorDinG to AnoTheR aSpect of thE present InVeNtIoN, thE formATion of a sElEct GaTe tRansiSTor strUcturE utiLiZiNG thE stackeD oNo DIeleCtRiC layEr fOr A gate OxidE EliMinates The stackeD gaTE strUcTuRe for thE select gate trAnSistors and ThE neEd for a POLy1 contacT to short out the poly1 and poLY2 layers, TheReby aDvanTageously RedUcing tHe dIE area. IN additIon, elImInaTINg the STAcKed GaTe structurE FOr tHe selEcT gatE transiStor allows for a chanNEl sTop implant to bE peRforMED iN thE SeLEct GaTE trANSistor region, theReby improvInG ThE bit line isOLatIoN and decReasing The poTEntial fOr bit line To bit line PuNch tHROugH.
According To yet anoTher aspecT Of the PReSent iNveNtion, tHe SelEct gaTe tranSIstOr useS a stacKeD ONO diElectRiC layer whIch improves the resistancE of the SelecT gaTe transisTor TO hiGh field stRess Induced dieLecTriC damaGe. IN AdditIon, tHE OnO lAYer is SubsTAntially tHInNer THAn The other selECT GatE tranSisTOr oxidE, theReby improving the dRIve current and pErfoRMAncE of THe seLeCt gate transistOr. THiS INvention ReLates in geneRal to strUcTUral pAnels aNd, more SpecifiCALlY, To a metAl-suRfaCed polyimIde FoAM structUrAl PAnel in WhicH tHe metaL layer IS difFUSed into intersticEs or dISContiNUitIes in ThE foam suRFace.
metal surfaCe layers havE been aPpliEd
 while the drain 14a and t he source14b a reall ow ed t o fl oat. Under the s e co nditions, a strong ele ctric  f i eldi sdevel oped ac r os s the  t un nel  o x id e 17a  be tween t he floatin g g at e 17b and th e  P -well 16.The  electrons t hat  are t ra ppe d  in t hefloat ing ga t e 17bflow towa rd and cl u ster at t he  por tion of the float i ng gate 17b overl ying t he so u r cereg ion 14b an dare e x tracted fr o m the floating gate  17b and in t o t he sou rc e r e gion 1 4b by  w a y o f Fowler-No rdhe im tunnel ing th r ough th e  tunnel  oxide  17 a.Cons e qu en tly ,a s t h eele c tro ns are r em ov ed fr om t h e f loat ing  gat e 17b , the cell 14  is  era s ed. 
Ther e isa st ro ng ne ed inthe a rt  for a flash me mory  device s tru ct ure  a nd pr o cess f orman ufactur e thati mpr ov e s th e performance andre l i ab ility of  the d e vi ce while si mp lif ying i ts me thod of  manufac ture.T he  p resentin ventio nrel ate s tof lash  memor y device  stru c ture and a met h od for its ma n uf a c tu r e. I n a  core porti on o f  a N AND- t yp e f l ash m emory  c e ll ,  a select gate tran si stor h as astructure whi ch include s a  stacked  ONO di e lectric layerfor a  gate oxid e . The se lectgate tra nsistor s t r ucture a llo wsthe  de v i ce  to be easily f abri ca ted byeli minatin g t hedua l c or e oxide f ormation  p ro ce ss . E limin a tion ofth e d ua l c ore o x ide pr ocess  ste ps  r e duc es then um b e r of  p ro cess  st ep s and  pre v ent s a pot ential so urc e  ofco nt aminati on prior to t he  formation  o f t he cor e tunnel o xide, thereby improving the rel iab ility  ofthe devic e.Accord ing to ano ther a spect  o f t h e  pres e n tinv en tion, thef o rma tionof  a s elect g ate transistor str u ctu re utilizingthe  sta c k ed  ON O  d i ele ct r icl a yer for a gateoxide elim in a te s the stac k edga te stru cture f or th e  select  gate tra nsistorsan d th e nee d for a po ly1 cont act to sh o rt ou t  t he po ly1  and p ol y2layer s, the r eby  adva ntageo us ly red ucing  t he die a rea. In addition, elimi nating  thesta cked gate  st r uct ure for t he s elect gate  tr ans istor  al l ows f or a ch ann e l sto p im p lant to b e  p erf o r me d in the se l e c t g ate t ran s istorregi on, thereby impro v ing the bit li ne i s o lat ion andde creasing the p ote nt i a l for bi tline to bit  line pu nc h  thro ugh.
A ccordi ng to y e t  a n otheraspe ctof the pr ese nt inventi on ,t he sel ectga te tra nsisto r  use s a stacked ONO di elect r i c lay e r w hichim provest he r esistanceof the sele ct gat e tr ansis tor tohi gh fie ldst ress induc e d dielect ric d amage.In  add iti on, th e ON O layer  issu bst antiallyt h in n er  t h antheother  s elec t gate tr a nsistoroxi d e, ther eb y i m p roving th e drive curr ent  andp e rformanceo f th e  s e lectgate t ransis tor. Th i s i nv entionrel a t es in gen eral to s t ruc tu ralpanels a nd , mo re  sp ec ifically, to ametal-su rfaced p o l yimide  fo a m st r uctura lpanel in whi ch th em etal la y e r i s diffu s edint o i nter sti ceso r discontinuities in the  foa m sur f ace .
Met al su rf ace laye r s ha ve beena pplied
 while_the drain_14a and the source_14b are_allowed_to float._Under_these conditions, a_strong electric field_is developed across the_tunnel oxide 17a_between_the floating gate 17b and the P-well 16. The electrons that are trapped in_the_floating gate_17b_flow_toward and cluster at the_portion of the floating gate_17b overlying_the source region 14b and are extracted from_the_floating gate 17b_and into the source region 14b by way of_Fowler-Nordheim tunneling through the tunnel oxide_17a. Consequently, as_the_electrons_are removed from the_floating gate 17b, the cell 14_is erased.
There is a strong need_in the art for a flash memory_device structure and process for manufacture_that improves the performance and_reliability of_the device while simplifying its_method of manufacture.
The_present invention_relates to flash_memory device structure and a method_for its manufacture._In a core portion of a_NAND-type_flash memory cell,_a_select_gate transistor_has a structure_which_includes a_stacked_ONO dielectric layer for a gate_oxide._The select gate transistor structure allows the_device to be easily_fabricated_by eliminating the dual_core oxide formation process. Elimination_of the dual core oxide process_steps reduces_the number_of process steps and prevents a potential source of contamination prior_to the formation of the core_tunnel oxide, thereby improving_the reliability_of_the device.
According to_another_aspect of_the present invention, the formation of a_select gate_transistor structure utilizing the stacked ONO_dielectric layer for a_gate_oxide eliminates the stacked gate structure_for the select gate transistors and_the need for a poly1_contact_to_short out the poly1 and_poly2 layers, thereby advantageously reducing the_die area. In_addition, eliminating the stacked gate structure for_the_select gate transistor allows for a_channel_stop implant to be performed in_the_select_gate transistor region, thereby improving_the bit line isolation and decreasing_the potential for bit line to bit line punch_through.
According to yet_another aspect of the present_invention,_the_select gate transistor uses a stacked ONO dielectric layer which_improves the_resistance of the_select gate transistor to high field stress induced dielectric damage._In addition, the ONO layer is substantially_thinner than the other select gate transistor oxide, thereby improving the_drive current and performance of the select gate_transistor. This invention relates in general to_structural panels and, more_specifically,_to a metal-surfaced polyimide foam structural panel_in_which_the_metal layer is_diffused into interstices_or discontinuities in_the foam_surface.
Metal surface layers_have been_applied