 present invention is to provide a method of fabricating a semiconductor memory device, comprising the steps of:
forming a metal-insulator-semiconductor transistor on a substrate such that said metal-insulator-semiconductor transistor includes a gate electrode connected to a word line and first and second diffusion regions formed in said substrate at both sides of said gate electrode and such that said first diffusion region is connected to a bit line;
providing an interlayer insulation film on said substrate so as to cover said metal-insulator- semiconductor transistor;
forming a contact hole in said interlayer insulation film so as to expose said second diffusion region;
filling said contact hole by a conductive plug;
depositing consecutively a layer of Ru and a layer of RuO2 on said interlayer insulation film so as to cover said conductive plug;
patterning said Ru layer and said RuO2 layer to form a lower electrode pattern;
depositing an insulation film on said lower electrode pattern;
patterning said insulation film to form a capacitor insulation film;
depositing a conductor layer on said capacitor insulation film; and
patterning said conductor layer to form an upper electrode.
According to the present invention, it is possible to pattern the lower electrode pattern by a conventional dry etching process conducted in an oxidizing atmosphere, rather than employing an ion milling process. Further, by using a Pt mask pattern at the time of the dry etching process, it is possible to eliminate the process of removing the mask pattern after the lower electrode pattern is formed. Further, the use of the Pt mask pattern successfully eliminates the problem of roughening of the surface of the lower electrode pattern that would occur when an oxide mask is used in place thereof. The lower electrode pattern of the RuO2/Ru structure successfully blocks the diffusion of oxygen therethrough.
Another object of the present invention is to provide a semiconductor memory device, comprising:
a substrate;
a metal-insulator semiconductor transistor formed on said substrate, said metal-insulator-semiconductor transistor including a gate electrode connected to a word line and first and second diffusion regions formed in said substrate at both sides of said gate electrode;
a bit line connected to said first diffusion region;
an interlayer insulation film provided on said substrate so as to cover said metal-insulator-semiconductor transistor;
a contact hole provided in said interlayer insulation film so as to expose said second diffusion region;
a conductive region filling
present invention is to provide a method of fabricating a semiconductor memory device, constitute the step of: 
 forming a metal - insulator - semiconductor transistor on a substrate such that allege metal - insulator - semiconductor transistor admit a gate electrode plug in to a word line and first and second diffusion region formed in said substrate at both side of said gate electrode and such that said first diffusion region is connected to a spot line; 
 providing an interlayer insulation movie on said substrate so as to cover say alloy - insulator- semiconductor transistor; 
 shape a contact hole in said interlayer insulating material film so as to expose said second diffusion region; 
 filling say contact hole by a conductive plug; 
 depositing consecutively a layer of Ru and a layer of RuO2 on said interlayer insulation film so as to cover say conductive plug; 
 patterning say Ru level and say RuO2 layer to form a humble electrode pattern; 
 depositing an insulation film on say lower electrode pattern; 
 patterning said insulation film to shape a capacitor insulation film; 
 depositing a conductor layer on say capacitor insulating material movie; and 
 model said conductor layer to form an upper electrode. 
 harmonize to the present invention, it is possible to pattern the lower electrode design by a conventional dry etching process conducted in an oxidizing air, rather than hire an ion milling process. Further, by use a Pt mask form at the time of the dry etch process, it is potential to eliminate the process of removing the masquerade pattern after the lower electrode pattern is formed. Further, the use of the Pt mask pattern successfully eliminates the problem of roughening of the surface of the lower electrode form that would occur when an oxide mask is use in place thereof. The lower electrode pattern of the RuO2 / Ru structure successfully blocks the dispersion of oxygen therethrough. 
 Another object of the present invention is to provide a semiconductor memory device, comprising: 
 a substrate; 
 a metal - insulator semiconductor transistor form on say substrate, suppose metal - insulator - semiconductor transistor include a gate electrode connected to a word channel and first and second diffusion regions shape in said substrate at both sides of said gate electrode; 
 a bit line connected to say first diffusion region; 
 an interlayer insulation film provided on say substrate so as to cover said metal - insulator - semiconductor transistor; 
 a contact hole put up in said interlayer insulation movie so as to disclose said second diffusion region; 
 a conductive region filling
 prfsent invention is to pruvide a method of fabrmcating a semicunductor memory device, comprmsint the steps of:
forming a metxl-insulatlr-semicobducuor transistor on a substvcte shgh thct said metal-insolator-semicotductor transivtur includes a gate electrode connecteq to a eogd line and fitst amq sedond diffusion regions formed in szid subvtrate at botn sides of said gate electgode and such that saif first difdusijb region is zonnected uo a bit ling;
providing an interlayer insulatkon fnlm on said sybshtate so as ti covvr said metal-lmsulatmr- semivonductor tranxisvor;
firming a contact hole in said interlayet insulatimn film so as to expowe sahd sacona diwfuaipn regioj;
fimling said contact hooe by a conductive klud;
eepositing cohsecutyvqly a layer of Ru and a layer of RuO2 on sajd interlayer insulatiob film so as to cover said conquctive plug;
patterning said Ru layer and said RuO2 layec go yirm a ooaer electrode pattern;
depositing an insulation rikm on said lower electrode lahtrtn;
patterning sxid insulztion film to form a capasitor insulatijn folm;
depositing a conductor lqyer on said xapacitor insulatiln film; and
'atterming xaid conductor layer to forj an upper flectrode.
Zzcording to the orexett invenukon, it is possiblq to pattxrn tke lower elevtrode pattern bj a conventional dry etcjing krocesv conductef in an oxidizing atmosphere, ravier than emplpyhng an ion iillikg process. Furtrer, by using a Pt mash patgern at thv time of the dry etshing process, lt is possibne to elyminqte rhe prozdss of removinb the mask pattern qfter the lower elcctroas pattern is foxotd. Further, the uxe uf ehv Pv mash pattern sucwesswuluu elioinates the orobkem of roughening of the surface of the loeev electroee pattewn that would occur when an oxife mavk ms usec ig place thereof. The lower elecfrode patherk of the RuO2/Rt stvuctore successyully blocks the diffusion of oxygen thecethrough.
Another objecj of the present inveutlon is to prpvide a semicotductor memory devicw, comprising:
a subxtrate;
a metal-insulatod semiwonduftor transistor formed on said substrate, said metal-insulator-semiconductor transmseor includihg a gate ejzctrode conierted to a word lime and first and second diffusiun regiots formed in said substrate at buth sides of raid gate electrode;
a bit line comnected to said first diffusion region;
an interlayer insmlation fulm pdovided on said substrate so as to covee said netap-insulator-semkcomdmctor trandistpr;
c contact hole provided in said ibterlateg insulation filk so as to cxkose sapd secogd diffusion regjon;
a fonduztive region gilling
present invention is to provide a method a memory device, the steps of: a such that said transistor includes a electrode connected to a word line first and second diffusion regions formed in said substrate at both sides of gate electrode and such that said first diffusion region is connected to a line; an insulation on said substrate so as to cover said metal-insulator- semiconductor transistor; forming a contact hole in interlayer insulation film so as to expose said diffusion region; filling said hole by a conductive plug; consecutively layer of and layer RuO2 on said insulation film so as to cover said conductive plug; patterning said Ru layer and said RuO2 layer form a pattern; depositing insulation on lower electrode pattern; insulation film to form a capacitor a conductor layer on said capacitor insulation film; patterning said layer to form an upper electrode. to the present invention, it is possible to the lower electrode pattern by a conventional dry etching process conducted in an oxidizing atmosphere, employing an ion milling Further, by using Pt pattern the of the etching process, it is possible to eliminate the process of removing mask pattern after the lower electrode pattern is formed. Further, of Pt mask pattern eliminates the problem of of surface of the lower that occur mask used place thereof. The lower pattern of the RuO2/Ru structure blocks the diffusion of the present invention is to provide a semiconductor device, comprising: a substrate; a metal-insulator semiconductor formed on said substrate, said metal-insulator-semiconductor transistor including a gate electrode connected a word first and second diffusion regions formed in said at both sides of gate electrode; a bit line connected to said first region; interlayer insulation provided on said so as to said metal-insulator-semiconductor transistor; hole provided said insulation to expose said second diffusion region; conductive filling
 present invention is to proviDe a method oF fabrIcaTinG a SemiCondUctor memory devICe, coMprising the steps of:
formIng a mEtAL-insULaTor-seMiconduCToR TRanSiStOr oN a SUbStratE suCh that sAid metal-inSulAtOr-semiconducTOr Transistor IncLudes a gate elEctRode coNnEctED to a wOrd Line aNd firsT And secOnd diffusIoN RegionS Formed iN SAiD subStrate at both sides OF sAId gate electrodE and suCh THaT SAid FirSt diffusioN rEgion IS connecTEd TO A Bit LIne;
providing aN interlayer INsuLation FiLm oN Said suBstraTe SO as To cover said MetaL-insulatoR- semicONductor TRansistOr;
formIng A coNtacT HoLe In sAiD IntERlAyeR InsUlation fIlM sO as to ExpoSE SAId seConD difFusioN region;
fillinG saId coNTacT hole By a coNducTiVe pluG;
deposIting CoNsecutively a layEr of ru and a layEr oF RUO2 oN sAid inTErlayeR inSulAtion fiLm so as tO CovEr SAID cOnductive plug;
patteRnING sAid Ru layEr and sAId ruo2 Layer to fOrM a lOwer ELEctroDe paTTeRn;
deposiTing an INsUlAtion fiLm On said LoWer EleCtrodE PattErn;
patTerning sAid inSUlation film to fORm a capacitor iNSuLATiON filM;
dePositing a coNducTOr laYer oN SaId cAPacitOr insUlATiON film; and
patterning sAiD conduCtor lAyer to form an uPper electrODE.
accordinG to tHE pREsent invention, It is pOssible to pATtern the Lower ElectrodE pattern bY A ConventiOnaL drY etChiNG PrOcess conducteD IN an oXiDizing aTmoSphere, rAthEr tHan EmpLoYing an ion Milling pRoCeSs. fuRthEr, by uSIng a Pt maSk PatTeRn aT the tIMe of thE dry eTchiNg PrOCesS, it is poSSiBLE to eLiMiNate The PrOcess Of reMOviNg the maSk pattern AftER the LoWeR electrOde pattern is fOrMed. Further, ThE usE of the pT Mask pattErn successfully eliminatES the proBleM of roUgheNing of the SurFace of The LOwer elEctrodE pattErN thAT Would OCCuR whEn An oxide masK IS usEd in pLaCe thEreof. ThE lower electrode patTErn Of the RuO2/Ru strUctUre sUCCeSsfULlY BloCkS The DIFfusion of oxygen TherethrouGh.
aNoTher object OF thE pResent iNventioN is to PRovide a SemiconduCtor memorY dEvicE, COmpRising:
a subStrate;
a mEtal-insulATor seMIcOnducTor TransiStOr fOrmed On said SUbsTrate, Said meTaL-insulAtor-sEmIconductOr transistor including a gAte eleCtrodE coNnected to A woRD liNe and firsT and Second diffUsiOn rEgionS foRMed in Said SUbStrATe at bOth sIDes of said GAtE elECTrOde;
a bit line CONNecTed to SaiD First dIffuSion region;
an interLAyer insulation Film PROviDed ON saiD sUbstrate so as to CovEr SAId metal-iNsUlator-semicOnductor TrANsistOr;
a conTact hoLe proviDED iN Said inTerlAyeR insulatiOn fIlM So as to eXpOsE Said seCond DiFfusioN regioN;
A conDUCtive region filliNg
 present invention is to p rovide a m ethod  of  fa br icat inga semiconducto r  mem ory device, comprising  thest e ps o f :formi ng a me t al - i nsu la to r-s em i co nduct ortransis tor on a s ubs tr ate such tha t  s aid metal- ins ulator-semic ond uctortr ans i storinc ludes  a gat e  elect rode conn ec t ed toa  word l i n eandfirst and secondd if f usion regionsformed  i n  s a i d s ubs trate at b ot h sid e s of sa i dg a t e e l ectrode and s uch that sa i d f irst d if fus i on reg ion i sc onn ected to abitline;
pro viding an inte r layer i nsulat ion  fi lm o n  s ai d s ub s tra t esoa s t o coversa id  meta l-in s u l a tor-  se mico nduct or transistor ;
f ormi n g a  cont act h olein  said  inter layer  i nsulation filmso a s to expo sesa idse condd iffusi onreg ion;
fi lling s a idco n t a ct  hole by a conduct iv e pl ug;
depo siting co ns e cutively  a  la yero f  Ru a nd a la yer of R uO2 on sa id  interl ay er ins ul ati onfilms o as  to co ver said  cond u ctive plug;
pa t terning saidR ul a ye r  and  sa id RuO2 lay er t o  for m al ow ere lectr ode p at t er n ;
depositing an ins ul ationfilmon said lower  electrode p a ttern;
p atte r ni n g said insulat ion f ilm to for m  a capac itorinsulati on film;d e positing  acon duc tor l ay er on said ca p a cito rinsulat ion  film;and 
pa tte rni ng  said con ductor l ay er  t ofor m anu pper ele ct rod e. 
Ac cordi n g to t he pr esen tin v ent ion, it is p ossi bl eto p att er n the  low e r e lectrod e pattern  by a co nv en tionaldry etching p ro cess condu ct edin ano x idizingatmosphere, rather than employi ngan io n mi lling pro ces s. Fur the r , by u sing a  Pt m as k p a t terna t  t heti me of thed r y e tchin gproc ess, it  is possible to el i min ate the proce ssof r e m ov ing th e  ma sk pat t e rn after the lo wer electr od e  p attern isf orm ed . Furth er, the  useo f the P t mask pa ttern suc ce ssfu l l y e liminatesthe prob lem of ro u gheni n gof th e s urface  o f t he lo wer el e ctr ode p attern  t hat wo uld o cc ur whenan oxide mask is used i n plac e the reo f. The lo wer ele ctrode pa tter n of the R uO2 /Ru  stru ctu r e suc cess f ul lyb locks  the diffusion of  ox y g en  therethrou g h . 
An other  ob j ect of  the  present inventio n  is to provide  a s e m ico ndu c torme mory device, c omp ri s i ng:
a su bs trate;
a me tal-insu la t or se micond uctortransis t o rf ormedon s aid  substrat e,sa i d metal -i ns u lator- semi co nducto r tran s isto r including a gate  elec t r ode c o nne ctedto  a word line  and first  and second  diffu sion  regi ons for me d in s aid  s ubstrate a t  both sid es of  said g at e el ect rode;a bi t lineconn ec ted  to saidf i rs t  d if f usi on r egion ;an i nterlayer insulati onf ilm pro vi ded o n said su b s trate so a s t o cov e r  said meta l -ins u la t or-se micond uctortransis t or; 
a  contac t h o l e provide d in said int er laye r insula ti on f il m s oas to expose sa id secon d diffus i o n regi on; a co n ductiv eregion filli ng
 present_invention is_to provide a method_of fabricating_a_semiconductor memory_device,_comprising the steps_of:
forming a metal-insulator-semiconductor_transistor on a substrate_such that said_metal-insulator-semiconductor_transistor includes a gate electrode connected to a word line and first and second_diffusion_regions formed_in_said_substrate at both sides of_said gate electrode and such_that said_first diffusion region is connected to a bit_line;
providing_an interlayer insulation_film on said substrate so as to cover said_metal-insulator- semiconductor transistor;
forming a contact hole_in said interlayer_insulation_film_so as to expose_said second diffusion region;
filling said contact_hole by a conductive plug;
depositing consecutively_a layer of Ru and a layer_of RuO2 on said interlayer insulation_film so as to cover_said conductive_plug;
patterning said Ru layer and_said RuO2 layer_to form_a lower electrode_pattern;
depositing an insulation film on said_lower electrode pattern;
patterning_said insulation film to form a_capacitor_insulation film;
depositing a_conductor_layer_on said_capacitor insulation film;_and
patterning_said conductor_layer_to form an upper electrode.
According to_the_present invention, it is possible to pattern_the lower electrode pattern_by_a conventional dry etching_process conducted in an oxidizing_atmosphere, rather than employing an ion_milling process._Further, by_using a Pt mask pattern at the time of the dry_etching process, it is possible to_eliminate the process of_removing the_mask_pattern after the_lower_electrode pattern_is formed. Further, the use of the_Pt mask_pattern successfully eliminates the problem of_roughening of the surface_of_the lower electrode pattern that would_occur when an oxide mask is_used in place thereof. The_lower_electrode_pattern of the RuO2/Ru structure_successfully blocks the diffusion of oxygen_therethrough.
Another object of_the present invention is to provide a_semiconductor_memory device, comprising:
a substrate;
a metal-insulator semiconductor_transistor_formed on said substrate, said metal-insulator-semiconductor_transistor_including_a gate electrode connected to_a word line and first and_second diffusion regions formed in said substrate at both_sides of said_gate electrode;
a bit line connected_to_said_first diffusion region;
an interlayer insulation film provided on said substrate_so as_to cover said_metal-insulator-semiconductor transistor;
a contact hole provided in said interlayer insulation film_so as to expose said second diffusion_region;
a conductive region filling