layer insulating film 114.
Accordingly, a plurality of capacitor upper electrodes 113, which are aligned over each capacitor lower electrode 111, are connected to MOS transistors To on the silicon substrate 101 on a one-by-one basis respectively.
In this case, a metal pad 116b is formed in the second interlayer insulating film 114 on the second conductive plug 115b. A bit line 117 that is formed over the metal pad 116b via a third interlayer insulating film (not shown) is connected to the metal pad 116b. The bit line 117 extends in the direction that intersects orthogonally with the word line WL and the capacitor lower electrode 111 respectively.
Meanwhile, the above capacitor is formed by methods described in the following.
The first method is such a method that a first conductive film, a ferroelectric film, and a second conductive film are formed sequentially on the first interlayer insulating film 109, then the capacitor upper electrodes 113 are formed by patterning the second conductive film, and then the ferroelectric films 112 and the capacitor lower electrodes 111 are formed by patterning the ferroelectric film and the first conductive film while using the same mask.
The second method is such a method that the first conductive film, the ferroelectric film, and the second conductive film are formed sequentially on the first interlayer insulating film 109, then the capacitor upper electrodes 113 are formed by patterning the second conductive film and the ferroelectric film while using the same mask, and then the capacitor lower electrodes 111 are formed by patterning the first conductive film.
The third method is such a method that the first conductive film, the ferroelectric film, and the second conductive film are formed sequentially on the first interlayer insulating film 109, and then the capacitor upper electrodes 113, the ferroelectric films 112 and the capacitor lower electrodes 111 are formed by patterning individually the first conductive film, the ferroelectric film, and the second conductive film while using separate masks respectively.
According to the first, second, and third methods, since the capacitor lower electrodes 111 are formed after the capacitor upper electrodes 113 are formed, there is a chance that areas of the capacitor upper electrodes 113 are reduced by the displacement of the mask that is used to pattern the capacitor lower electrodes 111. In order to prevent the reduction of the capacitor upper electrodes 113, the capacitor lower electrodes 111 may be formed widely. But this structure disturbs the higher integration of the memory cell regions.
Also, according to the second method, since the capacitor lower electrodes 111 are exposed from the ferroelectric films 112 in
layer insulating film 114. 
 Accordingly, a battalion of capacitor upper electrode 113, which are align over each capacitor lower electrode 111, are connect to MOS transistor To on the silicon substrate 101 on a one - by - one basis respectively. 
 In this case, a metal launching pad 116b is formed in the second interlayer insulating movie 114 on the second conductive spark plug 115b. A bit tune 117 that is formed over the metal diggings 116b via a third interlayer insulate film (not shown) is connected to the metal pad 116b. The spot line 117 extends in the direction that intersects orthogonally with the son line WL and the capacitor lower electrode 111 respectively. 
 Meanwhile, the above capacitor is formed by methods describe in the following. 
 The first method is such a method that a first conductive movie, a ferroelectric film, and a second conductive film are formed sequentially on the first interlayer insulating movie 109, then the capacitor upper electrode 113 are shape by patterning the second conductive film, and then the ferroelectric films 112 and the capacitor lower electrodes 111 are formed by model the ferroelectric movie and the inaugural conductive film while use the like mask. 
 The second method is such a method that the first conductive film, the ferroelectric film, and the second conductive film are formed consecutive on the first interlayer insulating film 109, then the capacitor upper electrodes 113 are formed by patterning the second conductive film and the ferroelectric film while using the same mask, and then the capacitor lower electrode 111 are formed by pattern the inaugural conductive film. 
 The third method is such a method that the first conductive movie, the ferroelectric film, and the second conductive film are formed sequentially on the first interlayer insulating film 109, and then the capacitor upper electrodes 113, the ferroelectric films 112 and the capacitor low electrodes 111 are formed by patterning individually the first conductive film, the ferroelectric movie, and the second conductive film while using separate masks respectively. 
 accord to the first, second, and third methods, since the capacitor lower electrodes 111 are formed after the capacitor upper electrode 113 are formed, there is a chance that area of the capacitor upper electrodes 113 are reduced by the displacement of the mask that is used to model the capacitor lower electrodes 111. In holy order to prevent the reduction of the capacitor upper electrodes 113, the capacitor lower electrodes 111 may be formed widely. But this structure touch the higher integration of the memory cell regions. 
 Also, according to the second method, since the capacitor abject electrodes 111 are exposed from the ferroelectric films 112 in
layfr insulating film 114.
Accoraingly, a pluralnry of rapacitkr upper electrodes 113, which are alignxd ocer eqch capacitor lower eldctrode 111, wre connwctev to MOS transisvkrs To on the dilieoi substrate 101 on a one-by-ona basis respecdixepy.
In this case, a metal pad 116b is foried in yhf second interjayeg ynsumating film 114 on the second conductjve pluj 115b. A bit line 117 that is formed over the mftal pad 116b via a third interlayer instoating film (vot shown) pv connectes to the metal pad 116b. The bit live 117 ertends in tye diggction that mntersvcts orthogonally witv the wprd line WL anc tie cqpacitor lower electrmde 111 respectively.
Mganwhile, tve above capacitor us formgd by metfids deaccibsd in hhe following.
Fhe first mwthod is such a metnoq that a first condustyve film, a ferroelectric film, and a secmnd conductive film are foemed sequentially on jhe first ynterlayer insulating film 109, then the capacitor up[er emdctxides 113 qrf formed by patterning the second conductive sjlk, snd then the fcrroelectric films 112 wnc the capacitot lower elsctrodes 111 are formfd by pwtterbing the serrpelectric film and the firsr conductive dilm while using tke same mask.
Che sevond kethod is such a method thaf the first conductibd film, the ferrodlebtriw film, and the second condtctive fiom axe formea seauentiwlly on thf first interlayer insulwting fhlm 109, then hhe capacitor upper electrodes 113 are formed by pdttvrning thz secokd conductive fylm and the fetroelectrnc filo while uspng the seme mask, and then the capdfitor lower xlectrodef 111 aee firmed bh patterning thr first conductive dilm.
The third methpd ka such a method thqt the first comduztide fmlm, tra ferroelectsic wilo, and ghe second gonauctove film are formed vequsntially on the fitsb interlaier insulwting film 109, amd then the capaciuor up'er elxctrodrs 113, the ferroelectric films 112 and fhe capacltov lower electwodew 111 are formeb by patterning individually the first cinductive film, thg ferroelectric film, cnc the seconv condtctive finm while using separqte masks respectlvely.
According to the rirst, veconf, and third methods, since the capacitor lower electrodes 111 are formed aftee the ra[acitor uppsr ekectrmdzs 113 are fjrmev, vhere is a chance that areas of the capacitor up'er electrmdzs 113 are reduced by the displaveoent of the mxsk that is used to pattsrn the vapacitor lower electrodes 111. In prder to prevent the redmction of the dapacinkr upper electrodes 113, the ccpacitir lowee elcctrodes 111 may ce govmed widelj. Buu thns structure disturbs the higher untegrqtlon of the memorb cell regioks.
Xlso, zccordyng to the secons mefjod, sknce the capavitor lower elrctrodes 111 are exposeg srom the ferrotlectric films 112 in
layer insulating film 114. Accordingly, a plurality upper 113, which aligned over each connected MOS transistors To the silicon substrate on a one-by-one basis respectively. In case, a metal pad 116b is formed in the second interlayer insulating film on the second conductive plug 115b. A bit line 117 that is formed the pad via third interlayer insulating film (not shown) is connected to the metal pad 116b. The bit line extends in the direction that intersects orthogonally with word line WL and capacitor lower electrode 111 respectively. the capacitor is by described the following. The method is such a method that a first conductive film, a ferroelectric film, and a second conductive are formed the first insulating 109, the capacitor upper are formed by patterning the second then the ferroelectric films 112 and the capacitor electrodes 111 formed by patterning the ferroelectric film the first conductive film while using the same The second method is such a method that the first conductive film, the ferroelectric film, second conductive film are sequentially on the interlayer film then capacitor upper 113 are formed by patterning the second conductive film and the film while using the same mask, and then the capacitor 111 formed by patterning first conductive film. The method such a method that conductive the the conductive are formed sequentially on first interlayer insulating film 109, then the capacitor upper 112 and the capacitor lower electrodes 111 are by patterning individually the first conductive film, ferroelectric film, and the second conductive film while using separate masks respectively. to the and third methods, since the capacitor lower electrodes are formed after the upper electrodes 113 are formed, there is a chance areas the capacitor electrodes 113 are by the displacement the mask that to pattern capacitor electrodes to prevent the reduction of the upper 113, the capacitor lower electrodes may widely. But this structure disturbs the higher integration of the memory cell regions. Also, according second method, since the lower 111 are exposed from the ferroelectric films 112 in
layer insulating film 114.
AccordIngly, a plurAlity Of cApaCiTor uPper Electrodes 113, whicH Are aLigned over each capacitoR loweR eLEctrODe 111, Are coNnected TO Mos TraNsIsTorS TO On The siLicOn substRate 101 on a one-By-oNe Basis respectIVeLy.
In this caSe, a Metal pad 116b is fOrmEd in thE sEcoND inteRlaYer inSulatiNG film 114 oN the seconD cONductiVE plug 115b. A BIT lIne 117 tHat is formed over thE MeTAl pad 116b via a thirD interLaYEr INSulAtiNg film (not sHoWn) is cONnected TO tHE MEtaL Pad 116b. The bit linE 117 extends in tHE diRectioN tHat INterseCts orThOGonAlly with the Word Line WL and The capACitor loWEr electRode 111 reSpeCtiVely.
mEaNwHilE, tHE abOVe CapACitOr is formEd By MethoDs deSCRIBed iN thE folLowinG.
The first methOd iS sucH A meThod tHat a fIrst CoNductIve filM, a ferRoElectric film, and A secOnd conducTivE fIlm ArE formED sequeNtiAllY on the fIrst intERlaYeR INSuLating film 109, then the cApACItOr upper eLectroDEs 113 ArE Formed by PaTteRninG THe secOnd cONdUctive fiLm, and tHEn ThE ferroeLeCtric fIlMs 112 aNd tHe capACitoR lower ElectrodEs 111 are FOrmed by patternINg the ferroeleCTrIC FiLM and The First conducTive FIlm wHile USiNg tHE same Mask.
THe SEcONd method is such a methOd That thE firsT conductive fiLm, the ferroELECtric filM, and THe SEcond conductivE film Are formed sEQuentialLy on tHe first iNterlayer INSulating FilM 109, thEn tHe cAPAcItor upper elecTROdes 113 ArE formed By pAtterniNg tHe sEcoNd cOnDuctive fiLm and the FeRrOeLeCtrIc filM While usiNg The SaMe mAsk, anD Then thE capaCitoR lOwER elEctrodeS 111 ArE FOrmeD bY pAtteRniNg The fiRst cONduCtive fiLm.
The thirD meTHod iS sUcH a methoD that the first CoNductive fiLm, The FerroeLECtric filM, and the second conductive FIlm are fOrmEd seqUentIally on thE fiRst intErlAYer insUlatinG film 109, AnD thEN The caPACiTor UpPer electroDES 113, thE ferrOeLectRic filmS 112 and the capacitor loWEr eLectrodes 111 are fOrmEd by PATtErnINg INdiViDUalLY The first conductIve film, the FeRRoElectric fiLM, anD tHe seconD conducTive fILm while Using sepaRate masks ReSpecTIVelY.
According To the firSt, second, aND thirD MeThods, SinCe the cApAciTor loWer eleCTroDes 111 arE formeD aFter thE capaCiTor upper Electrodes 113 are formed, therE is a chAnce tHat Areas of thE caPAciTor upper eLectRodes 113 are reDucEd bY the dIspLAcemeNt of THe MasK That iS useD To pattern THe CapACItOr lower elecTRODes 111. in ordEr tO PrevenT the Reduction of the capACitor upper elecTrodES 113, The CapACitoR lOwer electrodes 111 May Be FORmed wideLy. but this struCture disTuRBs the Higher IntegrAtion of THE mEMory ceLl reGioNs.
Also, accOrdInG To the seCoNd MEthod, sInce ThE capacItor loWEr elECTrodes 111 are exposed From tHE FerroELecTric fIlMs 112 in
layer insulating film 114. 
According ly, a  pl ura li ty o f ca pacitor uppere lect rodes 113, which are a ligne do vere ac h cap acitorl ow e r  el ec tr ode  1 1 1,  arecon nectedto MOS tra nsi st ors To on th e  s ilicon sub str ate 101 on a  on e-by-o ne  ba s is re spe ctive ly.
In this c ase, a me ta l  pad 1 1 6b is f o r me d in  the second inter l ay e r insulating f ilm 11 4o nt h e s eco nd conduct iv e plu g  115b.A  b i t lin e  117 that isformed over the  metal  p ad1 16b vi a a t hi r d i nterlayer i nsul ating fil m (not shown)i s conne cted t o t hemeta l  p ad  11 6b .  Th e  b itl ine  117 ext en ds  in t he d i r e c tion  th at i nters ects orthogon all y wi t h t he wo rd li ne W Land t he cap acito rlower electrode  111  respecti vel y. 
Me an while ,  the a bov e c apacito r is fo r med  b y m et hods described inth e fo llowing. 
The f i rs tm ethod is  s uch  a m e t hod t hata  f irst con ductiv e  f il m, a fe rr oelect ri c f ilm , and a se cond c onductiv e fil m  are formed se q uentially ont he f ir s t in ter layer insul atin g  fil m 10 9 ,the n  thecapac it o ru pper electrodes 113  a re for med b y patterningthe second c o nductive  fil m ,a nd then the fe rroel ectric fil m s 112 an d the  capacit or lowere l ectrodes  11 1 a refor m e dby patterning t he f er roelect ric  film a ndthe  fi rst  c onductive  film wh il eus in g t he sa m e mask.Th e s ec ond  meth o d is s uch a  met ho dt hat  the fi r st c ondu ct iv e fi lm,  t he fe rroe l ect ric fil m, and th e s e cond  c on ductive  film are for me d sequenti al lyon the f irst int erlayer insulating film 109, th enthe c apac itor uppe r e lectro des 113 ar e form ed by  p att e r ningt h esec on d conducti v e  fi lm an dtheferroel ectric film whileu sin g the same ma sk,  and t he n t h ec apa ci t orl o wer electrodes111 are fo rm e dby pattern i ngth e first  conduc tivef ilm.
Th e third m ethod issu ch a m eth od that th e firstconductiv e  film ,  t he fe rro electr ic  fi lm, a nd the sec ond c onduct iv e film  arefo rmed seq uentially on the firstinterl ayerins ulating f ilm 109 , and the n th e capacito r u ppe r ele ctr o des 1 13,t he  fe r roele ctri c  films 11 2  a ndt h ecapacitor l o w e r e lectr ode s  111 a re f ormed by patterni n g individually  the f irs t c o nduc ti ve film, the f err oe l e ctric fi lm , and the s econd co nd u ctive  filmwhileusing s e p ar a te mas ks r esp ectively. 
Ac co r ding to  t he first,  sec on d, and  third meth o d s, since the cap acito r lower ele ctrod es  111 ar e  for med afterthe capacit or upp er e lectr odes 11 3are fo rme d,  there isa  chance t hat a reas of  t he c apa citoruppe r elect rode s113  are redu c e db yth e  di spla cemen tof t he mask t h at is us edt o patte rn  th e capaci t or l ower elect rod es 11 1 .  In ordert o pr e ve n t the  reduc tion o f the c a pac it or uppe r e l e ctrodes 1 13, the c a pac it or l ower ele ct rode s111  m ay be formed wi dely. Bu t this s t r ucture  di s turb s  the h ig her integrat ion o ft he memo r y  ce ll regi o ns. 
Al so,  acc ord ingt o the second method, sin ce t he ca p aci tor l owerel ectrodes 111are expo s ed from the f erroelectric fi l ms1 12 i n
layer insulating_film 114.
Accordingly,_a plurality of capacitor_upper electrodes_113,_which are_aligned_over each capacitor_lower electrode 111,_are connected to MOS_transistors To on_the_silicon substrate 101 on a one-by-one basis respectively.
In this case, a metal pad 116b_is_formed in_the_second_interlayer insulating film 114 on_the second conductive plug 115b._A bit_line 117 that is formed over the metal_pad_116b via a_third interlayer insulating film (not shown) is connected to_the metal pad 116b. The bit_line 117 extends_in_the_direction that intersects orthogonally_with the word line WL and_the capacitor lower electrode 111 respectively.
Meanwhile,_the above capacitor is formed by methods_described in the following.
The first method_is such a method that_a first_conductive film, a ferroelectric film,_and a second_conductive film_are formed sequentially_on the first interlayer insulating film_109, then the_capacitor upper electrodes 113 are formed_by_patterning the second_conductive_film,_and then_the ferroelectric films_112_and the_capacitor_lower electrodes 111 are formed by_patterning_the ferroelectric film and the first conductive_film while using the_same_mask.
The second method is_such a method that the_first conductive film, the ferroelectric film,_and the_second conductive_film are formed sequentially on the first interlayer insulating film 109,_then the capacitor upper electrodes 113_are formed by patterning_the second_conductive_film and the_ferroelectric_film while_using the same mask, and then the_capacitor lower_electrodes 111 are formed by patterning_the first conductive film.
The_third_method is such a method that_the first conductive film, the ferroelectric_film, and the second conductive_film_are_formed sequentially on the first_interlayer insulating film 109, and then_the capacitor upper_electrodes 113, the ferroelectric films 112 and_the_capacitor lower electrodes 111 are formed_by_patterning individually the first conductive film,_the_ferroelectric_film, and the second conductive_film while using separate masks respectively.
According_to the first, second, and third methods, since the_capacitor lower electrodes_111 are formed after the_capacitor_upper_electrodes 113 are formed, there is a chance that areas_of the_capacitor upper electrodes_113 are reduced by the displacement of the mask that_is used to pattern the capacitor lower_electrodes 111. In order to prevent the reduction of the capacitor_upper electrodes 113, the capacitor lower electrodes 111_may be formed widely. But this structure_disturbs the higher integration_of_the memory cell regions.
Also, according to the_second_method,_since_the capacitor lower_electrodes 111 are_exposed from the_ferroelectric films_112 in