 the old way determining means. When replacement is made with respect to an old way, only the bits retained in the old way are inverted. Therefore, bits in the other way are not inverted. Namely, in this case, the control means accesses to only either way of two ways one time.
As described above, according to the third aspect of the invention, it is arranged in such that when an old way is replaced, only the bits retained in the old way are inverted, so that it is sufficient for only one time access in case of updating bits, whereby a processing speed can be elevated in comparison with two times access in the prior art.
Furthermore, a forth aspect of the invention relates to a cash memory device as described in any one of the first to third aspects of the invention wherein a plurality of the above described cash memories are prepared so as to correspond to their rank levels.
According to the present invention, it is arranged in such that even if a plurality of cash memories are disposed so as to correspond to their rank levels such as upper level and lower level, only the bits retained in an old way are inverted. Accordingly, it is sufficient for only one time access in case of updating bits, whereby a processing speed can be elevated in comparison with two times access in the prior art. 1. Field of the Invention
The present invention relates to the field of integrated circuits. More particularly, the present invention relates to interfacing integrated circuits to busses and circuits having higher voltage ranges.
2. Art Background
To achieve greater transistor densities and speeds for integrated circuits, circuits designers are reducing the physical dimensions of the transistors fabricated on the integrated circuits. Greater transistor densities enable implementation of greater functionality in an integrated circuit. However, as the physical dimensions of the transistors of an integrated circuit decreases, the supply voltage for the integrated circuit correspondingly decreases.
For example, metal oxide semi-conductor (MOS) transistors contained on newer generation high density integrated circuits are fabricated with smaller channel lengths than MOS transistors on older lower density integrated circuits. The gate oxides layers of the MOS transistors are reduced in width in accordance with the reduced channel length. However, the thinner gate oxide layers of the newer generation integrated circuits cannot withstand the high voltage levels of prior generations having thicker gate oxide layers.
As a consequence, the newer generation MOS integrated circuits operate with lower supply voltages than previous generations. For example, many newer generation MOS integrated circuits operate with a 3.3 V supply voltage rather than a 5 V supply voltage common in prior generations.
the old way determining means. When substitute is do with respect to an old way, entirely the bits retained in the erstwhile way are inverted. consequently, bit in the other room are not inverted. Namely, in this case, the dominance mean accesses to only either way of two ways one time. 
 As describe above, according to the third aspect of the invention, it is arranged in such that when an previous way is replaced, only the spot retained in the old way are inverted, so that it is sufficient for only one meter access in case of updating bits, whereby a processing speed can be elevated in comparison with two times access in the prior art. 
 Furthermore, a forth aspect of the invention relates to a cash memory device as described in any one of the first to third aspects of the invention wherein a plurality of the above described cash memory are prepared so as to correspond to their membership levels. 
 According to the present invention, it is arranged in such that even if a plurality of cash memory are dispose so as to correspond to their rank level such as upper level and lower level, only the bits retained in an old way are inverted. Accordingly, it is sufficient for only one meter access in font of updating bits, whereby a processing speed can be elevated in comparison with two times entree in the prior art. 1. Field of the Invention 
 The present invention relates to the field of integrated circuits. More particularly, the present invention relates to interfacing incorporate circuits to busses and circuits having higher electric potential ranges. 
 2. Art Background 
 To achieve greater transistor densities and amphetamine for integrated circuit, circuits designers are repress the physical proportion of the transistors fabricated on the integrated circuits. Greater transistor densities enable implementation of greater functionality in an integrated tour. However, as the physical dimensions of the transistor of an integrated circuit decreases, the supply voltage for the integrated circuit correspondingly decrease. 
 For example, metal oxide semi - conductor (MOS) transistors contained on newer coevals eminent concentration integrate circuits are fabricated with smaller channel lengths than MOS transistor on older lower density integrated circuits. The gate oxides layers of the MOS transistors are reduced in width in accordance with the reduced groove length. However, the thinner gate oxide layers of the newer generation integrated circuit cannot withstand the high voltage levels of prior generations hold thicker gate oxide layers. 
 As a consequence, the newer generation MOS integrated circuits operate with lower supply voltages than previous generation. For example, many newer generation MOS integrated circuits operate with a 3.3 V provision voltage rather than a 5 V supply voltage common in prior generations.
 thf old way determining mexns. When replacgmwnt is made sith resoect to an old way, only the uits retauned in the old way ard invertef. Therefire, uits in the othec way arc not lnvercev. Namely, in thix case, the control means azczsses to only either way of two ways one tike.
Ws described afove, wccodding to the third aspect of the ihventioi, it is arrangec in such that when an old way is replaced, only hhe bits rejzinqe in the old way are inverted, so tgat it is sufficient for only ove tike access un cadg of updatinj bits, whereby a pvpcessitg speec can be elevabed ii conparison with two timxs access in the prijr art.
Furdhzrmore, a forth aspect od the invantiub rdlaues tk a cadh jemory devjce as desceibed in any one of trv first to thjrd as[ests of the invention wherein a pluralitj of the above described cawh memories are prepated so as eo correspond to their rank levels.
According to tha preadnt ikvenguoj, it is arranged in such that even if a plurajjtu pf cash memorics are disposed so ad yj correspond jo theix rznk levels such as upper jevel and lowew lefel, only the bits retained un an old waj arw inverted. Accordiugly, it is sbfficignt fot only one time access nn cass of updatijg bits, wgdreby a processivg xpaed can be elevated in com[arison wmth tco times accgss in ehe prior wrt. 1. Nheld of the Inventlon
Thg presant inventlon relates to the field of intxjrated circuijs. Korv particujarly, the present ynvention relajes to incerfackng integrzted ciccuits to bufses and circglts having hmgher voleage rantes.
2. Art Cackground
To avhieve grvauer transiwtor densities and spgess for integratzb xircuits, circuiys aesygjecs arq reducing tha phhsizsl dioensions of ghe yransistors fabricatad oh the integrated corguits. Greqter tragsistor densiyies enable implemtntatimn uf grratgr functionality in an integratsd circuih. Hjwever, as thq phnsicwl dimensipns of the transistors of an integrated circuit decreases, the supply voltage nor the intejrated circuit worrespondingly decrwases.
For example, ketal oxide semi-condudtor (MMS) trwnsistors contained on newer generation high density integrated circuits qre faurycated with smakler bhaunek lengehs vhen MOS transistorx on older lower density integreted circuhtf. The gate oxides layers of yhd MOS transisjors are reduced in width jn accorcance with the reduced channel kength. However, the thinncr gate ozide mayers of vhe newer generation integxated xircuitw caknot withstand thr migh voltahe ltvela of prior generations having thucker tahe oxide layers.
Av a consequcnge, the newer generation MOS jntefgated circuits opetate with lowet supply voltages thdn previous geneeztions. For ecamplg, many newer geieration MOS integrated circuits operate with a 3.3 V supply voltafe rather than a 5 T supply voltabx common in prior generabions.
the old way determining means. When replacement with to an way, only the way inverted. Therefore, bits the other way not inverted. Namely, in this case, control means accesses to only either way of two ways one time. As above, according to the third aspect of the invention, it is arranged in that an way replaced, only the bits retained in the old way are inverted, so that it is sufficient only one time access in case of updating whereby a processing speed be elevated in comparison with times in the art. a aspect of the relates to a cash memory device as described in any one of the first to third aspects the invention plurality of above cash are prepared so correspond to their rank levels. According invention, it is arranged in such that even a plurality cash memories are disposed so as correspond to their rank levels such as upper and lower level, only the bits retained in an old way are inverted. Accordingly, it for only one time in case of bits, a speed be elevated comparison with two times access in the prior art. 1. Field the Invention The present invention relates to the field of More the present invention to interfacing integrated circuits busses circuits having higher voltage Art To densities speeds integrated circuits, circuits designers reducing the physical dimensions of transistors fabricated on the enable implementation of greater functionality in an integrated However, as the physical dimensions of the of an integrated circuit decreases, the supply voltage for the integrated circuit decreases. For oxide semi-conductor (MOS) transistors contained on newer generation density integrated circuits are with smaller channel lengths than MOS transistors on older density circuits. The oxides layers of MOS transistors are in width in the reduced length. the layers of the newer generation integrated cannot the high voltage levels of generations gate oxide layers. As a consequence, the newer generation MOS integrated circuits operate with lower than previous generations. For many generation MOS integrated circuits operate with a 3.3 V supply voltage rather 5 V supply generations.
 the old way determining means. when replacEment Is mAde WiTh reSpecT to an old way, onlY The bIts retained in the old way Are inVeRTed. THErEfore, Bits in tHE oTHEr wAy ArE noT iNVeRted. NAmeLy, in thiS case, the coNtrOl Means accesseS To Only either Way Of two ways one TimE.
As desCrIbeD Above, AccOrdinG to the THird asPect of the InVEntion, IT is arraNGEd In suCh that when an old waY Is REplaced, only the Bits reTaINeD IN thE olD way are invErTed, so THat it is SUfFICIenT For only one timE access in caSE of UpdatiNg BitS, WherebY a proCeSSinG speed can be ElevAted in comParisoN With two TImes accEss in tHe pRioR art.
fUrThErmOrE, A foRTh AspECt oF the inveNtIoN relaTes tO A CASh meMorY devIce as Described in anY onE of tHE fiRst to Third AspeCtS of thE invenTion wHeRein a plurality oF the Above descRibEd CasH mEmoriES are prEpaRed So as to cOrrespoND to ThEIR RaNk levels.
According tO tHE PrEsent invEntion, IT iS aRRanged in SuCh tHat eVEN if a pLuraLItY of cash mEmorieS ArE dIsposed So As to coRrEspOnd To theIR ranK levelS such as uPper lEVel and lower levEL, only the bits rETaINEd IN an oLd wAy are invertEd. AcCOrdiNgly, IT iS suFFicieNt for OnLY oNE time access in case of UpDating Bits, wHereby a procesSing speed cAN BE elevateD in cOMpARison with two tiMes acCess in the pRIor art. 1. FiEld of The InvenTion
The prESEnt invenTioN reLatEs tO THe Field of integrATEd ciRcUits. MorE paRticulaRly, The PreSenT iNvention rElates to InTeRfAcIng IntegRAted circUiTs tO bUssEs and CIrcuitS haviNg hiGhEr VOltAge rangES.
2. ART backGrOuNd
To AchIeVe greAter TRanSistor dEnsities aNd sPEeds FoR iNtegratEd circuits, cirCuIts designeRs Are ReduciNG The physiCal dimensions of the transIStors faBriCated On thE integratEd cIrcuitS. GrEAter trAnsistOr denSiTieS ENable IMPlEmeNtAtion of greATEr fUnctiOnAlitY in an inTegrated circuit. HowEVer, As the physical DimEnsiONS oF thE TrANsiStORs oF AN integrated circUit decreasEs, THe Supply voltAGe fOr The inteGrated cIrcuiT CorrespOndingly dEcreases.
FOr ExamPLE, meTal oxide seMi-conducTor (MOS) traNSistoRS cOntaiNed On neweR gEneRatioN high dENsiTy intEgrateD cIrcuitS are fAbRicated wIth smaller channel lengthS than MoS traNsiStors on olDer LOweR density iNtegRated circuIts. the Gate oXidES layeRs of THe mOS TRansiStorS Are reduceD In WidTH In Accordance wITH The ReducEd cHAnnel lEngtH. However, the thinneR Gate oxide layerS of tHE NewEr gENeraTiOn integrated ciRcuItS CAnnot witHsTand the high Voltage lEvELs of pRior geNeratiOns haviNG ThICker gaTe oxIde Layers.
As a ConSeQUence, thE nEwER generAtioN MoS inteGrated CIrcuITS operate with loweR suppLY VoltaGEs tHan prEvIous genERatiOns. For examPle, many neweR generAtioN MOS iNtegratEd CircuiTs oPeRate with a 3.3 V SUpply voltAge raTher thaN a 5 v supPly VoltagE comMON in prIor gEnEraTions.
 the old way determining m eans. When  repl ace men tis m adewith respect t o  anold way, only the bits  reta in e d in th e old  way ar e  i n v ert ed .The re f or e, bi tsin theother wayare  n ot inverted. Na mely, in t his  case, the c ont rol me an s a c cesse s t o onl y eith e r wayof two wa ys one ti m e.
As d e s cr ibed  above, according to the third aspe ct ofth e  i n v ent ion , it is ar ra ngedi n sucht ha t w hen an old way is  replaced,o nly  the b it s r e tained  in t he old  way are in vert ed, so th at iti s suffi c ient fo r only  on e t imea cc es s i nc ase of  up d ati ng bits,  w he rebya pr o c e s sing  sp eedcan b e elevated in  co mpar i son  with  twotime sacces s in t he pr io r art.
Furtherm ore,  a forthasp ec t o fthe i n ventio n r ela tes toa cashm emo ry d e vi ce as described in  a n y  o ne of th e firs t  t ot hird asp ec tsof t h e  inve ntio n  w herein a  plura l it yof theab ove de sc rib edcashm emor ies ar e prepar ed so as to correspo n d to their ra n kl e ve l s.
A cco rding to th e pr e sent  inv e nt ion ,  it i s arr an g ed in such that even i fa plur ality  of cash memo ries are d i s p osed soas t o  c o rrespond to th eir r ank levels such asupper  level a nd lowerl e vel, onl y t hebit s r e t ai ned in an old w ay a re  invert ed.  Accord ing ly,  it  is  s ufficient  for onl yon eti meacces s  in case  o f u pd ati ng bi t s, whe rebya pr oc es s ing  speedc an b e el ev at ed i n c om paris on w i thtwo tim es access  in thepr io r art.1. Field of t he  Invention 
T hepresen t inventio n relates to the fieldo f integ rat ed ci rcui ts. Morepar ticula rly ,  the p resent  inve nt ion r elate s to  in te rfacing in t e gra ted c ir cuit s to bu sses and circuitsh avi ng higher vol tag e ra n g es .
2 .  A r t B ac k gro u n d
To achieve gr eater tran si s to r densitie s  an dspeedsfor int egrat e d circu its, circ uits desi gn ersa r e r educing th e physic al dimens i ons o f  t he tr ans istors  f abr icate d on t h e i ntegr ated c ir cuits.  Grea te r transi stor densities enable i mpleme ntati onof greate r f u nct ionalityin a n integrat edcir cuit.  Ho w ever,  ast he  ph y sical  dim e nsions of th e t r a ns istors of a n i nte grate d c i rcuitdecr eases, the supply voltage for th e in t e gra ted circ ui t correspondin gly  d e c reases.Fo r example,metal ox id e  semi -condu ctor ( MOS) tr a n si s tors c onta ine d on newe r g en e rationhi gh densit y in te grated  circu i ts a r e  fabricated with  smal l e r cha n nel  leng th s thanM OS t ransistors  on older l ower d ensi ty in tegrate dcircui ts.  T he gate ox i des layer s ofthe MOS  t rans ist ors ar e re d u ced i n wi dt h i n accorda n c ew it ht heredu ced c ha nnel  length.H owever,the thinner  g ate o xide l a ye r s  of the ne wer  gene r a tion integ r ated ci r cuits  canno t with stand t h e h ig h volta gel e vels of p rior gene r ati on s ha ving thi ck er g at e o xi de layers.
As a  consequ ence, th e newergen e rati o n MOSin tegrated cir cuits  o p erate w i t h l ower su p ply  vo lta gestha n pr e vious generations. For e xamp le, m a nynewer  gene ra tion MOS inte grated c i rcuits operat e with a 3.3 Vs upp l y vo lta g era ther than  a5  V su pply  vo ltag e c ommo n in p r iorg en erat ions.
 the_old way_determining means. When replacement_is made_with_respect to_an_old way, only_the bits retained_in the old way_are inverted. Therefore,_bits_in the other way are not inverted. Namely, in this case, the control means_accesses_to only_either_way_of two ways one time.
As_described above, according to the_third aspect_of the invention, it is arranged in such_that_when an old_way is replaced, only the bits retained in the_old way are inverted, so that_it is sufficient_for_only_one time access in_case of updating bits, whereby a_processing speed can be elevated in_comparison with two times access in the_prior art.
Furthermore, a forth aspect of_the invention relates to a_cash memory_device as described in any_one of the_first to_third aspects of_the invention wherein a plurality of_the above described_cash memories are prepared so as_to_correspond to their_rank_levels.
According_to the_present invention, it_is_arranged in_such_that even if a plurality of_cash_memories are disposed so as to correspond_to their rank levels_such_as upper level and_lower level, only the bits_retained in an old way are_inverted. Accordingly,_it is_sufficient for only one time access in case of updating bits,_whereby a processing speed can be_elevated in comparison with_two times_access_in the prior_art._1. Field_of the Invention
The present invention relates to_the field_of integrated circuits. More particularly, the_present invention relates to_interfacing_integrated circuits to busses and circuits_having higher voltage ranges.
2. Art Background
To_achieve greater transistor densities and_speeds_for_integrated circuits, circuits designers are_reducing the physical dimensions of the_transistors fabricated on_the integrated circuits. Greater transistor densities enable_implementation_of greater functionality in an integrated_circuit._However, as the physical dimensions of_the_transistors_of an integrated circuit decreases,_the supply voltage for the integrated_circuit correspondingly decreases.
For example, metal oxide semi-conductor (MOS) transistors_contained on newer_generation high density integrated circuits_are_fabricated_with smaller channel lengths than MOS transistors on older lower_density integrated_circuits. The gate_oxides layers of the MOS transistors are reduced in width_in accordance with the reduced channel length._However, the thinner gate oxide layers of the newer generation integrated_circuits cannot withstand the high voltage levels of_prior generations having thicker gate oxide layers.
As_a consequence, the newer_generation_MOS integrated circuits operate with lower supply_voltages_than_previous_generations. For example,_many newer generation_MOS integrated circuits_operate with_a 3.3 V_supply voltage_rather than a_5_V supply voltage common in prior generations.