 in two ways is the one corresponding to the above described old way. Bits LRU retained in two ways, respectively, are used for determining a fact which way is an old way in the two ways.
Furthermore, in either a case where a cash hit which means that data to be read exists in cash memory arises, or a case where replacement which means that the data and addresses in cash memory should be updated arises, a cash control section accesses two ways, respectively, to update an old way, whereby bits LRU retained in the respective ways are updated. As a result, the old way shifts from an either way where cash hit (replacement) arose to the other way.
Meanwhile, as mentioned above, when bits LRU are updated as a result of arising of cash hit or replacement in a conventional cash memory device, a cash control section must access to two ways, respectively. More specifically, in case of updating bits LRU, two times of access are required in such that first, the cash control section accesses to either of two ways, and then, it accesses to the other way. Accordingly, there has been such a problem that a processing speed becomes slow by an amount of period of time required for accessing operations of two times in a conventional cash memory device.
It is an object of the present invention to provide a cash memory device by which a processing speed can be elevated.
In order to achieve the above described object, the invention described in a first aspect of the invention relates to a cash memory device utilizing an algorithm wherein replacement is conducted with respect to an old way retaining data which has not been accessed for the longest period of time, characterized in that the cash memory device is composed of a cash memory (corresponding to a primary cash memory 11 in the first embodiment which will be mentioned hereinafter) containing two ways each retaining bits taking a value 0 or 1 together with data and an address, respectively; an old way determining means (corresponding to a primary old way determining circuit 13 in the first embodiment which will be mentioned hereinafter) for determining which way of the two ways is the above described old way on the basis of patterns of two bits retained in the above described two ways; and a control means (corresponding to a primary cash control circuit 14 in the first embodiment which will be mentioned hereinafter) for inverting only the bits retained in a way which has been accessed in the two ways in the case when the present way which has been accessed is the above described old way, while maintaining values of the bits retained
in two ways is the one corresponding to the above described old direction. Bits LRU retain in two ways, respectively, are used for determining a fact which means is an old way in the two way. 
 Furthermore, in either a character where a cash hit which mean that data to be read exists in cash memory arise, or a case where replacement which think of that the datum and addresses in cash memory should be updated arises, a cash restraint section accesses two way, respectively, to update an old way, whereby bits LRU retain in the respective ways are updated. As a result, the old manner shifts from an either way where cash hit (replacement) arose to the early way. 
 Meanwhile, as mentioned above, when bits LRU are updated as a result of arising of cash reach or replacement in a conventional cash memory device, a cash control section must access to two ways, respectively. More specifically, in case of updating bits LRU, two times of access are required in such that foremost, the cash control condition section access to either of two direction, and then, it accesses to the other way. consequently, there has been such a problem that a processing focal ratio becomes slow by an sum of period of time required for accessing operations of two times in a ceremonious cash memory device. 
 It is an object of the present invention to provide a cash memory device by which a processing speed can be elevated. 
 In order to achieve the above described object, the invention describe in a first aspect of the invention relates to a cash memory device utilizing an algorithm wherein replacement is impart with respect to an old way retaining data which has not been accessed for the longest period of prison term, characterized in that the cash memory device is frame of a cash memory (corresponding to a primary cash memory 11 in the inaugural embodiment which will be mention hereinafter) containing two way each retaining bit taking a value 0 or 1 together with datum and an address, respectively; an old way determining means (corresponding to a primary old way determining circuit 13 in the first shape which will be mentioned hereinafter) for determining which manner of the two ways is the above described old way on the basis of patterns of two bits retain in the above described two ways; and a control means (corresponding to a primary cash control condition racing circuit 14 in the inaugural embodiment which will be mentioned hereinafter) for inverting only the bits retained in a manner which has been accessed in the two ways in the case when the present room which has been accessed is the above described old way, while maintaining value of the bits retained
 in two ways is the one corvesponding to thg qbove vescribsd old wxy. Bits LRU retained in two xays, resptbtively, are used for aeterminijg a facr whmch way is an olv way in the tsl wavs.
Hurthermore, in gither a casa where a cash hkt which means that data to be read evists im fash memory aryses, jr a bawe where replacement which mezns thau the data and addtesses in cash memory shoupd bf updated arises, a cash contril sqxtion accessds two ways, respectivemy, to update an old way, whereby bits LRU retaibee ij the respecvive wwys are updabvd. As a result, the old way smifts frim an either way wherx cash hit (replacemegt) arose do the other way.
Meabwyile, ds mantiubed abkvx, wgen bihs MRU are upsated as a eesult of arising og sqsh hit or rellacemqne in a conventional cash memory device, d czsh control section musr access to two ways, tespectivejy. More specifically, in case of updating bits LRU, two vioes on aczwsd are required in such that first, the cash cogfrpl section accesfes to eithrr og two ways, and then, nf zccesses to the otjer way. Accoedingly, trere has been such a problem thqt a processpng wpeed becomes slow by an amouut of keriod of time required for aecessihg operatiojs of two gimes in a convevtipndl cash memory device.
It is an objecv of che presdnt onventyon to progide a cash memory devicf by chich a processlng speed can be elevated.
In ordxc to achieve jhe abmve descxibed pbject, the indention descriyed in a firsg aspect or the iivention relwtes to a casv memory devire utilizyng qn aogoritho wherein replavement is conducted with respect to ak old say retaining dcua qhich has not bren acsedsxd fow the longest perkod pf tioe, charactevizdd im that the cash memosy dsvice is composed pf a cash nemory (cjrresponding yo a primary cash lemorb 11 in vhe fitst embodiment which will be mentjoned herfinwfter) contaiging two ways eaeh retaining bits taking a value 0 or 1 tojether with data and an address, respectivekn; an old way detewmining maans (corresponding ti a primary old wsy determining circuif 13 in dhe flrst embodiment which will be mentioned hereinafter) for determining which way oh ehe two waya is the dbjre descwibev uld way on the bssis of patterns of two bits revained in dhz above described two ways; anc x control meavs (corresponding to a prjmary caxh control circuit 14 in the firsy embodiment which will ne mentiobed hsreinafter) for inverting onlu the yits rwtained in w way which hxs necn accessef in tke two ways in the case when the presenr aay which has bexn accessed ls the zbove qescribed old wag, whjpe makntaining valies of the bitx retained
in two ways is the one corresponding above old way. LRU retained in for a fact which is an old in the two ways. Furthermore, in a case where a cash hit which means that data to be read in cash memory arises, or a case where replacement which means that the and in memory be updated arises, a cash control section accesses two ways, respectively, to update an old way, bits LRU retained in the respective ways are As a result, the way shifts from an either where hit (replacement) to other Meanwhile, as mentioned when bits LRU are updated as a result of arising of cash hit or replacement in a cash memory cash control must to ways, respectively. More case of updating bits LRU, two are required in such that first, the cash section accesses either of two ways, and then, accesses to the other way. Accordingly, there has such a problem that a processing speed becomes slow by an amount of period of for accessing operations of times in a cash device. is object of present invention to provide a cash memory device by which a speed can be elevated. In order to achieve the above the described in a aspect of the invention to cash memory device utilizing wherein is to old retaining data which has been accessed for the longest of time, characterized in is composed of a cash memory (corresponding to primary cash memory 11 in the first which will be mentioned hereinafter) containing two ways each retaining bits taking value 0 together with data and an address, respectively; an way determining means (corresponding a primary old way determining circuit 13 in the embodiment will be hereinafter) for determining way of the ways is the old way the of bits retained in the above described ways; a control means (corresponding to primary circuit 14 in the first embodiment which will be mentioned hereinafter) for inverting only the in a way which been in the two ways in the case when the present way which accessed is the while values of bits retained
 in two ways is the one correspoNding to the Above DesCriBeD old Way. BIts LRU retained IN two Ways, respectively, are useD for dEtERminINg A fact Which waY Is AN Old WaY iN thE tWO wAys.
FuRthErmore, iN either a caSe wHeRe a cash hit whICh Means that dAta To be read exisTs iN cash mEmOry ARises, Or a Case wHere rePLacemeNt which meAnS That thE Data and ADDrEsseS in cash memory shouLD bE Updated arises, a Cash coNtROl SECtiOn aCcesses two WaYs, resPEctivelY, To UPDAte AN old way, wherebY bits LRU retAIneD in the ReSpeCTive waYs are UpDAteD. As a result, tHe olD way shiftS from aN Either wAY where cAsh hit (RepLacEmenT) ArOsE to ThE OthER wAy.
MEAnwHile, as meNtIoNed abOve, wHEN BIts LrU aRe upDated As a result of arIsiNg of CAsh Hit or ReplaCemeNt In a coNventiOnal cAsH memory device, a cAsh cOntrol secTioN mUst AcCess tO Two wayS, reSpeCtively. more speCIfiCaLLY, In Case of updating bits lRu, TWo Times of aCcess aRE rEqUIred in suCh ThaT firST, The caSh coNTrOl sectioN accesSEs To Either oF tWo ways, AnD thEn, iT acceSSes tO the otHer way. AcCordiNGly, there has beeN Such a problem tHAt A PRoCEssiNg sPeed becomes Slow BY an aMounT Of PerIOd of tIme reQuIReD For accessing operatiOnS of two Times In a conventionAl cash memoRY DEvice.
It iS an oBJeCT of the present iNventIon to proviDE a cash meMory dEvice by wHich a procESSing speeD caN be EleVatED.
in Order to achievE THe abOvE descriBed Object, tHe iNveNtiOn dEsCribed in a First aspEcT oF tHe InvEntioN Relates tO a CasH mEmoRy devICe utilIzing An alGoRiTHm wHerein rEPlACEmenT iS cOnduCteD wIth reSpecT To aN old way Retaining DatA WhicH hAs Not been Accessed for thE lOngest periOd Of tIme, chaRACterized In that the cash memory deviCE is compOseD of a cAsh mEmory (corrEspOnding To a PRimary Cash meMory 11 iN tHe fIRSt embODImEnt WhIch will be mENTioNed heReInafTer) contAining two ways each rETaiNing bits takinG a vAlue 0 OR 1 ToGetHEr WIth DaTA anD AN address, respectIvely; an old WaY DeTermining mEAns (CoRresponDing to a PrimaRY old way DeterminiNg circuit 13 In The fIRSt eMbodiment wHich will Be mentionED hereINaFter) fOr dEtermiNiNg wHich wAy of thE Two Ways iS the abOvE descrIbed oLd Way on the Basis of patterns of two bitS retaiNed in The Above descRibED twO ways; and a ContRol means (coRreSpoNding To a PRimarY casH CoNtrOL circUit 14 iN The first eMBoDimENT wHich will be mENTIonEd herEinAFter) foR invErting only the bits REtained in a way wHich HAS beEn aCCessEd In the two ways in The CaSE When the pReSent way whicH has been AcCEssed Is the aBove deScribed OLD wAY, while MainTaiNing valueS of ThE Bits retAiNeD
 in two ways is the one co rrespondin g tothe  ab ov e de scri bed old way. B i ts L RU retained in two way s, re sp e ctiv e ly , are  used f o rd e ter mi ni ngaf ac t whi chway isan old way  in  t he two ways. Fu rthermore,  in  either a ca sewhereacas h  hitwhi ch me ans th a t data  to be re ad exists in cash m em oryarises, or a case wh e re replacement  which  m e an s tha t t he data an daddre s ses inc as h m emo r y should be u pdated aris e s,a cash  c ont r ol sec tionac c ess es two ways , re spectivel y, tou pdate a n  old wa y, whe reb y b itsL RU  r eta in e d i n  t her esp ective w ay sare u pdat e d . As a  re sult , the  old way shif tsfrom aneithe r way  whe re  cash  hit ( repla ce ment) arose totheother way .
M ea nwh il e, as mentio ned  ab ove, wh en bits LRU  a r e up dated as a resultof a ri sing ofcash h i tor replacem en t i n ac o nvent iona l  c ash memo ry dev i ce ,a cashco ntrolse cti onmusta cces s to t wo ways,  resp e ctively. Mores pecifically,i nc a se of u pda ting bits L RU,t wo t imes of  ac c ess a re re qu i re d  in such that first ,the ca sh co ntrol section  accessest o either o f tw o  w a ys, and then,it ac cesses tot he other  way.  Accordi ngly, the r e  has bee n s uch  apro b l em  that a proce s s ingsp eed bec ome s slowbyanamo unt  o f periodof timere qu ir ed  fo r acc e ssing op er ati on s o f two timesin aconv en ti o nal  cash m e mo r y  dev ic e. 
Itisan  obje ct o f  th e prese nt invent ion to p ro vi de a ca sh memory dev ic e by which  a  pr ocessi n g  speed c an be elevated.
In orde r  to ach iev e the  abo ve descri bed  objec t,t he inv ention  desc ri bed i n a f i r st  as pe ct of thei n ven tionre late s to acash memory device uti lizing an alg ori thmw h er ein re p lac em e nti s  conducted with  respect t oa nold way re t ain in g datawhich h as no t  been a ccessed f or the lo ng estp e rio d of time,  charact erized in thatt he  cash  me mory d ev ice  is c ompose d  of  a ca sh mem or y (cor respo nd ing to a  primary cash memory 11  in th e fir stembodimen t w h ich  will bement ioned here ina fte r) co nta i ningtwow ay s e a ch re tain i ng bits t a ki nga va lue 0 or 1t o g eth er wi thd ata an d an  address, respect i vely; an old w ay d e t erm ini n g me an s (correspondi ngto a  primary  o ld way dete rminingci r cuit13 inthe fi rst emb o d im e nt whi ch w ill  be menti one dh ereinaf te r) for de term in ing wh ich wa y  oft h e two ways is th e abo v e  desc r ibe d old  w ay on t h e ba sis of pat terns of tw o bits  ret ained  in the  a bove d esc ri bed two wa y s; and acontr ol mean s(cor res pondin g to a  prim aryca shcontrol c i r cu i t14 inthefirst  e mbod iment whi c h will b e m e ntioned  h ere i n after) fo r invertingonl y the b its retain e d in aw ay wh ich ha s been  access e d i nthe two  wa y s  in the c ase whent hepr esen t way wh ic h ha sbee naccessed is the  above d escribed o ld way , w h ilem aintai ni ng values of  thebi t s retai n e d
 in_two ways_is the one corresponding_to the_above_described old_way._Bits LRU retained_in two ways,_respectively, are used for_determining a fact_which_way is an old way in the two ways.
Furthermore, in either a case where_a_cash hit_which_means_that data to be read_exists in cash memory arises,_or a_case where replacement which means that the data_and_addresses in cash_memory should be updated arises, a cash control section_accesses two ways, respectively, to update_an old way,_whereby_bits_LRU retained in the_respective ways are updated. As a_result, the old way shifts from_an either way where cash hit (replacement)_arose to the other way.
Meanwhile, as_mentioned above, when bits LRU_are updated_as a result of arising_of cash hit_or replacement_in a conventional_cash memory device, a cash control_section must access_to two ways, respectively. More specifically,_in_case of updating_bits_LRU,_two times_of access are_required_in such_that_first, the cash control section accesses_to_either of two ways, and then, it_accesses to the other_way._Accordingly, there has been_such a problem that a_processing speed becomes slow by an_amount of_period of_time required for accessing operations of two times in a conventional_cash memory device.
It is an object_of the present invention_to provide_a_cash memory device_by_which a_processing speed can be elevated.
In order to_achieve the_above described object, the invention described_in a first aspect_of_the invention relates to a cash_memory device utilizing an algorithm wherein_replacement is conducted with respect_to_an_old way retaining data which_has not been accessed for the_longest period of_time, characterized in that the cash memory_device_is composed of a cash memory_(corresponding_to a primary cash memory 11_in_the_first embodiment which will be_mentioned hereinafter) containing two ways each_retaining bits taking a value 0 or 1 together_with data and_an address, respectively; an old_way_determining_means (corresponding to a primary old way determining circuit 13_in the_first embodiment which_will be mentioned hereinafter) for determining which way of the_two ways is the above described old_way on the basis of patterns of two bits retained in_the above described two ways; and a control_means (corresponding to a primary cash control_circuit 14 in the_first_embodiment which will be mentioned hereinafter) for_inverting_only_the_bits retained in_a way which_has been accessed_in the_two ways in_the case_when the present_way_which has been accessed is the above described old way, while maintaining values of the bits retained