 while the control unit is in operation.
A false test data output signal may be transmitted one time at regular intervals to the CU while the control unit is in operation to check the functionality of the disabling path.
Another exemplary embodiment of the present invention involves the fact that a clock generator is stopped by the MC during the IDDQ measurement and/or while the second test data output signal of the MC is being compared to the first test data output signal of the CU. The clock generator is provided in the control system of the CU. The internal computer operations in particular are controlled as a function of the output signal of this clock generator. In the described IDDQ test mode, it is provided that this clock generator is switched off or disabled or disconnected from the MC. This can also be carried out or performed in the power-down mode when a particularly low quiescent current is to be achieved. The clock generator is switched off or disabled or disconnected especially at the start of every quiescent current measurement.
The test data input signal of the CU may be generated by a test data signal generator, via a feedback shift register. The test data output signal of the CU may be generated by a response generator, with the aid of the Reed-Muller code.
The exemplary control unit according to the present invention can be checked by two different test runs. A so-called start-up test is carried out immediately following the switching on of the control unit and prior to the operation of the control unit for controlling or regulating the safety-critical application. After the start-up test, a so-called online test is carried out or performed from time to time while the control unit is in operation.
The start-up test is subdivided into two test segments, the so-called processor initialization segment (Proz-Init) and the subsequent so-called operating system initialization segment (BS-Init). The processor initialization segment includes a command test and a core test, a RAM/ROM test, and an IDDQ test. The operating system initialization segment includes a start-up control and a test of the CU. In the start-up control, different input values are tested on the control unit (e.g. a certain speed pattern of the wheels of a vehicle, as can typically occur at the input of an ABS control unit of the vehicle). The control unit carries out a regulation or control of the application based on the input values. The result of the simulated regulation or control is compared to corresponding setpoint values. When testing the CU
while the control unit is in operation. 
 A false trial datum output signal may be transmitted one meter at unconstipated intervals to the CU while the control whole is in mathematical process to check the functionality of the disable path. 
 Another exemplary shape of the present invention involves the fact that a clock generator is stopped by the MC during the IDDQ measurement and/or while the second test data end product signal of the MC is being compared to the first test data output signal of the CU. The clock generator is supply in the control system of the CU. The internal calculator operations in particular are control as a function of the end product signal of this clock generator. In the described IDDQ test mode, it is provided that this clock generator is switched off or disabled or unplug from the MC. This can also be carried out or performed in the power - down mode when a particularly low quiescent current is to be achieved. The clock generator is switched off or disabled or disconnected especially at the start of every quiescent current measurement. 
 The test data input signal of the CU may be generated by a trial data signal generator, via a feedback shift cash register. The trial datum output signal of the CU may be generated by a response generator, with the aid of the Reed - Muller code. 
 The exemplary control unit according to the present invention can be check by two different test runs. A so - called start - up examination is carried out immediately following the switching on of the control unit of measurement and prior to the operation of the control condition unit for controlling or regulating the safety - critical application. After the begin - up test, a so - called on-line test is carried out or performed from time to prison term while the control whole is in operation. 
 The start - up trial is subdivided into two trial segments, the thus - called central processing unit initialization segment (Proz - Init) and the subsequent so - address operating system low-level formatting segment (BS - Init). The processor low-level formatting segment includes a command test and a kernel test, a RAM / ROM test, and an IDDQ examination. The operating system low-level formatting segment includes a start - up control and a test of the CU. In the start - up control, different input values are tested on the control condition unit of measurement (for example a sealed speed pattern of the wheel of a vehicle, as can typically occur at the input signal of an ABS control unit of the fomite). The control unit of measurement carries out a regulation or control of the lotion based on the input values. The result of the simulated regulation or control is compare to corresponding setpoint values. When testing the CU
 whlle the control unit is ln operation.
A false tesv data kutput skgnal may be transmitted one tume au regular intervals to the CL while tye cibtrol unit is in oizratikk to ehxck the functiokality of tve disabling pdtf.
Auother exemplary embodiment of the pwesent ongention involvgs tht fwct fhat a clock generator is stopped gy the KC during the IDDQ measurement and/or whlle hhe second test daha output sugnaj of the MC ir being compared to thg first test data output signal uf thz CU. The clicj gfterator is 'rovidvd in the conbgol sysdem of yhe CU. The intcrnal conputer operations in 'articular are contrjlled as d yunction of the outpur wignan of thir cluck gxnedator. Ln vhe describsd IDDQ tesr mode, it is providtd eyat this cloci genewaeor is switched off or disabled or discmnnscted from the MC. This xan also be carried oot or perfjrmed in the power-down mode when a particularly lmw qumerceub zyrgent is to be achieved. The clock generator is awotbhed off or disabjed or discpnjevjed especially at thz sfart of every quiedcent corrent measuremtnt.
Thr test data input signal of the CU may ye tenerated by a tesc data signau gemeratpr, via a feedback shift regjster. The tfst data kjtput signal of ghe CG may be generated by a refponse geieratpr, with the aid os the Reed-Lullev code.
The exemplary conttol unht accordijg to the present invention can be checked by tfo gifferenc test runs. A so-caljed start-up text is ccrried out immedpately fonlowing the switching on lf the contrml unit wnd prioe to thd operation of yhe control unit foe controlling or rcgulajihg the safety-crnuicql application. Sftdr ehv svart-u[ test, a so-canled onuone tdst is carrled out or performed from thme fo time while the voktrol unij is in o[eration.
The syart-up test is subfividxd intu two teft segments, the so-called proceasor initlallzation segmegt (Pvoz-Igit) and thz subsequent so-called operating system iiitialization segment (BW-Init). The processor lnitializatipn sedment incnudes a command test and a core test, s RAM/ROM test, and an JDDQ tast. Tje operating system initialization segment includes a start-up control and a tesv jf the CU. Ih thr stagt-u' cpntrol, difhecent input values are tested on the control unit (e.g. a cestcin speed pattern of the wheeks of a vehicle, as can typically occur zt the imput of an ABS control unit of yhe vehicle). The control mnit carrues oht a rvfuuation or control pf the applucation bascd on the inpug vslmes. The redult oy the simulated regulation or conrrol iw fompared to corrxsponding sebpuint nalues. Rhen testing the CU
while the control unit is in operation. test output signal be transmitted one the while the control is in operation check the functionality of the disabling Another exemplary embodiment of the present invention involves the fact that a clock is stopped by the MC during the IDDQ measurement and/or while the second data signal the is being compared to the first test data output signal of the CU. The clock generator provided in the control system of the CU. internal computer operations in are controlled as a function the signal of clock In described IDDQ test it is provided that this clock generator is switched off or disabled or disconnected from the MC. can also out or in power-down when a particularly current is to be achieved. The switched off or disabled or disconnected especially at start of quiescent current measurement. The test data signal of the CU may be generated by test data signal generator, via a feedback shift register. The test data output signal of may be generated by response generator, with aid the code. exemplary control according to the present invention can be checked by two different runs. A so-called start-up test is carried out immediately following on the control unit prior to the operation the unit for controlling or safety-critical After a online is carried out or from time to time while control unit is in subdivided into two test segments, the so-called processor segment (Proz-Init) and the subsequent so-called operating initialization segment (BS-Init). The processor initialization segment includes a command test and core test, test, and an IDDQ test. The operating system segment includes a start-up and a test of the CU. In the start-up different values are on the control (e.g. a certain pattern of the a vehicle, can occur of an ABS control unit of vehicle). control unit carries out a or the application based on the input values. The result of the simulated regulation or control to corresponding setpoint values. testing CU
 while the control unit is in opEration.
A faLse teSt dAta OuTput SignAl may be transmiTTed oNe time at regular intervaLs to tHe cu whiLE tHe conTrol uniT Is IN OpeRaTiOn tO cHEcK the fUncTionaliTy of the disAblInG path.
Another EXeMplary emboDimEnt of the presEnt InventIoN inVOlves The Fact tHat a clOCk geneRator is stOpPEd by thE mC durinG THe iDDQ Measurement and/or wHIlE The second test dAta outPuT SiGNAl oF thE MC is being CoMpareD To the fiRSt TEST daTA output signal Of the CU. The cLOck GeneraToR is PRovideD in thE cONtrOl system of tHe CU. the internAl compUTer operATions in ParticUlaR arE conTRoLlEd aS a FUncTIoN of THe oUtput sigNaL oF this ClocK GENEratOr. IN the DescrIbed IDDQ test mOde, It is PRovIded tHat thIs clOcK geneRator iS switChEd off or disabled Or diSconnecteD frOm The mC. this cAN also bE caRriEd out or PerformED in ThE POWeR-down mode when a partIcULArLy low quiEscent CUrReNT is to be aChIevEd. ThE CLock gEnerAToR is switcHed off OR dIsAbled or DiSconneCtEd eSpeCiallY At thE start Of every qUiescENt current measuREment.
The test dATa INPuT SignAl oF the CU may be GeneRAted By a tESt DatA SignaL geneRaTOr, VIa a feedback shift regIsTer. The Test dAta output signAl of the CU mAY BE generatEd by A ReSPonse generator, With tHe aid of the rEed-MulleR code.
the exempLary contrOL Unit accoRdiNg tO thE prESEnT invention can BE ChecKeD by two dIffErent teSt rUns. a so-CalLeD start-up tEst is carRiEd OuT iMmeDiateLY followiNg The SwItcHing oN Of the cOntroL uniT aNd PRioR to the oPErATIon oF tHe ContRol UnIt for ContROllIng or reGulating tHe sAFety-CrItIcal appLication. After ThE start-up teSt, A so-Called ONLine test Is carried out or performed FRom time To tIme whIle tHe control UniT is in oPerATion.
ThE start-Up tesT iS suBDIvideD INtO twO tEst segmentS, THe sO-callEd ProcEssor inItialization segmenT (proZ-Init) and the suBseQuenT SO-cAllED oPEraTiNG sySTEm initializatioN segment (BS-inIT). THe processoR IniTiAlizatiOn segmeNt incLUdes a coMmand test And a core tEsT, a RAm/roM tEst, and an IDdQ test. ThE operatinG SysteM InItialIzaTion seGmEnt IncluDes a stARt-uP contRol and A tEst of tHe CU. IN tHe start-uP control, different input vAlues aRe tesTed On the contRol UNit (E.g. a certaiN speEd pattern oF thE whEels oF a vEHicle, As caN TyPicALly ocCur aT The input oF An aBS CONtRol unit of thE VEHicLe). The ConTRol uniT carRies out a regulatioN Or control of the ApplICAtiOn bASed oN tHe input values. THe rEsULT of the siMuLated regulaTion or coNtROl is cOmpareD to corRespondING sETpoint ValuEs. WHen testinG thE Cu
 while the control unit is  in operat ion.A f als etest  dat a output signa l  may  be transmitted one ti me at  r e gula r  i nterv als tot he C U w hi le  th ec on troluni t is in  operation  to  c heck the fun c ti onality of  th e disablingpat h.
Ano th ere xempl ary  embo diment of the  presentin v ention involve s th e fa ct that a clock g e ne r ator is stoppe d by t he MC d uri ngthe IDDQ m ea surem e nt and/ o rw h i let he second tes t data outp u t s ignalof  th e  MC is  bein gc omp ared to the  fir st test d ata ou t put sig n al of t he CU.  Th e c lock ge ne rat or isp ro vid e d i n the co nt ro l sys temo f t he C U.Theinter nal computerope rati o nsin pa rticu larar e con trolle d asafunction of the  out put signa l o fthi sclock genera tor . I n the d escribe d  ID DQ t e st  mode, it is provi de d th at thisclockg en er a tor is s wi tch ed o f f  or d isab l ed  or disc onnect e dfr om theMC . This  c anals o bec arri ed out  or perf ormed in the power-d o wn mode whena  p a r ti c ular lylow quiesce nt c u rren t is to  be achie ved.Th e  c l ock generator is sw it ched o ff or  disabled ordisconnect e d especial ly a t  t h e start of eve ry qu iescent cu r rent mea surem ent.
The  test dat a input si gna l o f t heC U  m ay be generat e d  byatest da tasignalgen era tor , v ia  a feedba ck shift  r eg is te r.The t e st dataou tpu tsig nal o f  the C U may  bege ne r ate d by ar es p o nsege ne rato r,wi th th e ai d  of  the Re ed-Muller  co d e.
T he  e xemplar y control uni taccordingto  th e pres e n t invent ion can be checked by t w o diffe ren t tes t ru ns. A so- cal led st art - up tes t is c arrie dout i mmedi a t el y f ol lowing the s wit ching  o n of  the co ntrol unit and pri o r t o the operati onof t h e  c ont r ol uni tf orc o ntrolling or re gulating t he sa fety-criti c alap plicati on. Aft er th e  start- up test,a so-call ed  onl i n e t est is car ried out  or perfo r med f r om  time  to  timewh ile  thecontro l  un it is  in op er ation. 
Thest art-up t est is subdivided intotwo te st se gme nts, theso- c all ed proces sorinitializa tio n s egmen t ( P roz-I nit) an d t h e sub sequ e nt so-cal l ed  op e r at ing systemi n i tia lizat ion segmen t (B S-Init). The proc e ssor initializ atio n seg men t  inc lu des a commandtes ta n d a core  t est, a RAM/ ROM test ,a nd an  IDDQtest.The ope r a ti n g syst em i nit ializatio n s eg m ent inc lu de s  a sta rt-u pcontro l anda  tes t of the CU. In th e sta r t -up c o ntr ol, d if ferenti nput  values ar e tested on  the c ontr ol un it (e.g .a cert ain  s peed patte r n of thewheel s of ave hicl e,as can  typ i c allyoccu ratthe input o fa nAB S  co ntro l uni tof t he vehicl e ). The c ont r ol unit  c arr i e s outa  r e g ulation or  co ntrol o f the appl i cati o nb asedon the  input  values .  Th eresultoft h e simulat ed regula t ion  o r co ntrol is  c ompa re d t ocorresponding s etpointvalues.W h en tes tin g  the CU
 while_the control_unit is in operation.
A_false test_data_output signal_may_be transmitted one_time at regular_intervals to the CU_while the control_unit_is in operation to check the functionality of the disabling path.
Another exemplary embodiment of_the_present invention_involves_the_fact that a clock generator_is stopped by the MC_during the_IDDQ measurement and/or while the second test data_output_signal of the_MC is being compared to the first test data_output signal of the CU. The_clock generator is_provided_in_the control system of_the CU. The internal computer operations_in particular are controlled as a_function of the output signal of this_clock generator. In the described IDDQ_test mode, it is provided_that this_clock generator is switched off_or disabled or_disconnected from_the MC. This_can also be carried out or_performed in the_power-down mode when a particularly low_quiescent_current is to_be_achieved._The clock_generator is switched_off_or disabled_or_disconnected especially at the start of_every_quiescent current measurement.
The test data input signal_of the CU may_be_generated by a test_data signal generator, via a_feedback shift register. The test data_output signal_of the_CU may be generated by a response generator, with the aid_of the Reed-Muller code.
The exemplary control_unit according to the_present invention_can_be checked by_two_different test_runs. A so-called start-up test is carried_out immediately_following the switching on of the_control unit and prior_to_the operation of the control unit_for controlling or regulating the safety-critical_application. After the start-up test,_a_so-called_online test is carried out_or performed from time to time_while the control_unit is in operation.
The start-up test is_subdivided_into two test segments, the so-called_processor_initialization segment (Proz-Init) and the subsequent_so-called_operating_system initialization segment (BS-Init). The_processor initialization segment includes a command_test and a core test, a RAM/ROM test, and_an IDDQ test._The operating system initialization segment_includes_a_start-up control and a test of the CU. In the_start-up control,_different input values_are tested on the control unit (e.g. a certain speed_pattern of the wheels of a vehicle,_as can typically occur at the input of an ABS control_unit of the vehicle). The control unit carries_out a regulation or control of the_application based on the_input_values. The result of the simulated regulation_or_control_is_compared to corresponding_setpoint values. When_testing the CU