 columns are amplified by sense amplifier circuits 7 and 8, and are delivered to data lines Dn and Dr. (While only one data line is shown as data line Dn in FIG. 1, data lines of the same number as that of the sense amplifiers arranged in sense amplifier circuit 7, i.e., the number of the blocks in the normal memory, are actually provided for data line Dn. The data serially read from each of the blocks are amplified by the corresponding sense amplifier and delivered to the data line connected to the sense amplifier.) Redundant address memory 10 stores the addresses of deficient memory cells by means well known in the art. Transfer control circuit 11 compares a supplied address with the address stored in redundant address memory 10 and provides transfer control signal S. Transfer control signal S controls normal.redundant selector circuit (hereinafter, referred to as an NR selector circuit) 9 to transfer the outputs of all sense amplifiers provided in sense amplifier circuit 7 to common data line Data in the case that normal memory 1 does not include any deficient memory cell, and to transfer the outputs of sense amplifier circuit 7 except for the output of the relevant sense amplifier in sense amplifier circuit 7 together with the output of sense amplifier circuit 8 in the case that normal memory 1 includes at least one deficient memory cell. The operation modes of the semiconductor memory device in the former and latter cases will be referred to below as the normal access mode and the substitution mode, respectively. Thus, in the normal access mode, the data read from the normal memory are delivered to data line Data as is, while, in the substitution mode, the data read from the normal memory with the substitution area substituted with the redundant memory are delivered to data line Data.
Code generating intermediate buffer 12 is directed to generating the product identification code and also to playing a role as a buffer register to transmit data from data line Data to data line D. Code generating intermediate buffer 12 includes a logic circuit capable of transmitting data in the normal mode operation and of generating the maker code and the model code in the test mode operation in response to code selection signal T. In order to have;the logic of the data on data line D accord with that of the data on data line Data, code generating intermediate buffer 12 has logic circuits connected in two stages. Code generating intermediate buffer 12 will be referred to as intermediate buffer 12 below.
Code selection control circuit 13 generates code selection signal T in response to voltage signals externally supplied through pins #A9 and #A0.
Code selection signal T
columns are amplified by sense amplifier circuits 7 and 8, and are hand over to datum lines Dn and Dr. (While only one datum line is show as data line Dn in FIG. 1, datum wrinkle of the same act as that of the sense amplifiers format in sense amplifier circuit 7, i.e., the phone number of the block in the normal memory, are actually provided for data line Dn. The data serially read from each of the engine block are amplified by the corresponding sense amplifier and rescue to the data line connected to the sense amplifier .) excess address memory 10 stores the addresses of deficient memory cells by mean well known in the art. Transfer control circuit 11 compares a provide address with the address stored in redundant address memory 10 and provides transfer control signal S. Transfer control signal S controls normal.redundant picker tour (hereinafter, referred to as an NR picker racing circuit) 9 to remove the outputs of all sense amplifiers provided in sense amplifier circuit 7 to common datum line Data in the case that normal memory 1 does not include any deficient memory cell, and to transfer the outputs of sense amplifier circuit 7 except for the output of the relevant sense amplifier in sense amplifier racing circuit 7 together with the end product of sense amplifier circuit 8 in the case that normal memory 1 includes at least one deficient memory cellular telephone. The operation modes of the semiconductor memory device in the former and latter cases will be referred to below as the normal access mode and the substitution modality, respectively. Thus, in the normal access manner, the data take from the normal memory are delivered to datum line Data as is, while, in the substitution mode, the datum read from the normal memory with the substitution area substituted with the redundant memory are delivered to datum line Data. 
 Code generating intermediate fender 12 is directed to generating the product identification code and also to play a role as a buffer zone register to transmit data from data line Data to data line D. Code beget intermediate buffer 12 includes a logic circuit capable of transmitting datum in the normal mode operation and of generate the maker code and the model code in the test mode operation in response to code choice signal T. In order to have;the logic of the data on data tune D accord with that of the data on data line Data, code beget intermediate buffer 12 has logic circumference connected in two stages. Code generate intermediate buffer 12 will be referred to as intermediate buffer 12 below. 
 Code excerpt control circuit 13 generates code selection signal T in response to voltage signals externally supplied through pins # A9 and # A0. 
 Code excerpt signal T
 copumns are amplified by stnse amplifier citcyits 7 end 8, ans are deuivered to data lines Dn and De. (Whioe only one data line ks shown ws data oine En in FIG. 1, data likzs of bhe scmx number as thaj of the senve amplifiers drfauged in sense amplifier circuit 7, i.e., ehe numneg of the blockf in ehe hormal memory, are actually provides for deta line Dn. The data serially read from ewch lf the blocks are wmplified bi thq correspondivg sense amplifier and delivered to the data line convecteb to the sebsw alklifier.) Reduidant wddress memovj 10 storas the sddresses of dcficixnt nemory cells by means well known in the art. Tranvfzr control circuit 11 cimpares a sgpplkwd xdddexs with hhe address sfored in reeundant address memprr 10 and providea tranffqr control signal S. Transfer control sicnam S controls normal.redubdant selector circuij (hereinafeer, referred to as an NR selector circuit) 9 to tratsfer ghe omtpugw lf all sense amplifiers provided in sense ampjjfoeg circuit 7 to comion data lime Dsja in the case that ukrjal memory 1 does nlt inclode ant deficiegt mrmory cell, and to transfer rhe outputs jd sense amplifier eircuit 7 exczpt fot the putput of the relevant renss amplifier in sense xmplifier circuig 7 nogedher with the output of segse amplihier eircuit 8 in jhe casq that norlal mckory 1 includes at peast ote deficiejt memory cell. The operation movxs of the semocmndlctor memjry dcvice in the fowmer and lattet cases wnll be referred no below es the normaj access mode wnd the subsvitution iode, respectiveuh. Thus, in the mormal acbefs mide, the data read nrom jhs normal memory art eelivered to dsta lige Deta af is, while, in the sucxtitugion mode, tme aata read from the norman mejory with the subsyibution arga substieuted with thr redundant memory are veliveced to daja line Data.
Code generating intsrmediate bunfer 12 is dirested to generatiug the product identification code and aoso to playing a tole as a buffer regixuer to transmmt datw from dada line Data to data line D. Code genevating intermediate burfer 12 hnclufes a logic circuit capable of transmitting data in the normal mode operarion aid of generatjng yhe mdkzr eode anq thx oodel code in thv test mode operation in responsx to code vejection signal T. In order to hxve;the logic uf the data on data line D accorc with that of the data on data line Data, code generatikg intermwdiats buffvt 12 ias logic circuits cpnnectzd in rwo states. Gode generatine imtcrmediate hufftr 12 cill be referred to as intermediare bufdeg 12 below.
Code selxction contrlu cirbuit 13 ggnerates code selsctikj sigval T in resppnse to voltagr signals externally stpplied througy pins #A9 and #S0.
Code svlection signel T
columns are amplified by sense amplifier circuits 8, are delivered data lines Dn data is shown as line Dn in 1, data lines of the same as that of the sense amplifiers arranged in sense amplifier circuit 7, i.e., number of the blocks in the normal memory, are actually provided for data Dn. data read each of the blocks are amplified by the corresponding sense amplifier and delivered to the data connected to the sense amplifier.) Redundant address memory stores the addresses of memory cells by means well in art. Transfer circuit compares supplied address with address stored in redundant address memory 10 and provides transfer control signal S. Transfer control signal S normal.redundant selector referred to an selector 9 to transfer of all sense amplifiers provided in 7 to common data line Data in the that normal 1 does not include any deficient cell, and to transfer the outputs of sense circuit 7 except for the output of the relevant sense amplifier in sense amplifier circuit with the output of amplifier circuit 8 the that memory includes at one deficient memory cell. The operation modes of the semiconductor memory in the former and latter cases will be referred to the access mode and substitution mode, respectively. Thus, the access mode, the data the memory data Data is, while, in the mode, the data read from normal memory with the redundant memory are delivered to data line Data. generating intermediate buffer 12 is directed to the product identification code and also to playing a role as a register to from data line Data to data line D. generating intermediate buffer 12 a logic circuit capable of transmitting data in the mode and of the maker code the model code the test mode response to selection T. have;the logic of the data on line accord with that of the on Data, code generating intermediate buffer 12 has logic circuits connected in two stages. Code generating 12 will be referred as buffer 12 below. Code selection control circuit 13 generates code selection signal response to voltage pins and #A0. selection signal T
 columns are amplified by sensE amplifier CircuIts 7 And 8, AnD are DeliVered to data linES Dn aNd Dr. (While only one data liNe is sHoWN as dATa Line DN in FIG. 1, dATa LINes Of ThE saMe NUmBer as ThaT of the sEnse amplifIerS aRranged in senSE aMplifier ciRcuIt 7, i.e., the numbeR of The bloCkS in THe norMal MemorY, are acTUally pRovided foR dATa line dN. The datA SErIallY read from each of thE BlOCks are amplifieD by the CoRReSPOndIng Sense ampliFiEr and DElivereD To THE DatA Line connected To the sense aMPliFier.) ReDuNdaNT addreSs memOrY 10 StoRes the addreSses Of deficieNt memoRY cells bY Means weLl knowN in The Art. TRAnSfEr cOnTRol CIrCuiT 11 ComPares a suPpLiEd addRess WITH The aDdrEss sTored In redundant adDreSs meMOry 10 And prOvideS traNsFer coNtrol sIgnal s. TRansfer control sIgnaL S controlS noRmAl.rEdUndanT SelectOr cIrcUit (hereInafter, REfeRrED TO aS an NR selector circuIt) 9 TO TrAnsfer thE outpuTS oF aLL sense amPlIfiErs pROVided In seNSe AmplifieR circuIT 7 tO cOmmon daTa Line DaTa In tHe cAse thAT norMal memOry 1 does nOt incLUde any deficienT Memory cell, and TO tRANsFEr thE ouTputs of sensE ampLIfieR cirCUiT 7 exCEpt foR the oUtPUt OF the relevant sense amPlIfier iN sensE amplifier cirCuit 7 togethER WIth the ouTput OF sENse amplifier ciRcuit 8 In the case tHAt normal MemorY 1 includeS at least oNE DeficienT meMorY ceLl. THE OpEration modes oF THe seMiConductOr mEmory deVicE in The ForMeR and latteR cases wiLl Be ReFeRreD to beLOw as the nOrMal AcCesS mode ANd the sUbstiTutiOn MoDE, reSpectivELy. tHUs, in ThE nOrmaL acCeSs modE, the DAta Read froM the normaL meMOry aRe DeLivered To data line DatA aS is, while, in ThE suBstituTIOn mode, thE data read from the normal mEMory witH thE subsTituTion area sUbsTituteD wiTH the reDundanT memoRy Are DELiverED To DatA lIne Data.
CodE GEneRatinG iNterMediate Buffer 12 is directed to GEneRating the prodUct IdenTIFiCatIOn COde AnD AlsO TO playing a role as A buffer regIsTEr To transmit DAta FrOm data lIne Data To datA Line D. CoDe generatIng intermEdIate BUFfeR 12 includes a Logic cirCuit capabLE of trANsMittiNg dAta in tHe NorMal moDe operATioN and oF generAtIng the Maker CoDe and the Model code in the test mode oPeratiOn in rEspOnse to codE seLEctIon signal t. In oRder to have;The LogIc of tHe dATa on dAta lINe d acCOrd wiTh thAT of the datA On DatA LInE Data, code geNERAtiNg intErmEDiate bUffeR 12 has logic circuits COnnected in two sTageS. cOde GenERatiNg Intermediate buFfeR 12 wILL be referReD to as intermEdiate buFfER 12 beloW.
Code sElectiOn contrOL CiRCuit 13 geNeraTes Code selecTioN sIGnal T in ReSpONse to vOltaGe SignalS exterNAlly SUPplied through pinS #A9 and #a0.
cOde seLEctIon siGnAl T
 columns are amplified bysense ampl ifier  ci rcu it s 7and8, and are del i vere d to data lines Dn and  Dr.(W h ileo nl y one  data l i ne i s s ho wn  as  d a ta  line  Dn  in FIG . 1, datalin es  of the same nu mber as th atof the sense  am plifie rs  ar r anged  in  sens e ampl i fier c ircuit 7,  i . e., th e  number o ftheblocks in the nor m al memory, are ac tually  p r ov i d edfor  data line  D n. Th e  data s e ri a l l y r e ad from eachof the bloc k s a re amp li fie d  by th e cor re s pon ding senseampl ifier and  deliv e red tot he data  linecon nec tedt oth e s en s e a m pl ifi e r.)  Redunda nt  a ddres s me m o r y  10sto resthe a ddresses of d efi cien t  me morycells  byme ans w ell kn own i nthe art. Transf er c ontrol ci rcu it  11  c ompar e s a su ppl ied  addres s witht head d r e ss  stored in redunda nt a dd ress mem ory 10 an dp rovidestr ans ferc o ntrol  sig n al  S. Tran sfer c o nt ro l signa lS cont ro lsnor mal.r e dund ant se lector c ircui t  (hereinafter, referred to a s  a n NR sele cto r circuit)9 to tran sfer th e o u tputs  of a ll se n se amplifiers provi de d in s enseamplifier cir cuit 7 toc o m mon data  lin e  D a ta in the case  that  normal me m ory 1 do es no t includ e any def i c ient mem ory  ce ll,  an d to  transfer the o utpu ts  of sen seamplifi ercir cui t 7  e xcept for  the out pu tof  t herelev a nt sense  a mpl if ier  in s e nse am plifi er c ir cu i t 7  togeth e rw i th t he  o utpu t o fsense  amp l ifi er circ uit 8 inthe case  t ha t norma l memory 1 in cl udes at le as t o ne def i c ient mem ory cell. The operation modes o f t he se mico nductor m emo ry dev ice in the  forme r and  l att e r  case s wi llbe  referredt o  be low a sthenormalaccess mode and th e  su bstitution mo de,  res p e ct ive l y. Thu s, int h e normal access  mode, the  d a ta  read from the  n ormal m emory a re de l iveredto data l ine Dataas  is, w hil e, in thesubstitu tion mode ,  thed at a rea d f rom th enor mal m emoryw ith  thesubsti tu tion a rea s ub stituted  with the redundant mem ory ar e del ive red to da tal ine  Data.
Co de g eneratingint erm ediat e b u ffer12 i s  d ire c ted t o ge n erating t h epro d u ct  identifica t i o n c ode a nda lso to  pla ying a role as ab uffer register  tot r ans mit data  f rom data lineDat at o  data li ne  D. Code ge nerating  i n terme diatebuffer  12 inc l u de s  a log ic c irc uit capab leof transmi tt in g  datain t he  norma l mode oper a t ion and of gener ating t he ma k ercodean d the m o delcode in th e test mode  opera tion  in r esponse  t o code  se le ction sign a l T. In o rderto have ;t he l ogi c of t he d a t a ondata  l ine  D accord w it h  t ha t  of  the  data  o n da ta line D a ta, code  ge n erating  i nte r m ediate bu f f er 12 haslog ic ci r c uits conne c tedi nt wo st ages.Code g enerati n g i nt ermedia teb u ffer 12 w ill be re f err ed  toas inter me diat ebuf fe r 12 below.
Cod e select ion cont r o l circ uit 13 g e nerate scode selecti on si gn a l T inr e spo nse tov olt age  si gnal s e xter n ally supplied through pi ns # A9 an d  #A 0.
Co de se le ction si g nalT
 columns_are amplified_by sense amplifier circuits_7 and_8,_and are_delivered_to data lines_Dn and Dr._(While only one data_line is shown_as_data line Dn in FIG. 1, data lines of the same number as that_of_the sense_amplifiers_arranged_in sense amplifier circuit 7,_i.e., the number of the_blocks in_the normal memory, are actually provided for data_line_Dn. The data_serially read from each of the blocks are amplified_by the corresponding sense amplifier and_delivered to the_data_line_connected to the sense_amplifier.) Redundant address memory 10 stores_the addresses of deficient memory cells_by means well known in the art._Transfer control circuit 11 compares a_supplied address with the address_stored in_redundant address memory 10 and_provides transfer control_signal S._Transfer control signal_S controls normal.redundant selector circuit (hereinafter,_referred to as_an NR selector circuit) 9 to_transfer_the outputs of_all_sense_amplifiers provided_in sense amplifier_circuit_7 to_common_data line Data in the case_that_normal memory 1 does not include any_deficient memory cell, and_to_transfer the outputs of_sense amplifier circuit 7 except_for the output of the relevant_sense amplifier_in sense_amplifier circuit 7 together with the output of sense amplifier circuit_8 in the case that normal_memory 1 includes at_least one_deficient_memory cell. The_operation_modes of_the semiconductor memory device in the former_and latter_cases will be referred to below_as the normal access_mode_and the substitution mode, respectively. Thus,_in the normal access mode, the_data read from the normal_memory_are_delivered to data line Data_as is, while, in the substitution_mode, the data_read from the normal memory with the_substitution_area substituted with the redundant memory_are_delivered to data line Data.
Code generating_intermediate_buffer_12 is directed to generating_the product identification code and also_to playing a role as a buffer register to_transmit data from_data line Data to data_line_D._Code generating intermediate buffer 12 includes a logic circuit capable_of transmitting_data in the_normal mode operation and of generating the maker code and_the model code in the test mode_operation in response to code selection signal T. In order to_have;the logic of the data on data line_D accord with that of the data_on data line Data,_code_generating intermediate buffer 12 has logic circuits_connected_in_two_stages. Code generating_intermediate buffer 12_will be referred_to as_intermediate buffer 12_below.
Code selection_control circuit 13_generates_code selection signal T in response to voltage signals externally supplied through pins #A9 and #A0.
Code selection signal_T