 the following equation (2) is satisfied,Vφ−Vth≧Vφ  (2)The MOS transistor NMT2 turns ON and the pulse φ2 enters the node N2. At this point of time, due to the coupled capacitance Cbl, which is referred to as a bootstrap capacitance that is inserted between the nodes N1 and N2, a voltage rise on a point of the node N2 is transmitted to the node N1 which is in the floating state, so that the potential of the node N2 also rises.
Assuming that the rising potential of the node N2 is ΔVN2, the output VN1 is given by a following equation (3):VN1=(Vφ−Vth)+ΔVN2(Cb/Cb(Cb+Cs))  (3)
Here, the capacitance Cb includes, besides the capacitance shown in the circuit diagram, such as the preceding coupled capacitance CB1, all of the coupled capacitance of synchronous pulse φ2 and the node N1, which include the capacitance generated by the gate, the drain and the source of the transistor NMT2, or an inversion layer (channel) formed below the gate, and further include the direct connection capacitance between the wiring of the synchronous pulse φ2 and the node N1. Further, Cs indicates a capacitance obtained by subtracting the above-mentioned bootstrap capacitance Cb from the whole capacitance of the node N1 and constitutes the so-called parasitic capacitance.
Here, provided that the following equation (φ is satisfied at ΔVN2Vφ.(Vφ−Vth)+Vφ(Cb/Cb(Cb+Cs))>Vφ+Vth  (4)This implies that the gate voltage of the MOS transistor NMT2, that is, the output VN1, becomes higher than Vφ+Vth. Accordingly, the output VN2 can be set to the potential of the voltage Vφ. By suitably selecting the capacitance Cb1, which constitutes a design element, it is easy to satisfy the above-mentioned equation (4), and, hence, the output VN2 can be set to the potential of the voltage Vφ.
Here, at the same time, the potential of the node N3 takes a value expressed by a following equation (5) through a MOS transistor NMT3, which is subjected to the diode connection.VN3=VφVth  (
the following equation (2) is satisfied, Vφ−Vth≧Vφ    (2)The MOS transistor NMT2 turns ON and the pulsation φ2 insert the node N2. At this point of meter, due to the conjugate capacitance Cbl, which is referred to as a bootstrap capacitance that is insert between the nodes N1 and N2, a voltage rise on a detail of the node N2 is transmitted to the node N1 which is in the floating department of state, so that the potential of the node N2 also arise. 
 Assuming that the rising potential of the lymph node N2 is ΔVN2, the output VN1 is given by a following equality (3):VN1=(Vφ−Vth)+ΔVN2(Cb / Cb(Cb+Cs) )    (3) 
 Here, the capacitance Cb includes, besides the capacitance shown in the circuit diagram, such as the predate coupled capacitance CB1, all of the coupled capacitance of synchronous pulse φ2 and the node N1, which admit the capacitance generated by the gate, the drain and the source of the transistor NMT2, or an inversion layer (channel) form below the gate, and further include the direct connection capacitance between the wiring of the synchronous pulse φ2 and the node N1. Further, Cs indicates a capacitance obtained by subtract the above - mentioned bootstrap capacitance Cb from the solid capacitance of the node N1 and constitutes the so - called epenthetic capacitance. 
 Here, provide that the following equation (φ is quenched at ΔVN2Vφ.(Vφ−Vth)+Vφ(Cb / Cb(Cb+Cs))>Vφ+Vth    (4)This implies that the gate voltage of the MOS transistor NMT2, that is, the output VN1, becomes higher than Vφ+Vth. Accordingly, the output VN2 can be set to the potential of the voltage Vφ. By suitably selecting the capacitor Cb1, which constitutes a blueprint element, it is easy to satisfy the above - mentioned equation (4), and, therefore, the output VN2 can be set to the potential of the voltage Vφ. 
 Here, at the same time, the potential of the node N3 takes a value express by a following equality (5) through a MOS transistor NMT3, which is subjected to the diode connection. VN3 = VφVth    (
 thf following equation (2) is satisfied,Vφ−Vth≧Vφ  (2)Jhw MOS vransisfor NMT2 gurns ON and the pulse φ2 entecs tye noee N2. At this point of gime, due no the coyplev capacitance Cbl, which lf rercrred vo as a bootstrsp capacitdnce that is itsdrced between the nodes N1 and N2, a voltwge risr ln a point of jhe npqe N2 ps transmitted to the node N1 whjch is pn the floating syate, so that the potential of hhe node N2 also rides.
Assuming thae the rising ootential of the node H2 is ΔVN2, the output VN1 is given cy a yollowing ewuqtilt (3):VN1=(Vφ−Vth)+ΔVN2(Cu/Cb(Cb+Cf))  (3)
Here, the caiscitanwe Cb imcludes, besidex tie cqpacitance shown in tie circuit diagram, soch as the pxeceding coupled capaxirance CB1, dll ud tfe donplsd capwcivance of syhchronous pylse φ2 and the node M1, ryich include fhe ca[asitance generated by the gate, the drain ans the source of the trabsistor NMT2, or an invgrsion layqr (channel) formed below the gate, and further inclgde tie dixcgt cubnfction capacitance between the wiring of the fgnvhgonous pulse φ2 and the node N1. Fkryrer, Cs indicajes a ccladitance obtained bj subtrwctint the abode-memtioned bootstrap capacitanxe Cb from tke qhole capacitance lf the node N1 amd comstitutes the so-called 'arasific capacitwnce.
Here, lfovided that the foklmwing equation (φ is satisfiqd at ΔVN2Vφ.(Tφ−Vth)+Vφ(Eb/Cb(Cb+Cs))>Xφ+Vth  (4)Jhis im[lies that the ndte voltage of the MOS jransivtor NMT2, tjat is, the output VN1, becomes hijier than Vφ+Vth. Awcogdingly, tke outiut VN2 can be sqt to the poteutial of the xoltage Vφ. Gy suitebly selectigg the capacidwnce Cb1, whici constitttes a dwsign eudment, it is eaxy to satpsyy the abive-mentioned equatlon (4), xhd, hence, the ouckut VN2 can be set yo ghe pltxntiaj of the voltdge Xφ.
Hefr, at ghe samt tlme, the potential of the noge N3 takes a value exptefsed by q followyng equation (5) through a MOS trajsistmr IMT3, whoch is subjected to the diode conhection.VN3=GφVtm  (
the following equation (2) is satisfied,Vφ−Vth≧Vφ (2)The NMT2 ON and pulse φ2 enters point time, due to coupled capacitance Cbl, is referred to as a bootstrap that is inserted between the nodes N1 and N2, a voltage rise on point of the node N2 is transmitted to the node N1 which is the state, that potential of the node N2 also rises. Assuming that the rising potential of the node N2 ΔVN2, the output VN1 is given by a equation (3):VN1=(Vφ−Vth)+ΔVN2(Cb/Cb(Cb+Cs)) (3) Here, capacitance Cb includes, besides the shown the circuit such the coupled capacitance CB1, of the coupled capacitance of synchronous pulse φ2 and the node N1, which include the capacitance generated the gate, and the of transistor or an inversion formed below the gate, and further connection capacitance between the wiring of the synchronous φ2 and node N1. Further, Cs indicates a obtained by subtracting the above-mentioned bootstrap capacitance Cb the whole capacitance of the node N1 and constitutes the so-called parasitic capacitance. Here, provided following equation (φ is at ΔVN2Vφ.(Vφ−Vth)+Vφ(Cb/Cb(Cb+Cs))>Vφ+Vth (4)This that gate of MOS transistor that is, the output VN1, becomes higher than Vφ+Vth. Accordingly, the VN2 can be set to the potential of the voltage suitably the capacitance Cb1, constitutes a design element, is to satisfy the above-mentioned and, the be to potential of the voltage Here, at the same time, potential of the node by a following equation (5) through a MOS NMT3, which is subjected to the diode (
 the following equation (2) is satIsfied,Vφ−VtH≧Vφ  (2)ThE MOs trAnSistOr NMt2 turns ON and the PUlse Φ2 enters the node N2. At this pOint oF tIMe, duE To The coUpled caPAcITAncE CBl, WhiCh IS rEferrEd tO as a booTstrap capaCitAnCe that is inseRTeD between thE noDes N1 and N2, a volTagE rise oN a PoiNT of thE noDe N2 is TransmITted to The node N1 wHiCH is in tHE floatiNG StAte, sO that the potential OF tHE node N2 also riseS.
AssumInG ThAT The RisIng potentiAl Of the NOde N2 is Δvn2, tHE OUtpUT VN1 is given by a Following eqUAtiOn (3):VN1=(Vφ−vtH)+ΔVn2(cb/Cb(Cb+cs))  (3)
HerE, tHE caPacitance Cb InclUdes, besidEs the cAPacitanCE shown iN the ciRcuIt dIagrAM, sUcH as ThE PreCEdIng COupLed capacItAnCe CB1, aLl of THE COuplEd cApacItancE of synchronouS puLse φ2 ANd tHe nodE N1, whiCh inClUde thE capacItancE gEnerated by the gaTe, thE drain and The SoUrcE oF the tRAnsistOr NmT2, oR an inveRsion laYEr (cHaNNEL) fOrmed below the gate, aNd FURtHer incluDe the dIReCt COnnectioN cApaCitaNCE betwEen tHE wIring of tHe syncHRoNoUs pulse Φ2 aNd the nOdE N1. FUrtHer, Cs INdicAtes a cApacitanCe obtAIned by subtractINg the above-menTIoNED bOOtstRap Capacitance cb frOM the WholE CaPacITance Of the NoDE N1 ANd constitutes the so-cAlLed parAsitiC capacitance.
HEre, provideD THAt the folLowiNG eQUation (φ is satisFied aT ΔVN2Vφ.(Vφ−VtH)+vφ(Cb/Cb(Cb+cs))>Vφ+VTh  (4)This imPlies that THE gate volTagE of The mOS TRAnSistor NMT2, that IS, The oUtPut VN1, beComEs higheR thAn VΦ+VtH. AcCoRdingly, thE output Vn2 cAn Be SeT to The poTEntial of ThE voLtAge vφ. By sUItably SelecTing ThE cAPacItance CB1, WhICH conStItUtes A deSiGn eleMent, IT is Easy to sAtisfy the AboVE-menTiOnEd equatIon (4), and, hence, thE oUtput VN2 can Be Set To the pOTEntial of The voltage Vφ.
Here, at the saME time, thE poTentiAl of The node N3 tAkeS a valuE exPRessed By a folLowinG eQuaTIOn (5) thrOUGh A MOs tRansistor Nmt3, WhiCh is sUbJectEd to the Diode connection.VN3=VΦvth  (
 the following equation (2 ) is satis fied, Vφ− Vth ≧V φ  ( 2)Th e MOS transist o r NM T2 turns ON and the pu lse φ 2e nter s  t he no de N2.A tt h ispo in t o ft im e, du e t o the c oupled cap aci ta nce Cbl, whi c his referre d t o as a boots tra p capa ci tan c e tha t i s ins ertedb etween  the node sN 1 andN 2, a vo l t ag e ri se on a point oft he node N2 is tra nsmitt ed to t henod e N1 which  i s int he floa t in g s tat e , so that the  potentialo f t he nod eN2a lso ri ses.As s umi ng that the  ris ing poten tial o f  the no d e N2 is  ΔVN2,  th e o utpu t  V N1  is  g i ven by  af oll owing eq ua ti on (3 ):VN 1 = ( V φ−Vt h)+ ΔVN2 (Cb/C b(Cb+Cs))  (3 )
H ere, the  capa citan ce C binclu des, b eside sthe capacitance  sho wn in the  ci rc uit  d iagra m , such  as  th e prece ding co u ple dc a p ac itance CB1, all of  t h e  c oupled c apacit a nc eo f synchr on ous  pul s e  φ2 a nd t h enode N1,  which in cl ude the  c apacit an cegen erate d  bythe ga te, thedrain and the source of the transi s to r NM T 2, o r a n inversion  lay e r (c hann e l)  fo r med b elowth e  g a te, and further inc lu de the  dire ct connection  capacitan c e betweenthew ir i ng of the sync hrono us pulse φ 2  and the  node  N1. Fur ther, Csi n dicatesa c apa cit anc e ob tained by sub t r acti ng  the ab ove -mentio ned  bo ots tra pcapacitan ce Cb fr om  t he  w hol e cap a citanceof  th enod e N1a nd con stitu testh es o-c alled p a ra s i ticca pa cita nce .Here,  pro v ide d thatthe follo win g  equ at io n (φ is  satisfied at  Δ VN2Vφ.(Vφ− Vt h)+ Vφ(Cb/ C b (Cb+Cs)) >Vφ+Vth  (4)This implie s  that t hegatevolt age of th e M OS tra nsi s tor NM T2, th at is ,the o utput V N1 , b ec omes highe r tha n Vφ+ Vt h. A ccordin gly, the output VN 2  ca n be set to t hepote n t ia l o f  t h e v ol t age V φ. By suitablyselectingth e  c apacitance Cb1 ,which c onstitu tes a designelement,it is eas yto s a t isf y the abov e-mentio ned equat i on (4 ) ,and,hen ce, th eout put V N2 can beset t o thepo tentia l ofth e voltag e Vφ.
Here, at the same  time,  thepot ential of  th e  no de N3 tak es a  value exp res sed  by a  fo l lowin g eq u at ion (5) t hrou g h a MOS t r an sis t o rNMT3, which i s  su bject edt o thediod e connection.VN3= V φVth  (
 the_following equation_(2) is satisfied,Vφ−Vth≧Vφ  (2)The MOS_transistor NMT2_turns_ON and_the_pulse φ2 enters_the node N2._At this point of_time, due to_the_coupled capacitance Cbl, which is referred to as a bootstrap capacitance that is inserted_between_the nodes_N1_and_N2, a voltage rise on_a point of the node_N2 is_transmitted to the node N1 which is in_the_floating state, so_that the potential of the node N2 also rises.
Assuming_that the rising potential of the_node N2 is_ΔVN2,_the_output VN1 is given_by a following equation (3):VN1=(Vφ−Vth)+ΔVN2(Cb/Cb(Cb+Cs))  (3)
Here, the_capacitance Cb includes, besides the capacitance_shown in the circuit diagram, such as_the preceding coupled capacitance CB1, all_of the coupled capacitance of_synchronous pulse_φ2 and the node N1,_which include the_capacitance generated_by the gate,_the drain and the source of_the transistor NMT2,_or an inversion layer (channel) formed_below_the gate, and_further_include_the direct_connection capacitance between_the_wiring of_the_synchronous pulse φ2 and the node_N1._Further, Cs indicates a capacitance obtained by_subtracting the above-mentioned bootstrap_capacitance_Cb from the whole_capacitance of the node N1_and constitutes the so-called parasitic capacitance.
Here,_provided that_the following_equation (φ is satisfied at ΔVN2Vφ.(Vφ−Vth)+Vφ(Cb/Cb(Cb+Cs))>Vφ+Vth  (4)This implies that the gate voltage_of the MOS transistor NMT2, that_is, the output VN1,_becomes higher_than_Vφ+Vth. Accordingly, the_output_VN2 can_be set to the potential of the_voltage Vφ._By suitably selecting the capacitance Cb1,_which constitutes a design_element,_it is easy to satisfy the_above-mentioned equation (4), and, hence, the_output VN2 can be set_to_the_potential of the voltage Vφ.
Here,_at the same time, the potential_of the node_N3 takes a value expressed by a_following_equation (5) through a MOS transistor_NMT3,_which is subjected to the diode_connection.VN3=VφVth  (