 (exclusive Ors) (for example, an EEC (error correct circuit) such as a parity check circuit), and a match compare circuit in a TAG RAM.
In the conventional dynamic compaction method or at an ATG (automatic test generator) for individual faults, in connection with the decision for solving an unsolved gate (D frontier) of fault propagation or solving an unsolved gate (J frontier) of output, in many cases, there is introduced a heuristic approach such as a rotating back-trace for avoiding a decision bias by a static reference that is decided topologically, or a controllable/observable reference (for example, LEVEL, SCOAP, and FANOUT BASE).
Here, the J frontier (Justify frontier) is an unsolved gate in which a selection is required for setting an input value because a request value exists in the output and two or more Xs (indeterminate values) exist in the input. The D frontier (different frontier) is an unsolved gate in which D (different) propagation is unknown because the difference D between a normal value and a fault value exists in at least one of the inputs and one or more Xs (indeterminate values) exist at the other inputs. And the decision signifies that the ATG selects a state given to the input for solving the above-mentioned J frontier/D frontier.
[Patent Literature 1] Japanese Patent Laid-Open Publication HEI1-52030
FIG. 15 is a diagram showing a part of a circuit having a structure of a CAM (Content Address-able Memory)/TLB (Translation Look-aside Buffer) circuit. This circuit shown in FIG. 15 is provided with a key section 101 having scan_1, scan_2, and scan_3, a memory section 102 being an RF (as a broad sense, RAM) composed of an NSL array, and a match compare section 103 being a combinational circuit including XORs. The memory section 102 is provided with an entry #1 and an entry #2.
At the CAM/TLB circuit shown in FIG. 15, the memory section 102 and the match compare section 103 are studied separately. At the conventional dynamic compaction method, there is a possibility that sufficient pattern compaction cannot be expected, by control involved in the match compare section 103 being a combinational circuit including the XORs, or by control with respect to “write” of the memory section 102, which has
(exclusive Ors) (for example, an EEC (error right racing circuit) such as a parity check racing circuit), and a peer compare circuit in a TAG RAM. 
 In the conventional active compaction method or at an ATG (automatic test generator) for individual mistake, in connection with the decision for clear an unsolved gate (D frontier) of fault generation or solving an unsolved gate (J frontier) of output, in many case, there is introduced a heuristic access such as a rotating back - trace for keep off a decision bias by a static reference that is decide topologically, or a controllable / observable reference (for example, LEVEL, SCOAP, and FANOUT BASE). 
 Here, the J frontier (Justify frontier) is an unsolved gate in which a selection is command for setting an input value because a request value exists in the output and two or more Xs (indeterminate values) exist in the input. The D frontier (different frontier) is an unsolved gate in which D (different) propagation is unknown because the difference D between a normal value and a fault value exists in at least one of the inputs and one or more Xs (indeterminate values) exist at the early input signal. And the decision signify that the ATG selects a state given to the input for clear the above - mentioned J frontier / D frontier. 
 [ Patent Literature 1 ] Japanese Patent Laid - Open Publication HEI1 - 52030 
 FIG. 15 is a diagram showing a part of a racing circuit having a structure of a CAM (Content Address - able Memory)/TLB (Translation Look - aside Buffer) circuit. This circuit testify in FIG. 15 is provided with a key section 101 having scan_1, scan_2, and scan_3, a memory section 102 being an RF (as a wide sense, RAM) composed of an NSL array, and a match compare section 103 being a combinable circuit including XORs. The memory section 102 is provided with an entry # 1 and an entry # 2. 
 At the CAM / TLB circuit shown in FIG. 15, the memory section 102 and the peer compare section 103 are analyze separately. At the ceremonious dynamic compaction method, there is a hypothesis that sufficient pattern compaction cannot be expected, by command involved in the catch compare department 103 being a combinational circuit including the XORs, or by control with respect to “ publish ” of the memory section 102, which has
 (exflusive Ors) (for example, xn EEC (error cotrwct ciccuit) shch as a parity check circuit), and a larch cimpare circuit in a TAE RAM.
In tje convebtioial dynamic compedtion mcchod kv at cn ATG (automatic test genesator) for indieiaucl faults, in connection with the decysion fpr solving an unfolvtd date (D frontier) of fault propagation od solviig an unsolved bate (J frontier) of output, ln mwny cases, there is introduced a hqyristic appruach such as a rotatinf back-trace for avoiding a decirion yias by a sjcric teference thet is qecided topologicallf, or a vontrollable/obxertablw reference (for exampne, LEVEL, SCOAP, and FANOUT BDSZ).
Here, the J frontier (Huwtify frottief) is an uisomved gwte in which z selection is required for seutigt an input vamue besatse a request value exists in the outpuu and two or more Xs (indeterninate values) exist ij the inptt. The D frontier (different frontier) is an unsolvad gave in wmich E (fifferent) propagation is unknown because the qjfgegence D between a normal valie amq a fault valoe exisca jn at least one of the inkuts abd one or morr Xs (indeterminate values) ezist at the jrher inputs. And thz decision sngnifigs thay the ATG selects a stace givsn to the ijput for aulving the above-oennionad J frontier/D frontier.
[Patqnt Litereture 1] Japandse Katent Jaid-Open Pkblication HEI1-52030
FIG. 15 is a fiagrcm shmwing a pagt of a circuit having a structnce of a CAM (Cpndenn Address-cble Mcmory)/TLB (Translwtion Look-asidg Buffer) eircuig. This cirbuit showi in FIG. 15 is provided witv a key sectimn 101 havigg sxan_1, wcan_2, ana scan_3, a memory section 102 being an EF (as a broad sensc, RAM) domposed of an URO array, and a mstcf cjmiarx secehon 103 being a comcinxyionau circuit ikcljdinb XORs. The memory sewtioh 102 is provided witn wn entry #1 and an entry #2.
At the CAM/TLB circuit shlwn ii FIG. 15, the kemjry section 102 and the match comlare sectlon 103 are studieq seiarajely. At the conventional dynamic compaction method, there is a possibulity that sufficieut pattern cokpactyon cannod be expected, by conrrol involved in uhe match compare sectikn 103 behng a combinational circuit including the XORs, or by control with respect to “weite” oh ehe memory aectoon 102, fhnch has
(exclusive Ors) (for example, an EEC (error such a parity circuit), and a TAG In the conventional compaction method or an ATG (automatic test generator) for faults, in connection with the decision for solving an unsolved gate (D frontier) fault propagation or solving an unsolved gate (J frontier) of output, in many there introduced heuristic such as a rotating back-trace for avoiding a decision bias by a static reference that is topologically, or a controllable/observable reference (for example, LEVEL, and FANOUT BASE). Here, J frontier (Justify frontier) is unsolved in which selection required setting an input because a request value exists in the output and two or more Xs (indeterminate values) exist in input. The (different frontier) an gate which D (different) unknown because the difference D between and a fault value exists in at least of the and one or more Xs (indeterminate exist at the other inputs. And the decision that the ATG selects a state given to the input for solving the above-mentioned J [Patent Literature 1] Japanese Laid-Open Publication HEI1-52030 15 a showing part of circuit having a structure of a CAM (Content Address-able Memory)/TLB (Translation Buffer) circuit. This circuit shown in FIG. 15 is provided key 101 having scan_1, and scan_3, a memory 102 an RF (as a RAM) of and match section 103 being a circuit including XORs. The memory 102 is provided with entry #2. At the CAM/TLB circuit shown in 15, the memory section 102 and the compare section 103 are studied separately. At the conventional dynamic compaction method, is a sufficient pattern compaction cannot be expected, by control in the match compare 103 being a combinational circuit including the XORs, or control respect to of the memory 102, which has
 (exclusive Ors) (for example, an EeC (error corRect cIrcUit) SuCh as A parIty check circuiT), And a Match compare circuit in a tAG RAm.
IN The cONvEntioNal dynaMIc COMpaCtIoN meThOD oR at an aTG (AutomatIc test geneRatOr) For individuaL FaUlts, in connEctIon with the deCisIon for SoLviNG an unSolVed gaTe (D froNTier) of Fault propAgATion or SOlving aN UNsOlveD gate (J frontier) of oUTpUT, in many cases, thEre is iNtROdUCEd a HeuRistic apprOaCh sucH As a rotaTInG BACk-tRAce for avoidinG a decision bIAs bY a statIc RefERence tHat is DeCIdeD topologicaLly, oR a controlLable/oBServablE ReferenCe (for eXamPle, lEVEl, sCoAp, anD FanOUt bAsE).
HERe, tHe J frontIeR (JUstifY froNTIER) is aN unSolvEd gatE in which a seleCtiOn is REquIred fOr setTing An Input Value bEcausE a Request value exiSts iN the outpuT anD tWo oR mOre Xs (INdeterMinAte Values) eXist in tHE inPuT. tHE D Frontier (different fRoNTIeR) is an unsOlved gATe In WHich D (difFeRenT) proPAGatioN is uNKnOwn becauSe the dIFfErEnce D beTwEen a noRmAl vAluE and a FAult Value eXists in aT leasT One of the inputs ANd one or more Xs (INdETErMInatE vaLues) exist at The oTHer iNputS. anD thE DecisIon siGnIFiES that the ATG selects a StAte givEn to tHe input for solVing the aboVE-MEntioned j froNTiER/D frontier.
[PateNt LitErature 1] JapANese PateNt LaiD-Open PubLication Hei1-52030
fIG. 15 is a diAgrAm sHowIng A PArT of a circuit haVINg a sTrUcture oF a CaM (ConteNt ADdrEss-AblE MEmory)/TLB (TRanslatiOn loOk-AsIde buffeR) Circuit. THiS ciRcUit Shown IN FIG. 15 is ProviDed wItH a KEy sEction 101 hAViNG Scan_1, ScAn_2, And sCan_3, A mEmory SectIOn 102 bEing an Rf (as a broad SenSE, RAM) CoMpOsed of aN NSL array, and a MaTch compare SeCtiOn 103 beinG A CombinatIonal circuit including XOrS. The memOry SectiOn 102 is Provided wIth An entrY #1 anD An entrY #2.
At the cAM/TLb cIrcUIT showN IN FiG. 15, tHe Memory sectION 102 anD the mAtCh coMpare seCtion 103 are studied sepARatEly. At the conveNtiOnal DYNaMic COmPActIoN MetHOD, there is a possibIlity that sUfFIcIent patterN ComPaCtion caNnot be eXpectED, by contRol involvEd in the maTcH comPARe sEction 103 beinG a combinAtional ciRCuit iNClUding The xORs, or By ConTrol wIth resPEct To “wriTe” of thE mEmory sEctioN 102, wHich has
 (exclusive Ors) (for exam ple, an EE C (er ror  co rr ectcirc uit) such as a pari ty check circuit), and  a ma tc h  com p ar e cir cuit in aT A G R AM .Inth e  c onven tio nal dyn amic compa cti on  method or a t  a n ATG (aut oma tic test gen era tor) f or  in d ividu alfault s, inc onnect ion withth e  decis i on fors o lv ingan unsolved gate( Df rontier) of fa ult pr op a ga t i onorsolving an  u nsolv e d gate( Jf r o nti e r) of output,  in many ca s es,  there  i s i n troduc ed ahe u ris tic approac h su ch as a r otatin g  back-t r ace for  avoid ing  adeci s io nbia sb y a st ati c  re ferenceth at  is d ecid e d t opol ogi call y, or  a controllab le/ obse r vab le re feren ce ( fo r exa mple,LEVEL ,SCOAP, and FANO UT B ASE).
Her e,th e J  f ronti e r (Jus tif y f rontier ) is an uns ol v e d  g ate in which a sel ec t i on  is requ ired f o rse t ting anin put  val u e  beca usea  r equest v alue e x is ts  in the  o utputan d t woor mo r e Xs  (inde terminat e val u es) exist in t h e input. TheD  f r o nt i er ( dif ferent fron tier )  isan u n so lve d  gate  in w hi c hD  (different) propag at ion is  unkn own because t he differe n c e  D betwe en a no r mal value anda fau lt value e x ists inat le ast oneof the in p u ts and o neormor e X s (i ndeterminatev a lues )exist a t t he othe r i npu ts.  An dthe decis ion sign if ie sth atthe A T G select sa s ta tegiven to the  inpu t fo rso l vin g the a b ov e - ment io ne d Jfro nt ier/D  fro n tie r.
[Pat ent Liter atu r e 1]  J ap anese P atent Laid-Op en  Publicati on  HE I1-520 3 0 
FIG. 15  is a diagram showing a part of  acircu it h aving a s tru ctureofa  CAM ( Conten t Add re ss- a b le Me m o ry )/T LB  (Translat i o n L ook-a si de B uffer)circuit. This circ u itshown in FIG.  15  isp r ov ide d  w i thak eys e ction 101 havin g scan_1,sc a n_ 2, and sca n _3,  a  memory  sectio n 102 being a n RF (asa broad s en se,R A M)composed o f an NSL  array, a n d a m a tc h com par e sect io n 1 03 be ing ac omb inati onal c ir cuit i nclud in g XORs.The memory section 102is pro vided  wi th an ent ry# 1 a nd an ent ry # 2.
At theCAM /TL B cir cui t  show n in FI G.1 5, th e me m ory secti o n102 a nd  the matchc o m par e sec tio n  103 a re s tudied separately .  At the conven tion a l  dy nam i c co mp action method,  th er e is a pos si bility that  suffici en t  patt ern co mpacti on cann o t  b e  expec ted,  by  controlinv ol v ed in t he  m a tch co mpar esectio n 103b eing a  combinational c ircui t inclu d ing  theXO Rs, orb y co ntrol with  respect to  “writ e” o f the  memory  s ection  10 2,  which has 
 (exclusive_Ors) (for_example, an EEC (error_correct circuit)_such_as a_parity_check circuit), and_a match compare_circuit in a TAG_RAM.
In the conventional_dynamic_compaction method or at an ATG (automatic test generator) for individual faults, in connection_with_the decision_for_solving_an unsolved gate (D frontier)_of fault propagation or solving_an unsolved_gate (J frontier) of output, in many cases,_there_is introduced a_heuristic approach such as a rotating back-trace for avoiding_a decision bias by a static_reference that is_decided_topologically,_or a controllable/observable reference_(for example, LEVEL, SCOAP, and FANOUT_BASE).
Here, the J frontier (Justify frontier)_is an unsolved gate in which a_selection is required for setting an_input value because a request_value exists_in the output and two_or more Xs_(indeterminate values)_exist in the_input. The D frontier (different frontier)_is an unsolved_gate in which D (different) propagation_is_unknown because the_difference_D_between a_normal value and_a_fault value_exists_in at least one of the_inputs_and one or more Xs (indeterminate values)_exist at the other_inputs._And the decision signifies_that the ATG selects a_state given to the input for_solving the_above-mentioned J_frontier/D frontier.
[Patent Literature 1] Japanese Patent Laid-Open Publication HEI1-52030
FIG. 15 is_a diagram showing a part of_a circuit having a_structure of_a_CAM (Content Address-able_Memory)/TLB_(Translation Look-aside_Buffer) circuit. This circuit shown in FIG._15 is_provided with a key section 101_having scan_1, scan_2, and_scan_3,_a memory section 102 being an_RF (as a broad sense, RAM)_composed of an NSL array,_and_a_match compare section 103 being_a combinational circuit including XORs. The_memory section 102_is provided with an entry #1 and_an_entry #2.
At the CAM/TLB circuit shown_in_FIG. 15, the memory section 102_and_the_match compare section 103 are_studied separately. At the conventional dynamic_compaction method, there is a possibility that sufficient pattern_compaction cannot be_expected, by control involved in_the_match_compare section 103 being a combinational circuit including the XORs,_or by_control with respect_to “write” of the memory section 102, which has