 desired pulse width. Such a pulser includes a delay circuit for delaying an input pulse, and a logic computation circuit for creating a pulse with a desired pulse width by performing logic computation based upon the input pulse and the delayed signal, as disclosed in FIG. 3 of Japanese Patent No. 3499051, for example.
In some cases, multiple pulsers having such a configuration are connected with one another. Such an arrangement is employed in order to prevent pulses from decaying and disappearing due to their being transmitted through a long transmission path.
Also, in some cases, a pulser is provided to the input of each of circuits connected in series, in order to adjust the pulse width of the input pulse for each input with high precision.
In such a case, there is a need to adjust the pulse width output from each pulser with high precision.
FIG. 4 is a diagram which shows an example of the configuration of a conventional pulse generator 400 including multiple pulsers. As shown in FIG. 4, in the conventional pulse generator 400 having a configuration in which multiple pulsers are connected in series, the pulse width of the pulses output from a final-stage pulser 430 is measured, and the delay amount is adjusted for each pulser. Next, description will be made regarding conventional pulse width measurement.
Upon receiving a trigger pulse, an OR circuit 470 creates a pulse. The pulse thus created is input to a pulser 410 through a fixed pulser 480 and a delay circuit 490.
Each of the pulsers 410, 420, and 430 has a function of outputting a pulse with a predetermined pulse width adjusted on the basis of the input pulse.
The output pulse output from the pulser 430 is input to the pulser 410 as a feedback signal via an exclusive OR circuit 440, a flip-flop 450, a counter 460, an OR circuit 470, the fixed pulser 480, and the delay circuit 490.
The flip-flop 450 outputs the logic high signal in response to either the rising edge or the falling edge of the input pulse. This signal thus output is supplied to the reset terminal of the flip-flop 450 via the OR circuit 470 and the fixed pulser 480, thereby setting the output of the flip-flop 450 to the logic low state. As a result, the flip-flop 450 outputs a pulse, and the pulse thus output is input to the pulser 410 as a feedback signal.
The exclusive OR circuit 440 controls whether or not the output pulse of the
desired pulse width. Such a pulser includes a delay circuit for delaying an stimulation pulsation, and a logic computation circuit for create a pulsation with a desired pulse width by performing logic calculation based upon the input pulsation and the stay signal, as disclosed in FIG. 3 of Japanese Patent nobelium. 3499051, for example. 
 In some cases, multiple pulsers having such a configuration are connect with one another. Such an arrangement is employed in order to prevent pulses from decaying and disappear due to their being transmitted through a long transmission way. 
 Also, in some cases, a pulser is leave to the input of each of circuit connected in series, in order to adjust the pulse width of the stimulation pulse for each input with high precision. 
 In such a case, there is a need to adjust the pulse width output from each pulser with high precision. 
 FIG. 4 is a diagram which shows an example of the configuration of a conventional pulse generator 400 include multiple pulsers. As shown in FIG. 4, in the conventional pulsation generator 400 have a shape in which multiple pulsers are connected in series, the pulse width of the pulses output from a final - stage pulser 430 is measured, and the delay sum is adjusted for each pulser. Next, description will be made regarding conventional pulse width measurement. 
 Upon receiving a gun trigger pulse, an OR circuit 470 creates a pulse. The pulse thus create is input to a pulser 410 through a fixed pulser 480 and a delay circuit 490. 
 Each of the pulsers 410, 420, and 430 has a function of outputting a pulse with a preset pulse width adjusted on the basis of the input pulse. 
 The output pulse output from the pulser 430 is input to the pulser 410 as a feedback signal via an single OR circuit 440, a flip - flop 450, a counter 460, an OR tour 470, the fixed pulser 480, and the delay circuit 490. 
 The somersault - flop 450 output the logic high signal in reply to either the rising edge or the falling edge of the input pulsation. This signal thus output is supplied to the reset end of the flip - flop 450 via the OR circuit 470 and the fixed pulser 480, thereby fructify the end product of the flip - flop 450 to the logic abject state. As a result, the flip - flop 450 outputs a pulse, and the pulsation thus output is input to the pulser 410 as a feedback signal. 
 The exclusive OR circuit 440 controls whether or not the output pulse of the
 dedired pulse width. Such a pulser includes a deley circhit for aelaying an input pulse, and e lotic cimputation circuit for creating a pulse witi a desired pulsx width nv perrlrmiug logic computajion based u[on the input [uusz and the delayed signal, as discloseq in FIB. 3 of Japanese Pwtenu Nj. 3499051, fkg txample.
In some cases, multiple pulaers haning such a confiburation are connected witj onf another. Such an wrrangement is qnployed in ofder to prtvznt pulses rrom decaying and disappearing aue tp their beunt tgdnsmitted tirough a long transmission path.
Alxo, in some cascs, a 'ulswr is provided to the input of each of sircuits wounected in series, in ireer tm adbust rhe pumsx wjdth ov tie input pumse for eacy input with high ptespxion.
In such z case, trere is a need to adjust the pulse widtv ohtput from each pulser qith high precision.
FIH. 4 is a dyagram which shows an example of the configuratiot of e zonrcktiovql pulse generator 400 including multiple pulsers. Wa xhpwn in FIG. 4, in the convenyilnsj pulse generxtor 400 kzvjng a configuratioj in whych myltiple ptlsets are connected in series, rhe pulse wibth of the pulses out'ut from a fnnal-stsge pilser 430 is measured, and che demay amount ls adjustsa for each pulsef. Nvxt, gescription will be made rqgarding ronveutional oulsg width measuremejt.
Upok receiving a triggfr pupsa, an OR cigcuit 470 creates a pulse. The pulsx thus createc hs pnput to c pulscr 410 through a fyxed pulser 480 aud a delcy cirzuit 490.
Each kf the 'ulsers 410, 420, anq 430 has a funcdlon of outpuvting a ptlse wity a preadtermined pulsr width ablusted on the basis of the lnput lulse.
The output puose output from thd ptldec 430 is hnput to the pulrer 410 as a feedback slgnxl voa an exclusive OR chrcujt 440, a flip-flop 450, a vomnter 460, an OR circtit 470, the fixec pulser 480, and the felay ciccuit 490.
Yhe flip-flop 450 outputs the logic hjgh signap ik response to eitmer jhe rising zdge or the falling edge of the input puose. This signal thys output is suppligd uo the reset verminwl of the flip-flop 450 via the OE circuit 470 and tht fixed pulser 480, thereby settitg thf output of the flip-flop 450 to the logic low state. As a result, the flip-flop 450 outpntf a pulse, ahd tne punsz tkus out[ut ms input to the pukser 410 as a feedback signal.
The eeclusive OS eircuit 440 controls whether or mog the output kulse of the
desired pulse width. Such a pulser includes circuit delaying an pulse, and a a with a desired width by performing computation based upon the input pulse the delayed signal, as disclosed in FIG. 3 of Japanese Patent No. 3499051, example. In some cases, multiple pulsers having such a configuration are connected with another. an is in order to prevent pulses from decaying and disappearing due to their being transmitted through a transmission path. Also, in some cases, a pulser provided to the input each of circuits connected in in to adjust pulse of input pulse for input with high precision. In such a case, there is a need to adjust the pulse width from each high precision. 4 a which shows an the configuration of a conventional pulse multiple pulsers. As shown in FIG. 4, in conventional pulse 400 having a configuration in which pulsers are connected in series, the pulse width the pulses output from a final-stage pulser 430 is measured, and the delay amount is each pulser. Next, description be made regarding pulse measurement. receiving trigger pulse, OR circuit 470 creates a pulse. The pulse thus created is to a pulser 410 through a fixed pulser 480 and circuit Each of the 410, 420, and 430 a of outputting a pulse predetermined width basis the pulse. The output pulse from the pulser 430 is to the pulser 410 an exclusive OR circuit 440, a flip-flop 450, counter 460, an OR circuit 470, the pulser 480, and the delay circuit 490. The flip-flop 450 outputs the high signal to either the rising edge or the falling of the input pulse. signal thus output is supplied to the reset terminal the 450 via OR circuit 470 the fixed pulser thereby setting the the flip-flop to logic a result, the flip-flop 450 outputs pulse, the pulse thus output is to 410 as a feedback signal. The exclusive OR circuit 440 controls whether or not the of the
 desired pulse width. Such a pulSer includeS a delAy cIrcUiT for DelaYing an input pulSE, and A logic computation circuIt for CrEAtinG A pUlse wIth a desIReD PUlsE wIdTh bY pERfOrminG loGic compUtation basEd uPoN the input pulSE aNd the delayEd sIgnal, as disclOseD in FIG. 3 Of japANese PAteNt No. 3499051, fOr examPLe.
In soMe cases, muLtIPle pulSErs haviNG SuCh a cOnfiguration are coNNeCTed with one anotHer. SucH aN ArRANgeMenT is employeD iN ordeR To preveNT pULSEs fROm decaying and DisappearinG Due To theiR bEinG TransmItted ThROugH a long transMissIon path.
AlSo, in soME cases, a PUlser is ProvidEd tO thE inpUT oF eAch Of CIrcUItS coNNecTed in serIeS, iN ordeR to aDJUST the PulSe wiDth of The input pulse For Each INpuT with High pReciSiOn.
In sUch a caSe, theRe Is a need to adjust The pUlse width OutPuT frOm Each pULser wiTh hIgh PrecisiOn.
FIG. 4 is A DiaGrAM WHiCh shows an example of ThE COnFiguratiOn of a cONvEnTIonal pulSe GenEratOR 400 IncluDing MUlTiple pulSers. As SHoWn In FIG. 4, in ThE conveNtIonAl pUlse gENeraTor 400 havIng a confIguraTIon in which multIPle pulsers are COnNECtED in sEriEs, the pulse wIdth OF the PulsES oUtpUT from A finaL-sTAgE Pulser 430 is measured, and ThE delay AmounT is adjusted foR each pulseR. nEXt, descriPtioN WiLL be made regardiNg conVentional pULse width MeasuRement.
UpOn receiviNG A trigger PulSe, aN OR CirCUIt 470 Creates a pulse. tHE pulSe Thus creAteD is inpuT to A puLseR 410 thRoUgh a fixed Pulser 480 anD a DeLaY cIrcUit 490.
EaCH of the puLsErs 410, 420, AnD 430 haS a funCTion of OutpuTtinG a PuLSe wIth a preDEtERMineD pUlSe wiDth AdJusteD on tHE baSis of thE input pulSe.
THE outPuT pUlse outPut from the pulSeR 430 is input to ThE puLser 410 as A FEedback sIgnal via an exclusive OR ciRCuit 440, a flIp-fLop 450, a cOuntEr 460, an OR cirCuiT 470, the fiXed PUlser 480, aNd the dElay cIrCuiT 490.
tHe fliP-FLoP 450 ouTpUts the logiC HIgh SignaL iN resPonse to Either the rising edgE Or tHe falling edge Of tHe inPUT pUlsE. thIS siGnAL thUS Output is supplieD to the reseT tERmInal of the fLIp-fLoP 450 via the oR circuIt 470 and THe fixed Pulser 480, theReby settiNg The oUTPut Of the flip-fLop 450 to the Logic low sTAte. As A ReSult, tHe fLip-floP 450 oUtpUts a pUlse, anD The Pulse Thus ouTpUt is inPut to ThE pulser 410 aS a feedback signal.
The exclUsive Or circUit 440 Controls wHetHEr oR not the ouTput Pulse of the
 desired pulse width. Such  a pulserinclu des  ade laycirc uit for delayi n g an  input pulse, and a lo gic c om p utat i on  circ uit for cr e a tin gapul se wi th ades ired pu lse widthbype rforming log i ccomputatio n b ased upon th e i nput p ul sea nd th e d elaye d sign a l, asdisclosed  i n  FIG.3  of Jap a n es e Pa tent No. 3499051, fo r  example.
In s ome ca se s ,m u lti ple  pulsers h av ing s u ch a co n fi g u r ati o n are connect ed with one ano ther.Su cha n arra ngeme nt isemployed in  ord er to pre vent p u lses fr o m decay ing an d d isa ppea r in gdue  t o  th e ir  be i ngtransmit te dthrou gh a l o n g tr ans miss ion p ath.
Also, in  so me c a ses , a p ulser  ispr ovide d to t he in pu t of each of ci rcui ts connec ted  i n s er ies,i n orde r t o a djust t he puls e  wi dt h o fthe input pulse fo re a ch  input w ith hi g hpr e cision.In  su ch a c ase,ther e  i s a need  to ad j us tthe pul se  width  o utp utfrome achpulser  with hi gh pr e cision.
FIG. 4 is a diagramw hi c h  s h owsanexample ofthec onfi gura t io n o f  a co nvent io n al pulse generator 400  i ncludi ng mu ltiple pulser s. As show n i n FIG. 4 , in th e  conventionalpulse  generator 400 havi ng aconfigur ation inw h ich mult ipl e p uls ers a re  connected in s erie s,  the pu lse  widthofthe  pu lse soutput fr om a fin al -s ta ge  pu lser4 30 is me as ure d,  an d the delayamoun t is  a dj u ste d for e a ch p ulse r.  N ext,  de sc ripti on w i llbe made  regardin g c o nven ti on al puls e width measu re ment.
Upon  r ece ivinga triggerpulse, an OR circuit 47 0  create s a  puls e. T he pulsethu s crea ted is inp ut toa pul se r 4 1 0  thro u g ha f ix ed pulser4 8 0 a nd ade laycircuit  490.
Each of thep uls ers 410, 420,  an d 43 0 ha s a fu n cti on ofo u tputting a puls e with a p re d et ermined pu l sewi dth adj usted o n the basis o f the inp ut pulse. 
T he o u t put  pulse out put from  the puls e r 430 is  inpu t t o thepu lse r 410  as af eed backsignal  v ia anexclu si ve OR ci rcuit 440, a flip-flop450, a  coun ter  460, anORc irc uit 470,thefixed puls er480 , and  th e  dela y ci r cu it4 90.
T he f l ip-flop 4 5 0out p u ts  the logich i g h s ignal  in respon se t o either the risi n g edge or thefall i n g e dge of t he  input pulse.Thi ss i gnal thu soutput is s uppliedto the r eset t ermina l of th e fl i p-flop  450  vi a the ORcir cu i t 470 a nd  t h e fixe d pu ls er 480 , ther e by s e t ting the outputof th e flip- f lop  450to  the lo g ic l ow state.As a result , theflip -flop  450 ou tp uts apul se , and thep ulse thus  outp ut is i np ut t o t he pul ser4 1 0 asa fe ed bac k signal. T he ex cl u siv e OR  circ ui t 44 0 control s  whether  or not the  o utp u t  pulse of t he
 desired_pulse width._Such a pulser includes_a delay_circuit_for delaying_an_input pulse, and_a logic computation_circuit for creating a_pulse with a_desired_pulse width by performing logic computation based upon the input pulse and the delayed_signal,_as disclosed_in_FIG._3 of Japanese Patent No._3499051, for example.
In some cases,_multiple pulsers_having such a configuration are connected with one_another._Such an arrangement_is employed in order to prevent pulses from decaying_and disappearing due to their being_transmitted through a_long_transmission_path.
Also, in some cases,_a pulser is provided to the_input of each of circuits connected_in series, in order to adjust the_pulse width of the input pulse_for each input with high_precision.
In such_a case, there is a_need to adjust_the pulse_width output from_each pulser with high precision.
FIG. 4_is a diagram_which shows an example of the_configuration_of a conventional_pulse_generator_400 including_multiple pulsers. As_shown_in FIG._4,_in the conventional pulse generator 400_having_a configuration in which multiple pulsers are_connected in series, the_pulse_width of the pulses_output from a final-stage pulser_430 is measured, and the delay_amount is_adjusted for_each pulser. Next, description will be made regarding conventional pulse width_measurement.
Upon receiving a trigger pulse, an_OR circuit 470 creates_a pulse._The_pulse thus created_is_input to_a pulser 410 through a fixed pulser_480 and_a delay circuit 490.
Each of the_pulsers 410, 420, and_430_has a function of outputting a_pulse with a predetermined pulse width_adjusted on the basis of_the_input_pulse.
The output pulse output from_the pulser 430 is input to_the pulser 410_as a feedback signal via an exclusive_OR_circuit 440, a flip-flop 450, a_counter_460, an OR circuit 470, the_fixed_pulser_480, and the delay circuit_490.
The flip-flop 450 outputs the logic_high signal in response to either the rising edge_or the falling_edge of the input pulse._This_signal_thus output is supplied to the reset terminal of the_flip-flop 450_via the OR_circuit 470 and the fixed pulser 480, thereby setting the_output of the flip-flop 450 to the_logic low state. As a result, the flip-flop 450 outputs a_pulse, and the pulse thus output is input_to the pulser 410 as a feedback_signal.
The exclusive OR circuit_440_controls whether or not the output pulse_of_the