 Further, because of the difficulty in reducing the wiring width, there has been a limit in the forming of integrated circuits of higher density. Still further, in recent years, there is a new problem such that, with respect to long-distance wiring such as a clock line or a data bus line, the wiring resistance is increased in accordance with an increase of chip size, thereby causing an increase of propagation delay time of electrical signal (RC delay time=resistance×capacity) Therefore, it is now needed to use a material of lower resistance in wiring layers.
Accordingly, it has been proposed to perform Cu wiring in place of the conventional wiring with Al or Al alloys. For example, it has been proposed to first provide an insulating film superimposed on a substrate with wiring channels and subsequently deposit Cu in the wiring channels according to the electroplating method, CVD method, etc. so as to form an intended wiring. However, in this technique, it has been difficult to accomplish satisfactory deposition of Cu in minute wiring channels and connecting holes with the intent to densify wiring. Furthermore, it has been difficult to obtain deposit films with satisfactory planarity. Still further, it has been experienced that the deposit films are not dense films and have holes formed therein.
For coping with these problems, it has been proposed to employ a method (SOM method) wherein a solution containing ultrafine particles of Cu is applied onto a substrate provided with wiring channels according to the spin coating method to thereby form a circuit on the substrate (ULVAC TECHNICAL JOURNAL, No. 51, 1999, p. 15). However, in this technique, the thickness of deposit film which can be formed by one application is so small that the application must be repeated for realizing wiring with all the wiring channels filled up. Further, the spin coating method has a drawback in that, when it is intended to uniformly apply the solution containing ultrafine particles of Cu onto the entire surface of substrate, portion of the solution containing ultrafine particles of Cu would be applied outside the substrate, thereby causing the ratio of utilization of the solution containing ultrafine particles of Cu to be low.
Moreover, the deposition of metal fine particles, such as Cu fine particles, is effected by the weight of metal fine particles themselves, so that the closest packing with metal fine particles may not be realized. Thus, it has been experienced that the interparticulate resistance cannot be reduced to thereby disenable obtaining a circuit of satisfactorily low wiring resistance. In a liquid crystal display, a
Further, because of the difficulty in reducing the wiring width, there has been a limit in the forming of incorporate circuit of higher density. however far, in recent years, there be a modern problem such that, with esteem to long - distance wiring such as a clock line or a datum bus line, the wiring resistance is increased in accord with an increase of chip size, thereby cause an increase of propagation delay clock time of electrical signal (RC delay time = resistance×capacity) Therefore, it is immediately needed to use a material of lower electric resistance in wiring layers. 
 Accordingly, it has been proposed to perform Cu wiring in place of the ceremonious wiring with Al or Al alloys. For example, it has been proposed to first provide an insulating film superimpose on a substrate with wiring channel and subsequently deposit Cu in the wiring channels according to the electroplating method, CVD method, etc. so as to form an intended wiring. However, in this technique, it has been difficult to accomplish satisfactory deposit of Cu in moment wiring channels and connect hole with the intent to densify wiring. Furthermore, it has been difficult to obtain down payment films with satisfactory planarity. Still further, it has been experienced that the down payment films are not dense films and have holes formed therein. 
 For coping with these problem, it has been proposed to employ a method (SOM method) wherein a solution hold ultrafine atom of Cu is applied onto a substrate provided with wiring channels according to the spin application method to thereby form a circuit on the substrate (ULVAC TECHNICAL JOURNAL, No. 51, 1999, p. 15). However, in this technique, the thickness of deposit film which can be formed by one application is so little that the application must be reprise for realizing wiring with all the wiring channels fill up. Further, the tailspin coating method has a drawback in that, when it is intended to uniformly lend oneself the solution containing ultrafine particles of Cu onto the integral surface of substrate, portion of the solution containing ultrafine particles of Cu would be applied outside the substrate, thereby causing the ratio of utilization of the solution containing ultrafine particles of Cu to be low. 
 Moreover, the deposit of metal fine atom, such as Cu fine particles, is effected by the weight of metal fine particles themselves, so that the airless packing with metal fine particles may not be realized. Thus, it has been experience that the interparticulate underground cannot be reduce to thereby disenable obtaining a racing circuit of satisfactorily low wiring resistance. In a melted crystal display, a
 Fugther, because of the difniculty in reducnbg the wirinf width, ghere has been a limit in thx foeming of integrated circuitr of highvr densitt. Stmll further, in rxdent years, thsve is e new problem soch that, witv respect to lmne-dnstance wiring such as a clock line jr a daya bus line, the ririmd reapsuance is increased in accordance sith an increase of vhip size, thereby causing wn ijcrease of propagahion delay jjme if electricau signal (RB delay timg=resistance×capacity) Therefore, it is npw needed jo udg a material of ljwer resistakbe in whring lsyers.
Accordingky, mt hqs been proposed to pxrform Cu wiring in klace of tve conventional wirunt witv Al or Xo aulogs. Fkr exalplx, it has besn proposed to first provide am ybsulating filj supewiiposed on a substrate with wiring channtls ahd subsequently deposit Cu in the wiring chajnels accjrding to the electroplating method, CVD method, etw. so es to fjfn wn intended wiring. However, in this technique, yf nax been difficujt to accomlllsn satisfactory deposnfikn of Cu in minute wiring chanbels and sonnrcting holes with the intenr to densify qiring. Furthermore, it has beeu diffocult to obtain deposit filmr wifh satisfachory planzfity. Still furthdr, pt hds been tbperienced that tre deposiv filks are vot cense silms and jave mmles formed thereij.
For eopinc with thede problems, it has been proposev to employ a mathmd (SOM mzthod) eherein a solttion containiug ultrayine pxrticles or Cu is applied oneo a substrata provided wivh wiring chabnelw accorakng to the spim coating method to thereby form a civcuit kn the substratz (OOVAC TECHNICAL JOJRNWL, Np. 51, 1999, p. 15). However, hn tfis yechnkque, tht tmicynesx of deposit film whhch dan be formed by ome applicajion is sj small that yhe application mudt be re'eated fot realizing wiring with all the wiring cjankels filled u[. Fuvthet, the spin eoating method has a drawback in that, whxn it is intended to unuformly apply the spkution conteining ultrafina particles of Cu onro the entire surnace of substrate, portjon of the dolution containing ultrafine particles of Cu would be applied outside thw subsvrwte, thereby cauxing nhe xatio os utmlmzation of the sokution containing ultrafine parvicles of Wu to be low.
Moreover, the deposotkon of metal wine particles, such as Ch fine psrticles, is effected by the weibht of metal fine partickes themwelvea, so that vhe closest packing eith mztal fune parriclcs may not be feakided. Thus, ih hax yeen experienced that the interpaeticulqtf resistance caniot be reduccd to tgereby disenable obtaihing w cirzuit of satisgactorily low eiring resistance. In a liquid crystao display, a
Further, because of the difficulty in reducing width, has been limit in the higher Still further, in years, there is new problem such that, with respect long-distance wiring such as a clock line or a data bus line, the resistance is increased in accordance with an increase of chip size, thereby causing increase propagation time electrical signal (RC delay time=resistance×capacity) Therefore, it is now needed to use a material of lower in wiring layers. Accordingly, it has been proposed perform Cu wiring in of the conventional wiring with or alloys. For it been to first provide insulating film superimposed on a substrate with wiring channels and subsequently deposit Cu in the wiring channels to the CVD method, so to an intended wiring. this technique, it has been difficult deposition of Cu in minute wiring channels and holes with intent to densify wiring. Furthermore, it been difficult to obtain deposit films with satisfactory Still further, it has been experienced that the deposit films are not dense films and formed therein. For coping these problems, it been to a (SOM method) a solution containing ultrafine particles of Cu is applied onto a provided with wiring channels according to the spin coating method form circuit on the (ULVAC TECHNICAL JOURNAL, No. 1999, 15). However, in this thickness deposit be by application is so small the application must be repeated realizing wiring with all Further, the spin coating method has a drawback that, when it is intended to uniformly the solution containing ultrafine particles of Cu onto the entire surface of portion of containing ultrafine particles of Cu would be applied the substrate, thereby causing ratio of utilization of the solution containing ultrafine particles Cu be low. the deposition of fine particles, such Cu fine particles, by the of fine that the closest packing with metal particles not be realized. Thus, it been the interparticulate resistance cannot be reduced to thereby disenable obtaining a circuit of satisfactorily low In a liquid crystal a
 Further, because of the difficUlty in reduCing tHe wIriNg WidtH, theRe has been a limiT In thE forming of integrated ciRcuitS oF HighER dEnsitY. Still fURtHER, in ReCeNt yEaRS, tHere iS a nEw problEm such that, WitH rEspect to long-DIsTance wirinG suCh as a clock liNe oR a data BuS liNE, the wIriNg resIstancE Is incrEased in acCoRDance wITh an incREAsE of cHip size, thereby cauSInG An increase of prOpagatIoN DeLAY tiMe oF electricaL sIgnal (rc delay tIMe=RESIstANce×capacity) ThErefore, it is NOw nEeded tO uSe a MAteriaL of loWeR ResIstance in wiRing Layers.
AccOrdingLY, it has bEEn propoSed to pErfOrm cu wiRInG iN plAcE Of tHE cOnvENtiOnal wiriNg WiTh Al oR Al aLLOYS. For ExaMple, It has Been proposed tO fiRst pROviDe an iNsulaTing FiLm supErimpoSed on A sUbstrate with wirIng cHannels anD suBsEquEnTly dePOsit Cu In tHe wIring chAnnels aCCorDiNG TO tHe electroplating meThOD, cVd method, eTc. so as TO fOrM An intendEd WirIng. HOWEver, iN thiS TeChnique, iT has beEN dIfFicult tO aCcomplIsH saTisFactoRY depOsitioN of Cu in mInute WIring channels aND connecting hoLEs WITh THe inTenT to densify wIrinG. furtHermORe, It hAS been DiffiCuLT tO Obtain deposit films wItH satisFactoRy planarity. StIll further, IT HAs been exPeriENcED that the deposiT filmS are not denSE films anD have Holes forMed thereiN.
fOr coping WitH thEse ProBLEmS, it has been proPOSed tO eMploy a mEthOd (SOM meThoD) whEreIn a SoLution conTaining uLtRaFiNe ParTicleS Of Cu is apPlIed OnTo a SubstRAte proVided With WiRiNG chAnnels aCCoRDIng tO tHe Spin CoaTiNg metHod tO TheReby forM a circuit On tHE subStRaTe (ULVAC tECHNICAL JOURnAl, No. 51, 1999, p. 15). HoweveR, iN thIs techNIQue, the thIckness of deposit film whiCH can be fOrmEd by oNe apPlication Is sO small ThaT The appLicatiOn musT bE rePEAted fOR ReAliZiNg wiring wiTH All The wiRiNg chAnnels fIlled up. Further, the sPIn cOating method hAs a DrawBACk In tHAt, WHen It IS inTENded to uniformly Apply the soLuTIoN containinG UltRaFine parTicles oF Cu onTO the entIre surfacE of substrAtE, porTIOn oF the solutiOn contaiNing ultraFIne paRTiCles oF Cu Would bE aPplIed ouTside tHE suBstraTe, therEbY causiNg the RaTio of utiLization of the solution coNtainiNg ultRafIne particLes OF Cu To be low.
MoReovEr, the deposItiOn oF metaL fiNE partIcleS, SuCh aS cu finE parTIcles, is efFEcTed BY ThE weight of meTAL FinE partIclES themsElveS, so that the closest PAcking with metaL finE PArtIclES may NoT be realized. ThuS, it HaS BEen experIeNced that the InterparTiCUlate ResistAnce caNnot be rEDUcED to theReby DisEnable obtAinInG A circuiT oF sATisfacToriLy Low wirIng resIStanCE. in a liquid crystal DisplAY, A
 Further, because of the d ifficultyin re duc ing  t he w irin g width, there hasbeen a limit in the fo rming  o f  int e gr atedcircuit s  o f hig he rden si t y.  Stil l f urther,  in recent  ye ar s, there isa  n ew problem  su ch that, wit h r espect  t o l o ng-di sta nce w irings uch as  a clockli n e or a data bu s li ne,the wiring resist a nc e  is increasedin acc or d an c e  wi than increas eof ch i p size, th e r e byc ausing an inc rease of pr o pag ationde lay time o f ele ct r ica l signal (R C de lay time= resist a nce×cap a city) T herefo re,  it  isn ow  n eed ed tou se  am ate rial oflo we r res ista n c e in w iri ng l ayers .
Accordingly , i t ha s  be en pr opose d to  p erfor m Cu w iring  i n place of theconv entionalwir in g w it h Alo r Al a llo ys.  For ex ample,i t h as b e en  proposed to first  p r o vi de an in sulati n gfi l m superi mp ose d on a  subs trat e  w ith wiri ng cha n ne ls  and su bs equent ly  de pos it Cu in t he wir ing chan nelsa ccording to th e  electroplati n gm e th o d, C VDmethod, etc . so as t o fo r mani ntend ed wi ri n g. However, in this te ch nique,  it h as been diffi cult to ac c o m plish sa tisf a ct o ry depositionof Cu  in minute wiring c hanne ls and c onnecting h oles wit h t heint ent t odensify wirin g .  Fur th ermore,  it  has be endif fic ult  t o obtaindepositfi lm swi thsatis f actory p la nar it y.Still furthe r, it  has  b ee n  ex perienc e dt h at t he  d epos itfi lms a re n o t d ense fi lms and h ave hole sfo rmed th erein.
For co pi ng with th es e p roblem s ,  it hasbeen proposed to employ a metho d ( SOM m etho d) wherei n a  solut ion contai ning u ltraf in e p a r ticle s of  Cu  i s appliedo n toa sub st rate  provid ed with wiring cha n nel s according t o t he s p i ncoa t in g  me th o d t o thereby form acircuit on  t h esubstrate( ULV AC  TECHNI CAL JOU RNAL, No. 51,  1999, p.  15). How ev er,i n  th is techniq ue, thethickness of de p os it fi lmwhichca n b e for med by one  appl icatio nis sosmall  t hat theapplication must be rep eatedfor r eal izing wir ing wit h all the  wir ing channe lsfil led u p.F urthe r, t h espi n  coat ingm ethod has adra w b ac k in that,w h e n i t isint e nded t o un iformly apply the solution conta inin g ult raf i ne p ar ticles of Cu o nto  t h e  entiresu rface of su bstrate,  p o rtion  of th e solu tion co n t ai n ing ul traf ine  particle s o fC u would  b ea pplied  out si de the  subst r ate, t hereby causing t he ra t i o ofu til izati on  of the solu tion conta ining ultra fine p arti clesof Cu t obe low .
M or eover, the depositio n ofmetal f in e pa rti cles,such a s Cufine  p art icles, is e ff e ct ed bytheweigh tof m etal fine particle s t h emselve s,  so t hat th e  c l o sest packi ngwithm e tal fine p a rtic l es may n ot berealiz ed. Thu s , i thas bee n e x p eriencedthat thei nte rp arti culate r es ista nc e c an not be reducedto there by disen a b le obt ain i ng a circui tof satisfact orily  l o w wirin g res istance .  In  aliq uidcry stal display, a
 Further,_because of_the difficulty in reducing_the wiring_width,_there has_been_a limit in_the forming of_integrated circuits of higher_density. Still further,_in_recent years, there is a new problem such that, with respect to long-distance wiring_such_as a_clock_line_or a data bus line,_the wiring resistance is increased_in accordance_with an increase of chip size, thereby causing_an_increase of propagation_delay time of electrical signal (RC delay time=resistance×capacity) Therefore,_it is now needed to use_a material of_lower_resistance_in wiring layers.
Accordingly, it_has been proposed to perform Cu_wiring in place of the conventional_wiring with Al or Al alloys. For_example, it has been proposed to_first provide an insulating film_superimposed on_a substrate with wiring channels_and subsequently deposit_Cu in_the wiring channels_according to the electroplating method, CVD_method, etc. so_as to form an intended wiring._However,_in this technique,_it_has_been difficult_to accomplish satisfactory_deposition_of Cu_in_minute wiring channels and connecting holes_with_the intent to densify wiring. Furthermore, it_has been difficult to_obtain_deposit films with satisfactory_planarity. Still further, it has_been experienced that the deposit films_are not_dense films_and have holes formed therein.
For coping with these problems, it has_been proposed to employ a method_(SOM method) wherein a_solution containing_ultrafine_particles of Cu_is_applied onto_a substrate provided with wiring channels according_to the_spin coating method to thereby form_a circuit on the_substrate_(ULVAC TECHNICAL JOURNAL, No. 51, 1999,_p. 15). However, in this technique,_the thickness of deposit film_which_can_be formed by one application_is so small that the application_must be repeated_for realizing wiring with all the wiring_channels_filled up. Further, the spin coating_method_has a drawback in that, when_it_is_intended to uniformly apply the_solution containing ultrafine particles of Cu_onto the entire surface of substrate, portion of the_solution containing ultrafine_particles of Cu would be_applied_outside_the substrate, thereby causing the ratio of utilization of the_solution containing_ultrafine particles of_Cu to be low.
Moreover, the deposition of metal fine particles,_such as Cu fine particles, is effected_by the weight of metal fine particles themselves, so that the_closest packing with metal fine particles may not_be realized. Thus, it has been experienced_that the interparticulate resistance_cannot_be reduced to thereby disenable obtaining a_circuit_of_satisfactorily_low wiring resistance._In a liquid_crystal display, a