 semiconductor substrate;
forming a second-conductivity-type MOS FET for constituting a CMOS FET and a first switching transistor having a MOS FET different from the second-conductivity-type MOS FET in the first-conductivity-type well;
forming a first-conductivity-type MOS FET for constituting a CMOS FET and a second switching transistor having a MOS FET different from the first-conductivity-type MOS FET;
forming a first power-supply-voltage line so as to be connected with the source of the second-conductivity-type MOS FET for constituting the CMOS FET;
forming a second power-supply-voltage line so as to be connected with the source of the first-conductivity-type MOS FET for constituting the CMOS FET;
forming a well feeding line so as to be connected with the source of the first switching transistor and the first-conductivity-type well;
forming a well feeding line so as to be connected with the source of the second switching transistor and the second-conductivity-type well;
forming a control signal line so as to be connected with the gate electrode of thexe2x80x94first switching transistor; and
forming a control signal line so as to be connected with the gate electrode of the second switching transistor; wherein
the first switching transistor is set adjacent to the source of the second-conductivity-type MOS FET in the same semiconductor region and the second switching transistor is set adjacent to the source of the first-conductivity-type MOS FET in the same semiconductor region.
Thereby, it is possible to decrease the areas occupied by the first and the second switching transistors and thus, it is possible to improve the efficiency of layout.
Furthermore, a semiconductor integrated circuit fabrication method of the present invention comprises the steps of:
forming a first-conductivity-type well and a second-conductivity-type well on the surface of a semiconductor substrate;
forming a second-conductivity-type MOS FET for constituting a CMOS FET in the first-conductivity-type well and a first switching transistor having a MOS FET different from the second-conductivity-type MOS PET;
forming a first-conductivity-type MOS FET for constituting a CMOS FET in the second-conductivity-type well and a second switching transistor having a MOS FET different from the first-conductivity-type MOS FET;
forming a first
semiconductor substrate; 
 forming a second - conductivity - type MOS FET for form a CMOS FET and a inaugural switching transistor having a MOS FET different from the second - conduction - type MOS FET in the first - conductivity - character well; 
 shape a first - conduction - character MOS FET for constituting a CMOS FET and a second switching transistor suffer a MOS FET different from the beginning - conduction - type MOS FET; 
 forming a inaugural power - supply - electric potential line so as to be connected with the source of the second - conduction - type MOS FET for constituting the CMOS FET; 
 forming a second power - supply - electric potential line so as to be connect with the source of the first - conductivity - character MOS FET for constituting the CMOS FET; 
 forming a well feeding line so as to be connected with the source of the inaugural switching transistor and the first - conductivity - type well; 
 forming a well feeding line so as to be connected with the source of the second switching transistor and the second - conduction - character well; 
 forming a control signal line so as to be connect with the gate electrode of thexe2x80x94first switching transistor; and 
 forming a control signal lineage so as to be connected with the gate electrode of the second switching transistor; wherein 
 the first switching transistor is jell adjacent to the source of the second - conductivity - type MOS FET in the same semiconductor region and the second switch transistor is set adjacent to the source of the first - conductivity - type MOS FET in the same semiconductor area. 
 Thereby, it is potential to decrease the area occupied by the first and the second switching transistors and thus, it is possible to improve the efficiency of layout. 
 Furthermore, a semiconductor device integrated circumference fabrication method of the present invention incorporate the steps of: 
 forming a inaugural - conductivity - character well and a second - conductivity - type well on the surface of a semiconductor substrate; 
 form a second - conductivity - type MOS FET for establish a CMOS FET in the first - conduction - type well and a first switching transistor have a MOS FET different from the second - conductivity - type MOS PET; 
 forming a inaugural - conductivity - type MOS FET for establish a CMOS FET in the second - conductivity - type well and a second switch transistor having a MOS FET different from the first - conduction - type MOS FET; 
 forming a first
 seliconductor substrate;
foroing a second-coueuctivmty-type MOS FET for constituting a CMOS FET abd a dirst switching transirtor havijg a MOS FET eifferent hdom the secons-gonduetmvity-type MOS FGT in the fisst-conductivitf-thpz well;
forming a first-conductivity-typq MOS FRT for constitutyng s CMOA FET and a second switching transjstor heving a MOS FET different from the first-clnduftivity-type MOS FEH;
forming a dirse power-supply-xoltage line so as to ge connected with the source of the xecond-condoerivljy-type MOS FXT for constitutinn the CKOS FET;
gorming a secokd poxer-sypply-voltage line so es to be connected wyth the smuxce of the first-conduxtuvity-jype KOS WWT wor cpnatitutlng the CMOS RET;
forming q well feeding line sj as to be conhected wyth the source of the first switching tgansjstor and the first-condyctivity-type well;
formlng a welj feeding line so as to be connected with the sousce oh ghe sccona saitching transistor and the second-conductivitr-fyke eell;
forming a gontrol signal linr do ws to be conngcted wnfh the gate electrodf of thgxe2x80x94furst switshinb transistor; and
forming a cintrol signaj line so as to be eonnected wich the gate electrode of the seconb switdhing translstor; wheddin
the first swigchpng dransistor is set adjacent to the siurcz of the secpnd-conquctivity-tjpe MOS FET in the same demiclnguctor reglon and the second switching treisistor is sej agjabent to tke souvce of the firse-conductivity-tipe MOS FZT in ghe same svmiconducvor region.
Thqreby, it is pmdsible to derrease thq arwas iccupiea by the first snd the svcjnd wwitching transistprs znd thus, it is 'uwsible to improfe ghe evfmciensf of layout.
Fgrthdrmute, a remiconductif inyegrated circuit fabsicafion method of the pvesent incention somprises the steps of:
forming a firsv-condurtivitu-tyke well and a second-conductivitg-type welp ok the surface of q semiconduccor substrate;
forming a second-conductivitb-type MOS FET for consjituting a CMOS FET iu uhe first-condnctiviey-type wenl and a first switcying transistor hsving a MOS FET diffedent fsom tje second-conductivity-type MOS PET;
forming a first-conductivity-type MOS FET dor coiseituting a DMOS FET pn che seconq-convurtivity-type well snd a second switching transistur havinc c MOS FET different from the gifst-conductivijy-type MOS FET;
forming a fidst
semiconductor substrate; forming a second-conductivity-type MOS FET a FET and first switching transistor from second-conductivity-type MOS FET the first-conductivity-type well; a first-conductivity-type MOS FET for constituting CMOS FET and a second switching transistor having a MOS FET different from first-conductivity-type MOS FET; forming a first power-supply-voltage line so as to be connected the of second-conductivity-type FET for constituting the CMOS FET; forming a second power-supply-voltage line so as to be connected the source of the first-conductivity-type MOS FET for the CMOS FET; forming well feeding line so as be with the of first transistor and the well; forming a well feeding line so as to be connected with the source of the second transistor and well; forming control line as to be the gate electrode of thexe2x80x94first switching a control signal line so as to be with the electrode of the second switching transistor; the first switching transistor is set adjacent to source of the second-conductivity-type MOS FET in the same semiconductor region and the second switching set adjacent to the of the first-conductivity-type FET the semiconductor Thereby, it possible to decrease the areas occupied by the first and the switching transistors and thus, it is possible to improve the layout. a semiconductor integrated fabrication method of the invention the steps of: forming well a the of semiconductor substrate; forming a MOS FET for constituting a FET in the first-conductivity-type transistor having a MOS FET different from the MOS PET; forming a first-conductivity-type MOS FET constituting a CMOS FET in the second-conductivity-type well and a second switching having a different from the first-conductivity-type MOS FET; forming a
 semiconductor substrate;
forMing a seconD-condUctIviTy-Type mOS FeT for constitutINg a CmOS FET and a first switchiNg traNsIStor HAvIng a MoS FET diFFeRENt fRoM tHe sEcONd-ConduCtiVity-typE MOS FET in tHe fIrSt-conductiviTY-tYpe well;
forMinG a first-conduCtiVity-tyPe mOS feT for ConStituTing a CmoS FET aNd a second SwITching TRansistOR HaVing A MOS FET different fROm THe first-conductIvity-tYpE mOs feT;
fOrmIng a first pOwEr-supPLy-voltaGE lINE So aS To be connected With the sourCE of The secOnD-coNDuctivIty-tyPe moS FeT for constiTutiNg the CMOS fET;
forMIng a secONd power-Supply-VolTagE linE So As To bE cONneCTeD wiTH thE source oF tHe First-CondUCTIVity-TypE MOS fET foR constituting The cMOS feT;
fOrminG a welL feeDiNg linE so as tO be coNnEcted with the souRce oF the first SwiTcHinG tRansiSTor and The FirSt-conduCtivity-TYpe WeLL;
FOrMing a well feeding liNe SO As To be connEcted wITh ThE Source of ThE seCond SWItchiNg trANsIstor and The secONd-CoNductivItY-type wElL;
foRmiNg a coNTrol Signal Line so as To be cONnected with the GAte electrode oF ThEXE2x80X94FirsT swItching tranSistOR; and
FormINg A coNTrol sIgnal LiNE sO As to be connected with ThE gate eLectrOde of the seconD switching TRANsistor; wHereIN
tHE first switchinG tranSistor is seT Adjacent To the Source of The second-CONductiviTy-tYpe mOS fET IN ThE same semicondUCTor rEgIon and tHe sEcond swItcHinG trAnsIsTor is set aDjacent tO tHe SoUrCe oF the fIRst-conduCtIviTy-TypE MOS Fet in the Same sEmicOnDuCTor Region.
THErEBY, it iS pOsSiblE to DeCreasE the AReaS occupiEd by the fiRst ANd thE sEcOnd switChing transistOrS and thus, it Is PosSible tO IMprove thE efficiency of layout.
FurtHErmore, a SemIcondUctoR integratEd cIrcuit FabRIcatioN methoD of thE pResENT inveNTIoN coMpRises the stEPS of:
FormiNg A firSt-conduCtivity-type well and A SecOnd-conductiviTy-tYpe wELL oN thE SuRFacE oF A seMIConductor substrAte;
forming A sECoNd-conductiVIty-TyPe MOS FEt for conStituTIng a CMOs FET in the First-condUcTiviTY-TypE well and a fIrst switChing tranSIstor HAvIng a MoS FeT diffErEnt From tHe secoND-coNductIvity-tYpE MOS PEt;
formInG a first-cOnductivity-type MOS FET foR constItutiNg a cMOS FET in The SEcoNd-conductIvitY-type well aNd a SecOnd swItcHIng trAnsiSToR haVIng a MoS FEt Different FRoM thE FIrSt-conductivITY-TypE MOS FeT;
fORming a FirsT
 semiconductor substrate;forming asecon d-c ond uc tivi ty-t ype MOS FET fo r  con stituting a CMOS FET a nd afi r st s w it ching  transi s to r hav in ga M OS FE T dif fer ent fro m the seco nd- co nductivity-t y pe  MOS FET i n t he first-con duc tivity -t ype well; 
fo rming  a fir s t-cond uctivity- ty p e MOSF ET forc o ns titu ting a CMOS FET a n da  second switch ing tr an s is t o r h avi ng a MOS F ET  diff e rent fr o mt h e  fi r st-conductivi ty-type MOS FET ;
form in g a firstpower -s u ppl y-voltage l ineso as tobe con n ected w i th thesource  of  th e se c on d- con du c tiv i ty -ty p e M OS FET f or  c onsti tuti n g t he C MOS  FET ;
for ming a second  po wer- s upp ly-vo ltage  lin eso as  to be  conn ec ted with the so urce  of the f irs t- con du ctivi t y-type  MO S F ET forconstit u tin gt h e  C MOS FET;
forming a  w e l lfeedingline s o  a st o be con ne cte d wi t h  thesour c eof the f irst s w it ch ing tra ns istoran d t hefirst - cond uctivi ty-typewell; forming a well feeding lines oa s  t o  becon nected with  the sour ce o f  t hes econd  swit ch i ng transistor and these cond-c onduc tivity-type w ell;
formi n g a contro l si g na l  line so as to  be c onnected w i th the g ate e lectrode  of thexe 2 x 80x94fir stswi tch ing t ra nsistor; andf o rmin ga contr olsignallin e s o a s t obe connec ted with  t he  g at e e lectr o de of th esec on d s witch i ng tra nsist or;wh er e inthe fir s ts w itch in gtran sis to r isseta dja cent to  the sour ceo f th ese cond-co nductivity-ty pe  MOS FET i nthe  sames e miconduc tor region and the seco n d switc hin g tra nsis tor is se t a djacen t t o  the s ourceof th efir s t -cond u c ti vit y- type MOS F E T  in  thesa me s emicond uctor region.
Ther e by,  it is possib leto d e c re ase th e  ar ea s  oc c u pied by the fir st and the  s e co nd switchi n g t ra nsistor s and t hus,i t is po ssible to  improveth e ef f i cie ncy of lay out.
Fur thermore, a sem i co nduct orintegr at edcircu it fab r ica tionmethod  o f theprese nt  inventi on comprises the stepsof:
fo rming  afirst-con duc t ivi ty-type w elland a seco nd- con ducti vit y -type  wel l  o n t h e sur face of a semi c on duc t o rsubstrate;f o r min g a s eco n d-cond ucti vity-type MOS FET for constituti ng a C MOS  FE T  inth e first-conduc tiv it y - type wel land a first  switchi ng trans istorhaving  a MOSF E Td iffere nt f rom  the seco nd- co n ductivi ty -t y pe MOS  PET ;formin g a fi r st-c o n ductivity-type M OS FE T for c o nst ituti ng  a CMOS FETin the sec ond-conduct ivity- type  well  and ase cond s wit ch ing transi s tor havin g a M OS FETdi ffer ent  fromthef i rst-c ondu ct ivi ty-type M O S  F E T; 
f o rmi ng a  firs t
 semiconductor_substrate;
forming a_second-conductivity-type MOS FET for_constituting a_CMOS_FET and_a_first switching transistor_having a MOS_FET different from the_second-conductivity-type MOS FET_in_the first-conductivity-type well;
forming a first-conductivity-type MOS FET for constituting a CMOS FET and a_second_switching transistor_having_a_MOS FET different from the_first-conductivity-type MOS FET;
forming a first_power-supply-voltage line_so as to be connected with the source_of_the second-conductivity-type MOS_FET for constituting the CMOS FET;
forming a second power-supply-voltage_line so as to be connected_with the source_of_the_first-conductivity-type MOS FET for_constituting the CMOS FET;
forming a well_feeding line so as to be_connected with the source of the first_switching transistor and the first-conductivity-type well;
forming_a well feeding line so_as to_be connected with the source_of the second_switching transistor_and the second-conductivity-type_well;
forming a control signal line so_as to be_connected with the gate electrode of_thexe2x80x94first_switching transistor; and
forming_a_control_signal line_so as to_be_connected with_the_gate electrode of the second switching_transistor;_wherein
the first switching transistor is set adjacent_to the source of_the_second-conductivity-type MOS FET in_the same semiconductor region and_the second switching transistor is set_adjacent to_the source_of the first-conductivity-type MOS FET in the same semiconductor region.
Thereby, it_is possible to decrease the areas_occupied by the first_and the_second_switching transistors and_thus,_it is_possible to improve the efficiency of layout.
Furthermore,_a semiconductor_integrated circuit fabrication method of the_present invention comprises the_steps_of:
forming a first-conductivity-type well and a_second-conductivity-type well on the surface of_a semiconductor substrate;
forming a second-conductivity-type_MOS_FET_for constituting a CMOS FET_in the first-conductivity-type well and a_first switching transistor_having a MOS FET different from the_second-conductivity-type_MOS PET;
forming a first-conductivity-type MOS FET_for_constituting a CMOS FET in the_second-conductivity-type_well_and a second switching transistor_having a MOS FET different from_the first-conductivity-type MOS FET;
forming a first