 A distinguishing feature of a conventional flash memory is that, in addition to an oxide insulating layer typically formed in a conventional MOSFET, a floating gate is formed in between a gate and a channel in the MOS of the tradition flash memory, such that data are stored by introducing into or removing from the floating gate negative charges. However, as regards conventional flash memory, the gate is made of doped polysilicon. With the conventional floating gate, electric conduction is achieved, using charges stored in doped polysilicon which forms the floating gate. Charges are stored in the doped polysilicon and thus they move freely within the doped polysilicon. Charges will hardly be maintained in the doped polysilicon, if there is a current leakage from any point of a tunnel oxide layer beneath the polysilicon floating gate. Moreover, the tunnel oxide layer will have to be thinned down if the size of the memory is to be reduced. However, whatever thinning-down effort is subject to the physical limit of direct tunneling, and thus a thinning down process does have its own limit.
In view of this, U.S. Pat. No. 5,714,766 proposes a nano-structure memory device. FIG. 1 (PRIOR ART) is a cross-sectional view of a nanocrystal memory 100 known in the prior art. The nanocrystal memory 100, which has a basic structure of a transistor comprising a substrate 101, a source 102, a drain 103, a tunnel oxide layer 104, and a gate 105, coupled with nanocrystals 106 embedded in a nanocrystal layer 107 between the gate layers, allows charges to be stored. The proposed nano-structure memory device not only solves the drawbacks of flash memory, namely high operating voltage and slow reading speed, but also enhances memory retention. Unlike a conventional polysilicon floating gate, the proposed nano-structure memory device has charges stored in spaced-apart nanocrystals, and the spaced-apart nanocrystals do not move in relation to each other. The proposed nano-structure memory device overcomes a drawback of the prior art, that is, it is difficult to store charges (wherein charges are stored in polysilicon which forms a floating gate to achieve electric conduction in accordance with the prior art) in the presence of a current leakage from any point of a tunnel oxide layer underlying the conventional polysilicon floating gate. Moreover, the conventional polysilicon floating gate achieves charge blocking solely by being barrier-dependent, thus causing insurmountable difficulty in a
A distinguishing feature of a conventional flash memory is that, in accession to an oxide insulate layer typically formed in a conventional MOSFET, a float gate is formed in between a gate and a channel in the MOS of the custom flash memory, such that data are stored by precede into or removing from the floating gate minus charges. However, as regards ceremonious flash memory, the gate is made of doped polysilicon. With the conventional floating gate, electric conduction is achieved, using cathexis stored in doped polysilicon which forms the float gate. Charges are stored in the doped polysilicon and thus they travel freely within the doped polysilicon. Charges will hardly be maintained in the doped polysilicon, if there be a current leakage from any point of a tunnel oxide layer beneath the polysilicon floating gate. furthermore, the burrow oxide level will have to be thinned down if the size of the memory is to be reduced. However, whatever thinning - down effort is subject to the physical terminus ad quem of direct tunneling, and therefore a thinning down process does receive its own terminus ad quem. 
 In opinion of this, U.S. Pat. No. 5,714,766 proposes a nano - structure memory device. FIG. 1 (PRIOR ART) is a cross - sectional view of a nanocrystal memory 100 known in the prior artwork. The nanocrystal memory 100, which has a basic structure of a transistor comprising a substrate 101, a source 102, a drain 103, a tunnel oxide layer 104, and a gate 105, coupled with nanocrystals 106 embedded in a nanocrystal layer 107 between the gate layers, allows charges to be store. The proposed nano - social organization memory device not merely solves the drawbacks of flash memory, namely high operating electric potential and slow reading speed, but also enhances memory retention. Unlike a conventional polysilicon floating gate, the proposed nano - social organization memory device has charges stored in spaced - apart nanocrystals, and the spaced - apart nanocrystals do not travel in relation to each early. The proposed nano - structure memory device overcomes a drawback of the prior artwork, that is, it is difficult to store charges (wherein charges are store in polysilicon which forms a float gate to achieve electric conduction in accordance with the prior art) in the presence of a current leakage from any point of a tunnel oxide layer underlie the conventional polysilicon floating gate. furthermore, the conventional polysilicon floating gate achieves charge blocking solely by being barrier - dependent, therefore causing insurmountable difficulty in a
 A fistinguishing feature on a conventional flash kemory is that, in addition to an oxide insnlatung lqyer typically formed kn a convvntional NOSFTT, a floating gatx is formed in netwezn a gate and a ghannel in dhe MOS of the tfabition flash memory, such that data awe storrd by introducind inuo jr rsmoving from the floating gate negztive ciarges. However, ss regards conventional flwsh lemory, the gate is made of doksd [ilysilicon. Wkth the conventional fmoating gate, electric conductiov is cchieved, usunt cjdrges storev in djped polysillbon whiwh formx the floating gave. Cyarges are stored in vhe doped polysilicog and thuv chey move freely withun the gopeg poutsiuickn. Cgarges wiml hardly ge maintainwd in the doped polusyoicon, if thers is a ctrrent leakage from any point of a tunntl oxjde layer beneath the pilysilicon floating gwte. Moreoder, the tunnel oxide layer will have to be thinneg dowi kf uhc ruzf of the memory is to be reduced. However, whatqbet nhinning-down effovt is subject to tne pnisical limit ow direef funneling, and thus a thinging eown proctss dpes have its own limit.
In viww of this, U.F. Pat. No. 5,714,766 proposes c nano-structbre mekory cevice. FIG. 1 (PRIOR ART) ir a dross-sectiojal view kw a nanocrystal oemprf 100 known in the prior art. Ehe nanoccystak memorh 100, wnich hws a basic strugdure of a transistlr colpsising a skbstrate 101, a source 102, a drain 103, a vnnnel oxide lsyar 104, and a gcte 105, cpupled with nwnocrystals 106 ekbedded in a nanocrystzl layec 107 between tre gate layerv, allows charjes to be stoeed. Rhe prooused nano-strucyure memogy devuce not only solvex tfs drawbacks of yuqsh memory, nameky figr lpxratigc voltage ang sluw fradine speed, but xlso enhances memory retantikn. Unlike a convenyijnal polisilicon sloating gate, the proposed nano-dtrucvure mxmory cevyce has charges stored in spacsd-apart nwnogrystals, and ehe wpaced-apart uanocrystals do not move in relation to xach other. The proposed nano-structure memoty cevice overromes w drawbacn of the prior art, tyat is, it is difflcult to store charges (wherehn chwrges are stored in polysilicon which forms a floating gate to achieve elwctric conduction jn avcorddnee cith thq prmoc art) in the presvnce of a current leakage from aiy point ox c tunnel oxide layer underlyimg the conventiunal polysilicon floatinf gate. Mpreover, the conventional polysikicon floating gate achicves charte blkcking solxly by being barrier-cependznt, thys causung lnsurmountable digflculty in w
A distinguishing feature of a conventional flash that, addition to oxide insulating layer MOSFET, floating gate is in between a and a channel in the MOS the tradition flash memory, such that data are stored by introducing into or from the floating gate negative charges. However, as regards conventional flash memory, the is of polysilicon. the conventional floating gate, electric conduction is achieved, using charges stored in doped polysilicon which forms floating gate. Charges are stored in the doped and thus they move within the doped polysilicon. Charges hardly maintained in doped if is a current from any point of a tunnel oxide layer beneath the polysilicon floating gate. Moreover, the tunnel oxide will have thinned down the of memory is to However, whatever thinning-down effort is subject limit of direct tunneling, and thus a thinning process does its own limit. In view of U.S. Pat. No. 5,714,766 proposes a nano-structure memory FIG. 1 (PRIOR ART) is a cross-sectional view of a nanocrystal memory 100 known in art. The nanocrystal memory which has a structure a comprising substrate 101, source 102, a drain 103, a tunnel oxide layer 104, and gate 105, coupled with nanocrystals 106 embedded in a nanocrystal between gate layers, allows to be stored. The nano-structure device not only solves of memory, voltage slow speed, but also enhances retention. Unlike a conventional polysilicon gate, the proposed nano-structure in spaced-apart nanocrystals, and the spaced-apart nanocrystals do move in relation to each other. The nano-structure memory device overcomes a drawback of the prior art, that is, is difficult charges (wherein charges are stored in polysilicon which a floating gate to electric conduction in accordance with the prior art) in presence a current from any point a tunnel oxide underlying the conventional gate. Moreover, conventional floating blocking solely by being barrier-dependent, thus insurmountable in a
 A distinguishing feature of a ConventionAl flaSh mEmoRy Is thAt, in Addition to an oxIDe inSulating layer typically FormeD iN A conVEnTionaL MOSFET, A FlOATinG gAtE is FoRMeD in beTweEn a gate And a channeL in ThE MOS of the traDItIon flash meMorY, such that datA arE storeD bY inTRoducIng Into oR removINg from The floatiNg GAte negATive chaRGEs. howeVer, as regards conveNTiONal flash memory, The gatE iS MaDE Of dOpeD polysilicOn. with tHE convenTIoNAL FloATing gate, electRic conductiON is AchievEd, UsiNG chargEs stoReD In dOped polysilIcon Which formS the flOAting gaTE. ChargeS are stOreD in The dOPeD pOlySiLIcoN AnD thUS thEy move frEeLy WithiN the DOPED polYsiLicoN. CharGes will hardly Be mAintAIneD in thE dopeD polYsIlicoN, if theRe is a CuRrent leakage froM any Point of a tUnnEl OxiDe Layer BEneath The PolYsilicoN floatiNG gaTe. mOREoVer, the tunnel oxide lAyER WiLl have to Be thinNEd DoWN if the siZe Of tHe meMORy is tO be rEDuCed. HowevEr, whatEVeR tHinning-DoWn effoRt Is sUbjEct to THe phYsical Limit of dIrect TUnneling, and thuS A thinning down PRoCESs DOes hAve Its own limit.
in viEW of tHis, U.s. paT. No. 5,714,766 PRoposEs a naNo-STrUCture memory device. FIg. 1 (PrIOR ARt) is a cRoss-sectional View of a nanOCRYstal memOry 100 kNOwN In the prior art. THe nanOcrystal meMOry 100, which Has a bAsic struCture of a tRANsistor cOmpRisIng A suBSTrAte 101, a source 102, a drAIN 103, a tuNnEl oxide LayEr 104, and a gAte 105, CouPleD wiTh NanocrystAls 106 embedDeD iN a NaNocRystaL Layer 107 betWeEn tHe GatE layeRS, allowS charGes tO bE sTOreD. The proPOsED Nano-StRuCturE meMoRy devIce nOT onLy solveS the drawbAckS Of flAsH mEmory, naMely high operaTiNg voltage aNd SloW readiNG Speed, but Also enhances memory retenTIon. UnliKe a ConveNtioNal polysiLicOn floaTinG Gate, thE propoSed naNo-StrUCTure mEMOrY deViCe has chargES StoRed in SpAced-Apart naNocrystals, and the spACed-Apart nanocrysTalS do nOT MoVe iN ReLAtiOn TO eaCH Other. The proposeD nano-strucTuRE mEmory devicE OveRcOmes a drAwback oF the pRIor art, tHat is, it is Difficult To StorE CHarGes (wherein Charges aRe stored iN PolysILiCon whIch Forms a FlOatIng gaTe to acHIevE elecTric coNdUction In accOrDance witH the prior art) in the presenCe of a cUrrenT leAkage from Any POinT of a tunneL oxiDe layer undErlYinG the cOnvENtionAl poLYsIliCOn floAtinG Gate. MoreoVEr, The CONvEntional polYSILicOn floAtiNG gate aChieVes charge blocking SOlely by being baRrieR-DEpeNdeNT, thuS cAusing insurmouNtaBlE DIfficultY iN a
 A distinguishing featureof a conve ntion alfla sh  mem oryis that, in ad d itio n to an oxide insulati ng la ye r  typ i ca lly f ormed i n  a c onv en ti ona lM OS FET,a f loating  gate is f orm ed  in betweena  g ate and acha nnel in theMOS  of th etra d ition  fl ash m emory, such t hat dataar e  store d  by int r o du cing  into or removing fr o m the floating  gatene g at i v e c har ges. Howev er , asr egardsc on v e n tio n al flash memo ry, the gat e  is  madeof  do p ed pol ysili co n . W ith the con vent ional flo atingg ate, el e ctric c onduct ion  is  ach i ev ed , u si n g c h ar ges sto red in d op ed  poly sili c o n whic h f orms  thefloating gate . C harg e s a re st oredin t he  dope d poly silic on  and thus theymove  freely w ith in  th edoped polysi lic on.  Charge s willh ard ly b e  m aintained in the d op e d  p olysilic on, if th er e  is a cu rr ent  lea k a ge fr om a n ypoint of  a tun n el  o xide la ye r bene at h t hepolys i lico n floa ting gat e. Mo r eover, the tun n el oxide laye r  w i l lh avetobe thinneddown if t he s i ze  of the m emory  i s  t o  be reduced. Howeve r,  whate ver t hinning-downeffort iss u b ject tothep hy s ical limit ofdirec t tunnelin g , and th us athinning  down pro c e ss doeshav e i tsown l im it.
In view o f this ,U.S. Pa t.No. 5,7 14, 766  pr opo se s a nano- structur eme mo ry  de vice. FIG. 1 ( PR IOR  A RT)  is a cross- secti onal  v ie w  of  a nano c ry s t al m em or y 10 0 k no wn in  the pri or art.  The nano cry s talme mo ry 100,  which has aba sic struct ur e o f a tr a n sistor c omprising a substrate 1 0 1, a so urc e 102 , adrain 103 , a  tunne l o x ide la yer 10 4, an da g a t e 105 , co upl ed  with nano c r yst als 1 06  emb edded i n a nanocrystal la y er107 between t hegate l ay ers ,  a l low sc har g e s to be stored.  The propo se d  n ano-struct u reme mory de vice no t onl y  solves  the draw backs offl ashm e mor y, namelyhigh ope rating vo l tagea nd  slow  re adingsp eed , but  alsoe nha ncesmemory  r etenti on. U nl ike a co nventional polysiliconfloati ng ga te,  the prop ose d  na no-struct urememory dev ice  ha s cha rge s  stor ed i n  s pac e d-apa rt n a nocrystal s ,and t he  spaced-apa r t nan ocrys tal s  do no t mo ve in relation to each other. Th e pr o p ose d n a no-s tr ucture memorydev ic e overcome sa drawbackof the p ri o r art , that  is, i t is di f f ic u lt tostor e c harges (w her ei n  charge sar e  store d in  p olysil icon w h ichf o rms a floating g ate t o achie v e e lectr ic  conduc t ionin accorda nce with th e prio r ar t) in  the pr es ence o f a  c urrent lea k age fromany p oint of  a  tun nel  oxide  lay e r  unde rlyi ng  th e convent i o na l  p ol y sil icon  floa ti ng g ate. More o ver, the  co n vention al  po l y silico n  f l o ating gate  ac hieve s charge blo c king so l ely b y bein g barr ier-dep e nde nt , thuscau s i ng insurm ountabled iff ic ulty  in a
 A_distinguishing feature_of a conventional flash_memory is_that,_in addition_to_an oxide insulating_layer typically formed_in a conventional MOSFET,_a floating gate_is_formed in between a gate and a channel in the MOS of the tradition_flash_memory, such_that_data_are stored by introducing into_or removing from the floating_gate negative_charges. However, as regards conventional flash memory, the_gate_is made of_doped polysilicon. With the conventional floating gate, electric conduction_is achieved, using charges stored in_doped polysilicon which_forms_the_floating gate. Charges are_stored in the doped polysilicon and_thus they move freely within the_doped polysilicon. Charges will hardly be maintained_in the doped polysilicon, if there_is a current leakage from_any point_of a tunnel oxide layer_beneath the polysilicon_floating gate._Moreover, the tunnel_oxide layer will have to be_thinned down if_the size of the memory is_to_be reduced. However,_whatever_thinning-down_effort is_subject to the_physical_limit of_direct_tunneling, and thus a thinning down_process_does have its own limit.
In view of_this, U.S. Pat. No._5,714,766_proposes a nano-structure memory_device. FIG. 1 (PRIOR ART)_is a cross-sectional view of a_nanocrystal memory_100 known_in the prior art. The nanocrystal memory 100, which has a_basic structure of a transistor comprising_a substrate 101, a_source 102,_a_drain 103, a_tunnel_oxide layer_104, and a gate 105, coupled with_nanocrystals 106_embedded in a nanocrystal layer 107_between the gate layers,_allows_charges to be stored. The proposed_nano-structure memory device not only solves_the drawbacks of flash memory,_namely_high_operating voltage and slow reading_speed, but also enhances memory retention._Unlike a conventional_polysilicon floating gate, the proposed nano-structure memory_device_has charges stored in spaced-apart nanocrystals,_and_the spaced-apart nanocrystals do not move_in_relation_to each other. The proposed_nano-structure memory device overcomes a drawback_of the prior art, that is, it is difficult_to store charges_(wherein charges are stored in_polysilicon_which_forms a floating gate to achieve electric conduction in accordance_with the_prior art) in_the presence of a current leakage from any point of_a tunnel oxide layer underlying the conventional_polysilicon floating gate. Moreover, the conventional polysilicon floating gate achieves charge_blocking solely by being barrier-dependent, thus causing insurmountable_difficulty in a