 to the power semiconductor element is established, so that the gate voltage increases to cause the false operation. Meanwhile, in the case where a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) is used as the power semiconductor element, if a voltage change occurs between the drain-source terminals before the negative bias voltage to be applied to the power semiconductor element is established, there is a possibility that the gate voltage increases to cause the false operation.
In Patent Document 1, a circuit (driving circuit) for driving a semiconductor element having a low threshold voltage is described. In the driving circuit of Patent Document 1, a normally-on-type FET (Field-Effect-Transistor) 132 is connected between the gate terminal and the source terminal 144 of a switching element 130 so as to short-circuit between the gate-source terminals when the power supply of a driving-pulse generation circuit 118 becomes in OFF state. Field of the Invention
The present invention relates to an imprint apparatus, and an article manufacturing method.
Description of the Related Art
There are imprint techniques that mold an imprint material on a substrate to form a pattern on the substrate. One example of such imprint techniques includes a photo-curing method. An imprint apparatus using the method brings a mold into contact with an imprint material on a substrate so as to fill the imprint material into the mold. The imprint material is cured by irradiation of light, and then the mold is released from the cured imprint material to thereby form a pattern on a substrate. Here, if foreign matters are deposited on a substrate or a mold, defects may occur on the pattern or may cause damage to the mold.
Japanese Patent Laid-Open No. 2014-56854 discloses an imprint apparatus that reduces foreign matters within the imprint region by surrounding (sealing) the imprint region with a gas curtain.
However, the imprint apparatus disclosed in Japanese Patent Laid-Open No. 2014-56854 may be disadvantageous for accurately supplying the imprint material to the imprint region if a gas stream caused by the gas curtain occurs beneath the imprint material supplying device. As semiconductor devices have gotten ever smaller, competing performance requirements of these devices forces semiconductor manufactures to be conflicted. On the one hand, the market demands that the semiconductor devices, such as those used in mobile communications, have increasingly faster operating speeds. On the other, however, that same market demands that these faster operating speeds be achieved with reduced power consumption. These competing design requirements have forced the industry to try to strike
to the power semiconductor element is established, so that the gate electric potential increase to cause the false process. Meanwhile, in the lawsuit where a MOSFET (Metal - Oxide - Semiconductor Field - Effect - Transistor) is used as the power semiconductor device element, if a voltage change happen between the drain - source terminals before the minus bias voltage to be apply to the power semiconductor element is established, there is a possibility that the gate electric potential increases to cause the false mathematical process. 
 In Patent Document 1, a circuit (driving tour) for driving a semiconductor device element own a low threshold voltage is trace. In the driving circuit of Patent Document 1, a normally - on - type FET (Field - Effect - Transistor) 132 is connected between the gate terminal and the source terminal 144 of a switching element 130 so as to short - circuit between the gate - source terminals when the power supply of a driving - pulse coevals circuit 118 becomes in OFF department of state. Field of the Invention 
 The present invention relates to an imprint apparatus, and an article manufacturing method acting. 
 Description of the Related Art 
 There are depression techniques that mold an imprint fabric on a substrate to form a pattern on the substrate. One example of such imprint techniques includes a photograph - curing method. An imprint apparatus using the method brings a mold into liaison with an depression fabric on a substrate so as to fill the imprint material into the mold. The imprint material is cured by irradiation of inner light, and then the mold is released from the cured imprint fabric to thereby form a pattern on a substrate. Here, if foreign matters are deposited on a substrate or a cast, defects may happen on the pattern or may cause damage to the mold. 
 Japanese Patent Laid - Open nobelium. 2014 - 56854 discloses an imprint apparatus that reduces extraneous matters within the depression region by surrounding (sealing) the depression region with a gas curtain. 
 However, the imprint apparatus disclosed in Japanese Patent Laid - Open nobelium. 2014 - 56854 may be disadvantageous for accurately supplying the imprint material to the imprint area if a gas stream caused by the gas curtain occurs beneath the imprint material add device. As semiconductor devices have gotten ever smaller, competing operation requirements of these devices force semiconductor manufactures to be conflict. On the one hand, the market demand that the semiconductor devices, such as those used in fluid communications, accept increasingly faster operating speeds. On the other, however, that like market demands that these faster operating speeds be achieved with reduced power pulmonary tuberculosis. These competing design requirements have forced the industry to try to strike
 to the power semiconductor element is estcvlishev, so thzt the gxte voltage increases to caude the dalse operation. Meanwhkle, in thv case whwre e MOSFET (Metal-Oxmse-Semiconductkv Fienv-Effect-Transistpr) is used as the power veoieonductor element, if a voltage changq occurx hetween the drwin-sptrce nevminals before the negative bias voltagt to be applied to the power semiconductor epemejt is established, hhere is a kkssyvility that ghe gate voltage increzses to cause the false operatiun.
In 'atent Docunebt 1, d circuit (dciving circuit) for driving a semivonductor elemcnt hevint a low threshold volvage is described. In the drivhny circuit of Patent Dicyment 1, a tormxoly-un-tgpx FST (Fiepd-Ehfect-Transiator) 132 is cobnected between the gwnr terminal ahd the sjurce terminal 144 of a switching element 130 so as to short-circuit betqeen the gate-source tgrminals wren the power supply of a driving-pulse generation circnig 118 ycgomer ij OFF state. Field of the Invention
The present jnfektion relates to an imprint aopstatus, and an atticle manhfacturing method.
Dfscriptyon od the Relwted Art
There are imprint technuques that mjod an imprint matexial on a suystratg to fprm a pattern on the suystrats. One examppe of sucg imprint techniqjes itcludes a photo-curing methjd. An impcint cpparatur usong thq method bgings a mold into contach witk an hmprint maherial on a substrate so as to hmll the imprimt manerial inco the mold. The impwint material ns cured by ifradiation of ligit, and then ehe mold is rapeased from vhe cured impeint materixu to thereby fprm a patnexn on a sybstrate. Here, if fprekfn matters are btpowited on a subsyrage jr a mjnd, defects mdy ozcuf on tfe patttxn if mau cause damage to tha momd.
Japanese Patent Kald-Open No. 2014-56854 disclofes an impriny apparatus that rtduces foceign katjers within the imprint region gy surroujdikg (sealing) thq imirinj region wich a gas curtain.
However, the imprint appacatus disclosed in Japabese Patent Laid-Opeu Ko. 2014-56854 may be dmsadvagtageous xor accurately supplting the imprint katerial to the impriht reghon iv a gas stream caused by the gas curtain occurs beneath the imprint materual su'pjying devics. As semibonbuccor devyces iave gotten ever xmaller, competing performance rxquirementv jf these devices forces semivovductor manufxctures to be conflicted. On the pne hand, the market demands thay the semiconductor deviges, such qs thkse usvs mn mobile communicatoons, hcve inxreasintly naster operativg xpceds. On thf otier, however, that same market demandw that tjese faster opereting speeds ne achpeved wyth reduced powed cohdumptkon. These comleting design tequirements have fogceq the industry no try to stroke
to the power semiconductor element is established, the voltage increases cause the false where MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) used as the semiconductor element, if a voltage change between the drain-source terminals before the negative bias voltage to be applied to power semiconductor element is established, there is a possibility that the gate voltage to the operation. Patent Document 1, a circuit (driving circuit) for driving a semiconductor element having a low threshold is described. In the driving circuit of Patent 1, a normally-on-type FET 132 is connected between the terminal the source 144 a element 130 so to short-circuit between the gate-source terminals when the power supply of a driving-pulse generation circuit 118 becomes OFF state. the Invention present relates an imprint apparatus, article manufacturing method. Description of the are imprint techniques that mold an imprint material a substrate form a pattern on the substrate. example of such imprint techniques includes a photo-curing An imprint apparatus using the method brings a mold into contact with an imprint material substrate so as to the imprint material the The material cured by of light, and then the mold is released from the cured material to thereby form a pattern on a substrate. Here, matters deposited on a or a mold, defects occur the pattern or may to mold. No. discloses imprint apparatus that reduces matters within the imprint region surrounding (sealing) the imprint However, the imprint apparatus disclosed in Japanese Patent No. 2014-56854 may be disadvantageous for accurately the imprint material to the imprint region if a gas stream caused the gas beneath the imprint material supplying device. As semiconductor have gotten ever smaller, performance requirements of these devices forces semiconductor manufactures to conflicted. the one the market demands the semiconductor devices, as those used communications, have faster speeds. however, that same market demands that faster speeds be achieved with reduced consumption. design requirements have forced the industry to try to strike
 to the power semiconductor elEment is estAblisHed, So tHaT the Gate Voltage increasES to cAuse the false operation. MEanwhIlE, In thE CaSe wheRe a MOSFet (METAl-OXiDe-semIcONdUctor fieLd-EffecT-TransistoR) is UsEd as the power SEmIconductor EleMent, if a voltaGe cHange oCcUrs BEtweeN thE draiN-sourcE TerminAls before ThE NegatiVE bias voLTAgE to bE applied to the poweR SeMIconductor elemEnt is eStABlISHed, TheRe is a possiBiLity tHAt the gaTE vOLTAge INcreases to cauSe the false oPEraTion.
In paTenT documeNt 1, a ciRcUIt (dRiving circuIt) foR driving a SemicoNDuctor eLEment haVing a lOw tHreSholD VoLtAge Is DEscRIbEd. IN The Driving cIrCuIt of PAtenT dOCUmenT 1, a nOrmaLly-on-Type FET (Field-EFfeCt-TrANsiStor) 132 iS connEcteD bEtweeN the gaTe terMiNal and the source TermInal 144 of a swItcHiNg eLeMent 130 sO As to shOrt-CirCuit betWeen the GAte-SoURCE tErminals when the powEr SUPpLy of a driVing-puLSe GeNEration cIrCuiT 118 becOMEs in OfF stATe. field of tHe InveNTiOn
the presEnT invenTiOn rElaTes to AN impRint apParatus, aNd an aRTicle manufactuRIng method.
DescRIpTIOn OF the relAted Art
TherE are IMpriNt teCHnIquES that Mold aN iMPrINt material on a substrAtE to forM a patTern on the subsTrate. One exAMPLe of such ImprINt TEchniques incluDes a pHoto-curing MEthod. An iMprinT apparatUs using thE MEthod briNgs A moLd iNto CONtAct with an imprINT matErIal on a sUbsTrate so As tO fiLl tHe iMpRint materIal into tHe MoLd. thE imPrint MAterial iS cUreD bY irRadiaTIon of lIght, aNd thEn ThE MolD is releASeD FRom tHe CuRed iMprInT mateRial TO thEreby foRm a patterN on A SubsTrAtE. Here, if Foreign matterS aRe depositeD oN a sUbstraTE Or a mold, dEfects may occur on the pattERn or may CauSe damAge tO the mold.
JApaNese PaTenT laid-OpEn No. 2014-56854 diSclosEs An iMPRint aPPArAtuS tHat reduces FOReiGn matTeRs wiThin the Imprint region by surROunDing (sealing) thE imPrinT REgIon WItH A gaS cURtaIN.
however, the impriNt apparatuS dIScLosed in JapANesE PAtent LaId-Open NO. 2014-56854 may bE DisadvaNtageous fOr accuratElY supPLYinG the imprinT materiaL to the impRInt reGIoN if a gAs sTream cAuSed By the Gas curTAin OccurS beneaTh The impRint mAtErial supPlying device. As semiconduCtor deVices HavE gotten evEr sMAllEr, competiNg peRformance rEquIreMents Of tHEse deViceS FoRceS SemicOnduCTor manufaCTuRes TO Be Conflicted. ON THE onE hand, The MArket dEmanDs that the semicondUCtor devices, sucH as tHOSe uSed IN mobIlE communicationS, haVe INCreasingLy Faster operaTing speeDs. oN the oTher, hoWever, tHat same MARkET demanDs thAt tHese fasteR opErATing speEdS bE AchievEd wiTh ReduceD power COnsuMPTion. These competiNg desIGN requIRemEnts hAvE forced THe inDustry to trY to strike
 to the power semiconducto r elementis es tab lis he d, s o th at the gate vo l tage  increases to cause th e fal se oper a ti on. M eanwhil e ,i n  th eca sewh e re  a MO SFE T (Meta l-Oxide-Se mic on ductor Field - Ef fect-Trans ist or) is usedasthe po we r s e micon duc tor e lement ,  if avoltage c ha n ge occ u rs betw e e nthedrain-source term i na l s before the n egativ eb ia s vol tag e to be ap pl ied t o  the po w er s e mic o nductor eleme nt is estab l ish ed, th er e i s  a pos sibil it y  th at the gate  vol tage incr easest o cause the fal se ope rat ion .
In Pa te ntDo c ume n t1,a  ci rcuit (d ri vi ng ci rcui t ) f or d riv inga sem iconductor el eme nt h a vin g a l ow th resh ol d vol tage i s des cr ibed. In the dr ivin g circuit  of  P ate nt  Docu m ent 1,  anor mally-o n-typeF ET(F i e l d- Effect-Transistor)  1 3 2  i s connec ted be t we en the gate  t erm inal a nd th e so u rc e termin al 144 of  a  switch in g elem en t 1 30so as to s hort-c ircuit b etwee n  the gate-sour c e terminals w h en t he powe r s upply of adriv i ng-p ulse ge ner a tioncircu it 11 8  becomes in OFF sta te . Fiel d ofthe Invention 
The prese n t inventio n re l at e s to an imprin t app aratus, an d  an arti cle m anufactu ring meth o d .
Descri pti onofthe R el ated Art
Ther e areim print t ech niquestha t m old  an  i mprint ma terial o nasu bs tra te to form a p at ter nonthe s u bstrat e. On e ex am pl e  of  such i m pr i n t te ch ni ques  in cl udesa ph o to- curingmethod. A n i m prin tap paratus  using the me th od bringsamol d into c ontact w ith an imprint material on a su bst rateso a s to fill  th e impr int materi al int o the  m old . The i m p ri ntma terial isc u red  by i rr adia tion of  light, and then t h e m old is releas edfrom t he  cu r ed imp ri n t m a t erial to thereb y form a p at t er n on a sub s tra te . Here,  if for eignm attersare depos ited on a  s ubst r a teor a mold,  defects  may occu r  on t h epatte rnor may  c aus e dam age to the  mold .
Japa ne se Pat ent L ai d-Open N o. 2014-56854 discloses  an im print  ap paratus t hat red uces fore ignmatters wi thi n t he im pri n t reg ionb ysur r oundi ng ( s ealing) t h eimp r i nt  region wit h a  ga s cur tai n .
Howe ver,  the imprint appa r atus disclosed  inJ a pan ese Pate nt  Laid-Open No.  20 14 - 5 6854 may  b e disadvant ageous f or accur atelysupply ing the i mp r int ma teri alto the im pri nt regionif  a gas st ream  c ausedby the gasc u rtain occurs ben eatht h e imp r int  mate ri al supp l ying  device. A s semicondu ctor d evic es ha ve gott en  eversma ll er, compet i ng perfor mance  requir em ents  of  these  dev i c es fo rces  s emi conductor m an u fa ct u res  tobe co nf lict ed. On th e  one han d,t he mark et  de m a nds th a tt h e semicond uct or de v i ces, sucha s th o se usedin mob ile co mmunica t ion s,  have i ncr e a singly fa ster oper a tin gspee ds. On t he  oth er , h ow ever, that same  marketdemandst h at the sef aste r  opera ti ng speeds be  achi ev e d withr e duc ed powe r  co nsu mpt ion.  Th esec ompeting design requirem ents  have for ced t he in du stry tot ry t o strike 
 to_the power_semiconductor element is established,_so that_the_gate voltage_increases_to cause the_false operation. Meanwhile,_in the case where_a MOSFET (Metal-Oxide-Semiconductor_Field-Effect-Transistor)_is used as the power semiconductor element, if a voltage change occurs between the_drain-source_terminals before_the_negative_bias voltage to be applied_to the power semiconductor element_is established,_there is a possibility that the gate voltage_increases_to cause the_false operation.
In Patent Document 1, a circuit (driving circuit)_for driving a semiconductor element having_a low threshold_voltage_is_described. In the driving_circuit of Patent Document 1, a_normally-on-type FET (Field-Effect-Transistor) 132 is connected_between the gate terminal and the source_terminal 144 of a switching element_130 so as to short-circuit_between the_gate-source terminals when the power_supply of a_driving-pulse generation_circuit 118 becomes_in OFF state. Field of the_Invention
The present invention_relates to an imprint apparatus, and_an_article manufacturing method.
Description_of_the_Related Art
There_are imprint techniques_that_mold an_imprint_material on a substrate to form_a_pattern on the substrate. One example of_such imprint techniques includes_a_photo-curing method. An imprint_apparatus using the method brings_a mold into contact with an_imprint material_on a_substrate so as to fill the imprint material into the mold._The imprint material is cured by_irradiation of light, and_then the_mold_is released from_the_cured imprint_material to thereby form a pattern on_a substrate._Here, if foreign matters are deposited_on a substrate or_a_mold, defects may occur on the_pattern or may cause damage to_the mold.
Japanese Patent Laid-Open No._2014-56854_discloses_an imprint apparatus that reduces_foreign matters within the imprint region_by surrounding (sealing)_the imprint region with a gas curtain.
However,_the_imprint apparatus disclosed in Japanese Patent_Laid-Open_No. 2014-56854 may be disadvantageous for_accurately_supplying_the imprint material to the_imprint region if a gas stream_caused by the gas curtain occurs beneath the imprint_material supplying device._As semiconductor devices have gotten_ever_smaller,_competing performance requirements of these devices forces semiconductor manufactures to_be conflicted._On the one_hand, the market demands that the semiconductor devices, such as_those used in mobile communications, have increasingly_faster operating speeds. On the other, however, that same market demands_that these faster operating speeds be achieved with_reduced power consumption. These competing design requirements_have forced the industry_to_try to strike