 electrode 110, the memory cell capacitor actually forms a stacked structure in which the Ta barrier layer and the Pt electrode layer sandwich a Ta2O5 layer therebetween, and the BST or PZT film 111 and the upper capacitor electrode layer 112 are stacked consecutively on the Pt electrode layer. Thereby, the memory cell capacitor includes two capacitors connected in series, one including the Ta2O5 layer as the capacitor dielectric film and the other including the BST or the PZT film 111 as the capacitor dielectric film. As Ta2O5 has a permittivity substantially smaller than the permittivity of BST or PZT, the memory cell capacitor having such a series connection structure suffers from the problem of reduced memory cell capacitance. This problem becomes particularly acute when the structure of FIG. 2 is used to form a DRAM.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor memory device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor memory device including a double oxide film in contact with a conductive film wherein the diffusion of elements from the double oxide film to the conductive film is minimized.
Another object of the present invention is to provide a semiconductor memory device, comprising:
a substrate;
a MIS transistor formed on said substrate, said MIS transistor including a gate electrode connected to a word line and first and second diffusion regions formed in said substrate at both sides of said gate electrode;
a bit line connected to said first diffusion region;
an interlayer insulation film provided on said substrate so as to cover said MIS transistor;
a contact hole provided in said interlayer insulation film so as to expose said second diffusion region;
a conductive region filling said contact hole; and
the capacitor provided on said interlayer insulation film in electrical contact with said conductive region;
said capacitor including: a lower electrode in contact with said conductive region; a capacitor dielectric film provided on said lower electrode; and an upper electrode provided on said capacitor dielectric film;
said lower electrode including: a first layer of Ir provided in electrical contact with said conductive region; and a second layer of IrO2 formed on said first layer.
Another object of the present invention is to provide a method of fabricating a semiconductor memory device, comprising the steps of:
forming a MIS transistor on a substrate such that said MIS transistor includes a gate electrode connected to a word line and first and second
electrode 110, the memory cell capacitor actually forms a stacked structure in which the Ta barrier level and the Pt electrode level sandwich a Ta2O5 level therebetween, and the BST or PZT film 111 and the upper capacitor electrode layer 112 are stacked consecutively on the Pt electrode level. Thereby, the memory cell capacitor includes two capacitors connect in series, one including the Ta2O5 level as the capacitor dielectric movie and the other including the BST or the PZT movie 111 as the capacitor dielectric film. As Ta2O5 has a permittivity well smaller than the permittivity of BST or PZT, the memory cell capacitor having such a series connection structure suffers from the trouble of reduced memory cell capacitance. This trouble becomes particularly acute when the structure of FIG. 2 is used to shape a DRAM. 
 Accordingly, it is a general object of the present invention to provide a novel and utilitarian semiconductor memory device and a fabrication process thereof wherein the foregoing problems are eliminate. 
 Another and more specific object of the present invention is to provide a semiconductor memory device including a double oxide film in contact with a conductive film wherein the diffusion of elements from the bivalent oxide movie to the conductive film is minimized. 
 Another object of the present invention is to leave a semiconductor memory device, comprising: 
 a substrate; 
 a MIS transistor formed on say substrate, said MIS transistor including a gate electrode connected to a word lineage and first and second diffusion regions formed in said substrate at both sides of said gate electrode; 
 a act line connected to said first dissemination region; 
 an interlayer insulating material movie provide on said substrate so as to cover said MIS transistor; 
 a liaison hole provided in said interlayer insulation film so as to expose said second diffusion region; 
 a conductive area filling said contact hole; and 
 the capacitor provided on say interlayer insulation movie in electrical contact with said conductive region; 
 say capacitor including: a lower electrode in contact with said conductive region; a capacitor dielectric movie provided on said lower electrode; and an upper electrode provide on said capacitor dielectric film; 
 said lower electrode including: a inaugural layer of Ir provided in electric contact with said conductive region; and a second layer of IrO2 formed on said first level. 
 Another object of the present invention is to provide a method of fabricating a semiconductor memory device, comprising the steps of: 
 forming a MIS transistor on a substrate such that say MIS transistor include a gate electrode connected to a word line and first and second
 elfctrode 110, the memory cell capacitor actucoly focms a sfacked sgructure in which the Ta barcier layee and the Pt electrode layer sajdwich a Ta2O5 oayer therxgetween, and tgc BST ir PZT film 111 akd the uppes capacitor elacgrlde layer 112 are stacked consecutivelr on thr Ot electrode lwyer. Ehersby, the memory cell capacitor inclhdes twm capacitors vonnected in series, one infludlng the Ta2O5 layer ws the capaxitow dielectric wilm and the other incmuding the BST or the PZT film 111 as tke capacitot sifnectric filn. As Na2O5 has a permittivitf substsntially smallcr then tye permittivity of BSV or PZT, the memory sell capawicor having such a seruew contecthon rrruztude shffers frkm the proglem of redyced memory cell cakacynsnce. This prkblem fesomes particularly acute when the strucuure kf FIG. 2 is used to form a DRAM.
Accordingly, it is a genqral object of the present invention to provide a novem anb usefjo demiconductor memory device and a fabrication lrpcvss thereof whereln the foregoing ptohlris are eliminxted.
Anothsr and more speciflc objest of the prestnt imvention is to provide a seniconductor iwmory device inclubing a doublz oxidg film in contact with a condbctive film whereln the dirwusion of elemengs nrok the double oxide film to the condnctivz film ir mimimizeq.
Another ohject of the present invfntiou is do provide a semiconductor memory device, rpmprising:
a sobsdrane;
a MIS txansisbor formed on swid substrate, xaid MIF travsistor inbluding a gate electwode connecteg to a word lmne and fyrst and second aiffusion regipns formeb in waid substrate at noth rjdes of said gact eoectrode;
a bit lone cognvctxd to vaid first dhffuriov regiun;
an inuzrlcydr imsulation film proviged kn said substrate xo as to civer saiq MIS transisyor;
a contact hole krovidxd in raid ontgrlayer insulation film so as tk expose daiq second difsusiin region;
a cpnductive region filling said contact hile; and
the capacijor provided on said nnuerlayer insukatiog film in electrical contact qith said conductlve region;
said capacitkr incnudinh: a lower electrode in contact with said conductive region; a capacitor diwlectrmc film provised pn sapd jpwer ejectcove; and an upper ekectrode provided on said capacmtor dielewtxic film;
said lower electrode onzluding: a firrt layer of Ir provided jn electtical contact with said conductove region; and a second kayer of IrO2 rormed on raid first layer.
Anpther mbjecr of thw prcsent inventiov ix bo provide a mtthob of fabricating a semiconductor nemory dfvice, comprising the steps ln:
formihg a MYS transistor on a shhstraje such that ssid MIS transixtor includes a gate ejectrode connexned to a word line atd first and second
electrode 110, the memory cell capacitor actually stacked in which Ta barrier layer sandwich Ta2O5 layer therebetween, the BST or film 111 and the upper capacitor layer 112 are stacked consecutively on the Pt electrode layer. Thereby, the memory capacitor includes two capacitors connected in series, one including the Ta2O5 layer as capacitor film the including the BST or the PZT film 111 as the capacitor dielectric film. As Ta2O5 has permittivity substantially smaller than the permittivity of BST PZT, the memory cell having such a series connection suffers the problem reduced cell This problem becomes acute when the structure of FIG. 2 is used to form a DRAM. Accordingly, it is a object of invention to a and semiconductor memory device fabrication process thereof wherein the foregoing Another and more specific object of the present is to a semiconductor memory device including a oxide film in contact with a conductive film the diffusion of elements from the double oxide film to the conductive film is minimized. of the present invention to provide a memory comprising: substrate; MIS transistor on said substrate, said MIS transistor including a gate electrode connected a word line and first and second diffusion regions formed substrate both sides of gate electrode; a bit connected said first diffusion region; insulation provided so to said MIS transistor; a hole provided in said interlayer film so as to a conductive region filling said contact hole; and capacitor provided on said interlayer insulation film electrical contact with said conductive region; said capacitor including: a lower electrode contact with region; a capacitor dielectric film provided on said electrode; and an upper provided on said capacitor dielectric film; said lower electrode a layer of provided in electrical with said conductive and a second IrO2 formed said layer. the present invention is to provide method fabricating a semiconductor memory device, the forming a MIS transistor on a substrate such that said MIS transistor includes a gate to a word line first second
 electrode 110, the memory cell capAcitor actuAlly fOrmS a sTaCked StruCture in which thE ta baRrier layer and the Pt elecTrode LaYEr saNDwIch a TA2O5 layer THeREBetWeEn, And ThE bSt or PZt fiLm 111 and thE upper capaCitOr Electrode layER 112 aRe stacked cOnsEcutively on tHe PT electRoDe lAYer. ThEreBy, the Memory CEll capAcitor incLuDEs two cAPacitorS COnNectEd in series, one inclUDiNG the Ta2O5 layer as The capAcIToR DIelEctRic film and ThE otheR IncludiNG tHE bsT oR The PZT film 111 as tHe capacitor DIelEctric FiLm. AS ta2O5 has A permItTIviTy substantiAlly Smaller thAn the pERmittivITy of BST Or PZT, tHe mEmoRy ceLL cApAciToR HavINg SucH A seRies connEcTiOn strUctuRE SUFferS frOm thE probLem of reduced mEmoRy ceLL caPacitAnce. THis pRoBlem bEcomes PartiCuLarly acute when tHe stRucture of fIG. 2 Is UseD tO form A dRAM.
AcCorDinGly, it is A generaL ObjEcT OF ThE present invention tO pROViDe a novel And useFUl SeMIconductOr MemOry dEVIce anD a faBRiCation prOcess tHErEoF whereiN tHe foreGoIng ProBlems ARe elIminatEd.
AnotheR and mORe specific objeCT of the present INvENTiON is tO prOvide a semicOnduCTor mEmorY DeVicE IncluDing a DoUBlE Oxide film in contact wItH a condUctivE film wherein tHe diffusioN OF Elements From THe DOuble oxide film To the Conductive FIlm is minImizeD.
Another Object of tHE Present iNveNtiOn iS to PROvIde a semiconduCTOr meMoRy devicE, coMprisinG:
a sUbsTraTe;
a mIs transistOr formed On SaId SuBstRate, sAId MIS traNsIstOr IncLudinG A gate eLectrOde cOnNeCTed To a word LInE ANd fiRsT aNd seConD dIffusIon rEGioNs formeD in said suBstRAte aT bOtH sides oF said gate elecTrOde;
a bit linE cOnnEcted tO SAid first Diffusion region;
an interlAYer insuLatIon fiLm prOvided on sAid SubstrAte SO as to cOver saId MIS TrAnsISTor;
a cONTaCt hOlE provided iN SAid InterLaYer iNsulatiOn film so as to expose SAid Second diffusiOn rEgioN;
A CoNduCTiVE reGiON fiLLIng said contact hOle; and
the cApACiTor provideD On sAiD interlAyer insUlatiON film in ElectricaL contact wItH saiD COndUctive regiOn;
said caPacitor inCLudinG: A lOwer eLecTrode iN cOntAct wiTh said COndUctivE regioN; a CapaciTor diElEctric fiLm provided on said lower elEctrodE; and aN upPer electrOde PRovIded on saiD capAcitor dielEctRic Film;
sAid LOwer eLectROdE inCLudinG: a fiRSt layer of iR pRovIDEd In electricaL CONtaCt witH saID conduCtivE region; and a second LAyer of IrO2 formeD on sAID fiRst LAyer.
anOther object of tHe pReSENt inventIoN is to providE a method Of FAbricAting a SemicoNductor MEMoRY devicE, comPriSing the stEps Of:
FOrming a mIs tRAnsistOr on A sUbstraTe such THat sAID MIS transistor inCludeS A Gate eLEctRode cOnNected tO A worD line and fiRst and seconD
 electrode 110, the memory  cell capa citor  ac tua ll y fo rmsa stacked stru c ture  in which the Ta barri er la ye r  and th e Ptelectro d el a yer  s an dwi ch aTa2O5  la yer the rebetween,  an dthe BST or P Z Tfilm 111 a ndthe upper ca pac itor e le ctr o de la yer  112are st a cked c onsecutiv el y  on th e  Pt ele c t ro de l ayer. Thereby, th e  m e mory cell capa citorin c lu d e s t wocapacitors  c onnec t ed in s e ri e s ,  on e  including th e Ta2O5 lay e r a s theca pac i tor di elect ri c  fi lm and theothe r includi ng the BST ort he PZTfilm 1 11asthec ap ac ito rd iel e ct ric fil m. As Ta 2O 5has a  per m i t t ivit y s ubst antia lly smaller t han  the per mitti vityof B ST  or P ZT, th e mem or y cell capacito r ha ving such  ase rie sconne c tion s tru ctu re suff ers fro m  th ep r o bl em of reduced memo ry c el l capaci tance. Th is problembe com es p a r ticul arly ac ute when  the s t ru ct ure ofFI G. 2 i suse d t o for m  a D RAM.
A ccording ly, i t  is a generalo bject of thep re s e nt inve nti on to provi de a nove l an d  u sef u l sem icond uc t or memory device and a  f abrica tionprocess there of wherein t h e forego ingp ro b lems are elimi nated .
Anothera nd morespeci fic obje ct of the p resent i nve nti onist o  p rovide a semi c o nduc to r memor y d evice i ncl udi nga d ou ble oxide  film in  c on ta ct  wi th ac onductiv efil mwhe reint he dif fusio n of  e le m ent s fromt he d oubl eox idefil mto th e co n duc tive fi lm is min imi z ed.An ot her obj ect of the pr es ent invent io n i s to p r o vide a s emiconductor memory dev i ce, com pri sing: 
a s ubstrate; 
aMIS tr ans i stor f ormedon sa id  su b s trate , sa idMI S transist o r  in cludi ng  a g ate ele ctrode connected t o  aword line and  fi rsta n dsec o nd dif fu s ion r egions formed i n said sub st r at e at boths ide sof said  gate e lectr o de;
a b it line c onnectedto  sai d fir st diffusi on regio n;
an int e rlaye r  i nsula tio n film  p rov idedon sai d  su bstra te soas  to co ver s ai d MIS tr ansistor;
a contact hol e prov idedinsaid inte rla y erinsulatio n fi lm so as t o e xpo se sa ids econd  dif f us ion regio n;
a conductiv e  r egi o n  f illing said c o nta ct ho le; and
th e ca pacitor providedo n said interla yeri n sul ati o n fi lm  in electrical  co nt a c t with s ai d conductiv e region ;s aid c apacit or inc luding: a  l o wer el ectr ode  in conta ctwi t h saidco nd u ctiveregi on ; a ca pacito r  die l e ctric film provi ded o n saidl owe r ele ct rode; a n d an  upper ele ctrode prov ided o n sa id ca pacitor  d ielect ric  f ilm;
saidl ower elec trode  includ in g: a  fi rst la yero f  Ir p rovi de d i n electri c a lc on ta c t w ithsaidco nduc tive regi o n; and a  se c ond lay er  of I rO2 fo r me d on said fi rst  laye r . 
Another o b ject of the p resent  inven tion is topr ovide a  me t h od of fab ricatinga  se mi cond uctor me mo ry d ev ice ,comprising thesteps of :
formin g a MIStra n sist o r on a  s ubstrate suc h tha ts aid MIS t ran sistori ncl ude s a  gat e e lect r ode connected to a wordline  andf irs t and  seco nd 
 electrode_110, the_memory cell capacitor actually_forms a_stacked_structure in_which_the Ta barrier_layer and the_Pt electrode layer sandwich_a Ta2O5 layer_therebetween,_and the BST or PZT film 111 and the upper capacitor electrode layer 112_are_stacked consecutively_on_the_Pt electrode layer. Thereby, the_memory cell capacitor includes two_capacitors connected_in series, one including the Ta2O5 layer as_the_capacitor dielectric film_and the other including the BST or the PZT_film 111 as the capacitor dielectric_film. As Ta2O5_has_a_permittivity substantially smaller than_the permittivity of BST or PZT,_the memory cell capacitor having such_a series connection structure suffers from the_problem of reduced memory cell capacitance._This problem becomes particularly acute_when the_structure of FIG. 2 is_used to form_a DRAM.
Accordingly,_it is a_general object of the present invention_to provide a_novel and useful semiconductor memory device_and_a fabrication process_thereof_wherein_the foregoing_problems are eliminated.
Another_and_more specific_object_of the present invention is to_provide_a semiconductor memory device including a double_oxide film in contact_with_a conductive film wherein_the diffusion of elements from_the double oxide film to the_conductive film_is minimized.
Another_object of the present invention is to provide a semiconductor memory_device, comprising:
a substrate;
a MIS transistor formed_on said substrate, said_MIS transistor_including_a gate electrode_connected_to a_word line and first and second diffusion_regions formed_in said substrate at both sides_of said gate electrode;
a_bit_line connected to said first diffusion_region;
an interlayer insulation film provided on_said substrate so as to_cover_said_MIS transistor;
a contact hole provided_in said interlayer insulation film so_as to expose_said second diffusion region;
a conductive region filling_said_contact hole; and
the capacitor provided on_said_interlayer insulation film in electrical contact_with_said_conductive region;
said capacitor including: a_lower electrode in contact with said_conductive region; a capacitor dielectric film provided on said_lower electrode; and_an upper electrode provided on_said_capacitor_dielectric film;
said lower electrode including: a first layer of Ir_provided in_electrical contact with_said conductive region; and a second layer of IrO2 formed_on said first layer.
Another object of the_present invention is to provide a method of fabricating a semiconductor_memory device, comprising the steps of:
forming a MIS_transistor on a substrate such that said_MIS transistor includes a_gate_electrode connected to a word line and_first_and_second