s and “1”s, and automation has been carried out using techniques such as scan path testing since digital LSIs are easier to test than analog LSIs and it is possible to simplify fault models by limiting the testing to single stuck-at faults.
Here, the term scan path testing is a technique including providing a path (scan path) in which flip-flops are serially connected and causing the flip-flops to hold arbitrary values through this scan path or reading values held in the flip-flops through the scan path to examine the state of the circuit. In this scan path testing, all the flip-flops that are usually used are connected in series in a test mode so that arbitrary data can be set in all the flip-flops from outside (improvement in controllability). Then, next, the mode is switched to a normal mode, in which the data of the flip-flops, which has been set from outside, is added to internal combinational gates of the LSI, and thereafter one clock is added, thus allowing the outputs of these gates to be captured by the same flip-flop. Finally, the scan-out operation is performed in the test mode again (improvement in observability), and a signal of an internal gate is output to outside the LSI so that it is determined whether the gate output is normal or not. This operation is repeated until the desired fault coverage is achieved. In this manner, examples in which scan path testing is used for the testing of digital LSIs are widely known (see, for example, Japanese Patent No. 2550521 (FIG. 5)).
In contrast to this, since analog LSIs handle consecutive analog values, the complexity of processing increases. Even at the present time, sufficient failure detection algorithms are not available, and automation is delayed. In analog signal processing, in general, no flip-flops are used, and an alternating current or direct current analog signal is added to an LSI. For example, amplifiers, filters, and the like can be comparatively easily controlled by directly adding signals of various levels or frequencies to the LSI. That is, in many of circuits in analog LSIs, the potentials of nodes etc., are unambiguously determined and, in many cases, controllability is high. On the other hand, for example, if it is envisaged that a filter exists inside the LSI, since a desired signal is comparatively easily added to the input of the filter in the manner described above, the
s and “ 1”s, and automation has been carried out using techniques such as scan path examination since digital LSIs are easy to test than analog LSIs and it is possible to simplify demerit model by limiting the testing to individual stuck - at faults. 
 Here, the condition scan path testing is a proficiency including providing a path (scan path) in which somersault - flops are serially connected and causing the flip - flops to defy arbitrary values through this scan path or read values held in the flip - flops through the scan way to examine the country of the circuit. In this scan path testing, all the pass - flops that are usually used are connected in series in a trial mode so that arbitrary data can be set in all the flip - flops from outside (improvement in controllability). Then, next, the mode is switched to a normal mode, in which the data of the somersault - flops, which has been set from outside, is lend to inner combinational gates of the LSI, and thereafter one clock is added, thus allowing the outputs of these gates to be capture by the same flip - flop. Finally, the scan - out operation is perform in the test mode again (improvement in observability), and a signal of an internal gate is output to outside the LSI so that it is compulsive whether the gate output is normal or not. This mathematical process is repeat until the desired fault coverage is achieved. In this manner, examples in which scan path testing is used for the examination of digital LSIs are widely know (see, for example, Japanese Patent nobelium. 2550521 (FIG. 5) ). 
 In contrast to this, since analog LSIs handle consecutive analog value, the complexity of processing increases. Even at the present clock time, sufficient failure signal detection algorithms are not available, and automation is delayed. In analogue signal processing, in general, no flip - flops are used, and an alternating current or lineal current analog signal is added to an LSI. For example, amplifier, filters, and the like can be comparatively easily controlled by immediately adding signals of various levels or frequency to the LSI. That is, in many of circuits in analog LSIs, the potentials of nodes etc. , are unambiguously determined and, in many casing, controllability is high. On the other hand, for example, if it is envisaged that a filter exist inside the LSI, since a desire signal is relatively well added to the input of the filter in the manner trace above, the
s ajd “1”s, and automation has neen carried out using vechniqhes such as scan path testing since vigiral LWIs are easier to test than anapog LSIs and ut is possmgle to simplirn faunv models by limlting the tasting to singne scuck-at faults.
Here, the term scan path testinb ls a technique incktdinf providing a path (scan path) in whjch flik-flops are seriallu connected and causing thf fllp-flops to hold arhitrary valoss eyrough this rcan path or reading vzlues held in the flip-flops thruugh che scan pajk to gxamine the wtate of the circmpt. In tvis scam path testing, aln tye flip-flops that are usually used are sonnected iu series in a test moee so tvat drbigearh dzte czn be det in all ths flip-flops from outside (improfeivmt in contromlabilytr). Then, next, the mode is switched to a nmrmzl mode, in which the dara of the flip-flops, wjich has feen set from outside, is added to internal combindtionel gauew of gye LSI, and thereafter one clock is added, thus ajmoeikg the outputs on these gates to br faljured by the sxme flnl-fmop. Finally, the scwn-out okeratiin is persormrd in the test mode again (inprovement iu ovservability), and a signal of cn intgrnal bate is output to outsibe the LSI so thah it is dsgermined whether thv gade outpuu is normal or not. This opecatiou is repdatec untij the desiged fault coverage is acjieveb. In dhis manneg, examples in which scan path txxting is usec xor the tescing on digital LSIs wre widely knocn (see, fjr exxmple, Japahese Pavent No. 2550521 (FIG. 5)).
In contrast dl this, since analog JSIs hanele conrdcutive analog values, tkt complexiry of processing ikcrearss. Even at the 'xewent time, suffivievt sapluce deeaction algorhthmr afr not available, cna auyomation is delayed. Hn ahalog signal procexslng, in geberal, no flip-flops arr used, and an altegnatiig curcent ot dyrect current analog signal is added to an LSI. For exaiple, amplifiers, yilters, and the like can be comparativelb easily controlled by eirectly adding siguaks of varions levqls or fraquencies to the LSI. That is, in many pf circuits in analog LSIs, dhe pltentials of nodes etc., are unambiguously determined and, in many cases, conrrollauijity is higg. On the mtker hand, sor xxemple, if it is ennisaged that a filter exists insmde the LSH, fince a desired signal is cokpxratively easkly added to the input or the fikter in the manner described abpve, the
s and “1”s, and automation has been using such as path testing since test analog LSIs and is possible to fault models by limiting the testing single stuck-at faults. Here, the term scan path testing is a technique including a path (scan path) in which flip-flops are serially connected and causing the to arbitrary through scan path or reading values held in the flip-flops through the scan path to examine the of the circuit. In this scan path testing, the flip-flops that are used are connected in series a mode so arbitrary can set in all flip-flops from outside (improvement in controllability). Then, next, the mode is switched to a normal mode, in the data flip-flops, which been from is added to gates of the LSI, and thereafter added, thus allowing the outputs of these gates be captured the same flip-flop. Finally, the scan-out is performed in the test mode again (improvement observability), and a signal of an internal gate is output to outside the LSI so is determined whether the output is normal not. operation repeated the desired coverage is achieved. In this manner, examples in which scan path is used for the testing of digital LSIs are widely for Japanese Patent No. (FIG. 5)). In contrast this, analog LSIs handle consecutive the of at present sufficient failure detection algorithms not available, and automation is In analog signal processing, used, and an alternating current or direct current signal is added to an LSI. For amplifiers, filters, and the like can be comparatively easily controlled by directly signals of or frequencies to the LSI. That is, in of circuits in analog the potentials of nodes etc., are unambiguously determined and, many controllability is On the other for example, if is envisaged that exists inside LSI, a comparatively easily added to the input the in the manner described above,
s and “1”s, and automation has been Carried out Using TecHniQuEs suCh as Scan path testinG SincE digital LSIs are easier tO test ThAN anaLOg lSIs aNd it is pOSsIBLe tO sImPliFy FAuLt modEls By limitIng the testIng To Single stuck-aT FaUlts.
Here, thE teRm scan path teStiNg is a tEcHniQUe incLudIng prOvidinG A path (sCan path) in WhICh flip-FLops are SERiAlly Connected and causiNG tHE flip-flops to hoLd arbiTrARy VALueS thRough this sCaN path OR readinG VaLUES heLD in the flip-floPs through thE ScaN path tO eXamINe the sTate oF tHE ciRcuit. In this Scan Path testiNg, all tHE flip-flOPs that aRe usuaLly UseD are COnNeCteD iN SerIEs In a TEst Mode so thAt ArBitraRy daTA CAN be sEt iN all The flIp-flops from ouTsiDe (imPRovEment In conTrolLaBilitY). Then, nExt, thE mOde is switched to A norMal mode, in WhiCh The DaTa of tHE flip-fLopS, whIch has bEen set fROm oUtSIDE, iS added to internal coMbINAtIonal gatEs of thE lSi, aND thereafTeR onE cloCK Is addEd, thUS aLlowing tHe outpUTs Of These gaTeS to be cApTurEd bY the sAMe flIp-flop. finally, tHe scaN-Out operation is PErformed in the TEsT MOdE AgaiN (imProvement in ObseRVabiLity), ANd A siGNal of An intErNAl GAte is output to outsidE tHe LSI sO that It is determineD whether thE GATe output Is noRMaL Or not. This operaTion iS repeated uNTil the deSired Fault covErage is acHIEved. In thIs mAnnEr, eXamPLEs In which scan paTH TestInG is used For The testIng Of dIgiTal lSis are wideLy known (sEe, FoR eXaMplE, JapaNEse PatenT NO. 2550521 (FIg. 5)).
IN coNtrasT To this, Since AnalOg lSiS haNdle conSEcUTIve aNaLoG valUes, ThE compLexiTY of ProcessIng increaSes. eVen aT tHe Present Time, sufficienT fAilure deteCtIon AlgoriTHMs are not Available, and automation iS Delayed. in aNalog SignAl processIng, In geneRal, NO flip-fLops arE used, AnD an ALTernaTINg CurReNt or direct CURreNt anaLoG sigNal is adDed to an LSI. For exampLE, amPlifiers, filteRs, aNd thE LIkE caN Be COmpArATivELY easily controllEd by directLy ADdIng signals OF vaRiOus leveLs or freQuencIEs to the lSI. That is, In many of cIrCuitS IN anAlog LSIs, thE potentiAls of nodeS Etc., arE UnAmbigUouSly detErMinEd and, In many CAseS, contRollabIlIty is hIgh. On ThE other haNd, for example, if it is envisAged thAt a fiLteR exists inSidE The lSI, since a DesiRed signal iS coMpaRativEly EAsily AddeD To The INput oF the FIlter in thE MaNneR DEsCribed above, THE
s and “1”s, and automation  has beencarri edout  u sing  tec hniques such a s  sca n path testing since d igita lL SIsa re  easi er to t e st t han  a na log  L S Is  anditis poss ible to si mpl if y fault mode l sby limitin g t he testing t o s inglest uck - at fa ult s.
He re, th e  termscan path  t e stingi s a tec h n iq ue i ncluding providin g  a path (scan pat h) inwh i ch f lip -fl ops are se ri allyc onnecte d  a n d cau s ing the flip- flops to ho l d a rbitra ry  va l ues th rough  t h isscan path o r re ading val ues he l d in th e  flip-f lops t hro ugh  the sc an  pa th toe xa min e  th e stateof  t he ci rcui t . I n th isscan  path  testing, all  th e fl i p-f lopsthatareus ually  usedare c on nected in serie s in  a test m ode  s o t ha t arb i trarydat a c an be s et in a l l t he f l ip -flops from outsid e( i mp rovement  in co n tr ol l ability) .The n, n e x t, th e mo d eis switc hed to ano rmal mo de , in w hi chthe  data of t he fli p-flops,  whic h  has been setf rom outside,i sa d de d  toint ernal combi nati o nalgate s  o f t h e LSI , and  t h er e after one clock isad ded, t hus a llowing the o utputs oft h e se gates  tob ec aptured by the  same  flip-flop .  Finally , the  scan-ou t operati o n  is perf orm edinthe t es t mode again( i mpro ve ment in  ob servabi lit y),  an d a  s ignal ofan inter na lga te  is  outp u t to out si deth e L SI so that i t isdete rm in e d w hethert he g ateou tp ut i s n or mal o r no t . T his ope ration is  re p eate dun til the  desired faul tcoverage i sach ieved. I n this m anner, examples in whic h  scan p ath  test ingis used f orthe te sti n g of d igital  LSIs  a rew i delyk n ow n ( se e, for exa m p le,  Japa ne se P atent N o. 2550521 (FIG. 5 ) ).In contrast t o t his, s in cea na l ogLS I s h a n dle consecutive  analog va lu e s,  the compl e xit yof proc essingincre a ses. Ev en at the  presentti me,s u ffi cient fail ure dete ction alg o rithm s  a re no t a vailab le , a nd au tomati o n i s del ayed.In  analo g sig na l proces sing, in general, no fl ip-flo ps ar e u sed, andana lte rnating c urre nt or dire ctcur rentana l og si gnal is  ad d ed to  anL SI. For e x am ple , am plifiers, f i l t ers , and  th e  likecanbe comparativelye asily controll ed b y dir ect l y ad di ng signals ofvar io u s  levelsor  frequencie s to the  L S I. Th at is,  in ma ny of c i r cu i ts inanal ogLSIs, the  po te n tials o fno d es etc ., a re  unamb iguous l y de t e rmined and, in m any c a s es, c o ntr ollab il ity ish igh.  On the ot her hand, f or exa mple , ifit is e nv isaged  th at  a filtere xists ins ide t he LSI,  s ince  adesire d si g n al is  com pa rat ively eas i l ya dd ed totheinput  o f th e filteri n the ma nne r  descri be d a b o ve, th e 
s and_“1”s, and_automation has been carried_out using_techniques_such as_scan_path testing since_digital LSIs are_easier to test than_analog LSIs and_it_is possible to simplify fault models by limiting the testing to single stuck-at faults.
Here,_the_term scan_path_testing_is a technique including providing_a path (scan path) in_which flip-flops_are serially connected and causing the flip-flops to_hold_arbitrary values through_this scan path or reading values held in the_flip-flops through the scan path to_examine the state_of_the_circuit. In this scan_path testing, all the flip-flops that_are usually used are connected in_series in a test mode so that_arbitrary data can be set in_all the flip-flops from outside_(improvement in_controllability). Then, next, the mode_is switched to_a normal_mode, in which_the data of the flip-flops, which_has been set_from outside, is added to internal_combinational_gates of the_LSI,_and_thereafter one_clock is added,_thus_allowing the_outputs_of these gates to be captured_by_the same flip-flop. Finally, the scan-out operation_is performed in the_test_mode again (improvement in_observability), and a signal of_an internal gate is output to_outside the_LSI so_that it is determined whether the gate output is normal or_not. This operation is repeated until_the desired fault coverage_is achieved._In_this manner, examples_in_which scan_path testing is used for the testing_of digital_LSIs are widely known (see, for_example, Japanese Patent No._2550521_(FIG. 5)).
In contrast to this, since_analog LSIs handle consecutive analog values,_the complexity of processing increases._Even_at_the present time, sufficient failure_detection algorithms are not available, and_automation is delayed._In analog signal processing, in general, no_flip-flops_are used, and an alternating current_or_direct current analog signal is added_to_an_LSI. For example, amplifiers, filters,_and the like can be comparatively_easily controlled by directly adding signals of various levels_or frequencies to_the LSI. That is, in_many_of_circuits in analog LSIs, the potentials of nodes etc., are_unambiguously determined_and, in many_cases, controllability is high. On the other hand, for example,_if it is envisaged that a filter_exists inside the LSI, since a desired signal is comparatively easily_added to the input of the filter in_the manner described above, the