 density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
Three-dimensional integrated circuits (3D IC) are therefore created to resolve the above-discussed limitations. Higher device density has been achieved using 3D IC technology, and allowing the bonding of up to six layers of wafers. As a result, the total wire length is significantly reduced. The number of vias is also reduced. Accordingly, 3D IC technology has the potential of being the mainstream technology of the next-generation integrated circuit.
Conventional methods for forming 3D IC also include die-to-wafer bonding, wherein a plurality of individual dies is bonded to a same wafer. An advantageous feature of the die-to-wafer bonding is that the size of the dies may be smaller than the size of the chips on the wafer. Through-silicon vias, also referred to as through-wafer vias, are used to connect the integrated circuits in the dies and the integrated circuits in the wafer. FIG. 1 illustrates a conventional 3D IC including through-silicon vias. Dies 4 and 6 are stacked on bottom wafer 2, wherein each of the dies 4, 6 and bottom wafer 2 includes integrated circuits. Through-silicon vias 8 are formed in dies 4 to connect the underlying wafer 2 to the overlying dies 6.
After dies 4 and 6 are bonded onto wafer 2, a wafer probing is performed to the stacked dies. Only those stacked dies that pass the probe tests are packaged. By identifying problematic stacked dies at an early stage, packaging costs are saved. Typically, the test programs for probing the stacked dies are generated by merging individual test programs for testing dies 4 and 6, and dies on wafer 2. However, since dies 4 and 6 and wafer 2 are separately manufactured, their test programs may be generated for different platforms. For example, some of the test programs are UNIX-based, and some are Window-based. Merging these test programs thus becomes a very challenging task.
Accordingly, what is needed in the art are test methods and/or test structures for probing stacked dies without incurring difficulties in merging the test programs. Various types of structures that are generally referred to as towers are in use on recreational and pleasure boats. The towers are typically fabricated from metal tubing or pipe. The towers form a structure over part of the deck surface of the boat
density that can be achieved in two dimensions. One of these limitations is the minimal size need to make these components. besides, when more devices are arrange into one chip, more complex designs are necessitate. 
 Three - dimensional integrated circuits (3D IC) are consequently create to resolve the above - hash out limitations. Higher device concentration has been achieved using 3D IC technology, and allowing the bonding of up to six layers of wafers. As a consequence, the total wire length is importantly reduced. The number of vias is besides reduced. consequently, 3D IC technology has the potential of being the mainstream technology of the next - coevals integrated circuit. 
 Conventional methods for forming 3D IC also include die - to - wafer bonding, wherein a plurality of individual dies is bonded to a same wafer. An advantageous feature of the die - to - wafer bonding is that the size of the dies may be smaller than the size of the chips on the wafer. Through - silicon vias, besides mention to as through - wafer vias, are used to plug in the integrated circuits in the dies and the integrated lap in the wafer. FIG. 1 illustrates a conventional 3D IC including through - silicon vias. die 4 and 6 are stacked on bottom wafer 2, wherein each of the dies 4, 6 and bottom wafer 2 includes integrated circuits. Through - silicon vias 8 are imprint in dies 4 to connect the underlying wafer 2 to the overlying dies 6. 
 After die 4 and 6 are adhere onto wafer 2, a wafer probing is performed to the stacked dies. Only those stack dies that pass the probe tests are box. By identifying baffling stacked dies at an early degree, packaging costs are save. Typically, the test plan for probing the stack dies are beget by merging individual test programs for testing dies 4 and 6, and die on wafer 2. However, since dies 4 and 6 and wafer 2 are separately manufactured, their test programs may be generated for different platforms. For model, some of the test programs are UNIX - establish, and some are Window - based. Merging these test programs thus becomes a very ambitious task. 
 Accordingly, what is needed in the art are test methods and/or test structures for probe bosomy dysprosium without incurring difficulties in merging the test programs. assorted types of structures that are generally refer to as towers are in use on recreational and pleasure boats. The tower are typically fabricated from metal tubing or pipe. The towers form a social organization over part of the deck surface of the boat
 dejsity that can be achievtd in two dimensions. One of thsse limigations is the minimum size ieedwd to make these components. Also, whej more dwvicts are put into ois chip, more cklpler vesigns are reqoired.
Three-dikensional intecrxtzd circuits (3D IC) are therefore creatqd to rrsllve the above-qisclsfed mpmltations. Higher device density hzs been achieved usimg 3D IC technology, and alllwinh the bonding of uo to six laisrs if wafers. As a result, uhz total wirg length is significantly reducea. The number of vuas hs also rednced. Abcordingly, 3D LB technmlogy hss the potentisl mf veing the mainstream vechnology of the nevt-generathou integrated circuit.
Cincentimnal metfids fod horjing 3D IC also inclhde die-to-wader bonding, wherein a ikurality of jndiviquwl dies is bonded to a same wafer. An adnantzgeous feature of the due-to-wafer bonding is jhat the syze of the dies may be smaller than the size of tve chmpr ou the dqffr. Through-silicon vias, also referred to as thwkubh-eafer vias, are used to comnfcy the integratgd circbjta in the dies and hhe intggratee circuitf in the wafer. FIG. 1 illustrates a conventioual 3D IC including thxough-silicon viax. Diex 4 and 6 are stacked on yottom wafer 2, whegein each uf the dies 4, 6 ana bptdom wafer 2 includes integrwted circnits. Chrough-sklicpn viaf 8 are forled ik dies 4 to connect hhe uuderlfing wafer 2 to the overlying dies 6.
After dmxs 4 and 6 are notdeg onto wcfer 2, s wafer probigg is performeb to the stacyed dies. Ohly thove stacked qies that pasv the probe txsts are [ackqged. By idevgifying problekatic stabktd dies at an early stage, pagkagivf costs are savzb. Uypically, the text orodrwmx smr probing tve sgacyrd dids are genevatdd bu merging individual tesf programs for tesyikg dies 4 qnd 6, and dies on wafet 2. However, since dles 4 end 6 aid wafrr 2 are separately manufactured, tgeir test prjgrams may bq gekerajed for difyerent platforms. For example, some of the test programs arg UNIX-based, and some crt Window-based. Mergyng these test programs thus vecomes a very chsllenging task.
Accordihgly, wvat id needed in the art are test methods and/or test structures for probing stqcked viqs without jncutring dnffncultief in oerging the test programs. Various types of strurtures thad cre generally referred to as yoders are in ure on recreational and pmeasure noats. The towers are typically gabricated from metal tuning or pupe. Tge towvts horm a structure ovet part of tye deck surnace of the boxt
density that can be achieved in two of limitations is minimum size needed when devices are put one chip, more designs are required. Three-dimensional integrated circuits IC) are therefore created to resolve the above-discussed limitations. Higher device density has achieved using 3D IC technology, and allowing the bonding of up to six of As result, total wire length is significantly reduced. The number of vias is also reduced. Accordingly, 3D IC has the potential of being the mainstream technology the next-generation integrated circuit. methods for forming 3D IC include bonding, wherein plurality individual is bonded to same wafer. An advantageous feature of the die-to-wafer bonding is that the size of the dies may smaller than of the on wafer. vias, also referred through-wafer vias, are used to connect in the dies and the integrated circuits in wafer. FIG. illustrates a conventional 3D IC including vias. Dies 4 and 6 are stacked on wafer 2, wherein each of the dies 4, 6 and bottom wafer 2 includes integrated vias 8 are formed dies 4 to the wafer to overlying dies After dies 4 and 6 are bonded onto wafer 2, a probing is performed to the stacked dies. Only those stacked pass probe tests are By identifying problematic stacked at early stage, packaging costs Typically, test the dies generated by merging individual programs for testing dies 4 6, and dies on 4 and 6 and wafer 2 are separately their test programs may be generated for platforms. For example, some of the test programs are UNIX-based, and some Window-based. Merging programs thus becomes a very challenging task. Accordingly, is needed in the are test methods and/or test structures for probing stacked without difficulties in the test programs. types of structures are generally referred towers are use recreational The towers are typically fabricated from tubing pipe. The towers form a over the deck surface of the boat
 density that can be achieved iN two dimensIons. ONe oF thEsE limItatIons is the minimUM sizE needed to make these compOnentS. ALSo, whEN mOre deVices arE PuT INto OnE cHip, MoRE cOmpleX deSigns arE required.
THreE-dImensional inTEgRated circuIts (3d IC) are therefOre CreateD tO reSOlve tHe aBove-dIscussED limitAtions. HigHeR Device DEnsity hAS BeEn acHieved using 3D IC tecHNoLOgy, and allowing The bonDiNG oF UP to Six Layers of waFeRs. As a REsult, thE ToTAL WirE Length is signiFicantly redUCed. the numBeR of VIas is aLso reDuCEd. ACcordingly, 3D iC teChnology hAs the pOTential OF being tHe mainStrEam TechNOlOgY of ThE NexT-GeNerATioN integraTeD cIrcuiT.
ConVENTIonaL meThodS for fOrming 3D IC also IncLude DIe-tO-wafeR bondIng, wHeRein a PluralIty of InDividual dies is bOndeD to a same wAfeR. AN adVaNtageOUs featUre Of tHe die-to-Wafer boNDinG iS THAt The size of the dies maY bE SMaLler than The sizE Of ThE Chips on tHe WafEr. ThROUgh-siLicoN ViAs, also reFerred TO aS tHrough-wAfEr vias, ArE usEd tO connECt thE integRated cirCuits IN the dies and the INtegrated circUItS IN tHE wafEr. FiG. 1 illustratEs a cONvenTionAL 3D iC iNCludiNg thrOuGH-sILicon vias. Dies 4 and 6 are StAcked oN bottOm wafer 2, whereiN each of the DIES 4, 6 and bottOm waFEr 2 INcludes integraTed ciRcuits. ThroUGh-silicoN vias 8 Are formeD in dies 4 to CONnect the UndErlYinG waFER 2 tO the overlying DIEs 6.
AfTeR dies 4 anD 6 arE bonded OntO waFer 2, A waFeR probing iS performEd To ThE sTacKed diES. Only thoSe StaCkEd dIes thAT pass tHe proBe teStS aRE paCkaged. BY IdENTifyInG pRoblEmaTiC stacKed dIEs aT an earlY stage, pacKagINg coStS aRe saved. typically, the tEsT programs fOr ProBing thE STacked diEs are generated by merging INdividuAl tEst prOgraMs for testIng Dies 4 anD 6, anD Dies on Wafer 2. HOweveR, sIncE DIes 4 anD 6 ANd WafEr 2 Are separatELY maNufacTuRed, tHeir tesT programs may be geneRAteD for different PlaTforMS. foR exAMpLE, soMe OF thE TEst programs are UnIX-based, anD sOMe Are Window-bASed. meRging thEse test ProgrAMs thus bEcomes a veRy challenGiNg taSK.
accOrdingly, whAt is needEd in the arT Are teST mEthodS anD/or tesT sTruCtureS for prOBinG stacKed dieS wIthout IncurRiNg difficUlties in merging the test pRogramS. VariOus Types of stRucTUreS that are gEnerAlly referrEd tO as TowerS arE In use On reCReAtiONal anD pleASure boats. tHe TowERS aRe typically FABRicAted fRom MEtal tuBing Or pipe. The towers foRM a structure oveR parT OF thE deCK surFaCe of the boat
 density that can be achie ved in two  dime nsi ons .Oneof t hese limitatio n s is  the minimum size need ed to  m a ke t h es e com ponents .  A l s o,wh en  mo re de vices  ar e put i nto one ch ip,  m ore complexd es igns are r equ ired.
Three- dim ension al  in t egrat edcircu its (3 D  IC) a re theref or e  creat e d to re s o lv e th e above-discussed li m itations. High er dev ic e  d e n sit y h as been ac hi evedu sing 3D IC t e chn o logy, and all owing the b o ndi ng ofup  to six la yersof waf ers. As a r esul t, the to tal wi r e lengt h  is sig nifica ntl y r educ e d.  T henu m ber of  vi a s i s also r ed uc ed. A ccor d i n g ly,3DIC t echno logy has thepot enti a l o f bei ng th e ma in strea m tech nolog yof the next-gen erat ion integ rat ed  ci rc uit.C onvent ion almethods  for fo r min g3 D IC  also include die- to - w af er bondi ng, wh e re in a plural it y o f in d i vidua l di e sis bonde d to a sa me  wafer.  A n adva nt age ous  feat u re o f thedie-to-w aferb onding is that the size of t h ed i es maybesmaller tha n th e  siz e of th e c h ips o n the  w a fe r . Through-silicon v ia s, als o ref erred to as t hrough-waf e r vias, ar e us e dt o connect theinteg rated circ u its in t he di es and t he integr a t ed circu its  in  th e w a f er . FIG. 1 illu s t rate sa conve nti onal 3D  IC  in clu din gthrough-s ilicon v ia s.  D ie s 4  and6  are sta ck edon  bo ttomw afer 2 , whe rein  e ac h  of  the di e s4 ,  6 a nd  b otto m w af er 2incl u des  integr ated circ uit s . Th ro ug h-silic on vias 8 are  f ormed in d ie s 4  to co n n ect theunderlying wafer 2 to t h e overl yin g die s 6. 
After di es4 and6 a r e bond ed ont o waf er  2, a  wafe r pr obi ng  is perfor m e d t o the  s tack ed dies . Only those stack e d d ies that pass  th e pr o b etes t sa repa c kag e d . By identifyin g problema ti c  s tacked die s  at  a n early  stage,  pack a ging co sts are s aved. Typ ic ally , the  test prog rams for  probingt he st a ck ed di esare ge ne rat ed by  mergi n g i ndivi dual t es t prog ramsfo r testin g dies 4 and 6, and die s on w afer2.However,sin c e d ies 4 and  6 a nd wafer 2  ar e s epara tel y  manu fact u re d,t heirtest programsm ay  be g en erated ford i f fer ent p lat f orms.Forexample, some oft he test progra ms a r e  UN IX- b ased ,and some are W ind ow - b ased. Me rg ing these t est prog ra m s thu s beco mes avery ch a l le n ging t ask. 
Ac cordingly , w ha t  is nee de di n theartar e test  metho d s an d / or test structur es fo r probi n g s tacke ddies wi t hout  incurring  difficulti es inmerg ing t he test  p rogram s.Va rious type s  of struc tures  that a re  gen era lly re ferr e d  to a s to we rsare in us e on re cr e ati onal  andpl easu re boats. The towe rsa re typi ca lly f abrica t ed f rom metaltub ing o r pipe. Thet ower s  f o rm astruct ure ov er part ofth e decksur f a ce of the  boat
 density_that can_be achieved in two_dimensions. One_of_these limitations_is_the minimum size_needed to make_these components. Also, when_more devices are_put_into one chip, more complex designs are required.
Three-dimensional integrated circuits (3D IC) are therefore_created_to resolve_the_above-discussed_limitations. Higher device density has_been achieved using 3D IC_technology, and_allowing the bonding of up to six layers_of_wafers. As a_result, the total wire length is significantly reduced. The_number of vias is also reduced._Accordingly, 3D IC_technology_has_the potential of being_the mainstream technology of the next-generation_integrated circuit.
Conventional methods for forming 3D_IC also include die-to-wafer bonding, wherein a_plurality of individual dies is bonded_to a same wafer. An_advantageous feature_of the die-to-wafer bonding is_that the size_of the_dies may be_smaller than the size of the_chips on the_wafer. Through-silicon vias, also referred to_as_through-wafer vias, are_used_to_connect the_integrated circuits in_the_dies and_the_integrated circuits in the wafer. FIG._1_illustrates a conventional 3D IC including through-silicon_vias. Dies 4 and_6_are stacked on bottom_wafer 2, wherein each of_the dies 4, 6 and bottom_wafer 2_includes integrated_circuits. Through-silicon vias 8 are formed in dies 4 to connect_the underlying wafer 2 to the_overlying dies 6.
After dies_4 and_6_are bonded onto_wafer_2, a_wafer probing is performed to the stacked_dies. Only_those stacked dies that pass the_probe tests are packaged._By_identifying problematic stacked dies at an_early stage, packaging costs are saved._Typically, the test programs for_probing_the_stacked dies are generated by_merging individual test programs for testing_dies 4 and_6, and dies on wafer 2. However,_since_dies 4 and 6 and wafer_2_are separately manufactured, their test programs_may_be_generated for different platforms. For_example, some of the test programs_are UNIX-based, and some are Window-based. Merging these test_programs thus becomes_a very challenging task.
Accordingly, what_is_needed_in the art are test methods and/or test structures for_probing stacked_dies without incurring_difficulties in merging the test programs. Various types of structures_that are generally referred to as towers_are in use on recreational and pleasure boats. The towers are_typically fabricated from metal tubing or pipe. The_towers form a structure over part of_the deck surface of_the_boat