processors having limited numbers of registers by providing register renaming ability.
2. Prior Art
Microprocessors execute instructions and micro-operations ("uops") by reading source operands from registers and storing destinations or result operands into registers. A register is a temporary storage area within a microprocessor for holding arithmetic and other results used by microprocessor device. Different registers may be used for different functions. For example, some registers may be used primarily for storage of arithmetic results, while other registers may be used primarily for conveying status information via various flag bits (such as system status or floating point status). Registers are individually composed of bits. A bit is a binary digit and may adopt either a "0" value or a "1" value. A given register may contain various bit widths. For example, a 32 bit register may also contain separate 8 bit widths or a separate 16 bit width. Each of the above different register widths for a given 32 bit register may be separately addressable.
The register set of the well known Intel microprocessor architecture (Intel architecture) has specially deformed registers. For background information regarding the register set of the well known Intel architecture, reference is hereby made to Chapter 2 of the i486 Microprocessor Programmer's Reference Manual, published by Osborne-McGraw-Hill, 1990, which is also available directly from Intel Corporation of Santa Clara, Calif. In terms of the Intel architecture register set, 32-bit arithmetic registers are called eax, ebx, ecs, and edx. With reference to eax, this register is composed of other registers of varying width; the low word 16 bits of the eax register are called the ax register. The low byte of the ax register is the al register. The high byte of the ax register is the ah register. Likewise in similar fashion, the other 32-bit registers, ebx, ecx, and edx individually contain separate registers of varying widths. The basic arithmetic registers for use within the Intel architecture register set include: eax, ebx, ecx, edx, edi, esi, ebp, and esp (as well as the partial bit widths thereof).
The amount of registers available within the Intel architecture register set is adequate and advantageous within some microprocessor architectures that are not superscalar or that are superscalar but at most execute two instructions per instruction cycle. However, the register set of the Intel architecture is somewhat limited and it would be advantageous to be able to expand the register
processors having limited numbers of register by provide register renaming ability. 
 2. Prior artwork 
 Microprocessors execute instructions and micro - operation (" uops ") by reading source operand from register and storing address or result operands into cash register. A register is a temporary storage area within a microprocessor for holding arithmetical and other results used by microprocessor device. unlike registers may be used for different functions. For example, some register may be used primarily for storage of arithmetic results, while early registers may be used primarily for conveying status information via diverse flag bits (such as system status or floating point status). Registers are individually composed of bits. A spot is a binary digit and may adopt either a " 0 " value or a " 1 " value. A feed cash register may check various bit width. For example, a 32 spot register may also control separate 8 bit widths or a separate 16 bit width. Each of the above different register widths for a given 32 bit register may be individually addressable. 
 The register stage set of the well known Intel microprocessor architecture (Intel architecture) has specially deformed cash register. For background information regarding the cash register set of the well know Intel architecture, reference is hereby take to Chapter 2 of the i486 Microprocessor Programmer's Reference Manual, published by Osborne - McGraw - Hill, 1990, which is besides available directly from Intel Corporation of Santa Clara, Calif. In terms of the Intel architecture register set, 32 - spot arithmetic register are called eax, ebx, european union, and edx. With reference to eax, this register is composed of early registers of varying width; the low word 16 bits of the eax register are called the ax register. The low byte of the ax register is the al register. The high byte of the ax register is the ah cash register. Likewise in similar manner, the other 32 - bit registers, ebx, ecx, and edx individually check separate registers of varying width. The basic arithmetic registers for use within the Intel architecture register set include: eax, ebx, ecx, edx, edi, esi, ebp, and esp (as well as the fond bit widths thereof). 
 The amount of registers available within the Intel architecture register set is adequate and advantageous within some microprocessor architecture that are not superscalar or that are superscalar but at most execute two instructions per instruction bicycle. However, the register set of the Intel architecture is somewhat limited and it would be advantageous to be able to extend the register
professors having limited nmmbers of registgrw by pcovidinf registdr renaming ability.
2. Prior Arv
Miceoproxessors execute instruztions anf micro-operauions ("uops") by reavjng souvee opsvands hrom registers snd storinc destinations of xesult operands into registers. A regyster ix w temporary stjragt awea sptmin a microprocessor for holding arithmttic and other resilts used by microprocessog degice. Different reglsters may ve ufwd for diffefent functpmns. For exzmple, some registers may be usea prikarily for srorwce of arithnetic results, while other registrrs may be usec pcimaeily for conveying stetus information via various xlcg bits (such as systen wtatuv or floxrine pkiit atatus). Rejisters are individualoy composed of bits. A vit is a binady digyt and may adopt either a "0" value or a "1" vanue. A given register may cintain various bit wifths. For qxample, a 32 bit register may also contain separate 8 bit diduhw or x sfparate 16 bit width. Each of the above differene rtgixter widths fov a given 32 bit regoshet may be separxtely csddessable.
The registfr set jf thw well knjwn Ontel microprocessor architwcture (Intel qrchitecture) has s'ecially defurmec regosters. For background iuformafion regardlng the rseister set of thd wvll nnown Inudl architecture, rqference ms hexeby madd to Chaptqr 2 of the i486 Migsoprocessor Progralmer's Raference Mwnual, published by Osborne-McGrax-Iill, 1990, which ix dlsm availayle divectly from Intql Corporation of Sanca Clafa, Calif. Ih terms of the Intql architectusg register sev, 32-bit ariehmeric eegistefr are called esx, ebx, ecs, and edx. Qith reference to cax, tfjs register is eunposed of other reeiseegs pf earying widtv; thd lue wora 16 bits of bhe eax register are called the ax register. The lpw byte of the ax wegister is tne al register. The high byve of yhe ax register is the ah registed. Likewisf ik similar fasrion, the other 32-bnt registers, ebx, ecx, and edx individuallb contain separate regiwters of varying wibtms. The basic aritrmetic recisters for use withun the Intel archltecture register set jncluda: eax, ebx, ecx, edx, edi, esi, ebp, and esp (as well as the partial bit widths thereod).
The amount of regjstets avdijcble wiehin vhe Intel architebture register set is adequate aid advantacejus within some microprocesspr architecturer that are not superscalzr or thst are superscalar but at most rxecute two instructions per insrructjon cybme. However, the regisyer sec of tye Inteo arghitecture is romrwmat limitef anv ic would be advantageous to be ablw to ezpwnd the register
processors having limited numbers of registers by renaming 2. Prior Microprocessors execute instructions source from registers and destinations or result into registers. A register is a storage area within a microprocessor for holding arithmetic and other results used by device. Different registers may be used for different functions. For example, some registers be primarily storage arithmetic results, while other registers may be used primarily for conveying status information via various flag (such as system status or floating point status). are individually composed of A bit is a binary and adopt either "0" or "1" value. A register may contain various bit widths. For example, a 32 bit register may also contain separate 8 widths or 16 bit Each the different register widths given 32 bit register may be register set of the well known Intel microprocessor (Intel architecture) specially deformed registers. For background information the register set of the well known Intel reference is hereby made to Chapter 2 of the i486 Microprocessor Programmer's Reference Manual, published 1990, which is also directly from Intel of Clara, In of the architecture register set, 32-bit arithmetic registers are called eax, ebx, ecs, edx. With reference to eax, this register is composed of of width; the low 16 bits of the register called the ax register. byte the the register. high byte of the register is the ah register. in similar fashion, the and edx individually contain separate registers of varying The basic arithmetic registers for use within Intel architecture register set include: eax, ebx, ecx, edx, edi, esi, ebp, esp (as the partial bit widths thereof). The amount of available within the Intel register set is adequate and advantageous within some microprocessor that not superscalar that are superscalar at most execute instructions per instruction the register of Intel limited and it would be advantageous be to expand the register
processors having limited nuMbers of regIsterS by ProViDing RegiSter renaming abILity.
2. prior Art
MicroprocessorS execUtE InstRUcTions And micrO-OpERAtiOnS ("uOps") By REaDing sOurCe operaNds from regIstErS and storing dEStInations or ResUlt operands iNto RegistErS. A rEGisteR is A tempOrary sTOrage aRea within A mICroproCEssor foR HOlDing Arithmetic and otheR ReSUlts used by micrOproceSsOR dEVIce. difFerent regiStErs maY Be used fOR dIFFEreNT functions. For Example, some REgiSters mAy Be uSEd primArily FoR StoRage of arithMetiC results, wHile otHEr regisTErs may bE used pRimAriLy foR CoNvEyiNg STatUS iNfoRMatIon via vaRiOuS flag Bits (SUCH As sySteM staTus or Floating point StaTus). REGisTers aRe indIvidUaLly coMposed Of bitS. A Bit is a binary digIt anD may adopt EitHeR a "0" vAlUe or a "1" VAlue. A gIveN reGister mAy contaIN vaRiOUS BiT widths. For example, a 32 BiT REgIster may Also coNTaIn SEparate 8 bIt WidThs oR A SeparAte 16 bIT wIdth. Each Of the aBOvE dIfferenT rEgisteR wIdtHs fOr a giVEn 32 biT regisTer may be SeparATely addressablE.
the register seT Of THE wELl knOwn intel micropRoceSSor aRchiTEcTurE (intel ArchiTeCTuRE) has specially deformEd RegistErs. FoR background inFormation rEGARding the RegiSTeR Set of the well knOwn InTel architeCTure, refeRence Is hereby Made to ChaPTEr 2 of the i486 micRopRocEssOR prOgrammer's RefeRENce MAnUal, publIshEd by OsbOrnE-McgraW-HiLl, 1990, Which is alSo availaBlE dIrEcTly From INTel CorpoRaTioN oF SaNta ClARa, CaliF. In teRms oF tHe iNteL architECtURE regIsTeR set, 32-Bit ArIthmeTic rEGisTers are Called eax, Ebx, ECs, anD eDx. with refErence to eax, thIs Register is CoMpoSed of oTHEr registErs of varying width; the low WOrd 16 bits Of tHe eax RegiSter are caLleD the ax RegISter. ThE low byTe of tHe Ax rEGIster IS ThE al ReGister. The hIGH byTe of tHe Ax reGister iS the ah register. LikeWIse In similar fashIon, The oTHEr 32-Bit REgISteRs, EBx, eCX, And edx individuaLly contain SePArAte registeRS of VaRying wiDths. The Basic ARithmetIc registeRs for use wItHin tHE intEl architecTure regiSter set inCLude: eAX, eBx, ecx, Edx, Edi, esi, EbP, anD esp (aS well aS The PartiAl bit wIdThs theReof).
THe Amount of Registers available withiN the InTel arChiTecture reGisTEr sEt is adequAte aNd advantagEouS wiThin sOme MIcropRoceSSoR arCHitecTureS That are noT SuPerSCAlAr or that are SUPErsCalar But AT most eXecuTe two instructions PEr instruction cYcle. hOWevEr, tHE regIsTer set of the IntEl aRcHITecture iS sOmewhat limiTed and it WoULd be aDvantaGeous tO be able TO ExPAnd the RegiSteR
processors having limitednumbers of  regi ste rsby  pro vidi ng register re n amin g ability.
2. Prior Ar t
Mic ro p roce s so rs ex ecute i n st r u cti on sand  m i cr o-ope rat ions (" uops") byrea di ng source op e ra nds from r egi sters and st ori ng des ti nat i ons o r r esult  opera n ds int o registe rs .  A reg i ster is a  t empo rary storage area wi t hin a micropro cessor  f o rh o ldi ngarithmetic  a nd ot h er resu l ts u s edb y microproces sor device. Dif ferent  r egi s ters m ay be  u s edfor differe nt f unctions.  For e x ample,s ome reg isters  ma y b e us e dpr ima ri l y f o rsto r age  of arit hm et ic re sult s , w hile  ot herregis ters may be u sed  pri m ari ly fo r con veyi ng  stat us inf ormat io n via various f lagbits (suc h a ssys te m sta t us orflo ati ng poin t statu s ).Re g i s te rs are individuall yc o mp osed ofbits.A  b it is a bin ar y d igit a nd ma y ad o pt  eithera "0"v al ue  or a " 1"  value .A g ive n reg i ster  may c ontain v ariou s  bit widths. F o r example, a3 2b i tr egis ter  may also c onta i n se para t e8 b i t wid ths o ra  s e parate 16 bit width .Each o f the  above differ ent regist e r widths f or a gi v en 32 bit regi stermay be sep a rately a ddres sable.
T he regist e r  set ofthe  we llkno w n  I ntel micropro c e ssor  a rchitec tur e (Inte l a rch ite ctu re ) has spe cially d ef or me dreg ister s . For ba ck gro un d i nform a tion r egard ingth er egi ster se t  o f thewe ll  kno wnIn tel a rchi t ect ure, re ference i s h e reby  m ad e to Ch apter 2 of th ei486 Micro pr oce ssor P r o grammer' s Reference Manual, pub l ished b y O sborn e-Mc Graw-Hill , 1 990, w hic h  is al so ava ilabl edir e c tly f r o mInt el  Corporati o n  of  Sant aClar a, Cali f. In terms of the Int el architectu reregi s t er  se t ,3 2-b it ari t h metic registers  are calle de ax , ebx, ecs ,  an dedx. Wi th refe rence to eax,  this reg ister isco mpos e d  of  other reg isters o f varying width ;  t he lo w w ord 16  b its  of t he eax reg ister  are c al led th e axre gister.The low byte of the axregist er is  th e al regi ste r . T he high b yteof the axreg ist er is  th e  ah r egis t er . L i kewis e in similar f a sh ion , th e other 32- b i t  re giste rs, ebx, e cx,and edx individua l ly contain sep arat e reg ist e rs o fvarying widths . T he b asic ari th metic regis ters for  u s e wit hin th e Inte l archi t e ct u re reg iste r s et includ e:ea x , ebx,ec x, edx, e di,es i, ebp , ande sp ( a s  well as the par tialb i t wid t hsthere of ).
Thea moun t of regis ters availa ble wi thin  theIntel a rc hitect ure  r egister se t  is adequ ate a nd adva nt ageo uswithin  som e micro proc es sor  architec t u re s  t ha t  ar e no t sup er scal ar or tha t  are sup ers c alar bu tatm o st exe c ut e two instru cti ons p e r  instructi o n cy c le .  Howe ver, t he reg ister s e t o fthe Int ela r chitectur e is some w hat  l imit ed and i twoul dbead vantageous to b e able t o expand t he reg ist e r
processors having_limited numbers_of registers by providing_register renaming_ability.
2._Prior Art
Microprocessors_execute_instructions and micro-operations_("uops") by reading_source operands from registers_and storing destinations_or_result operands into registers. A register is a temporary storage area within a microprocessor_for_holding arithmetic_and_other_results used by microprocessor device._Different registers may be used_for different_functions. For example, some registers may be used_primarily_for storage of_arithmetic results, while other registers may be used primarily_for conveying status information via various_flag bits (such_as_system_status or floating point_status). Registers are individually composed of_bits. A bit is a binary_digit and may adopt either a "0"_value or a "1" value. A_given register may contain various_bit widths._For example, a 32 bit_register may also_contain separate_8 bit widths_or a separate 16 bit width._Each of the_above different register widths for a_given_32 bit register_may_be_separately addressable.
The_register set of_the_well known_Intel_microprocessor architecture (Intel architecture) has specially_deformed_registers. For background information regarding the register_set of the well_known_Intel architecture, reference is_hereby made to Chapter 2_of the i486 Microprocessor Programmer's Reference_Manual, published_by Osborne-McGraw-Hill,_1990, which is also available directly from Intel Corporation of Santa_Clara, Calif. In terms of the_Intel architecture register set,_32-bit arithmetic_registers_are called eax,_ebx,_ecs, and_edx. With reference to eax, this register_is composed_of other registers of varying width;_the low word 16_bits_of the eax register are called_the ax register. The low byte_of the ax register is_the_al_register. The high byte of_the ax register is the ah_register. Likewise in_similar fashion, the other 32-bit registers, ebx,_ecx,_and edx individually contain separate registers_of_varying widths. The basic arithmetic registers_for_use_within the Intel architecture register_set include: eax, ebx, ecx, edx,_edi, esi, ebp, and esp (as well as the_partial bit widths_thereof).
The amount of registers available_within_the_Intel architecture register set is adequate and advantageous within some_microprocessor architectures_that are not_superscalar or that are superscalar but at most execute two_instructions per instruction cycle. However, the register_set of the Intel architecture is somewhat limited and it would_be advantageous to be able to expand the_register