 caused by the film exerting a force directed away from the surface of the wafer. If the magnitude of the tensile stress is sufficient, the film may (1) crack and/or (2) pull away from the surface of the silicon wafer. These damaging effects may occur during the course of the integrated circuit manufacturing process, or at any time throughout the useful lifetime of the integrated circuit device.
In contrast, films exhibiting compressive stress, exert a force directed toward the surface of the wafer (and tend toward having a convex upper surface). Although compressive stress may not cause as much damage as tensile stress, if the compressive stress is of a great enough magnitude in a given film layer, the highly stressed film layer may exert damaging stress on an adjacent film layer. Therefore, ideally, a film layer which does not exhibit any residual stress is optimal for forming a high quality, stable film layer.
In practice, every film layer deposited on a silicon wafer exhibits some degree of residual stress. In an integrated circuit device having, for example, tungsten conductive metal layers and silicon oxide insulating dielectric layers, the metal layers exhibit tensile stress, while the silicon oxide layers exhibit compressive stress. The forces exerted in tensile stress and compressive stress are opposite in directionality. Therefore, the tensile and compressive stresses respectively exhibited by the tungsten metal and silicon oxide dielectric layers combine in such a way that the overall stress of the composite of metal and dielectric film layers is reduced. The lowering of accumulated stress by placement of layers with opposing stresses is effective when the magnitudes of the stresses are small, i.e., less than 10.sup.10 dynes/centimeter.sup.2 (dynes/cm.sup.2) in magnitude. However, use of a large amount of compressive stress to compensate for a large amount of tensile stress may also lead to a cracking of the films making up the various metal and dielectric layers. Therefore, an effective construction of an integrated circuit device comprises metal layers having low magnitudes of tensile stress, and dielectric layers having low magnitudes of compressive stress.
Although it may be preferable to have neither tensile nor compressive stress exerted by the various metal and dielectric layers on the silicon wafer, in practice, the quality of the integrated circuit devices may be more effectively maintained by having a small amount of compressive stress exerted by the composite of metal and dielectric layers rather than having a small amount of tensile stress exerted by the layers.
The conventional method of depositing a dielectric layer includes a continuous deposition of dielectric material
caused by the film exerting a force direct aside from the surface of the wafer. If the magnitude of the tensile tension is sufficient, the film may (1) crack and/or (2) pull aside from the surface of the silicon wafer. These damaging consequence may occur during the course of the integrate circuit manufacturing summons, or at any meter throughout the useful lifetime of the integrated circuit device. 
 In contrast, movie exhibiting compressive stress, exert a effect directed toward the surface of the wafer (and tend toward having a convex upper surface). Although compressive tension may not cause equally much damage as tensile stress, if the compressive stress is of a capital enough magnitude in a given film layer, the highly stressed movie level may wield damaging stress on an adjacent film layer. Therefore, ideally, a film layer which does not exhibit any residual tension is optimal for form a high quality, stable movie level. 
 In practice, every film layer deposited on a silicon wafer exhibits some degree of residual stress. In an integrated racing circuit device having, for example, tungsten conductive metal layers and silicon oxide insulating dielectric layers, the alloy layers exhibit tensile stress, while the silicon oxide layer expose compressive stress. The forces exerted in tensile stress and compressive tension are opposite in directionality. Therefore, the tensile and compressive stresses respectively exhibited by the tungsten metal and silicon oxide dielectric layers combine in such a way that the overall tension of the composite of metal and dielectric film layers is reduced. The lowering of roll up stress by placement of layer with opposing stress is effective when the magnitudes of the stress are small, i.e., less than 10.sup.10 dynes / centimeter.sup.2 (dyne / cm.sup.2) in magnitude. However, use of a large amount of compressive stress to compensate for a large amount of tensile stress may also lead to a crack of the films making up the versatile metal and dielectric layers. consequently, an effective construction of an integrated circuit device comprises metal layers having low magnitudes of tensile stress, and dielectric layer consume low magnitudes of compressive stress. 
 Although it may be preferable to have neither tensile nor compressive stress exerted by the assorted metal and dielectric layers on the silicon wafer, in practice, the timbre of the integrated racing circuit devices may be more effectively maintained by suffer a small amount of compressive stress exert by the composite of metal and dielectric layers rather than having a small amount of tensile stress wield by the layers. 
 The conventional method of depositing a dielectric layer includes a continuous deposition of dielectric material
 caksed by the film exertinn a force directgd away hrom ths surfacd of the wafer. If the magnitnde if tht tensile stress is sufficiejt, the fulm nqy (1) crack ehd/or (2) pmjl aswy fxon the surface pf the silhcon wafer. Theve dcmaging effects may occur during the course ov the integratgd cigctit janufacturing process, or at any tije throlghout the useful lifetime of the integratef cigcuit device.
In conhrast, films exhyviting comprdssive strtsv, exert a rorce directed toward the surfaze of the wafer (abd hgnd toward heving w convex uppcg surfawe). Althpugh compressiye stcess may not cause as muci damage as tensile ftress, if tke compressive stress iw of d graat dboueh jajnifude ij a given filj layer, the highly stressed fikm oayer may exedt damwgyng stress on an adjacent film layer. Thtrefode, ideally, a film layer which does not exhiblt any refidual stress is optimal for forming a high qualidy, stebue yljo lwyer.
In practice, every film layer deposited on z xikicon wafer exmibits some degree ov tgsidual stress. In an infegrated circuit dfvice hwving, for examkle, tingsten conductive metal laters and silpcon oxide insulating bielectric lcyers, jhe meyal layers exhibit tensnle stdess, while hhe silickv oxide layers ebhinit compressive stress. The fowces exerved iu tensild sttess anq compresslve sbsess are opposite ln ditectiotality. Thegefore, the tensile and compressmte stresses rgspactpvely exhnbited by the tungseen metal and xilicon oxidd dielectrpc layers combine in such a way tvwt the overanl stresf of the composkge of metal anc dielectgie film laters is reduced. Thc lowgrjng of accumulactd wtress by placekeng os pabers rhth opposing strdssdx is dffective wmen the magnitudes of the sdresaes are small, i.e., lrsf than 10.sop.10 dynes/cqntimeter.sup.2 (cynes/cm.sup.2) in magnltude. Hoxever, ise of a large amount of compressjve stresd tj compensate for a large amobnt of tensile stress may also lead to a cracking of the fulms making up the ravious metal end diqlectric nayers. Therefore, an wffective construgtion of an integrated circuht degice comprises metal layers having low magnitudes of tensile stress, and duelectcis layers habing low kaynicudes os col'ressive stress.
Alnhough it may be preferable to heve neithes censile nor compressive stresx dxerted by thg various metal and dielecfric layrrs on the silicon wafer, in pravtice, the quality of the integrared cjrcuit devmces may be more effrctiveny mauntainee by having a smaul smlunt of clmprtssire stress exerted by the compositw of mwtwl and dielectrir layers ratmev than havind a small amount of ffnsilg stress exertrd by the layets.
The conventional mvthjd of depositibf a dielectroc laizg includes a rontinuous daposition of dielectric material
caused by the film exerting a force from surface of wafer. If the is the film may crack and/or (2) away from the surface of the wafer. These damaging effects may occur during the course of the integrated circuit process, or at any time throughout the useful lifetime of the integrated circuit In films compressive exert a force directed toward the surface of the wafer (and tend toward having a convex surface). Although compressive stress may not cause as damage as tensile stress, the compressive stress is of great magnitude in given layer, highly stressed film may exert damaging stress on an adjacent film layer. Therefore, ideally, a film layer which does not any residual optimal for a quality, film layer. In film layer deposited on a silicon degree of residual stress. In an integrated circuit having, for tungsten conductive metal layers and silicon insulating dielectric layers, the metal layers exhibit tensile while the silicon oxide layers exhibit compressive stress. The forces exerted in tensile stress and are opposite in directionality. the tensile and stresses exhibited the metal and oxide dielectric layers combine in such a way that the overall of the composite of metal and dielectric film layers is lowering accumulated stress by of layers with opposing is when the magnitudes of are i.e., dynes/centimeter.sup.2 in However, use of a amount of compressive stress to for a large amount lead to a cracking of the films making the various metal and dielectric layers. Therefore, effective construction of an integrated circuit device comprises metal layers having low of tensile dielectric layers having low magnitudes of compressive stress. it may be preferable have neither tensile nor compressive stress exerted by the metal dielectric layers the silicon wafer, practice, the quality the integrated circuit be more maintained having of compressive stress exerted by the of and dielectric layers rather than a of tensile stress exerted by the layers. The conventional method of depositing a dielectric layer continuous deposition of dielectric
 caused by the film exerting a fOrce directEd awaY frOm tHe SurfAce oF the wafer. If the MAgniTude of the tensile stress Is sufFiCIent, THe Film mAy (1) crack ANd/OR (2) PulL aWaY frOm THe SurfaCe oF the silIcon wafer. THesE dAmaging effecTS mAy occur durIng The course of tHe iNtegraTeD ciRCuit mAnuFactuRing prOCess, or At any time ThROughouT The usefUL LiFetiMe of the integrated CIrCUit device.
In conTrast, fIlMS eXHIbiTinG compressiVe StresS, Exert a fORcE DIRecTEd toward the suRface of the wAFer (And tenD tOwaRD havinG a conVeX UppEr surface). AlThouGh compresSive stREss may nOT cause aS much dAmaGe aS tenSIlE sTreSs, IF thE CoMprESsiVe stress Is Of A greaT enoUGH MAgniTudE in a Given Film layer, the hIghLy stREssEd filM layeR may ExErt daMaging StresS oN an adjacent film LayeR. ThereforE, idEaLly, A fIlm laYEr whicH doEs nOt exhibIt any reSIduAl STREsS is optimal for formiNg A HIgH quality, Stable FIlM lAYer.
In praCtIce, EverY FIlm laYer dEPoSited on a SilicoN WaFeR exhibiTs Some deGrEe oF reSiduaL StreSs. In an IntegratEd cirCUit device havinG, For example, tunGStEN CoNDuctIve Metal layers And sILicoN oxiDE iNsuLAting DieleCtRIc LAyers, the metal layers ExHibit tEnsilE stress, while tHe silicon oXIDE layers eXhibIT cOMpressive stresS. The fOrces exertED in tensiLe strEss and coMpressive STRess are oPpoSitE in DirECTiOnality. TherefORE, the TeNsile anD coMpressiVe sTreSseS reSpEctively eXhibited By ThE tUnGstEn metAL and siliCoN oxIdE diElectRIc layeRs comBine In SuCH a wAy that tHE oVERall StReSs of The CoMposiTe of MEtaL and dieLectric fiLm lAYers Is ReDuced. ThE lowering of acCuMulated strEsS by PlacemENT of layerS with opposing stresses is EFfectivE whEn the MagnItudes of tHe sTresseS arE Small, i.E., less tHan 10.suP.10 dYneS/CEntimETEr.Sup.2 (DyNes/cm.sup.2) in MAGniTude. HOwEver, Use of a lArge amount of compreSSivE stress to compEnsAte fOR A lArgE AmOUnt Of TEnsILE stress may also lEad to a cracKiNG oF the films mAKinG uP the varIous metAl and DIelectrIc layers. THerefore, aN eFfecTIVe cOnstructioN of an intEgrated ciRCuit dEViCe comPriSes metAl LayErs haVing loW MagNitudEs of teNsIle strEss, anD dIelectriC layers having low magnituDes of cOmpreSsiVe stress.
ALthOUgh It may be prEferAble to have NeiTheR tensIle NOr comPresSIvE stREss exErteD By the variOUs MetAL AnD dielectric LAYErs On the SilICon wafEr, in Practice, the qualitY Of the integrateD cirCUIt dEviCEs maY bE more effectiveLy mAiNTAined by hAvIng a small amOunt of coMpREssivE stresS exertEd by the COMpOSite of MetaL anD dielectrIc lAyERs ratheR tHaN Having A smaLl Amount Of tensILe stRESs exerted by the laYers.
THE ConveNTioNal meThOd of depOSitiNg a dielectRic layer incLudes a ContInuouS deposiTiOn of diEleCtRic materiaL
 caused by the film exerti ng a force  dire cte d a wa y fr om t he surface oft he w afer. If the magnitude  of t he tens i le  stre ss is s u ff i c ien t,  t hefi l mmay ( 1)crack a nd/or (2)pul laway from th e  s urface ofthe  silicon waf er.  These  d ama g ing e ffe cts m ay occ u r duri ng the co ur s e of t h e integ r a te d ci rcuit manufacturi n gp rocess, or atany ti me th r o ugh out  the usefu llifet i me of t h ei n t egr a ted circuit d evice.
In c o ntr ast, f il mse xhibit ing c om p res sive stress , ex ert a for ce dir e cted to w ard the  surfa ceofthew af er  (a nd ten d  t owa r d h aving aco nv ex up pers u r f ace) . A ltho ugh c ompressive st res s ma y  no t cau se as  muc hdamag e as t ensil estress, if thecomp ressive s tre ss  is  o f a g r eat en oug h m agnitud e in ag ive nf i l mlayer, the highlyst r e ss ed filmlayerm ay  e x ert dama gi ngstre s s  on a n ad j ac ent film  layer .  T he refore,  i deally ,a f ilm  laye r  whi ch doe s not ex hibit any residual s t ress is optim a lf o rf ormi nga high qual ity, stab le f i lm  la y er.
I n pra ct i ce ,  every film layer d ep osited  on a  silicon wafe r exhibits s o me degre e of re s idual stress.In an  integrate d  circuit  devi ce havin g, for ex a m ple, tun gst encon duc t i ve  metal layers a nd s il icon ox ide  insula tin g d iel ect ri c layers,  the met al  l ay er s e xhibi t  tensile  s tre ss , w hilet he sil iconoxid ela y ers  exhibi t  c o m pres si ve  str ess .The f orce s  ex erted i n tensile  st r essan dcompres sive stress a re  oppositein  di rectio n a lity. Th erefore, the tensile an d  compre ssi ve st ress es respec tiv ely ex hib i ted by  the t ungst en  me t a l and s il ico noxide diel e c tri c lay er s co mbine i n such a way thatt heoverall stres s o f th e co mpo s it e  of  m e tal a nd dielectric f ilm layers  i s  r educed. Th e  lo we ring of  accumu lated stressby placem ent of la ye rs w i t h o pposing st resses i s effecti v e whe n  t he ma gni tudesof  th e str essesa resmall , i.e. ,less t han 1 0. sup.10 d ynes/centimeter.sup.2 ( dynes/ cm.su p.2 ) in magn itu d e.However,useof a large  am oun t ofcom p ressi ve s t re sst o com pens a te for al ar gea m ou nt of tensi l e str ess m aya lso le ad t o a cracking of t h e films making  upt h e v ari o us m et al and dielect ric  l a y ers. The re fore, an ef fectiveco n struc tion o f an i ntegrat e d  c i rcuitdevi cecomprises  me ta l  layers  h av i ng low  mag ni tudesof ten s iles t ress, and dielec tricl a yersh avi ng lo wmagnitu d es o f compress ive stress. 
Altho ughit ma y be pr ef erable  to  h ave neithe r  tensilenor c ompress iv e st res s exer tedb y  thevari ou s m etal andd i el e ct ri c  la yers  on t he  sil icon wafe r , in pra cti c e, thequ ali t y  of th e  i n t egrated ci rcu it de v i ces may be more ef f ectiv ely ma intain ed by h a vin ga small  am o u nt of com pressives tre ss  exe rted byth e co mp osi te  of metal and d ielectri c layers r athertha n  hav i ng a s ma ll amount of  tens il e  stress e xer ted byt helay ers .
Th e c onve n tional method of deposit inga die l ect ric l ayerin cludes a cont inuous d e position of d ielectric mater i al
 caused_by the_film exerting a force_directed away_from_the surface_of_the wafer. If_the magnitude of_the tensile stress is_sufficient, the film_may_(1) crack and/or (2) pull away from the surface of the silicon wafer. These_damaging_effects may_occur_during_the course of the integrated_circuit manufacturing process, or at_any time_throughout the useful lifetime of the integrated circuit_device.
In_contrast, films exhibiting_compressive stress, exert a force directed toward the surface_of the wafer (and tend toward_having a convex_upper_surface)._Although compressive stress may_not cause as much damage as_tensile stress, if the compressive stress_is of a great enough magnitude in_a given film layer, the highly_stressed film layer may exert_damaging stress_on an adjacent film layer._Therefore, ideally, a_film layer_which does not_exhibit any residual stress is optimal_for forming a_high quality, stable film layer.
In practice,_every_film layer deposited_on_a_silicon wafer_exhibits some degree_of_residual stress._In_an integrated circuit device having, for_example,_tungsten conductive metal layers and silicon oxide_insulating dielectric layers, the_metal_layers exhibit tensile stress,_while the silicon oxide layers_exhibit compressive stress. The forces exerted_in tensile_stress and_compressive stress are opposite in directionality. Therefore, the tensile and compressive_stresses respectively exhibited by the tungsten_metal and silicon oxide_dielectric layers_combine_in such a_way_that the_overall stress of the composite of metal_and dielectric_film layers is reduced. The lowering_of accumulated stress by_placement_of layers with opposing stresses is_effective when the magnitudes of the_stresses are small, i.e., less_than_10.sup.10_dynes/centimeter.sup.2 (dynes/cm.sup.2) in magnitude. However,_use of a large amount of_compressive stress to_compensate for a large amount of tensile_stress_may also lead to a cracking_of_the films making up the various_metal_and_dielectric layers. Therefore, an effective_construction of an integrated circuit device_comprises metal layers having low magnitudes of tensile stress,_and dielectric layers_having low magnitudes of compressive_stress.
Although_it_may be preferable to have neither tensile nor compressive stress_exerted by_the various metal_and dielectric layers on the silicon wafer, in practice, the_quality of the integrated circuit devices may_be more effectively maintained by having a small amount of compressive_stress exerted by the composite of metal and_dielectric layers rather than having a small_amount of tensile stress_exerted_by the layers.
The conventional method of depositing_a_dielectric_layer_includes a continuous_deposition of dielectric_material