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2. Description of the Related Art
As the size of semiconductor device is scaled down, the requirements for device design and fabrication continue to be tightened in order to fit more circuitry on smaller chips. To achieve higher device packing densities, smaller and smaller sizes are required for device features, such as gate electrodes, interconnect lines, spacing and diameter of contact holes, and the surface geometry, such as corners and edges of various features. In addition, the spacing between adjacent features of an integrated circuit is also reduced in order to obtain higher packing densities.
Prior approaches used high resolution photolithographic processes in order to achieve small feature by improving the control of the length or width and placement of device features, such as the floating gates used in non-volatile memory (NVM) cells. For example, with NVM devices, the printing and etching of spaces in a floating gate poly layer is becoming more and more difficult as the poly-to-poly space shrinks. Conventional approaches for defining and separating the floating gates have required high resolution photolithographic processes to pattern and etch a space in a previously deposited polysilicon layer. With this process, the unetched polysilicon layer located over the active region serves as the floating gate(s) for the NVM bitcell. However, the selective etching of the polysilicon layer can result in overetching effects, such as mouse bites in the upper surface of a floating gate where the reduced width of the floating gate does not allow enough photoresist to protect the floating gate. Another overetching effect from conventional approaches is that the etched floating gates are too small, which can degrade device performance from the reduced charge storage capacity of the overetched floating gate.
Accordingly, a need exists for a smaller device features that are fabricated with a controlled process. There is also a need for a controlled fabrication process that reliably produces reduced spacing between device features. In addition, there is a need for improved semiconductor device structure and manufacturing process to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been
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 2. Description of the Related Art 
 As the size of semiconductor device is scaled down, the requirements for device design and lying stay to be tightened in order to match more circuitry on minor chips. To achieve higher device packing material densities, smaller and smaller size are required for device features, such as gate electrode, interconnect lines, spacing and diameter of contact fix, and the surface geometry, such as corners and edges of various features. In accession, the spacing between adjacent features of an integrated circuit is besides reduced in order to receive higher packing material densities. 
 Prior approach path used high resolution photolithographic process in order to achieve small feature by improving the control of the duration or width and placement of device features, such as the floating gates used in non - volatile memory (NVM) cells. For example, with NVM devices, the printing and etching of quad in a floating gate poly layer is become more and more unmanageable as the poly - to - poly quad shrinks. Conventional approaches for defining and separating the floating gates have command high resolution photolithographic processes to pattern and etch a space in a previously deposit polysilicon layer. With this process, the unetched polysilicon layer located over the active area serves as the float gate(s) for the NVM bitcell. However, the selective engraving of the polysilicon layer can result in overetching effects, such as mouse bites in the upper surface of a floating gate where the reduced width of the float gate does not permit enough photoresist to protect the floating gate. Another overetching impression from conventional approach is that the etched floating gate are too little, which can degrade device operation from the reduced charge storage capacitance of the overetched floating gate. 
 consequently, a need exists for a smaller device feature that are fabricated with a controlled process. There is also a motivation for a controlled fabrication summons that reliably produces repress spacing between device features. In addition, there be a need for improved semiconductor device structure and manufacturing process to overcome the problem in the artwork, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the end of the present application with reference to the drawings and detailed description which follow. 
 It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawing have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated proportional to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been
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2. Dedcription of the Related Art
As the size of semmconducfor devize is scaled down, the requirxmenrs foe device design and facrication continuw to ve tightenxs in order to nit mmce circuitry on smaller cvips. To achieva fiyher device packing densities, smallew and skapler sizes are reqliwed ror device features, such as gate emectrodts, interconnect limes, spacing and diameter ov cojtact holes, and thf surface ggkmeeey, such as curners and edges of vatious features. In addition, the soaciny between aejqcejj features oh an igtegrated civbuit is also rrduced in ordev to mbtqin higher packing deisities.
Prior approacres used viyh resolution photolirhigrapvic [rocdwser ih prser to aciieve small feature by improving the conttoj of the lengtg or wydeh and placement of device features, sucv aa the floating gates uswd in non-volatile memlry (NVM) cqlls. For example, with NVM devices, the printing ang etciivg if rpafes in a floating gate poly layer is becoming jote and more difflcult as the poly-tp-pllu space shrinkr. Convzhtjonal approaches flr defiging qnd separwtinb the floating gates have rwquired high eesolution photolichographic pxocessgs to lattern and etch a spacz in a previously deposites polysilicon laydr. Eidh this kfocess, the unetchqd polysioicou layer uocajed ovew the actige renhon serves as the vloatnng gdte(s) for tje NVM bitcell. However, the selervive etching pf thv polysilncon lsyer can resujt in overetchnng effeets, suzh as mousv bites ii the upper furface of a xpoating gate where tre rwducwd widtf of the floatimg gate does not aloow enough photorexisj fo protect the yuiating gate. Anoyhef odegetrhing affect from wonvdntkpnal xpproaches ls ghat the etched floating gatss are too small, wnigh can detrade dedice performamce from the reductd chacge sturage cakacity of the overetched floatihg gate.
Acforqingly, a neeq exlsts for a smakler device features that are fabricatev with a controlled proxess. There is also c keed for a cpntrojled fabrhcation process that reliably producex reduced spacing betseen davice features. In addition, there is a need for improved semiconductor device srructuce and manufadturong pgoczss to ovqrcolx the problems in the art, such as outlined above. Further lnmitations and disadvantages pf conventional processes and technologjes will become apparent to one of skilk in the art after revieeing the remajnder of tie present applicatipn witk refeeence ti thc drawings and deyalled descrlptipn which follow.
It will be appreciared thqt for simplicity end clarity ln illuatratijn, elements illuatraffd in the drawings have not necexsarily been drawn tm fcale. For examkle, the dimensipns of vome of the xlements are exaggerated relative to other elements for purposea of promkting and improving clscity and understanding. Fmrthew, where zonsidered a[propriate, reference numerals have been
. 2. Description of the Related Art size semiconductor device scaled down, the fabrication to be tightened order to fit circuitry on smaller chips. To achieve device packing densities, smaller and smaller sizes are required for device features, such gate electrodes, interconnect lines, spacing and diameter of contact holes, and the surface such corners edges various features. In addition, the spacing between adjacent features of an integrated circuit is also reduced order to obtain higher packing densities. Prior approaches high resolution photolithographic processes order to achieve small feature improving control of length width placement of device such as the floating gates used in non-volatile memory (NVM) cells. For example, with NVM devices, the and etching in a gate layer becoming more and as the poly-to-poly space shrinks. Conventional and separating the floating gates have required high photolithographic processes pattern and etch a space in previously deposited polysilicon layer. With this process, the polysilicon layer located over the active region serves as the floating gate(s) for the NVM the selective etching of polysilicon layer can in effects, as bites in upper surface of a floating gate where the reduced width of floating gate does not allow enough photoresist to protect the Another effect from conventional is that the etched gates too small, which can performance the capacity the floating gate. Accordingly, a exists for a smaller device that are fabricated with also a need for a controlled fabrication process reliably produces reduced spacing between device features. addition, there is a need for improved semiconductor device structure and manufacturing to overcome in the art, such as outlined above. Further and disadvantages of conventional and technologies will become apparent to one of skill the after reviewing remainder of the application with reference the drawings and which follow. will appreciated and clarity of illustration, elements illustrated the have not necessarily been drawn scale. the dimensions of some of the elements are exaggerated relative to other elements for purposes and improving clarity and Further, considered appropriate, reference numerals have been
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2. Description of the Related ArT
As the size Of semIcoNduCtOr deVice Is scaled down, thE RequIrements for device desigN and fAbRIcatIOn ContiNue to be TIgHTEneD iN oRdeR tO FiT more CirCuitry oN smaller chIps. to Achieve higheR DeVice packinG deNsities, smallEr aNd smalLeR siZEs are ReqUired For devICe featUres, such aS gATe elecTRodes, inTERcOnneCt lines, spacing and DIaMEter of contact hOles, anD tHE sURFacE geOmetry, such As CorneRS and edgES oF VARioUS features. In adDition, the spACinG betweEn AdjACent feAtureS oF An iNtegrated ciRcuiT is also reDuced iN Order to OBtain hiGher paCkiNg dEnsiTIeS.
PRioR aPProAChEs uSEd hIgh resolUtIoN photOlitHOGRAphiC prOcesSes in Order to achievE smAll fEAtuRe by iMprovIng tHe ContrOl of thE lengTh Or width and placeMent Of device fEatUrEs, sUcH as thE FloatiNg gAteS used in Non-volaTIle MeMORY (NvM) cells. For example, wItH nvM Devices, tHe prinTInG aND etching Of SpaCes iN A FloatIng gATe Poly layeR is becOMiNg More and MoRe diffIcUlt As tHe polY-To-poLy spacE shrinks. conveNTional approachES for defining aND sEPArATing The Floating gatEs haVE reqUireD HiGh rESolutIon phOtOLiTHographic processes tO pAttern And etCh a space in a prEviously dePOSIted polySiliCOn LAyer. With this prOcess, The unetcheD PolysiliCon laYer locatEd over the ACTive regiOn sErvEs aS thE FLoAting gate(s) for THE NVM BiTcell. HoWevEr, the seLecTivE etChiNg Of the polySilicon lAyEr CaN rEsuLt in oVEretchinG eFfeCtS, suCh as mOUse bitEs in tHe upPeR sURfaCe of a flOAtING gatE wHeRe thE reDuCed wiDth oF The FloatinG gate does Not ALlow EnOuGh photoResist to proteCt The floatinG gAte. anotheR OVeretchiNg effect from conventionaL ApproacHes Is thaT the Etched floAtiNg gateS arE Too smaLl, whicH can dEgRadE DEvice PERfOrmAnCe from the rEDUceD charGe StorAge capaCity of the overetcheD FloAting gate.
AccoRdiNgly, A NEeD exIStS For A sMAllER Device features tHat are fabrIcATeD with a contROllEd Process. there is Also a NEed for a ControlleD fabricatIoN proCESs tHat reliablY produceS reduced sPAcing BEtWeen dEviCe featUrEs. IN addiTion, thERe iS a neeD for imPrOved seMiconDuCtor deviCe structure and manufactuRing prOcess To oVercome thE prOBleMs in the arT, sucH as outlineD abOve. furthEr lIMitatIons ANd DisADvantAges OF conventiONaL prOCEsSes and technOLOGieS will BecOMe appaRent To one of skill in the ARt after reviewiNg thE REmaIndER of tHe Present applicaTioN wITH referenCe To the drawinGs and detAiLEd desCriptiOn whicH follow.
iT WiLL be appReciAteD that for sImpLiCIty and cLaRiTY of illUstrAtIon, eleMents iLLustRATed in the drawings Have nOT NecesSAriLy beeN dRawn to sCAle. FOr example, tHe dimensionS of somE of tHe eleMents arE eXaggerAteD rElative to oTHer elemenTs for PurposeS oF proMotIng and ImprOVIng clAritY aNd uNderstandING. FURtHeR, WheRe coNsideReD appRopriate, rEFerence nUmeRAls have BeEn
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2. Description of the Re lated ArtAs th e s ize  o f se mico nductor device is s caled down, the requir ement sf or d e vi ce de sign an d  f a b ric at io n c on t in ue to  be  tighte ned in ord erto  fit more ci r cu itry on sm all er chips. To  ac hievehi ghe r  devi cepacki ng den s ities,  smalleran d  small e r sizes a re  req uired for devicef ea t ures, such asgate e le c tr o d es,  in terconnect  l ines, spacing an d d iam e ter of contac t holes, an d  th e surf ac e g e ometry , suc ha s c orners andedge s of vari ous fe a tures.I n addit ion, t hespa cing be tw een  a d jac e nt  fe a tur es of an  i nt egrat ed c i r c u it i s a lsoreduc ed in order t o o btai n  hi gherpacki ng d en sitie s.
Pri or ap pr oaches used hig h re solutionpho to lit ho graph i c proc ess esin orde r to ac h iev es m a ll  feature by improv in g th e contro l of t h ele n gth or w id thandp l aceme nt o f  d evice fe atures ,  s uc h as th efloati ng  ga tes  used in n on-vol atile me mory( NVM) cells. Fo r  example, wit h  N V M  d e vice s,the printin g an d  etc hing of  sp a ces i n a f lo a ti n g gate poly layer i sbecomi ng mo re and more d ifficult a s t he poly- to-p o ly space shrinks.  Conv entional a p proaches  fordefining  and sepa r a ting the  fl oat ing  ga t e shave required h ighre solutio n p hotolit hog rap hic  pr oc esses topatternan det ch  aspace in a pre vi ous ly  de posit e d poly silic on l ay er .  Wi th this pr o c ess,  t he  une tch ed  poly sili c onlayer l ocated ov ert he a ct iv e regio n serves as t he  floatingga te( s) for t he NVM b itcell. However, the se l ectiveetc hingof t he polysi lic on lay erc an res ult in  over et chi n g  effe c t s,  su ch  as mouseb i tes  in t he  upp er surf ace of a floatingg ate  where the re duc ed w i d th  of th e  fl oa t ing g ate does not al low enough  p h ot oresist to pro te ct thefloatin g gat e . Anoth er overet ching eff ec t fr o m  co nventional  approac hes is th a t the et chedflo atingga tes  aretoo sm a ll,  whic h cande gradedevic eperforma nce from the reduced ch arge s torag e c apacity o f t h e o veretched  flo ating gate .
A cco rding ly, a nee d ex i st s f o r a s mall e r devicef ea tur e s  t hat are fab r i c ate d wit h a contro lled  process. There i s  also a need f or a c ont rol l ed f ab rication proce ssth a t  reliabl yproduces re duced sp ac i ng be tweendevice  featur e s .I n addi tion , t here is a  ne ed for imp ro ve d  semic ondu ct or dev ice st r uctu r e  and manufacturi ng pr o c ess t o  ov ercom ethe pro b lems  in the ar t, such asoutlin ed a bove.  Furthe rlimita tio ns  and disad v antages o f con vention al  pro ces ses an d te c h nolog ieswi llbecome ap p a re n tto one  ofskill  i n th e art aft e r review ing the rem ai nde r of the pr e s ent applic ati on wi t h  reference to t h ed rawin gs and  detai led des c rip ti on whic h f o l low.
It w ill be ap p rec ia tedthat for  s impl ic ity  a nd clarity of i llustrat ion, ele m e nts il lus t rate d  in th edrawings hav e not  n e cessari l y  be en draw n  to  sc ale . Fo r e xamp l e, the dimensions of som e of  thee lem entsare e xa ggerated rela tive too ther elements  for purposes o f  pr o moti nga nd  i mprovingcla r ity a nd u nde rsta ndi ng.F u rthe r , wh e re  con sidere d ap pr op riate, re fe rence n u mera l s h avebeen
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2. Description_of the_Related Art
As the size_of semiconductor_device_is scaled_down,_the requirements for_device design and_fabrication continue to be_tightened in order_to_fit more circuitry on smaller chips. To achieve higher device packing densities, smaller and_smaller_sizes are_required_for_device features, such as gate_electrodes, interconnect lines, spacing and_diameter of_contact holes, and the surface geometry, such as_corners_and edges of_various features. In addition, the spacing between adjacent features_of an integrated circuit is also_reduced in order_to_obtain_higher packing densities.
Prior approaches_used high resolution photolithographic processes in_order to achieve small feature by_improving the control of the length or_width and placement of device features,_such as the floating gates_used in_non-volatile memory (NVM) cells. For_example, with NVM_devices, the_printing and etching_of spaces in a floating gate_poly layer is_becoming more and more difficult as_the_poly-to-poly space shrinks._Conventional_approaches_for defining_and separating the_floating_gates have_required_high resolution photolithographic processes to pattern_and_etch a space in a previously deposited_polysilicon layer. With this_process,_the unetched polysilicon layer_located over the active region_serves as the floating gate(s) for_the NVM_bitcell. However,_the selective etching of the polysilicon layer can result in overetching_effects, such as mouse bites in_the upper surface of_a floating_gate_where the reduced_width_of the_floating gate does not allow enough photoresist_to protect_the floating gate. Another overetching effect_from conventional approaches is_that_the etched floating gates are too_small, which can degrade device performance_from the reduced charge storage_capacity_of_the overetched floating gate.
Accordingly, a_need exists for a smaller device_features that are_fabricated with a controlled process. There is_also_a need for a controlled fabrication_process_that reliably produces reduced spacing between_device_features._In addition, there is a_need for improved semiconductor device structure_and manufacturing process to overcome the problems in the_art, such as_outlined above. Further limitations and_disadvantages_of_conventional processes and technologies will become apparent to one of_skill in_the art after_reviewing the remainder of the present application with reference to_the drawings and detailed description which follow.
It_will be appreciated that for simplicity and clarity of illustration, elements_illustrated in the drawings have not necessarily been_drawn to scale. For example, the dimensions_of some of the_elements_are exaggerated relative to other elements for_purposes_of_promoting_and improving clarity_and understanding. Further,_where considered appropriate,_reference numerals_have been