stacked package structure 100 comprises a package substrate 110, chip 120a, chip 120b, a spacer 130, a plurality of wires 140, and an encapsulant 150. The package substrate 110 is provided with a plurality of pads 112. The chips 120a and 120b are respectively provided with peripherally arranged pads 122a and 122b. The chip 120a is provided on the package substrate 110 while the chip 120b is provided on the chip 120a with a spacer 130 intervened there-between. The chip 120a is electrically connected to the package substrate 110 by bonding two ends of one of the wires 140 to the pads 112 and 122a respectively. The chip 120b is electrically connected to the package substrate 110 in similar manner. The encapsulant 150 is then provided on the package substrate 110 to cover the chips 120a and 120b and the wires 140.
Since the pads 122a and 122b are respectively provided at the peripheral of the chip 120a and the chip 120b, there is a need to apply the spacer 130 to prevent the chip 120b from directly contacting with the chip 120a for performing the subsequent wire-bonding process. However, the spacer 130 is used for increasing the thickness of the prior chip-stacked package structure 100.
Another prior chip-stacked package structure with different-sized chips has been disclosed. Referring to FIG. 1B, another conventional chip-stacked package structure 10 includes a package substrate 110, chips 120c and 120d, the plurality of wires 140, and an encapsulant 150. The package substrate 110 has pads 112 thereon. The size of chip 120c is larger than the chip's 120d. The chips 120c and 120d are respectively provided with peripherally arranged pads 122c and 122d. The chip 120c is provided on the package substrate 110 while the chip 120d is provided on the chip 120c. The chip 120c is electrically connected to the package substrate 110 by bonding two ends of one of the wires 140 to the pads 112 and 122c respectively. The chip 120d is electrically connected to the package substrate 110 in similar manner. The encapsulant 150 is then provided on the package substrate 110 to cover the chips 120c and 120d and the wires 140.
Since the size of chip 120d is smaller than chip's 120c, the pads 122c of chip 120c would not covered by the chip 120d when the chip 120d is stacked on the chip 120c. However, the condition that
stacked package structure 100 comprises a software substrate 110, bit 120a, chip 120b, a spacer 130, a plurality of wire 140, and an encapsulant 150. The software substrate 110 is provided with a plurality of pads 112. The chip 120a and 120b are respectively provided with peripherally arranged pad 122a and 122b. The chip 120a is provided on the software substrate 110 while the chip 120b is provided on the chip 120a with a spacer 130 intervened there - between. The bit 120a is electrically connected to the package substrate 110 by bonding two ends of one of the wires 140 to the pad 112 and 122a respectively. The chip 120b is electrically connected to the package substrate 110 in exchangeable manner. The encapsulant 150 is then provided on the package substrate 110 to cover the french fries 120a and 120b and the wires 140. 
 Since the pads 122a and 122b are respectively provided at the peripheral of the chip 120a and the chip 120b, there be a need to apply the spacer 130 to prevent the chip 120b from directly contacting with the bit 120a for performing the subsequent wire - bonding process. However, the spacer 130 is used for increasing the thickness of the prior chip - stacked package structure 100. 
 Another anterior bit - stacked software social organization with different - sized chips has been disclosed. Referring to FIG. 1B, another ceremonious chip - stack package structure 10 include a package substrate 110, chips 120c and 120d, the plurality of wires 140, and an encapsulant 150. The package substrate 110 has diggings 112 thereon. The size of chip 120c is larger than the chip's 120d. The chips 120c and 120d are respectively provide with peripherally arranged launching pad 122c and 122d. The chip 120c is provided on the package substrate 110 while the chip 120d is provided on the bit 120c. The chip 120c is electrically connected to the package substrate 110 by bond two ends of one of the wires 140 to the pads 112 and 122c respectively. The chip 120d is electrically connect to the package substrate 110 in similar manner. The encapsulant 150 is then provided on the package substrate 110 to cover the chip 120c and 120d and the wires 140. 
 Since the size of bit 120d is smaller than check's 120c, the pads 122c of chip 120c would not covered by the chip 120d when the chip 120d is stack on the chip 120c. However, the circumstance that
stafked package structure 100 gomprises a packcte subvtrate 110, chip 120a, chip 120b, a spacer 130, a pluralitb of wirew 140, and an encapsulant 150. The packwge subsrratt 110 is provided wivg a pluvclity lf pcdw 112. The chips 120a and 120b are respectively [ruvnded with peripherally arranged pads 122a and 122n. Hhe chip 120a is krovicqd oh the package substrate 110 while the chip 120b is provided pn the chip 120a with a spaceg 130 ijtervened there-betaeen. The chup 120a us electricauly connecueb to the padkage substrate 110 by bonding two ends of one of tye ahres 140 to thx pads 112 and 122a respcbtively. The chop 120b is electrlcallb cobnected to the packagx substrate 110 in simijar mannes. Che encapsulant 150 is tyeb proeideg on rhe padkege substgatx 110 to cover the chips 120q and 120b and the wirts 140.
Fpmce the pads 122a and 122b are respectively provided at the peripverzl of the chip 120a and thw chip 120b, there is a nged to appjy the spacer 130 to prevent the chip 120b from directlf convaztiun dutj the chip 120a for performing the subsequent wiws-bpncing process. Hjwever, the xpwcrt 130 is used for increcaihg the thickness ov the ptior cyip-stackeq pavkage structure 100.
Another priir chip-stackvd pqckage structure wnth differenc-sized chipx has been disclosed. Reyerrinf to FIG. 1B, wnother ckvventional chip-sgacleg packagt structure 10 incluqes a pacjage substrxte 110, chips 120c and 120d, tje plmsality of wires 140, ajd an etcapsulant 150. The package substrate 110 has pavx 112 thereon. Tne side of chi' 120c is larger than ehe chip's 120d. Thg chips 120c and 120a are respvctively 'rovided witr peripherallf arranged pavs 122c and 122q. Thw chup 120c is orovided on thr package substrate 110 while the chip 120d is lrovided on the chup 120c. The chip 120c is elqcnrirally wonnected to the pazlage rubstrauz 110 ny condong two ends of one mf tge wires 140 to the psdf 112 and 122c respectyvely. The chil 120d is electricallj coniected to tne kackage substrate 110 in similar mznner. The engapsulant 150 is thek prjvided on che package substrate 110 to cover the chipw 120c and 120d and the qires 140.
Since the sizg on chip 120d is xmallqr than cvip's 120c, the pads 122c of chip 120c would not covered by the chip 120s when the fhip 120d is stacked on the chip 120c. However, the condition that
stacked package structure 100 comprises a package chip chip 120b, spacer 130, a an 150. The package 110 is provided a plurality of pads 112. The 120a and 120b are respectively provided with peripherally arranged pads 122a and 122b. chip 120a is provided on the package substrate 110 while the chip 120b provided the 120a a spacer 130 intervened there-between. The chip 120a is electrically connected to the package substrate 110 bonding two ends of one of the wires to the pads 112 122a respectively. The chip 120b electrically to the substrate in manner. The encapsulant is then provided on the package substrate 110 to cover the chips 120a and 120b and the 140. Since 122a and are provided the peripheral of 120a and the chip 120b, there to apply the spacer 130 to prevent the 120b from contacting with the chip 120a for the subsequent wire-bonding process. However, the spacer 130 used for increasing the thickness of the prior chip-stacked package structure 100. Another prior chip-stacked with different-sized chips has disclosed. Referring to 1B, conventional package 10 includes package substrate 110, chips 120c and 120d, the plurality of wires and an encapsulant 150. The package substrate 110 has pads The of chip 120c larger than the chip's The 120c and 120d are with arranged 122d. chip is provided on the substrate 110 while the chip is provided on the is electrically connected to the package substrate 110 bonding two ends of one of the 140 to the pads 112 and 122c respectively. The chip 120d is connected to substrate 110 in similar manner. The encapsulant 150 then provided on the substrate 110 to cover the chips 120c and 120d the 140. Since size of chip is smaller than 120c, the pads chip 120c not by when the chip 120d is stacked the 120c. However, the condition that
stacked package structure 100 coMprises a paCkage SubStrAtE 110, chiP 120a, chIp 120b, a spacer 130, a pluRAlitY of wires 140, and an encapsulaNt 150. The PaCKage SUbStratE 110 is provIDeD WIth A pLuRalItY Of Pads 112. THe cHips 120a anD 120b are respeCtiVeLy provided wiTH pEripherallY arRanged pads 122a aNd 122b. the chiP 120a Is pROvideD on The paCkage sUBstratE 110 while the ChIP 120b is prOVided on THE cHip 120a With a spacer 130 intervENeD There-between. ThE chip 120a Is ELeCTRicAllY connected To The paCKage subSTrATE 110 By bONding two ends oF one of the wiREs 140 tO the paDs 112 And 122A RespecTivelY. THE chIp 120b is electrIcalLy connectEd to thE Package SUbstratE 110 in simIlaR maNner. tHe EnCapSuLAnt 150 IS tHen PRovIded on thE pAcKage sUbstRATE 110 To coVer The cHips 120a And 120b and the wirEs 140.
SInce THe pAds 122a aNd 122b arE resPeCtiveLy provIded aT tHe peripheral of tHe chIp 120a and the ChiP 120b, TheRe Is a neED to appLy tHe sPacer 130 to Prevent THe cHiP 120B FRoM directly contactinG wITH tHe chip 120a fOr perfORmInG The subseQuEnt Wire-BONding ProcESs. however, tHe spacER 130 iS uSed for iNcReasinG tHe tHicKness OF the Prior cHip-stackEd pacKAge structure 100.
AnOTher prior chip-STaCKEd PAckaGe sTructure witH difFErenT-sizED cHipS Has beEn disClOSeD. referring to FIG. 1B, anotHeR conveNtionAl chip-stacked Package strUCTUre 10 incluDes a PAcKAge substrate 110, chIps 120c aNd 120d, the plurALity of wiRes 140, anD an encapSulant 150. The PACkage subStrAte 110 Has PadS 112 THeReon. The size of CHIp 120c iS lArger thAn tHe chip's 120D. ThE chIps 120C anD 120d Are respecTively prOvIdEd WiTh pEriphERally arrAnGed PaDs 122c And 122d. THE chip 120c Is proVideD oN tHE paCkage suBStRATe 110 whIlE tHe chIp 120d Is ProviDed oN The Chip 120c. ThE chip 120c is eLecTRicaLlY cOnnecteD to the package SuBstrate 110 by bOnDinG two enDS Of one of tHe wires 140 to the pads 112 and 122c resPEctivelY. ThE chip 120D is eLectricalLy cOnnectEd tO The pacKage suBstraTe 110 In sIMIlar mANNeR. ThE eNcapsulant 150 IS TheN provIdEd on The packAge substrate 110 to coveR The Chips 120c and 120d and The WireS 140.
sInCe tHE sIZe oF cHIp 120d IS Smaller than chip'S 120c, the pads 122c Of CHiP 120c would not COveReD by the cHip 120d wheN the cHIp 120d is stAcked on thE chip 120c. HowEvEr, thE COndItion that
stacked package structure100 compri ses a  pa cka ge  sub stra te 110, chip 1 2 0a,chip 120b, a spacer 13 0, apl u rali t yof wi res 140 ,  a n d  an  e nc aps ul a nt  150.  Th e packa ge substra te11 0 is provide d  w ith a plur ali ty of pads 1 12.  The c hi ps1 20a a nd120bare re s pectiv ely provi de d  withp eripher a l ly  arr anged pads 122a a n d1 22b. The chip120a i sp ro v i ded  on  the packa ge  subs t rate 11 0  w h i l e t h e chip 120b i s providedo n t he chi p120 a  witha spa ce r  13 0 intervene d th ere-betwe en. Th e  chip 1 2 0a is e lectri cal lyconn e ct ed  to  t h e p a ck age sub strate 1 10  b y bon ding t w o  end s o f on e ofthe wires 140  to  the pad s 112  and122a  r espec tively . The  c hip 120b is ele ctri cally con nec te d t othe p a ckagesub str ate 110  in sim i lar  m a n n er . The encapsulant15 0 is  then pr ovided on  t h e packag esub stra t e  110to c o ve r the ch ips 12 0 aan d 120ban d thewi res  14 0.
Si n ce t he pad s 122a a nd 12 2 b are respecti v ely provideda tt h ep erip her al of the c hip1 20aandt he  ch i p 120 b, th er e  i s  a need to apply th espacer  130to prevent th e chip 120 b f rom dire ctly co n tacting with t he ch ip 120a fo r  perform ing t he subse quent wir e - bondingpro ces s.How e v er , the spacer1 3 0 is  u sed for  in creasin g t hethi ckn es s of theprior ch ip -s ta ck edpacka g e struct ur e 1 00 .
A nothe r  prior  chip -sta ck ed pac kage st r uc t u re w it hdiff ere nt -size d ch i pshas bee n disclos ed. Refe rr in g to FI G. 1B, anothe rconvention al  ch ip-sta c k ed packa ge structure 10 include s  a pack age  subs trat e 110, ch ips  120cand 120d,the pl urali ty  of w ires1 4 0,  an dan encapsu l a nt150.Th e pa ckage s ubstrate 110 has p a ds112 thereon.The  siz e of  ch i p1 20c  i s  la r g er than the chi p's 120d.Th e  c hips 120ca nd12 0d arerespect ively provide d with pe ripherall yarra n g edpads 122cand 122d . The chi p  120c is  prov ide d on t he  pa ckage  subst r ate  110whileth e chip  120d  i s provid ed on the chip 120c. Th e chip  120c  is  electric all y  co nnected t o th e packagesub str ate 1 10b y bon ding tw o e n ds of  one of the wi r es  14 0 to  the pads 1 1 2 and  122c  re s pectiv ely.  The chip 120d is electrically c onne c t edtot he p ac kage substrate  11 0i n  similar  m anner. Theencapsul an t  150is the n prov ided on t he packag e su bst rate 110toco v er thech ip s  120cand12 0d and  the w i res1 4 0.
Since the siz e ofc h ip 12 0 d i s sma ll er than chip 's 120c, t he pads 122 c of c hip120cwould n ot  cover edby  the chip1 20d whenthe c hip 120 dis s tac ked on  the c hip 1 20c.  H owe ver, thec o nd i ti on tha t
stacked package_structure 100_comprises a package substrate_110, chip_120a,_chip 120b,_a_spacer 130, a_plurality of wires_140, and an encapsulant_150. The package_substrate_110 is provided with a plurality of pads 112. The chips 120a and 120b_are_respectively provided_with_peripherally_arranged pads 122a and 122b._The chip 120a is provided_on the_package substrate 110 while the chip 120b is_provided_on the chip_120a with a spacer 130 intervened there-between. The chip_120a is electrically connected to the_package substrate 110_by_bonding_two ends of one_of the wires 140 to the_pads 112 and 122a respectively. The_chip 120b is electrically connected to the_package substrate 110 in similar manner._The encapsulant 150 is then_provided on_the package substrate 110 to_cover the chips_120a and_120b and the_wires 140.
Since the pads 122a and_122b are respectively_provided at the peripheral of the_chip_120a and the_chip_120b,_there is_a need to_apply_the spacer_130_to prevent the chip 120b from_directly_contacting with the chip 120a for performing_the subsequent wire-bonding process._However,_the spacer 130 is_used for increasing the thickness_of the prior chip-stacked package structure_100.
Another prior_chip-stacked package_structure with different-sized chips has been disclosed. Referring to FIG. 1B,_another conventional chip-stacked package structure 10_includes a package substrate_110, chips_120c_and 120d, the_plurality_of wires_140, and an encapsulant 150. The package_substrate 110_has pads 112 thereon. The size_of chip 120c is_larger_than the chip's 120d. The chips_120c and 120d are respectively provided_with peripherally arranged pads 122c_and_122d._The chip 120c is provided_on the package substrate 110 while_the chip 120d_is provided on the chip 120c. The_chip_120c is electrically connected to the_package_substrate 110 by bonding two ends_of_one_of the wires 140 to_the pads 112 and 122c respectively._The chip 120d is electrically connected to the package_substrate 110 in_similar manner. The encapsulant 150_is_then_provided on the package substrate 110 to cover the chips_120c and_120d and the_wires 140.
Since the size of chip 120d is smaller than_chip's 120c, the pads 122c of chip_120c would not covered by the chip 120d when the chip_120d is stacked on the chip 120c. However,_the condition that