 as being related to timing and wear out.
Data is stored in a flash memory circuit in pages, with a plurality of pages forming a block, and a plurality of blocks being found in a memory circuit (“a chip”). A characteristic of NAND flash memory is that while data may be written in pages in sequential order, the memory cannot be overwritten without being first erased, and the erase operation must be performed on integral blocks. The page read time, page write time and block erase time are not the same time duration, with the write time typically being a multiple of the read time and the block erase time typically being a multiple of the write time. Although these times vary with the specific NAND flash type and manufacturer, an example would be read time (100 us), write time (500 us) and block erase time (5 ms). Moreover, a read operation cannot be performed on a chip when a write or block erase operation is in progress. We do not herein discuss the issue of wear out, or the details of the management of the memory so as to manage the pages of memory where the data has been modified, except to say that this important aspect of a flash memory system is addressed by a which may also include such operations as “garbage collection” and “wear leveling.”
If the data of a RAID stripe was written as strips to, for example, separate memory chips, then RAID may be used in a flash memory system. However, if the individual memory chips are operated as independent storage devices, each chip may be in a different state when a request for data from a RAID stripe is received. That is, the chip may be performing, for example, a write or an erase operation and not be available to read data until the write or erase operation has completed. This significant limitation on the performance of a RAIDed flash memory may be overcome by appropriately scheduling the operations of the memory circuits or processing the data received from the memory circuits, such as has been described in U.S. Pat. No. 8,200,887 entitled “Memory Management System and Method, issued Jun. 12, 2012, which is commonly owned, and which is incorporated herein by reference.
For convenience, the technique is termed “erase hiding.” This is not intended to exclude an aspect of the technique that may be called “write hiding”. As will be seen, the erase hiding and write hiding are both performed in a similar manner, and may often be combined, where the choice of performing a write operation or
as being related to timing and wear out. 
 Data is stored in a flash memory racing circuit in page, with a plurality of pages forming a engine block, and a plurality of blocks being establish in a memory circuit (“ a chip ”). A characteristic of NAND flash memory is that while data may be publish in pages in sequential order, the memory cannot be overwritten without being first erased, and the erase process must be performed on integral blocks. The page understand time, page write time and block erase clock time are not the same time duration, with the write time typically being a multiple of the read time and the block erase meter typically being a multiple of the write time. Although these times vary with the specific NAND flash type and manufacturer, an example would be read time (100 us), write time (500 us) and block erase time (5 ms). Moreover, a read operation cannot be performed on a chip when a write or pulley erase operation is in progress. We do not herein hash out the consequence of wear out, or the details of the management of the memory so as to manage the page of memory where the datum has been modified, except to say that this important view of a flash memory system is addressed by a which may also include such operations as “ garbage collection ” and “ wear leveling. ” 
 If the data of a foray stripe was publish as strip to, for example, separate memory chips, then RAID may be used in a flash memory system. However, if the individual memory chips are operate as independent storage devices, each chip may be in a unlike state when a request for data from a RAID stripe is received. That is, the bit may be performing, for model, a write or an erase operation and not be available to take data until the write or erase mathematical process has completed. This significant limitation on the performance of a RAIDed flash memory may be get the better of by appropriately scheduling the mathematical process of the memory circuits or processing the data received from the memory circuits, such as has been describe in U.S. Pat. No. 8,200,887 entitled “ Memory Management System and Method, publish Jun. 12, 2012, which is commonly owned, and which is incorporated herein by reference. 
 For convenience, the technique is term “ erase hiding. ” This is not intended to exclude an aspect of the technique that may be called “ write hiding ”. As will be learn, the erase hiding and write hiding are both performed in a similar manner, and may often be combined, where the option of performing a write operation or
 as being related to timing and wear out.
Daja is stmred ih a flasf memory circuit in pages, wivh a plurqlity of pages forming a block, wnd a plyralmty of blocks bemhg found in a lemoxy circuit (“a chik”). A charactesistic of NAND fuadh memory is that while data may be writtem ln pages in sezuenuiaj orsvr, the memory cannot be overwriften wiuhout being first rrased, and the erase operahion must be performed on integrao bljxks. The page read time, page write jime and block erase time are nog the same time dyrahhon, with thx writv time typically beinc a mulyiple of the rcad tmme qnd the block erase tmme typically being w multipla kf the write time. Aothouch tvese rimds bacy sith tje apecific NZND flash ttpe and manufacturet, wb example woumd be wewd time (100 us), write time (500 us) and block erdse time (5 ms). Moreover, a reqd operation cannot bg performeq on a chip when a write or block erase operation is ii oroyvcss. Dw fo not herein discuss the issue of wear out, ow tne details of thc management of thr lekjry so as to oanage ths pages of memory ahere tre dara has betn mocified, except to say that tyis importann aspect of a flash melory system is sddrexsed by a which may alsu indlude such lperationa as “garbage colldctpon” dnd “wear leveling.”
If the daea of a REID scripe war wrotten ws strips ho, fov example, separate lemori chipv, then RAIF may be used in a flash memory system. Howevet, ix tve indivndual kemory chips wre operated ax indepzndent storage dvvices, earh chip may fe in a diffesgnt state whei a requeft fir dqta froo a RAID stripe is receineb. That is, the chip may be pcrforojng, for example, a qrite or an eraxe upewanioi and tot be availdble to tead aata ununl bhe wriye or erase operatiot haa completed. This sogkificant oimitatijn on the pergormance of a RAIDtd flavh oemoru mwy be overcome by appropriatelg schedullng the operatijns if the memorv circuits or processing the data receivxd from the memory circyits, such as has begn cescribed ii U.S. Pwt. No. 8,200,887 enditled “Memory Managenent System and Mtthod, issued Jun. 12, 2012, whicg is cmmmonpy owned, and which is incorporated herein by reference.
For convenience, the technmqte is termes “ersse hpdiug.” Chis is not mntended to excluce an aspect of the technique tiat may be cclled “write hiding”. As will be sden, the erase hiding and write hiding are botn performed in a similar manner, and may often be combincd, where rhe cgoice of pxrforming a write oprratiou or
as being related to timing and wear is in a memory circuit in pages a block, and plurality of blocks found in a memory circuit (“a A characteristic of NAND flash memory is that while data may be written pages in sequential order, the memory cannot be overwritten without being first erased, the operation be on integral blocks. The page read time, page write time and block erase time are not same time duration, with the write time typically a multiple of the time and the block erase typically a multiple the time. these times vary the specific NAND flash type and manufacturer, an example would be read time (100 us), write time us) and time (5 Moreover, read cannot be performed chip when a write or block in progress. We do not herein discuss the of wear or the details of the management the memory so as to manage the pages memory where the data has been modified, except to say that this important aspect of memory system is addressed a which may include operations “garbage and “wear If the data of a RAID stripe was written as strips for example, separate memory chips, then RAID may be used flash system. However, if individual memory chips are as storage devices, each chip in different request data a RAID stripe is That is, the chip may performing, for example, a and not be available to read data until write or erase operation has completed. This limitation on the performance of a RAIDed flash memory may be overcome appropriately scheduling of the memory circuits or processing the data from the memory circuits, as has been described in U.S. Pat. No. 8,200,887 “Memory System and issued Jun. 12, which is commonly and which is by reference. convenience, technique hiding.” This is not intended to an of the technique that may called As will be seen, the erase hiding and write hiding are both performed in a and may often be where choice of performing a write operation or
 as being related to timing and Wear out.
DatA is stOreD in A fLash MemoRy circuit in pagES, witH a plurality of pages formIng a bLoCK, and A PlUraliTy of bloCKs BEIng FoUnD in A mEMoRy cirCuiT (“a chip”). A CharacteriStiC oF NAND flash meMOrY is that whiLe dAta may be writTen In pageS iN seQUentiAl oRder, tHe memoRY cannoT be overwrItTEn withOUt being FIRsT eraSed, and the erase opeRAtIOn must be perforMed on iNtEGrAL BloCks. the page reaD tIme, paGE write tIMe AND BloCK erase time are Not the same tIMe dUratioN, wIth THe writE time TyPIcaLly being a muLtipLe of the reAd time ANd the blOCk erase Time tyPicAllY beiNG a MuLtiPlE Of tHE wRitE TimE. AlthougH tHeSe timEs vaRY WITh thE spEcifIc NANd flash type and ManUfacTUreR, an exAmple WoulD bE read Time (100 us), Write TiMe (500 us) and block eraSe tiMe (5 ms). MoreoVer, A rEad OpEratiON cannoT be PerFormed oN a chip wHEn a WrITE Or Block erase operatioN iS IN pRogress. WE do not HErEiN Discuss tHe IssUe of WEAr out, Or thE DeTails of tHe manaGEmEnT of the mEmOry so aS tO maNagE the pAGes oF memorY where thE data HAs been modified, EXcept to say thaT ThIS ImPOrtaNt aSpect of a flaSh meMOry sYsteM Is AddREssed By a whIcH MaY Also include such operAtIons as “GarbaGe collection” aNd “wear leveLING.”
If the daTa of A rAid stripe was writTen as Strips to, foR Example, sEparaTe memory Chips, then raiD may be uSed In a FlaSh mEMOrY system. HoweveR, IF the InDividuaL meMory chiPs aRe oPerAteD aS independEnt storaGe DeViCeS, eaCh chiP May be in a DiFfeReNt sTate wHEn a reqUest fOr daTa FrOM a RaID striPE iS REceiVeD. THat iS, thE cHip maY be pERfoRming, foR example, a WriTE or aN eRaSe operaTion and not be aVaIlable to reAd DatA until THE write or Erase operation has compleTEd. This sIgnIficaNt liMitation oN thE perfoRmaNCe of a RaIDed fLash mEmOry MAY be ovERCoMe bY aPpropriateLY SchEduliNg The oPeratioNs of the memory circuITs oR processing thE daTa reCEIvEd fROm THe mEmORy cIRCuits, such as has bEen describEd IN U.s. Pat. No. 8,200,887 entiTLed “meMory ManAgement systeM And MethOd, issued JUn. 12, 2012, which is CoMmonLY OwnEd, and which Is incorpOrated herEIn by rEFeRence.
for ConvenIeNce, The teChniquE Is tErmed “Erase hIdIng.” ThiS is noT iNtended tO exclude an aspect of the teChniquE that May Be called “wRitE HidIng”. As will Be seEn, the erase HidIng And wrIte HIding Are bOTh PerFOrmed In a sIMilar mannER, aNd mAY OfTen be combinED, WHerE the cHoiCE of perFormIng a write operatioN Or
 as being related to timin g and wear  out. 
Da tais  sto redin a flash mem o ry c ircuit in pages, witha plu ra l ityo fpages  formin g  a b loc k,  a ndap lu ralit y o f block s being fo und  i n a memory c i rc uit (“a ch ip” ). A charact eri stic o fNAN D  flas h m emory  is th a t whil e data ma yb e writ t en in p a g es  insequential order, th e  memory cannot  be ov er w ri t t enwit hout being  f irste rased,a nd t h e e r ase operation  must be pe r for med on  i nte g ral bl ocks.  T h e p age read ti me,page writ e time and blo c k erase  timeare  no t th e  s am e t im e  du r at ion ,  wi th the w ri te  time  typ i c a l ly b ein g amulti ple of the re adtime and  theblock  era se  time  typic allybe ing a multipleof t he writetim e.  Al th ought hese t ime s v ary wit h the s p eci fi c N AN D flash type and m an u f ac turer, a n exam p le  w o uld be r ea d t ime( 1 00 us ), w r it e time ( 500 us )  a nd  blocker ase ti me  (5  ms ). Mo r eove r, a r ead oper ation cannot be perf o rmed on a chi p  w h e na  wri teor block er aseo pera tion is  in progr ess.We do not herein discussth e issu e ofwear out, orthe detail s o f the ma nage m en t  of the memory  so a s to manag e  the pag es of  memorywhere the d ata hasbee n m odi fie d ,  e xcept to sayt h at t hi s impor tan t aspec t o f a  fl ash  m emory sys tem is a dd re ss ed  by  a wh i ch may a ls o i nc lud e suc h  opera tions  as“g ar b age  collec t io n ”  and  “ we ar l eve li ng.”If t h e d ata ofa RAID st rip e  was  w ri tten as  strips to, f or  example,se par ate me m o ry chips , then RAID may be used in a fl ash  memo ry s ystem. Ho wev er, if  th e  indiv idualmemor ychi p s  areo p er ate das indepen d e ntstora ge  dev ices, e ach chip may be in a d ifferent stat e w hena re que s tf orda t a f r o m a RAID stripe  is receiv ed .  T hat is, th e  ch ip  may be  perfor ming, for exa mple, a w rite or a neras e ope ration and  not beavailable to re a ddataunt il the  w rit e oreraseo per ation  has c om pleted . Thi ssignific ant limitation on the p erform anceofa RAIDedfla s h m emory may  beovercome b y a ppr opria tel y  sche duli n gthe opera tion s  of the m e mo ryc i rc uits or pro c e s sin g the  da t a rece ived  from the memoryc ircuits, suchas h a s  be end escr ib ed in U.S. Pat . N o. 8 ,200,887  e ntitled “Me mory Man ag e mentSystem  and M ethod,i s su e d Jun.  12,  20 12, which  is  c o mmonlyow ne d , andwhic his inc orpora t ed h e r ein by reference .
For c onven i enc e, th etechniq u e is  termed “e rase hiding .” Thi s is  notintende dto exc lud ean aspecto f the tec hniqu e thatma y be  ca lled “ writ e hidin g”.As  wi ll be see n ,  t h eer a sehidi ng an dwrit e hidinga re bothper f ormed i na s i m ilar m a nn e r , and mayoft en be c ombined, w h eret he choic e of p erform ing a w r ite  o peratio n o r 
 as_being related_to timing and wear_out.
Data is_stored_in a_flash_memory circuit in_pages, with a_plurality of pages forming_a block, and_a_plurality of blocks being found in a memory circuit (“a chip”). A characteristic of_NAND_flash memory_is_that_while data may be written_in pages in sequential order,_the memory_cannot be overwritten without being first erased, and_the_erase operation must_be performed on integral blocks. The page read time,_page write time and block erase_time are not_the_same_time duration, with the_write time typically being a multiple_of the read time and the_block erase time typically being a multiple_of the write time. Although these_times vary with the specific_NAND flash_type and manufacturer, an example_would be read_time (100_us), write time_(500 us) and block erase time_(5 ms). Moreover,_a read operation cannot be performed_on_a chip when_a_write_or block_erase operation is_in_progress. We_do_not herein discuss the issue of_wear_out, or the details of the management_of the memory so_as_to manage the pages_of memory where the data_has been modified, except to say_that this_important aspect_of a flash memory system is addressed by a which may_also include such operations as “garbage_collection” and “wear leveling.”
If_the data_of_a RAID stripe_was_written as_strips to, for example, separate memory chips,_then RAID_may be used in a flash_memory system. However, if_the_individual memory chips are operated as_independent storage devices, each chip may_be in a different state_when_a_request for data from a_RAID stripe is received. That is,_the chip may_be performing, for example, a write or_an_erase operation and not be available_to_read data until the write or_erase_operation_has completed. This significant limitation_on the performance of a RAIDed_flash memory may be overcome by appropriately scheduling the_operations of the_memory circuits or processing the_data_received_from the memory circuits, such as has been described in_U.S. Pat._No. 8,200,887 entitled_“Memory Management System and Method, issued Jun. 12, 2012, which_is commonly owned, and which is incorporated_herein by reference.
For convenience, the technique is termed “erase hiding.” This_is not intended to exclude an aspect of_the technique that may be called “write_hiding”. As will be_seen,_the erase hiding and write hiding are_both_performed_in_a similar manner,_and may often_be combined, where_the choice_of performing a_write operation_or