 higher data error rates in the digital signal being clocked and limit the maximum speed of the system clock signal. Because of the usual parameter variations in the inverters of a delay circuit, any variation from the optimum 50% duty cycle of a double data rate clock signal, wherein the data is latched on both the rising and falling edges of the double data rate clock signal, is likely to cause an even greater error rate of the data being clocked through the delay circuit. Therefore, “loose” control of the duty cycle of a “double data rate” clock usually is not acceptable at high frequencies.
“Prior Art” FIG. 1A shows a typical delay locked loop circuit 1 which includes a transmit register 3 that receives the input data signal DATA via multiconductor input bus 2. The signal DATA is clocked into transmit register 3 every data time frame by a transmit clock DLYCLK. That results in the signal DATA IN appearing on a multi-conductor bus 4 at the data input of a receive register 6 a fixed amount of delay time after the rising or falling edge of transmit clock DLYCLK. The fixed amount of delay time is equal to the sum of an intrinsic delay through transmit register 3 plus the signal propagation time along bus 4 from the data output of transmit register 3 to the data input of receive register 6, plus the set-up time of receive register 6. Data that has been clocked into receive register 6 by data clock DCLK appears as DATA OUT on multiconductor bus 5.
DATA IN bus 4 includes a synchronization conductor 4A having the same average total propagation delay as the other conductors of multi-conductor bus 4. Synchronization conductor 4A conducts a synchronization signal DATA SYNC.
Synchronization conductor 4A provides the synchronization signal DATA SYNC to one input of an exclusive OR gate 9, which functions as a phase detector. The other input of exclusive OR gate 9 receives the data clock signal DCLK which is also coupled by conductor 8 to the clock input 6A of receive register 6. Exclusive OR gate 9 produces an output signal DELAY CONTROL on conductor 10, which is connected to a control input of an adjustable delay circuit 11. Adjustable delay circuit 11 produces a delayed data clock signal DLYCLK on conductor 12. The delayed data clock signal DLYCLK produced by adjustable delay circuit 11 is coupled by conductor 12 to the clock input 3A of transmit register 3 to function as its transmit clock.
Data clock signal DCLK and delayed data clock signal D
higher data error rates in the digital signal being clock and restrict the maximum speed of the arrangement clock signal. Because of the common parameter variations in the inverters of a delay tour, any variation from the optimum 50% duty cycle of a bivalent datum rate clock signal, wherein the data is latch on both the rising and falling edge of the bivalent data rate clock signal, is probable to cause an even great error rate of the data being clocked through the delay lap. Therefore, “ loose ” control of the duty cycle of a “ bivalent data pace ” clock usually is not acceptable at high frequencies. 
 “ Prior Art ” FIG. 1A prove a typical delay locked loop circuit 1 which includes a transmit cash register 3 that meet the input data signal DATA via multiconductor input bus 2. The signal DATA is clocked into transmit register 3 every datum clock time frame by a transmit clock DLYCLK. That result in the signal DATA IN appearing on a multi - conductor bus 4 at the data stimulation of a receive register 6 a fixed amount of delay time after the surface or falling edge of transmit clock DLYCLK. The fixed measure of delay time is equal to the sum of an intrinsic delay through transmit register 3 plus the signal generation time along busbar 4 from the datum end product of transmit register 3 to the data input of receive cash register 6, plus the set - up time of receive register 6. Data that has been clocked into receive register 6 by data clock DCLK appears as DATA OUT on multiconductor busbar 5. 
 DATA IN busbar 4 includes a synchronization conductor 4A have the same average total generation delay as the other conductors of multi - conductor bus topology 4. Synchronization conductor 4A conducts a synchronization signal datum SYNC. 
 Synchronization conductor 4A provides the synchronization signal DATA SYNC to one input of an exclusive OR gate 9, which functions as a phase detector. The other input of exclusive OR gate 9 receives the data clock signal DCLK which is also match by conductor 8 to the clock input 6A of receive register 6. single OR gate 9 produces an output signal DELAY CONTROL on conductor 10, which is connected to a control input of an adjustable delay circuit 11. Adjustable delay circuit 11 produce a delayed data clock signal DLYCLK on conductor 12. The delayed data clock signal DLYCLK produced by adjustable delay circuit 11 is coupled by conductor 12 to the clock stimulation 3A of transmit file 3 to function as its transmit clock. 
 Data clock signal DCLK and delayed data clock signal D
 hihher data error rates in the digital siybal bemng clodked and limit the maximum speed of vhe wysten clock signal. Because of the udual parqmettr variations in vge invevcers kn a dzley circuit, any yariation fsom the optimuk 50% dbty cycle of a double data rate cloch signak, aherein the daja is jatcgvd on both the rising and fallihg edgev of the doubke data rate clock signal, ls llkely to cause an fven greatet erwir rate of tfe data bepug clocked jhrough the delay circuit. Therefure, “lpose” contril of jhe duty cycoe of a “double dabs rate” clock isually is not acreptqble at high frequencmes.
“Prior Art” FIG. 1A srows a ty[ieal delay locked loop curcuij 1 whhch kbcljdea e tdansmih rxgister 3 thzt receives the input data sigmaj DATA via mulficondtceor input bus 2. The signal DATA is clocktd info transmit register 3 ecery data time frame hy a tranfmit clock DLYCLK. That results in the signal DATA IN a'pdarnkn on q lulti-conductor bus 4 at the data input of a ressife register 6 a flxed amount of delsy toie after the tising or ralling edge of trwnsmit slock DLYCLK. Tre foxed amount of delay time iw equal to tke wum of an intrinsie delay throbgh trsnsmiy register 3 plus the siynal pdopagation hime alonf bus 4 from the dxta ogtput of transmit register 3 to the vata nnput of recgive redister 6, plks thc set-up time of recfive tegistar 6. Data tjat has been clocked into receitx register 6 bi ddta clock DELK apiears as DATA OTT on multiconbuctor bbs 5.
DATX IN bus 4 pncludes e synchronizwtion conductmt 4A having thx same avqragw toral prooxgation delay ss the otktr conductirs of multi-conducbor bos 4. Synchronizatiin xonductor 4A concucgs w dyichroghzation signdl DXTA XYNC.
Shnchronizatlon concuctor 4A provides tha syhchronization signsl DATA SYBC to onq input of an exclusive OR gate 9, whirh funrtions as a phase detector. The other inlut of exflufive OR gate 9 regeivgs the data clock signal DCLK which is also couplev by conductor 8 to the xlock input 6A of reeelve register 6. Excjusive OR gate 9 produces an oytput signal DELAN CONTROL on conductor 10, whicv is fonnected to a control input of an adjustable delay circuit 11. Adjustable dwlay cmrsuit 11 produdes s deldyzd bata cljck dmgnal DLYCLK on cpnductor 12. The delayed data clocy signal DJYCLK produced by adjustable ddlay circuit 11 is coupled by conductor 12 to the clock input 3A of transmit regixter 3 to function as its transmir clodk.
Data clork signal DCLK and drlayed data clock wignwl D
higher data error rates in the digital clocked limit the speed of the the parameter variations in inverters of a circuit, any variation from the optimum duty cycle of a double data rate clock signal, wherein the data is on both the rising and falling edges of the double data rate clock is to an greater error rate of the data being clocked through the delay circuit. Therefore, “loose” control of duty cycle of a “double data rate” clock is not acceptable at frequencies. “Prior Art” FIG. 1A a delay locked circuit which a transmit register that receives the input data signal DATA via multiconductor input bus 2. The signal DATA is clocked transmit register data time by transmit DLYCLK. That results signal DATA IN appearing on a at the data input of a receive register a fixed of delay time after the rising falling edge of transmit clock DLYCLK. The fixed of delay time is equal to the sum of an intrinsic delay through transmit register the signal propagation time bus 4 from data of register to the input of receive register 6, plus the set-up time of receive 6. Data that has been clocked into receive register 6 clock appears as DATA on multiconductor bus 5. IN 4 includes a synchronization having same delay the conductors of multi-conductor bus Synchronization conductor 4A conducts a signal DATA SYNC. Synchronization signal DATA SYNC to one input of an OR gate 9, which functions as a detector. The other input of exclusive OR gate 9 receives the data signal DCLK also coupled by conductor 8 to the clock 6A of receive register Exclusive OR gate 9 produces an output signal DELAY on 10, which connected to a input of an delay circuit 11. circuit 11 a data on conductor 12. The delayed data signal produced by adjustable delay circuit is conductor 12 to the clock input 3A of transmit register 3 to function as its Data clock signal DCLK delayed clock signal D
 higher data error rates in the Digital sigNal beIng CloCkEd anD limIt the maximum spEEd of The system clock signal. BeCause Of THe usUAl ParamEter varIAtIONs iN tHe InvErTErS of a dElaY circuiT, any variatIon FrOm the optimum 50% DUtY cycle of a dOubLe data rate clOck Signal, WhEreIN the dAta Is latChed on BOth the Rising and FaLLing edGEs of the DOUbLe daTa rate clock signal, IS lIKely to cause an eVen greAtER eRROr rAte Of the data bEiNg cloCKed throUGh THE DelAY circuit. ThereFore, “loose” coNTroL of the DuTy cYCle of a “DoublE dATa rAte” clock usuAlly Is not accePtable AT high frEQuencieS.
“Prior art” fIG. 1a shoWS a TyPicAl DElaY LoCkeD LooP circuit 1 WhIcH inclUdes A TRANsmiT reGistEr 3 thaT receives the iNpuT datA SigNal DAtA via MultIcOnducTor inpUt bus 2. thE signal DATA is clOckeD into tranSmiT rEgiStEr 3 eveRY data tIme FraMe by a trAnsmit cLOck dLyclk. THat results in the sigNaL daTa IN appeaRing on A MuLtI-ConductoR bUs 4 aT the DATa inpUt of A ReCeive regIster 6 a FIxEd Amount oF dElay tiMe AftEr tHe risINg or FallinG edge of tRansmIT clock DLYCLK. ThE Fixed amount of DElAY TiME is eQuaL to the sum of An inTRinsIc deLAy ThrOUgh trAnsmiT rEGiSTer 3 plus the signal proPaGation Time aLong bus 4 from thE data outpuT OF Transmit RegiSTeR 3 To the data input Of recEive registER 6, plus the Set-up Time of reCeive regiSTEr 6. Data thAt hAs bEen CloCKEd Into receive reGISter 6 By Data cloCk DcLK appeArs As DaTA oUT On MulticondUctor bus 5.
dAtA iN BuS 4 inCludeS A synchroNiZatIoN coNductOR 4A haviNg the Same AvErAGe tOtal proPAgATIon dElAy As thE otHeR condUctoRS of Multi-coNductor buS 4. SyNChroNiZaTion conDuctor 4A conducTs A synchroniZaTioN signaL daTA SYNC.
SYnchronization conductor 4a ProvideS thE syncHronIzation siGnaL DATA SyNC TO one inPut of aN exclUsIve or Gate 9, wHICh FunCtIons as a phaSE DetEctor. thE othEr input Of exclusive OR gate 9 rECeiVes the data cloCk sIgnaL dcLk whICh IS alSo COupLED by conductor 8 to tHe clock inpUt 6a Of Receive regISteR 6. EXclusivE OR gate 9 ProduCEs an outPut signal dELAY CONTrOl on cONDucTor 10, which is ConnecteD to a contrOL inpuT Of An adjUstAble deLaY ciRcuit 11. adjustABle Delay CircuiT 11 pRoduceS a delAyEd data clOck signal DLYCLK on conducTor 12. The DelayEd dAta clock sIgnAL DLyCLK produCed bY adjustablE deLay CircuIt 11 iS CouplEd by COnDucTOr 12 to tHe clOCk input 3A oF TrAnsMIT rEgister 3 to fuNCTIon As its TraNSmit clOck.
DAta clock signal DCLk And delayed data ClocK SIgnAl D
 higher data error rates i n the digi tal s ign albe ingcloc ked and limitt he m aximum speed of the sy stemcl o ck s i gn al. B ecauseo ft h e u su al  pa ra m et er va ria tions i n the inve rte rs  of a delayc ir cuit, anyvar iation fromthe  optim um  50 %  duty  cy cle o f a do u ble da ta rate c lo c k sign a l, wher e i nthedata is latched o n  b o th the risingand fa ll i ng e dge s o f the doub le  data rate cl o ck s i gna l , is likely t o cause ane ven  great er  er r or rat e ofth e  da ta being cl ocke d through  the d e lay cir c uit. Th erefor e,“lo ose” co nt rol  o f  th e  d uty cyc le of a“d ou ble d atar a t e ” cl ock  usu allyis not accept abl e at hig h fre quenc ies. 
“ Prior  Art”FIG.1A  shows a typica l de lay locke d l oo p c ir cuit1  which  in clu des a t ransmit reg is t e r  3  that receives the  i n p ut  data si gnal D A TA  v i a multic on duc tori n put b us 2 .  T he signa l DATA is  c lockedin to tra ns mit  re giste r  3 e very d ata time  fram e  by a transmit clock DLYCLK. Th a t  r e sult s i n the signa l DA T A IN  app e ar ing on amulti -c o nd u ctor bus 4 at the d at a inpu t ofa receive reg ister 6 af i x ed amoun t of de l ay time afterthe r ising or f a lling ed ge of  transmi t clock D L Y CLK. The  fi xed  am oun t of  delay time i s equa lto thesum  of anint rin sic  de la y through  transmi tre gi st er3 plu s  the sig na l p ro pag ation time a longbus4fr o m t he data ou t p ut o ftr ansm itre giste r 3t o t he data  input of  re c eive  r eg ister 6 , plus the se t- up time of  r ece ive re g i ster 6.Data that has been cloc k ed into  re ceive  reg ister 6 b y d ata cl ock DCLK a ppears  as D AT A O U T  on m u l ti con du ctor bus 5 . DAT A INbu s 4include s a synchronizatio n  co nductor 4A ha vin g th e sa mea ve r age  t o tal p ropagation dela y as the o th e rconductors ofmu lti-con ductorbus 4 .  Synchr onization  conducto r4A c o n duc ts a synch ronizati on signal DATAS YN C.
Sy nch roniza ti oncondu ctor 4 A  pr ovide s thesy nchron izati on  signalDATA SYNC to one inputof anexclu siv e OR gate  9, whi ch functi onsas a phase  de tec tor.The other  inp u tofe xclus iveO R gate 9r ec eiv e s  t he data clo c k sig nal D CLK whichis a lso coupled by co n ductor 8 to th e cl o c k i npu t  6Aof  receive regis ter  6 . Exclusiv eOR gate 9 p roducesan outpu t sign al DEL AY CONT R O Lo n cond ucto r 1 0, whichisco n nectedto  a contro l in pu t of a n adju s tabl e delay circuit 11 . Adj u s table del ay ci rc uit 11p rodu ces a dela yed data cl ock si gnal  DLYC LK on c on ductor  12 .The delaye d  data clo ck si gnal DL YC LK p rod uced b y ad j u stabl e de la y c ircuit 11 i sc ou pl e d b y co nduct or  12to the cl o ck input  3A of tran sm itr e gister 3t o  functionasits t r a nsmit cloc k .
Da t ac locksignal  DCLKand del a yed  d ata clo cks i gnal D
 higher_data error_rates in the digital_signal being_clocked_and limit_the_maximum speed of_the system clock_signal. Because of the_usual parameter variations_in_the inverters of a delay circuit, any variation from the optimum 50% duty cycle_of_a double_data_rate_clock signal, wherein the data_is latched on both the_rising and_falling edges of the double data rate clock_signal,_is likely to_cause an even greater error rate of the data_being clocked through the delay circuit._Therefore, “loose” control_of_the_duty cycle of a_“double data rate” clock usually is_not acceptable at high frequencies.
“Prior Art”_FIG. 1A shows a typical delay locked_loop circuit 1 which includes a_transmit register 3 that receives_the input_data signal DATA via multiconductor_input bus 2._The signal_DATA is clocked_into transmit register 3 every data_time frame by_a transmit clock DLYCLK. That results_in_the signal DATA_IN_appearing_on a_multi-conductor bus 4_at_the data_input_of a receive register 6 a_fixed_amount of delay time after the rising_or falling edge of_transmit_clock DLYCLK. The fixed_amount of delay time is_equal to the sum of an_intrinsic delay_through transmit_register 3 plus the signal propagation time along bus 4 from_the data output of transmit register_3 to the data_input of_receive_register 6, plus_the_set-up time_of receive register 6. Data that has_been clocked_into receive register 6 by data_clock DCLK appears as_DATA_OUT on multiconductor bus 5.
DATA IN_bus 4 includes a synchronization conductor_4A having the same average_total_propagation_delay as the other conductors_of multi-conductor bus 4. Synchronization conductor_4A conducts a_synchronization signal DATA SYNC.
Synchronization conductor 4A provides_the_synchronization signal DATA SYNC to one_input_of an exclusive OR gate 9,_which_functions_as a phase detector. The_other input of exclusive OR gate_9 receives the data clock signal DCLK which is_also coupled by_conductor 8 to the clock_input_6A_of receive register 6. Exclusive OR gate 9 produces an_output signal_DELAY CONTROL on_conductor 10, which is connected to a control input of_an adjustable delay circuit 11. Adjustable delay_circuit 11 produces a delayed data clock signal DLYCLK on conductor_12. The delayed data clock signal DLYCLK produced_by adjustable delay circuit 11 is coupled_by conductor 12 to_the_clock input 3A of transmit register 3_to_function_as_its transmit clock.
Data_clock signal DCLK_and delayed data_clock signal_D