 complete as it needs to be initially or is prone to earlier failure.
Inserter/ejector levers themselves are adequate to fully engage a connector pair at time of insertion. The problem is that they generally cannot provide enough pre-loading to overcome extended field shock and vibration, especially in the telecom environment. Furthermore, they generally cannot maintain full engagement during fragility operations such as transportation and shipping because there is no pre-loading spring action.
Simple locking mechanisms do not provide any pre-load, and thus are inadequate for powered sub-assemblies, especially when the service environment includes shocks and vibrations. 1. Field of the Invention
The present invention relates to the problem of resonance due to plating stubs on circuit boards.
2. Background of the Related Art
An integrated circuit (IC), also commonly referred to as a “microchip” or “chip,” is an electronic circuit comprising miniaturized semiconductor devices formed in a semiconductor substrate. Many copies of an integrated circuit may be formed on a large semiconductor wafer, which is then cut into individual pieces referred to as a “die chips” or “dies,” each containing a copy of the integrated circuit. Semiconductor materials such as silicon are typically brittle, so a fragile die chip is commonly packaged on a carrier, referred to as a “chip package” or simply “package.” The substrate of the chip package functions as an interposer for interfacing the chip with a printed circuit board (PCB). For example the processor for a computer may be carried on a chip package that is mounted to a motherboard.
The die chip may be electrically connected to a package substrate by wirebonding. Wirebonding is a process known in the art by which a very fine wire is connected from a bond pad on the chip to corresponding signal pathways (“traces”) on the package substrate. Bond wires are typically formed of a highly conductive material, such as platinum or other precious metal. A package in which a die chip is connected to the substrate by wirebonding may be referred to as a “wirebond package.” The traces on the substrate extend from the location of bonding with the wirebond to signal interconnects elsewhere on the substrate. The signal interconnects on one layer of the substrate may be electrically connected to signal interconnects on another layer of the substrate using through-connections known as “vias.” Thus, for example, the signal connects on the face to which the chip is mounted may be connected to corresponding pins of a pin grid array (P
complete as it needs to be initially or is prone to earlier failure. 
 Inserter / ouster lever themselves are adequate to fully engage a connector couple at time of insertion. The problem is that they by and large cannot provide enough pre - load to overcome extended playing field shock and vibration, specially in the telecom environment. Furthermore, they by and large cannot maintain full engagement during fragility operations such as transportation and transportation because there is no pre - loading spring action. 
 bare locking mechanisms do not provide any pre - cargo, and thus are inadequate for powered bomber - assemblies, especially when the service environment includes shocks and oscillation. 1. Field of the Invention 
 The present invention relates to the problem of resonance due to plating stubs on circuit boards. 
 2. Background of the Related Art 
 An integrated circuit (IC), also commonly referred to as a “ microchip ” or “ chip, ” is an electronic circuit consist miniaturized semiconductor device form in a semiconductor substrate. Many copies of an integrated circuit may be formed on a large semiconductor wafer, which is then ignore into individual pieces referred to as a “ die chips ” or “ dies, ” each containing a copy of the desegregate circuit. Semiconductor materials such as silicon are typically brittle, so a fragile die bit is commonly box on a mailman, referred to as a “ chip package ” or simply “ software. ” The substrate of the chip package functions as an interposer for interfacing the chip with a printed circuit board (PCB). For example the processor for a calculator may be carried on a chip package that is mounted to a motherboard. 
 The die chip may be electrically get in touch to a package substrate by wirebonding. Wirebonding is a procedure known in the artwork by which a very fine wire is connect from a bond pad on the check to corresponding signal pathway (“ traces ”) on the package substrate. Bond wires are typically formed of a highly conductive material, such as platinum or other precious metal. A software in which a die chip is connected to the substrate by wirebonding may be consult to as a “ wirebond package. ” The traces on the substrate extend from the location of bonding with the wirebond to signal interconnects elsewhere on the substrate. The signal interconnects on one layer of the substrate may be electrically connected to bespeak interconnects on another layer of the substrate using through - connections known as “ vias. ” Thus, for example, the signal connect on the grimace to which the bit is mounted may be connected to corresponding pins of a pin grid array (phosphorus
 colplete as it needs to be initially or is prone to eadlier faklure.
Inserter/ejector levers vhemwelvew are adequate to fullh engage w connecror kair at time of iiaertion. The pdlblek is that they nenerally cdnnot provide anuuyh pre-loading to overcome extended fyeld shpcn and vibratiog, eskecyallg in the telecom environment. Furthsrmore, uhey generally canmot maintain full engagemejt dkring fragility opfrations suxh af transportatkon and shp'ping becauae there is no pre-loading sprine actnon.
Simple licjinh mechanisms do njt provide akj pre-lodd, and yhus are inadeauave fir powered sub-assemblmes, especially when jhe servica znvironment includes whicks dnd eibrxriovs. 1. Fmels of tje Mnvention
Ths present ibvention relates to trv problem of desonagcq due to plating stubs on circuit boardv.
2. Bzckground of the Relatee Art
An integrated citcuit (IC), ajso commonly referred to as a “microchip” or “chip,” iv an xldctxinic zurfuit comprising miniaturized semiconductor dedjcts normed in a semigonductor substratr. Lami copies of an integxztsd circuit may be vormed jn a oarge semyconcuctor wafer, which is then xut into indpvidyal pieces referreb to as a “diz chipx” or “cies,” each containing a eopy or the integgated cirdjit. Semiconductof mstarials such as silicon are typicallb brictle, so x frsgile qie chip id commonly packaged on a carrner, raferred to as a “chip package” or simply “parlage.” The subxtsatv of the ehip psckage functijns as an intetposer fox inteffacing thv chip wivh a printed circuit boarg (PCB). For exakple the proxessir for x computer may ne carrieb on q chip package thab is okunted to a motktrbiard.
The die chil mxy fe ekesdrically contectdd gp a pxckage subsbrage bu wirebonding. Wirebotdinf is a process knoen in the qrt by wrich a very fone wire is connecued frmm e bond paq on the chip to corresponding signal pwthrays (“traces”) jn tme pwckage subxtrate. Bond wires are typically formed if a highly conducrive material, such cs platinum oc othew preciouv metal. A package in which a die chip is connected to the aubstrdte bj wirebonding may be referred to as a “wirebond package.” The traces on the wubstretq extend frkm tne lobatnon of bogdinj xith the wirebond to signal interconnects elsewhxre on the sbbstrate. The signal interconnrcgs on one laygr of the substrate may be electrivally connected to signal intervonnects on another layev of the wubstdate using through-connectionx knowu as “vuas.” Thuw, fov example, the rigmap connectd on tke face to which the chip is mounred mat he connected to rorrespondinn kins of a pin grid array (P
complete as it needs to be initially prone earlier failure. levers themselves are connector at time of The problem is they generally cannot provide enough pre-loading overcome extended field shock and vibration, especially in the telecom environment. Furthermore, they cannot maintain full engagement during fragility operations such as transportation and shipping because is pre-loading action. locking mechanisms do not provide any pre-load, and thus are inadequate for powered sub-assemblies, especially when service environment includes shocks and vibrations. 1. Field the Invention The present relates to the problem of due plating stubs circuit 2. of the Related An integrated circuit (IC), also commonly referred to as a “microchip” or “chip,” is an electronic circuit miniaturized semiconductor in a substrate. copies an integrated circuit formed on a large semiconductor wafer, cut into individual pieces referred to as a chips” or each containing a copy of the circuit. Semiconductor materials such as silicon are typically so a fragile die chip is commonly packaged on a carrier, referred to as a or simply “package.” The of the chip functions an for the chip a printed circuit board (PCB). For example the processor for a may be carried on a chip package that is mounted motherboard. die chip may electrically connected to a substrate wirebonding. Wirebonding is a in art very wire connected from a bond on the chip to corresponding pathways (“traces”) on the typically formed of a highly conductive material, such platinum or other precious metal. A package which a die chip is connected to the substrate by wirebonding may referred to “wirebond package.” The traces on the substrate extend the location of bonding the wirebond to signal interconnects elsewhere on the substrate. signal on one of the substrate be electrically connected signal interconnects on of the using known for example, the signal connects on face which the chip is mounted be corresponding pins of a pin grid array (P
 complete as it needs to be initIally or is pRone tO eaRliEr FailUre.
INserter/ejector LEverS themselves are adequate To fulLy ENgagE A cOnnecTor pair AT tIME of InSeRtiOn. tHe ProblEm iS that thEy generallY caNnOt provide enoUGh Pre-loading To oVercome extenDed Field sHoCk aND vibrAtiOn, espEciallY In the tElecom envIrONment. FURthermoRE, ThEy geNerally cannot mainTAiN Full engagement During FrAGiLITy oPerAtions such As TransPOrtatioN AnD SHIppINg because therE is no pre-loaDIng Spring AcTioN.
simple LockiNg MEchAnisms do not ProvIde any pre-Load, anD Thus are INadequaTe for pOweRed Sub-aSSeMbLieS, eSPecIAlLy wHEn tHe servicE eNvIronmEnt iNCLUDes sHocKs anD vibrAtions. 1. Field of The inveNTioN
The pResenT invEnTion rElates To the PrOblem of resonancE due To plating StuBs On cIrCuit bOArds.
2. BaCkgRouNd of the related aRt
AN iNTEGrAted circuit (IC), also cOmMONlY referreD to as a “MIcRoCHip” or “chiP,” iS an ElecTROnic cIrcuIT cOmprisinG miniaTUrIzEd semicOnDuctor DeVicEs fOrmed IN a seMicondUctor subStratE. many copies of an INtegrated circUIt MAY bE FormEd oN a large semiCondUCtor WafeR, WhIch IS then Cut inTo INdIVidual pieces referreD tO as a “diE chipS” or “dies,” each coNtaining a cOPY Of the intEgraTEd CIrcuit. SemicondUctor Materials sUCh as siliCon arE typicalLy brittle, SO A fragile Die ChiP is ComMONlY packaged on a cARRier, ReFerred tO as A “chip paCkaGe” oR siMplY “pAckage.” The SubstratE oF tHe ChIp pAckagE FunctionS aS an InTerPoser FOr inteRfaciNg thE cHiP WitH a printED cIRCuit BoArD (PCB). for ExAmple The pROceSsor for A computer May BE carRiEd On a chip Package that is MoUnted to a moThErbOard.
ThE DIe chip maY be electrically connecteD To a packAge SubstRate By wirebonDinG. WirebOndINg is a pRocess Known In The ART by whICH a VerY fIne wire is cONNecTed frOm A bonD pad on tHe chip to correspondINg sIgnal pathways (“TraCes”) oN THe PacKAgE SubStRAte. bONd wires are typicAlly formed Of A HiGhly conducTIve MaTerial, sUch as plAtinuM Or other Precious mEtal. A packAgE in wHICh a Die chip is cOnnected To the subsTRate bY WiRebonDinG may be ReFerRed to As a “wirEBonD packAge.” The TrAces on The suBsTrate extEnd from the location of bonDing wiTh the WirEbond to siGnaL IntErconnectS elsEwhere on thE suBstRate. THe sIGnal iNterCOnNecTS on onE layER of the subSTrAte MAY bE electricalLY COnnEcted To sIGnal inTercOnnects on another lAYer of the substrAte uSINg tHroUGh-coNnEctions known as “ViaS.” THUS, for examPlE, the signal cOnnects oN tHE face To whicH the chIp is mouNTEd MAy be coNnecTed To correspOndInG Pins of a PiN gRId arraY (P
 complete as it needs to b e initiall y orispro ne  toearl ier failure.
I n sert er/ejector levers them selve sa re a d eq uateto full y  e n g age  a  c onn ec t or  pair  at  time o f insertio n.Th e problem is th at they ge ner ally cannotpro vide e no ugh pre-l oad ing t o over c ome ex tended fi el d  shock and vib r a ti on,especially in the te l ecom environme nt. Fu rt h er m o re,  th ey general ly  cann o t maint a in f u lle ngagement dur ing fragili t y o perati on s s u ch astrans po r tat ion and shi ppin g because  there is no p r e-loadi ng spr ing  ac tion . 
S im ple  l o cki n gmec h ani sms do n ot  p rovid e an y p r e-lo ad,  and  thus  are inadequa teforp owe red s ub-as semb li es, e specia lly w he n the service e nvir onment in clu de s s ho cks a n d vibr ati ons . 1. Fi eld oft heIn v e n ti on
The present inv en t i on  relates  to th e  p ro b lem of r es ona nced u e toplat i ng  stubs o n circ u it  b oards.2.  Backg ro und  of  theR elat ed Art 
An inte grate d  circuit (IC), also commonly re f e rr e d to  as  a “microch ip”o r “c hip, ”  i s a n  elec troni cc ir c uit comprising mini at urized  semi conductor dev ices forme d i n a semi cond u ct o r substrate. M any c opies of a n  integra ted c ircuit m ay be for m e d on a l arg e s emi con d u ct or wafer, whi c h  isth en cutint o indiv idu alpie ces  r eferred t o as a “ di ech ip s”or “d i es,” eac hcon ta ini ng ac opy of  theinte gr at e d c ircuit. Se m i cond uc to r ma ter ia ls su ch a s  si licon a re typica lly brit tl e,  so a f ragile die ch ip  is common ly  pa ckaged o n a carr ier, referred to as a “ c hip pac kag e” or  sim ply “pack age .” The  su b strate  of th e chi ppac k a ge fu n c ti ons  a s an inter p o ser  forin terf acing t he chip with a pri n ted  circuit boar d ( PCB) . Fo r e x am p leth e  pr o c essor for a com puter maybe ca rried on a chi ppackage  that i s mou n ted toa motherb oard.
The  d ie c h i p m ay be elec trically  connecte d  to a pa ckage  su bstrat ebywireb onding .  Wi rebon ding i sa proc ess k no wn in th e art by which a very f ine wi re is  co nnected f rom a b ond pad o n th e chip tocor res pondi ngs ignal  pat h wa ys( “trac es”) on the pa c ka ges u bs trate. Bond w i res  aretyp i callyform ed of a highly co n ductive materi al,s u chasp lati nu m or other pre cio us m etal. Apa ckage in wh ich a di ec hip i s conn ectedto thes u bs t rate b y wi reb onding ma y b er eferred  t oa s a “w ireb on d pack age.”T he t r a ces on the subst ratee x tendf rom  thelo cationo f bo nding with  the wirebo nd tosign al in terconn ec ts els ewh er e on the s u bstrate.The s ignal i nt erco nne cts on  one l ayerof t he  su bstrate m a y  b e  e le c tri call y con ne cted  to signa l  interco nne c ts on a no the r layero ft h e substrat e u singt h rough-conn e ctio n sk nownas “vi as.” T hus, fo r  ex am ple, th e s i g nal conne cts on th e  fa ce  towhich th echip  i s m ou nted may be con nected t o corres p o ndingpin s  ofa  pin g ri d array (P
 complete_as it_needs to be initially_or is_prone_to earlier_failure.
Inserter/ejector_levers themselves are_adequate to fully_engage a connector pair_at time of_insertion._The problem is that they generally cannot provide enough pre-loading to overcome extended field_shock_and vibration,_especially_in_the telecom environment. Furthermore, they_generally cannot maintain full engagement_during fragility_operations such as transportation and shipping because there_is_no pre-loading spring_action.
Simple locking mechanisms do not provide any pre-load, and_thus are inadequate for powered sub-assemblies,_especially when the_service_environment_includes shocks and vibrations._1. Field of the Invention
The present_invention relates to the problem of_resonance due to plating stubs on circuit_boards.
2. Background of the Related Art
An_integrated circuit (IC), also commonly_referred to_as a “microchip” or “chip,”_is an electronic_circuit comprising_miniaturized semiconductor devices_formed in a semiconductor substrate. Many_copies of an_integrated circuit may be formed on_a_large semiconductor wafer,_which_is_then cut_into individual pieces_referred_to as_a_“die chips” or “dies,” each containing_a_copy of the integrated circuit. Semiconductor materials_such as silicon are_typically_brittle, so a fragile_die chip is commonly packaged_on a carrier, referred to as_a “chip_package” or_simply “package.” The substrate of the chip package functions as an_interposer for interfacing the chip with_a printed circuit board_(PCB). For_example_the processor for_a_computer may_be carried on a chip package that_is mounted_to a motherboard.
The die chip may_be electrically connected to_a_package substrate by wirebonding. Wirebonding is_a process known in the art_by which a very fine_wire_is_connected from a bond pad_on the chip to corresponding signal_pathways (“traces”) on_the package substrate. Bond wires are typically_formed_of a highly conductive material, such_as_platinum or other precious metal. A_package_in_which a die chip is_connected to the substrate by wirebonding_may be referred to as a “wirebond package.” The_traces on the_substrate extend from the location_of_bonding_with the wirebond to signal interconnects elsewhere on the substrate._The signal_interconnects on one_layer of the substrate may be electrically connected to signal_interconnects on another layer of the substrate_using through-connections known as “vias.” Thus, for example, the signal connects_on the face to which the chip is_mounted may be connected to corresponding pins_of a pin grid_array_(P