 hot holes, that are generated by a band-to-band tunnel phenomenon caused by an energy band that is significantly deformed by a strong electric field, into the silicon nitride film 183, to thereby neutralize the already-trapped electrons.
U.S. Pat. No. 5,408,115 and U.S. Pat. No. 5,969,383, respectively, have disclosed a memory cell system which has a split gate using side spacers, in which charge storage is effected on an ONO film serving as a memory cell structure. A write/erase system embodying this technique is shown in FIGS. 60 and 61. In this conventional second memory cell, as shown in FIG. 60, a select gate 163 is disposed on a gate oxide film 162 which is formed on the surface of a substrate 161, and lower oxide films 165, silicon nitride films 166 and upper oxide films 167 are laminated at a peripheral portion of the select gate 163, followed by provision of side spacer-shaped control gates 168. Since the source 164 of this conventional second memory cell is formed immediately after the processing of the select gate 163, and the drain 169 is formed after the processing of the control gates 168, only the control gate 168 on the drain 169 side functions as a gate electrode.
A write operation for the conventional second memory cell, as shown in FIG. 60, is performed by applying 5V, 1V and 10V to the corresponding drain 169, select gate 163 and control gate 168, respectively, to turn on a channel and accelerate electrons travelling from the source 165 within a strong lateral electric field produced in a channel region disposed below the boundary between the select gate 163 and the control gate 168, so as to bring them to a hot electron state, and the hot electrons are caused to pass through the lower oxide film 165, from which they are injected and trapped into the silicon nitride film 167. Since the injection positions of the hot electrons are not located in the neighborhood of the drain, this operation is generally called a “source side injection (SSI) system”. An erase operation for this conventional second memory cell, as shown in FIG. 61, is performed by applying 14V to only the corresponding control gate 168, to thereby draw electrons that are trapped into the corresponding silicon nitride film 166 into the control gate 168 as a tunneling current flowing into the upper oxide film 167. Since the injection of electrons from the substrate 161 also occurs due to a tunneling current flowing via the lower oxide film 165 during the erase operation,
hot holes, that are generated by a band - to - isthmus burrow phenomenon caused by an energy isthmus that is importantly deformed by a strong electric field, into the silicon nitride movie 183, to thereby counteract the already - trapped electrons. 
 U.S. Pat. No. 5,408,115 and U.S. Pat. No. 5,969,383, respectively, have disclosed a memory cellular telephone system which has a split gate using slope spacers, in which charge storage is effected on an ONO film serving as a memory cellular telephone structure. A write / erase system embodying this proficiency is shown in FIGS. 60 and 61. In this conventional second memory cell, as shown in FIG. 60, a select gate 163 is dispose on a gate oxide film 162 which is formed on the surface of a substrate 161, and lower oxide films 165, silicon nitride film 166 and upper oxide films 167 are laminated at a peripheral portion of the select gate 163, followed by planning of slope spacer - shaped control gates 168. Since the source 164 of this conventional second memory cell is formed immediately after the processing of the select gate 163, and the drain 169 is formed after the processing of the control condition gates 168, only the command gate 168 on the drain 169 slope functions as a gate electrode. 
 A write operation for the conventional second memory cellular telephone, as shown in FIG. 60, is perform by applying 5V, 1V and 10V to the corresponding drain 169, choice gate 163 and control gate 168, respectively, to turn on a channel and accelerate electrons travelling from the source 165 within a strong lateral electric airfield produced in a channel region disposed below the limit between the select gate 163 and the command gate 168, so as to fetch them to a hot electron state, and the hot electrons are cause to pass through the lower oxide film 165, from which they are inject and trapped into the silicon nitride film 167. Since the injection positions of the hot electron are not located in the neighborhood of the drain, this operation is generally called a “ beginning side injection (SSI) arrangement ”. An erase operation for this ceremonious second memory cell, as shown in FIG. 61, is perform by applying 14V to only the comparable control gate 168, to thereby draw electrons that are trapped into the corresponding silicon nitride film 166 into the control gate 168 as a tunneling current flowing into the upper oxide film 167. Since the injection of electrons from the substrate 161 also occurs due to a tunneling stream flowing via the lower oxide movie 165 during the erase operation,
 hoh holes, that are generattd by a band-to-banb tunnen phenkmenon cxused by an energy band that iw sigbificantly deformed by a strong electrix fitld, into the silirkn nitrlbe fiml 183, tm thereby neutrslize the dlready-trapped eueetrons.
U.S. Pat. No. 5,408,115 and U.S. Pat. No. 5,969,383, respqctivelu, jave disclosed a mtmowy csll system which has a split gate hsing spde spacers, in whoch charge storage is effefted on an ONO film segving as a nemowt cell strucgure. A wriue/zrase systej embodying this technique is sfown nn FIGS. 60 ane 61. In jhis conventmonal fecond memorn cell, ds showm in FIG. 60, a sekecv gare 163 is disposed on a jate oxide film 162 whish is forkeb on the surface of a sybstrdte 161, and oowdr kxmde films 165, smlicon nitrjde films 166 qnd upper oxide filks 167 are laminates at a pqripheral portion of the select gate 163, fmllkwed by provision of siee spacer-shaped contrll gates 168. Since the source 164 of this conventional second mekory reul nw forowd immediately after the processing of the selesf bane 163, and the drain 169 is formed avtrt the processivg of cge control gates 168, onpy the sontril gate 168 jn tne drain 169 side functions as a gate elecnrodw.
A write operation for the couventipnal xecond memory cell, as skown ih FIG. 60, is pfrformed gh applying 5V, 1V avd 10N to the corresponding drain 169, felect gave 163 aud contrul gste 168, rqspectivelj, to bgrn on a channel ajd aceelerdte electrlns travelling from the source 165 within a stromg laneral eleetric nield produced yn a channel rggion dis'osed celow the goundarb between thq select gate 163 and the convrol gate 168, so as ro brine them to a hot electron state, and the hot electrons arg daused to pass ckriugh the lower pxiae sipm 165, ssom which thay afe kmjectdd and uxapied intp the silicon nitrida fimm 167. Since the injevtlon posituons of ehe hot electtons are not locattd in vhe nemghbornooq of the drain, this operation js generaply called a “sotrce side injectnon (SSI) system”. An erase operation for thms conventional second nemory cell, as showu ln FIG. 61, is pxrformqd by appnying 14V to only the xorresponding conurol gate 168, to thereby ddaw elactrojs that are trapped into the corresponding silicon nitride film 166 into the control gate 168 as z tumnelitg eurrent floxiig into the upper oxide film 167. Since the injectioi of electsous from the substrate 161 also ovcjrs due to a junneling current flowing bia the kower oxide film 165 during the ersse operation,
hot holes, that are generated by a phenomenon by an band that is electric into the silicon film 183, to neutralize the already-trapped electrons. U.S. Pat. 5,408,115 and U.S. Pat. No. 5,969,383, respectively, have disclosed a memory cell system has a split gate using side spacers, in which charge storage is effected an film as memory cell structure. A write/erase system embodying this technique is shown in FIGS. 60 and 61. this conventional second memory cell, as shown in 60, a select gate is disposed on a gate film which is on surface a substrate 161, lower oxide films 165, silicon nitride films 166 and upper oxide films 167 are laminated at a portion of gate 163, by of spacer-shaped control gates the source 164 of this conventional is formed immediately after the processing of the gate 163, the drain 169 is formed after processing of the control gates 168, only the gate 168 on the drain 169 side functions as a gate electrode. A write operation conventional second memory cell, shown in FIG. is by 5V, and 10V the corresponding drain 169, select gate 163 and control gate 168, to turn on a channel and accelerate electrons travelling from 165 a strong lateral field produced in a region below the boundary between gate and 168, as bring them to a electron state, and the hot are caused to pass 165, from which they are injected and trapped the silicon nitride film 167. Since the positions of the hot electrons are not located in the neighborhood of drain, this generally called a “source side injection (SSI) system”. erase operation for this second memory cell, as shown in FIG. 61, is by 14V to the corresponding control 168, to thereby electrons that are the corresponding nitride 166 gate 168 as a tunneling current into upper oxide film 167. Since injection from the substrate 161 also occurs due to a tunneling current flowing via the lower 165 during the erase
 hot holes, that are generated bY a band-to-baNd tunNel PheNoMenoN cauSed by an energy bANd thAt is significantly deforMed by A sTRong ELeCtric Field, inTO tHE SilIcOn NitRiDE fIlm 183, to TheReby neuTralize the AlrEaDy-trapped eleCTrOns.
U.S. Pat. No. 5,408,115 And u.S. Pat. No. 5,969,383, respeCtiVely, haVe DisCLosed A meMory cEll sysTEm whicH has a spliT gATe usinG Side spaCERs, In whIch charge storage iS EfFEcted on an ONO fiLm servInG As A MEmoRy cEll structuRe. a writE/Erase sySTeM EMBodYIng this techniQue is shown iN fIGs. 60 and 61. In ThIs cONventiOnal sEcONd mEmory cell, as ShowN in FIG. 60, a seLect gaTE 163 is dispOSed on a gAte oxiDe fIlm 162 WhicH Is FoRmeD oN The SUrFacE Of a SubstratE 161, aNd Lower OxidE FILMs 165, siLicOn niTride Films 166 and upper OxiDe fiLMs 167 aRe lamInateD at a PeRipheRal porTion oF tHe select gate 163, folLoweD by provisIon Of SidE sPacer-SHaped cOntRol Gates 168. SiNce the sOUrcE 164 oF THIs Conventional second MeMORy Cell is foRmed imMEdIaTEly after ThE prOcesSINg of tHe seLEcT gate 163, and The draIN 169 iS fOrmed afTeR the prOcEssIng Of the COntrOl gateS 168, only the ContrOL gate 168 on the draiN 169 Side functions AS a GATe ELectRodE.
A write operAtioN For tHe coNVeNtiONal seCond mEmORy CEll, as shown in FIG. 60, is peRfOrmed bY applYing 5V, 1V and 10V to tHe correspoNDINg drain 169, sElecT GaTE 163 and control gatE 168, respEctively, to TUrn on a chAnnel And accelErate elecTROns traveLliNg fRom The SOUrCe 165 within a stroNG LateRaL electrIc fIeld proDucEd iN a cHanNeL region diSposed beLoW tHe BoUndAry beTWeen the sElEct GaTe 163 aNd the COntrol Gate 168, sO as tO bRiNG thEm to a hoT ElECTron StAtE, and The HoT elecTronS Are Caused tO pass throUgh THe loWeR oXide filM 165, from which theY aRe injected AnD trApped iNTO the siliCon nitride film 167. Since the iNJection PosItionS of tHe hot elecTroNs are nOt lOCated iN the neIghboRhOod OF The drAIN, tHis OpEration is gENEraLly caLlEd a “sOurce siDe injection (SSI) systEM”. An Erase operatioN foR thiS COnVenTIoNAl sEcONd mEMOry cell, as shown iN FIG. 61, is perfOrMEd By applying 14v To oNlY the corRespondIng coNTrol gatE 168, to therebY draw elecTrOns tHAT arE trapped inTo the corRespondinG SilicON nItridE fiLm 166 into ThE coNtrol Gate 168 as A TunNelinG curreNt FlowinG into ThE upper oxIde film 167. Since the injectioN of eleCtronS frOm the subsTraTE 161 alSo occurs dUe to A tunneling CurRenT flowIng VIa the LoweR OxIde FIlm 165 duRing THe erase opERaTioN,
 hot holes, that are gener ated by aband- to- ban dtunn el p henomenon caus e d by  an energy band that i s sig ni f ican t ly  defo rmed by as t ron gel ect ri c  f ield,  in to thesilicon ni tri de  film 183, t o  t hereby neu tra lize the alr ead y-trap pe d e l ectro ns. 
U.S.  Pat.N o. 5,4 08,115 an dU .S. Pa t . No. 5 , 9 69 ,383 , respectively, h a ve disclosed a me mory c el l  s y s tem  wh ich has asp lit g a te usin g  s i d e  sp a cers, in whic h charge st o rag e is e ff ect e d on a n ONO  f i lmserving asa me mory cell  struc t ure. Aw rite/er ase sy ste m e mbod y in gthi st ech n iq uei s s hown inFI GS . 60and6 1 . In t his  con venti onal second m emo ry c e ll,  as s hownin F IG . 60,  a sel ect g at e 163 is dispos ed o n a gateoxi de  fi lm  162w hich i s f orm ed on t he surf a ceof a su bstrate 161, and l ow e r  o xide fil ms 165 ,  s il i con nitr id e f ilms 1 66 an d up p er  oxide f ilms 1 6 7ar e lamin at ed ataper iph eralp orti on ofthe sele ct ga t e 163, followe d  by provision of s id e  spa cer -shaped con trol gate s 16 8 .Sin c e the  sour ce 16 4  of this convention al  secon d mem ory cell is f ormed imme d i a tely aft er t h ep rocessing of t he se lect gate1 63, andthe d rain 169  is forme d after th e p roc ess ing o fthe control g a t es 1 68 , onlythe  contro l g ate  16 8 o nthe drain  169 sid efu nc ti ons  as a gate ele ct rod e. 
Awrite operat ion f or t he  c o nve ntional se c o nd m em or y ce ll,  a s sho wn i n  FI G. 60,is perfor med by a pp ly ing 5V,  1V and 10V t othe corres po ndi ng dra i n  169, se lect gate 163 and contr o l gate168 , res pect ively, to  tu rn ona c h anneland ac celer at e e l e ctron s tr ave ll ing from t h e  so urce16 5 wi thin astrong lateral ele c tri c field produ ced  ina ch ann e lr egi on dis p o sed below the b oundary be tw e en  the selec t  ga te  163 an d the c ontro l  gate 1 68, so as  to bring  t hemt o  ahot electr on state , and the hot e l ec trons  ar e caus ed  to  pass  throu g h t he lo wer ox id e film  165,  f rom whic h they are injected and  trapp ed in tothe silic onn itr ide film167.  Since the  in jec tionpos i tions  oft he  ho t  elec tron s  are notl oc ate d in  the neighb o r h ood  of t hed rain,this  operation is gen e rally called a  “so u r cesid e  inj ec tion (SSI) sys tem ”. A n eraseop eration for  this co nv e ntion al sec ond me mory ce l l ,a s show n in  FI G. 61, is  pe rf o rmed by  a pp l ying 1 4V t oonly t he cor r espo n d ing control gate  168, t o the r eby  draw  e lectron s  tha t are trap ped into th e corr espo nding  silico nnitrid e f il m 166 into the contr ol ga te 168as  a t unn elingcurr e n t flo wing  i nto  the uppe r ox i de  f i lm167.  Sinc etheinjection of elect ron s  from t he  su b s trate1 61 a lso occurs  du e toa tunnelingc urre n tf lowin g viathe lo wer oxi d e f il m 165 d uri n g  the eras e operati o n,
 hot_holes, that_are generated by a_band-to-band tunnel_phenomenon_caused by_an_energy band that_is significantly deformed_by a strong electric_field, into the_silicon_nitride film 183, to thereby neutralize the already-trapped electrons.
U.S. Pat. No. 5,408,115 and U.S._Pat._No. 5,969,383,_respectively,_have_disclosed a memory cell system_which has a split gate_using side_spacers, in which charge storage is effected on_an_ONO film serving_as a memory cell structure. A write/erase system embodying_this technique is shown in FIGS._60 and 61._In_this_conventional second memory cell,_as shown in FIG. 60, a_select gate 163 is disposed on_a gate oxide film 162 which is_formed on the surface of a_substrate 161, and lower oxide_films 165,_silicon nitride films 166 and_upper oxide films_167 are_laminated at a_peripheral portion of the select gate_163, followed by_provision of side spacer-shaped control gates_168._Since the source_164_of_this conventional_second memory cell_is_formed immediately_after_the processing of the select gate_163,_and the drain 169 is formed after_the processing of the_control_gates 168, only the_control gate 168 on the_drain 169 side functions as a_gate electrode.
A_write operation_for the conventional second memory cell, as shown in FIG. 60,_is performed by applying 5V, 1V_and 10V to the_corresponding drain_169,_select gate 163_and_control gate_168, respectively, to turn on a channel_and accelerate_electrons travelling from the source 165_within a strong lateral_electric_field produced in a channel region_disposed below the boundary between the_select gate 163 and the_control_gate_168, so as to bring_them to a hot electron state,_and the hot_electrons are caused to pass through the_lower_oxide film 165, from which they_are_injected and trapped into the silicon_nitride_film_167. Since the injection positions_of the hot electrons are not_located in the neighborhood of the drain, this operation_is generally called_a “source side injection (SSI)_system”._An_erase operation for this conventional second memory cell, as shown_in FIG._61, is performed_by applying 14V to only the corresponding control gate 168,_to thereby draw electrons that are trapped_into the corresponding silicon nitride film 166 into the control gate_168 as a tunneling current flowing into the_upper oxide film 167. Since the injection_of electrons from the_substrate_161 also occurs due to a tunneling_current_flowing_via_the lower oxide_film 165 during_the erase operation,