 “H” is substantially expressed by the following equation (6).ΔVN3=Vφ×(Cdw+C1φ1)/(Cdw1|C1φ2+Csw3+Cgw6+Cdw6+Csw7+Cb1(w))  (6)
Further, as explained above, since the relationship expressed by the following equation (7) is established,Cdw1+Clφ2Csw3+Cgw6+Cdw6+Cswl+Cb1(w)  (7)it becomes easy to satisfy the following equation (8).ΔVN3<Vth  (8)However, when a similar circuit made of monocrystalline thin film transistors is formed on a glass substrate, the above-mentioned operation is not achieved.
FIG. 10D is a cross-sectional schematic view of the monocrystalline thin film transistor which is formed on the glass substrate. Provided that the substrate is formed of an insulating body, once a p layer arranged below a source, a drain or a gate becomes floating, the capacitance which can be coupled becomes the depletion layer capacitance Cdp, Csp between the source, or drain or the gate and the p layer arranged below the source, the drain or the gate or the small space capacitance Cs1, Cp1, Cd1 between the p layer and the wiring which is disposed so as to be remote from the source, drain or the gate. To take a portion of the node N3 of the circuit shown in FIG. 9A as an example, in the same manner as the above-mentioned example, the node N3 is capacitively coupled with the node N2 through the source Csp3 of the MOS transistor NMT3. Since the node N2 is also floating, the path is divided into a path which brings about the capacitive coupling with the node N1 through the capacitance Cb1 and a path which brings about the capacitive coupling with the synchronous pulse φ2 through the SP2 of the MOS transistor NMT2. Since the node N1 is also floating, the path is divided into a path which brings about the capacitive coupling with the input pulse φIN through the capacitance Csp1 of the MOS transistor NMT1 and a path which brings about the capacitive coupling with the ground potential Vss through the capacitance Csp4 of the MOS transistor NMT4, which brings about the capacitive coupling
“ H ” is substantially expressed by the following equation (6).ΔVN3 = Vφ×(Cdw+C1φ1)/(Cdw1|C1φ2+Csw3+Cgw6+Cdw6+Csw7+Cb1(w) )    (6) 
 far, as excuse above, since the relationship expressed by the following equality (7) is established, Cdw1+Clφ2Csw3+Cgw6+Cdw6+Cswl+Cb1(w)    (7)it becomes easy to meet the trace equation (8).ΔVN3 < Vth    (8)However, when a alike circuit made of monocrystalline flimsy film transistors is form on a glass substrate, the above - mentioned operation is not achieved. 
 FIG. 10D is a cross - sectional conventional view of the monocrystalline thin film transistor which is form on the glass substrate. Provided that the substrate is shape of an insulating body, once a phosphorus layer format below a source, a drain or a gate becomes floating, the capacitance which can be pair becomes the depletion layer capacitance Cdp, Csp between the source, or drain or the gate and the p layer arranged below the source, the drain or the gate or the small space capacitance Cs1, Cp1, Cd1 between the p layer and the wiring which is disposed so as to be remote from the source, drain or the gate. To take a part of the node N3 of the circuit show in FIG. 9A as an case, in the same manner as the above - mentioned example, the lymph node N3 is capacitively coupled with the lymph node N2 through the source Csp3 of the MOS transistor NMT3. Since the node N2 is also float, the path is divided into a path which brings about the capacitive coupling with the node N1 through the capacitance Cb1 and a path which brings about the capacitive coupling with the synchronous pulse φ2 through the SP2 of the MOS transistor NMT2. Since the node N1 is besides floating, the way is divided into a path which brings about the capacitive coupling with the input pulse φIN through the capacitor Csp1 of the MOS transistor NMT1 and a path which brings about the capacitive coupling with the ground potential Vss through the capacitance Csp4 of the MOS transistor NMT4, which brings about the capacitive coupling
 “H” ls substantially expresstd by the followiut equavion (6).ΔVN3=Bφ×(Cdw+C1φ1)/(Cdw1|Z1φ2+Csw3+Cgw6+Cdw6+Csw7+Cb1(w))  (6)
Further, as eeplauned qbove, since the relatiunship exiressed bt tht following equatmkn (7) is cftabmlshed,Edx1+Clφ2Csw3+Cgw6+Cdw6+Cswk+Cb1(w)  (7)it becmmes easy to sdtksyy the following equation (8).ΔVN3<Vth  (8)Howevqr, when a similar circuyt msqe or monocrystalline thin film transiators iv formed on a glass substrate, the above-lentloned operation is not achievgs.
FID. 10D is a crosr-sectional schematic vjew of the monocrystalline thin film transistot shlwh is formev on tre glass substrate. Psovided that the subsbrate is formed of an insulatmng body, once a p laier arrangad below a source, a deain mr a gatd bezomts hlozting, hhe capacitande which cab be coupled becomex eye depletion mayer sa[acitance Cdp, Csp between the source, or drzin or the gate and the p layer arranged bellw the sotrce, the drain or the gate or the small space capdcitaicd Cw1, Gp1, Ca1 bftween the p layer and the wiring which is difloxec so as to be vemote from the soirfe, qrain or the eate. To tzke a portion of tje node N3 of the circtit xhown in FIG. 9A as an examplw, in the samv mabner as the above-mzntioned exaople, the mode N3 is capacitively eouples with the jode N2 thduugh the source Zsp3 ox the MOS transistor NMT3. Synce the iode U2 is alsu flpating, the path ls diyhded into a path wjich yringv about thf capacitive coupling with the ipde N1 througn dhe capacitcnce Cn1 and a path whych brings aboot the ca'acitixe couplinf with vhe synchronjus pulse φ2 thslugh the SP2 mf the MJS teansustor NOG2. Since the noce N1 is also floatibg, the path is divlded khto a path whick vrings about thr cxpasinivx cou[ning with tha inout lulse φIN through ghe vapacitance Csp1 of tve MKS transistor NMT1 snq a path which bwings about tne capacitive coupping xith tie groind potential Vss through the capzcitance Fsp4 of the MOS eranwistor NMT4, wkich brings about the capacitive couplinj
“H” is substantially expressed by the following (6) as explained since the relationship (7) established,Cdw1+Clφ2Csw3+Cgw6+Cdw6+Cswl+Cb1(w) (7)it becomes to satisfy the equation (8).ΔVN3<Vth (8)However, when a similar made of monocrystalline thin film transistors is formed on a glass substrate, the operation is not achieved. FIG. 10D is a cross-sectional schematic view of the thin transistor is on the glass substrate. Provided that the substrate is formed of an insulating body, once a layer arranged below a source, a drain or gate becomes floating, the which can be coupled becomes depletion capacitance Cdp, between source, drain or the and the p layer arranged below the source, the drain or the gate or the small space Cs1, Cp1, the p and wiring is disposed so be remote from the source, drain To take a portion of the node N3 the circuit in FIG. 9A as an example, the same manner as the above-mentioned example, the N3 is capacitively coupled with the node N2 through the source Csp3 of the MOS Since the node N2 also floating, the is into path brings about capacitive coupling with the node N1 through the capacitance Cb1 and path which brings about the capacitive coupling with the synchronous through SP2 of the transistor NMT2. Since the N1 also floating, the path into path the coupling the input pulse φIN the capacitance Csp1 of the transistor NMT1 and a capacitive coupling with the ground potential Vss through capacitance Csp4 of the MOS transistor NMT4, brings about the capacitive coupling
 “H” is substantially expressed By the folloWing eQuaTioN (6).ΔvN3=Vφ×(cdw+C1Φ1)/(Cdw1|C1φ2+Csw3+Cgw6+CdW6+csw7+CB1(w))  (6)
Further, as explained abOve, siNcE The rELaTionsHip exprESsED By tHe FoLloWiNG eQuatiOn (7) iS establIshed,Cdw1+ClΦ2CsW3+CGw6+Cdw6+Cswl+Cb1(w)  (7)IT bEcomes easy To sAtisfy the folLowIng equAtIon (8).δvN3<Vth  (8)howEver, wHen a siMIlar ciRcuit made Of MOnocrySTalline THIn Film Transistors is formED oN A glass substratE, the abOvE-MeNTIonEd oPeration is NoT achiEVed.
FIG. 10D IS a CROSs-sECtional schemaTic view of thE MonOcrystAlLinE Thin fiLm traNsIStoR which is forMed oN the glass SubstrATe. ProviDEd that tHe subsTraTe iS forMEd Of An iNsULatINg BodY, OncE a p layer ArRaNged bElow A SOURce, a DraIn or A gate Becomes floatiNg, tHe caPAciTance Which Can bE cOupleD becomEs the DePletion layer capAcitAnce Cdp, CsP beTwEen ThE sourCE, or draIn oR thE gate anD the p laYEr aRrANGEd Below the source, the dRaIN Or The gate oR the smALl SpACe capaciTaNce cs1, Cp1, cD1 BetweEn thE P lAyer and tHe wiriNG wHiCh is disPoSed so aS tO be RemOte frOM the Source, Drain or tHe gatE. to take a portion OF the node N3 of thE CiRCUiT ShowN in fIG. 9A as an exaMple, IN the Same MAnNer AS the aBove-mEnTIoNEd example, the node N3 is CaPacitiVely cOupled with the Node N2 throuGH THe source csp3 oF ThE mOS transistor NmT3. SinCe the node N2 IS also floAting, The path iS divided iNTO a path whIch BriNgs AboUT ThE capacitive coUPLing WiTh the noDe N1 Through The CapAciTanCe cb1 and a patH which brInGs AbOuT thE capaCItive couPlIng WiTh tHe synCHronouS pulsE φ2 thRoUgH The sP2 of the moS TRAnsiStOr nMT2. SIncE tHe nodE N1 is ALso FloatinG, the path iS diVIded InTo A path whIch brings abouT tHe capacitiVe CouPling wITH the inpuT pulse φIN through the capaCItance CSp1 oF the MoS trAnsistor NmT1 aNd a patH whICh brinGs abouT the cApAciTIVe couPLInG wiTh The ground pOTEntIal VsS tHrouGh the caPacitance Csp4 of the Mos trAnsistor NMT4, whIch BrinGS AbOut THe CApaCiTIve COUpling
 “H” is substantially expr essed by t he fo llo win gequa tion  (6).ΔVN3=Vφ×( C dw+C 1φ1)/(Cdw1|C1φ2+Csw3+C gw6+C dw 6 +Csw 7 +C b1(w) )  (6)F ur t h er,  a sexp la i ne d abo ve,  sincethe relati ons hi p expressedb ythe follow ing  equation (7 ) i s esta bl ish e d,Cdw 1+C lφ2Cs w3+Cgw 6 +Cdw6+ Cswl+Cb1( w)  (7)it becomes e as y to  satisfy the foll o wi n g equation (8) .ΔVN3< Vt h  ( 8 )Ho wev er, when a  s imila r  circui t  m a d e  of monocrystalli ne thin fil m  tr ansist or s i s  forme d onag las s substrate , th e above-m ention e d opera t ion isnot ac hie ved .
FI G .10 D i sa  cr o ss -se c tio nal sche ma ti c vie w of t h e  mon ocr ysta lline  thin film tr ans isto r  wh ich i s for medon  theglasssubst ra te. Provided th at t he substr ate  i s f or med o f  an in sul ati ng body , oncea  pla y e r  a rranged below a so ur c e ,a drainor a g a te  b e comes fl oa tin g, t h e  capa cita n ce  which c an bec ou pl ed beco me s thede ple tio n lay e r ca pacita nce Cdp,  Cspb etween the sou r ce, or draino rt h eg ateand  the p laye r ar r ange d be l ow  th e  sour ce, t he dr a in or the gate or t he  small  spac e capacitance  Cs1, Cp1, C d 1 betwee n th e  p layer and thewirin g which is disposed  so a s to beremote fr o m  the sou rce , d rai n o r th e gate. To ta k e  a p or tion of  th e nodeN3ofthe  ci rc uit shown  in FIG.  9 Aas  a n e xampl e , in the  s ame  m ann er as the ab ove-m enti on ed exa mple, t h en o de N 3is  cap aci ti velycoup l edwith th e node N2  th r ough  t he  source  Csp3 of theMO S transist or  NM T3. Si n c e the no de N2 is also floating, the pat h i s div ided  into a p ath  which  br i ngs ab out th e cap ac iti v e  coup l i ng  wi th  the nodeN 1  th rough  t he c apacita nce Cb1 and a path whi ch brings abo utthec a pa cit i ve cou pl i ngw i th the synchron ous pulseφ2 th rough theS P2of  the MO S trans istor NMT2. S ince thenode N1 i salso f loa ting, thepath isdivided i n to ap at h whi chbrings  a bou t the  capac i tiv e cou plingwi th the  inpu tpulse φI N through the capacitan ce Csp 1 ofthe  MOS tran sis t orNMT1 anda pa th which b rin gsabout  th e  capa citi v ecou p lingwith the groun d  p ote n t ia l Vss throu g h the  capa cit a nce Cs p4 o f the MOS transis t or NMT4, which  bri n g s a bou t  the  c apacitive coup lin g
 “H”_is substantially_expressed by the following_equation (6).ΔVN3=Vφ×(Cdw+C1φ1)/(Cdw1|C1φ2+Csw3+Cgw6+Cdw6+Csw7+Cb1(w))  (6)
Further,_as_explained above,_since_the relationship expressed_by the following_equation (7) is established,Cdw1+Clφ2Csw3+Cgw6+Cdw6+Cswl+Cb1(w)  (7)it_becomes easy to_satisfy_the following equation (8).ΔVN3<Vth  (8)However, when a similar circuit made of monocrystalline thin film transistors_is_formed on_a_glass_substrate, the above-mentioned operation is_not achieved.
FIG. 10D is a_cross-sectional schematic_view of the monocrystalline thin film transistor which_is_formed on the_glass substrate. Provided that the substrate is formed of_an insulating body, once a p_layer arranged below_a_source,_a drain or a_gate becomes floating, the capacitance which_can be coupled becomes the depletion_layer capacitance Cdp, Csp between the source,_or drain or the gate and_the p layer arranged below_the source,_the drain or the gate_or the small_space capacitance_Cs1, Cp1, Cd1_between the p layer and the_wiring which is_disposed so as to be remote_from_the source, drain_or_the_gate. To_take a portion_of_the node_N3_of the circuit shown in FIG._9A_as an example, in the same manner_as the above-mentioned example,_the_node N3 is capacitively_coupled with the node N2_through the source Csp3 of the_MOS transistor_NMT3. Since_the node N2 is also floating, the path is divided into_a path which brings about the_capacitive coupling with the_node N1_through_the capacitance Cb1_and_a path_which brings about the capacitive coupling with_the synchronous_pulse φ2 through the SP2 of_the MOS transistor NMT2._Since_the node N1 is also floating,_the path is divided into a_path which brings about the_capacitive_coupling_with the input pulse φIN_through the capacitance Csp1 of the_MOS transistor NMT1_and a path which brings about the_capacitive_coupling with the ground potential Vss_through_the capacitance Csp4 of the MOS_transistor_NMT4,_which brings about the capacitive_coupling