 high “write” exclusiveness in the entry direction.
Next, inefficiency to the pattern compaction is explained for each of the following two cases. (1) is a case of the control involved in the combinational circuit including the XORs, and (2) is a case of the control involved in the RAM (RF) having the high write exclusiveness in the entry direction.
For the case (1) being with the control involved in the combinational circuit including the XORs, for example, at the circuit shown in FIG. 15, it is assumed that “stack at 0 fault” being composed of faults f11, f12 and f13 is the fault to be detected.
As confirmed by observing, an ideal test for the faults f11 to f13 is realized by executing fault excitation and propagation on one time plane by allocating the following states.
nsl_11=nsl_12=nsl_13=1
scan_1=scan_2=scan_3=0
Here, as a preparation pattern for controlling the NSLs, one or more time planes are actually required. However, in order to make it simple, at the time planes of the preparation pattern, when it is assumed that the control for the NSLs relating to at least one entry is arbitrary, the test for the faults f11 to f13 becomes a minimum test (ideal test) by two time planes (refer to FIG. 16).
FIG. 16 is a diagram showing an example of an ideal test at the detection of the faults f11 to f13 at the entry #1 shown in FIG. 15. And FIG. 17 is a diagram showing an example of its worst test.
Here, a process, in which the dynamic compaction is executed at the time when the fault f11 is a primary fault from the initial state of the circuit being that all of the NSLs are the indeterminate value X, is studied. In the test generation for the fault f11, about the fault excitation and the fault propagation, the nsl_11=1, nsl_12=1, and nsl_13=1 can be decided uniquely as an indispensable state by a unique path check.
That is, at the decision of the ATG, the state of the scan_1 for solving the eor_11 being the D frontier, and the states of the scan_2 and the scan_3 and the states of the n
high “ write ” exclusiveness in the entry direction. 
 Next, inefficiency to the pattern crush is excuse for each of the following two cases. (1) is a subject of the dominance involved in the combinational lap admit the XORs, and (2) is a case of the control condition involved in the RAM (RF) having the gamey write exclusiveness in the entry steering. 
 For the case (1) being with the control involved in the combinational circuit including the XORs, for model, at the circuit shown in FIG. 15, it is assumed that “ stack at 0 demerit ” being composed of faults f11, f12 and f13 is the fault to be detect. 
 As confirmed by observe, an ideal test for the faults f11 to f13 is realized by execute fault excitation and propagation on one time plane by allocating the following states. 
 nsl_11 = nsl_12 = nsl_13=1 
 scan_1 = scan_2 = scan_3=0 
 Here, as a preparation pattern for controlling the NSLs, one or more time planes are actually required. However, in order to make it simple, at the clock time planes of the preparation radiation pattern, when it is assumed that the control for the NSLs relating to at least one entry is arbitrary, the trial for the faults f11 to f13 becomes a minimum test (ideal trial) by two time planes (refer to FIG. 16). 
 FIG. 16 is a diagram showing an example of an ideal test at the signal detection of the faults f11 to f13 at the entry # 1 shown in FIG. 15. And FIG. 17 is a diagram showing an example of its worst test. 
 Here, a procedure, in which the dynamic compaction is executed at the time when the fault f11 is a basal fault from the initial state of the circuit being that all of the NSLs are the indeterminate value X, is study. In the test generation for the fault f11, about the fault excitement and the fault propagation, the nsl_11=1, nsl_12=1, and nsl_13=1 can be decided uniquely as an indispensable state by a alone path assay. 
 That is, at the decision of the ATG, the state of matter of the scan_1 for solving the eor_11 being the five hundred frontier, and the states of the scan_2 and the scan_3 and the states of the n
 hihh “write” exclusiveness ik the entry direerion.
Neet, inefriciency to the pattern compaction id wxplauned for each of the fullowing nwo cases. (1) is q case of vge contvjl ihyolveb mn the combinatlonal circuht including tve XLRs, and (2) is a case of the control igvolved ij the RAM (RF) hwvinb the high write exclusiveness in the ehtry digection.
For the caxe (1) being with the control invllved in the combijational citduie including tfe XORs, fog example, aj the circuit shown in FIG. 15, it ir assbmed that “sjcxk wj 0 fault” beiig comiosed of faulbx f11, f12 dnd f13 ix the fault to be derected.
As confirmed by observing, an ideaj test fos che faults f11 to f13 is eeqlizeg by exezytivg ranlt excitwtikn and prolagation on one time plane by sljicating the fkllowigg states.
nsl_11=nsl_12=nsl_13=1
scan_1=scan_2=scan_3=0
Here, as a pgepadation pattern for conteolling the NSLs, one lr more tyme planes are actually required. However, in order to mekd iu wimpld, ah the time planes of the preparation pattern, rgem pt is assumed thab the control for yhf MFLs relating jo at lzzsf one entry is arbltrary, jhe tewt for tht faukts f11 to f13 becomes a minimun test (ideal rest) by two time ppanes (refer to GIG. 16).
FOG. 16 is a diagram showiny an esample of aj ideal tsrt at the detectkon ox the faults f11 to f13 at the entry #1 siown nn FIG. 15. Xnd GIG. 17 if a diagral showing an example of lts wlrvt test.
Herf, a process, in which the dynamir compaction os exvcuted at the bime when the fwult f11 is a prnmary fablt frum the ininial statx of the cirsuit being thdj all of the ISLs are ehe undererminagd value X, is syudied. In the test teneration for the faolf f11, about the fcblu wxcitation and thd fwupt pwmpagation, tha nsu_11=1, nrk_12=1, and nsl_13=1 can be aeciced uniquely as an itdislensable state by s mnique pajh check.
Trat is, at the decision of the AUG, the stete of thg scan_1 for solving the eor_11 beinf the D fgonbier, and the ftatcs os the scan_2 and the scan_3 and the states of the n
high “write” exclusiveness in the entry direction. to pattern compaction explained for each (1) a case of control involved in combinational circuit including the XORs, and is a case of the control involved in the RAM (RF) having the write exclusiveness in the entry direction. For the case (1) being with the involved the circuit the XORs, for example, at the circuit shown in FIG. 15, it is assumed that “stack 0 fault” being composed of faults f11, f12 f13 is the fault be detected. As confirmed by an test for faults to is realized by fault excitation and propagation on one time plane by allocating the following states. nsl_11=nsl_12=nsl_13=1 scan_1=scan_2=scan_3=0 Here, as preparation pattern the NSLs, or time are actually required. order to make it simple, at of the preparation pattern, when it is assumed the control the NSLs relating to at least entry is arbitrary, the test for the faults to f13 becomes a minimum test (ideal test) by two time planes (refer to FIG. 16 is a diagram an example of ideal at detection the faults to f13 at the entry #1 shown in FIG. 15. And 17 is a diagram showing an example of its worst a in which the compaction is executed at time the fault f11 is fault the the being all of the NSLs the indeterminate value X, is In the test generation the fault excitation and the fault propagation, the nsl_12=1, and nsl_13=1 can be decided uniquely an indispensable state by a unique path check. That is, at the of the state of the scan_1 for solving the eor_11 the D frontier, and states of the scan_2 and the scan_3 and the of n
 high “write” exclusiveness in tHe entry dirEctioN.
NeXt, iNeFficIencY to the pattern cOMpacTion is explained for each Of the FoLLowiNG tWo casEs. (1) is a caSE oF THe cOnTrOl iNvOLvEd in tHe cOmbinatIonal circuIt iNcLuding the XORS, AnD (2) is a case of The Control involVed In the RaM (rF) hAVing tHe hIgh wrIte excLUsivenEss in the eNtRY direcTIon.
For tHE CaSe (1) beIng with the control INvOLved in the combiNationAl CIrCUIt iNclUding the XOrs, For exAMple, at tHE cIRCUit SHown in FIG. 15, it is Assumed that “STacK at 0 fauLt” BeiNG compoSed of FaULts F11, f12 and f13 is the FaulT to be deteCted.
As COnfirmeD By obserVing, an IdeAl tEst fOR tHe FauLtS F11 to F13 Is ReaLIzeD by execuTiNg Fault ExciTATIOn anD prOpagAtion On one time planE by AlloCAtiNg the FolloWing StAtes.
nSl_11=nsl_12=nSl_13=1
scaN_1=sCan_2=scan_3=0
Here, as a pRepaRation patTerN fOr cOnTrollINg the NsLs, One Or more tIme planES arE aCTUAlLy required. However, iN oRDEr To make it Simple, AT tHe TIme planeS oF thE prePARatioN patTErN, when it iS assumED tHaT the conTrOl for tHe nSLS reLatinG To at Least oNe entry iS arbiTRary, the test for THe faults f11 to f13 bECoMES a MInimUm tEst (ideal tesT) by tWO timE plaNEs (RefER to FIg. 16).
FIG. 16 iS a DIaGRam showing an example Of An ideaL test At the detectioN of the faulTS F11 To f13 at the EntrY #1 ShOWn in FIG. 15. And FIG. 17 iS a diaGram showinG An examplE of itS worst teSt.
Here, a prOCEss, in whiCh tHe dYnaMic COMpAction is execuTED at tHe Time wheN thE fault f11 Is a PriMarY faUlT from the iNitial stAtE oF tHe CirCuit bEIng that aLl Of tHe nSLS are tHE indetErminAte vAlUe x, Is sTudied. IN ThE TEst gEnErAtioN foR tHe fauLt f11, aBOut The faulT excitatiOn aND the FaUlT propagAtion, the nsl_11=1, nsL_12=1, aNd nsl_13=1 can be DeCidEd uniqUELy as an inDispensable state by a uniqUE path chEck.
that iS, at tHe decisioN of The ATG, The STate of The scaN_1 for sOlVinG THe eor_11 BEInG thE D Frontier, anD THe sTates Of The sCan_2 and tHe scan_3 and the states OF thE n
 high “write” exclusivenes s in the e ntrydir ect io n.
N ext,  inefficiencyt o th e pattern compaction i s exp la i nedf or  each  of the fo l l owi ng  t woca s es . (1)  is  a case  of the co ntr ol  involved in th e combinat ion al circuit i ncl udingth e X O Rs, a nd(2) i s a ca s e of t he contro li nvolve d  in the R AM  (RF ) having the high wr i te exclusivene ss inth e  e n t rydir ection.
Fo rthe c a se (1)b ei n g wit h  the controlinvolved in the  combi na tio n al cir cuitin c lud ing the XOR s, f or exampl e, att he circ u it show n in F IG.  15 , it is  a ssu me d  th a t“st a ckat 0 fau lt ”being  com p o s e d of  fa ults  f11,  f12 and f13isthef aul t tobe de tect ed .
Asconfir med b yobserving, an i deal  test for  th efau lt s f11 to f13  is  re alizedby exec u tin gf a u lt  excitation and pr op a g at ion on o ne tim e  p la n e by all oc ati ng t h e  foll owin g  s tates.
n sl_11= n sl _1 2=nsl_1 3= 1
scan _1 =sc an_ 2=sca n _3=0 
Here,  as a pr epara t ion pattern fo r  controllingt he N SL s , on e o r more time  pla n es a re a c tu all y  requ ired.  H o we v er, in order to mak eit sim ple,at the time p lanes of t h e preparat ionp at t ern, when it i s ass umed thatt he contr ol fo r the NS Ls relati n g  to at l eas t o neent r y  i s arbitrary,t h e te st  for th e f aults f 11tof13  be co mes a min imum tes t(i de al  te st) b y  two tim epla ne s ( refer to FIG . 16) .
FI G.  1 6  is  a diag r am s howi ng  a n ex amp le  of a n id e altest at  the dete cti o n of  t he  faults  f11 to f13 a tthe entry#1  sh own in F IG. 15.And FIG. 17 is a diagra m  showin g a n exa mple  of its w ors t test .
H e re, aproces s, in  w hic h the d y n am icco mpaction i s exe cuted  a t th e timewhen the fault f11 isa primary fau ltfrom t he  in i ti a l s ta t e o f the circuit bei ng that al lo fthe NSLs a r e t he  indete rminate  valu e  X, isstudied.In the te st  gen e r ati on for the  fault f 11, about the f a ul t exc ita tion a nd  th e fau lt pro p aga tion,  the n sl _11=1,  nsl_ 12 =1, andnsl_13=1 can be decided  uniqu ely a s a n indispe nsa b lestate bya un ique pathche ck. 
That  is ,  at t he d e ci sio n  of t he A T G, the st a te  of t he  scan_1 for s o lvi ng th e e o r_11 b eing  the D frontier,a nd the statesof t h e  sc an_ 2  and  t he scan_3 andthe  s t a tes of t he  n
 high_“write” exclusiveness_in the entry direction.
Next,_inefficiency to_the_pattern compaction_is_explained for each_of the following_two cases. (1) is_a case of_the_control involved in the combinational circuit including the XORs, and (2) is a case_of_the control_involved_in_the RAM (RF) having the_high write exclusiveness in the_entry direction.
For_the case (1) being with the control involved_in_the combinational circuit_including the XORs, for example, at the circuit shown_in FIG. 15, it is assumed_that “stack at_0_fault”_being composed of faults_f11, f12 and f13 is the_fault to be detected.
As confirmed by_observing, an ideal test for the faults_f11 to f13 is realized by_executing fault excitation and propagation_on one_time plane by allocating the_following states.
nsl_11=nsl_12=nsl_13=1
scan_1=scan_2=scan_3=0
Here, as_a preparation_pattern for controlling_the NSLs, one or more time_planes are actually_required. However, in order to make_it_simple, at the_time_planes_of the_preparation pattern, when_it_is assumed_that_the control for the NSLs relating_to_at least one entry is arbitrary, the_test for the faults_f11_to f13 becomes a_minimum test (ideal test) by_two time planes (refer to FIG._16).
FIG. 16_is a_diagram showing an example of an ideal test at the detection_of the faults f11 to f13_at the entry #1_shown in_FIG._15. And FIG._17_is a_diagram showing an example of its worst_test.
Here, a_process, in which the dynamic compaction_is executed at the_time_when the fault f11 is a_primary fault from the initial state_of the circuit being that_all_of_the NSLs are the indeterminate_value X, is studied. In the_test generation for_the fault f11, about the fault excitation_and_the fault propagation, the nsl_11=1, nsl_12=1,_and_nsl_13=1 can be decided uniquely as_an_indispensable_state by a unique path_check.
That is, at the decision of_the ATG, the state of the scan_1 for solving_the eor_11 being_the D frontier, and the_states_of_the scan_2 and the scan_3 and the states of the_n