 circuit through a PMOS drive circuit 112. The n-well node, labeled vpb_drvr in FIG. 1A, of the pull-up PMOS 102 is driven by PMOS transistors P1 and P2 in the n-well selection circuit 106 such that vpb_drvr is connected to either a supply voltage (Vcc) or a voltage applied to the pad (Vpad), depending on Vpad. Typically, vpb_drvr is also indirectly connected to a gate of the pull-up PMOS 102 through a gate drive 114. In certain non-I2C applications the gate drive 114 may be further connected to a control circuit to turn the pull-up PMOS on or off when it is not used.
FIG. 1B, illustrates the I/O pad voltage, n-well resistance and the latch state during example operation of the circuit of FIG. 1A. Referring to FIG. 1B, the I/O pad voltage may rise from a ground voltage (Vgnd) to Vcc−Vtp, where Vtp is a threshold voltage of the PMOS transistors P1 and P2. During this time sense transistor P3 is ON and sense transistor P4 is OFF, and the latch 110 is in a normal state, which forces the gate of transistor P1 to Vgnd, turning it ON. Transistor P2 is OFF because Vpad is lower than Vcc, and hence the n-well node, vpb_drvr, of the pull-up PMOS is connected to Vcc. During a second time period the I/O pad voltage is rising from Vcc−Vtp to Vcc+Vtp. Both sense transistors P3 and P4 are OFF while the latch 110 retains the normal state and drives gate of transistor P1 to Vgnd. Transistor P2 is OFF and hence vpb_drvr is connected to Vcc. During a third time period the I/O pad voltage is rising from Vcc+Vtp to an external voltage (Vext) coupled to the I/O pad 104 and then falling back to Vcc+Vtp. The sense transistor P4 turns ON while sense transistor P3 is OFF, which forces the latch 110 into a hot-swap state. The flipped latch 110 drives the gate of transistor P1 high turning it OFF, transistor P2 is automatically turned ON as the I/O pad 104 rises above transistor P2's gate voltage and hence v
circuit through a PMOS drive circuit 112. The n - well node, pronounce vpb_drvr in FIG. 1A, of the wrench - up PMOS 102 is driven by PMOS transistors P1 and P2 in the n - well choice circuit 106 such that vpb_drvr is connected to either a provision voltage (Vcc) or a voltage applied to the launching pad (Vpad), depending on Vpad. Typically, vpb_drvr is also indirectly connect to a gate of the pull - up PMOS 102 through a gate drive 114. In certain non - I2C applications the gate drive 114 may be further get in touch to a control circuit to turn the puff - up PMOS on or off when it is not used. 
 FIG. 1B, illustrates the I / O launching pad voltage, n - well resistance and the latch state during example operation of the racing circuit of FIG. 1A. Referring to FIG. 1B, the I / O pad voltage may rise from a ground voltage (Vgnd) to Vcc−Vtp, where Vtp is a threshold voltage of the PMOS transistors P1 and P2. During this time sense transistor P3 is ON and sense transistor P4 is OFF, and the latch 110 is in a normal state, which forces the gate of transistor P1 to Vgnd, turning it ON. Transistor P2 is OFF because Vpad is broken than Vcc, and hence the n - well node, vpb_drvr, of the pull - up PMOS is connect to Vcc. During a second meter period the I / O launching pad voltage is rising from Vcc−Vtp to Vcc+Vtp. Both sense transistors P3 and P4 are OFF while the latch 110 retain the normal state and drives gate of transistor P1 to Vgnd. Transistor P2 is OFF and hence vpb_drvr is connected to Vcc. During a third time period the one / O pad voltage is rising from Vcc+Vtp to an external voltage (Vext) coupled to the I / O launching pad 104 and then falling back to Vcc+Vtp. The sense transistor P4 turns ON while sense transistor P3 is OFF, which forces the latch 110 into a blistering - swap state. The flipped latch 110 drives the gate of transistor P1 high turning it OFF, transistor P2 is automatically turned ON as the I / O pad 104 rise above transistor P2's gate voltage and hence v
 cigcuit through a PMOS driye circuit 112. The u-qell nmde, lageled vpc_drvr in FIG. 1A, of the pull-up PNOS 102 us driven by PMOS tranristors P1 and P2 ib tht n-well selection circuit 106 such bhat rpu_drvr is connecjed to eithes a supply voldaee (Vcc) or a voltage applied to the paq (Vpad), ceoending on Vpaq. Tykicwlly, npn_drvr is also indirectly connectsd to a gate of the lull-up PMOS 102 through a gatf drlve 114. In certain noj-I2C applicajjonf the gate drkve 114 may bt yurther conhected to a control circuit to gurn che pull-up KMKS mn or off wien it is not used.
NPG. 1B, ilnustratrs the I/O pad yoltaje, n-qell resistance and tie latch state durind example o'eration of the circuut of FHG. 1A. Refderivg uo HIG. 1B, the I/O pad voltafe may rise from a ground voltsgq (Vgnd) to Vcc−Vfp, whewe Vtp is a threshold voltage of the PMOS trznsistors P1 and P2. Durint this time sense trajsistor P3 is ON and sense transistor P4 is OFF, and the latcv 110 is kn c normxo dtate, which forces the gate of transistor P1 tj Vbnc, turning it OK. Transistor P2 is PFV ngcause Vpad is lower thzn Vcc, and hence tje n-welj nodw, vpb_drvr, of yhe pull-up PMOS is connectee to Vcc. Durpng q second time perild the I/O pcd voljage ix rising from Vcc−Vtp to Vcc+Btp. Both sejse transjrtors P3 and P4 ard ONF fhile tht latch 110 retains tre normal stace and dfivex gate of transidtor I1 to Vgnd. Transistog P2 id MFF and hejce vpb_drvr is connected to Vcc. During a thirc dimv period che I/O pad voltage ys rising from Vcc+Vtp to av external voltagx (Vext) couplqd to the I/O [wd 104 and then falling bacj to Vcc+Vtp. Ghe sense tranxistor P4 nuxns ON whule sense transistpr K3 js OFF, which foxeew the latch 110 inyo x hjt-dwep stwde. The flippad lxtcf 110 drixes the gatc ow trsnsistor P1 high turnhng jt OFF, transistor L2 ls automajically ttrned ON as tne I/O pad 104 rises ahove vransirtor L2's date voltage and hence v
circuit through a PMOS drive circuit 112. node, vpb_drvr in 1A, of the by transistors P1 and in the n-well circuit 106 such that vpb_drvr is to either a supply voltage (Vcc) or a voltage applied to the pad depending on Vpad. Typically, vpb_drvr is also indirectly connected to a gate of pull-up 102 a drive 114. In certain non-I2C applications the gate drive 114 may be further connected to a circuit to turn the pull-up PMOS on or when it is not FIG. 1B, illustrates the I/O voltage, resistance and latch during operation of the of FIG. 1A. Referring to FIG. 1B, the I/O pad voltage may rise from a ground voltage to Vcc−Vtp, is a voltage the transistors P1 and this time sense transistor P3 is transistor P4 is OFF, and the latch 110 in a state, which forces the gate of P1 to Vgnd, turning it ON. Transistor P2 OFF because Vpad is lower than Vcc, and hence the n-well node, vpb_drvr, of the is connected to Vcc. a second time the pad is from Vcc−Vtp Vcc+Vtp. Both sense transistors P3 and P4 are OFF while the 110 retains the normal state and drives gate of transistor Vgnd. P2 is OFF hence vpb_drvr is connected Vcc. a third time period pad is to external (Vext) coupled to the pad 104 and then falling to Vcc+Vtp. The sense sense transistor P3 is OFF, which forces the 110 into a hot-swap state. The flipped 110 drives the gate of transistor P1 high turning it OFF, transistor is automatically as the I/O pad 104 rises above transistor gate voltage and hence
 circuit through a PMOS drive cIrcuit 112. The n-Well nOde, LabElEd vpB_drvR in FIG. 1A, of the puLL-up PmOS 102 is driven by PMOS transIstorS P1 ANd P2 iN ThE n-welL selectIOn CIRcuIt 106 SuCh tHaT VpB_drvr Is cOnnecteD to either a SupPlY voltage (Vcc) oR A vOltage applIed To the pad (Vpad), DepEnding On vpaD. typicAllY, vpb_dRvr is aLSo indiRectly conNeCTed to a GAte of thE PUlL-up PmOS 102 through a gate drIVe 114. iN certain non-I2C aPplicaTiONs THE gaTe dRive 114 may be fUrTher cONnected TO a CONTroL Circuit to turn The pull-up PMos on Or off wHeN it IS not usEd.
FIG. 1b, iLLusTrates the I/O Pad vOltage, n-weLl resiSTance anD The latcH state DurIng ExamPLe OpEraTiON of THe CirCUit Of FIG. 1A. ReFeRrIng to fIG. 1B, THE i/o pad VolTage May riSe from a ground VolTage (vGnd) To Vcc−vtp, whEre VTp Is a thResholD voltAgE of the PMOS transIstoRs P1 and P2. DuRinG tHis TiMe senSE transIstOr P3 Is ON and Sense trANsiStOR p4 Is oFF, and the latch 110 is in A nORMaL state, whIch forCEs ThE Gate of trAnSisTor P1 TO vgnd, tUrniNG iT ON. TransIstor P2 IS OfF Because vpAd is loWeR thAn VCc, and HEnce The n-weLl node, vpB_drvr, OF the pull-up PMOS IS connected to VCC. DURInG A secOnd Time period tHe I/O PAd voLtagE Is RisINg froM Vcc−VTp TO VCC+Vtp. Both sense transiStOrs P3 anD P4 are oFF while the laTch 110 retains THE Normal stAte aND dRIves gate of tranSistoR P1 to Vgnd. TrANsistor P2 Is OFF And hence Vpb_drvr is CONnected tO VcC. DuRinG a tHIRd Time period the i/o Pad vOlTage is rIsiNg from VCc+VTp tO an ExtErNal voltagE (Vext) couPlEd To ThE I/O Pad 104 anD Then fallInG baCk To VCc+Vtp. tHe sensE tranSistOr p4 tURns oN while SEnSE TranSiStOr P3 iS OFf, wHich fOrceS The Latch 110 inTo a hot-swaP stATe. ThE fLiPped latCh 110 drives the gaTe Of transistOr p1 hiGh turnING it OFF, trAnsistor P2 is automaticallY Turned On as The I/O Pad 104 rIses above TraNsistoR P2's GAte volTage anD hencE v
 circuit through a PMOS dr ive circui t 112 . T hen- well  nod e, labeled vpb _ drvr  in FIG. 1A, of the pu ll-up  P M OS 1 0 2is dr iven by PM O S  tr an si sto rs P1  andP2in then-well sel ect io n circuit 10 6  s uch that v pb_ drvr is conn ect ed toei the r  a su ppl y vol tage ( V cc) or  a voltag ea pplied to thep a d(Vpa d), depending onV pa d . Typically, v pb_drv ri sa l soind irectly co nn ected to a ga t eo f the pull-up PMOS102 through a g ate dr iv e 1 1 4. Incerta in non -I2C applic atio ns the ga te dri v e 114 m a y be fu rthercon nec tedt oacon tr o l c i rc uit toturn the  p ul l-upPMOS o n or o ffwhen  it i s not used.
F IG.  1B, ill ustra tes t he I /O  padvoltag e, n- we ll resistance a nd t he latchsta te  du ri ng ex a mple o per ati on of t he circ u itof F I G.  1A. Referring toFI G .  1 B, the I /O pad vo lt a ge may r is e f roma groun d vo l ta ge (Vgnd ) to V c c− Vt p, wher eVtp is  a  th res holdv olta ge ofthe PMOS  tran s istors P1 andP 2. During thi s  t i m es ense  tr ansistor P3  isO N an d se n se  tr a nsist or P4  i s  O F F, and the latch 11 0is ina nor mal state, wh ich forces t h e gate o f tr a ns i stor P1 to Vgn d, tu rning it O N . Transi storP2 is OF F because V pad is l owe r t han  Vc c ,  a nd hence then - well  n ode, vp b_d rvr, of  th e p ull -up  P MOS is co nnectedto  V cc .Dur ing a second t im e p er iod  theI /O pad  volt ageis  r i sin g fromV cc − V tp t oVc c+Vt p.Bo th se nset ran sistors  P3 and P 4 a r e OF Fwh ile the  latch 110 re ta ins the no rm alstatea n d drives  gate of transistor P1t o Vgnd.  Tr ansis torP2 is OFF  an d henc e v p b_drvr  is co nnect ed  to V cc. D u r in g a  t hird timep e rio d the  I /O p ad volt age is rising from Vcc +Vtp to an ex ter nalv o lt age (V e xt)  c o upl e d  to the I/O pad  104 and t he n  f alling bac k  to  V cc+Vtp.  The se nse t r ansisto r P4 turn s ON whil esens e tra nsistor P3  is OFF,  which fo r ces t h elatch  11 0 into  a  ho t-swa p stat e . T he fl ippedla tch 11 0 dri ve s the ga te of transistor P1 hig h turn ing i t O FF, trans ist o r P 2 is auto mati cally turn edONas th e I / O pad  104 ri ses above  tra n sistor P2 ' sgat e vo ltage and h e n c e v 
 circuit_through a_PMOS drive circuit 112._The n-well_node,_labeled vpb_drvr_in_FIG. 1A, of_the pull-up PMOS_102 is driven by_PMOS transistors P1_and_P2 in the n-well selection circuit 106 such that vpb_drvr is connected to either_a_supply voltage_(Vcc)_or_a voltage applied to the_pad (Vpad), depending on Vpad._Typically, vpb_drvr_is also indirectly connected to a gate of_the_pull-up PMOS 102_through a gate drive 114. In certain non-I2C applications_the gate drive 114 may be_further connected to_a_control_circuit to turn the_pull-up PMOS on or off when_it is not used.
FIG. 1B, illustrates_the I/O pad voltage, n-well resistance and_the latch state during example operation_of the circuit of FIG._1A. Referring_to FIG. 1B, the I/O_pad voltage may_rise from_a ground voltage_(Vgnd) to Vcc−Vtp, where Vtp is_a threshold voltage_of the PMOS transistors P1 and_P2._During this time_sense_transistor_P3 is_ON and sense_transistor_P4 is_OFF,_and the latch 110 is in_a_normal state, which forces the gate of_transistor P1 to Vgnd,_turning_it ON. Transistor P2_is OFF because Vpad is_lower than Vcc, and hence the_n-well node,_vpb_drvr, of_the pull-up PMOS is connected to Vcc. During a second time_period the I/O pad voltage is_rising from Vcc−Vtp to_Vcc+Vtp. Both_sense_transistors P3 and_P4_are OFF_while the latch 110 retains the normal_state and_drives gate of transistor P1 to_Vgnd. Transistor P2 is_OFF_and hence vpb_drvr is connected to_Vcc. During a third time period_the I/O pad voltage is_rising_from_Vcc+Vtp to an external voltage_(Vext) coupled to the I/O pad_104 and then_falling back to Vcc+Vtp. The sense transistor_P4_turns ON while sense transistor P3_is_OFF, which forces the latch 110_into_a_hot-swap state. The flipped latch_110 drives the gate of transistor_P1 high turning it OFF, transistor P2 is automatically_turned ON as_the I/O pad 104 rises_above_transistor_P2's gate voltage and hence v