 made in the design of synthesizers, resulting in less than optimum performance of one or more frequency synthesizer characteristics. For instance, current frequency synthesizer noise reduction techniques are directed toward single frequency noise reduction, lack coherent spurious signals, or do not exploit the coherent spurious nature of the frequency synthesizer architecture if present. Disadvantageously, this creates a shortcoming in frequency synthesizers. For instance, in order to provide a frequency synthesizer having a small step size between adjacent output frequencies, a very low reference frequency is required. Using a very low reference frequency, however, limits the frequency range and extends the time required for the PLL to settle (or lock) once a new frequency has been selected.
Referring to FIG. 1, a prior art synthesizer 100 is shown. Synthesizer includes at least one phase locked loop which includes an input reference frequency 102, a modulated fractional divider (MFD) 104, a phase detector 106, a voltage controlled oscillator (VCO) 108, a mixer 110 and a divider 112. The phase detector 106 typically has an output coupled through a loop filter to control the frequency of the VCO 108. The output of the VCO 108 is fed back through a circuit, such as a divide by N circuit 112, to a first input of the phase detector 106. The frequency of the VCO 108 output signal is changed in steps by changing “N” of the divide-by-N circuit 112 in a known manner. At phase-lock, a synthesized output frequency 114 is proportional to the input frequency 102. A constant reference frequency signal is applied to a second input of the phase detector 106 by a crystal oscillator, for instance. A modulated fractional divider is utilized to provide fine frequency steps. However, this prior art circuitry is capable of providing non-coherent spurious signals on the modulated fractional divider.
Referring to FIG. 2, an additional prior art synthesizer is shown. Synthesizer 200 includes a single frequency source as an input reference frequency, a first divider 204, a phase detector 206, a VCO 208, a mixer 210 and a second divider 212. By utilizing a divider circuit 212 in the VCO feedback path and selectably controlling the division ratio, a variable frequency can be provided at the output of the frequency synthesizer. In this manner, the VCO output frequency 214 is divided by the selectable divisor, and the VCO output frequency is an exact multiple of the reference frequency. If the divisor N is
made in the design of synthesizers, resulting in less than optimum operation of one or more frequency synthesist characteristic. For instance, current frequency synthesizer randomness reduction proficiency are directed toward single frequency randomness decrease, lack coherent spurious signals, or do not exploit the coherent spurious nature of the frequency synthesizer computer architecture if present. Disadvantageously, this creates a shortcoming in frequency synthesizers. For case, in order to provide a frequency synthesizer having a small measure size between adjacent output frequencies, a very low reference book frequency is required. Using a very low reference frequency, however, restrict the frequency range and extends the time required for the PLL to settle (or lock in) once a new frequency has been selected. 
 Referring to FIG. 1, a prior art synthesizer 100 is shown. Synthesizer includes at least one phase locked loop which includes an input reference frequency 102, a modulated fractional divider (MFD) 104, a phase detector 106, a voltage controlled oscillator (VCO) 108, a sociable 110 and a divider 112. The phase detector 106 typically have an output copulate through a loop topology filter to control the frequency of the VCO 108. The output of the VCO 108 is fed back through a racing circuit, such as a divide by N circuit 112, to a first input of the phase detector 106. The frequency of the VCO 108 end product signal is changed in steps by changing “ N ” of the divide - by - N circuit 112 in a known manner. At phase - lock, a synthesized output signal frequency 114 is proportional to the input frequency 102. A constant reference frequency signal is applied to a second stimulation of the phase detector 106 by a crystal oscillator, for case. A modulated fractional divider is utilized to provide fine frequency step. However, this prior art circuitry is capable of provide non - coherent spurious signals on the modulated fractional divider. 
 refer to FIG. 2, an additional anterior art synthesizer is shown. Synthesizer 200 includes a single frequency beginning as an input character frequency, a first partition 204, a phase detector 206, a VCO 208, a mixer 210 and a second divider 212. By utilizing a divider circuit 212 in the VCO feedback path and selectably master the division ratio, a variable frequency can be provided at the output of the frequency synthesizer. In this manner, the VCO output frequency 214 is divided by the selectable divisor, and the VCO output frequency is an accurate multiple of the reference frequency. If the divisor N is
 mafe in the design of syntmesizers, resultiut in lxss thah optimuo performance of one or more feequebcy synthesizer characgeristics. For insranct, current frequenrg synthcfized noivx reduction tecmniques are directed towasd snngle frequency noise reduction, lack coheremt spurious signwls, pw do not exploit the coherent spurious nature of the frequrncy synthesizer architectkre lf present. Disadvajtageously, jgis xreates a shurtcoming pu frequency synthesizers. For instance, in ofder co provide q dreeoency synthewizer having a small step size brtween adjacenb out'ut drequencies, a very lox reference frequenci is requiseb. Using a very low redeeence frexuenzt, huwebec, ljmits hhe frequency range and wxtends the time reauygrd for the PML to feetle (or lock) once a new frequency has bten sslected.
Referring to FIG. 1, a prior art syntheslzer 100 is fhown. Synthesizer includes at least one phase locned lkup cmlch kbcpudes an input reference frequency 102, a modulatqs grsctional dividcr (MFD) 104, a phase deyeftpt 106, a voltage cuntrolled oscillator (VCO) 108, a mixer 110 and q divider 112. Thr phase detector 106 typically has an outplt ciupled through a llop filter co conjrol tne frequency of the VCO 108. Ths output of the VCO 108 ks fed back throjgh a circuit, such as a divide fy N circnit 112, co a firrt imput os the phasf detcwtor 106. The frequencj of jhe VCM 108 output dignal is changed in steps by cienging “N” of tne dinide-by-N cnrcuit 112 in a known ianner. At phasg-lock, a svntheskzed outpun frequenry 114 is propowtional to tha input frequxncy 102. A cjnstqnt eeferenzd frequency sibnal is aipjied to a second input of fhe phase deteccut 106 by a crystal osziljanor, fjs instance. A modjlagrd frxctional diyiddr ix utilized to provida fihe frequency steps. Hjwever, tyis priow art circuitty is capable of pgovidmng noi-coherrnt spurious signals on the modulzted frachiokal divider.
Reserrlng jo FIG. 2, an cdditional prior art synthesizer is showi. Synthesizer 200 includes a single frequency xource as ai inpue referenwe frequency, a first divider 204, a phase detector 206, a VCO 208, a mjxer 210 dnd a second divider 212. By utilizing a divider circuit 212 in the VCO feedback path and sxlqctably confrolking nhe bivisiog raviu, a variable freauency can be provided at the ontput of tve frequency synthesizer. In thos manner, the VZO output frequency 214 is sivided ny the selectable divisor, and tne VCO output frequency ls an exaxt mumtiple of vhe reference frequemcy. If the eivisor N id
made in the design of synthesizers, resulting than performance of or more frequency frequency noise reduction techniques directed toward single noise reduction, lack coherent spurious signals, do not exploit the coherent spurious nature of the frequency synthesizer architecture if Disadvantageously, this creates a shortcoming in frequency synthesizers. For instance, in order to a synthesizer a step size between adjacent output frequencies, a very low reference frequency is required. Using a very reference frequency, however, limits the frequency range and the time required for PLL to settle (or lock) a frequency has selected. to 1, a prior synthesizer 100 is shown. Synthesizer includes at least one phase locked loop which includes an input reference 102, a divider (MFD) a detector a voltage controlled 108, a mixer 110 and a phase detector 106 typically has an output coupled a loop to control the frequency of the 108. The output of the VCO 108 is back through a circuit, such as a divide by N circuit 112, to a first the phase detector 106. frequency of the 108 signal changed steps by “N” of the divide-by-N circuit 112 in a known manner. At a synthesized output frequency 114 is proportional to the input A reference frequency signal applied to a second of phase detector 106 by oscillator, instance. divider utilized provide fine frequency steps. this prior art circuitry is of providing non-coherent spurious divider. Referring to FIG. 2, an additional prior synthesizer is shown. Synthesizer 200 includes a frequency source as an input reference frequency, a first divider 204, a detector 206, 208, a mixer 210 and a second divider By utilizing a divider 212 in the VCO feedback path and selectably controlling division a variable can be provided the output of frequency synthesizer. In the VCO frequency is selectable divisor, and the VCO output is exact multiple of the reference If N is
 made in the design of synthesiZers, resultIng in LesS thAn OptiMum pErformance of onE Or moRe frequency synthesizer CharaCtERistICs. for inStance, cURrENT frEqUeNcy SyNThEsizeR noIse reduCtion technIquEs Are directed tOWaRd single frEquEncy noise redUctIon, lacK cOheREnt spUriOus siGnals, oR Do not eXploit the CoHErent sPUrious nATUrE of tHe frequency syntheSIzER architecture iF preseNt. dIsADVanTagEously, this CrEates A ShortcoMInG IN FreQUency synthesiZers. For instANce, In ordeR tO prOVide a fRequeNcY SynThesizer havIng a Small step Size beTWeen adjACent outPut freQueNciEs, a vERy LoW reFeREncE FrEquENcy Is requirEd. usIng a vEry lOW REFereNce FreqUency, However, limits The FreqUEncY rangE and eXtenDs The tiMe requIred fOr The PLL to settle (oR locK) once a new FreQuEncY hAs beeN SelectEd.
REfeRring to fIG. 1, a priOR arT sYNTHeSizer 100 is shown. SyntheSiZER iNcludes aT least ONe PhASe locked LoOp wHich INCludeS an iNPuT referenCe freqUEnCy 102, A modulaTeD fractIoNal DivIder (Mfd) 104, a phAse detEctor 106, a voLtage COntrolled oscilLAtor (VCO) 108, a mixer 110 ANd A DIvIDer 112. THe pHase detectoR 106 typICallY has AN oUtpUT coupLed thRoUGh A Loop filter to control ThE frequEncy oF the VCO 108. The outPut of the VCo 108 IS Fed back tHrouGH a CIrcuit, such as a dIvide By N circuit 112, TO a first iNput oF the phasE detector 106. tHE frequenCy oF thE VCo 108 ouTPUt Signal is changED In stEpS by chanGinG “N” of the DivIde-By-N CirCuIt 112 in a knowN manner. AT pHaSe-LoCk, a SynthESized outPuT frEqUenCy 114 is pROportiOnal tO the InPuT FreQuency 102. A COnSTAnt rEfErEnce FreQuEncy sIgnaL Is aPplied tO a second iNpuT Of thE pHaSe detecTor 106 by a crystal OsCillator, foR iNstAnce. A mODUlated frActional divider is utilizED to provIde Fine fRequEncy steps. howEver, thIs pRIor art CircuiTry is CaPabLE Of proVIDiNg nOn-Coherent spURIouS signAlS on tHe modulAted fractional diviDEr.
REferring to FIG. 2, An aDditIONaL prIOr ARt sYnTHesIZEr is shown. SyntheSizer 200 incluDeS A sIngle frequENcy SoUrce as aN input rEfereNCe frequEncy, a firsT divider 204, a PhAse dETEctOr 206, a VCO 208, a mixEr 210 and a seCond dividER 212. By utILiZing a DivIder ciRcUit 212 In the vCO feeDBacK path And selEcTably cOntroLlIng the diVision ratio, a variable freQuency Can be ProVided at thE ouTPut Of the freqUencY synthesizEr. IN thIs manNer, THe VCO OutpUT fReqUEncy 214 iS divIDed by the sELeCtaBLE dIvisor, and thE vco ouTput fReqUEncy is An exAct multiple of the rEFerence frequenCy. If THE diVisOR N is
 made in the design of syn thesizers,  resu lti ngin  les s th an optimum per f orma nce of one or more fre quenc ys ynth e si zer c haracte r is t i cs.  F or  in st a nc e, cu rre nt freq uency synt hes iz er noise red u ct ion techni que s are direct edtoward  s ing l e fre que ncy n oise r e ductio n, lack c oh e rent s p uriouss i gn als,  or do not exploi t  t h e coherent spu riousna t ur e ofthe  frequency  s ynthe s izer ar c hi t e c tur e  if present.Disadvantag e ous ly, th is  cr e ates a  shor tc o min g in freque ncysynthesiz ers. F o r insta n ce, inordertopro vide afr equ en c y s y nt hes i zer  havingasm all s teps i z e  bet wee n ad jacen t output freq uen cies ,  averylow r efer en ce fr equenc y isre quired. Using a  ver y low ref ere nc e f re quenc y , howe ver , l imits t he freq u enc yr a n ge  and extends the t im e re quired f or the PL Lt o settle  ( orlock ) oncea ne w  f requency  has b e en  s elected .Referr in g t o F IG. 1 ,  a p rior a rt synth esize r  100 is shown. Synthesizer i n cl u d es at l eas t one phase  loc k ed l oopw hi chi nclud es an  i n pu t  reference frequenc y102, a  modu lated fractio nal divide r ( MFD) 104 , ap ha s e detector 106 , a v oltage con t rolled o scill ator (VC O) 108, a m ixer 110  an d a  di vid e r  1 12. The phase d etec to r 106 t ypi cally h asanout put  c oupled th rough alo op  f il ter  to c o ntrol th efre qu enc y oft he VCO  108.  The  o ut p utof theV CO 1 08 i sfe d ba ckth rough  a c i rcu it, suc h as a di vid e  byNci rcuit 1 12, to a firs tinput of t he  ph ase de t e ctor 106 . The frequency of theV CO 108out put s igna l is chan ged  in st eps by cha nging“N” o fthe d ivide - b y- N c ir cuit 112 i n a k nownma nner . At ph ase-lock, a synthe s ize d output freq uen cy 1 1 4  i s p r op o rti on a l t o the input frequ ency 102.Ac on stant refe r enc efrequen cy sign al is applied  to a sec ond input  o f th e pha se detecto r 106 by  a crysta l  osci l la tor,for  insta nc e.A mod ulated fra ction al div id er isutili ze d to pro vide fine frequency ste ps. Ho wever , t his prior  ar t  ci rcuitry i s ca pable of p rov idi ng no n-c o heren t sp u ri ous signa ls o n  the modu l at edf r ac tional divi d e r .
R eferr ing to FIG . 2,  an additional pr i or art synthes izer i s s how n . Sy nt hesizer 200 in clu de s a single  f requency so urce asan input  refer ence f requenc y ,  a firstdivi der  204, a p has ed etector  2 06 ,  a VCO  208 ,a mixe r 210a nd a s econd divider 21 2. By u tiliz i nga div id er circ u it 2 12 in theVCO feedbac k path  and  sele ctablyco ntroll ing  t he divisio n  ratio, a  vari able fr eq uenc y c an beprov i d ed at  the  o utp ut of the f re q ue nc y  sy nthe sizer .In t his manne r , the VC O o u tput fr eq uen c y  214 i s  d i v ided by th e s elect a b le divisor ,  and th e  VCOoutput  frequ ency is anex act mul tip l e  of the r eferencef req ue ncy.  If thedi viso rN i s
 made_in the_design of synthesizers, resulting_in less_than_optimum performance_of_one or more_frequency synthesizer characteristics._For instance, current frequency_synthesizer noise reduction_techniques_are directed toward single frequency noise reduction, lack coherent spurious signals, or do not_exploit_the coherent_spurious_nature_of the frequency synthesizer architecture_if present. Disadvantageously, this creates_a shortcoming_in frequency synthesizers. For instance, in order to_provide_a frequency synthesizer_having a small step size between adjacent output frequencies,_a very low reference frequency is_required. Using a_very_low_reference frequency, however, limits_the frequency range and extends the_time required for the PLL to_settle (or lock) once a new frequency_has been selected.
Referring to FIG. 1,_a prior art synthesizer 100_is shown._Synthesizer includes at least one_phase locked loop_which includes_an input reference_frequency 102, a modulated fractional divider_(MFD) 104, a_phase detector 106, a voltage controlled_oscillator_(VCO) 108, a_mixer_110_and a_divider 112. The_phase_detector 106_typically_has an output coupled through a_loop_filter to control the frequency of the_VCO 108. The output_of_the VCO 108 is_fed back through a circuit,_such as a divide by N_circuit 112,_to a_first input of the phase detector 106. The frequency of the_VCO 108 output signal is changed_in steps by changing_“N” of_the_divide-by-N circuit 112_in_a known_manner. At phase-lock, a synthesized output frequency_114 is_proportional to the input frequency 102._A constant reference frequency_signal_is applied to a second input_of the phase detector 106 by_a crystal oscillator, for instance._A_modulated_fractional divider is utilized to_provide fine frequency steps. However, this_prior art circuitry_is capable of providing non-coherent spurious signals_on_the modulated fractional divider.
Referring to FIG._2,_an additional prior art synthesizer is_shown._Synthesizer_200 includes a single frequency_source as an input reference frequency,_a first divider 204, a phase detector 206, a_VCO 208, a_mixer 210 and a second_divider_212._By utilizing a divider circuit 212 in the VCO feedback_path and_selectably controlling the_division ratio, a variable frequency can be provided at the_output of the frequency synthesizer. In this_manner, the VCO output frequency 214 is divided by the selectable_divisor, and the VCO output frequency is an_exact multiple of the reference frequency. If_the divisor N is