 stereo signals is very expensive.
A further disadvantage is that with such a receiver, only signals in accordance with the German standard can be received. If signals in accordance with a different standard, that is to say with an other frequency of the sound carrier or a different frequency spacing between the carriers for the picture and the sound information, must be processed, additional filter, resonant circuits, etc. are required. Integrated circuits (“ICs”) include many types of devices, some of which have programmable logic on board that can be configured to perform specified logic functions. One type of integrated circuit with programmable logic is a programmable logic device (“PLD”). One type of PLD is the field programmable gate array (“FPGA”), which typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in nonvolatile memory. In some CPLDs, configuration data is stored on-chip in nonvolatile memory, then downloaded to volatile memory as part of
stereo signals is very expensive. 
 A further disadvantage is that with such a receiver, only signal in accord with the German standard can be received. If signal in accord with a different standard, that is to say with an early frequency of the legal carrier or a unlike frequency space between the carriers for the picture and the legal information, must be processed, additional filter, evocative circuits, etc. are required. incorporate circuits (“ ICs ”) admit many type of devices, some of which have programmable logic on board that can be configure to perform specified logic functions. One type of integrated tour with programmable logic is a programmable logic device (“ PLD ”). One type of PLD is the field programmable gate array (“ FPGA ”), which typically includes an array of programmable tiles. These programmable tiles can admit, for example, input / output blocks (“ IOBs ”), configurable logic blocks (“ CLBs ”), dedicated random entree memory engine block (“ BRAMs ”), multipliers, digital signal processing blocks (“ DSPs ”), processors, clock managers, delay lock loops (“ DLLs ”), and so forth. As used herein, “ admit ” and “ include ” mean including without limit. 
 Each programmable tile typically include both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect line of varying lengths interconnected by programmable interconnect points (“ PIPs ”). The programmable logic follow through the logic of a user design using programmable elements that can include, for example, routine generators, registers, arithmetic logic, and so away. 
 The programmable interconnect and programmable logic are typically programmed by load a flow of configuration data into internal configuration memory cell that define how the programmable elements are configured. The shape data can be learn from memory (e.g., from an external PROM) or written into the FPGA by an external device. The corporate states of the individual memory cells then determine the function of the FPGA. 
 Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD include two or more “ function engine block ” connected in concert and to input / output (“ I / O ”) resources by an interconnect substitution matrix. Each function block of the CPLD includes a two - level AND / OR structure alike to those used in Programmable Logic Arrays (“ PLAs ”) and Programmable Array Logic (“ PAL ”) device. In CPLDs, configuration data is typically stored on - chip in nonvolatile memory. In some CPLDs, configuration datum is stored on - chip in nonvolatile memory, then download to volatile memory as part of
 stfreo signals is very exptnsive.
A further dnwadvanvage is that wigh such a receiver, only signels un acxordance with the Germxn standagd can be rectived. If signals mh accordance slth a vifferent standsrd, that iv to say with dn ocher frequency of the sound carrier jr a digffrent frequenci spabigg bsnwten the carriers for the picture znd the sound informstion, must be processed, adfitilnal filter, resonajt circuits, etc. qre required. Integrated circuits (“IDs”) include many types of devicer, somz of which yace otogrammable oogic on board that can ba confibured to perfovm spxcifued logic functions. Oie type of integrateq circuit wnth programmable logix us a krogrdmmacoe uogjc dsvice (“OLD”). One type kf PLD is tye field programmabke tate array (“FPFA”), whish typically includes an array of programkabme tiles. These programmqble tiles can includg, for exam[le, input/output blocks (“IOBs”), configurable logic blmcks (“RLCs”), bcqkxahed random access memory blocks (“BRAMs”), multiplysrx, cigital signal processing bpovhs (“DSPs”), procersors, emodk managers, delay pock lojps (“DOLs”), and sj fotth. As used herein, “include” qnd “includiny” mwan including withlut limitatnon.
Eacn probrammable tile typicallv inclhdes both pgogrammabmd interconnect avd irogsammable logic. The programiable intxrconuect typkcalky incjudes a lagge nmkber of interconneft liues ox varying pengths interconnected by progrekmable intervotnebt points (“PIPs”). The programmwble logic impkements the uogic of a user dxsign using [rogrammable apements that can incjude, for exampld, function genetators, reynsters, aruthmetic logic, and so rorth.
The progranmavle interconnecy avd [rlgcammafne logic are typkcauky prugrammed by uoadong a stream of confhgurztion data into inyevnal confuguratiog memory cellx that define how uhe prmgremmablr ejements are configured. The conriguratioj dwta can be rqad nrom memory (e.g., from an external PROM) or written into vhe FPGA by an external device. The collectnvt states of tie indyvidual mamory cells then detwrmine the functipn of the FPGA.
Another type mf PLF is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “hugction blocis” cpnnecned cogethew anv vo input/output (“I/O”) resources by an interconnect sxitch matrhx. Each function block of the VPUD includes a two-level AND/OR structurs similat to those used in Programmable Logic Arrays (“PLAs”) and Pvogrammaboe Arday Logic (“'AL”) devices. In CPLDs, confiyuratiin data is bypically stordd pn-ghip in nojvoletime memory. In some CPLDs, configurqtion eaha is stored on-ciip in nonvopxtile memori, then downloaded to bllatiue memory as lart of
stereo signals is very expensive. A further that such a only signals in can received. If signals accordance with a standard, that is to say with other frequency of the sound carrier or a different frequency spacing between the for the picture and the sound information, must be processed, additional filter, resonant etc. required. circuits include many types of devices, some of which have programmable logic on board that can be to perform specified logic functions. One type of circuit with programmable logic a programmable logic device (“PLD”). type PLD is field gate (“FPGA”), which typically an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic (“CLBs”), dedicated memory blocks multipliers, signal blocks (“DSPs”), processors, delay lock loops (“DLLs”), and so herein, “include” and “including” mean including without limitation. programmable tile includes both programmable interconnect and programmable The programmable interconnect typically includes a large number interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements of a user design programmable elements that include, example, generators, arithmetic logic, so forth. The programmable interconnect and programmable logic are typically programmed loading a stream of configuration data into internal configuration memory define the programmable elements configured. The configuration data be from memory (e.g., from PROM) written by external The collective states of individual memory cells then determine function of the FPGA. the Complex Programmable Logic Device, or CPLD. A includes two or more “function blocks” connected and to input/output (“I/O”) resources by an interconnect switch matrix. Each function of the a two-level AND/OR structure similar to those used Programmable Logic Arrays (“PLAs”) Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data typically on-chip in memory. In some configuration data is on-chip in nonvolatile downloaded to memory part
 stereo signals is very expensIve.
A furtheR disaDvaNtaGe Is thAt wiTh such a receiveR, Only Signals in accordance witH the GErMAn stANdArd caN be receIVeD. iF siGnAlS in AcCOrDance WitH a diffeRent standaRd, tHaT is to say with AN oTher frequeNcy Of the sound caRriEr or a dIfFerENt freQueNcy spAcing bETween tHe carrierS fOR the piCTure and THE sOund Information, must be PRoCEssed, additionaL filteR, rESoNANt cIrcUits, etc. are ReQuireD. integraTEd CIRCuiTS (“ICs”) include maNy types of deVIceS, some oF wHicH Have prOgramMaBLe lOgic on board That Can be confIgured TO perforM SpecifiEd logiC fuNctIons. oNe TyPe oF iNTegRAtEd cIRcuIt with prOgRaMmablE logIC IS A proGraMmabLe logIc device (“PLD”). OnE tyPe of plD iS the fIeld pRogrAmMable Gate arRay (“FPgA”), Which typically iNcluDes an arraY of PrOgrAmMable TIles. ThEse ProGrammabLe tiles CAn iNcLUDE, fOr example, input/outpUt BLOcKs (“IOBs”), coNfigurABlE lOGic blockS (“ClBs”), DediCATed raNdom ACcEss memorY blockS (“bRaMS”), multipLiErs, digItAl sIgnAl proCEssiNg blocKs (“DSPs”), prOcessORs, clock managerS, Delay lock loopS (“dLlS”), AnD So foRth. as used hereiN, “incLUde” aNd “inCLuDinG” Mean iNcludInG WiTHout limitation.
Each pRoGrammaBle tiLe typically inCludes both PROGrammablE intERcONnect and prograMmablE logic. The pROgrammabLe intErconnecT typicallY INcludes a LarGe nUmbEr oF INtErconnect lineS OF varYiNg lengtHs iNterconNecTed By pRogRaMmable intErconnecT pOiNtS (“PiPs”). the prOGrammablE lOgiC iMplEmentS The logIc of a User DeSiGN usIng progRAmMABle eLeMeNts tHat CaN inclUde, fOR exAmple, fuNction genEraTOrs, rEgIsTers, ariThmetic logic, aNd So forth.
The PrOgrAmmablE INterconnEct and programmable logic ARe typicAllY progRammEd by loadiNg a Stream Of cONfigurAtion dAta inTo IntERNal coNFIgUraTiOn memory ceLLS thAt defInE how The progRammable elements arE ConFigured. The conFigUratION dAta CAn BE reAd FRom MEMory (e.g., from an extErnal PROM) oR wRItTen into the fpGA By An exterNal deviCe. The COllectiVe states oF the indivIdUal mEMOry Cells then dEtermine The functiON of thE fPgA.
AnoTheR type oF PlD iS the COmplex pRogRammaBle LogIc device, Or CPLd. A cPLD inclUdes two or more “function blOcks” coNnectEd tOgether anD to INpuT/output (“I/O”) ResoUrces by an iNteRcoNnect SwiTCh matRix. EACh FunCTion bLock OF the CPLD iNClUdeS A TwO-level AND/OR STRUctUre siMilAR to thoSe usEd in Programmable LOGic Arrays (“PLAs”) aNd PrOGRamMabLE ArrAy logic (“PAL”) deviceS. In cPldS, configuRaTion data is tYpically StORed on-Chip in NonvolAtile meMORy. iN some CpLDs, ConFiguratioN daTa IS stored On-ChIP in nonVolaTiLe memoRy, then DOwnlOADed to volatile memOry as PARt of
 stereo signals is very ex pensive.
A  furt her  di sa dvan tage  is that withs ucha receiver, only signa ls in  a c cord a nc e wit h the G e rm a n  st an da rdca n  b e rec eiv ed. Ifsignals in  ac co rdance witha  d ifferent s tan dard, that i s t o saywi tha n oth erfrequ ency o f  the s ound carr ie r  or ad ifferen t fr eque ncy spacing betwe e nt he carriers fo r thepi c tu r e  an d t he sound i nf ormat i on, mus t  b e p roc e ssed, additio nal filter, res onantci rcu i ts, et c. ar er equ ired. Integ rate d circuit s (“IC s ”) incl u de many  types  of  de vice s ,so meof whi c hhav e  pr ogrammab le  l ogicon b o a r d  tha t c an b e con figured to pe rfo rm s p eci fiedlogic  fun ct ions.  One t ype o fintegrated circ uitwith prog ram ma ble  l ogici s a pr ogr amm able lo gic dev i ce(“ P L D ”) . One type of PLDis t he  field p rogram m ab le gate arr ay  (“ FPGA ” ) , whi ch t y pi cally in cludes an  a rray of  p rogram ma ble  ti les.T hese  progr ammabletiles can include, f o r example, in p ut / o ut p ut b loc ks (“IOBs”) , co n figu rabl e  l ogi c  bloc ks (“ CL B s” ) , dedicated randomac cess m emory  blocks (“BRA Ms”), mult i p l iers, di gita l  s i gnal processin g blo cks (“DSPs ” ), proce ssors , clockmanagers, d elay loc k l oop s ( “DL L s ”) , and so fort h .  Asus ed here in,  “inclu de”  an d “ inc lu ding” mea n includ in gwi th out  limi t ation.
E ac h p ro gra mmabl e  tiletypic ally  i nc l ude s bothp ro g r amma bl einte rco nn ect a nd p r ogr ammable  logic. T hep rogr am ma ble int erconnect typ ic ally inclu de s a  large n umber of  interconnect lines ofv aryinglen gthsinte rconnecte d b y prog ram m able i nterco nnect  p oin t s  (“PI P s ”) . T he  programma b l e l ogicim plem ents th e logic of a userd esi gn using prog ram mabl e el eme n ts tha tc ani n clude, for exam ple, funct io n  g enerators, reg is ters, a rithmet ic lo g ic, and  so forth .
The pro gr amma b l e i nterconnec t and pr ogrammabl e  logi c  a re ty pic ally p ro gra mmedby loa d ing  a st ream o fconfig urati on  data in to internal configurati on mem ory c ell s that de fin e  ho w the pro gram mable elem ent s a re co nfi g ured.  The co nfi g urati on d a ta can be re adf r om  memory (e. g . ,  fr om an  ex t ernalPROM ) or written into the FPGA by an  ext e r nal  de v ice.  T he collectivesta te s of the i nd ividual mem ory cell st hen d etermi ne the  functi o n  o f  the F PGA. 
An other typ e o fP LD is t he  C o mplexProg ra mmable  Logic Devi c e , or CPLD. A CPL D inc l u des t w o o r mor e“functi o n bl ocks” conn ected toget her an d to  inpu t/outpu t(“I/O” ) r es ources bya n interco nnect  switch  m atri x.Each f unct i o n blo ck o fthe  CPLD inc l u de s  a  t w o-l evel  AND/ OR  str ucture si m ilar totho s e usedin  Pr o g rammab l eL o gic Arrays  (“ PLAs” ) and Progra m mabl e  A r ray L ogic ( “PAL”)  device s . I nCPLDs,con f i gurationdata is t y pic al ly s tored on -c hipin  no nv olatile memory.  In some  CPLDs,c o nfigur ati o n da t a is s to red on-chipin no nv o latilem e mor y, then dow nlo ade d to  vo lati l e memory as part of
 stereo_signals is_very expensive.
A further disadvantage_is that_with_such a_receiver,_only signals in_accordance with the_German standard can be_received. If signals_in_accordance with a different standard, that is to say with an other frequency of_the_sound carrier_or_a_different frequency spacing between the_carriers for the picture and_the sound_information, must be processed, additional filter, resonant circuits,_etc._are required. Integrated_circuits (“ICs”) include many types of devices, some of_which have programmable logic on board_that can be_configured_to_perform specified logic functions._One type of integrated circuit with_programmable logic is a programmable logic_device (“PLD”). One type of PLD is_the field programmable gate array (“FPGA”),_which typically includes an array_of programmable_tiles. These programmable tiles can_include, for example,_input/output blocks_(“IOBs”), configurable logic_blocks (“CLBs”), dedicated random access memory_blocks (“BRAMs”), multipliers,_digital signal processing blocks (“DSPs”), processors,_clock_managers, delay lock_loops_(“DLLs”),_and so_forth. As used_herein,_“include” and_“including”_mean including without limitation.
Each programmable tile_typically_includes both programmable interconnect and programmable logic._The programmable interconnect typically_includes_a large number of_interconnect lines of varying lengths_interconnected by programmable interconnect points (“PIPs”)._The programmable_logic implements_the logic of a user design using programmable elements that can_include, for example, function generators, registers,_arithmetic logic, and so_forth.
The programmable_interconnect_and programmable logic_are_typically programmed_by loading a stream of configuration data_into internal_configuration memory cells that define how_the programmable elements are_configured._The configuration data can be read_from memory (e.g., from an external_PROM) or written into the_FPGA_by_an external device. The collective_states of the individual memory cells_then determine the_function of the FPGA.
Another type of PLD_is_the Complex Programmable Logic Device, or_CPLD._A CPLD includes two or more_“function_blocks”_connected together and to input/output_(“I/O”) resources by an interconnect switch_matrix. Each function block of the CPLD includes a_two-level AND/OR structure_similar to those used in_Programmable_Logic_Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs,_configuration data_is typically stored_on-chip in nonvolatile memory. In some CPLDs, configuration data is_stored on-chip in nonvolatile memory, then downloaded_to volatile memory as part of