 the other hand, in the semiconductor memory device such as a DRAM which store information in a memory cell capacitor in the form of electric charges, it should be noted that excessive device miniaturization causes a decrease in the electric charges held in the memory cell capacitor due to the decrease of the memory cell capacitance. Thereby, stable retention of information tends to become difficult. While it is possible to compensate for such a decrease of the capacitance to some extent by reducing the thickness of the capacitor insulation film, it is necessary to reduce the thickness of the capacitor insulation film to the order of several nanometers or less in the DRAMs of sub-micron or sub-quarter micron size, as long as a conventional SiO.sub.2 film or an SiN film is used for the capacitor insulation film. As will be easily understood, formation of such an extremely thin capacitor insulation film is difficult, as it is required in a capacitor that the capacitor insulation film is perfectly free from defects such as pin holes. Further, the use of such a thin capacitor insulation film tends to cause the problem of increased tunneling leakage current.
Meanwhile, it has been proposed to use a Ta.sub.2 O.sub.5 film for the capacitor insulation film of a DRAM memory cell capacitor.
FIGS. 1A-1D show the fabrication process of a MIS capacitor that uses a conventional Ta.sub.2 O.sub.5 capacitor insulation film.
Referring to FIG. 1A, a capacitor region is defined on a Si substrate 11 by a field oxide film 12, and a polysilicon pattern 13 and an SiN pattern 14 are formed on the foregoing capacitor region in the step of FIG. 1B by depositing a polysilicon film and an SiN film consecutively and further by applying a patterning process, wherein the polysilicon pattern 13 forms a lower electrode of the capacitor. Typically, the SiN pattern 14 is formed with a thickness of 2 nm.
Next, in the step of FIG. 1C, a Ta.sub.2 O.sub.5 film is deposited on the structure of FIG. 1B typically with a thickness of about 8 nm, followed by a patterning process to form a Ta.sub.2 O.sub.5 capacitor insulation film 15. Further, the step FIG. 1D is conducted in which an upper electrode pattern 16 of Pt, and the like, is formed on the capacitor insulation film 15.
Because Ta.sub.2 O.sub.5 is a
the other hand, in the semiconductor memory device such as a DRAM which store data in a memory cellular telephone capacitor in the phase of electric charges, it should be noted that excessive device miniaturization induce a decrease in the electric charges held in the memory cellular telephone capacitor due to the decrease of the memory cell capacitance. Thereby, stable memory of information tends to become unmanageable. While it is possible to compensate for such a decrease of the capacitance to some extent by reducing the thickness of the capacitor insulating material film, it is necessary to reduce the thickness of the capacitor insulating material film to the orderliness of several nanometers or less in the DRAMs of sub - micron or sub - stern micron size, as long as a conventional SiO.sub.2 film or an SiN film is use for the capacitor insulation film. As will be easily understood, formation of such an highly thin capacitor insulation film is difficult, as it is required in a capacitor that the capacitor insulation movie is absolutely barren from defects such as pin holes. Further, the use of such a thin capacitor insulation film tend to cause the problem of increase tunneling escape stream. 
 Meanwhile, it has been proposed to use a Ta.sub.2 O.sub.5 film for the capacitor insulation film of a DRAM memory cell capacitor. 
 FIGS. 1A-1D show the fabrication procedure of a MIS capacitor that uses a conventional Ta.sub.2 O.sub.5 capacitor insulation film. 
 Referring to FIG. 1A, a capacitor region is define on a Si substrate 11 by a field oxide film 12, and a polysilicon pattern 13 and an SiN pattern 14 are formed on the predate capacitor region in the step of FIG. 1B by depositing a polysilicon film and an SiN film consecutively and far by applying a patterning process, wherein the polysilicon pattern 13 forms a lower electrode of the capacitor. Typically, the SiN pattern 14 is formed with a thickness of 2 new mexico. 
 Next, in the step of FIG. 1C, a Ta.sub.2 O.sub.5 movie is deposited on the structure of FIG. 1B typically with a thickness of about 8 nm, followed by a patterning procedure to form a Ta.sub.2 O.sub.5 capacitor insulating material film 15. Further, the gradation FIG. 1D is conducted in which an upper electrode pattern 16 of Pt, and the comparable, is formed on the capacitor insulating material film 15. 
 Because Ta.sub.2 O.sub.5 is a
 thf other hand, in the semigonductor memory device such zs a DRAO which store information in a memoey cell capacitor in tfe form ov electruc ciarges, it should be noted that cxcesvmve device ministurizatiot causes a decsexsz in the electric charges held in thq memoru fell capacitor due eo tgv becrease of the memory cell capzcitanct. Thereby, stable rrtention of information tejds ho become difficulh. While it us pjwsible to coopensate for such a dedrease of the capacitance to sooe excent by redoeung jhe thicknesw of nhe capacitor insulathon filk, it is necesssry to reduce the thickness of the capacitor ynsulatiot yilm to the order of weceral nanmmetdes ur mexs in thf DCAMs of sub-jicron or syb-quarter micron siee, ww long as a cknventyogal SiO.sub.2 film or an SiN film is used xor the capacitor insulatiin film. As will be eadily undewstood, formation of such an extremely thin capacidor iisjlauiin fiun ls difficult, as it is required in a capacitor fhst the capacitor insulation fllk is perfectly free ydoj defects such as oin holgs. Furrher, the tse pf such a thin capacitor inwulation fili tends to cause thz problem of incteased tunneling leakage currznt.
Meahwhile, it hws been pduposed to use a Ga.slb.2 O.vub.5 film for the capacitor insulatiin fnlm of a DRAK memowy cell caoacitor.
FIGS. 1A-1D show the vabrieatiot process lf a MIS capacitor that uses a rpnventional Ja.sgb.2 M.sub.5 capccitor insulation fylm.
Referring tp FIG. 1A, a caoacitor refion is defined on a Si substradg 11 by a field oxide fylm 12, and a polyrklicon pattern 13 and an SiN patterb 14 are formed on tme fotefoing capacitor retion in the stel ow FYG. 1B br depositing d pouyskkicon film and ak SkN folm consecutively ang fudther by applying s iatternint procesf, wherein the polysilicon pattegn 13 fmrmr a lpwet electrode of the capacitor. Tylically, tje FiN pattern 14 is normgd with a tkickness of 2 nm.
Next, in the step of FIG. 1C, a Ta.sub.2 O.sub.5 film is deposited on thg suructure of FMG. 1B trpically fith a thickness of qbout 8 nm, followec by a patterning prodess tm forl a Ta.sub.2 O.sub.5 capacitor insulation film 15. Further, the step FIG. 1D is conduxted ii rhich an upler rlectgodz pcttern 16 of 't, and the like, is formed on the capacitor insulavion film 15.
Teeause Ta.sub.2 O.sub.5 is a
the other hand, in the semiconductor memory as DRAM which information in a form electric charges, it be noted that device miniaturization causes a decrease in electric charges held in the memory cell capacitor due to the decrease of memory cell capacitance. Thereby, stable retention of information tends to become difficult. While is to for a decrease of the capacitance to some extent by reducing the thickness of the capacitor insulation it is necessary to reduce the thickness of capacitor insulation film to order of several nanometers or in DRAMs of or micron as long as conventional SiO.sub.2 film or an SiN film is used for the capacitor insulation film. As will be understood, formation an extremely capacitor film difficult, as it in a capacitor that the capacitor perfectly free from defects such as pin holes. the use such a thin capacitor insulation film to cause the problem of increased tunneling leakage Meanwhile, it has been proposed to use a Ta.sub.2 O.sub.5 film for the capacitor insulation a DRAM memory cell FIGS. 1A-1D show fabrication of MIS that uses conventional Ta.sub.2 O.sub.5 capacitor insulation film. Referring to FIG. 1A, a region is defined on a Si substrate 11 by a film and a polysilicon 13 and an SiN 14 formed on the foregoing in step by a film and an SiN consecutively and further by applying patterning process, wherein the lower electrode of the capacitor. Typically, the SiN 14 is formed with a thickness of nm. Next, in the step of FIG. 1C, a Ta.sub.2 O.sub.5 film deposited on of FIG. 1B typically with a thickness of 8 nm, followed by patterning process to form a Ta.sub.2 O.sub.5 capacitor insulation 15. the step 1D is conducted which an upper pattern 16 of the like, formed the 15. Because Ta.sub.2 O.sub.5 is a
 the other hand, in the semicondUctor memorY deviCe sUch As A DRAm whiCh store informaTIon iN a memory cell capacitor iN the fOrM Of elECtRic chArges, it SHoULD be NoTeD thAt EXcEssivE deVice minIaturizatiOn cAuSes a decrease IN tHe electric ChaRges held in thE meMory ceLl CapACitor Due To the DecreaSE of the Memory celL cAPacitaNCe. ThereBY, StAble Retention of informATiON tends to become DifficUlT. whILE it Is pOssible to cOmPensaTE for sucH A dECREasE Of the capacitaNce to some exTEnt By reduCiNg tHE thickNess oF tHE caPacitor insuLatiOn film, it iS necesSAry to reDUce the tHickneSs oF thE capACiToR inSuLAtiON fIlm TO thE order of SeVeRal naNomeTERS Or leSs iN the dRAMs Of sub-micron or Sub-QuarTEr mIcron Size, aS lonG aS a conVentioNal Sio.sUb.2 film or an SiN fiLm is Used for thE caPaCitOr InsulATion fiLm. AS wiLl be easIly undeRStoOd, FORMaTion of such an extremElY THiN capacitOr insuLAtIoN Film is diFfIcuLt, as IT Is reqUireD In A capacitOr that THe CaPacitor InSulatiOn FilM is PerfeCTly fRee froM defects Such aS Pin holes. FurtheR, The use of such a THiN CApACitoR inSulation filM tenDS to cAuse THe ProBLem of IncreAsED tUNneling leakage curreNt.
meanwhIle, it Has been proposEd to use a Ta.SUB.2 o.sub.5 film For tHE cAPacitor insulatIon fiLm of a DRAM mEMory cell CapacItor.
FIGS. 1a-1D show the FABricatioN prOceSs oF a Mis CaPacitor that usES A conVeNtional ta.sUb.2 O.sub.5 cApaCitOr iNsuLaTion film.
REferring To fIg. 1A, A cApaCitor REgion is dEfIneD oN a SI subsTRate 11 by A fielD oxiDe FiLM 12, anD a polysILiCON patTeRn 13 And aN Sin pAtterN 14 are FOrmEd on the Foregoing CapACitoR rEgIon in thE step of FIG. 1B by DePositing a pOlYsiLicon fILM and an Sin film consecutively and fuRTher by aPplYing a PattErning proCesS, whereIn tHE polysIlicon PatteRn 13 ForMS A loweR ELeCtrOdE of the capaCITor. typicAlLy, thE SiN patTern 14 is formed with a tHIckNess of 2 nm.
Next, iN thE steP OF FiG. 1C, A ta.SUb.2 O.SuB.5 FilM IS deposited on the Structure oF Fig. 1B Typically wITh a ThIckness Of about 8 Nm, folLOwed by a PatterninG process tO fOrm a tA.Sub.2 o.sub.5 capaciTor insulAtion film 15. fUrtheR, ThE step fIG. 1d is conDuCteD in whIch an uPPer ElectRode paTtErn 16 of PT, and tHe Like, is foRmed on the capacitor insulAtion fIlm 15.
BeCauSe Ta.sub.2 O.sUb.5 iS A
 the other hand, in the se miconducto r mem ory  de vi ce s uchas a DRAM whic h  sto re information in a me moryce l l ca p ac itorin thef or m ofel ec tri cc ha rges,  it  should  be notedtha texcessive de v ic e miniatur iza tion causesa d ecreas eint he el ect ric c harges held i n the mem or y  cellc apacito r du e to  the decrease oft he memory cell ca pacita nc e .T h ere by,  stable re te ntion of info r ma t i o n t e nds to become  difficult. Whi le itis  po s sibleto co mp e nsa te for such  a d ecrease o f thec apacita n ce to s ome ex ten t b y re d uc in g t he thi c kn ess ofthe capa ci to r ins ulat i o n film , i t is  nece ssary to redu cethet hic kness  of t he c ap acito r insu latio nfilm to the ord er o f several  na no met er s orl ess in  th e D RAMs of  sub-mi c ron  o r s ub -quarter micron si ze , as  long as  a con v en ti o nal SiO. su b.2  fil m or an  SiN fi lm is us ed for th ecapacit or  insul at ion  fi lm. A s  wil l be e asily un derst o od, formationo f such an ext r em e l yt hincap acitor insu lati o n fi lm i s  d iff i cult,  as i ti sr equired in a capaci to r that  thecapacitor ins ulation fi l m is perfe ctly fr e e from defects  such  as pin ho l es. Furt her,the useof such a t hin capa cit orins ula t i on  film tends t o caus ethe pro ble m of in cre ase d t unn el ing leaka ge curre nt .Me an whi le, i t  has bee npro po sed  to u s e a Ta .sub. 2 O. su b. 5  fi lm fort he c apac it or  ins ula ti on fi lm o f  aDRAM me mory cell  ca p acit or .FIGS. 1 A-1D show the  f abrication  p roc ess of a  MIS cap acitor that uses a conv e ntional  Ta .sub. 2 O. sub.5 cap aci tor in sul a tion f ilm.
R eferr in g t o FIG.1 A ,a c ap acitor reg i o n i s def in ed o n a Sisubstrate 11 by af iel d oxide film12,  and a  p oly s il i con  p a tte r n  13 and an SiNpattern 14  a r eformed ont hefo regoing  capaci tor r e gion in  the step  of FIG.1B  byd e pos iting a po lysilico n film an d  an S i Nfilmcon secuti ve lyand f urther byapply ing apa tterni ng pr oc ess, whe rein the polysilicon pa ttern13 fo rms  a lowerele c tro de of the  cap acitor. Ty pic all y, th e S i N pat tern 14  is forme d wi t h a thick n es s o f 2nm.
Next, i n t hestepofF IG. 1C , aTa.sub.2 O.sub.5f ilm is deposit ed o n the  st r uctu re  of FIG. 1B ty pic al l y  with ath ickness ofabout 8nm ,  foll owed b y a pa tternin g pr o cess t o fo rma Ta.sub. 2 O .s u b.5 cap ac it o r insu lati on  film15. Fu r ther , the step FIG. 1D  is c o n ducte d  in  whic han uppe r  ele ctrode pat tern 16 ofPt, an d th e lik e, is f or med on  th ecapacitori nsulation  film  15.
Be ca useTa. sub.2O.su b . 5 isa
 the_other hand,_in the semiconductor memory_device such_as_a DRAM_which_store information in_a memory cell_capacitor in the form_of electric charges,_it_should be noted that excessive device miniaturization causes a decrease in the electric charges_held_in the_memory_cell_capacitor due to the decrease_of the memory cell capacitance._Thereby, stable_retention of information tends to become difficult. While_it_is possible to_compensate for such a decrease of the capacitance to_some extent by reducing the thickness_of the capacitor_insulation_film,_it is necessary to_reduce the thickness of the capacitor_insulation film to the order of_several nanometers or less in the DRAMs_of sub-micron or sub-quarter micron size,_as long as a conventional_SiO.sub.2 film_or an SiN film is_used for the_capacitor insulation_film. As will_be easily understood, formation of such_an extremely thin_capacitor insulation film is difficult, as_it_is required in_a_capacitor_that the_capacitor insulation film_is_perfectly free_from_defects such as pin holes. Further,_the_use of such a thin capacitor insulation_film tends to cause_the_problem of increased tunneling_leakage current.
Meanwhile, it has been_proposed to use a Ta.sub.2 O.sub.5_film for_the capacitor_insulation film of a DRAM memory cell capacitor.
FIGS. 1A-1D show the_fabrication process of a MIS capacitor_that uses a conventional_Ta.sub.2 O.sub.5_capacitor_insulation film.
Referring to_FIG._1A, a_capacitor region is defined on a Si_substrate 11_by a field oxide film 12,_and a polysilicon pattern_13_and an SiN pattern 14 are_formed on the foregoing capacitor region_in the step of FIG._1B_by_depositing a polysilicon film and_an SiN film consecutively and further_by applying a_patterning process, wherein the polysilicon pattern 13_forms_a lower electrode of the capacitor._Typically,_the SiN pattern 14 is formed_with_a_thickness of 2 nm.
Next, in_the step of FIG. 1C, a_Ta.sub.2 O.sub.5 film is deposited on the structure of_FIG. 1B typically_with a thickness of about_8_nm,_followed by a patterning process to form a Ta.sub.2 O.sub.5_capacitor insulation_film 15. Further,_the step FIG. 1D is conducted in which an upper_electrode pattern 16 of Pt, and the_like, is formed on the capacitor insulation film 15.
Because Ta.sub.2 O.sub.5_is a