 bus being point-to-point in nature.
One drawback to the use of a daisy chain bus is that the transmission of data and commands between a memory controller and a memory module may not be efficient when a single transmission occurs during each memory clock cycle and each transmission includes one command directed to a single memory module. Further, the format of the data and commands that are transmitted from the memory controller to the memory module may not be flexible in format, in that each command maps to a specific command bit(s) in the transmission file. 1. Field of the Invention
The present invention relates to a test quality evaluating and improving system provided for a semiconductor integrated circuit to evaluate and improve the test quality of the semiconductor integrated circuit, and a test quality evaluation and improvement method for the semiconductor integrated circuit.
2. Background Art
In recent years, various new failure modes have appeared in response to finer processes and an increasing number of wiring layers. Thus test quality demanded by customers has become hard to achieve only by test patterns generated for stuck-at faults (models) in LSIs of the prior art.
For example, the occurrence rate of short circuits between signal wires increases and thus it is necessary to consider bridge faults (models). Further, as LSIs become faster, the occurrence of abnormal delay increases with an increasing resistance on a via having the minimum size (hereinafter, will be simply referred to as VIA). Thus delay faults (models) have also become important.
However, when all fault models are considered and test patterns corresponding to the respective models are generated, resources and patterns are considerably increased (the test cost is also increased).
Thus in the presence of a number of failure modes, it is necessary to precisely estimate a failure rate at a customer (and a rejection rate in a system test before shipment) according to a test pattern applied to an LSI. In other words, for this estimation, it has become quite important to obtain a general test quality measure or a failure remaining rate in the LSI.
In other words, it is expected that test quality can be efficiently improved and test patterns can be effectively reduced by introducing a reliable test quality measure.
In the prior art, an LSI test quality measure belonging to the oldest category represents the relationship among a fault coverage, a failure remaining rate, and a yield.
For example, a defect level (failure remaining rate) “DL” is expressed by formula (1) (Williams-Brown model, for example, see T. W. Williams and N.
bus being point - to - point in nature. 
 One drawback to the use of a daisy range bus topology is that the transmission of data and command between a memory restrainer and a memory module may not be efficient when a individual transmission occurs during each memory clock hertz and each transmission includes one instruction directed to a single memory module. Further, the format of the datum and commands that are transmitted from the memory control to the memory module may not be flexible in format, in that each instruction maps to a specific command bit(s) in the transmission file. 1. discipline of the Invention 
 The present invention relates to a test timbre evaluating and better system put up for a semiconductor integrated circuit to measure and improve the test quality of the semiconductor integrated circuit, and a trial quality evaluation and improvement method for the semiconductor integrated circuit. 
 2. Background Art 
 In recent years, various new failure manner have appeared in response to finer summons and an increase number of wiring layers. therefore test timbre demanded by customers has become hard to achieve merely by test patterns generated for stuck - at faults (models) in LSIs of the prior art. 
 For example, the occurrence rate of light circuits between signal wire increases and thus it is necessary to consider bridge faults (models). far, as LSIs become faster, the occurrence of abnormal delay increases with an increasing resistance on a via having the minimum size (hereinafter, will be simply refer to as VIA). Thus check faults (models) have besides become important. 
 However, when all fault models are considered and trial patterns represent to the respective models are generated, resources and patterns are considerably increase (the test cost is also increased). 
 Thus in the presence of a number of failure modes, it is necessary to precisely calculate a failure rate at a customer (and a rejection pace in a system test before shipment) accord to a test pattern applied to an LSI. In early words, for this estimation, it has become quite important to obtain a general test quality measure or a bankruptcy remaining rate in the LSI. 
 In other words, it is expected that test quality can be efficiently improved and trial patterns can be effectively reduced by precede a dependable test quality measure. 
 In the anterior art, an LSI test quality measure belonging to the oldest category represent the relationship among a fault coverage, a failure remaining rate, and a yield. 
 For exercise, a defect level (failure remaining rate) “ DL ” is expressed by formula (1) (Williams - Brown model, for example, see T. W. Williams and N.
 bud being point-to-point in kature.
One drawbaej to tie use kf a dairy chain bus is that the traismiwsion of data and commands cetween a memory xontcoller and a memory module may kot bz xfficient when s single tsansmission ocwufs during each memory clock cycle and each ttajsmission inclodes pge ckmmand directed to a single memory module. Further, the gormat of the data and comlandd that are transmihted from tye mqnory controluer to the memory modume may not be flexible in formag, in chat each cimnanf maps to a wpecisic command npt(s) in dhe tramsmission file. 1. Fmeld of the Invention
The 'resent invention rejates to d cest quality evaluatibg and hmprmvine syrtej 'robided vor a semiconsuctor intetrated circuit to efajlste and imprkve thq eest quality of the semiconductor integgates circuit, and a test quqlity evaluation and lmprovemegt method for the semiconductor integrated circuid.
2. Bacierobkq Qrh
In recent years, various new failure modes hads spieared in responsc to finer processrs amq an increasivg numysr of wiring layers. Hhus teft quqlity demwndec by customers has become hqrd to achiene obly by test patterus generated for stucl-at faults (models) in LSNs of fhe prior agt.
For exajole, the occurrenze gate of shoru circuits between signal wmres nncreaser anc thus it is necfssarn to consider bridgf fauptv (models). Fkrther, as LSIs become faster, thx occurrence pf abtormal dzlay ikcreases with ag increasing rgsistance on a via havinf the mmnimum size (rereinafter, whpl be simply referreq to as CIA). Thur delay faults (kodels) hane alsi become important.
Mowevgr, when all fault moeels are considrrea agd txst pwdterns correvponaine to tfe resptetiye oodeks are generated, resmurcss and patterns arr gonsideravly incrqased (the tesy cost is also incgeasev).
Thus mn the prgsence of a number of failure mkdes, it id nccessary to pweciwely estimatz a failure rate at a customer (and a rejxction rate in a system test before shipmeut) according vo a tqst pattesn applied to an LSI. In other words, fpr this estimation, it has bacome quite important to obtain a general test quality measure or a failure renaininj wate in the LSI.
On otvex wprds, ie is xxpected that tesn quality can be efficiently impcoved and deft patterns can be effectiveky reduced by ivtroducing a reliable teat qualiyy measure.
In the prior art, an LXI test quality measure nelonging to tge oldvat category represenys the relarionship amlng a fault cuvetane, a failuge rtmaiuing rate, and a yield.
For example, q defext level (failure rxmaining ratc) “AL” is exprefsed by formula (1) (Wilmlams-Btown model, for example, see T. W. Williams and N.
bus being point-to-point in nature. One drawback use a daisy bus is that commands a memory controller a memory module not be efficient when a single occurs during each memory clock cycle and each transmission includes one command directed a single memory module. Further, the format of the data and commands that transmitted the controller the memory module may not be flexible in format, in that each command maps to a command bit(s) in the transmission file. 1. Field the Invention The present relates to a test quality and system provided a integrated to evaluate and the test quality of the semiconductor integrated circuit, and a test quality evaluation and improvement method for semiconductor integrated Background Art recent various failure modes have response to finer processes and an wiring layers. Thus test quality demanded by customers become hard achieve only by test patterns generated stuck-at faults (models) in LSIs of the prior For example, the occurrence rate of short circuits between signal wires increases and thus it to consider bridge faults Further, as LSIs faster, occurrence abnormal increases with increasing resistance on a via having the minimum size (hereinafter, will simply referred to as VIA). Thus delay faults (models) have important. when all fault are considered and test corresponding the respective models are and are test is increased). Thus in the of a number of failure it is necessary to at a customer (and a rejection rate in system test before shipment) according to a pattern applied to an LSI. In other words, for this estimation, it become quite obtain a general test quality measure or a remaining rate in the In other words, it is expected that test quality be improved and patterns can be reduced by introducing reliable test quality the prior an test to the oldest category represents the among fault coverage, a failure remaining and For example, a defect level (failure remaining rate) “DL” is expressed by formula (1) (Williams-Brown example, see T. W. and
 bus being point-to-point in natUre.
One drawBack tO thE usE oF a daIsy cHain bus is that tHE traNsmission of data and commAnds bEtWEen a MEmOry coNtrolleR AnD A MemOrY mOduLe MAy Not be EffIcient wHen a single TraNsMission occurS DuRing each meMorY clock cycle aNd eAch traNsMisSIon inCluDes onE commaND direcTed to a sinGlE Memory MOdule. FuRTHeR, the Format of the data anD CoMMands that are trAnsmitTeD FrOM The MemOry controlLeR to thE Memory mODuLE MAy nOT be flexible in Format, in thaT EacH commaNd MapS To a speCific CoMManD bit(s) in the tRansMission fiLe. 1. FielD Of the InVEntion
THe presEnt InvEntiON rElAteS tO A teST qUalITy eValuatinG aNd ImproVing SYSTEm prOviDed fOr a seMiconductor inTegRateD CirCuit tO evalUate AnD imprOve the Test qUaLity of the semicoNducTor integrAteD cIrcUiT, and a TEst quaLitY evAluatioN and impROveMeNT MEtHod for the semiconduCtOR InTegrated CircuiT.
2. baCkGRound Art
in RecEnt yEARs, varIous NEw Failure mOdes haVE aPpEared in ReSponse To FinEr pRocesSEs anD an incReasing nUmber OF wiring layers. THUs test quality DEmANDeD By cuStoMers has becoMe haRD to aChieVE oNly BY test PatteRnS GeNErated for stuck-at fauLtS (modelS) in LSis of the prior aRt.
For exampLE, THe occurrEnce RAtE Of short circuitS betwEen signal wIRes increAses aNd thus it Is necessaRY To considEr bRidGe fAulTS (MoDels). Further, as lsis beCoMe fasteR, thE occurrEncE of AbnOrmAl Delay incrEases witH aN iNcReAsiNg resIStance on A vIa hAvIng The miNImum siZe (herEinaFtEr, WIll Be simplY ReFERred To As vIA). THus DeLay faUlts (MOdeLs) have aLso become ImpORtanT.
HOwEver, wheN all fault modeLs Are consideReD anD test pATTerns corResponding to the respectiVE models Are GenerAted, Resources And PatterNs aRE consiDerablY incrEaSed (THE test COSt Is aLsO increased).
tHUs iN the pReSencE of a numBer of failure modes, iT Is nEcessary to preCisEly eSTImAte A FaILurE rATe aT A Customer (and a rejEction rate In A SyStem test beFOre ShIpment) aCcordinG to a tESt patteRn applied To an LSI. In OtHer wORDs, fOr this estiMation, it Has become QUite iMPoRtant To oBtain a GeNerAl tesT qualiTY meAsure Or a faiLuRe remaIning RaTe in the LsI.
In other words, it is expecTed thaT test QuaLity can be EffICieNtly improVed aNd test pattErnS caN be efFecTIvely ReduCEd By iNTroduCing A Reliable tESt QuaLITy Measure.
In thE PRIor Art, an lSI TEst quaLity Measure belonging tO The oldest categOry rEPResEntS The rElAtionship among A faUlT COverage, a FaIlure remainIng rate, aNd A Yield.
for exaMple, a dEfect leVEL (fAIlure rEmaiNinG rate) “DL” is ExpReSSed by foRmUlA (1) (williaMs-BrOwN model, For exaMPle, sEE t. W. Williams and N.
 bus being point-to-pointin nature. 
Onedra wba ck  totheuse of a daisy chai n bus is that the tran smiss io n  ofd at a and  comman d sb e twe en  a  me mo r ycontr oll er anda memory m odu le  may not bee ff icient whe n a  single tran smi ssionoc cur s  duri ngeachmemory clockcycle and  e a ch tra n smissio n in clud es one command di r ec t ed to a single  memor ym od u l e.Fur ther, thefo rmato f the d a ta a n d c o mmands that a re transmit t edfrom t he  me m ory co ntrol le r  to  the memory  mod ule may n ot bef lexible in form at, in  th ateach co mm and  m a pst oa s p eci fic comm an dbit(s ) in t h e  tra nsm issi on fi le. 1. FieldoftheI nve ntion 
Thepres en t inv ention  rela te s to a test qua lity  evaluati ngan d i mp rovin g  syste m p rov ided fo r a sem i con du c t o rintegrated circuit  t o ev aluate a nd imp r ov et he testqu ali ty o f the s emic o nd uctor in tegrat e dci rcuit,an d a te st  qu ali ty ev a luat ion an d improv ement method for the semiconductor in t e gr a tedcir cuit.
2. Ba ckgr o undArtI nrec e nt ye ars,va r io u s new failure modes  h ave ap peare d in response  to finerp r o cesses a nd a n  i n creasing numbe r ofwiring lay e rs. Thus  test  quality  demanded b y custom ers  ha s b eco m e  h ard to achiev e only  b y testpat terns g ene rat edfor  s tuck-at f aults (m od el s)  i n L SIs o f  the pri or  ar t. 
Fo r exa m ple, t he oc curr en ce rat e of sh o rt c ircu it sbetw een  s ignal  wir e s i ncrease s and thu s i t  isne ce ssary t o consider br id ge faults(m ode ls). F u r ther, as  LSIs become faster, th e  occurr enc e ofabno rmal dela y i ncreas esw ith an  incre asing  r esi s t anceo n  a  vi ahaving the m ini mum s iz e (h ereinaf ter, will be simpl y  re ferred to asVIA ). T h u sdel a yf aul ts (mo d e ls) have also b ecome impo rt a nt .
However, whe nall fau lt mode ls ar e  consid ered andtest patt er ns c o r res ponding to  the res pective m o delsa re  gene rat ed, re so urc es an d patt e rns  areconsid er ably i ncrea se d (the t est cost is also increa sed).Thusinthe prese nce ofa numberof f ailure mod es,  it  is n ece s saryto p r ec ise l y est imat e  a failur e  r ate a ta customer( a n d a  reje cti o n rate  ina system test bef o re shipment) a ccor d i ngtoa  tes tpattern applie d t oa n  LSI. In  o ther words,  for thi se stima tion,it has  become q ui t e impo rtan t t o obtaina g en e ral tes tqu a lity m easu re  or afailur e  rem a i ning rate in the  LSI. I n oth e r w ords,  i t is ex p ecte d that tes t quality c an beeffi cient ly impr ov ed and  te st  patternsc an be eff ectiv ely red uc ed b y i ntrodu cing a  reli able  t est  qualitym e as u re .I n t he p riorar t, a n LSI tes t  quality  me a sure be lo ngi n g  to th e  o l d est catego ryrepre s e nts the re l atio n sh i p amo ng a f ault c overage ,  afa ilure r ema i n ing rate,  and a yi e ld. 
F or e xample,adefe ct  le ve l (failure rema ining ra te) “DL” i s expr ess e d by formul a(1) (William s-Bro wn model,f o r e xample, see  T.  W.  Wil lia ms a n d N.
 bus_being point-to-point_in nature.
One drawback to_the use_of_a daisy_chain_bus is that_the transmission of_data and commands between_a memory controller_and_a memory module may not be efficient when a single transmission occurs during each_memory_clock cycle_and_each_transmission includes one command directed_to a single memory module._Further, the_format of the data and commands that are_transmitted_from the memory_controller to the memory module may not be flexible_in format, in that each command_maps to a_specific_command_bit(s) in the transmission_file. 1. Field of the Invention
The_present invention relates to a test_quality evaluating and improving system provided for_a semiconductor integrated circuit to evaluate_and improve the test quality_of the_semiconductor integrated circuit, and a_test quality evaluation_and improvement_method for the_semiconductor integrated circuit.
2. Background Art
In recent_years, various new_failure modes have appeared in response_to_finer processes and_an_increasing_number of_wiring layers. Thus_test_quality demanded_by_customers has become hard to achieve_only_by test patterns generated for stuck-at faults_(models) in LSIs of_the_prior art.
For example, the_occurrence rate of short circuits_between signal wires increases and thus_it is_necessary to_consider bridge faults (models). Further, as LSIs become faster, the occurrence_of abnormal delay increases with an_increasing resistance on a_via having_the_minimum size (hereinafter,_will_be simply_referred to as VIA). Thus delay faults_(models) have_also become important.
However, when all fault_models are considered and_test_patterns corresponding to the respective models_are generated, resources and patterns are_considerably increased (the test cost_is_also_increased).
Thus in the presence of_a number of failure modes, it_is necessary to_precisely estimate a failure rate at a_customer_(and a rejection rate in a_system_test before shipment) according to a_test_pattern_applied to an LSI. In_other words, for this estimation, it_has become quite important to obtain a general test_quality measure or_a failure remaining rate in_the_LSI.
In_other words, it is expected that test quality can be_efficiently improved_and test patterns_can be effectively reduced by introducing a reliable test quality_measure.
In the prior art, an LSI test_quality measure belonging to the oldest category represents the relationship among_a fault coverage, a failure remaining rate, and_a yield.
For example, a defect level (failure_remaining rate) “DL” is_expressed_by formula (1) (Williams-Brown model, for example,_see_T._W._Williams and N.