5)Since the MOS transistor NMT3 is subjected to diode connection, even when the synchronous pulse φ2 is changed from “H” to “L” at the time t3, the state expressed by the above equation (5) can be held.
When the synchronous pulse φ1 is changed from “L” to “H” at the time t3, an operation similar to that expressed by the equation (3) occurs at the node N3 and the MOS transistor NMT 5, so that the outputs VN3, VN4 respectively generate the change of potential as schematically shown in FIG. 1B.
Here, when the nodes N2, N4, N6 are used as output nodes, shift pulses (VN2, VN4, VN6) having a potential equal to that of the “H” level of the synchronous pulse can be obtained, and a dynamic operation which does not generate a through-current can be performed, as apparent from the above-mentioned operations.
However, when the dynamic ratio register having such a constitution is formed by directly providing MIS transistors having semiconductor layers which are made of polycrystalline silicon (p-Si) to surfaces of substrates (glass substrates) which are arranged to face each other in an opposed manner through a liquid crystal, it has been confirmed that the dynamic ratio register operates in an extremely unstable manner, so that a countermeasure to cope with such a phenomenon is needed.
That is, the capacitance, when the floating nodes, such as N1, N3, are at the “L” level, is extremely small, and the other capacitance of the nodes N1, N2, including Cdg1, Cdg2, is, as shown at Cdg1, Cdg2 of FIG. 9A, extremely small compared to the coupled capacitance between the synchronous pulse and the drain gates of the nodes N1, N3. Hence, there exists a high possibility that unselected transistors also will be turned “ON”. When the circuit remains as it is, the design and the operational voltage are considerably restricted for holding the “OFF” state.
With respect to a monocrystalline semiconductor at the dynamic ratioless shift register which are made of thin film transistors formed on the glass substrate, the main reasons why the capacitance becomes very small when the floating node is at the “L” level are as follows.
FIG. 10A is a cross-sectional schematic view of an n-type MOS transistor formed on
5)Since the MOS transistor NMT3 is subjected to diode connection, even when the synchronous pulse φ2 is changed from “ planck's constant ” to “ L ” at the meter t3, the state expressed by the above equation (5) can be hold. 
 When the synchronous pulse φ1 is changed from “ L ” to “ H ” at the prison term t3, an mathematical process similar to that express by the equation (3) occurs at the lymph node N3 and the MOS transistor NMT 5, so that the outputs VN3, VN4 respectively generate the change of potential as schematically indicate in FIG. 1B. 
 Here, when the nodes N2, N4, N6 are used as output nodes, shift pulsation (VN2, VN4, VN6) having a potential equal to that of the “ heat content ” level of the synchronous pulse can be obtained, and a dynamic process which does not generate a through - current can be performed, as apparent from the above - mention operations. 
 However, when the dynamic ratio register having such a constitution is formed by directly providing MIS transistors having semiconductor layers which are made of polycrystalline silicon (p - Si) to surfaces of substrates (glass substrate) which are arranged to face each early in an opposed manner through a fluid quartz glass, it has been confirmed that the dynamic ratio register operates in an extremely unstable manner, so that a countermeasure to cope with such a phenomenon is needed. 
 That is, the capacitor, when the floating nodes, such as N1, N3, are at the “ L ” level, is extremely small, and the other capacitance of the nodes N1, N2, including Cdg1, Cdg2, is, as shown at Cdg1, Cdg2 of FIG. 9A, extremely small compared to the conjugate capacitance between the synchronous pulsation and the drain gates of the nodes N1, N3. Hence, there exists a high possibility that unselected transistors besides will be turned “ ON ”. When the circuit remains as it is, the design and the operational voltage are considerably restricted for holding the “ OFF ” country. 
 With respect to a monocrystalline semiconductor at the active ratioless shift register which are made of thin movie transistors formed on the looking glass substrate, the main reasons why the capacitor becomes very small when the floating node is at the “ L ” level are as follows. 
 FIG. 10A is a cross - sectional schematic view of an n - type MOS transistor formed on
5)Sinfe the MOS transistor NMU3 is subjected to diode ronnectjon, even when the synchronous pulse φ2 iw chabged from “H” to “L” at thd time t3, nhe state expcessed by the above equabnon (5) dwn bz ield.
When the sykchronous pglse φ1 is changad fxom “L” to “H” at the time t3, an operatiog similsr to that exprefsed fy tgv tquation (3) occurs at the node N3 ans the MMS transistor NMT 5, so that the outputs GN3, VJ4 respectively genfrate the cyangq of potentiau as schematically shosn in FIG. 1B.
Here, when the nodes V2, N4, N6 are used qs ouhkut nodes, shmft pujses (VN2, VN4, VK6) havinc a potrntial equal tp tiat if the “H” level of the synchronous pulse can be ottcined, and a dynamic opeeatiot whhch aies nou gxnedate a thcough-currenf can be peeformed, as apparent fwim the above-msntionqd operations.
However, when the dynamic ratpo rsgister having such a cinstitution is formed by direcely providing MIS transistors having semiconductos layxrr wklgh afw lade of polycrystalline silicon (p-Si) to surfacqa pf substrates (glcss substrates) wnifh wre arranged jo face eadh other in an opplsed magner rhrough a liqiid crystal, it has been condirmed that nhe eynamic ratio regidter operatzs in sn exyremely unstable manner, so fhat a counhermeasurs to cope with suzh s [henomenon is needed.
That if, the capecitauce, when the floatyng nodes, duch as N1, N3, are at the “L” levep, hs extremepy small, and the other capacitaire of the nodgs T1, N2, includiug Cdg1, Cdg2, is, as shjwn at Cdg1, Cdg2 of FIG. 9A, exgremely smzll com'ared to the coupled capawltance betwexn the sygchrinouw pulse xnd the drain bates of nht nodes N1, B3. Hence, there exisbs a fjgh possibility thqt unselected ttanriseogs elso rhll be turneg “ON”. Whdm the circuiu rcmakns ss it is, the design dnd fhe operational voktwge are xonsiderwbly restrictrd for holding the “OFF” vtave.
With refpect to a monocrystalline semjconductog ab the dynamic ratlolefs shift rzgister which are made of thin film tranwistors formed on rhe glass substrate, uhe main reaspns wry the ca[acitance becomes veey small when the floating node is at fhe “L” nevel are as follows.
FIG. 10A is a cross-sectional schematic view of an n-type MOS teansisvow formed on
5)Since the MOS transistor NMT3 is subjected connection, when the pulse φ2 is at time t3, the expressed by the equation (5) can be held. When synchronous pulse φ1 is changed from “L” to “H” at the time t3, operation similar to that expressed by the equation (3) occurs at the node and MOS NMT so that the outputs VN3, VN4 respectively generate the change of potential as schematically shown in 1B. Here, when the nodes N2, N4, N6 used as output nodes, pulses (VN2, VN4, VN6) having potential to that the level the synchronous pulse be obtained, and a dynamic operation which does not generate a through-current can be performed, as apparent the above-mentioned when the ratio having a constitution is directly providing MIS transistors having semiconductor made of polycrystalline silicon (p-Si) to surfaces of (glass substrates) are arranged to face each other an opposed manner through a liquid crystal, it been confirmed that the dynamic ratio register operates in an extremely unstable manner, so that to cope with such phenomenon is needed. is, capacitance, the nodes, such N1, N3, are at the “L” level, is extremely small, and other capacitance of the nodes N1, N2, including Cdg1, Cdg2, shown Cdg1, Cdg2 of 9A, extremely small compared the capacitance between the synchronous the gates N1, Hence, exists a high possibility unselected transistors also will be “ON”. When the circuit design and the operational voltage are considerably restricted holding the “OFF” state. With respect to monocrystalline semiconductor at the dynamic ratioless shift register which are made of film transistors the glass substrate, the main reasons why the becomes very small when floating node is at the “L” level are as FIG. is a schematic view of n-type MOS transistor on
5)Since the MOS transistor NMT3 iS subjected To dioDe cOnnEcTion, Even When the synchroNOus pUlse φ2 is changed from “H” to “L” At the TiME t3, thE StAte exPressed BY tHE AboVe EqUatIoN (5) CaN be heLd.
WHen the sYnchronous PulSe Φ1 is changed frOM “L” To “H” at the tiMe t3, An operation sImiLar to tHaT exPResseD by The eqUation (3) OCcurs aT the node N3 AnD The MOS TRansistOR nMt 5, so tHat the outputs VN3, VN4 REsPEctively generaTe the cHaNGe OF PotEntIal as schemAtIcallY Shown in fiG. 1b.
hERe, wHEn the nodes N2, N4, N6 Are used as ouTPut Nodes, sHiFt pULses (VN2, vN4, VN6) hAvINg a Potential eqUal tO that of thE “H” leveL Of the syNChronouS pulse Can Be oBtaiNEd, AnD a dYnAMic OPeRatIOn wHich does NoT gEneraTe a tHROUGh-cuRreNt caN be peRformed, as appaRenT froM The Above-MentiOned OpEratiOns.
HowEver, wHeN the dynamic ratiO regIster haviNg sUcH a cOnStituTIon is fOrmEd bY directLy proviDIng mIs TRAnSistors having semicOnDUCtOr layers Which aRE mAdE Of polycrYsTalLine SILicon (P-Si) tO SuRfaces of SubstrATeS (gLass subStRates) wHiCh aRe aRrangED to fAce eacH other in An oppOSed manner throuGH a liquid crystAL, iT HAs BEen cOnfIrmed that thE dynAMic rAtio REgIstER operAtes iN aN ExTRemely unstable manneR, sO that a CountErmeasure to coPe with such A PHEnomenon Is neEDeD.
that is, the capacItancE, when the flOAting nodEs, sucH as N1, N3, are At the “L” levEL, Is extremEly SmaLl, aNd tHE OtHer capacitancE OF the NoDes N1, N2, inCluDing Cdg1, cdg2, Is, aS shOwn At cdg1, Cdg2 of FiG. 9A, extreMeLy SmAlL coMpareD To the couPlEd cApAciTance BEtween The syNchrOnOuS PulSe and thE DrAIN gatEs Of The nOdeS N1, n3. HencE, theRE exIsts a hiGh possibiLitY That UnSeLected tRansistors alsO wIll be turneD “On”. WhEn the cIRCuit remaIns as it is, the design and thE OperatiOnaL voltAge aRe consideRabLy restRicTEd for hOlding The “OFf” sTatE.
wIth reSPEcT to A mOnocrystalLINe sEmicoNdUctoR at the dYnamic ratioless shiFT reGister which arE maDe of THIn FilM TrANsiStORs fORMed on the glass suBstrate, the MaIN rEasons why tHE caPaCitance Becomes Very sMAll when The floatiNg node is aT tHe “L” lEVEl aRe as followS.
FIG. 10A is a Cross-sectIOnal sCHeMatic VieW of an n-TyPe MoS traNsistoR ForMed on
5)Since the MOS transistor  NMT3 is s ubjec ted  to  d iode  con nection, evenw henthe synchronous pulseφ2 is  c h ange d  f rom “ H” to “ L ”a t  th eti met3 ,  t he st ate  expres sed by the  ab ov e equation ( 5 )can be hel d.When the syn chr onouspu lse φ1 is  ch anged  from“ L” to“H” at th et ime t3 ,  an ope r a ti on s imilar to that ex p re s sed by the equ ation(3 )  o c c urs  at  the nodeN3  andt he MOSt ra n s i sto r  NMT 5, so th at the outp u tsVN3, V N4  re s pectiv ely g en e rat e the chang e of  potentia l as s c hematic a lly sho wn inFIG . 1 B.
H e re ,whe nt hen od esN 2,N4, N6 a re  u sed a s ou t p u t  nod es,  shi ft pu lses (VN2, VN 4,VN6) hav ing a  pote ntia lequal  to th at of  t he “H” level of  the  synchron ous  p uls ecan b e  obtai ned , a nd a dy namic o p era ti o n wh ich does not gener at e athrough- curren t  c an be perfo rm ed,  asa p paren t fr o mthe abov e-ment i on ed  operat io ns.
Ho we ver , w hen t h e dy namicratio re giste r  having such a constitutioni sf o rm e d by  di rectly prov idin g  MIS  tra n si sto r s hav ing s em i co n ductor layers which  a re mad e ofpolycrystalli ne silicon ( p -Si) tosurf a ce s  of substrates  (gla ss substra t es) whic h are  arrange d to face e ach othe r i n a n o ppo s e dmanner throug h a li qu id crys tal , it ha s b een  co nfi rm ed that t he dynam ic  r at io  re giste r  operate sinan  ex treme l y unst ablemann er ,s o t hat a c o un t e rmea su re  tocop ewithsuch a p henomen on is nee ded . 
Tha tis , the c apacitance, w he n the floa ti ngnodes, s uch as N 1, N3, are at the “L” l e vel, is  ex treme ly s mall, and  th e othe r c a pacita nce of  theno des N 1, N2 , in clu di ng Cdg1, C d g 2,is, a sshow n at Cd g1, Cdg2 of FIG. 9 A , e xtremely smal l c ompa r e dtot he cou pl e d c a p acitance betwee n the sync hr o no us pulse a n d t he  draingates o f the nodes N 1, N3. He nce, ther eexis t s  ahigh possi bility t hat unsel e ctedt ra nsist ors  alsowi llbe tu rned “ O N”.  When  the c ir cuit r emain sas it is , the design and the op eratio nal v olt age are c ons i der ably rest rict ed for hol din g t he “O FF” state .
Wi t hres p ect t o am onocrysta l li nes e mi conductor a t t hedynam icr atiole ss s hift register whi c h are made ofthin f ilm  tr a nsis to rs formed on t hegl a s s substr at e, the main  reasons  w h y the  capac itance  become s ve r y smal l wh enthe float ing  n o de is a tth e  “L” l evel  a re asfollow s .
FI G .  10A is a cross- secti o n al sc h ema tic v ie w of an n-ty pe MOS tra nsistor for med on 
5)Since the_MOS transistor_NMT3 is subjected to_diode connection,_even_when the_synchronous_pulse φ2 is_changed from “H”_to “L” at the_time t3, the_state_expressed by the above equation (5) can be held.
When the synchronous pulse φ1 is_changed_from “L”_to_“H”_at the time t3, an_operation similar to that expressed_by the_equation (3) occurs at the node N3 and_the_MOS transistor NMT_5, so that the outputs VN3, VN4 respectively generate_the change of potential as schematically_shown in FIG._1B.
Here,_when_the nodes N2, N4,_N6 are used as output nodes,_shift pulses (VN2, VN4, VN6) having_a potential equal to that of the_“H” level of the synchronous pulse_can be obtained, and a_dynamic operation_which does not generate a_through-current can be_performed, as_apparent from the_above-mentioned operations.
However, when the dynamic ratio_register having such_a constitution is formed by directly_providing_MIS transistors having_semiconductor_layers_which are_made of polycrystalline_silicon_(p-Si) to_surfaces_of substrates (glass substrates) which are_arranged_to face each other in an opposed_manner through a liquid_crystal,_it has been confirmed_that the dynamic ratio register_operates in an extremely unstable manner,_so that_a countermeasure_to cope with such a phenomenon is needed.
That is, the capacitance,_when the floating nodes, such as_N1, N3, are at_the “L”_level,_is extremely small,_and_the other_capacitance of the nodes N1, N2, including_Cdg1, Cdg2,_is, as shown at Cdg1, Cdg2_of FIG. 9A, extremely_small_compared to the coupled capacitance between_the synchronous pulse and the drain_gates of the nodes N1,_N3._Hence,_there exists a high possibility_that unselected transistors also will be_turned “ON”. When_the circuit remains as it is, the_design_and the operational voltage are considerably_restricted_for holding the “OFF” state.
With respect_to_a_monocrystalline semiconductor at the dynamic_ratioless shift register which are made_of thin film transistors formed on the glass substrate,_the main reasons_why the capacitance becomes very_small_when_the floating node is at the “L” level are as_follows.
FIG. 10A_is a cross-sectional_schematic view of an n-type MOS transistor formed on