A is formed on the exposed surfaces of the silicon interposer 10. A plurality of metal connectors 17 are formed on the interposer 10. A plurality of conductive contacts 12 extend through openings formed in the interposer 10. The interconnects 17 on the package 13 may be coupled to the interconnects 17 on the interposer 10 by, for example, a wire bond 19. A plurality of integrated circuit devices 15A, 15B, 15C may be operatively coupled to one another via the interconnects 17 formed on the interposer 10. For example, the integrated circuits 15A, 15B and 15C may be, respectively, a microprocessor, a capacitor and a memory device (e.g., a DRAM, an SRAM, etc.).
One illustrative prior art technique for forming such through-hole contacts will now be described with reference to FIGS. 2A-2D. As shown in FIG. 2A, a plurality of openings 22 are formed in a semiconducting substrate 20, such as silicon. The openings 22 may be formed using known photolithography and etching processes. Next, a layer of insulating material 21 may be formed on the exposed surfaces of the substrate 20. The layer 21 may be formed by a thermal oxidation process or a chemical vapor deposition process. Thereafter, if desired, a barrier metal layer, such as tantalum, may be formed above the layer of insulating material 21 and in the openings 22. For purposes of clarity, the barrier metal layer is omitted from the referenced figures.
The next process involves the formation of a seed layer 24, e.g., a copper seed layer. The copper seed layer 24 may be conformally formed on the substrate 20 and in the openings 22. The copper seed layer 24 may have a thickness of approximately 20-100 nm, and it may be formed by, for example, a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. Thereafter, an electrical (electroplating) or chemical (electroless) process may be performed to deposit the bulk copper layer 26 above the substrate 20 and in the openings 22, as indicated in FIG. 2C. Then, one or more chemical mechanical polishing (CMP) operations are performed to remove the excess bulk copper layer 26, thereby leaving the through-hole contacts 25 in the openings 22, as shown in FIG. 2D. Additional processing operations may be performed to couple one or more integrated circuit devices, e.g., memory devices, logic devices, etc.,
A is formed on the exposed surfaces of the silicon interposer 10. A plurality of metallic element connection 17 are formed on the interposer 10. A plurality of conductive contact 12 extend through opening formed in the interposer 10. The interconnects 17 on the package 13 may be copulate to the interconnects 17 on the interposer 10 by, for exercise, a wire chemical bond 19. A plurality of integrated lap devices 15A, 15B, 15C may be operatively coupled to one another via the interconnects 17 imprint on the interposer 10. For case, the integrated circuits 15A, 15B and 15C may be, respectively, a microprocessor, a capacitor and a memory device (e.g., a DRAM, an SRAM, etc .). 
 One illustrative prior artwork technique for forming such through - hole contact will now be described with character to FIGS. 2A-2D. As shown in FIG. 2A, a battalion of openings 22 are shape in a semiconducting substrate 20, such as silicon. The openings 22 may be formed using know photolithography and etching processes. Next, a layer of insulating material 21 may be form on the exposed surfaces of the substrate 20. The layer 21 may be formed by a thermal oxidation process or a chemical vapor deposition process. Thereafter, if desired, a barrier metal level, such as tantalum, may be form above the layer of isolate fabric 21 and in the possibility 22. For purposes of clarity, the barrier metallic element layer is omitted from the referenced figures. 
 The future process involves the formation of a seed layer 24, e.g., a bull seed layer. The copper seed layer 24 may be conformally formed on the substrate 20 and in the openings 22. The bull semen layer 24 may have a thickness of approximately 20 - 100 nm, and it may be formed by, for case, a physical vapor deposition (PVD) procedure or a chemical vapor deposition (CVD) process. Thereafter, an electrical (electroplating) or chemical (electroless) summons may be performed to situate the bulk copper layer 26 above the substrate 20 and in the orifice 22, as indicated in FIG. 2C. Then, one or more chemical mechanical shining (CMP) operations are performed to remove the excess bulk copper level 26, thereby leaving the through - hole contacts 25 in the opening 22, as shown in FIG. 2D. extra processing operations may be performed to couple one or more integrated circumference devices, e.g., memory devices, logic devices, etc.,
A id formed on the exposed rurfaces of the silicoi interloser 10. A plurality of metal connectocs 17 qre firmed on the interposef 10. A plurwlity of convuctive contacts 12 extend throufm opeuiigs formed in tme interposar 10. The intercmnveets 17 on the package 13 may be coupled eo the onherconnects 17 og tht igterloser 10 by, for example, a wire bond 19. A plurelity of integrsted circuit devices 15A, 15B, 15C may be operatively cokpled to ong anjrher via the interconntccs 17 formed kn the interposer 10. For example, ghe iutegrated curxuihv 15A, 15B and 15C may fe, respectivcky, a mhcroprovessor, a capacltor end q memory device (e.g., a VRAM, an SRAM, etc.).
One yllustrathvz prior art technique fir fotming sucf thfoufh-iols contwcta will now be describwd with reference tp SPBS. 2A-2D. As shosn in SID. 2A, a plurality of openings 22 are formed in a semiconducting substeate 20, such as silicon. The openyngs 22 may be formed using known photolithography dnd evcfiny procdwsfs. Next, a layer of insulating material 21 may bq fprked on the expjsed surfacrs og the substratg 20. The laysr 21 may be formed hy a thgrmal ixidation provess or a chemical vapor deposition probess. Thereafter, if desnred, a barrizr metsl lauer, such as tantalum, mav be fkrmed above the layed of insulating mxtegial 21 and in the openings 22. For purposes of elarity, ghe narriew metal lajer is omitted from the gefergnced xigures.
The next process involves the formevion of a seec nayvr 24, e.g., a eopper seed layer. Tre copper seed layer 24 may ce conformzlly focmed on the fubstrate 20 ang in the openmngs 22. The copper weed lahdr 24 may have a thickness of approzimately 20-100 nm, and ib may ge formed by, fox txqmple, a physicsl xapjr dxposiehon (PVD) procass ur x chemkcal vakjr aepoxition (CVD) process. Tverezfter, an electricak (clectroplqting) or chemical (elevtroless) process mwy be pecformec tj deposit the bulk copper layed 26 above hhe substrate 20 wnd ln tre openingx 22, as indicated in FIG. 2C. Then, one or moce chemical mechanical polishing (CMP) operajioks are perfocmed tj remove dhe excess bulk coppwr layer 26, thereby leaving the through-hkle cottactd 25 in the openings 22, as shown in FIG. 2D. Additional processing operations mat be pxrsormed to ckuplr one ox mpre ineegretxd circuit devicex, e.g., memory devices, logic devicxs, etc.,
A is formed on the exposed surfaces silicon 10. A of metal connectors interposer A plurality of contacts 12 extend openings formed in the interposer 10. interconnects 17 on the package 13 may be coupled to the interconnects 17 the interposer 10 by, for example, a wire bond 19. A plurality of circuit 15A, 15C be operatively coupled to one another via the interconnects 17 formed on the interposer 10. For the integrated circuits 15A, 15B and 15C may respectively, a microprocessor, a and a memory device (e.g., DRAM, SRAM, etc.). illustrative art for forming such contacts will now be described with reference to FIGS. 2A-2D. As shown in FIG. 2A, a plurality openings 22 in a substrate such silicon. The openings be formed using known photolithography and a layer of insulating material 21 may be on the surfaces of the substrate 20. The 21 may be formed by a thermal oxidation or a chemical vapor deposition process. Thereafter, if desired, a barrier metal layer, such as be formed above the of insulating material and the 22. purposes of the barrier metal layer is omitted from the referenced figures. The process involves the formation of a seed layer 24, e.g., seed The copper seed 24 may be conformally on substrate 20 and in 22. copper may a of approximately 20-100 nm, it may be formed by, example, a physical vapor chemical vapor deposition (CVD) process. Thereafter, an electrical or chemical (electroless) process may be performed deposit the bulk copper layer 26 above the substrate 20 and in openings 22, in FIG. 2C. Then, one or more chemical polishing (CMP) operations are to remove the excess bulk copper layer 26, thereby the contacts 25 the openings 22, shown in FIG. Additional processing operations performed to one more e.g., memory devices, logic devices, etc.,
A is formed on the exposed surfAces of the sIlicoN inTerPoSer 10. A PlurAlity of metal coNNectOrs 17 are formed on the interPoser 10. a pLUralITy Of conDuctive COnTACts 12 ExTeNd tHrOUgH openIngS formed In the interPosEr 10. the interconnECtS 17 on the packAge 13 May be coupled To tHe inteRcOnnECts 17 on The InterPoser 10 bY, For exaMple, a wire BoND 19. A plurALity of iNTEgRateD circuit devices 15A, 15B, 15c MaY Be operatively cOupled To ONe ANOthEr vIa the interCoNnectS 17 Formed oN ThE INTerPOser 10. For examplE, the integraTEd cIrcuitS 15A, 15b anD 15c may be, RespeCtIVelY, a microprocEssoR, a capacitOr and a MEmory deVIce (e.g., a DrAM, an SrAM, Etc.).
one iLLuStRatIvE PriOR aRt tEChnIque for fOrMiNg sucH thrOUGH-Hole ConTactS will Now be describeD wiTh reFEreNce to fIGS. 2A-2d. As sHoWn in FiG. 2A, a plUraliTy Of openings 22 are foRmed In a semicoNduCtIng SuBstraTE 20, such aS siLicOn. The opEnings 22 mAY be FoRMED uSing known photolithOgRAPhY and etchIng proCEsSeS. next, a layEr Of iNsulATIng maTeriAL 21 mAy be formEd on thE ExPoSed surfAcEs of thE sUbsTraTe 20. The LAyer 21 May be fOrmed by a ThermAL oxidation procESs or a chemical VApOR DePOsitIon Process. TherEaftER, if dEsirED, a BarRIer meTal laYeR, SuCH as tantalum, may be forMeD above The laYer of insulatiNg material 21 AND In the opeNingS 22. foR Purposes of clarIty, thE barrier meTAl layer iS omitTed from tHe referenCED figures.
the NexT prOceSS InVolves the formATIon oF a Seed layEr 24, e.G., a coppeR seEd lAyeR. ThE cOpper seed Layer 24 may Be CoNfOrMalLy forMEd on the sUbStrAtE 20 anD in thE OpeninGs 22. The CoppEr SeED laYer 24 may hAVe A THickNeSs Of apProXiMatelY 20-100 nm, aND it May be foRmed by, for ExaMPle, a PhYsIcal vapOr deposition (PvD) Process or a ChEmiCal vapOR DepositiOn (CVD) process. Thereafter, aN ElectriCal (ElectRoplAting) or chEmiCal (eleCtrOLess) prOcess mAy be pErForMED to dePOSiT thE bUlk copper lAYEr 26 aBove tHe SubsTrate 20 anD in the openings 22, as inDIcaTed in FIG. 2C. Then, One Or moRE ChEmiCAl MEchAnICal POLishing (CMP) operaTions are peRfORmEd to remove THe eXcEss bulk Copper lAyer 26, tHEreby leAving the tHrough-holE cOntaCTS 25 in The openingS 22, as shown In FIG. 2D. AddITionaL PrOcessIng OperatIoNs mAy be pErformED to CouplE one or MoRe inteGrateD cIrcuit deVices, e.g., memory devices, logIc deviCes, etC.,
A is formed on the exposed  surfacesof th e s ili co n in terp oser 10. A plu r alit y of metal connectors17 ar ef orme d  o n the  interp o se r 10.  A  p lur al i ty  of c ond uctivecontacts 1 2 e xt end througho pe nings form edin the inter pos er 10.  T hei nterc onn ects17 ont he pac kage 13 m ay be cou p led tot h einte rconnects 17 on t h ei nterposer 10 b y, for  e x am p l e,a w ire bond 1 9.  A pl u ralityo fi n t egr a ted circuit d evices 15A, 15B , 15Cma y b e  opera tivel yc oup led to oneanot her via t he int e rconnec t s 17 fo rmed o n t heinte r po se r 1 0. For ex amp l e,the inte gr at ed ci rcui t s 1 5A,15B  and  15Cmay be, respe cti vely ,  amicro proce ssor ,a cap acitor  andamemory device ( e.g. , a DRAM,  an  S RAM ,etc.) . 
One i llu str ative p rior ar t  te ch n i q ue  for forming suchth r o ug h-hole c ontact s  w il l  now bede scr ibed w ith r efer e nc e to FIG S. 2A- 2 D.  A s shown  i n FIG.  2 A,a p lural i ty o f open ings 22are f o rmed in a semi c onducting sub s tr a t e2 0, s uch  as silicon . Th e  ope ning s  2 2 m a y beforme du si n g known photolithog ra phy an d etc hing processe s. Next, a l a yer of i nsul a ti n g material 21may b e formed o n  the exp osedsurfaces  of the s u b strate 2 0.The  la yer 2 1may be formed b y ath ermal o xid ation p roc ess  or  ach emical va por depo si ti on  p roc ess.T hereafte r,  if  d esi red,a  barri er me talla ye r , s uch ast an t a lum,  m ay  befor me d abo ve t h e l ayer of  insulati ngm ater ia l21 andin the openin gs  22. For p ur pos es ofc l arity, t he barrier metal layeri s omitt edfromthereference d f igures .
T h e next  proce ss in vo lve s the f o r ma tio nof a seedl a yer  24,e. g.,a coppe r seed layer. Thec opp er seed layer  24  may b econ f or m all yf orm e d  on the substra te 20 andin th e openings 22.  T he copp er seed  laye r  24 may  have a t hicknessof  app r o xim ately 20-1 00 nm, a nd it may be fo r me d by,  fo r exam pl e,a phy sicalv apo r dep ositio n(PVD)proce ss  or a ch emical vapor deposition  (CVD)  proc ess . Thereaf ter ,  an  electric al ( electropla tin g)or ch emi c al (e lect r ol ess )  proc essm ay be per f or med t odeposit the b u lkcoppe r l a yer 26  abo ve the substrate2 0 and in the o peni n g s 2 2,a s in di cated in FIG.2C.  T h e n, one o rmore chemic al mecha ni c al po lishin g (CMP ) opera t i on s  are p erfo rme d to remo veth e  excess  b ul k  coppe r la ye r 26,thereb y  lea v i ng the through-h ole c o n tacts 25in th eopening s  22,  as shownin FIG. 2D.  Addit iona l pro cessing  o perati ons  m ay be perf o rmed to c ouple  one or  m oreint egrate d ci r c uit d evic es , e .g., memo r y  d e vi ce s , l ogic  devi ce s, e tc.,
A is_formed on_the exposed surfaces of_the silicon_interposer_10. A_plurality_of metal connectors_17 are formed_on the interposer 10._A plurality of_conductive_contacts 12 extend through openings formed in the interposer 10. The interconnects 17 on_the_package 13_may_be_coupled to the interconnects 17_on the interposer 10 by,_for example,_a wire bond 19. A plurality of integrated_circuit_devices 15A, 15B,_15C may be operatively coupled to one another via_the interconnects 17 formed on the_interposer 10. For_example,_the_integrated circuits 15A, 15B_and 15C may be, respectively, a_microprocessor, a capacitor and a memory_device (e.g., a DRAM, an SRAM, etc.).
One_illustrative prior art technique for forming_such through-hole contacts will now_be described_with reference to FIGS. 2A-2D._As shown in_FIG. 2A,_a plurality of_openings 22 are formed in a_semiconducting substrate 20,_such as silicon. The openings 22_may_be formed using_known_photolithography_and etching_processes. Next, a_layer_of insulating_material_21 may be formed on the_exposed_surfaces of the substrate 20. The layer_21 may be formed_by_a thermal oxidation process_or a chemical vapor deposition_process. Thereafter, if desired, a barrier_metal layer,_such as_tantalum, may be formed above the layer of insulating material 21_and in the openings 22. For_purposes of clarity, the_barrier metal_layer_is omitted from_the_referenced figures.
The_next process involves the formation of a_seed layer_24, e.g., a copper seed layer._The copper seed layer_24_may be conformally formed on the_substrate 20 and in the openings_22. The copper seed layer_24_may_have a thickness of approximately_20-100 nm, and it may be_formed by, for_example, a physical vapor deposition (PVD) process_or_a chemical vapor deposition (CVD) process._Thereafter,_an electrical (electroplating) or chemical (electroless)_process_may_be performed to deposit the_bulk copper layer 26 above the_substrate 20 and in the openings 22, as indicated_in FIG. 2C._Then, one or more chemical_mechanical_polishing_(CMP) operations are performed to remove the excess bulk copper_layer 26,_thereby leaving the_through-hole contacts 25 in the openings 22, as shown in_FIG. 2D. Additional processing operations may be_performed to couple one or more integrated circuit devices, e.g., memory_devices, logic devices, etc.,