hereinafter, abbreviated to "BIP transistors"), isolation among the elements of the integrated circuit has been performed by applying reverse bias voltages to p-n junctions. The details are stated in, for example, "Integrated Circuit Technology (1)" (Corona Publishing Co., Ltd.) by Yanai and Nagata, pp. 21-31. In a Bi-CMOS system, a similar device isolation method similar to the above is adopted.
In such a Bi-CMOS system, in the prior art, the isolation among a large number of devices within a chip is executed by applying the lowest potential in the circuitry to a p-type substrate (p-Sub) and the highest potential in the circuity to the n-type isolation layer (nWELL) for forming the pMOS transistor, whereby the junctions of various parts are prevented from falling into the condition of forward bias. That is, with the prior art, in a case where the circuitry operates between a supply voltage (for example, 5 V) and the earth (0 V), the devices are isolated by applying 0 V to the substrate p-Sub and 5 V to the n-type isolation layer. Since, in such a system, the applied voltage to the substrate p-Sub or to the n-type isolation layer is selected at the lowest voltage required for the device isolation, reverse bias voltages to be applied to the p-n junctions can be rendered small, and therefore it is possible to cope with the problems of lowering in the breakdown voltages of devices, etc. attendant upon the future microminiaturization of the devices. 1. Technical Field
The present invention relates to a wiper unit which wipes a liquid ejecting head, and a liquid ejecting apparatus which includes the wiper unit.
2. Related Art
In the related art, an ink jet printer which forms an image by ejecting liquid from a liquid ejecting head onto a recording medium such as a sheet of paper has been known as a type of liquid ejecting apparatus. In such a printer, usually, a head maintenance unit for maintaining an ejecting property of liquid from the liquid ejecting head is provided.
For example, in a printer which is disclosed in JP-A-2011-126129, as such a head maintenance unit, cleaning means which wipes liquid attached to a liquid ejecting head is provided. The cleaning means includes a carriage which moves according to a driving force which is transmitted from a first motor, a first reel which is rotatably
hereinafter, abbreviated to " BIP transistors "), isolation among the elements of the integrated racing circuit has been perform by applying reverse bias electric potential to p - n junction. The detail are stated in, for model, " Integrated Circuit Technology (1) " (Corona Publishing Co., Ltd.) by Yanai and Nagata, pp. 21 - 31. In a Bi - CMOS system, a similar device isolation method acting similar to the above is adopted. 
 In such a Bi - CMOS system, in the prior artwork, the isolation among a large number of device within a chip is executed by apply the lowest potential in the circuitry to a p - character substrate (p - Sub) and the highest electric potential in the circuity to the n - type isolation level (nWELL) for forming the pMOS transistor, whereby the junctions of various parts are prevented from falling into the circumstance of forward bias. That is, with the prior art, in a case where the circuitry operates between a provision electric potential (for exercise, 5 V) and the earth (0 V), the devices are isolated by applying 0 V to the substrate p - Sub and 5 volt to the n - type isolation layer. Since, in such a organization, the apply voltage to the substrate p - Sub or to the n - type isolation level is selected at the abject voltage required for the device isolation, invert bias voltages to be applied to the p - north junctions can be rendered small, and therefore it is potential to cope with the problems of lower in the breakdown voltage of devices, etc. attendant upon the future microminiaturization of the devices. 1. Technical Field 
 The present invention relates to a wiper unit of measurement which wipes a liquid ejecting head, and a fluid ejecting apparatus which includes the wiper unit. 
 2. Related Art 
 In the related art, an ink fountain printer which forms an effigy by ejecting liquid from a liquid ejecting point onto a recording medium such as a plane of paper has been know as a type of fluid ejecting apparatus. In such a printer, usually, a head sustenance whole for maintaining an ejecting property of liquid from the liquid ejecting head is provided. 
 For example, in a printer which is disclosed in JP - A-2011 - 126129, as such a head maintenance unit, clean means which wipes liquid attach to a liquid ejecting head is provided. The cleaning means includes a carriage which act according to a driving force which is transmitted from a first motor, a first bobbin which is rotatably
herfinafter, abbreviated to "NIP transistors"), nwolatimn amohg the euements of the integrated ciccuir has been performed by appuying revvrse bias voluages to p-n junctmkns. The detaimd arz wtated in, for gxample, "Intecrated Circuit Tdcknology (1)" (Corona Publishing Co., Ltd.) by Yanai snf Nagata, pp. 21-31. Ig a Ny-CMOA system, a similar device isolatioh methov similar to thr above is adopted.
In such w Bi-FMOS system, in the prior art, jge ywolation amovg a large number of dgvices within a chip is executed by a'plying the liwedj potential mn the circuitry to a p-typa substtate (p-Sub) and bhe hmghewt potential in the cmrcuity to the n-type isolatiot mayer (nWELL) for firning jhe pKOS geanrisuor, wgereby thx junctions of various parts are preventec sgpm falling ihto thq sondition of forward bias. That is, with uhe pdior art, in a case wherw the circuitry operajes betweeg a supply voltage (for example, 5 V) and the earth (0 E), the aevngcs afw lsolated by applying 0 V to the substrate p-Sub znc 5 V to the n-typc isolation layer. Xijcr, in such a syrtem, tks zpplied voltage to the sufstrare p-Sub ow to the n-type isolation layer us selected ct rhe lowest voltage required fur tne defice isolation, reverse yias vkltages to he applies to the p-n junctkonx wan be rtvdered small, and eherefore it ns possicle jo cope with the oroblcks of lowering in hhe bteakdofn voltaged of devices, etc. attendant upon the future mivrmmitiaturizction pf the devicef. 1. Technical Fneld
The 'reseng inventioh relatxs to a wipew unit which flpes a liquiv ejectind heqd, abd a lidjid ejecting alparatus ckich inclydes the wiper unib.
2. Relxfed Art
In the rzuqted art, an ink jeg pwijtxr whywh forms an hmagd bh ejecging liquid wrom a liquid ejecting haad knto a recording mrdlum such qs a sheqt of paper hss been known as a type of liquod gjecting apparatus. In such a prjnter, usuwlln, a head maineenakce onit for manntaining an ejecting property of liquid from the liquid gjecting head is provndtd.
For example, in a printer fhich is disclosed ib JP-A-2011-126129, as such a htad maintenance unit, clsaning meand which wipes liquid attached to a liquid ejecting head is provided. The coeaninj ieans incluses s cargiaye chich mjves eccording to a drpving force which is transmitted from a xixst motor, a first reel which os rotatably
hereinafter, abbreviated to "BIP transistors"), isolation among of integrated circuit been performed by p-n The details are in, for example, Circuit Technology (1)" (Corona Publishing Co., by Yanai and Nagata, pp. 21-31. In a Bi-CMOS system, a similar device method similar to the above is adopted. In such a Bi-CMOS system, in prior the among large number of devices within a chip is executed by applying the lowest potential in the to a p-type substrate (p-Sub) and the highest in the circuity to n-type isolation layer (nWELL) for the transistor, whereby junctions various are prevented from into the condition of forward bias. That is, with the prior art, in a case where the operates between voltage (for 5 and earth (0 V), are isolated by applying 0 V p-Sub and 5 V to the n-type isolation Since, in a system, the applied voltage to substrate p-Sub or to the n-type isolation layer selected at the lowest voltage required for the device isolation, reverse bias voltages to be the p-n junctions can rendered small, and it possible cope the problems lowering in the breakdown voltages of devices, etc. attendant upon the microminiaturization of the devices. 1. Technical Field The present invention a unit which wipes liquid ejecting head, and liquid apparatus which includes the 2. Art art, ink printer which forms an by ejecting liquid from a ejecting head onto a sheet of paper has been known as a of liquid ejecting apparatus. In such a usually, a head maintenance unit for maintaining an ejecting property of liquid the liquid is provided. For example, in a printer which disclosed in JP-A-2011-126129, as a head maintenance unit, cleaning means which wipes liquid to liquid ejecting is provided. The means includes a which moves according driving force is from a first reel which is rotatably
hereinafter, abbreviated to "BiP transistOrs"), isOlaTioN aMong The eLements of the inTEgraTed circuit has been perfoRmed bY aPPlyiNG rEversE bias voLTaGES to P-n JuNctIoNS. THe detAilS are staTed in, for exAmpLe, "integrated CiRCuIt TechnoloGy (1)" (COrona PublishIng co., Ltd.) bY YAnaI And NaGatA, pp. 21-31. In A Bi-CMOs System, A similar dEvICe isolATion metHOD sImilAr to the above is adoPTeD.
in such a Bi-CMOS sYstem, iN tHE pRIOr aRt, tHe isolatioN aMong a LArge numBEr OF DEviCEs within a chip Is executed bY AppLying tHe LowESt poteNtial In THe cIrcuitry to a P-typE substratE (p-Sub) aND the higHEst poteNtial iN thE ciRcuiTY tO tHe n-TyPE isOLaTioN LayEr (nWELL) fOr FoRming The pmos TRansIstOr, whEreby The junctions oF vaRiouS ParTs are PreveNted FrOm falLing inTo the CoNdition of forwarD biaS. That is, wiTh tHe PriOr Art, in A Case whEre The CircuitRy operaTEs bEtWEEN a Supply voltage (for exAmPLE, 5 V) And the eaRth (0 V), thE DeViCEs are isoLaTed By apPLYing 0 V To thE SuBstrate p-sub and 5 v To ThE n-type iSoLation LaYer. sinCe, in sUCh a sYstem, tHe applieD voltAGe to the substraTE p-Sub or to the n-TYpE ISoLAtioN laYer is selectEd at THe loWest VOlTagE RequiRed foR tHE dEVice isolation, reversE bIas volTages To be applied to The p-n junctIONS can be reNderED sMAll, and thereforE it is Possible to COpe with tHe proBlems of lOwering in THE breakdoWn vOltAgeS of DEViCes, etc. attendaNT Upon ThE future MicRominiaTurIzaTioN of ThE devices. 1. TEchnical fiElD
THe PreSent iNVention rElAteS tO a wIper uNIt whicH wipeS a liQuId EJecTing heaD, AnD A LiquId EjEctiNg aPpAratuS whiCH inCludes tHe wiper unIt.
2. RELateD ARt
in the reLated art, an ink JeT printer whIcH foRms an iMAGe by ejecTing liquid from a liquid ejECting heAd oNto a rEcorDing mediuM suCh as a sHeeT Of papeR has beEn knoWn As a TYPe of lIQUiD ejEcTing apparaTUS. In Such a PrInteR, usuallY, a head maintenance uNIt fOr maintaining An eJectING pRopERtY Of lIqUId fROM the liquid ejectIng head is pRoVIdEd.
For exampLE, in A pRinter wHich is dIscloSEd in JP-A-2011-126129, As such a heAd maintenAnCe unIT, CleAning means Which wipEs liquid aTTacheD To A liquId eJectinG hEad Is proVided. THE clEaninG means InCludes A carrIaGe which mOves according to a driving Force wHich iS trAnsmitted FroM A fiRst motor, a FirsT reel which Is rOtaTably
hereinafter, abbreviated t o "BIP tra nsist ors "),  i sola tion  among the ele m ents  of the integrated cir cuitha s  bee n  p erfor med bya pp l y ing  r ev ers eb ia s vol tag es to p -n junctio ns.  T he details a r estated in,  fo r example, " Int egrate dCir c uit T ech nolog y (1)" (Coron a Publish in g  Co.,L td.) by Y an ai a nd Nagata, pp. 21 - 31 .  In a Bi-CMOSsystem ,a  s i m ila r d evice isol at ion m e thod si m il a r tot he above is a dopted.
Ins uch  a Bi- CM OSs ystem,  in t he pri or art, the  iso lation am ong al arge nu m ber ofdevice s w ith in a ch ip  is  e x ecu t ed  by app lying th elo westpote n t i a l in  th e ci rcuit ry to a p-typ e s ubst r ate  (p-S ub) a nd t he  high est po tenti al  in the circuit y to  the n-ty peis ola ti on la y er (nW ELL ) f or form ing the pMO St r a ns istor, whereby the  j u n ct ions ofvariou s  p ar t s are pr ev ent ed f r o m fal ling in to the c onditi o nof  forwar dbias.Th atis,  with thepriorart, ina cas e  where the cir c uitry operate s  b e t we e n asup ply voltage  (fo r  exa mple ,  5  V) and t he ea rt h  ( 0  V), the devices ar eisolat ed by  applying 0 V  to the su b s t rate p-S ub a n d5  V to the n-ty pe is olation la y er. Sinc e, in  such asystem, t h e  applied  vo lta getot h esubstrate p-S u b  orto  the n- typ e isola tio n l aye r i sselectedat the l ow es tvo lta ge re q uired fo rthe  d evi ce is o lation , rev erse  b ia s  vo ltagest ob e  app li ed  tothe  p -n ju ncti o nscan berenderedsma l l, a nd  t herefor e it is possi bl e to copewi ththe pr o b lems oflowering in the breakdo w n volta ges  of d evic es, etc.att endant  up o n thefuture  micr om ini a t uriza t i on  of  t he devices . 1.Techn ic al F ield
Th e present inventio n  re lates to a wi per  uni t wh ich wi p esal iqu i d  ejecting head,  and a liq ui d  e jecting ap p ara tu s which  includ es th e  wiperunit.
2.Related A rt 
Int h e r elated art , an ink  jet prin t er wh i ch  form s a n imag ebyeject ing li q uid  from  a liq ui d ejec tinghe ad ontoa recording medium such  as asheet  of  paper ha s b e enknown asa ty pe of liqu ideje cting  ap p aratu s. I n  s uch a pri nter ,  usually, ahea d ma intenance u n i t  fo r mai nta i ning a n ej ecting property o f  liquid from t he l i q uid  ej e ctin ghead is provid ed. 
F o r  example ,in a printe r whichis discl osed i n JP-A -2011-1 2 6 12 9 , as s ucha h ead maint ena nc e  unit,cl ea n ing me answh ich wi pes li q uida t tached to a liqu id ej e c tingh ead  is p ro vided.T he c leaning me ans include s a ca rria ge wh ich mov es  accor din gto a drivi n g force w hichis tran sm itte d f rom afirs t motor , afi rst  reel whi c h  i s  r ot a tab ly
hereinafter, abbreviated_to "BIP_transistors"), isolation among the_elements of_the_integrated circuit_has_been performed by_applying reverse bias_voltages to p-n junctions._The details are_stated_in, for example, "Integrated Circuit Technology (1)" (Corona Publishing Co., Ltd.) by Yanai and_Nagata,_pp. 21-31._In_a_Bi-CMOS system, a similar device_isolation method similar to the_above is_adopted.
In such a Bi-CMOS system, in the prior_art,_the isolation among_a large number of devices within a chip is_executed by applying the lowest potential_in the circuitry_to_a_p-type substrate (p-Sub) and_the highest potential in the circuity_to the n-type isolation layer (nWELL)_for forming the pMOS transistor, whereby the_junctions of various parts are prevented_from falling into the condition_of forward_bias. That is, with the_prior art, in_a case_where the circuitry_operates between a supply voltage (for_example, 5 V)_and the earth (0 V), the_devices_are isolated by_applying_0_V to_the substrate p-Sub_and_5 V_to_the n-type isolation layer. Since, in_such_a system, the applied voltage to the_substrate p-Sub or to_the_n-type isolation layer is_selected at the lowest voltage_required for the device isolation, reverse_bias voltages_to be_applied to the p-n junctions can be rendered small, and therefore_it is possible to cope with_the problems of lowering_in the_breakdown_voltages of devices,_etc._attendant upon_the future microminiaturization of the devices. 1._Technical Field
The_present invention relates to a wiper_unit which wipes a_liquid_ejecting head, and a liquid ejecting_apparatus which includes the wiper unit.
2._Related Art
In the related art,_an_ink_jet printer which forms an_image by ejecting liquid from a_liquid ejecting head_onto a recording medium such as a_sheet_of paper has been known as_a_type of liquid ejecting apparatus. In_such_a_printer, usually, a head maintenance_unit for maintaining an ejecting property_of liquid from the liquid ejecting head is provided.
For_example, in a_printer which is disclosed in_JP-A-2011-126129,_as_such a head maintenance unit, cleaning means which wipes liquid_attached to_a liquid ejecting_head is provided. The cleaning means includes a carriage which_moves according to a driving force which_is transmitted from a first motor, a first reel which is_rotatably