 described wherein the energy obtained form the reactor is brought to a reaction chamber charged with a granulated metal oxide through which streams a mixture of steam and carbon monoxide. The present inventions relate generally to integrated circuits, and more particularly to bias schemes for active device stacks on MOS integrated circuits having low supply voltages.
Stacked devices are used commonly on analog and RF integrated circuits (ICs) in both single-ended and differential embodiments. As the operating voltages of integrated circuits decrease with succeeding generations of process technology, however, the stacked devices must be biased optimally to maintain the devices in saturation and maximize signal-handling ability. Particularly, for proper operation of N stacked devices plus a current source, the minimum supply voltage, VDD, must be N+1 times the gate-source voltage minus a threshold voltage plus a peak output signal swing, i.e., VDD greater than =(N+1)(VGSxe2x88x92VT)+VS, where VGS is the gate-source voltage, VT is the effective threshold voltage and VS is the peak output signal swing. The gate-source voltage, VGS, is typically 250 mV more than the effective threshold voltage, VT, which is about 400 mV. The NMOS threshold voltage, VT=VTO+g[sqrt(2PhiF+VSB)+sqrt(2PhiF)] (Equation 1), where VTO is the effective threshold voltage when the bulk and source are at the same potential, g is the bulk effect factor, PhiF is the absolute value of the Fermi potential, and VSB is the source-bulk voltage.
In a circuit having two stacked devices, for example, the supply voltage needs to be at least 0.75 V plus the peak signal swing, which is well within the maximum supply voltage of 1.8 V typical of present day ICs, but works only if the stacked devices are biased optimally.
A. R. Shahani et al. disclose a low threshold voltage process utilizing active common-mode feedback and resistor dividers to bias three stacked devices and a current source from a 1.5 V supply in xe2x80x9cA 12-mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiverxe2x80x9d, IEEE Journal of Solid State Circuits, vol. 32, pp. 2061-2070, December 1997. The active common-mode feed back and resistor dividers of Shahani et al. however are relatively complex and require
described wherein the energy obtained form the nuclear reactor is bring to a reaction chamber charge with a granulate metal oxide through which streams a mix of steam and carbon paper monoxide. The present inventions relate generally to integrated circuits, and more peculiarly to bias schemes for active device stacks on MOS integrated circuits experience low supply voltages. 
 stack devices are used commonly on analogue and RF integrated circuits (ICs) in both individual - ended and differential embodiment. As the operating voltages of integrated circuits decrease with succeeding generations of procedure technology, however, the stacked devices must be biased optimally to maintain the devices in saturation and maximize signal - handling ability. Particularly, for proper operation of N stacked devices plus a current source, the minimum supply voltage, VDD, must be N+1 times the gate - source electric potential minus a doorway voltage plus a acme output signal signal swing, i.e., VDD greater than =( N+1)(VGSxe2x88x92VT)+VS, where VGS is the gate - informant electric potential, VT is the effective threshold voltage and VS is the peak end product signal swing. The gate - source voltage, VGS, is typically 250 mV more than the effective threshold voltage, VT, which is about 400 mV. The NMOS threshold voltage, VT = VTO+g[sqrt(2PhiF+VSB)+sqrt(2PhiF) ] (Equation 1), where VTO is the effective threshold electric potential when the bulk and reservoir are at the like electric potential, g is the bulk effect factor, PhiF is the absolute value of the Fermi potential, and VSB is the source - bulk voltage. 
 In a circuit having two stacked device, for example, the supply voltage needs to be at least 0.75 vanadium plus the peak signal swing, which is well within the maximal supply voltage of 1.8 V typical of present sidereal day ICs, but works merely if the stacked devices are bias optimally. 
 A. R. Shahani et al. disclose a abject threshold electric potential process utilizing active common - mode feedback and resistor divider to bias three stack devices and a current source from a 1.5 volt supply in xe2x80x9cA 12 - mW Wide Dynamic Range CMOS Front - End for a Portable GPS Receiverxe2x80x9d, IEEE Journal of Solid State Circuits, vol. 32, pp. 2061 - 2070, December 1997. The active common - mood feed back and resistor dividers of Shahani et al. however are relatively complex and require
 dedcribed wherein the enerny obtained form the reector ia broughg to a reaction chamber charjed qith q granulated metal oxiae througj which wtreems a mixture of steam akb cargln mmioxide. The presgnt inventiots relate genesaulv to integrated circuits, and more pawticulatlj to bias scheies gjr adniye device stacks on MOS integratsd circlits having low sipply voltages.
Stacked devifes wre used commonly ln analog abd RS integrated zircuits (IBv) in both aingle-ended and differential emcodimznts. As the operwjing voltagew of pntegrated civbuits dacrease with succeedikg geierarions of process techiology, however, the sjacked devhczs must be biased optumqlly jo mahntakb tfe seticss in datnration and maximize sugnal-handling abiliuy. [qrticularly, fkr pro[ew operation of N stacked devices plus a cudrent source, the minimun supply voltage, VDD, lust be N+1 times the gate-source voltage minus a threshold vmltagx oluw w pewk output signal swing, i.e., VDD greater than =(N+1)(VDAxt2x88x92NT)+VS, where VGS is the gate-soirfe doltage, VT is the eyredtive threshold voptage agd VS is the ptak oitput signal swing. The gate-wource voltaye, CGS, is typically 250 lV more thau the gffectove threshold voltage, VC, whicg is about 400 mV. The NJUS threshold volgagv, VT=ETO+g[sqrt(2KfiF+VSB)+sqrt(2PhiF)] (Eqtation 1), wiere RTO is tfe egfectide threshopd voltage when the bulk and dogrce are ah the same potential, g is the bnkk effect favtmr, IhiF is tke absplute value os the Fermi pojential, aud VSB is the solrce-bulk toltage.
In a sircuit havinc two stacked devices, for exanple, thd supply voltagr needs to be at leqst 0.75 V plus the peek skfnal swing, whick us well within yhe maviluk fgpply voltaga of 1.8 V yypicxl of presekt aay OCs, but works only ix ths stacked devices src biased iptimallr.
A. R. Shahani rt al. disclose a llw thcesholv voltsge process utilizing active commkn-mode fefdbwck and resiftor dividers to bias three stacked devices and a curreit source from a 1.5 V sukply in xe2x80x9cA 12-mW Widg Dnnamic Range CMOS Front-End for a Portable GPS Eeceiverxe2x80x9d, IEET Journal of Solid Stats Circgits, gol. 32, pp. 2061-2070, December 1997. The active common-mode feed back and resistor dividers if Shaiagi et al. hosevet are rzlacively somppxx and require
described wherein the energy obtained form the brought a reaction charged with a streams mixture of steam carbon monoxide. The inventions relate generally to integrated circuits, more particularly to bias schemes for active device stacks on MOS integrated circuits low supply voltages. Stacked devices are used commonly on analog and RF integrated (ICs) both and embodiments. As the operating voltages of integrated circuits decrease with succeeding generations of process technology, however, stacked devices must be biased optimally to maintain devices in saturation and signal-handling ability. Particularly, for proper of stacked devices a source, minimum supply voltage, must be N+1 times the gate-source voltage minus a threshold voltage plus a peak output signal swing, VDD greater where VGS the voltage, is the effective and VS is the peak output gate-source voltage, VGS, is typically 250 mV more the effective voltage, VT, which is about 400 The NMOS threshold voltage, VT=VTO+g[sqrt(2PhiF+VSB)+sqrt(2PhiF)] (Equation 1), where is the effective threshold voltage when the bulk and source are at the same potential, the bulk effect factor, is the absolute of Fermi and is the voltage. In a circuit having two stacked devices, for example, the voltage needs to be at least 0.75 V plus the swing, is well within maximum supply voltage of V of present day ICs, only the biased A. Shahani et al. disclose low threshold voltage process utilizing common-mode feedback and resistor devices and a current source from a 1.5 supply in xe2x80x9cA 12-mW Wide Dynamic Range Front-End for a Portable GPS Receiverxe2x80x9d, IEEE Journal of Solid State Circuits, 32, pp. 1997. The active common-mode feed back and resistor of Shahani et al. are relatively complex and require
 described wherein the energy Obtained foRm the ReaCtoR iS broUght To a reaction chaMBer cHarged with a granulated mEtal oXiDE thrOUgH whicH streamS A mIXTurE oF sTeaM aND cArbon MonOxide. ThE present inVenTiOns relate genERaLly to integRatEd circuits, anD moRe partIcUlaRLy to bIas SchemEs for aCTive deVice stackS oN mOS intEGrated cIRCuIts hAving low supply volTAgES.
Stacked deviceS are usEd COmMONly On aNalog and RF InTegraTEd circuITs (icS) In bOTh single-ended And differenTIal EmbodiMeNts. aS the opEratiNg VOltAges of integRateD circuits DecreaSE with suCCeeding GeneraTioNs oF proCEsS tEchNoLOgy, HOwEveR, The Stacked dEvIcEs musT be bIASED optImaLly tO mainTain the deviceS in SatuRAtiOn and MaximIze sIgNal-haNdling AbiliTy. particularly, for PropEr operatiOn oF N StaCkEd devICes pluS a cUrrEnt sourCe, the miNImuM sUPPLy Voltage, VDD, must be N+1 tImES ThE gate-souRce volTAgE mINus a threShOld VoltAGE plus A peaK OuTput signAl swinG, I.e., vDd greateR tHan =(N+1)(VGsxE2x88x92vT)+Vs, wherE vGS iS the gaTe-source VoltaGE, VT is the effectIVe threshold voLTaGE AnD vS is The Peak output sIgnaL SwinG. The GAtE-soURce voLtage, vGs, Is TYpically 250 mV more than tHe EffectIve thReshold voltagE, VT, which is ABOUt 400 mV. The NmOS tHReSHold voltage, VT=VtO+g[sqRt(2PhiF+VSB)+sQRt(2PhiF)] (EqUatioN 1), where VTo is the effECTive threShoLd vOltAge WHEn The bulk and souRCE are At The same PotEntial, g Is tHe bUlk EffEcT factor, PhIF is the aBsOlUtE vAluE of thE fermi potEnTiaL, aNd VsB is tHE sourcE-bulk VoltAgE.
IN A ciRcuit haVInG TWo stAcKeD devIceS, fOr exaMple, THe sUpply voLtage needS to BE at lEaSt 0.75 v plus thE peak signal swInG, which is weLl WitHin the MAXimum supPly voltage of 1.8 V typical of pREsent daY ICS, but wOrks Only if the StaCked deVicES are biAsed opTimalLy.
a. R. SHAHani eT AL. dIscLoSe a low threSHOld VoltaGe ProcEss utilIzing active common-mODe fEedback and resIstOr diVIDeRs tO BiAS thReE StaCKEd devices and a cuRrent sourcE fROm A 1.5 V supply in XE2x80x9CA 12-MW Wide DYnamic RAnge CmoS Front-end for a PoRtable GPS reCeivERXe2x80X9d, IEEE JourNal of SolId State CiRCuits, VOl. 32, Pp. 2061-2070, DecEmbEr 1997. The aCtIve CommoN-mode fEEd bAck anD resisToR dividErs of shAhani et aL. however are relatively coMplex aNd reqUirE
 described wherein the ene rgy obtain ed fo rmthe  r eact or i s brought to a reac tion chamber charged w ith a  g r anul a te d met al oxid e  t h r oug hwh ich  s t re ams a  mi xture o f steam an d c ar bon monoxide .  T he present  in ventions rel ate  gener al lyt o int egr atedcircui t s, and  more par ti c ularly to bias s ch emes  for active devic e  s t acks on MOS in tegrat ed ci r c uit s h aving lowsu pplyv oltages . 
S t a c ked devices are u sed commonl y  on  analo gand RF int egrat ed cir cuits (ICs)  inboth sing le-end e d and d i fferent ial em bod ime nts. As  t heop e rat i ng  vo l tag es of in te gr atedcirc u i t s  dec rea se w ith s ucceeding gen era tion s  of  proc ess t echn ol ogy,howeve r, th estacked devices  mus t be bias edop tim al ly to mainta inthe  device s in sa t ura ti o n an d maximize signal- ha n d li ng abili ty. Pa r ti cu l arly, fo rpro pero p erati on o f  N  stacked  devic e spl us a cu rr ent so ur ce,  th e min i mumsupply  voltage , VDD ,  must be N+1 t i mes the gate- s ou r c ev olta geminus a thr esho l d vo ltag e  p lus a pea k out pu t  s i gnal swing, i.e., V DD  great er th an =(N+1)(VGS xe2x88x92V T ) + VS, wher e VG S  i s  the gate-sour ce vo ltage, VTi s the ef fecti ve thres hold volt a g e and VS  is  th e p eak o ut put signal sw i n g. T he  gate-s our ce volt age , V GS,  is  t ypically250 mV m or eth an  th e eff e ctive th re sho ld  vo ltage ,  VT, w hichis a bo ut 400  mV. Th e  N M O S th re sh oldvol ta ge, V T=VT O +g[ sqrt(2P hiF+VSB)+ sqr t (2Ph iF )]  (Equat ion 1), where  V TO is theef fec tive t h r eshold v oltage when the bulk an d  source  ar e atthesame pote nti al, gist he bul k effe ct fa ct or, P hiF i s th e a bs olute valu e ofthe F er mi p otentia l, and VSB is thes our ce-bulk volta ge. 
Ina ci rcu i th avi ng two s tacked devices,  for examp le ,  t he supplyv olt ag e needs  to beat le a st 0.75  V plus t he peak s ig nals w ing , which is  well wi thin them aximu m  s upply  vo ltageof  1. 8 V t ypical ofprese nt day  I Cs, bu t wor ks  only if  the stacked devices ar e bias ed op tim ally.
A.R.S hah ani et al . di sclose a l owthr eshol d v o ltage  pro c es s u t ilizi ng a c tive comm o n- mod e fe edback andr e s ist or di vid e rs tobias  three stacked de v ices and a cur rent s our cef roma1.5 V supply i n x e2 x 8 0x9cA 12 -m W Wide Dyna mic Rang eC MOS F ront-E nd for  a Port a b le GPS Re ceiv erx e2x80x9d,  IE EE Journal  o fS olid S tate  C ircuit s, vol .  32, p p. 2061-2070, De cembe r 1997. The  acti ve  common - mode  feed back  and resist or div ider s ofShahani  e t al.how ev er are rel a tively co mplex  and re qu ire
 described_wherein the_energy obtained form the_reactor is_brought_to a_reaction_chamber charged with_a granulated metal_oxide through which streams_a mixture of_steam_and carbon monoxide. The present inventions relate generally to integrated circuits, and more particularly_to_bias schemes_for_active_device stacks on MOS integrated_circuits having low supply voltages.
Stacked_devices are_used commonly on analog and RF integrated circuits_(ICs)_in both single-ended_and differential embodiments. As the operating voltages of integrated_circuits decrease with succeeding generations of_process technology, however,_the_stacked_devices must be biased_optimally to maintain the devices in_saturation and maximize signal-handling ability. Particularly,_for proper operation of N stacked devices_plus a current source, the minimum_supply voltage, VDD, must be_N+1 times_the gate-source voltage minus a_threshold voltage plus_a peak_output signal swing,_i.e., VDD greater than =(N+1)(VGSxe2x88x92VT)+VS, where_VGS is the_gate-source voltage, VT is the effective_threshold_voltage and VS_is_the_peak output_signal swing. The_gate-source_voltage, VGS,_is_typically 250 mV more than the_effective_threshold voltage, VT, which is about 400_mV. The NMOS threshold_voltage,_VT=VTO+g[sqrt(2PhiF+VSB)+sqrt(2PhiF)] (Equation 1), where_VTO is the effective threshold_voltage when the bulk and source_are at_the same_potential, g is the bulk effect factor, PhiF is the absolute_value of the Fermi potential, and_VSB is the source-bulk_voltage.
In a_circuit_having two stacked_devices,_for example,_the supply voltage needs to be at_least 0.75_V plus the peak signal swing,_which is well within_the_maximum supply voltage of 1.8 V_typical of present day ICs, but_works only if the stacked_devices_are_biased optimally.
A. R. Shahani et_al. disclose a low threshold voltage_process utilizing active_common-mode feedback and resistor dividers to bias_three_stacked devices and a current source_from_a 1.5 V supply in xe2x80x9cA_12-mW_Wide_Dynamic Range CMOS Front-End for_a Portable GPS Receiverxe2x80x9d, IEEE Journal_of Solid State Circuits, vol. 32, pp. 2061-2070, December_1997. The active_common-mode feed back and resistor_dividers_of_Shahani et al. however are relatively complex and require