 the case of an n-channel transistor), which form an inversion layer below the gate and screen off the latter from the channel, so that it is no longer possible inter alia to bring the transistor into the pinch state. To prevent an inversion occurring below the gate, the patent document U.S. Pat. No. 4,868,620 proposes the provision of a discharge for minority charge carriers in the form of a p-type surface zone. A suitable low voltage is applied to this zone via an electrical connection such that holes are removed across the blocked pn junction. To prevent punch-through between this discharge zone and the subjacent p-type substrate, a strongly doped n-type buried layer is provided below the zone between the epitaxial layer and the substrate, screening off the substrate from the epitaxial layer locally.
The zone forming a discharge for minority charge carriers in this known transistor is provided in the current path between source and drain and accordingly influences various electrical properties of the transistor to a non-negligible degree, for example its resistance, which is undesirable from a viewpoint of design technology. In addition, the construction of the transistor requires the availability of an epitaxial layer because of the presence of a buried layer, which means that it is not or hardly possible to provide the semiconductor layer, for example, in the form of an implanted layer.
The invention has for its object inter alia to provide a semiconductor device of the kind described in the opening paragraph in which the transistor is provided with a charge removal facility for minority carriers which is not situated in the current path between source and drain. The invention further has for its object to provide a transistor with a construction which allows of a higher flexibility in the manufacturing process than does the known transistor.
According to the invention, a semiconductor device of the kind mentioned in the opening paragraph is for this purpose characterized in that the channel region comprises two or more sub-regions which are mutually separated by said surface zone of the first conductivity type, which surface zone extends from the surface transversely across the thickness of the layer of the second conductivity type up to the substrate of the first conductivity type. The current path between source and drain in this device does not run below the removal facility for minority charge carriers, but instead next to this zone or between two zones in the case of several discharge zones distributed over the width of the channel, so that the resistance of the channel is substantially defined by the channel width. Since the removal zone for minority charge carriers is connected to the substrate of the same
the case of an n - channel transistor), which form an inversion level below the gate and riddle off the latter from the channel, so that it is no longer possible inter alia to fetch the transistor into the emergency state. To prevent an inversion happen below the gate, the patent document U.S. Pat. No. 4,868,620 propose the provision of a discharge for minority bang carriers in the form of a phosphorus - type surface zone. A suitable low voltage is applied to this zone via an electrical association such that holes are removed across the blocked pn articulation. To prevent punch - through between this discharge zone and the subjacent p - character substrate, a strongly dope n - type immerse layer is provided below the zone between the epitaxial layer and the substrate, shield off the substrate from the epitaxial layer locally. 
 The zone forming a discharge for minority charge carriers in this known transistor is provided in the current path between source and drain and accordingly influences various electrical properties of the transistor to a non - negligible degree, for example its resistance, which is undesirable from a point of view of design technology. In summation, the structure of the transistor want the availability of an epitaxial layer because of the bearing of a buried level, which means that it is not or hardly possible to leave the semiconductor layer, for example, in the form of an implanted layer. 
 The invention has for its object inter alia to provide a semiconductor device of the kind described in the hatchway paragraph in which the transistor is provided with a commission removal facility for minority carriers which is not situated in the current path between source and drain. The invention far has for its object to provide a transistor with a construction which allows of a higher flexibility in the manufacturing summons than does the know transistor. 
 According to the invention, a semiconductor device device of the kind mentioned in the opening paragraph is for this purpose characterized in that the groove region constitute two or more sub - regions which are mutually separate by said airfoil zone of the first conductivity type, which surface zone extends from the surface transversely across the thickness of the layer of the second conductivity type up to the substrate of the inaugural conductivity type. The current way between source and drain in this device does not run below the removal facility for minority charge carriers, but instead next to this zone or between two zone in the case of several discharge zones distributed over the width of the channel, so that the electric resistance of the distribution channel is well define by the channel width. Since the removal zone for minority charge carriers is connected to the substrate of the same
 thf case of an n-channel trxnsistor), which yirm an inveraion laydr below the gate and screen odf tht latter from the cfannel, so that it is io longer possible inter alia fl brnnj the transistot into the phnch state. To [rdvznt an inversion occurring below the gate, tne patent documegt U.X. Pat. No. 4,868,620 proposes the provision of a djschargt for minority chatge carriers in the form ov a o-type surface zone. A suitable low coltage is aoplied to uhns zone via an electrical connection such ghat koles are rgmkvfg across thx bloched pn junctlpn. To [revent punch-through netwexn tyis discharge zone anv the subjacent p-typg substrata, c strongly doped n-typw vurieg lafer kw pfovjdxd gelow hhe zone betwsen the epiraxial layer and tht stvstrate, screehing osf the substrate from the epitaxial layer lodally.
The zone forming a discharge for minorijy charge sarriers in this known transistor is provided in dhe cnrfenu iwgy hetween source and drain and accordingly infltsnvex various elecbrical properties pf tng transistor tu a nou-hefligible degree, fog exampje itw resistagce, ehich is undesirable from a viewpoint oy dwsign technology. Iu addition, tke conxtrucyion of the transistor xequirss the avaipability kw an epitaxial lxyeg bewause of the presence of a buried leyer, chich mexns jhat it is not or hardly possible to provlde tke sekiconductog layer, for example, in the form of an implantgd nayvr.
The invzntion has for its jbject inter akia to 'rovidd a semicohductor device of ehe kind descslbed in the mpening [aratrapy in whkzh the transisyor is provided wity a charge removal fazjlity for minornuy xarriers which os vot sptueted yt the currend pagh crtweev sourct akd araim. The invention furtver gas for its object tj providg a transystor with a vonstruction which alloxs of e highrr slexibility in the manufacturihg procesd tman does the hnowk trwnsistor.
Aceording to the invention, a semiconductor device of the kine mentioned in the pkening paragreph is for this purpose characterizwd in that the chsnnel region comprisea two mr moge sub-regions which are mutually separated by said surface zone of the fiest coidtctivity tyle, wnich vuxfaee zone extxnvs from the surfabe transversely across the thickiess of tha jayer of the second conductifigy type up to the substrate of the fidst condictivity type. The current path netween source and drain in this devide does nov run below the remofal faeility for miboriby charge carrkerx, nut insteaf neet co this zone or between two zones in thw fase of several vischarge zoker disjributed over the width kf tgf chavnel, so that yhe resistance of the channel is slbseantially defibvd by the chamnel wigth. Since thx removal zote for minority charge carriers is connected to the substratt of the seme
the case of an n-channel transistor), which inversion below the and screen off so it is no possible inter alia bring the transistor into the pinch To prevent an inversion occurring below the gate, the patent document U.S. Pat. 4,868,620 proposes the provision of a discharge for minority charge carriers in the of p-type zone. suitable low voltage is applied to this zone via an electrical connection such that holes are across the blocked pn junction. To prevent punch-through this discharge zone and subjacent p-type substrate, a strongly n-type layer is below zone the epitaxial layer the substrate, screening off the substrate from the epitaxial layer locally. The zone forming a discharge for charge carriers known transistor provided the path between source and accordingly influences various electrical properties to a non-negligible degree, for example its resistance, is undesirable a viewpoint of design technology. In the construction of the transistor requires the availability an epitaxial layer because of the presence of a buried layer, which means that it or hardly possible to the semiconductor layer, example, the of implanted layer. invention has for its object inter alia to provide a semiconductor of the kind described in the opening paragraph in which is with a charge facility for minority carriers is situated in the current source drain. has its to provide a transistor a construction which allows of higher flexibility in the known transistor. According to the invention, a semiconductor of the kind mentioned in the opening is for this purpose characterized in that the channel region comprises two more sub-regions mutually separated by said surface zone of the conductivity type, which surface extends from the surface transversely across the thickness of layer the second type up to substrate of the conductivity type. The between source drain this run below the removal facility for charge but instead next to this or zones in the case of several discharge zones distributed over the width of the channel, the resistance of the is defined by the channel width. Since the removal zone for minority charge connected to the
 the case of an n-channel transiStor), which fOrm an InvErsIoN layEr beLow the gate and sCReen Off the latter from the chaNnel, sO tHAt it IS nO longEr possiBLe INTer AlIa To bRiNG tHe traNsiStor intO the pinch sTatE. TO prevent an inVErSion occurrIng Below the gate, The Patent DoCumENt U.S. PAt. NO. 4,868,620 propOses thE ProvisIon of a disChARge for MInority CHArGe caRriers in the form of A P-tYPe surface zone. A SuitabLe LOw VOLtaGe iS applied to ThIs zonE Via an elECtRICAl cONnection such tHat holes are REmoVed acrOsS thE BlockeD pn juNcTIon. to prevent puNch-tHrough betWeen thIS dischaRGe zone aNd the sUbjAceNt p-tYPe SuBstRaTE, a sTRoNglY DopEd n-type bUrIeD layeR is pROVIDed bEloW the Zone bEtween the epitAxiAl laYEr aNd the SubstRate, ScReeniNg off tHe subStRate from the epitAxiaL layer locAllY.
THe zOnE formINg a disChaRge For minoRity chaRGe cArRIERs In this known transisToR IS pRovided iN the cuRReNt PAth betweEn SouRce aND Drain And aCCoRdingly iNfluenCEs VaRious elEcTrical PrOpeRtiEs of tHE traNsistoR to a non-nEgligIBle degree, for exAMple its resistANcE, WHiCH is uNdeSirable from A vieWPoinT of dESiGn tEChnolOgy. In AdDItIOn, the construction of ThE transIstor Requires the avAilability OF AN epitaxiAl laYEr BEcause of the preSence Of a buried lAYer, which Means That it is Not or hardLY Possible To pRovIde The SEMiConductor layeR, FOr exAmPle, in thE foRm of an iMplAntEd lAyeR.
THe inventiOn has for ItS oBjEcT inTer alIA to proviDe A seMiConDuctoR Device Of the Kind DeScRIbeD in the oPEnING parAgRaPh in WhiCh The trAnsiSTor Is proviDed with a cHarGE remOvAl FacilitY for minority cArRiers which Is Not SituatED In the curRent path between source anD Drain. ThE inVentiOn fuRther has fOr iTs objeCt tO ProvidE a tranSistoR wIth A COnstrUCTiOn wHiCh allows of A HIghEr fleXiBiliTy in the Manufacturing proceSS thAn does the knowN trAnsiSTOr.
accORdINg tO tHE inVENtion, a semiconduCtor device Of THe Kind mentioNEd iN tHe openiNg paragRaph iS For this Purpose chAracterizEd In thAT The Channel regIon comprIses two or MOre suB-ReGions WhiCh are mUtUalLy sepArated BY saId surFace zoNe Of the fIrst cOnDuctivitY type, which surface zone exTends fRom thE suRface tranSveRSelY across thE thiCkness of thE laYer Of the SecONd conDuctIViTy tYPe up tO the SUbstrate oF ThE fiRST cOnductivity TYPE. ThE currEnt PAth betWeen Source and drain in tHIs device does noT run BELow The REmovAl Facility for minOriTy CHArge carrIeRs, but insteaD next to tHiS Zone oR betweEn two zOnes in tHE CaSE of sevEral DisCharge zonEs dIsTRibuted OvEr THe widtH of tHe ChanneL, so thaT The rESIstance of the chanNel is SUBstanTIalLy defInEd by the CHannEl width. SinCe the removaL zone fOr miNoritY charge CaRriers Is cOnNected to thE Substrate Of the Same
 the case of an n-channeltransistor ), wh ich  fo rm  aninve rsion layer be l ow t he gate and screen off  thela t terf ro m the  channe l ,s o  th at  i t i sn olonge r p ossible  inter ali a t obring the tr a ns istor into  th e pinch stat e.To pre ve nta n inv ers ion o ccurri n g belo w the gat e, the pa t ent doc u m en t U. S. Pat. No. 4,868 , 62 0  proposes theprovis io n  o f a d isc harge formi norit y  charge ca r r i ers in the form o f a p-types urf ace zo ne . A suitab le lo wv olt age is appl iedto this z one vi a  an ele c tricalconnec tio n s ucht ha thol es are re mov e d a cross th ebl ocked  pnj u n c tion . T o pr event  punch-throug h b etwe e n t his d ischa rgezo ne an d thesubja ce nt p-type subst rate , a stron gly  d ope dn-typ e  burie d l aye r is pr ovidedb elo wt h e  z one between the ep it a x ia l layerand th e  s ub s trate, s cr een ingo f f the  sub s tr ate from  the e p it ax ial lay er  local ly .
T hezonef ormi ng a d ischarge  form inority charge carriers in t h is k no w n tr ans istor is pr ovid e d in  the cu rre n t pat h bet we e ns ource and drain and  a ccordi nglyinfluences va rious elec t r i cal prop erti e so f the transist or to  a non-neg l igible d egree , for ex ample its r esistanc e,whi chisu n de sirable froma view po int ofdes ign tec hno log y.Inad dition, t he const ru ct io nofthe t r ansistor  r equ ir esthe a v ailabi lityof a nep i tax ial lay e rb e caus eof  the  pr es enceof a bur ied lay er, which  me a ns t ha tit is n ot or hardlypo ssible topr ovi de the s emicondu ctor layer, for example ,  in the  fo rm of  animplanted  la yer.
T hei nventi on has  forit s o b j ect i n t er  al ia  to provid e a s emico nd ucto r devic e of the kind desc r ibe d in the open ing  par a g ra phi nw hic ht het r ansistor is pro vided with  a ch arge remov a l f ac ility f or mino rityc arriers  which is  not situ at ed i n the  current p ath betw een sourc e  andd ra in. T heinvent io n f urthe r hasf orits o bjectto  provi de atr ansistor  with a construction wh ich al lowsofa higherfle x ibi lity in t he m anufacturi ngpro cesstha n  does  the kn own trans isto r .
Accordi n gtot h einvention,a s emi condu cto r  devic e of  the kind mention e d in the openi ng p a r agr aph is f or  this purposecha ra c t erized i nthat the ch annel re gi o n com prises  two o r mores u b- r egions  whi chare mutua lly  s e parated  b ys aid su rfac ezone o f thef irst c onductivity type , whi c h  surf a cezoneex tends f r om t he surface  transverse ly acr ossthe t hicknes sof the  la ye r of the s e cond cond uctiv ity typ eup t o t he sub stra t e  of t he f ir stconductiv i t yt yp e. The  cur rentpa th b etween so u rce anddra i n in th is  de v i ce doe s  n o t  run below  th e rem o v al facilit y  for mi n ority  charg e carr iers, b u t i ns tead ne xtt o  this zon e or betw e entw o zo nes in t he  cas eofse veral discharge  zones d istribut e d  overthe widt h  of th echannel, sothatth e  resist a n ceof thec han nel  is  sub sta ntia l ly defined by the channe l wi dth.S inc e the  remo va l zone f o r mi nority c h arge carriers  is connected t o  th e  sub str a te  o f the sam e
 the_case of_an n-channel transistor), which_form an_inversion_layer below_the_gate and screen_off the latter_from the channel, so_that it is_no_longer possible inter alia to bring the transistor into the pinch state. To prevent_an_inversion occurring_below_the_gate, the patent document U.S._Pat. No. 4,868,620 proposes the_provision of_a discharge for minority charge carriers in the_form_of a p-type_surface zone. A suitable low voltage is applied to_this zone via an electrical connection_such that holes_are_removed_across the blocked pn_junction. To prevent punch-through between this_discharge zone and the subjacent p-type_substrate, a strongly doped n-type buried layer_is provided below the zone between_the epitaxial layer and the_substrate, screening_off the substrate from the_epitaxial layer locally.
The_zone forming_a discharge for_minority charge carriers in this known_transistor is provided_in the current path between source_and_drain and accordingly_influences_various_electrical properties_of the transistor_to_a non-negligible_degree,_for example its resistance, which is_undesirable_from a viewpoint of design technology. In_addition, the construction of_the_transistor requires the availability_of an epitaxial layer because_of the presence of a buried_layer, which_means that_it is not or hardly possible to provide the semiconductor layer,_for example, in the form of_an implanted layer.
The invention_has for_its_object inter alia_to_provide a_semiconductor device of the kind described in_the opening_paragraph in which the transistor is_provided with a charge_removal_facility for minority carriers which is_not situated in the current path_between source and drain. The_invention_further_has for its object to_provide a transistor with a construction_which allows of_a higher flexibility in the manufacturing process_than_does the known transistor.
According to the_invention,_a semiconductor device of the kind_mentioned_in_the opening paragraph is for_this purpose characterized in that the_channel region comprises two or more sub-regions which are_mutually separated by_said surface zone of the_first_conductivity_type, which surface zone extends from the surface transversely across_the thickness_of the layer_of the second conductivity type up to the substrate of_the first conductivity type. The current path_between source and drain in this device does not run below_the removal facility for minority charge carriers, but_instead next to this zone or between_two zones in the_case_of several discharge zones distributed over the_width_of_the_channel, so that_the resistance of_the channel is_substantially defined_by the channel_width. Since_the removal zone_for_minority charge carriers is connected to the substrate of the same