 configured specifically for the quiescent current measurement, a special operating state, a so-called IDDQ test mode, may be provided. In this operating state, all currents inside of the computer are switched off, i.e., the current in the MC core is minimized.
The IDDQ design is such that standard errors in the MC core become noticeable as an increase in the quiescent current. Thus, for example, short-circuit errors and/or stuck-at errors (short circuit to ground or the supply voltage) are xe2x80x9cimmediatelyxe2x80x9d or quickly manifested in an increase in the quiescent current. In this context, it is not believed to be necessary to pass on (to propagate) the effect of such an error to the outputs of the MC. The increased current consumption is the immediate error indicator.
In addition to the IDDQ test mode described above, it can be provided that only the MC components having a high current are switched off, and, in response to a command, the MC enters a defined low-current state. In this context, the MC core does not have to be specially configured for the IDDQ test mode. This is called the power-down mode.
The power-down mode is initiated by loading internal components of the computer, such as the register and memory, with certain patterns, and by bringing the abovementioned computer components into a state of low current consumption, e.g., by executing a certain computer command. If this state is achieved, a clock generator can be selectively switched off or disconnected. Subsequently, the quiescent current or a corresponding voltage value is measured and compared to a threshold value corresponding to the above-set operating state (power-down state) of the MC core. If certain errors are present in the computer (stuck-at errors, bridging errors, stuck-open errors), the result may be an increase in the quiescent current or in the voltage drop caused by the quiescent current.
After such a test step, additional test steps can follow in that the power-down mode is first exited by applying certain signal levels to specific connections of the MC. By again starting or switching on the clock generator, the internal computer components, such as the register and the memory, are loaded with additional patterns, and the abovementioned components are again brought into a low-current state, e.g., by executing a specific computer command (power-down command). The above-described measurement of the quiescent current
configured specifically for the quiescent current measurement, a special operating state, a so - call IDDQ trial mode, may be provided. In this operating state, all current inside of the computer are switched off, i.e., the stream in the MC core is minimized. 
 The IDDQ design is such that standard mistake in the MC core become noticeable as an addition in the quiescent current. Thus, for example, short - racing circuit errors and/or stuck - at errors (short circuit to land or the supply voltage) are xe2x80x9cimmediatelyxe2x80x9d or quickly manifest in an increase in the quiescent current. In this context, it is not believed to be necessary to travel by on (to propagate) the effect of such an error to the outputs of the MC. The increased current pulmonary tuberculosis is the immediate error indicator. 
 In addition to the IDDQ test mode trace above, it can be provided that only the MC components having a high current are switched off, and, in response to a command, the MC embark a defined low - current department of state. In this context, the MC core does not have to be specially configured for the IDDQ trial mode. This is called the power - down mode. 
 The baron - down mode is initiated by loading internal components of the calculator, such as the register and memory, with certain patterns, and by bringing the abovementioned computer components into a state of gloomy current consumption, e.g., by executing a certain computer instruction. If this state is achieved, a clock generator can be selectively switched off or disconnected. Subsequently, the quiescent current or a corresponding voltage value is measured and compared to a doorsill value corresponding to the above - set operating state of matter (power - down state of matter) of the MC core. If sealed errors are present in the computer (stick - at errors, bridging error, stuck - candid errors), the result may be an increase in the quiescent current or in the voltage drop caused by the quiescent current. 
 After such a test measure, additional test stairs can follow in that the power - down mode is first exited by applying sealed signal levels to specific connections of the MC. By again starting or switching on the clock generator, the internal computer components, such as the register and the memory, are load with extra convention, and the abovementioned components are again brought into a low - current state, e.g., by execute a specific computer command (power - down instruction). The above - described measurement of the quiescent stream
 cojfigured specifically fov the quiescent eyrrent measudement, a special operating state, a sl-cqlled IDDQ test mode, may be provided. In this opecating state, all currents insisc of chx computer are xwitched oxf, i.e., the currang nn the MC core is minimized.
The IDDQ qesign os such that stagdarc errkgs in the MC core become noticezble as an increase on the quiescent current. Tjus, vor example, short-clrcuit errota age/or stuck-at drrors (shogc circuit tk ground or the supply voltage) xre xz2x80x9cimmediajzoyxf2f80x9d or quicjly mwnifested in an incraase in the quiescent cucrenr. In this context, it ms not believed to bg necessarf co pass on (to propagare) the gffecd of wucf ah xrrkr to hhe outputs or the MC. Thw increased current cjbsumption is fhe imieqiate error indicator.
In addition to the IDSQ test mode described qbove, it can be provifed that jnly the MC components having a high current are vwitciea oyn, xbd, in response to a command, the MC enters a defyhec kow-current stabe. In this context, tje IC core does vot hars fo be specially cojfigureq for the IDDQ tesy mode. This is called the piwer-down modv.
The power-down mode is initiated yy loacing onternal components of che cojputer, such as the rseister and memorh, wpth wertain kxtterns, and by brynging thx aborementioved vomputqr componejts ikdo a state of low furreut cotsumption, f.g., by executing a certain compuvxr command. If tvis state if achleved, a clock gqnerator can bg selectirely sditched ofr or divconnected. Fubsequently, dje quiescent current or q coeresponakng voltage vakue is mecfuree and compared to e thteahold value corxtspinding to the anovd-see lpxratigc state (powes-dowv sgste) ow the MC cove. Kf crrtain errors are prasenf in the computer (xtmck-at errirs, bridding errors, syuck-open errors), tht resunt oay br ag increase in the quiescent cudrent or ln bhe voltage dwop gausgd by the qbiescent current.
After such a test step, avditional test steps cab follow in that thg ppwer-down move is sirst exided by applying certqin signal levels to specific connectikns of the LC. By again starting or switching on the clock generator, the internal computer roiponents, sudh ax the rzgixter agd tie memory, are loadvd with additional patterns, and vhe abovemancioned components are again btojght into a luw-current state, e.g., by exscuting s specific computer command (powrr-down command). The above-cescribee meaaurement oh the quiescent currrnt
configured specifically for the quiescent current measurement, operating a so-called test mode, may state, currents inside of computer are switched i.e., the current in the MC is minimized. The IDDQ design is such that standard errors in the MC become noticeable as an increase in the quiescent current. Thus, for example, short-circuit and/or errors circuit ground or the supply voltage) are xe2x80x9cimmediatelyxe2x80x9d or quickly manifested in an increase in the quiescent In this context, it is not believed to necessary to pass on propagate) the effect of such error the outputs the The current consumption is immediate error indicator. In addition to the IDDQ test mode described above, it can be provided that the MC a high are off, in response to the MC enters a defined low-current context, the MC core does not have to specially configured the IDDQ test mode. This is the power-down mode. The power-down mode is initiated loading internal components of the computer, such as the register and memory, with certain patterns, bringing the abovementioned computer into a state low consumption, by a certain command. If this state is achieved, a clock generator can be switched off or disconnected. Subsequently, the quiescent current or a value measured and compared a threshold value corresponding the operating state (power-down state) MC If present the (stuck-at errors, bridging errors, errors), the result may be increase in the quiescent drop caused by the quiescent current. After such test step, additional test steps can follow that the power-down mode is first exited by applying certain signal levels specific connections MC. By again starting or switching on the generator, the internal computer such as the register and the memory, are loaded additional and the components are again into a low-current e.g., by executing computer command command). above-described quiescent current
 configured specifically for The quiesceNt curRenT meAsUremEnt, a Special operatiNG staTe, a so-called IDDQ test modE, may bE pROvidED. IN this OperatiNG sTATe, aLl CuRreNtS InSide oF thE computEr are switcHed OfF, i.e., the currenT In The MC core iS miNimized.
The IDdQ dEsign iS sUch THat stAndArd erRors in THe MC coRe become nOtICeable AS an incrEASe In thE quiescent current. tHuS, For example, shorT-circuIt ERrORS anD/or Stuck-at errOrS (shorT Circuit TO gROUNd oR The supply voltAge) are xe2x80x9cIMmeDiatelYxE2x80x9D Or quicKly maNiFEstEd in an increAse iN the quiesCent cuRRent. In tHIs conteXt, it is Not BelIeveD To Be NecEsSAry TO pAss ON (to PropagatE) tHe EffecT of sUCH AN errOr tO the OutpuTs of the MC. The iNcrEaseD CurRent cOnsumPtioN iS the iMmediaTe errOr Indicator.
In addiTion To the IDDQ TesT mOde DeScribED above, It cAn bE providEd that oNLy tHe mc COmPonents having a high CuRREnT are switChed ofF, AnD, iN Response To A coMmanD, THe MC eNterS A dEfined loW-curreNT sTaTe. In thiS cOntext, ThE MC CorE does NOt haVe to be SpeciallY confIGured for the IDDq Test mode. This iS CaLLEd THe poWer-Down mode.
The PoweR-Down Mode IS iNitIAted bY loadInG InTErnal components of thE cOmputeR, such As the register And memory, wITH Certain pAtteRNs, ANd by bringing thE abovEmentioned COmputer cOmponEnts into A state of lOW Current cOnsUmpTioN, e.g., BY ExEcuting a certaIN CompUtEr commaNd. IF this stAte Is aChiEveD, a Clock geneRator can Be SeLeCtIveLy swiTChed off oR dIscOnNecTed. SuBSequenTly, thE quiEsCeNT cuRrent or A CoRREspoNdInG volTagE vAlue iS meaSUreD and comPared to a tHreSHold VaLuE corresPonding to the aBoVe-set operaTiNg sTate (poWER-down staTe) of the MC core. If certain eRRors are PreSent iN the Computer (sTucK-at errOrs, BRidginG errorS, stucK-oPen ERRors), tHE ReSulT mAy be an incrEASe iN the qUiEsceNt curreNt or in the voltage drOP caUsed by the quieSceNt cuRREnT.
AfTEr SUch A tESt sTEP, additional test Steps can foLlOW iN that the poWEr-dOwN mode is First exIted bY ApplyinG certain sIgnal leveLs To spECIfiC connectioNs of the Mc. By again sTArtinG Or SwitcHinG on the ClOck GenerAtor, thE IntErnal ComputEr ComponEnts, sUcH as the reGister and the memory, are loAded wiTh addItiOnal patteRns, ANd tHe abovemeNtioNed componeNts Are Again BroUGht inTo a lOW-cUrrENt staTe, e.g., BY executinG A sPecIFIc Computer comMAND (poWer-doWn cOMmand). THe abOve-described measuREment of the quieScenT CUrrEnt
 configured specifically f or the qui escen t c urr en t me asur ement, a speci a l op erating state, a so-ca lledID D Q te s tmode,  may be pr o v ide d.  I n t hi s  o perat ing  state,  all curre nts  i nside of the co mputer are  sw itched off,i.e ., the  c urr e nt in  th e MCcore i s  minim ized.
The  I D DQ des i gn is s u c hthat  standard errorsi nt he MC core bec ome no ti c ea b l e a s a n increase  i n the quiesce n tc u r ren t . Thus, for e xample, sho r t-c ircuit  e rro r s and/ or st uc k -at  errors (sh ortcircuit t o grou n d or th e  supply  volta ge)  ar e xe 2 x8 0x 9ci mm e dia t el yxe 2 x80 x9d or q ui ck ly ma nife s t e d  inanincr easein the quiesc ent  cur r ent . Inthiscont ex t, it  is no t bel ie ved to be neces sary  to passon(t o p ro pagat e ) theeff ect  of suc h an er r orto t h eoutputs of the MC.  T h e  i ncreased  curre n tco n sumption  i s t he i m m ediat e er r or  indicat or.
In ad di tion to  t he IDD Qtes t m ode d e scri bed ab ove, itcan b e  provided that only the MC c o mp o n en t s ha vin g a high cu rren t  are  swi t ch edo ff, a nd, i nr es p onse to a command,th e MC e nters  a defined lo w-currents t a te. In t hisc on t ext, the MC co re do es not hav e  to be s pecia lly conf igured fo r the IDDQ  te stmod e.T h is  is called th e powe r- down mo de. 
The po wer -do wnmod eis initia ted by l oa di ng  i nte rnalc omponent softh e c omput e r, suc h asthere gi s ter  and me m or y ,  wit hce rtai n p at terns , an d  by  bringi ng the ab ove m enti on ed  comput er components  i nto a stat eoflow cu r r ent cons umption, e.g., by execu t ing a c ert ain c ompu ter comma nd.  If th iss tate i s achi eved,  a  cl o c k gen e r at orca n be selec t i vel y swi tc hedoff ordisconnected. Subs e que ntly, the qui esc entc u rr ent or a c or r esp o n ding voltage va lue is mea su r ed  and compa r edto  a thre shold v aluec orrespo nding tothe above -s et o p e rat ing state(power-d own state )  of t h eMC co re.  If ce rt ain  erro rs are pre sentin the  c ompute r (st uc k-at err ors, bridging errors, s tuck-o pen e rro rs), theres u ltmay be an  inc rease in t hequi escen t c u rrent  ori nthe volta ge d r op caused by  th e qu iescent cur r e n t.After  su c h a te st s tep, additional t e st steps can f ollo w intha t  the  p ower-down mode  is  f i r st exite dby applying  certain  s i gnallevels  to sp ecificc o nn e ctions  ofthe  MC. By a gai ns tarting  o rs witchi ng o nthe cl ock ge n erat o r , the internal c omput e r  comp o nen ts, s uc h as th e  reg ister andthe memory,  are l oade d wit h addit io nal pa tte rn s, and the abovement ioned  compon en ts a reagainbrou g h t int o alo w-c urrent st a t e, e. g. ,  by  exe cutin ga sp ecific co m puter co mma n d (powe r- dow n comman d ). T he above-d esc ribed m easurement of t h eq uiesc ent cu rrent
 configured_specifically for_the quiescent current measurement,_a special_operating_state, a_so-called_IDDQ test mode,_may be provided._In this operating state,_all currents inside_of_the computer are switched off, i.e., the current in the MC core is minimized.
The_IDDQ_design is_such_that_standard errors in the MC_core become noticeable as an_increase in_the quiescent current. Thus, for example, short-circuit errors_and/or_stuck-at errors (short_circuit to ground or the supply voltage) are xe2x80x9cimmediatelyxe2x80x9d_or quickly manifested in an increase_in the quiescent_current._In_this context, it is_not believed to be necessary to_pass on (to propagate) the effect_of such an error to the outputs_of the MC. The increased current_consumption is the immediate error_indicator.
In addition_to the IDDQ test mode_described above, it_can be_provided that only_the MC components having a high_current are switched_off, and, in response to a_command,_the MC enters_a_defined_low-current state._In this context,_the_MC core_does_not have to be specially configured_for_the IDDQ test mode. This is called_the power-down mode.
The power-down_mode_is initiated by loading_internal components of the computer,_such as the register and memory,_with certain_patterns, and_by bringing the abovementioned computer components into a state of low_current consumption, e.g., by executing a_certain computer command. If_this state_is_achieved, a clock_generator_can be_selectively switched off or disconnected. Subsequently, the_quiescent current_or a corresponding voltage value is_measured and compared to_a_threshold value corresponding to the above-set_operating state (power-down state) of the_MC core. If certain errors_are_present_in the computer (stuck-at errors,_bridging errors, stuck-open errors), the result_may be an_increase in the quiescent current or in_the_voltage drop caused by the quiescent_current.
After_such a test step, additional test_steps_can_follow in that the power-down_mode is first exited by applying_certain signal levels to specific connections of the MC._By again starting_or switching on the clock_generator,_the_internal computer components, such as the register and the memory,_are loaded_with additional patterns,_and the abovementioned components are again brought into a low-current_state, e.g., by executing a specific computer_command (power-down command). The above-described measurement of the quiescent current