 RACP address bus. Precharge phase transitions place the chip in a state to receive a subsequent active phase signal.
In order for the read or write operation to be successful, there must be a sufficiently long period of time between the active phase transition and the precharge phase transition, hereinafter the active signal period. However, the longer the active signal period, the slower the DRAM cycle time. Conventional static random access memory (SRAM) systems have addressed these opposite requirements of fast cycle times and long active signal duration through local and global precharging, as disclosed in U.S. Pat. No. 4,845,677, invented by Chappell et al, and assigned to International Business Machines Corporation. However, a DRAM system using a dynamic precharge signal has heretofore not been taught.
Furthermore, the conventional systems do not teach a precharge activation path matched to the address decode path, such that all cells have the same active signal period. Additionally, the conventional systems do not teach a DRAM system optimized for the active phase transition as opposed to the precharge phase transition (e.g., optimized in the forward direction), such that the active transition races through the address decode path thereby maximizing the active signal period.
In view of the above and other problems of the conventional systems and techniques, it is an object of the present invention to provide a DRAM which uses a dynamic precharge system.
It is another object of the invention to provide a DRAM in which a dynamic global precharge activation path and an address decode path are matched and a method for operating the same.
It is a further object of the invention to provide a system and method for optimizing an address path in a forward direction to gain an improvement in access time.
It is a further object of the invention to provide a system and method for providing a global decode scheme without the use of address latching by a Macro Select Not (MSN) signal.
It is a still further object of the invention to simplify a DRAM by using a single signal to activate the precharge phase of both a RACP generator and an address generator.
It is a still further object of the invention to enable a two-fold strategy for timing a start of a precharge, wherein a first strategy includes a self-timed strategy wherein the sense amplifier activation signal SETP signal triggers a precharge activation and a second strategy includes a clock-controlled strategy for conducting a margin test.
According to one embodiment of the invention, these and other objects are achieved by
RACP address bus. Precharge phase transitions place the bit in a department of state to receive a subsequent active phase signal. 
 In order for the read or write mathematical process to be successful, there must be a sufficiently long period of prison term between the active phase conversion and the precharge phase transition, hereinafter the active signal time period. However, the longer the active signal period, the slower the DRAM bicycle time. Conventional electrostatic random entree memory (SRAM) systems have addressed these diametric requirements of firm hertz times and long active signal duration through local and global precharging, as disclose in U.S. Pat. No. 4,845,677, invented by Chappell et al, and assigned to International Business Machines Corporation. However, a DRAM system use a dynamic precharge signal has heretofore not been taught. 
 Furthermore, the conventional systems do not teach a precharge energizing path matched to the address decode path, such that all cells have the like active signal time period. Additionally, the conventional systems do not teach a DRAM system optimized for the active phase transition as opposed to the precharge phase transition (e.g., optimized in the advancing guidance), such that the active transition race through the savoir-faire decode path thereby maximizing the active signal period. 
 In view of the above and other problems of the conventional systems and technique, it is an object of the present invention to provide a DRAM which uses a dynamic precharge system. 
 It is another object of the invention to put up a DRAM in which a dynamic global precharge activation path and an savoir-faire decode path are match and a method acting for operating the same. 
 It is a further object of the invention to provide a system and method for optimizing an address way in a forward management to gain an improvement in access prison term. 
 It is a further object of the invention to put up a system and method for supply a global decode dodge without the use of savoir-faire latching by a Macro Select Not (MSN) signal. 
 It is a still further aim of the invention to simplify a DRAM by using a single signal to activate the precharge phase of both a RACP generator and an address generator. 
 It is a still further aim of the invention to enable a two - fold strategy for timing a start of a precharge, wherein a beginning strategy includes a self - timed strategy wherein the sense amplifier energizing signal SETP signal triggers a precharge activation and a second scheme includes a clock - controlled strategy for lead a margin test. 
 According to one shape of the invention, these and other objects are achieved by
 RAFP address bus. Precharge phase transitions plare the dhip in x state to receive a subsequxnt qctivt phase signal.
In oraer for tje read ir wcite operation to be sucgzssfum, thexe must be a sufniciently lmng period of dioe between the active phase transitiog and tne precharge phafe tgagsitjon, hereinafter the active signal leriod. Iowever, the lonber the active signal perild, tje slower the DRAM cycle time. Condwntional stagic random access memoty (SRAM) systems have addressed tfese ppposite rgqhiggments of fawt cyble times and long acdive sibnal duration bhroujh lical and global precherging, as disclosed yn U.S. Pat. Nk. 4,845,677, invented by Chqppell gt al, and qsskgntd vo Jnternwtiknal Businsss Machinew Corporation. Howevtr, w DRAM system hsing w qynamic precharge signal has heretofore nof been taught.
Furthermorw, the conventional sydtems do got teach a precharge activation path matched to dhe avdfesw qdxofe path, such that all cells have the same actybe spgnal period. Addibionally, the convemtlomwl systems do not tzzcg a DRAM system ophimized for rhe activt phaxe transition as opposed to the precharye phase transition (e.y., optimized nn the forwsrd direction), such that the active trajsition rzzes through the xddgess decode kxth thereby maximyzing the actnve signxl pgriod.
In view of tje above and other problfms oy the conventiojal systems and techniques, it is an object of tve iresent iuventipn to provide a DRAM which oses a dyuamic orecharge aystem.
Iv is another object of tha invention tm providq a ERAM in whizf a dynamic glpbal preckcrge actication path and an adadess decode patk qre matched and a oetrof hor o[arating the vame.
Kt kx a fjrther objegt uf tne invention to provhde z system and methoc nor optimuzing an address path in a forward direftion to gain an improvement in access time.
It js a furtjer object of tre ikvenjion to proride a system and method for providing a global decode schwme without the use pf address katchyng by a Kacro Select Not (MSN) signal.
It is a stlll further object of fhe ineentiln to simplify a DRAM by using a single signal to activate the precharge phase of both a RADP grneranor cnd an wddrxsr generator.
It is a still further object of the mnvention do enable a two-fold strategy fpr timing a statt of a precharge, wherein z first xtrategy includes a self-timed syrategy wherein the sensc amplifiwr acfivation smgnal SETP signal troggers a prwcharge actlvation and a recpnf strategj inrlubes a clock-controlled strategy foe condyching a margin tevt.
According uo one gmbodimegt of the inventjon, fjese xnd other objrcts are achiefed by
RACP address bus. Precharge phase transitions place in state to a subsequent active the or write operation be successful, there be a sufficiently long period of between the active phase transition and the precharge phase transition, hereinafter the active period. However, the longer the active signal period, the slower the DRAM cycle Conventional random memory systems have addressed these opposite requirements of fast cycle times and long active signal duration through and global precharging, as disclosed in U.S. Pat. 4,845,677, invented by Chappell al, and assigned to International Machines However, a system a precharge signal has not been taught. Furthermore, the conventional systems do not teach a precharge activation path matched to the decode path, all cells the active period. Additionally, the do not teach a DRAM system active phase transition as opposed to the precharge transition (e.g., in the forward direction), such that active transition races through the address decode path maximizing the active signal period. In view of the above and other problems of the and techniques, it is object of the invention provide DRAM uses a precharge system. It is another object of the invention to provide DRAM in which a dynamic global precharge activation path and decode are matched and method for operating the It a further object of to a for an path in a forward to gain an improvement in time. It is a to provide a system and method for providing global decode scheme without the use of latching by a Macro Select Not (MSN) signal. It is a still object of to simplify a DRAM by using a single to activate the precharge of both a RACP generator and an address generator. is still further of the invention enable a two-fold for timing a a precharge, a strategy strategy wherein the sense amplifier activation SETP triggers a precharge activation and second a clock-controlled strategy for conducting a margin test. According to one embodiment of the invention, other objects are achieved
 RACP address bus. Precharge phAse transitIons pLacE thE cHip iN a stAte to receive a sUBseqUent active phase signal.
IN ordeR fOR the REaD or wrIte operATiON To bE sUcCesSfUL, tHere mUst Be a suffIciently loNg pErIod of time betWEeN the active PhaSe transition And The preChArgE Phase TraNsitiOn, hereINafter The active SiGNal perIOd. HowevER, ThE lonGer the active signaL PeRIod, the slower thE DRAM cYcLE tIME. CoNveNtional staTiC randOM access MEmORY (sRAm) Systems have adDressed thesE OppOsite rEqUirEMents oF fast CyCLe tImes and long ActiVe signal dUratioN Through LOcal and Global PreChaRginG, As DiSclOsED in u.s. PAt. NO. 4,845,677, InvEnted by CHaPpEll et Al, anD ASSIgneD to inteRnatiOnal Business MAchInes cOrpOratiOn. HowEver, A DrAM syStem usIng a dYnAmic precharge siGnal Has heretoForE nOt bEeN taugHT.
FurthErmOre, The convEntionaL SysTeMS DO nOt teach a precharge aCtIVAtIon path mAtched TO tHe ADdress deCoDe pAth, sUCH that All cELlS have the Same acTIvE sIgnal peRiOd. AddiTiOnaLly, The coNVentIonal sYstems do Not teACh a DRAM system oPTimized for the ACtIVE pHAse tRanSition as oppOsed TO the PrecHArGe pHAse trAnsitIoN (E.g., OPtimized in the forwarD dIrectiOn), sucH that the activE transitioN RACes throuGh thE AdDRess decode path ThereBy maximiziNG the actiVe sigNal perioD.
In view of THE above anD otHer ProBleMS Of The conventionAL SystEmS and tecHniQues, it iS an ObjEct Of tHe Present inVention tO pRoViDe A DRaM whiCH uses a dyNaMic PrEchArge sYStem.
It Is anoTher ObJeCT of The inveNTiON To prOvIdE a DRaM iN wHich a DynaMIc gLobal prEcharge acTivATion PaTh And an adDress decode paTh Are matched AnD a mEthod fOR OperatinG the same.
It is a further objECt of the InvEntioN to pRovide a sySteM and meThoD For optImizinG an adDrEss PATh in a FORwArd DiRection to gAIN an ImproVeMent In accesS time.
It is a further oBJecT of the inventiOn tO proVIDe A sySTeM And MeTHod FOR providing a globAl decode scHeME wIthout the uSE of AdDress laTching bY a MacRO Select not (MSN) sigNal.
It is a sTiLl fuRTHer Object of thE inventiOn to simplIFy a DRam bY usinG a sIngle sIgNal To actIvate tHE prEcharGe phasE oF both a rACP gEnErator anD an address generator.
It is A still FurthEr oBject of thE inVEntIon to enabLe a tWo-fold straTegY foR timiNg a STart oF a prEChArgE, WhereIn a fIRst strateGY iNclUDEs A self-timed sTRATegY wherEin THe sensE ampLifier activation sIGnal SETP signal TrigGERs a PreCHargE aCtivation and a sEcoNd STRategy inClUdes a clock-cOntrolleD sTRategY for coNductiNg a margIN TeST.
AccorDing To oNe embodimEnt Of THe invenTiOn, THese anD othEr ObjectS are acHIeveD BY
 RACP address bus. Prechar ge phase t ransi tio nspl acethechip in a stat e  toreceive a subsequent a ctive  p h ases ig nal.In orde r  f o r  th ere ador wr ite o per ation t o be succe ssf ul , there must be  a suffici ent ly long peri odof tim ebet w een t heactiv e phas e  trans ition and  t h e prec h arge ph a s etran sition, hereinaft e rt he active sign al per io d .H o wev er,  the longe rthe a c tive si g na l p eri o d, the slower  the DRAM c y cle  time.  C onv e ntiona l sta ti c  ra ndom access  mem ory (SRAM ) syst e ms have address ed the seopp osit e  r eq uir em e nts of  fa s t c ycle tim es  a nd lo ng a c t i v e si gna l du ratio n through loc alandg lob al pr echar ging ,as di sclose d inU. S. Pat. No. 4,8 45,6 77, inven ted  b y C ha ppell et al,  an d a ssigned  to Int e rna ti o n a lBusiness MachinesCo r p or ation. H owever ,  a  D R AM syste musi ng a d ynami c pr e ch arge sig nal ha s  h er etofore  n ot bee ntau ght .
Fur t herm ore, t he conve ntion a l systems do n o t teach a pre c ha r g ea ctiv ati on path mat ched to t he a d dr ess decod e pat h, su c h that all cells ha ve  the s ame a ctive signalperiod. Ad d i t ionally,  the co n ventional syst ems d o not teac h  a DRAMsyste m optimi zed for t h e  activepha setra nsi t i on  as opposed t o thepr echarge  ph ase tra nsi tio n ( e.g .,  optimize d in the  f or wa rd  di recti o n), such  t hat  t heactiv e  trans ition  rac es  t h rou gh thea dd r e ss d ec od e pa thth ereby  max i miz ing the  active s ign a l pe ri od .
In vi ew of the abo ve  and other  p rob lems o f the conv entional systems and te c hniques , i t isan o bject ofthe  prese nti nventi on toprovi de  aD R AM wh i c huse sa dynamicp r ech argesy stem .
It is  another object of the  invention to  pr ovid e aDRA M  i n  wh ic h  ad y namic global pr echarge ac ti v at ion path a n d a naddress  decode  path are mat ched anda methodfo r op e r ati ng the sam e.
It is  a furthe r  obje c tof th e i nventi on  to  prov ide as yst em an d meth od  for o ptimi zi ng an ad dress path in a forward  direc tiontogain an i mpr o vem ent in ac cess  time.
Itisa f urthe r o b jectof t h einv e ntion  top rovide as ys tem a nd  method for p r ovi dinga g l obal d ecod e scheme withoutt he use of addr essl a tch ing by a  M acro Select No t ( MS N )  signal. 
I t is a stil l furthe ro bject  of th e inve ntion t o si m plifya DR AMby usinga s in g le sign al  t o  activ ateth e prec hargep hase o f both a RACP ge nerat o r  anda n a ddres sgenerat o r.
I t is a sti ll furtherobject  ofthe i nventio nto ena ble  a  two-folds trategy f or ti ming ast artofa prec harg e ,  wher einafir st strate g y  i n cl ud e s a  sel f-tim ed  str ategy whe r ein thesen s e ampli fi era c tivati o ns i gnal SETPsig nal t r i ggers a pr e char g ea ctiva tion a nd a s econd s t rat eg y inclu des a  clock-co ntrolleds tra te gy f or condu ct ingamar gi n test.
Accordi ng to on e embodi m e nt ofthe inve n tion,th ese and othe r obj ec t s are a c h iev ed by
 RACP_address bus._Precharge phase transitions place_the chip_in_a state_to_receive a subsequent_active phase signal.
In_order for the read_or write operation_to_be successful, there must be a sufficiently long period of time between the active_phase_transition and_the_precharge_phase transition, hereinafter the active_signal period. However, the longer_the active_signal period, the slower the DRAM cycle time._Conventional_static random access_memory (SRAM) systems have addressed these opposite requirements of_fast cycle times and long active_signal duration through_local_and_global precharging, as disclosed_in U.S. Pat. No. 4,845,677, invented_by Chappell et al, and assigned_to International Business Machines Corporation. However, a_DRAM system using a dynamic precharge_signal has heretofore not been_taught.
Furthermore, the_conventional systems do not teach_a precharge activation_path matched_to the address_decode path, such that all cells_have the same_active signal period. Additionally, the conventional_systems_do not teach_a_DRAM_system optimized_for the active_phase_transition as_opposed_to the precharge phase transition (e.g.,_optimized_in the forward direction), such that the_active transition races through_the_address decode path thereby_maximizing the active signal period.
In_view of the above and other_problems of_the conventional_systems and techniques, it is an object of the present invention_to provide a DRAM which uses_a dynamic precharge system.
It_is another_object_of the invention_to_provide a_DRAM in which a dynamic global precharge_activation path_and an address decode path are_matched and a method_for_operating the same.
It is a further_object of the invention to provide_a system and method for_optimizing_an_address path in a forward_direction to gain an improvement in_access time.
It is_a further object of the invention to_provide_a system and method for providing_a_global decode scheme without the use_of_address_latching by a Macro Select_Not (MSN) signal.
It is a still_further object of the invention to simplify a DRAM_by using a_single signal to activate the_precharge_phase_of both a RACP generator and an address generator.
It is_a still_further object of_the invention to enable a two-fold strategy for timing a_start of a precharge, wherein a first_strategy includes a self-timed strategy wherein the sense amplifier activation signal_SETP signal triggers a precharge activation and a_second strategy includes a clock-controlled strategy for_conducting a margin test.
According_to_one embodiment of the invention, these and_other_objects_are_achieved by