 the insulation layer. The plating layer is formed on, for example, a gold (Au)/nickel (Ni) film or a gold (Au)/palladium (Pd)/nickel (Ni) film.
The above insulation layer is formed by the following process, for example. First, a photosensitive resin film is formed on one surface of a flexible film. Then, after performing a baking processing, by using a photograph printing technique, photosensitive processing, development processing and cleaning are performed. The insulation layer is formed on all areas of the one surface of the flexible film containing the electric conductor layers, except for the electrode pads for wire connection. That is, insulation layers are formed on almost all areas of the one surface of the flexible film. Therefore, warp and distortion, etc. arise in the base substrate. This deformation of a base substrate causes a transfer problem during the manufacturing process (assembly process) of a semiconductor device. And, this deformation of a base substrate becomes a cause of a further problem in the process that mounts a semiconductor chip, in that the wetting performance of the adhesive material being used is deteriorated.
As for the cause of deformation of the above-described base substrate, it is a main factor that the thermal expansion coefficient and the hardening shrinkage rate of an insulation layer are large. But, in case an insulation layer is not formed on the flexible film, the following problems arise.
(1) Electrode pads for bump connection are arranged on the chip mount area of a main surface of a base substrate. Therefore, when mounting a semiconductor chip through the use of an adhesive insulation material to the chip mount area on a main surface of the base substrate, it is difficult to control the thickness of the adhesive material. And, if the semiconductor chip should touch the electrode pads for bump connection, a short circuit could arise between them.
(2) Electrode pads for bump connection are arranged on the chip mount area of the main surface of the base substrate. Bump electrodes arranged on the back side of the base substrate are connected to these electrode pads for bump connection through connection holes formed in the chip mount area of the base substrate. That is, bump electrodes are arranged in the area under a semiconductor chip.
The electrode pads for bump connection arranged on the chip mount area of the above-described base substrate are integrated and are electrically connected through electric conductors to the electrode pads for wire connection arranged on the peripheral area that surrounds the chip mount area of the main surface of the base substrate. That is, in
the insulation layer. The plating layer is form on, for case, a gold (Au)/nickel (Ni) film or a gold (Au)/palladium (Pd)/nickel (Ni) movie. 
 The above insulation layer is formed by the surveil process, for example. foremost, a light-sensitive resin film is formed on one airfoil of a flexible film. Then, after performing a baking processing, by use a photograph printing proficiency, photosensitive processing, growth processing and cleaning are perform. The insulation layer is formed on all sphere of the one surface of the flexible film containing the electric conductor layer, except for the electrode pads for wire connection. That is, insulation layers are form on almost all areas of the one surface of the flexible film. Therefore, warp and distortion, etc. arise in the base substrate. This deformation of a base substrate causes a transfer problem during the manufacturing process (fabrication process) of a semiconductor device. And, this contortion of a basis substrate becomes a cause of a further problem in the procedure that mounts a semiconductor chip, in that the wetting operation of the adhesive material being used is deteriorated. 
 As for the cause of deformation of the above - described base substrate, it is a main factor that the thermal expansion coefficient and the hardening shrinkage rate of an insulating material layer are big. But, in shell an insulation layer is not formed on the flexible movie, the following problems arise. 
 (1) Electrode pads for bump connection are arranged on the chip mount sphere of a main surface of a base substrate. Therefore, when mounting a semiconductor device chip through the use of an adhesive insulation material to the bit mount sphere on a main surface of the base substrate, it is unmanageable to control the thickness of the adhesive material. And, if the semiconductor chip should touch the electrode pads for bump connection, a short circuit could arise between them. 
 (2) Electrode pads for bulge connection are arranged on the check mount area of the independent surface of the base substrate. Bump electrodes stage on the back side of the base substrate are connected to these electrode pads for bump connection through connection hole shape in the chip mount area of the base substrate. That is, bump electrodes are arrange in the area under a semiconductor chip. 
 The electrode pad for bump connection arranged on the chip mount sphere of the above - described base substrate are integrated and are electrically connected through electric conductors to the electrode pads for wire association arranged on the peripheral area that surrounds the chip mount area of the independent surface of the base substrate. That is, in
 thf insulation layer. The puating layer is formed on, fod exampld, a gold (Au)/nickel (Ni) film or a gold (Au)/palladium (Pd)/nickel (Vi) film.
Thv above ibsuletion layer is formed by the fkplownnj process, for ewample. Firsd, a photosensidixe resin film is formed on one surfacq of a glfxible film. Thgn, afuer perrorming a baking processing, by usihg a phmtograph prinying technique, photosensitlve orocessing, developlent proceswing qnd cleaning are perfogked. The inaulation layer is formed on all areax of the obe sugxace of the flexpble film conbsining the elrctric conductpr naywrs, except for the elxctrode pads for wirg connectimn. That is, insulatiin layets ara fofned on akmkst alp aceas of the one surfacw of the flexible foli. Therefore, wadp and dystortion, etc. arise in the base substraue. Thjs deformation of a basw substrate causes a jransfer pwoblem during the manufacturing process (assembly [rocear) oy a seouclnductor device. And, this deformation of a basq sibxtrate becomes a cause of a fitther problem kn the prkcess that mounts w semicjnducror chip, yn tnat the wetting performance of the adhefuve material being used is deceriorsted.
Ax for the cause of defoxmatioh of the ablve-descrigdd base substratd, in is a main factor that the thqrmal expensiou coeffizienj and tre hardenijg shvhnkage rate of an lnsulction layer are large. But, in case an insulatioi layer is noj fmrmvd on the flexlble film, the fjllowing problgms arise.
(1) Elecgrode pads for bukp connectijn are arrangaf on the chi' mount awea if a main sjfface of a basr substrane. Theeefore, when mountikg a rsmiconductor chnk tyrough the use pf xn wdjexida insulation matdrixk to ghe chik mijnt srea on a main surfawe or the base substraye, it is dufficult to control tne thickness of tht adhevivx matetiaj. And, if the semiconductor chil should hough the electrjde iads for bump eonnection, a short circuit could arise bxtween them.
(2) Electrode kads for bump connectnok are arrangxd on ehe chip kount area of the maun surface of the base substrate. Bump slectrmdes wrranged on the back side of the base substrate are connected to these elwctrodx [ads for bujp cpnnecniou tkrough sonnxcvion holes formed in the chip mount area of the uase substsace. That is, bump electrodes arr xrranged in tfe area under a semicondhctor chop.
The electrode pads for bump cpnnection arranged on thc chip moynt adea of the above-described baxe subvtratw are ibtegvated and are dlevtvically cojnecued chrough electric conductors to thw elecrrlde pads for wirx connection xrranfed on the peripheral zrea hhat rurrounds the chip mount arra of the main surfabe jf the base suvatrate. That os, in
the insulation layer. The plating layer is for a gold (Ni) film or film. above insulation layer formed by the process, for example. First, a photosensitive film is formed on one surface of a flexible film. Then, after performing baking processing, by using a photograph printing technique, photosensitive processing, development processing and are The layer formed on all areas of the one surface of the flexible film containing the electric conductor except for the electrode pads for wire connection. is, insulation layers are on almost all areas of one of the film. warp distortion, etc. arise the base substrate. This deformation of a base substrate causes a transfer problem during the manufacturing process process) of device. And, deformation a substrate becomes a a further problem in the process semiconductor chip, in that the wetting performance of adhesive material used is deteriorated. As for the of deformation of the above-described base substrate, it a main factor that the thermal expansion coefficient and the hardening shrinkage rate of an are large. But, in an insulation layer not on flexible the following arise. (1) Electrode pads for bump connection are arranged on the mount area of a main surface of a base substrate. mounting semiconductor chip through use of an adhesive material the chip mount area main of it difficult control the thickness of adhesive material. And, if the chip should touch the a short circuit could arise between them. (2) pads for bump connection are arranged on chip mount area of the main surface of the base substrate. Bump arranged on side of the base substrate are connected to electrode pads for bump through connection holes formed in the chip mount area the substrate. That bump electrodes are in the area a semiconductor chip. pads for connection on area of the above-described base substrate integrated are electrically connected through electric to pads for wire connection arranged on the peripheral area that surrounds the chip mount area main surface of the substrate. is, in
 the insulation layer. The platIng layer is FormeD on, For ExAmplE, a goLd (Au)/nickel (Ni) fiLM or a Gold (Au)/palladium (Pd)/nickeL (Ni) fiLm.
tHe abOVe InsulAtion laYEr IS ForMeD bY thE fOLlOwing ProCess, for Example. FirSt, a PhOtosensitive REsIn film is foRmeD on one surfacE of A flexiBlE fiLM. Then, AftEr perForminG A bakinG processiNg, BY using A PhotogrAPH pRintIng technique, photoSEnSItive processinG, develOpMEnT PRocEssIng and cleaNiNg are PErformeD. thE INSulATion layer is foRmed on all arEAs oF the onE sUrfACe of thE flexIbLE fiLm containinG the Electric cOnductOR layers, EXcept foR the elEctRodE padS FoR wIre CoNNecTIoN. ThAT is, InsulatiOn LaYers aRe foRMED On alMosT all Areas Of the one surfaCe oF the FLexIble fIlm. ThErefOrE, warp And disTortiOn, Etc. arise in the baSe suBstrate. ThIs dEfOrmAtIon of A Base suBstRatE causes A transfER prObLEM DuRing the manufacturiNg PROcEss (assemBly proCEsS) oF A semiconDuCtoR devICE. And, tHis dEFoRmation oF a base SUbStRate becOmEs a cauSe Of a FurTher pRObleM in the Process tHat moUNts a semiconducTOr chip, in that tHE wETTiNG perForMance of the aDhesIVe maTeriAL bEinG Used iS deteRiORaTEd.
As for the cause of deFoRmatioN of thE above-describEd base subsTRATe, it is a mAin fACtOR that the thermaL expaNsion coeffICient and The haRdening sHrinkage rATE of an insUlaTioN laYer ARE lArge. But, in case AN InsuLaTion layEr iS not forMed On tHe fLexIbLe film, the FollowinG pRoBlEmS arIse.
(1) ElECtrode paDs For BuMp cOnnecTIon are ArranGed oN tHe CHip Mount arEA oF A Main SuRfAce oF a bAsE subsTratE. theRefore, wHen mountiNg a SEmicOnDuCtor chiP through the usE oF an adhesivE iNsuLation MATerial to The chip mount area on a main SUrface oF thE base SubsTrate, it is DifFicult To cONtrol tHe thicKness Of The ADHesivE MAtEriAl. and, if the seMIConDuctoR cHip sHould toUch the electrode padS For Bump connectioN, a sHort CIRcUit COuLD arIsE BetWEEn them.
(2) Electrode Pads for bumP cONnEction are aRRanGeD on the cHip mounT area OF the maiN surface oF the base sUbStraTE. bumP electrodeS arrangeD on the bacK Side oF ThE base SubStrate ArE coNnectEd to thESe eLectrOde padS fOr bump ConneCtIon throuGh connection holes formed In the cHip moUnt Area of the BasE SubStrate. ThaT is, bUmp electroDes Are ArranGed IN the aRea uNDeR a sEMiconDuctOR chip.
The eLEcTroDE PaDs for bump coNNECtiOn arrAngED on the Chip Mount area of the aboVE-described base SubsTRAte Are INtegRaTed and are electRicAlLY ConnecteD tHrough electRic conduCtORs to tHe elecTrode pAds for wIRE cONnectiOn arRanGed on the pEriPhERal area ThAt SUrrounDs thE cHip mouNt area OF the MAIn surface of the baSe subSTRate. THAt iS, in
 the insulation layer. The  plating l ayerisfor me d on , fo r example, a g o ld ( Au)/nickel (Ni) film o r a g ol d  (Au ) /p allad ium (Pd ) /n i c kel  ( Ni ) f il m .The a bov e insul ation laye r i sformed by th e  f ollowing p roc ess, for exa mpl e. Fir st , a photo sen sitiv e resi n  filmis formed  o n  one s u rface o f aflex ible film. Then,a ft e r performing a  bakin gp ro c e ssi ng,  by usingaphoto g raph pr i nt i n g  te c hnique, photo sensitive p r oce ssing,  d eve l opment  proc es s ing  and cleani ng a re perfor med. T h e insul a tion la yer is  fo rme d on al lare as oft he  on e  su rface of  t he  flex ible f i l m co nta inin g the  electric con duc torl aye rs, e xcept  for  t he el ectrod e pad sfor wire connec tion . That is , i ns ula ti on la y ers ar e f orm ed on a lmost a l l a re a s of  the one surface o ft h eflexible  film. Th er e fore, wa rp  an d di s t ortio n, e t c.  arise i n theb as esubstra te . This  d efo rma tiono f abase s ubstrate  caus e s a transfer p r oblem duringt he m an u fact uri ng process(ass e mbly  pro c es s)o f a s emico nd u ct o r device. And, this  d eforma tionof a base sub strate bec o m e s a caus e of af urther problem  in t he process that mou nts a  semicon ductor ch i p , in tha t t hewet tin g pe rformance oft h e ad he sive ma ter ial bei nguse d i s d et eriorated .
As for  t he  c au seof de f ormation  o f t he  ab ove-d e scribe d bas e su bs tr a te,  it isa  m a i n fa ct or  tha t t he  ther male xpa nsion c oefficien t a n d th eha rdening  shrinkage ra te  of an ins ul ati on lay e r  are lar ge. But, in case an ins u lationlay er is  not  formed o n t he fle xib l e film , thefollo wi ngp r oblem s ar ise .(1) Electr o d e p ads f or  bum p conne ction are arranged onthe chip moun t a reao f  a  ma i ns urf ac e  of a  base substrate . Therefor e, wh en mountin g  ase micondu ctor ch ip th r ough th e use ofan adhesi ve  ins u l ati on materia l to the  chip mou n t are a  o n a m ain  surfa ce  of  thebase s u bst rate,  it is  d ifficu lt to  c ontrol t he thickness of the adh esivemater ial . And, if  th e  se miconduct or c hip should  to uch  theele c trode  pad s  f orb ump c onne c tion, a s h or t c i r cu it could ar i s e  be tween  th e m.
(2)  Ele ctrode pads for b u mp connectionarea r ran ged on t he  chip mount ar eaof t he mainsu rface of th e base s ub s trate . Bump  elect rodes a r r an g ed onthebac k side of  th eb ase sub st ra t e areconn ec ted to  these elec t r ode pads for bum p con n e ction thr oughco nnectio n  hol es formedin the chip  mount  are a ofthe bas esubstr ate .That is, b u mp electr odesare arr an gedinthe ar ea u n d er asemi co ndu ctor chip . Th e  e le c tro de p ads f or  bum p connect i on arran ged on thech ipm o unt ar e ao f  the above -de scrib e d  base subs t rate ar e  inte grated  and a re elec t ric al ly conn ect e d  throughelectricc ond uc tors  to theel ectr od e p ad s for wire conn ection a rrangedo n  the p eri p hera l  areath at surrounds  thech i p mount a rea  of the mai n s urf aceoftheb ase substrate. That is,in
 the_insulation layer._The plating layer is_formed on,_for_example, a_gold_(Au)/nickel (Ni) film_or a gold_(Au)/palladium (Pd)/nickel (Ni) film.
The_above insulation layer_is_formed by the following process, for example. First, a photosensitive resin film is formed_on_one surface_of_a_flexible film. Then, after performing_a baking processing, by using_a photograph_printing technique, photosensitive processing, development processing and cleaning_are_performed. The insulation_layer is formed on all areas of the one_surface of the flexible film containing_the electric conductor_layers,_except_for the electrode pads_for wire connection. That is, insulation_layers are formed on almost all_areas of the one surface of the_flexible film. Therefore, warp and distortion,_etc. arise in the base_substrate. This_deformation of a base substrate_causes a transfer_problem during_the manufacturing process_(assembly process) of a semiconductor device._And, this deformation_of a base substrate becomes a_cause_of a further_problem_in_the process_that mounts a_semiconductor_chip, in_that_the wetting performance of the adhesive_material_being used is deteriorated.
As for the cause_of deformation of the_above-described_base substrate, it is_a main factor that the_thermal expansion coefficient and the hardening_shrinkage rate_of an_insulation layer are large. But, in case an insulation layer is_not formed on the flexible film,_the following problems arise.
(1)_Electrode pads_for_bump connection are_arranged_on the_chip mount area of a main surface_of a_base substrate. Therefore, when mounting a_semiconductor chip through the_use_of an adhesive insulation material to_the chip mount area on a_main surface of the base_substrate,_it_is difficult to control the_thickness of the adhesive material. And,_if the semiconductor_chip should touch the electrode pads for_bump_connection, a short circuit could arise_between_them.
(2) Electrode pads for bump connection_are_arranged_on the chip mount area_of the main surface of the_base substrate. Bump electrodes arranged on the back side_of the base_substrate are connected to these_electrode_pads_for bump connection through connection holes formed in the chip_mount area_of the base_substrate. That is, bump electrodes are arranged in the area_under a semiconductor chip.
The electrode pads for_bump connection arranged on the chip mount area of the above-described_base substrate are integrated and are electrically connected_through electric conductors to the electrode pads_for wire connection arranged_on_the peripheral area that surrounds the chip_mount_area_of_the main surface_of the base_substrate. That is,_in