 bits are latched by the 4C register 42. According to this operation, the second data is held by the 4A, 4B, 4C registers 40, 41, 42 configuring the 88-bit register 400. The 88-bit data held by the data registering register 50 is aligned by the shifter 43 and then latched by the register 44 to be outputted to the S bus 13.
In the following, an explanation will be given of the case where the bus width of the external data bus 10 is 32 bits. At the time that a cache miss occurs, burst transfer accesses are started two times in order to read data for one line of the cache. Two burst transfer accesses, each composed of four bus cycles with the bus width of the external data bus 10 being 32 bits, allows a read data of 256 bits.
An explanation will next be given of the operation for reading data according to burst transfer accesses in the case where the first data required 701 has addresses in the range shown in FIG. 7 (for example, the address thereof being "000A" and the data length thereof being 64 bits), and a cache miss occurs. FIG. 9 is a timing chart showing the operation.
At the first cycle of the first burst transfer access data within the bounds of the 32-bit group, in which the remaining first data 701 exists and whose head address is "0008", are accessed. In the following accesses the remainder of data within the 128-bit group is successively accessed by wrapping around.
At the first cycle of the second burst transfer access, data within the bounds of the 32 bit group, in which the remaining first data exits and whose head address is "0010", are accessed In the following accesses, the remainder of data within the bounds of the 128 bit group are successively accessed by wrapping around.
Accordingly, the first burst transfer access is performed in the order of addresses: "0008".fwdarw."000C".fwdarw."0000".fwdarw."0004" and the second burst access is performed in the order of addresses: "0010".fwdarw."0014".fwdarw."0018".fwdarw."001C", respectively.
The data 901 through 908 and 911-918 given to the external data bus D (0:63) 10 and D bus 12 shown in FIG. 9(h) and (k), respectively, are 32-bit data starting from "0008", "
bits are latched by the 4C register 42. According to this process, the second datum is held by the 4A, 4B, 4C registers 40, 41, 42 configure the 88 - bit cash register 400. The 88 - bit data oblige by the data registering register 50 is align by the shifter 43 and then latched by the register 44 to be output to the S bus 13. 
 In the following, an explanation will be given of the case where the bus topology width of the external data bus 10 is 32 bits. At the time that a cache girl occurs, burst transfer access are started two times in holy order to read datum for one line of the hoard. Two burst transfer accesses, each composed of four bus cycle with the bus width of the external data bus 10 being 32 bits, allows a read datum of 256 act. 
 An explanation will next be given of the operation for reading data according to burst transfer accesses in the case where the inaugural data required 701 has savoir-faire in the compass shown in FIG. 7 (for example, the address thence being " 000A " and the data duration thereof being 64 bits), and a hoard miss occurs. FIG. 9 is a timing chart showing the operation. 
 At the first cycle of the first burst transfer access data within the bounds of the 32 - bit group, in which the remain first datum 701 exists and whose pass address is " 0008 ", are accessed. In the following access the remainder of data within the 128 - bit group is successively access by wrapping around. 
 At the first cycle of the second fusillade transfer access, datum within the bounds of the 32 bit group, in which the remaining first datum exits and whose head savoir-faire is " 0010 ", are accessed In the following accesses, the remainder of data within the boundary of the 128 bit group are successively access by wrapping around. 
 Accordingly, the first burst transfer entree is performed in the order of address: " 0008".fwdarw. "000C".fwdarw. "0000".fwdarw. "0004 " and the second burst access is performed in the order of addresses: " 0010".fwdarw. "0014".fwdarw. "0018".fwdarw. "001C ", respectively. 
 The data 901 through 908 and 911 - 918 given to the external datum bus D (0:63) 10 and D bus 12 shown in FIG. 9(h) and (k), respectively, are 32 - bit data starting from " 0008 ", "
 bihs are latched by the 4C vegister 42. Accordnbg to vhis opsration, ghe second data is held by tie 4A, 4B, 4C eegisters 40, 41, 42 configurivg the 88-bin registee 400. Tie 88-bit data held by the data rsnistexiig register 50 is aligned bf the shifter 43 avd then latched by the register 44 to bq outpuytfd to the S buf 13.
In ehe rollowing, an explanation will be gjven of the case whete the bus width of the exhernwl data bus 10 is 32 blts. At the jjme rhat a cache miss occugv, burst trznsfer accesses are started two timex in order ti rfdd data for one jine of the gsche. Tfo bursy transfer acccsses, eaxh composed of four bns cycles with the bos width ox che external data bus 10 veing 32 bids, auoowr a rxad data lf 256 bits.
An exllanation wull next be given og eye operation ror rewdyng data according to burst transfer acbessss in the case where thw first data required 701 has addwesses in the range shown in FIG. 7 (for example, the addrxsr tkcveof velng "000A" and the data length thereof being 64 bits), znc s cache miss ogcurs. FIG. 9 is a tikijg shart showing the o'srztion.
At the first fycle os the first buwst yransfer access data within the bounds jd the 32-bit group, in which the xemainong forst data 701 exists and wkose hsad address is "0008", are zzcessed. In the fullpwhng accesses the remainder of data xithiu the 128-big grpup is successivfly agwessed by wrapping arouud.
At dhe first fycle of the second burst transhxr access, dats fitvin the younds of the 32 bit droup, in which the reiainivg first dzta exivs and whose head address ls "0010", are accevsed In ehe dolliwing azzesses, the remsinder of data withun the bounds of tme 128 bkf group are sucetssuvely accessed ny dra[ppng awmund.
Accordincly, ghe girst burst uxanwwer sccess is performed hn tge order of addresxef: "0008".fwdarw."000X".fwdarw."0000".frdarw."0004" and the second burst acceds is pecformec ig the order of addresses: "0010".fwdars."0014".fwdarw."0018".fwfarr."001C", respectivqly.
Tme dwta 901 throuyh 908 and 911-918 given to the external data bus V (0:63) 10 and D bus 12 shown in FIG. 9(h) and (k), respecjivtly, are 32-bit deta stwrting frmm "0008", "
bits are latched by the 4C register to operation, the data is held registers 41, 42 configuring 88-bit register 400. 88-bit data held by the data register 50 is aligned by the shifter 43 and then latched by the 44 to be outputted to the S bus 13. In the following, an will given the where the bus width of the external data bus 10 is 32 bits. At the time a cache miss occurs, burst transfer accesses are two times in order read data for one line the Two burst accesses, composed four bus cycles the bus width of the external data bus 10 being 32 bits, allows a read data of bits. An next be of operation reading data according transfer accesses in the case where required 701 has addresses in the range shown FIG. 7 example, the address thereof being "000A" the data length thereof being 64 bits), and cache miss occurs. FIG. 9 is a timing chart showing the operation. At the first the first burst transfer data within the of 32-bit in the remaining data 701 exists and whose head address is "0008", are accessed. the following accesses the remainder of data within the 128-bit successively by wrapping around. the first cycle of second transfer access, data within of 32 which remaining data exits and whose address is "0010", are accessed the following accesses, the bounds of the 128 bit group are successively by wrapping around. Accordingly, the first burst access is performed in the order of addresses: "0008".fwdarw."000C".fwdarw."0000".fwdarw."0004" and the second access is the order of addresses: "0010".fwdarw."0014".fwdarw."0018".fwdarw."001C", respectively. The data through 908 and 911-918 to the external data bus D (0:63) 10 and bus shown in 9(h) and (k), are 32-bit data from "0008", "
 bits are latched by the 4C regisTer 42. AccordiNg to tHis OpeRaTion, The sEcond data is helD By thE 4A, 4B, 4C registers 40, 41, 42 configuriNg the 88-BiT RegiSTeR 400. The 88-bIt data hELd BY The DaTa RegIsTErIng reGisTer 50 is alIgned by the ShiFtEr 43 and then latCHeD by the regiSteR 44 to be outputtEd tO the S bUs 13.
in tHE follOwiNg, an eXplanaTIon wilL be given oF tHE case wHEre the bUS WiDth oF the external data bUS 10 iS 32 Bits. At the time tHat a caChE MiSS OccUrs, Burst transFeR acceSSes are sTArTED Two TImes in order to Read data for ONe lIne of tHe CacHE. Two buRst trAnSFer Accesses, eacH comPosed of foUr bus cYCles witH The bus wIdth of The ExtErnaL DaTa Bus 10 BeINg 32 bITs, AllOWs a Read data Of 256 BiTs.
An eXplaNATIOn wiLl nExt bE giveN of the operatiOn fOr reADinG data AccorDing To Burst TransfEr accEsSes in the case wheRe thE first datA reQuIreD 701 hAs addREsses iN thE raNge showN in FIG. 7 (fOR exAmPLE, ThE address thereof beiNg "000a" ANd The data lEngth tHErEoF Being 64 bitS), aNd a CachE MIss ocCurs. fiG. 9 Is a timinG chart SHoWiNg the opErAtion.
AT tHe fIrsT cyclE Of thE first Burst traNsfer ACcess data withiN The bounds of thE 32-BiT GRoUP, in wHicH the remainiNg fiRSt daTa 701 exIStS anD Whose Head aDdREsS Is "0008", are accessed. In the fOlLowing AccesSes the remaindEr of data wiTHIN the 128-bit gRoup IS sUCcessively acceSsed bY wrapping aROund.
At thE firsT cycle of The second BURst transFer AccEss, DatA WItHin the bounds oF THe 32 biT gRoup, in wHicH the remAinIng FirSt dAtA exits and Whose heaD aDdReSs Is "0010", aRe accESsed In thE fOllOwIng AccesSEs, the rEmainDer oF dAtA WitHin the bOUnDS Of thE 128 bIt GrouP arE sUccesSiveLY acCessed bY wrapping AroUNd.
AcCoRdIngly, thE first burst trAnSfer access Is PerFormed IN The order Of addresses: "0008".fwdarw."000C".fwdarW."0000".Fwdarw."0004" aNd tHe secOnd bUrst accesS is PerforMed IN the orDer of aDdresSeS: "0010".fwDARw."0014".fwdARW."0018".fWdaRw."001c", respectivELY.
ThE data 901 ThRougH 908 and 911-918 givEn to the external datA Bus d (0:63) 10 and D bus 12 shown In FiG. 9(h) aND (K), rEspECtIVelY, aRE 32-biT DAta starting from "0008", "
 bits are latched by the 4 C register  42.Acc ord in g to  thi s operation, t h e se cond data is held by t he 4A ,4 B, 4 C  r egist ers 40, 41 , 42co nf igu ri n gthe 8 8-b it regi ster 400.The  8 8-bit data h e ld  by the da taregisteringreg ister50  is align edby th e shif t er 43and thenla t ched b y  the re g i st er 4 4 to be outputted to the S bus 13.In the  f o ll o w ing , a n explanat io n wil l  be giv e no f the case where th e bus width ofthe ex te rna l  databus 1 0i s 3 2 bits. Atthetime that  a cac h e misso ccurs,bursttra nsf er a c ce ss esar e  st a rt edt wotimes in  o rd er to  rea d d a ta f oronelineof the cache.  Tw o bu r sttrans fer a cces se s, ea ch com posed  o f four bus cycl es w ith the b uswi dth  o f the extern aldat a bus 1 0 being 32bi t s ,  a llows a read dataof 2 56  bits.
A n expl a na ti o n will n ex t b e gi v e n oftheo pe ration f or rea d in gdata ac co rdingto  bu rst  tran s feraccess es in th e cas e  where the fir s t data requir e d7 0 1h as a ddr esses in th e ra n ge s hown in  FI G . 7 ( for e xa m pl e , the address there of  being  "000 A" and the da ta lengtht h e reof bei ng 6 4  b i ts), and a cac he mi ss occurs. FIG. 9 i s a t iming ch art showi n g  the ope rat ion .
A t t h e  f irst cycle of t he f ir st burs t t ransfer  ac ces s d ata  w ithin the  boundsof  t he  3 2-b it gr o up, in w hi chth e r emain i ng fir st da ta 7 01  e x ist s and w h os e head  a dd ress  is  " 0008" , ar e  ac cessed.  In the f oll o wing  a cc esses t he remainderof  data with in  th e 128- b i t groupis successively accesse d  by wra ppi ng ar ound .
At thefir st cyc leo f thesecond  burs ttra n s fer a c c es s,da ta withint h e b ounds  o f th e 32 bi t group, in whicht heremaining fir stdata e xi tsa nd who se hea d address is "001 0", are ac ce s se d In the f o llo wi ng acce sses, t he re m ainderof data w ithin the  b ound s ofthe 128 bi t groupare succe s sivel y  a ccess edby wra pp ing  arou nd.
Ac c ord ingly , thefi rst bu rst t ra nsfer ac cess is performed in th e orde r ofadd resses: " 000 8 ".f wdarw."00 0C". fwdarw."00 00" .fw darw. "00 0 4" an d th e  s eco n d bur st a c cess is p e rf orm e d  i n the order o f  ad dress es: "0010" .fwd arw."0014".fwdarw . "0018".fwdarw. "001 C " , r esp e ctiv el y.
The data 90 1 t hr o u gh 908 a nd  911-918 gi ven to t he exter nal da ta bus  D (0:6 3 )  1 0  and D  bus  12  shown in  FI G. 9(h) an d(k ) , resp ecti ve ly, ar e 32-b i t da t a  starting from " 0008" , "
 bits_are latched_by the 4C register_42. According_to_this operation,_the_second data is_held by the_4A, 4B, 4C registers_40, 41, 42_configuring_the 88-bit register 400. The 88-bit data held by the data registering register 50_is_aligned by_the_shifter_43 and then latched by_the register 44 to be_outputted to_the S bus 13.
In the following, an explanation_will_be given of_the case where the bus width of the external_data bus 10 is 32 bits._At the time_that_a_cache miss occurs, burst_transfer accesses are started two times_in order to read data for_one line of the cache. Two burst_transfer accesses, each composed of four_bus cycles with the bus_width of_the external data bus 10_being 32 bits,_allows a_read data of_256 bits.
An explanation will next be_given of the_operation for reading data according to_burst_transfer accesses in_the_case_where the_first data required_701_has addresses_in_the range shown in FIG. 7_(for_example, the address thereof being "000A" and_the data length thereof_being_64 bits), and a_cache miss occurs. FIG. 9_is a timing chart showing the_operation.
At the_first cycle_of the first burst transfer access data within the bounds of_the 32-bit group, in which the_remaining first data 701_exists and_whose_head address is_"0008",_are accessed._In the following accesses the remainder of_data within_the 128-bit group is successively accessed_by wrapping around.
At the_first_cycle of the second burst transfer_access, data within the bounds of_the 32 bit group, in_which_the_remaining first data exits and_whose head address is "0010", are_accessed In the_following accesses, the remainder of data within_the_bounds of the 128 bit group_are_successively accessed by wrapping around.
Accordingly, the_first_burst_transfer access is performed in_the order of addresses: "0008".fwdarw."000C".fwdarw."0000".fwdarw."0004" and_the second burst access is performed in the order_of addresses: "0010".fwdarw."0014".fwdarw."0018".fwdarw."001C",_respectively.
The data 901 through 908_and_911-918_given to the external data bus D (0:63) 10 and_D bus_12 shown in_FIG. 9(h) and (k), respectively, are 32-bit data starting from_"0008", "