 the timing analysis for circuit 50. Instead, the effects of the netlist inside model 70 are incorporated in the model for subcircuit 55. Thus, the layout parasitics that belong to circuit 50 are analyzed differently than the layout parasitics that belong to model 70, introducing accuracy problems in the timing analysis.
In addition, when a circuit analyzer is applied at the transistor level of a circuit (that is, at the lowest level in the hierarchy of the timing analysis), a higher level of accuracy is desired for the circuit analysis. Therefore, a reduction in accuracy due to the prior art technique for modeling layout parasitics at the interface pins is particularly undesirable at the transistor level.
Accordingly, a need exists to resolve the modeling duality caused by the treatment of layout parasitic data at a lower level versus a higher level of a hierarchical timing analysis. A need also exists for a device or method that can be utilized at the transistor level. The present invention solves these needs. These and other objects and advantages of the present invention will become clear to those of ordinary skill in the art in light of the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
The present invention provides a method of generating timing models that addresses the modeling duality caused by the treatment of layout parasitic data at the lower and higher levels in a hierarchical timing analysis. The present invention also provides a method and timing model that can be utilized at the transistor level.
The present invention pertains to a modeling method to improve the accuracy of a circuit timing analysis that more closely models timing information associated with layout parasitics that are connected to interface nodes of a transistor-level subcircuit. The modeling method is for performing a hierarchical timing analysis of a circuit that can include a transistor-level subcircuit.
In the present embodiment, for the timing analysis, a circuit is separated into a higher level block and a lower level block, where the higher level block and the lower level block are mutually exclusive. Certain data (e.g., the layout parasitic data associated with the interface pins or the xe2x80x9cinterface small nodesxe2x80x9d) of the lower level block are set aside. A timing model (timing arc or timing arcs) for the lower level block is created without using these data; that is, one or more timing arcs are generated without using the layout parasitic data connected to the interface pins or the interface small nodes (collectively, the xe2x80x9cinterface nodesxe2x80x
the timing analysis for circuit 50. Instead, the effects of the netlist inside exemplar 70 are incorporate in the model for subcircuit 55. Thus, the layout parasitics that belong to circumference 50 are analyzed differently than the layout parasitics that belong to mannequin 70, inaugurate accuracy problems in the timing analysis. 
 In addition, when a circuit analyzer is apply at the transistor level of a circuit (that is, at the lowest level in the hierarchy of the timing analysis), a higher degree of accuracy is desired for the circuit analysis. consequently, a reduction in accuracy due to the prior artwork technique for model layout parasitics at the interface pins is peculiarly undesirable at the transistor level. 
 Accordingly, a need exists to conclude the modeling duality caused by the treatment of layout parasitic datum at a broken level versus a higher level of a hierarchical timing analysis. A need also exists for a device or method that can be utilized at the transistor degree. The present invention solves these needs. These and early object and advantage of the present invention will become clear to those of ordinary skill in the art in light of the following detailed description of the preferred embodiments which are illustrate in the various drawing figures. 
 The present invention provides a method of generating timing model that addresses the modeling duality caused by the treatment of layout parasitic datum at the humble and higher levels in a hierarchical timing analysis. The present invention besides provides a method and timing model that can be utilized at the transistor level. 
 The present invention pertains to a modeling method to improve the accuracy of a lap timing psychoanalysis that more closely models timing information associated with layout parasitics that are get in touch to interface nodes of a transistor - floor subcircuit. The modeling method acting is for performing a hierarchical timing analysis of a circuit that can admit a transistor - level subcircuit. 
 In the present embodiment, for the timing analysis, a circuit is separated into a higher level block and a lower level block, where the higher degree block and the lower degree block are mutually exclusive. Certain data (e.g., the layout parasitic datum associated with the interface pins or the xe2x80x9cinterface small nodesxe2x80x9d) of the lower level block are set aside. A timing model (time discharge or timing arcs) for the lower level block is created without use these data; that is, one or more timing arcs are generated without use the layout parasitic data connected to the interface pins or the interface small node (collectively, the xe2x80x9cinterface nodesxe2x80x
 thf timing analysis for civcuit 50. Instead, tkw efferts of fhe netlkst inside model 70 are incorplrqted un the model for subcifcuit 55. Thls, the latout parasitics that belong tk cireumt 50 are analyzec differendly than the ldyuuc parasitics that belong to model 70, igtroduconh accuracy proflemx in fhe timing analysis.
In addition, wheh a cirbuit analyzer is spplied at the transistor pevep of a circuit (thah is, at the lowqwt level in ghe hierarbky of the tjming analysis), a higher level ow accbracy is dewieed xor the cirruit agalysis. Thercgore, a reductoon in accuracn due to the prior art technixue for modeling lwyout pardsntics at the interfacw pins hs pdrtizylafly uideairablf av the transjstor level.
Qccordingly, a need txifnx to resolve the mjdqling duality caused by the treatment ox lzyout parasitic data at a lower level versus a higher level of a hierarchical timing analysis. A need anso eeirts fjf a device or method that can be utilized at the frsnxistor level. Tme present inventipn spjves these negds. These znd other objects wnd advwntagws of the prexent invention will become xlear to thofw of ordinary skilp in the arc in loght pf the following detailzd desdription of the prefsfred embodiments whpch dre illustrated in the varyous drawmng fngures.
Thd prgsent igvention pgovidcv a method of genegatiny timhng models that addresses the modeling duekity caused ny thv treatmeut of kayout parasieic data at thg lower aud higfer levels in a hmerarchical eiming analyshd. The presenv inventijn aoso provider a method and yiming mobtl that cab be utilized at tme trxhsistor level.
Thz krwsent inventiom pdrtwijs tj a modeling kethud gp impfove tht agcufacy of a circuit timing anamysis that more clpscly modelw timing information sssociated with lajout 'arasivics tnat are connected to interface noses of a hraksistor-level fubclrcuyt. The modzling method is for performing a hierarciical timing analysis od a circuit that cau lnclude a trensistjr-level sgbcircuit.
In the preswnt embodiment, fov the timing analysis, z circgit id separated into a higher level block and a lower level block, where the hugher level block znd yhe lmwzr kevel flocn are mutually exblusive. Certain data (e.g., the layont parasithc data associated with the inyefface pins or the xe2x80x9cinterface smalm nodesxr2x80x9d) of the lower level block ate set aside. A timing mocel (timibg ard or tpjiig arcs) for the lowet leven bloxk is ceeatcd without usivg yhcse data; tjat ms, kne or more timing arcs are geneeated qihhout using the nayout paradltic dzta cognected to the ihterrwce pkns or the inyerface small modes (collectively, tve xe2x80x9cinterfact nodesxe2x80x
the timing analysis for circuit 50. Instead, of netlist inside 70 are incorporated 55. the layout parasitics belong to circuit are analyzed differently than the layout that belong to model 70, introducing accuracy problems in the timing analysis. In when a circuit analyzer is applied at the transistor level of a circuit is, the level the hierarchy of the timing analysis), a higher level of accuracy is desired for the circuit Therefore, a reduction in accuracy due to the art technique for modeling parasitics at the interface pins particularly at the level. a exists to resolve modeling duality caused by the treatment of layout parasitic data at a lower level versus a higher of a analysis. A also for device or method be utilized at the transistor level. solves these needs. These and other objects and of the invention will become clear to those ordinary skill in the art in light of following detailed description of the preferred embodiments which are illustrated in the various drawing figures. invention provides a method generating timing models addresses modeling caused the treatment layout parasitic data at the lower and higher levels in a timing analysis. The present invention also provides a method and that be utilized at transistor level. The present pertains a modeling method to accuracy a that closely timing information associated with parasitics that are connected to nodes of a transistor-level for performing a hierarchical timing analysis of a that can include a transistor-level subcircuit. In present embodiment, for the timing analysis, a circuit is separated into a level block lower level block, where the higher level block the lower level block mutually exclusive. Certain data (e.g., the layout parasitic data with interface pins the xe2x80x9cinterface small of the lower block are set timing model arc timing lower level block is created without these that is, one or more arcs without using the layout parasitic data connected to the interface pins or the interface small the xe2x80x9cinterface nodesxe2x80x
 the timing analysis for circuIt 50. Instead, tHe effEctS of ThE netList Inside model 70 are INcorPorated in the model for suBcircUiT 55. thus, THe LayouT parasiTIcS THat BeLoNg tO cIRcUit 50 arE anAlyzed dIfferently ThaN tHe layout paraSItIcs that belOng To model 70, introDucIng accUrAcy PRobleMs iN the tIming aNAlysis.
in additioN, wHEn a cirCUit analYZEr Is apPlied at the transisTOr LEvel of a circuit (That is, At THe LOWesT leVel in the hiErArchy OF the timINg ANALysIS), a higher level Of accuracy iS DesIred foR tHe cIRcuit aNalysIs. tHerEfore, a reducTion In accuracY due to THe prior ARt technIque foR moDelIng lAYoUt ParAsITicS At The INteRface pinS iS pArticUlarLY UNDesiRabLe at The trAnsistor level.
accOrdiNGly, A need ExistS to rEsOlve tHe modeLing dUaLity caused by the TreaTment of laYouT pAraSiTic daTA at a loWer LevEl versuS a higheR LevEl OF A HiErarchical timing anAlYSIs. a need alsO existS FoR a DEvice or mEtHod That CAN be utIlizED aT the tranSistor LEvEl. the presEnT invenTiOn sOlvEs theSE neeDs. ThesE and otheR objeCTs and advantageS Of the present iNVeNTIoN Will BecOme clear to tHose OF ordInarY SkIll IN the aRt in lIgHT oF The following detaileD dEscripTion oF the preferred EmbodimentS WHIch are ilLustRAtED in the various dRawinG figures.
ThE Present iNventIon proviDes a methoD OF generatIng TimIng ModELS tHat addresses tHE ModeLiNg dualiTy cAused by The TreAtmEnt Of Layout parAsitic daTa At ThE lOweR and hIGher leveLs In a HiEraRchicAL timinG analYsis. thE pREseNt invenTIoN ALso pRoViDes a MetHoD and tIminG ModEl that cAn be utiliZed AT the TrAnSistor lEvel.
The presenT iNvention peRtAinS to a moDELing methOd to improve the accuracy oF A circuiT tiMing aNalySis that moRe cLosely ModELs timiNg infoRmatiOn AssOCIated WITh LayOuT parasiticS THat Are coNnEcteD to inteRface nodes of a transIStoR-level subcircUit. the mODElIng MEtHOd iS fOR peRFOrming a hierarchIcal timing AnALySis of a circUIt tHaT can incLude a trAnsisTOr-level SubcircuiT.
In the preSeNt emBODimEnt, for the tIming anaLysis, a cirCUit is SEpArateD inTo a higHeR leVel blOck and A LowEr levEl blocK, wHere thE highEr Level bloCk and the lower level block Are mutUally ExcLusive. CerTaiN DatA (e.g., the layOut pArasitic daTa aSsoCiateD wiTH the iNterFAcE piNS or thE xe2x80X9CinterfacE SmAll NODeSxe2x80x9d) of the LOWEr lEvel bLocK Are set AsidE. A timing model (timiNG arc or timing arCs) foR THe lOweR LeveL bLock is created wIthOuT USing thesE dAta; that is, onE or more tImINg arcS are geNerateD withouT USiNG the laYout ParAsitic datA coNnECted to tHe InTErface Pins Or The intErface SMall NODes (collectively, tHe xe2x80X9CInterFAce NodesXe2X80x
 the timing analysis for c ircuit 50.  Inst ead , t he  eff ects  of the netlis t  ins ide model 70 are incor porat ed in t h emodel  for su b ci r c uit  5 5.  Th us ,  t he la you t paras itics that  be lo ng to circui t  5 0 are anal yze d differentl y t han th elay o ut pa ras itics  thatb elongto model70 ,  intro d ucing a c c ur acyproblems in the t i mi n g analysis.
In  addit io n ,w h ena c ircuit ana ly zer i s  applie d  a t t het ransistor lev el of a cir c uit  (that  i s,a t thelowes tl eve l in the hi erar chy of th e timi n g analy s is), ahigher  le vel  ofa cc ur acy  i s  de s ir edf orthe circ ui tanaly sis. T h e refo re,  a r educt ion in accura cyduet o t he pr ior a rt t ec hniqu e formodel in g layout parasi tics  at the i nte rf ace  p ins i s  parti cul arl y undes irablea t t he t r an sistor level.
Acco rd i n gl y, a nee d exis t sto resolveth e m odel i n g dua lity ca used bythe tr e at me nt of l ay out pa ra sit icdataa t alowerlevel ve rsusa  higher levelo f a hierarchi c al t im i ng a nal ysis. A nee d al s o ex ists fo r a devic e orme t ho d  that can be utiliz ed  at th e tra nsistor level . The pres e n t  inventi on s o lv e s these needs.  Thes e and othe r  objects  andadvantag es of the p resent i nve nti onwil l be come clear to t hose  o f ordin ary  skillinthe  ar t i nlight ofthe foll ow in gde tai led d e scriptio nofth e p refer r ed emb odime ntswh ic h  ar e illus t ra t e d in  t he  var iou sdrawi ng f i gur es.
The  presentinv e ntio npr ovidesa method of g en erating ti mi ngmodels t hat addr esses the modeling dual i ty caus edby th e tr eatment o f l ayoutpar a siticdata a t the  l owe r and h i g he r l ev els in a h i e rar chica ltimi ng anal ysis. The presenti nve ntion also pr ovi desa me tho d  a n d t im i ngm o del that can be  utilizedat th e transist o r l ev el.
The  presen t inv e ntion p ertains t o a model in g me t h odto improve  the acc uracy ofa  circ u it  timi nganalys is  th at mo re clo s ely  mode ls tim in g info rmati on  associa ted with layout parasit ics th at ar e c onnectedtoi nte rface nod es o f a transi sto r-l evelsub c ircui t. T h emod e lingmeth o d is forp er for m i ng  a hierarch i c a l t iming  an a lysisof a  circuit that can include a tran sist o r -le vel subc ir cuit.
In the p res en t embodime nt , for the t iming an al y sis,a circ uit is  separa t e di nto ahigh erlevel blo ckan d  a lowe rle v el blo ck,wh ere th e high e r le v e l block and thelower l evelb loc k are  m utually excl usive. Cer tain data ( e.g.,thelayou t paras it ic dat a a ss ociated wi t h the int erfac e pinsor  the  xe 2x80x9 cint e r facesmal lnod esxe2x80x 9 d )o fth e  lo werlevel  b lock  are seta side. Atim i ng mode l(ti m i ng arc or t iming arcs ) f or th e lower leve l  blo c ki s cre ated w ithout  usingt hes edata; t hat i s, one or  more tim i ngar cs a re gener at ed w it hou tusing the layou t parasi tic data c onnect edt o th e  inter fa ce pins or t he in te r face sm a l l n odes (c o lle cti vel y, t hexe2x 8 0x9cinterface nodesxe2x8 0x
 the_timing analysis_for circuit 50. Instead,_the effects_of_the netlist_inside_model 70 are_incorporated in the_model for subcircuit 55._Thus, the layout_parasitics_that belong to circuit 50 are analyzed differently than the layout parasitics that belong_to_model 70,_introducing_accuracy_problems in the timing analysis.
In_addition, when a circuit analyzer_is applied_at the transistor level of a circuit (that_is,_at the lowest_level in the hierarchy of the timing analysis), a_higher level of accuracy is desired_for the circuit_analysis._Therefore,_a reduction in accuracy_due to the prior art technique_for modeling layout parasitics at the_interface pins is particularly undesirable at the_transistor level.
Accordingly, a need exists to_resolve the modeling duality caused_by the_treatment of layout parasitic data_at a lower_level versus_a higher level_of a hierarchical timing analysis. A_need also exists_for a device or method that_can_be utilized at_the_transistor_level. The_present invention solves_these_needs. These_and_other objects and advantages of the_present_invention will become clear to those of_ordinary skill in the_art_in light of the_following detailed description of the_preferred embodiments which are illustrated in_the various_drawing figures.
The_present invention provides a method of generating timing models that addresses_the modeling duality caused by the_treatment of layout parasitic_data at_the_lower and higher_levels_in a_hierarchical timing analysis. The present invention also_provides a_method and timing model that can_be utilized at the_transistor_level.
The present invention pertains to a_modeling method to improve the accuracy_of a circuit timing analysis_that_more_closely models timing information associated_with layout parasitics that are connected_to interface nodes_of a transistor-level subcircuit. The modeling method_is_for performing a hierarchical timing analysis_of_a circuit that can include a_transistor-level_subcircuit.
In_the present embodiment, for the_timing analysis, a circuit is separated_into a higher level block and a lower level_block, where the_higher level block and the_lower_level_block are mutually exclusive. Certain data (e.g., the layout parasitic_data associated_with the interface_pins or the xe2x80x9cinterface small nodesxe2x80x9d) of the lower level_block are set aside. A timing model_(timing arc or timing arcs) for the lower level block is_created without using these data; that is, one_or more timing arcs are generated without_using the layout parasitic_data_connected to the interface pins or the_interface_small_nodes_(collectively, the xe2x80x9cinterface_nodesxe2x80x