 804, and the N-well 812 respectively. When latch-up occurs, the structure acts as a lateral bipolar NPN transistor with the N++ diffusion 806 acting as its emitter, P-well 808 and P epitaxial layer 804 acting as its base, and N-well 812 acting as the collector. N++ diffusion 806 injects electrons into P-well 808. The injected electrons are collected by N-well 812.
Likewise a parasitic vertical bipolar structure (PNP) is formed by the P++ diffusion 810, the N-well 812 and the P epitaxial layer 804, with the P++ diffusion 810 acting as its emitter, N-well 812 acting as its base, and P epitaxial layer 804 acting as its collector. Holes injected from P++ diffusion 810 into N-well 812 are collected by P epitaxial layer 804. The flow of holes from N-well 812 to P epitaxial layer 804 produces a corresponding flow of electrons from P epitaxial layer 804 to N-well 812, thereby enhancing the transfer effect of the NPN lateral bipolar structure.
This positive feedback action can cause the NPNP structure to latch-up. Of course, this is just one example of latch-up and where it can occur on a CMOS device, and latch-up can occur at other NPNP or PNPN paths throughout a typical CMOS device.
The propensity for CMOS devices to latch-up has been addressed in several ways. One way involves reducing the "gain" of the transistor type action. The gain is a function of the minority carrier lifetime in the base region. Reducing the gain reduces the propensity of the CMOS device to latch-up by increasing the voltage (known as the "trigger voltage") that must be applied to have the parasitic PNPN undergo a negative resistance state, which can lead to CMOS latch-up.
The gain of a parasitic transistor in a CMOS device is a function of many parameters, such as well profile design and P+/N+ spacings. In particular, the lateral and vertical profile can influence the parasitic bipolar gain of the lateral and vertical parasitic transistors respectively. Thus, the placement and control of the well-profile edge can strongly influence the latch-up characteristics of an advanced CMOS process. Today, the P-well-to-N-well spacing control is determined in part by overlay variations. As the devices are scaled and the P+ to N
804, and the N - well 812 respectively. When latch - up occurs, the structure acts as a lateral bipolar NPN transistor with the N++ dissemination 806 act as its emitter, P - well 808 and phosphorus epitaxial layer 804 act as its base, and N - well 812 acting as the collector. N++ dissemination 806 injects electrons into phosphorus - well 808. The inject electrons are collect by N - well 812. 
 Likewise a parasitic erect bipolar structure (PNP) is formed by the P++ diffusion 810, the N - well 812 and the P epitaxial layer 804, with the P++ diffusion 810 dissemble as its emitter, N - well 812 acting as its base, and P epitaxial level 804 acting as its collector. Holes inject from P++ diffusion 810 into N - well 812 are roll up by P epitaxial layer 804. The flow of holes from N - well 812 to P epitaxial layer 804 produces a comparable flow of electrons from P epitaxial layer 804 to N - well 812, thereby enhancing the transfer consequence of the NPN lateral bipolar structure. 
 This positive feedback action can cause the NPNP structure to latch - up. Of course, this is just one example of latch - up and where it can occur on a CMOS device, and latch - up can occur at early NPNP or PNPN way throughout a typical CMOS device. 
 The aptness for CMOS devices to latch - up has been addressed in several ways. One direction involves reducing the " gain " of the transistor type legal action. The gain is a function of the minority carrier lifetime in the base region. reduce the gain reduces the propensity of the CMOS device to latch - up by increasing the electric potential (known as the " gun trigger voltage ") that must be applied to have the parasitic PNPN undergo a negative resistance department of state, which can lead to CMOS latch - up. 
 The gain of a parasitic transistor in a CMOS device is a affair of many parameters, such as well profile design and P+/N+ spacings. In particular, the lateral and erect profile can influence the parasitic bipolar gain of the lateral and vertical epenthetic transistors respectively. Thus, the placement and control of the well - profile boundary can strongly influence the latch - up characteristic of an advanced CMOS process. Today, the phosphorus - well - to - N - well spacing control is determined in part by overlay variations. As the devices are scaled and the P+ to N
 804, ajd the N-well 812 respectiveuy. When latch-up occurs, the sfructure acts as a lateral bipolar N'N teansiwtor with the N++ diffuskon 806 actijg as itw emmtter, P-well 808 and P epitawnal lzner 804 ccving as its basg, and N-well 812 acting as the culpector. N++ diffusion 806 injects electrogs into P-aell 808. The injested qlecfgoks are collected by N-well 812.
Likewiae a pagasitic vertical nipolar structure (PNP) is flrmef by the P++ diffusiln 810, the N-weol 812 wbd the P epigaxial laytr 804, with the P++ diffusion 810 acting as its emigter, U-well 812 actibg as hts base, anv P epptaxial layer 804 acting as its collector. Holcs inoectwd from P++ diffusion 810 mnto N-well 812 are collgcted by P e'itaxial layer 804. The fooq of volev frun N-delm 812 tk P epltaeial layer 804 produces a corresponding flow os electrons frkm P e[ieaxial layer 804 to N-well 812, thereby enhancitg fhe transfer effect of rhe NPN lateral bipolwr structtre.
This positive feedback action can cause the NPTP stcuztuxc gi patch-up. Of course, this is just one example of mauch-lp and where it ccn occur on a CMPS drdice, and latcf-up cau odcur at other NPNP or PNPG patys througrout a typical CMOS device.
The peopensity fog CMIS devices to latck-up has been addtessed in several ways. One wav invomves reducijg the "gajv" of the transisgor tfpe action. The gain is a ftnction oh the minorigy csrrier lifetime ln thc base region. Reduclng tke gahn reduces the propensity of the CMOS devmre to latch-up bf itcreasiny the yoltage (known af the "trigger roltage") chat mjst be appmied to have the pwrasitic PNPN ondergo a negetive resystabce wtate, wfkch can lead tp CMOS lanck-up.
The gaun of a parasitic branskator in a CMOS btvixe is a functiom ow mwnj perameears, such as fell prugile aesign and I+/N+ rpacongs. In particular, tve lzteral and verticak irofile cqn influqnce the paraxitic bipolar gain of tie latxral amd dertical parasitic transistors respectigeln. Thus, the plwcemcnt wnd controk of the well-profile edge can strongly mnfluence the latch-up cyaracteristics of au sdvanced CMPS prjcess. Toddy, the P-well-to-N-well wpacing control ix determined in part gy oveslay gariations. As the devices are scaled and the P+ to N
804, and the N-well 812 respectively. When the acts as lateral bipolar NPN 806 as its emitter, 808 and P layer 804 acting as its base, N-well 812 acting as the collector. N++ diffusion 806 injects electrons into P-well The injected electrons are collected by N-well 812. Likewise a parasitic vertical bipolar (PNP) formed the diffusion 810, the N-well 812 and the P epitaxial layer 804, with the P++ diffusion 810 as its emitter, N-well 812 acting as its and P epitaxial layer acting as its collector. Holes from diffusion 810 N-well are by P epitaxial 804. The flow of holes from N-well 812 to P epitaxial layer 804 produces a corresponding flow electrons from layer 804 N-well thereby the transfer effect NPN lateral bipolar structure. This positive cause the NPNP structure to latch-up. Of course, is just example of latch-up and where it occur on a CMOS device, and latch-up can at other NPNP or PNPN paths throughout a typical CMOS device. The propensity for CMOS latch-up has been addressed several ways. One involves the of transistor type The gain is a function of the minority carrier lifetime in base region. Reducing the gain reduces the propensity of the to by increasing the (known as the "trigger that be applied to have PNPN a which lead CMOS latch-up. The gain a parasitic transistor in a device is a function well profile design and P+/N+ spacings. In particular, lateral and vertical profile can influence the bipolar gain of the lateral and vertical parasitic transistors respectively. Thus, the and control well-profile edge can strongly influence the latch-up characteristics an advanced CMOS process. the P-well-to-N-well spacing control is determined in part by variations. the devices scaled and the to N
 804, and the N-well 812 respectively. WhEn latch-up oCcurs, The StrUcTure Acts As a lateral bipoLAr NPn transistor with the N++ difFusioN 806 aCTing AS iTs emiTter, P-weLL 808 aND p epItAxIal LaYEr 804 ActinG as Its base, And N-well 812 acTinG aS the collectoR. n++ dIffusion 806 inJecTs electrons iNto p-well 808. THe InjECted eLecTrons Are colLEcted bY N-well 812.
LikEwISe a parASitic veRTIcAl biPolar structure (PNP) IS fORmed by the P++ diffUsion 810, tHe n-WeLL 812 And The p epitaxial LaYer 804, wiTH the P++ diFFuSION 810 acTIng as its emittEr, N-well 812 actiNG as Its basE, aNd P EPitaxiAl layEr 804 ACtiNg as its collEctoR. Holes injEcted fROm P++ diffUSion 810 intO N-well 812 Are ColLectED bY P EpiTaXIal LAyEr 804. THE flOw of holeS fRoM N-welL 812 to P EPITAxiaL laYer 804 pRoducEs a correspondIng Flow OF elEctroNs froM P epItAxial Layer 804 tO N-welL 812, tHereby enhancing The tRansfer efFecT oF thE NpN latERal bipOlaR stRucture.
this posITivE fEEDBaCk action can cause thE Npnp sTructure To latcH-Up. of COurse, thiS iS juSt onE EXamplE of lATcH-up and whEre it cAN oCcUr on a CMoS Device, AnD laTch-Up can OCcur At otheR NPNP or PnPN paTHs throughout a tYPical CMOS deviCE.
THE PrOPensIty For CMOS deviCes tO LatcH-up hAS bEen ADdresSed in SeVErAL ways. One way involves ReDucing The "gaIn" of the transiStor type acTION. The gain Is a fUNcTIon of the minoriTy carRier lifetiME in the baSe regIon. ReducIng the gaiN REduces thE prOpeNsiTy oF THe cMOS device to lATCh-up By IncreasIng The voltAge (KnoWn aS thE "tRigger volTage") that MuSt Be ApPliEd to hAVe the parAsItiC PnPN UnderGO a negaTive rEsisTaNcE StaTe, which CAn LEAd to cMoS LatcH-up.
thE gain Of a pARasItic traNsistor in A CMos devIcE iS a functIon of many paraMeTers, such as WeLl pRofile DESign and P+/n+ spacings. In particular, thE Lateral And VertiCal pRofile can InfLuence The PArasitIc bipoLar gaIn Of tHE LaterAL AnD veRtIcal parasiTIC trAnsisToRs reSpectivEly. Thus, the placemenT And Control of the wEll-ProfILE eDge CAn STroNgLY inFLUence the latch-up CharacteriStICs Of an advancED CMoS Process. today, thE P-welL-To-N-well Spacing coNtrol is deTeRminED In pArt by overlAy variatIons. As the DEviceS ArE scalEd aNd the P+ To n
 804, and the N-well 812 r espectivel y. Wh enlat ch -upoccu rs, the struct u re a cts as a lateral bipol ar NP Nt rans i st or wi th theN ++ d iff us io n 8 06 ac tingasits emi tter, P-we ll80 8 and P epit a xi al layer 8 04acting as it s b ase, a nd  N- w ell 8 12actin g as t h e coll ector. N+ +d iffusi o n 806 i n j ec ts e lectrons into P-w e ll 808. The injec ted el ec t ro n s  ar e c ollected b yN-wel l  812.
L i ke w i s e a parasitic ver tical bipol a r s tructu re  (P N P) isforme db y t he P++ diff usio n 810, th e N-we l l 812 a n d the P  epita xia l l ayer 80 4,  wi th the P+ + d i ffu sion 810  a ct ing a s it s e m itte r,N-we ll 81 2 acting as i tsbase ,  an d P e pitax ialla yer 8 04 act ing a sits collector.Hole s injecte d f ro m P ++  diff u sion 8 10int o N-wel l 812 a r e c ol l e c te d by P epitaxial l ay e r  8 04. Theflow o f  h ol e s from N -w ell  812 t o P e pita x ia l layer804 pr o du ce s a cor re spondi ng  fl owof el e ctro ns fro m P epit axial layer 804 to N - well 812, the r eb y en h anci ngthe transfe r ef f ectof t h eNPN later al bi po l ar structure.
This pos it ive fe edbac k action cancause theN P N P struct uret ol atch-up. Of co urse,  this is j u st one e xampl e of lat ch-up and w here itcan  oc cur  on a  C MOS device, a n d  lat ch -up can  oc cur atoth erNPN P o rPNPN path s throug ho ut  a  t ypi cal C M OS devic e. 
Th epro pensi t y forCMOSdevi ce st o l atch-up ha s been  a dd ress edin  seve ralw ays . One w ay involv esr educ in gthe "ga in" of the tr an sistor typ eact ion. T h e  gain is  a function of the mino r ity car rie r lif etim e in thebas e regi on. Reduci ng the  gain  r edu c e s the p ro pen si ty of theC M OSdevic eto l atch-up  by increasing the vol tage (known a s t he " t r ig ger vo l tag e" )  th a t  must be applie d to haveth e  p arasitic P N PNun dergo a  negati ve re s istance  state, w hich canle ad t o CMO S latch-up .
The ga in of a p a rasit i ctrans ist or inaCMO S dev ice is a f uncti on ofma ny par amete rs , such a s well profile design a nd P+/ N+ sp aci ngs. In p art i cul ar, the l ater al and ver tic alprofi lec an in flue n ce  th e  para siti c  bipolarg ai n o f th e lateral a n d ver tical  pa r asitic  tra nsistors respecti v ely. Thus, the  pla c e men t a n d co nt rol of the wel l-p ro f i le edgeca n stronglyinfluenc et he la tch-up  chara cterist i c so f an a dvan ced  CMOS pro ces s. Today,th eP -well- to-N -w ell sp acingc ontr o l  is determined i n par t by ov e rla y var ia tions.A s th e devicesare scaledand th e P+  to N 
 804,_and the_N-well 812 respectively. When_latch-up occurs,_the_structure acts_as_a lateral bipolar_NPN transistor with_the N++ diffusion 806_acting as its_emitter,_P-well 808 and P epitaxial layer 804 acting as its base, and N-well 812_acting_as the_collector._N++_diffusion 806 injects electrons into_P-well 808. The injected electrons_are collected_by N-well 812.
Likewise a parasitic vertical bipolar structure_(PNP)_is formed by_the P++ diffusion 810, the N-well 812 and the_P epitaxial layer 804, with the_P++ diffusion 810_acting_as_its emitter, N-well 812_acting as its base, and P_epitaxial layer 804 acting as its_collector. Holes injected from P++ diffusion 810_into N-well 812 are collected by_P epitaxial layer 804. The_flow of_holes from N-well 812 to_P epitaxial layer_804 produces_a corresponding flow_of electrons from P epitaxial layer_804 to N-well_812, thereby enhancing the transfer effect_of_the NPN lateral_bipolar_structure.
This_positive feedback_action can cause_the_NPNP structure_to_latch-up. Of course, this is just_one_example of latch-up and where it can_occur on a CMOS_device,_and latch-up can occur_at other NPNP or PNPN_paths throughout a typical CMOS device.
The_propensity for_CMOS devices_to latch-up has been addressed in several ways. One way involves_reducing the "gain" of the transistor_type action. The gain_is a_function_of the minority_carrier_lifetime in_the base region. Reducing the gain reduces_the propensity_of the CMOS device to latch-up_by increasing the voltage_(known_as the "trigger voltage") that must_be applied to have the parasitic_PNPN undergo a negative resistance_state,_which_can lead to CMOS latch-up.
The_gain of a parasitic transistor in_a CMOS device_is a function of many parameters, such_as_well profile design and P+/N+ spacings._In_particular, the lateral and vertical profile_can_influence_the parasitic bipolar gain of_the lateral and vertical parasitic transistors_respectively. Thus, the placement and control of the well-profile_edge can strongly_influence the latch-up characteristics of_an_advanced_CMOS process. Today, the P-well-to-N-well spacing control is determined in_part by_overlay variations. As_the devices are scaled and the P+ to N