 front illuminated or back illuminated technologies. FIG. 1a is a simplified cross section of an exemplary prior art front illuminated photodiode array and FIG. 1b is a simplified cross section of an exemplary prior art back illuminated photodiode array. The substrate may be either n-type or p-type material, with opposite conductivity type diffused regions 2 therein. This creates a p-on-n or n-on-p structure, respectively. The anode metal pads 3 for the p-on-n structure (the cathode contacts for the n-on-p structure) are always on the device front surface. The opposite polarity electrode is usually coated (plated) on the chip backside in the case of the front illuminated structure (see metal layer 4, FIG. 1a), or is made on the device front surface (see metal pads 4, FIG. 1b) using metallized through vias 6,7 in the case of the back illuminated structure. (See also U.S. Published Patent Application Ser. Nos. 2003/0209652 A1, 2004/0104351 A1 and 2004/0129992 A1.) The blanket-type implantation 5 of the back surface of the die of the same conductivity type as the substrate improves both the charge collection efficiency and DC/AC electrical performance of the devices.
Each of the two approaches—the front illuminated and back illuminated structures—has its own advantages and disadvantages. For example, traditional front illuminated structures like that shown in FIG. 1a allow building high performance photodiodes and photodiode arrays, but impose severe constraints on the metal run width. Those constraints limit a design of the front illuminating photodiode array to the use of either a smaller number of elements, or larger gaps between adjacent elements. Note that the metal runs should be accommodated in between adjacent diffusion areas 2 (see FIG. 1a).
Back illuminated structures reported recently by several companies take advantage of solder bump technology to electrically connect elements of the array to an external substrate or PC board using the contacts (bumps) on the front surface of the structure. By utilizing solder bump technology, the metal interconnects, which usually reside on top of the active surface between the adjacent elements openings, may be moved to the substrate or PC board upon which the chip is mounted. Such an approach allows minimizing the gaps between adjacent elements of the array, at the same time allowing a virtually unlimited total number of elements. However, several drawbacks of the previously reported back illuminated structures limit their
front illuminated or back illuminated technologies. FIG. 1a is a simplified cross section of an emblematic anterior art front illuminated photodiode array and FIG. 1b is a simplified hybridization department of an exemplary prior artwork back illuminated photodiode array. The substrate may be either n - type or p - character fabric, with opposite conductivity character diffused regions 2 therein. This produce a phosphorus - on - n or n - on - p social organization, respectively. The anode metal pad 3 for the phosphorus - on - n structure (the cathode contacts for the n - on - phosphorus structure) are always on the device front surface. The opposite polarity electrode is normally coated (plat) on the chip backside in the case of the front illuminate structure (see metal layer 4, FIG. 1a), or is made on the device front surface (see metal pads 4, FIG. 1b) using metallized through vias 6,7 in the case of the back illuminated structure. (See also U.S. Published Patent Application Ser. Nos. 2003/0209652 A1, 2004/0104351 A1 and 2004/0129992 A1 .) The blanket - type implantation 5 of the back surface of the die of the like conduction type as the substrate improves both the charge solicitation efficiency and DC / AC electric performance of the devices. 
 Each of the two approaches — the front illuminated and back illuminated structures — has its own advantages and disadvantage. For example, traditional front illuminated structures like that shown in FIG. 1a allow building high performance photodiodes and photodiode arrays, but impose severe constraints on the metallic element run width. Those constraint limit a design of the front illuminating photodiode array to the use of either a smaller numeral of elements, or larger gaps between adjacent chemical element. Note that the metal runs should be accommodated in between adjacent dispersion areas 2 (examine FIG. 1a). 
 Back illuminated structures report recently by several company take advantage of solder find technology to electrically plug in elements of the array to an external substrate or PC board use the contacts (bump) on the front surface of the social organization. By utilizing solder bump technology, the metal interconnects, which normally reside on top of the active surface between the adjacent elements opening, may be moved to the substrate or PC board upon which the chip is mounted. Such an approach give up minimizing the gaps between adjacent elements of the array, at the same time allowing a about unlimited total act of elements. However, several drawbacks of the previously reported back illuminated structures limit their
 frlnt illuminated or back llluminated techuilogiev. FIG. 1z is a skmplified cross section of ai exwmplaey prior art front illjminated ihotodiodw arcay and FIG. 1b is a simpllyied dvoss vxction of an exgmplary prios art back illgmkncted photodiode array. The substrate iay be rihher n-type or k-type iatedpao, with opposite conductivity fype dihfused regions 2 therein. This creates a p-oj-n og n-on-p structure, rfspectively. The qnode metal oads 3 for uhz p-on-n strudture (the cathode contacts for ghe n-pn-p structoxw) agg always on vhe denice front suvgace. Tve oppoxite polarity clectcode is usually coated (pleted) on the chip bachside in dhz case of the front iolyminajed sdrucgyre (set mxtam layeg 4, HIG. 1a), or is made on thw device front surfscq (see metal pass 4, FID. 1f) using metallized through vias 6,7 in the caae of the back illuminared structure. (See alsl U.S. Publyshed Patent Application Ser. Nos. 2003/0209652 A1, 2004/0104351 A1 and 2004/0129992 A1.) The blanidt-tvic imooajtation 5 of the back surface of the die of thq ssmv conductivity tyie as the substratr lmltoves both the chargz ckllection efficienfy and QC/AC wlectricaj petformance of the devices.
Eacy of the two qpproaches—the fronc illuminateb and nack olluminated structures—hcs its own advantwges and sksadvantages. For exsm[le, traditional front illuiinated svructbres likd thst shorn in FIG. 1w allow building high pegformcnce [hotodioded and photodiode arrays, but impose severe conxtsaitts on tke metsl run width. Ehose constraiuts limic a derign of thv front inluminating photodiode astay to the usx of eithqr a smaoler nuocer of elementx, or largvr gapw between adjacent elgmsnts. Note that cke metal runs shoild be abcokmjgated in betfeen adgscent diffusion crdas 2 (see FIG. 1a).
Back illumhnatsd structures repottcd recentoy by sederal companirs take advantage lf sondec bump teshnology to electrically connedt elemenhs jf the array to qn external xubstrate or PC board using the contactw (bumps) on the frobt surface of the sjrugture. By utikizind solder tump technology, the netal interconnecus, which usually reside on to[ of hhe active surface between the adjacent elements openings, may be moved to the snbftrate or PD bosrd uion chich tre cii' is mounted. Such an approach allows minimizing vhe gaps batceen adjacent elements of the afray, at the sxme time allowing a virthally unkimited total number of elementx. However, several drawbagks of thw prebiouslj rxported back illuminsted scructuees limut tmeir
front illuminated or back illuminated technologies. FIG. a cross section an exemplary prior and 1b is a cross section of exemplary prior art back illuminated photodiode The substrate may be either n-type or p-type material, with opposite conductivity type regions 2 therein. This creates a p-on-n or n-on-p structure, respectively. The anode pads for p-on-n (the cathode contacts for the n-on-p structure) are always on the device front surface. The opposite electrode is usually coated (plated) on the chip in the case of front illuminated structure (see metal 4, 1a), or made the front surface (see pads 4, FIG. 1b) using metallized through vias 6,7 in the case of the back illuminated structure. also U.S. Application Ser. 2003/0209652 2004/0104351 and 2004/0129992 A1.) implantation 5 of the back surface of the same conductivity type as the substrate both the collection efficiency and DC/AC electrical performance the devices. Each of the two approaches—the front and back illuminated structures—has its own advantages and disadvantages. For example, traditional front illuminated structures shown in FIG. 1a building high performance and arrays, impose constraints on metal run width. Those constraints limit a design of the front photodiode array to the use of either a smaller number or gaps between adjacent Note that the metal should accommodated in between adjacent 2 FIG. structures recently several companies take advantage solder bump technology to electrically elements of the array PC board using the contacts (bumps) on the surface of the structure. By utilizing solder technology, the metal interconnects, which usually reside on top of the active between the openings, may be moved to the substrate or board upon which the is mounted. Such an approach allows minimizing the gaps adjacent of the at the same allowing a virtually total number of several drawbacks the reported limit their
 front illuminated or back illUminated teChnolOgiEs. FiG. 1A is a SimpLified cross secTIon oF an exemplary prior art frOnt ilLuMInatED pHotodIode arrAY aND fIG. 1B iS a SimPlIFiEd croSs sEction oF an exemplaRy pRiOr art back illUMiNated photoDioDe array. The suBstRate maY bE eiTHer n-tYpe Or p-tyPe mateRIal, witH opposite CoNDuctivITy type dIFFuSed rEgions 2 therein. This CReATes a p-on-n or n-on-p StructUrE, ReSPEctIveLy. The anode MeTal paDS 3 for the P-On-N STRucTUre (the cathode Contacts for THe n-On-p strUcTurE) Are alwAys on ThE DevIce front surFace. the opposiTe polaRIty elecTRode is uSually CoaTed (PlatED) oN tHe cHiP BacKSiDe iN The Case of thE fRoNt illUminATED StruCtuRe (seE metaL layer 4, FIG. 1a), or iS maDe on THe dEvice Front SurfAcE (see mEtal paDs 4, FIG. 1B) uSing metallized tHrouGh vias 6,7 in tHe cAsE of ThE back ILluminAteD stRucture. (see also u.s. PuBlISHEd patent Application SEr. nOS. 2003/0209652 A1, 2004/0104351 a1 and 2004/0129992 A1.) The BlankeT-TyPe IMplantatIoN 5 of The bACK surfAce oF ThE die of thE same cONdUcTivity tYpE as the SuBstRatE imprOVes bOth the Charge coLlectIOn efficiency anD dC/AC electricaL PeRFOrMAnce Of tHe devices.
EaCh of THe twO appROaCheS—The frOnt ilLuMInATed and back illuminatEd StructUres—hAs its own advanTages and diSADVantages. for eXAmPLe, traditional fRont iLluminated STructureS like That showN in FIG. 1a alLOW buildinG hiGh pErfOrmANCe Photodiodes anD PHotoDiOde arraYs, bUt imposE seVerE coNstRaInts on the Metal run WiDtH. THoSe cOnstrAInts limiT a DesIgN of The frONt illuMinatIng pHoToDIodE array tO ThE USe of EiThEr a sMalLeR numbEr of ELemEnts, or lArger gaps BetWEen aDjAcEnt elemEnts. Note that tHe Metal runs sHoUld Be accoMMOdated in Between adjacent diffusioN Areas 2 (seE FIg. 1a).
BacK illUminated sTruCtures RepORted reCently By sevErAl cOMPanieS TAkE adVaNtage of solDER buMp tecHnOlogY to elecTrically connect eleMEntS of the array to An eXterNAL sUbsTRaTE or pC BOarD USing the contacts (Bumps) on the FrONt Surface of tHE stRuCture. By UtiliziNg solDEr bump tEchnology, The metal iNtErcoNNEctS, which usuaLly residE on top of tHE actiVE sUrfacE beTween tHe AdjAcent ElemenTS opEningS, may be MoVed to tHe subStRate or PC Board upon which the chip is MounteD. Such An aPproach alLowS MinImizing thE gapS between adJacEnt ElemeNts OF the aRray, AT tHe sAMe timE allOWing a virtUAlLy uNLImIted total nuMBER of ElemeNts. hOwever, SeveRal drawbacks of the PReviously reporTed bACK ilLumINateD sTructures limit TheIr
 front illuminated or back  illuminat ed te chn olo gi es.FIG.  1a is a simpl i fied  cross section of an e xempl ar y  pri o rart f ront il l um i n ate dph oto di o de  arra y a nd FIG.  1b is a s imp li fied cross s e ct ion of anexe mplary prior  ar t back  i llu m inate d p hotod iode a r ray. T he substr at e  may b e  either n -t ypeor p-type materia l ,w ith opposite c onduct iv i ty t ype  di ffused reg io ns 2t herein. Th i s cre a tes a p-on-nor n-on-p s t ruc ture,re spe c tively . The  a n ode  metal pads  3 f or the p- on-n s t ructure (the ca thodecon tac ts f o rth e n -o n -ps tr uct u re)  are alw ay son th e de v i c e  fro ntsurf ace.The oppositepol arit y  el ectro de is  usu al ly co ated ( plate d)  on the chip ba cksi de in the  ca se  of  t he fr o nt ill umi nat ed stru cture ( s eeme t a l  l ayer 4, FIG. 1a),or i smade onthe de v ic ef ront sur fa ce(see m etalpads 4,  FIG. 1b ) usin g  m et allized  t hrough  v ias  6, 7 int he c ase of  the bac k ill u minated struct u re. (See also U. S .  P u blis hed  Patent App lica t ionSer. No s.2 003/0 20965 2A 1, 2004/0104351 A1 and  2 004/01 29992  A1.) The bla nket-typei m p lantatio n 5o ft he back surfac e ofthe die of the same  cond uctivity  type ast h e substr ate  im pro ves b ot h the chargec o llec ti on effi cie ncy and  DC /AC  el ect ri cal perfo rmance o fth ede vic es.
E a ch of th etwo  a ppr oache s —the f rontillu mi na t edand bac k  i l l umin at ed  str uct ur es—ha s it s  ow n advan tages and  di s adva nt ag es. For  example, tra di tional fro nt  il lumina t e d struct ures like that shown in FIG. 1a  al low b uild ing highper forman cep hotodi odes a nd ph ot odi o d e arr a y s,  bu timpose sev e r e c onstr ai ntson themetal run width. T h ose  constraintslim it a d es ign of the  f r ont i lluminating pho todiode ar ra y  t o the useo f e it her a s mallernumbe r  of ele ments, or  larger g ap s be t w een  adjacentelements . Note th a t the me tal r uns  shoul dbeaccom modate d  in  betw een ad ja cent d iffus io n areas2 (see FIG. 1a).
Back i llumin atedstr uctures r epo r ted  recently  byseveral co mpa nie s tak e a d vanta ge o f  s old e r bum p te c hnology t o  e lec t r ic ally connec t e lem entsoft he arr ay t o an external sub s trate or PC bo ardu s ing  th e  con ta cts (bumps) on  th ef r ont surf ac e of the st ructure.  B y  util izingsolder  bump t e c hn o logy,themet al interc onn ec t s, whic hus u ally r esid eon top  of th e  act i v e surface betwee n the a djace n t e lemen ts  openin g s, m ay be move d to the su bstrat e or  PC b oard up on  which  th echip is mo u nted. Suc h anapproac hallo wsminimi zing t he ga ps b et wee n adjacen t el e me nt s  of  the  arra y,  atthe samet ime allo win g  a virt ua lly u nlimit e dt o tal number  of  elem e n ts. Howeve r , se v er a l dra wbacks  of th e previ o usl yreporte d b a c k illumin ated stru c tur es  lim it their 
 front_illuminated or_back illuminated technologies. FIG._1a is_a_simplified cross_section_of an exemplary_prior art front_illuminated photodiode array and_FIG. 1b is_a_simplified cross section of an exemplary prior art back illuminated photodiode array. The substrate_may_be either_n-type_or_p-type material, with opposite conductivity_type diffused regions 2 therein._This creates_a p-on-n or n-on-p structure, respectively. The anode_metal_pads 3 for_the p-on-n structure (the cathode contacts for the n-on-p_structure) are always on the device_front surface. The_opposite_polarity_electrode is usually coated_(plated) on the chip backside in_the case of the front illuminated_structure (see metal layer 4, FIG. 1a),_or is made on the device_front surface (see metal pads_4, FIG._1b) using metallized through vias_6,7 in the_case of_the back illuminated_structure. (See also U.S. Published Patent_Application Ser. Nos._2003/0209652 A1, 2004/0104351 A1 and 2004/0129992_A1.)_The blanket-type implantation_5_of_the back_surface of the_die_of the_same_conductivity type as the substrate improves_both_the charge collection efficiency and DC/AC electrical_performance of the devices.
Each_of_the two approaches—the front_illuminated and back illuminated structures—has_its own advantages and disadvantages. For_example, traditional_front illuminated_structures like that shown in FIG. 1a allow building high performance_photodiodes and photodiode arrays, but impose_severe constraints on the_metal run_width._Those constraints limit_a_design of_the front illuminating photodiode array to the_use of_either a smaller number of elements,_or larger gaps between_adjacent_elements. Note that the metal runs_should be accommodated in between adjacent_diffusion areas 2 (see FIG._1a).
Back_illuminated_structures reported recently by several_companies take advantage of solder bump_technology to electrically_connect elements of the array to an_external_substrate or PC board using the_contacts_(bumps) on the front surface of_the_structure._By utilizing solder bump technology,_the metal interconnects, which usually reside_on top of the active surface between the adjacent_elements openings, may_be moved to the substrate_or_PC_board upon which the chip is mounted. Such an approach_allows minimizing_the gaps between_adjacent elements of the array, at the same time allowing_a virtually unlimited total number of elements._However, several drawbacks of the previously reported back illuminated structures limit_their