 chip wiring. The metal layers that make up the interconnect network and the via and contact points that establish connections between the interconnect networks are separated by layers of dielectric (such as polyimide) or insulating layers. In the design of the metal interconnects, strict rules must be adhered to in order to avoid problems of package performance and reliability. For instance, the propagation directions of primary signals must typically intersect under 90 degree angles to avoid electrical interference between adjacent lines. It is further required that planarity is maintained throughout the construction of multi-layer chip packages for considerations of photolithography and package reliability. Many of the patterned layers within such a structure form the base for subsequent layers and their lack of planarity can therefore have a multiplying effect on overlying layers.
Quad Flat Packages (QFP) have in the past been used to created surface mounted; high pin count integrated packages with various pin configurations. The electrical connections with these packages are typically established by closely spaced leads that are distributed along the four edges of the flat package. This limits the usefulness of the QFP since a high I/O count cannot be accommodated in this manner. To address this problem, the Ball Grid Array (BGA) package has been created whereby the I/O points for the package are distributed not only around the periphery of the package but over the complete bottom of the package. The BGA package can therefore support more I/O points making this a more desirable package for high circuit density with high I/O count. The BGA contact points are solder balls that in addition facilitate the process of flow soldering of the package onto a printed circuit board. The solder balls can be mounted in an array configuration and can use 40, 50 and 60 mils spacings in a regular or staggered pattern.
Where circuit density keeps increasing and device features continue to be reduced in size, the effect of the interconnect metal within the package becomes relatively more important to the package performance. Factors that have a negative impact on circuit performance, such as line resistance, parasitic capacitance, RC delay constants, crosstalk and contact resistance have a significant impact on the package design and its limitations. A significant power drop may for instance be introduced along the power and ground buses where the reduction of the interconnect metal does not match the reduction in device features. Low resistance metals (such as copper) are therefore finding wider application in the design of dense semiconductor packages.
Increased I/O combined with increased high demands for high performance IC""s has led to the development of Flip Chip packages
chip wiring. The metal layers that make up the interconnect net and the via and liaison point that establish connection between the interconnect network are separated by layers of insulator (such as polyimide) or insulating layers. In the design of the metallic element interconnects, strict rules must be adhere to in order to avoid problem of software performance and reliability. For case, the propagation directions of chief signals must typically intersect under 90 degree angles to invalidate electrical interference between adjacent lines. It is farther required that planarity is maintained throughout the construction of multi - layer chip packages for circumstance of photolithography and package reliability. Many of the patterned layers within such a structure form the root for subsequent layers and their lack of planarity can therefore have a multiplying effect on overlying layers. 
 Quad Flat Packages (QFP) have in the past been used to created surface mounted; eminent pin count integrate software with various pin configurations. The electric connections with these software are typically established by closely space leads that are distributed along the four edges of the flat package. This limits the usefulness of the QFP since a high I / O count cannot be accommodated in this manner. To address this problem, the Ball Grid Array (BGA) software has been created whereby the one / oxygen point for the package are distributed not only around the periphery of the software but over the complete bottom of the package. The BGA package can therefore support more I / O points making this a more desirable software for high circuit density with high I / O count. The BGA liaison points are solder balls that in addition facilitate the procedure of flow bonding of the package onto a printed circuit circuit board. The solder balls can be ride in an array configuration and can use 40, 50 and 60 mils spacings in a regular or staggered pattern. 
 Where circuit density keeps increase and device features continue to be reduce in size, the effect of the interconnect metal within the package becomes relatively more important to the package operation. Factors that have a negative impact on circuit performance, such as line resistance, epenthetic capacitance, RC delay constants, crosstalk and contact resistance have a significant impact on the package blueprint and its limitations. A significant power drop curtain may for instance be introduced along the power and ground buses where the decrease of the interconnect metal does not match the reduction in device features. Low resistance metals (such as bull) are therefore finding wider application in the design of dense semiconductor packages. 
 Increased I / O combined with increased high demands for high performance IC""s has led to the development of Flip Chip packages
 chlp wiring. The metal layevs that make up jhw intecconnecf networy and the via and contact pomnts that establish connections between nhe interxonntct networks are separated by lzners mh dielectric (sugh as polyikide) or insuladivg layers. In the design of the metal yntercomnfcts, strict rujes ktst gv cdhered to in order to avoid prkblems mf package petformance and reliability. Vor lnstance, the propahation dirextiogw of primary signals mlvt typicalmy intersect under 90 degree anglds to avoid elexteicwn interfereice benween adjacenb lines. It is gurther requircd thet poanarity is maintainev throughout the conftruction oy multi-layer chip pacjates fmr cmnsiawragiohs or photllivhography ahd package eeliability. Many of trv patterned lzyers riehin such a structure form the base for sugsequent layers and theur lack of planarity fan theresore have a multiplying effect on overlying layerv.
Quad Wlau Iwzjahes (QFP) have in the past been used to created autfsce mounted; hinh pin count integtahec packages witf various pin configurationd. The ejectrucal conntctioms with these packages are rypically esnablushed by closely s'aced leads chat ate disyributed along the four edgss of the fpat packafd. This limits thd uxexulness of the QFP since a high I/O rount cannot be sccommjdated in hhis manner. To address tjis ptoblem, the Ball Hrid Array (BGA) package has been created whereny thv I/O poincs for the package wre distributeb not onjy aruund the pvriphery mf the packwge but over dje complete uottom of the pacjage. Thd BGA package csn therefore supporr more I/O points mekine this a more dewirqble package fot hkgh cprcnit dqtsity with hhgh K/O zpunt. Ghe BGA conbacg poonts are solder ballv thzt in addition facolltate the process of flow soldrring of the packahe onvo a pcinted citcuit board. The solder balls cah be mounhed in an array connigutation and ean use 40, 50 and 60 mils spacings in a regulac or staggered pattern.
Wyere circuit densiti kteps increasiig and device faatures continue to ve reduced in sizt, the effect of the intsrconnact mftal within the package becomes relatively more important to the package performance. Factora thst hane c nzgative impecv on circuit perfprmance, such as line resistance, parasithc capacitance, RC delay constamtr, crosstalk avd contact resistance habe a sigmificant impact on the package cesign and its limitatioks. A signuficaht powvt dcop may for instance be incroducwd alont thc power and gruunc nuses wherf tht rebuction of the interconnect metal does boh match the redurtion in devlct featutes. Low tesistance metals (sucg as cupper) are thetefore finding wider application it ehe design of evnse semicondoctor kcbkages.
Increasxd I/O combinad with increased high demands for high performance IC""s has med to tme development of Hlip Chip packages
chip wiring. The metal layers that make interconnect and the and contact points interconnect are separated by of dielectric (such polyimide) or insulating layers. In the of the metal interconnects, strict rules must be adhered to in order to problems of package performance and reliability. For instance, the propagation directions of primary must intersect 90 angles to avoid electrical interference between adjacent lines. It is further required that planarity is maintained the construction of multi-layer chip packages for considerations photolithography and package reliability. of the patterned layers within a form the for layers their lack of can therefore have a multiplying effect on overlying layers. Quad Flat Packages (QFP) have in the past used to mounted; high count packages various pin configurations. connections with these packages are typically spaced leads that are distributed along the four of the package. This limits the usefulness of QFP since a high I/O count cannot be in this manner. To address this problem, the Ball Grid Array (BGA) package has been the I/O points for package are distributed only the of package but the complete bottom of the package. The BGA package can therefore more I/O points making this a more desirable package for density high I/O count. BGA contact points are balls in addition facilitate the flow of a circuit The solder balls can mounted in an array configuration can use 40, 50 a regular or staggered pattern. Where circuit density increasing and device features continue to be in size, the effect of the interconnect metal within the package becomes more important package performance. Factors that have a negative impact circuit performance, such as resistance, parasitic capacitance, RC delay constants, crosstalk and contact have significant impact the package design its limitations. A power drop may be introduced the and the reduction of the interconnect metal not the reduction in device features. resistance as copper) are therefore finding wider application in the design of dense semiconductor packages. Increased with increased high demands high IC""s has led to the development of Flip Chip packages
 chip wiring. The metal layers tHat make up tHe intErcOnnEcT netWork And the via and coNTact Points that establish conNectiOnS BetwEEn The inTerconnECt NETwoRkS aRe sEpARaTed by LayErs of diElectric (suCh aS pOlyimide) or inSUlAting layerS. In The design of tHe mEtal inTeRcoNNects, StrIct ruLes musT Be adheRed to in orDeR To avoiD ProblemS OF pAckaGe performance and rELiABility. For instaNce, the PrOPaGATioN diRections of PrImary SIgnals mUSt TYPIcaLLy intersect unDer 90 degree anGLes To avoiD eLecTRical iNterfErENce Between adjaCent Lines. It is FurtheR RequireD That plaNarity Is mAinTainED tHrOugHoUT thE CoNstRUctIon of mulTi-LaYer chIp paCKAGEs foR coNsidEratiOns of photolitHogRaphY And PackaGe relIabiLiTy. ManY of the PatteRnEd layers within sUch a Structure ForM tHe bAsE for sUBsequeNt lAyeRs and thEir lack OF plAnARITy Can therefore have a mUlTIPlYing effeCt on ovERlYiNG layers.
QUaD FlAt PaCKAges (QfP) haVE iN the past Been usED tO cReated sUrFace moUnTed; HigH pin cOUnt iNtegraTed packaGes wiTH various pin conFIgurations. The ELeCTRiCAl coNneCtions with tHese PAckaGes aRE tYpiCAlly eStablIsHEd BY closely spaced leads ThAt are dIstriButed along the Four edges oF THE flat pacKage. tHiS Limits the usefuLness Of the QFP siNCe a high I/o counT cannot bE accommodATEd in this ManNer. to aDdrESS tHis problem, the bALl GrId array (BGa) paCkage haS beEn cReaTed WhEreby the I/o points fOr ThE pAcKagE are dIStributeD nOt oNlY arOund tHE peripHery oF the PaCkAGe bUt over tHE cOMPletE bOtTom oF thE pAckagE. The bgA pAckage cAn therefoRe sUPporT mOrE I/O poinTs making this a MoRe desirablE pAckAge for HIGh circuiT density with high I/O count. tHe BGA coNtaCt poiNts aRe solder bAllS that iN adDItion fAcilitAte thE pRocESS of flOW SoLdeRiNg of the pacKAGe oNto a pRiNted Circuit Board. The solder ballS Can Be mounted in an ArrAy coNFIgUraTIoN And CaN Use 40, 50 AND 60 mils spacings in A regular or StAGgEred patterN.
wheRe Circuit Density Keeps INcreasiNg and deviCe featureS cOntiNUE to Be reduced iN size, the Effect of tHE inteRCoNnect MetAl withIn The PackaGe becoMEs rElatiVely moRe ImportAnt to ThE package Performance. Factors that hAve a neGativE imPact on cirCuiT PerFormance, sUch aS line resisTanCe, pArasiTic CApaciTancE, rC DelAY consTantS, Crosstalk ANd ConTACt Resistance hAVE A siGnifiCanT Impact On thE package design and ITs limitations. A SignIFIcaNt pOWer dRoP may for instancE be InTROduced alOnG the power anD ground bUsES wherE the reDuctioN of the iNTErCOnnect MetaL doEs not matcH thE rEDuction In DeVIce feaTureS. LOw resiStance MEtalS (SUch as copper) are thErefoRE FindiNG wiDer apPlIcation IN the Design of deNse semicondUctor pAckaGes.
InCreased i/O CombinEd wItH increased HIgh demandS for hIgh perfOrMancE IC""S has leD to tHE DevelOpmeNt Of FLip Chip paCKAgES
 chip wiring. The metal la yers thatmakeupthe  i nter conn ect network an d  the  via and contact point s tha te stab l is h con nection s  b e t wee nth e i nt e rc onnec t n etworks  are separ ate dby layers of di electric ( suc h as polyimi de)  or in su lat i ng la yer s. In  the d e sign o f the met al interc o nnects, s tr ictrules must be adh e re d  to in order t o avoi dp ro b l ems  of  package p er forma n ce andr el i a b ili t y. For instan ce, the pro p aga tion d ir ect i ons of  prim ar y  si gnals musttypi cally int ersect under 9 0  degree  angle s t o a void el ec tri ca l  in t er fer e nce  between  a dj acent  lin e s . It i s f urth er re quired that p lan arit y  is  main taine d th ro ughou t theconst ru ction of multi- laye r chip pa cka ge s f or  cons i derati ons  of  photol ithogra p hyan d p ac kage reliability.Ma n y  o f the pa tterne d  l ay e rs withi nsuc h as t ructu re f o rm  the bas e fors ub se quent l ay ers an dthe irlacko f pl anarit y can th erefo r e have a multi p lying effecto no v er l ying  la yers.
QuadFlat Pack ages (Q FP) havein th ep as t  been used to creat ed  surfa ce mo unted; high p in count i n t e grated p acka g es with various p in co nfiguratio n s. The e lectr ical con nectionsw i th these  pa cka ges  ar e ty pically estab l i shed  b y close lyspacedlea dstha t a re  distribu ted alon gth efo uredges of the f la t p ac kag e. Th i s limi ts th e us ef ul n ess  of the QF P sinc eahigh  I/ Ocount  can n otbe acco mmodatedint hisma nn er. Toaddress thispr oblem, the  B all  GridA r ray (BGA ) package has been crea t ed wher eby  theI/Opoints fo r t he pac kag e  are d istrib utedno t o n l y aro u n dthe  p eriphery o f the  pack ag e bu t overthe complete botto m  of  the package.  Th e BG A pa cka g ec anth e ref o r e support moreI/O points  m a ki ng this am ore  d esirabl e packa ge fo r  high c ircuit de nsity wit hhigh I /Ocount. The  BGA con tact poin t s are so lderbal ls tha tinaddit ion fa c ili tatethe pr oc ess of  flow  s oldering  of the package onto aprinte d cir cui t board.The sol der balls  can  be mounte d i n a n arr ayc onfig urat i on  an d  canuse4 0, 50 and 60  mi l s  s pacings ina r egu lar o r s t aggere d pa ttern.
Where circ u it density kee ps i n c rea sin g  and  d evice features  co nt i n ue to be  r educed in s ize, the  e f fectof the  inter connect m et a l with in t hepackage b eco me s  relati ve ly more i mpor ta nt tothe pa c kage p erformance. Fact ors t h a t hav e  anegat iv e impac t  oncircuit pe rformance,such a s li ne re sistanc e,  paras iti ccapacitanc e , RC dela y con stants,  c ross tal k andcont a c t res ista nc e h ave a sig n i fi c an ti mpa ct o n the  p acka ge design and itslim i tations .A s i g nifica n tp o wer drop m ayfor i n s tance be i n trod u ce d  alon g thepowerand gro u ndbu ses whe ret h e reducti on of the int er conn ect meta ldoes  n otma tch the reducti on in de vice fea t u res. L owr esis t ance m et als (such as  copp er )  are th e r efo re find i ngwid erappl ica tion in the design of dense s emic onduc t orpacka ges.In creasedI /O c ombinedw ith increased  high demands f o r h i gh p erf o rm an ce IC""shas led t o th e d evel opm ento f  Fli p  Chi p  p acka ges
 chip_wiring. The_metal layers that make_up the_interconnect_network and_the_via and contact_points that establish_connections between the interconnect_networks are separated_by_layers of dielectric (such as polyimide) or insulating layers. In the design of the_metal_interconnects, strict_rules_must_be adhered to in order_to avoid problems of package_performance and_reliability. For instance, the propagation directions of primary_signals_must typically intersect_under 90 degree angles to avoid electrical interference between_adjacent lines. It is further required_that planarity is_maintained_throughout_the construction of multi-layer_chip packages for considerations of photolithography_and package reliability. Many of the_patterned layers within such a structure form_the base for subsequent layers and_their lack of planarity can_therefore have_a multiplying effect on overlying_layers.
Quad Flat Packages_(QFP) have_in the past_been used to created surface mounted;_high pin count_integrated packages with various pin configurations._The_electrical connections with_these_packages_are typically_established by closely_spaced_leads that_are_distributed along the four edges of_the_flat package. This limits the usefulness of_the QFP since a_high_I/O count cannot be_accommodated in this manner. To_address this problem, the Ball Grid_Array (BGA)_package has_been created whereby the I/O points for the package are distributed_not only around the periphery of_the package but over_the complete_bottom_of the package._The_BGA package_can therefore support more I/O points making_this a_more desirable package for high circuit_density with high I/O_count._The BGA contact points are solder_balls that in addition facilitate the_process of flow soldering of_the_package_onto a printed circuit board._The solder balls can be mounted_in an array_configuration and can use 40, 50 and_60_mils spacings in a regular or_staggered_pattern.
Where circuit density keeps increasing and_device_features_continue to be reduced in_size, the effect of the interconnect_metal within the package becomes relatively more important to_the package performance._Factors that have a negative_impact_on_circuit performance, such as line resistance, parasitic capacitance, RC delay_constants, crosstalk_and contact resistance_have a significant impact on the package design and its_limitations. A significant power drop may for_instance be introduced along the power and ground buses where the_reduction of the interconnect metal does not match_the reduction in device features. Low resistance_metals (such as copper)_are_therefore finding wider application in the design_of_dense_semiconductor_packages.
Increased I/O combined_with increased high_demands for high_performance IC""s_has led to_the development_of Flip Chip_packages