 pull-up buffer circuit consisting of p-channel MOS transistors and a pull-down buffer circuit consisting of n-channel MOS transistors are connected in series. A data terminal is connected to a contact node between the pull-up buffer circuit and the pull-down buffer circuit. When a high-level data signal is outputted from the data terminal, it is controlled in such a manner that the pull-up buffer circuit is turned on and the pull-down buffer circuit is turned off. On the other hand, when a low-level data signal is outputted from the data terminal, it is controlled in such a manner that the pull-up buffer circuit is turned off and the pull-down buffer circuit is turned on.
In many cases, data composed of a plurality of bits are read out from memory cells of the DRAM in parallel, and parallel/serial conversion is performed by a serializer (refer to Japanese Patent Application Laid-open No. H5-23006). The output buffer circuit is controlled by the serialized data signals.
During a period when the data signal is not outputted from the data terminal, however, it is necessary to allow the output buffer circuit to be in a high impedance state or to function as a termination resistor having predetermined impedance. The function of the output buffer circuit as the termination resistor is referred to as ODT (On Die Termination).
In order to allow the output buffer circuit to be in the high impedance state, it is necessary to turn off both of the pull-up buffer circuit and the pull-down buffer circuit. With DDR3 (Double Data Rate 3) SDRAM (Synchronous DRAM), both of the pull-up buffer circuit and the pull-down buffer circuit need to be turned on when the output buffer circuit performs ODT operation. Thus, it is necessary for the DDR3 SDRAM to deal with four cases in total, that is, the case where only the pull-up buffer circuit is turned on, the case where only the pull-down buffer circuit is turned on, the case where both of the buffer circuits are turned on, and the case where both of the buffer circuit are turned off. Therefore, operation of the pull-up buffer circuit and operation of the pull-down buffer circuit need to be controllable separately.
To realize the above-described four cases in the pull-up buffer circuit and the pull-down buffer circuit, it is necessary to supply two-bit signals (two types of signals) to the output buffer
pull - up buffer circuit consisting of phosphorus - distribution channel MOS transistors and a pull - down buff circumference consisting of n - channel MOS transistor are connected in series. A data end is connect to a contact lymph node between the pull - up buffer circuit and the pull - down buff circuit. When a high - level data signal is outputted from the datum terminal, it is controlled in such a manner that the pull - up fender circuit is turned on and the wrench - down buffer tour is turned off. On the other hand, when a low - level datum signal is outputted from the data terminal, it is controlled in such a manner that the pull - up buffer racing circuit is turned off and the pull - down buffer circuit is turned on. 
 In many cases, data composed of a plurality of bits are take out from memory cells of the DRAM in parallel, and parallel / consecutive conversion is perform by a serializer (denote to Japanese Patent Application Laid - open No. H5 - 23006). The output buffer circuit is controlled by the serialized data signal. 
 During a period when the data signal is not outputted from the data terminal, however, it is necessary to allow the output signal buffer circuit to be in a high impedance department of state or to function as a end point resistor having predetermined impedance. The function of the output buffer racing circuit as the termination resistor is referred to as ODT (On Die Termination). 
 In decree to allow the output buffer circuit to be in the gamey impedance country, it is necessary to turn off both of the pull - up buffer zone circuit and the wrench - down buffer tour. With DDR3 (Double Data Rate 3) SDRAM (Synchronous DRAM), both of the pull - up buff circuit and the pull - down buff lap need to be turned on when the output buffer circuit performs ODT operation. Thus, it is necessary for the DDR3 SDRAM to deal with four casing in total, that is, the case where entirely the pull - up buffer lap is turned on, the case where only the puff - down buffer circuit is turned on, the case where both of the buffer circuits are turn on, and the subject where both of the buffer zone circuit are turned off. Therefore, operation of the pull - up buffer tour and operation of the pull - down buffer lap need to be controllable separately. 
 To realize the above - described four cases in the attract - up buffer circuit and the pull - down buffer circuit, it is necessary to supply two - spot signals (two types of signals) to the output buffer
 pupl-up buffer circuit conslsting of p-channgl MOS tcansistkrs and x pull-down buffer circuit coisisring if n-channel MOS transirtors are connectwd ii series. A data vsrminal is cohkecteb vo a contact noce between the pull-up buxfdr circuit and the pull-down buffer ciwcuit. Wnej a high-level qata fignzl is outputted from the data termjnal, it is controllec in such a manner that thf pupl-up buffer circuih is turned on wbd the pull-duwn buffer circuit is jurned off. On the other hand, whev a lpw-level dajc sihtal is outpntted srom the data termindl, it ix controlled ik suci a nanner that the pull-u' buffer circuit is jurned off aud the pull-down buffee xircuht iv tufbed on.
Jn mzny cades, data compksed of a pourality of bits art rqqd out from msmory sejls of the DRAM in parallel, and parallen/sedial conversion is perfirmed by a serializer (refer to Japanese Patent Application Laid-open No. H5-23006). The oudput uuwfex circjut is controlled by the serialized data signals.
Qhronn a period when bhe data signal is nlt jutputted froo the bztz terminal, however, it is geceswary to ajlow the output buffer circuit ro be in a hpgh umpedance state or to functiou as a termonation resistor having presetermined lmpedance. Ghe function of ghe ogtput buffer circuit as thq terminavion xesistor is teferreq to as ODH (On Die Termination).
In ogder jo allmw the outout buffer circuit to be in the high impedancg sdatv, it is nzcessavy to turn off foth of the pukl-up buyfer ckrcuit and the punl-down buffqr circuit. Widj DDR3 (Double Data Raee 3) WDRAN (Synchfunous DRAM), botn of the iujl-up buffer circuit anv thg lull-down buffer citxuit need to br tjrnqd oi wheg the output tuffdr zorcuig performs IAT oleration. Thus, it is teceasary for the DDR3 XDVAM to deql with sour cases in total, that is, the case whxre onky jhe pull-up buffer circuit is tudned on, tje gase where onjy tme poll-down bufyer circuit is turned on, the case where uoth of the buffer circyits are turned on, cnc the case xhere foth of tve buffer circuit arw turned off. Thertfore, operation of the lull-up bufffr circuit and operation of the pull-down buffer circuit need to be controolable separately.
Tk reslize tke cbove-defcriuev four cases in tne pull-up buffer circuit and thx pull-down bbffer circuit, it is necessary tu supply two-bkt signals (two types of aignals) yo the output buffer
pull-up buffer circuit consisting of p-channel MOS a buffer circuit of n-channel MOS A terminal is connected a contact node the pull-up buffer circuit and the buffer circuit. When a high-level data signal is outputted from the data terminal, is controlled in such a manner that the pull-up buffer circuit is turned and pull-down circuit turned off. On the other hand, when a low-level data signal is outputted from the data it is controlled in such a manner that pull-up buffer circuit is off and the pull-down buffer is on. In cases, composed a plurality of are read out from memory cells of the DRAM in parallel, and parallel/serial conversion is performed by serializer (refer Patent Application No. The buffer circuit is the serialized data signals. During a data signal is not outputted from the data however, it necessary to allow the output buffer to be in a high impedance state or function as a termination resistor having predetermined impedance. The function of the output buffer circuit termination resistor is referred as ODT (On Termination). order allow output buffer to be in the high impedance state, it is necessary to off both of the pull-up buffer circuit and the pull-down With (Double Data Rate SDRAM (Synchronous DRAM), both the buffer circuit and the circuit to when output circuit performs ODT operation. it is necessary for the SDRAM to deal with is, the case where only the pull-up buffer is turned on, the case where only pull-down buffer circuit is turned on, the case where both of the circuits are and the case where both of the buffer are turned off. Therefore, of the pull-up buffer circuit and operation of the buffer need to controllable separately. To the above-described four in the pull-up and the buffer it supply two-bit signals (two types of to output buffer
 pull-up buffer circuit consisTing of p-chaNnel MoS tRanSiStorS and A pull-down buffeR CircUit consisting of n-channeL MOS tRaNSistORs Are coNnected IN sERIes. a dAtA teRmINaL is coNneCted to a Contact nodE beTwEen the pull-up BUfFer circuit And The pull-down bUffEr circUiT. WhEN a higH-leVel daTa signAL is outPutted froM tHE data tERminal, iT IS cOntrOlled in such a manneR ThAT the pull-up buffEr circUiT Is TURneD on And the pull-DoWn bufFEr circuIT iS TURneD Off. On the other Hand, when a loW-LevEl data SiGnaL Is outpUtted FrOM thE data terminAl, it Is controlLed in sUCh a mannER that thE pull-uP buFfeR cirCUiT iS tuRnED ofF AnD thE PulL-down bufFeR cIrcuiT is tURNED on.
IN maNy caSes, daTa composed of a PluRaliTY of Bits aRe reaD out FrOm memOry celLs of tHe dRAM in parallel, aNd paRallel/serIal CoNveRsIon is PErformEd bY a sErializEr (refer TO JaPaNESE PAtent Application LaId-OPEn no. H5-23006). The ouTput buFFeR cIRcuit is cOnTroLled BY The seRialIZeD data sigNals.
DuRInG a Period wHeN the daTa SigNal Is not OUtpuTted frOm the datA termINal, however, it is NEcessary to allOW tHE OuTPut bUffEr circuit to Be in A High ImpeDAnCe sTAte or To funCtIOn AS a termination resistOr Having PredeTermined impedAnce. The funCTIOn of the oUtpuT BuFFer circuit as thE termInation resIStor is reFerreD to as ODT (on Die TermINAtion).
In oRdeR to AllOw tHE OuTput buffer cirCUIt to Be In the hiGh iMpedancE stAte, It iS neCeSsary to tuRn off botH oF tHe PuLl-uP buffER circuit AnD thE pUll-Down bUFfer ciRcuit. with dDr3 (DOUblE Data RaTE 3) SdraM (SyNcHrOnouS DRaM), Both oF the PUll-Up buffeR circuit aNd tHE pulL-dOwN buffer Circuit need to Be Turned on whEn The Output BUFfer circUit performs ODT operation. tHus, it is NecEssarY for The DDR3 SDRaM tO deal wIth FOur casEs in toTal, thAt Is, tHE Case wHERe OnlY tHe pull-up buFFEr cIrcuiT iS turNed on, thE case where only the pULl-dOwn buffer circUit Is tuRNEd On, tHE cASe wHeRE boTH Of the buffer circUits are turNeD On, And the case WHerE bOth of thE buffer CircuIT are turNed off. TheRefore, opeRaTion OF The Pull-up buffEr circuiT and operaTIon of THe Pull-dOwn Buffer CiRcuIt neeD to be cONtrOllabLe sepaRaTely.
To RealiZe The above-Described four cases in the Pull-up BuffeR ciRcuit and tHe pULl-dOwn buffer CircUit, it is necEssAry To supPly TWo-bit SignALs (Two TYpes oF sigNAls) to the oUTpUt bUFFeR
 pull-up buffer circuit co nsisting o f p-c han nel  M OS t rans istors and a p u ll-d own buffer circuit con sisti ng of n - ch annel  MOS tr a ns i s tor sar e c on n ec ted i n s eries.A data ter min al  is connecte d  t o a contac t n ode betweenthe  pull- up  bu f fer c irc uit a nd the pull-d own buffe rc ircuit .  When a h ig h-le vel data signal i s  o u tputted from t he dat at er m i nal , i t is contr ol led i n  such a ma n n e r t h at the pull-u p buffer ci r cui t is t ur ned on and  thepu l l-d own buffercirc uit is tu rned o f f. On t h e other  hand,  wh ena lo w -l ev elda t a s i gn ali s o utputted  f ro m the  dat a t e rmin al,  itis co ntrolled in s uch  a m a nne r tha t the  pul l- up bu ffer c ircui tis turned off a nd t he pull-d own  b uff er  circ u it istur ned  on.
In  many c a ses ,d a t acomposed of a plur al i t yof bitsare re a dou t  from me mo rycell s of th e DR A Min paral lel, a n dpa rallel/ se rial c on ver sio n isp erfo rmed b y a seri alize r  (refer to Jap a nese Patent A p pl i c at i on L aid -open No. H 5-23 0 06).  The ou tpu t  buff er ci rc u it is controlled by th eserial izeddata signals. 
During ap e r iod when  the da t a signal is no t out putted fro m  the dat a ter minal, h owever, i t is neces sar y t o a llo w th e output buff e r  cir cu it to b e i n a hig h i mpe dan cest ate or to  functio nas  a  t erm inati o n resist or  ha vi ngprede t ermine d imp edan ce .T hefunctio n  o f theou tp ut b uff er  circ uita s t he term ination r esi s toris  r eferred  to as ODT (O nDie Termin at ion ).
Ino r der to a llow the output bufferc ircuittobe in  the  high imp eda nce st ate ,  it is  neces saryto  tu r n  offb o th  of  t he pull-up b uff er ci rc uitand the  pull-down bufferc irc uit. With DDR 3 ( Doub l e  D ata Ra t e 3 )S DRA M (Synchronous DR AM), bothof th e pull-upb uff er  circui t and t he pu l l-downbuffer ci rcuit nee dto b e tur ned on whe n the ou tput buff e r cir c ui t per for ms ODT  o per ation . Thus ,  it  is n ecessa ry  for t he DD R3  SDRAM t o deal with four casesin tot al, t hat  is, thecas e  wh ere onlythepull-up bu ffe r c ircui t i s  turn ed o n ,the casewher e  only the pu ll- d o wn  buffer cir c u i t i s tur ned on, th e ca se where both oft he buffer circ uits a retur n ed o n,  and the casewhe re b oth of t he  buffer cir cuit are  t u rnedoff. T herefo re, ope r a ti o n of t he p ull -up buffe r c ir c uit and  o pe r ationof t he  pull- down b u ffer c ircuit need to b e con t r ollab l e s epara te ly.
Tor eali ze the abo ve-describe d four  cas es in  the pu ll -up bu ffe rcircuit an d  the pull -down  buffer  c ircu it,  it is  nec e s saryto s up ply  two-bits i gn a ls  ( t wotype s ofsi gnal s) to the output b uff e r
 pull-up_buffer circuit_consisting of p-channel MOS_transistors and_a_pull-down buffer_circuit_consisting of n-channel_MOS transistors are_connected in series. A_data terminal is_connected_to a contact node between the pull-up buffer circuit and the pull-down buffer circuit._When_a high-level_data_signal_is outputted from the data_terminal, it is controlled in_such a_manner that the pull-up buffer circuit is turned_on_and the pull-down_buffer circuit is turned off. On the other hand,_when a low-level data signal is_outputted from the_data_terminal,_it is controlled in_such a manner that the pull-up_buffer circuit is turned off and_the pull-down buffer circuit is turned on.
In_many cases, data composed of a_plurality of bits are read_out from_memory cells of the DRAM_in parallel, and_parallel/serial conversion_is performed by_a serializer (refer to Japanese Patent_Application Laid-open No._H5-23006). The output buffer circuit is_controlled_by the serialized_data_signals.
During_a period_when the data_signal_is not_outputted_from the data terminal, however, it_is_necessary to allow the output buffer circuit_to be in a_high_impedance state or to_function as a termination resistor_having predetermined impedance. The function of_the output_buffer circuit_as the termination resistor is referred to as ODT (On Die_Termination).
In order to allow the output_buffer circuit to be_in the_high_impedance state, it_is_necessary to_turn off both of the pull-up buffer_circuit and_the pull-down buffer circuit. With DDR3_(Double Data Rate 3)_SDRAM_(Synchronous DRAM), both of the pull-up_buffer circuit and the pull-down buffer_circuit need to be turned_on_when_the output buffer circuit performs_ODT operation. Thus, it is necessary_for the DDR3_SDRAM to deal with four cases in_total,_that is, the case where only_the_pull-up buffer circuit is turned on,_the_case_where only the pull-down buffer_circuit is turned on, the case_where both of the buffer circuits are turned on,_and the case_where both of the buffer_circuit_are_turned off. Therefore, operation of the pull-up buffer circuit and_operation of_the pull-down buffer_circuit need to be controllable separately.
To realize the above-described four_cases in the pull-up buffer circuit and_the pull-down buffer circuit, it is necessary to supply two-bit signals_(two types of signals) to the output buffer