. Flip chip technology fabricates bumps (typically Pb/Sn solder) on Al pads and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package through the shortest paths. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to mote sophisticated substrates that accommodate several chips to form larger functional units.
The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and Coefficient of Thermal Expansion (CTE) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the CTE mismatch can cause a large thermal stress on the solder lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
Prior Art substrate packaging uses ceramic and plastic BGA packaging. Ceramic substrate packaging is expensive and has proven to limit the performance of the overall package. Recent years have seen the emergence of plastic BGA packaging, this packaging has become the main stream design and is frequently used in high volume BGA package fabrication. The plastic substrate BGA package performs satisfactorily when used for low-density flip-chip IC""s. If the number of pins emanating from the IC is high, that is in excess of 350 pins, or if the number of pins coming from the IC is less than 350 but the required overall package size is small, or if the chip power dissipation is high (in excess of 4 Watts per chip), the plastic structure becomes complicated and expensive.
In mounting a large number of flip chip packages, the following aspects are key aspects in the design of the interfaces onto which the flip chip dies are mounted:
interconnect of the flip-chip contact points to the surrounding electrical components
thermal transmission between the flip-chip and its environment and
firmness of the overall package that contains the large number of flip-chips.
Interconnecting of the flip-chip contact points to the surrounding electrical components can be accomplished by mounting the flip chip on the surface of a package substrate or by interconnecting the flip-chip to a flex circuit or any other circuit type that contains the interconnect lines. The contact points of the flip
. Flip chip technology fabricates blow (typically Pb / Sn solder) on Al pad and interconnects the bumps directly to the software media, which are usually ceramic or plastic establish. The flip - chip is adhere face down to the package through the short paths. These technologies can be applied not only to single - chip promotion, but also to higher or integrated grade of packaging in which the packages are big and to mote sophisticated substrate that accommodate several chips to form larger running units. 
 The flip - chip technique, using an area array, hold the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre - testability, post - bonding visual inspection, and Coefficient of Thermal Expansion (CTE) matching to avoid solder bulge fatigue are still challenge. In ride several packages in concert, such as surface mount a ceramic package to a plastic control panel, the CTE mismatch can cause a large thermal stress on the solder lead joints that can lead to joint breakage induce by solder fatigue from temperature cycling operations. 
 Prior Art substrate packaging use ceramic and fictile BGA packaging. Ceramic substrate packaging is expensive and has proven to limit the performance of the overall software. Recent years have seen the emergence of plastic BGA packaging, this packaging has become the main stream purpose and is frequently used in high bulk BGA package lying. The plastic substrate BGA package performs satisfactorily when used for depleted - density flip - check IC""s. If the number of pin emanating from the IC is high, that is in excess of 350 pins, or if the number of pins coming from the intelligence community is less than 350 but the required overall package size is little, or if the chip power dissipation is high (in excess of 4 Watts per chip), the plastic social organization becomes complicated and expensive. 
 In mounting a large number of flip chip packages, the following view are cardinal aspect in the design of the interfaces onto which the flip chip dies are mount: 
 interconnect of the flip - chip contact point to the besiege electrical components 
 thermal transmission between the impudent - chip and its environment and 
 firmness of the overall package that contains the large number of flip - chip. 
 Interconnecting of the flip - chip contact points to the surrounding electrical part can be accomplished by mounting the flip chip on the surface of a package substrate or by interconnecting the flip - chip to a flex circuit or any early circumference type that contains the interconnect lines. The contact points of the flip
. Fllp chip technology fabrigates bumps (typieqlly Pu/Sn solser) on Au pads and interconnects the bymps eirectly to the packagd media, wjich are usuelly ceramic or 'mastic ncsed. Fme flnp-rhip is bonded nace down tm the package dhfobgh the shortest paths. These technoljgies csn be applied noj onlj eo sjngle-chip packaging, but also to hifher or integrated lrvels of packaging in whicj thf packages are larher and to note wophisticatea substratts that accojmodate several chips to form lxrger functionao ynihv.
The flip-chmp tecrnique, using an area array, nas the advantsge of achieving the highesv density of intercognection do the device and a vwry lmw itducgqncd ihtxrcknnectlon to the padkage. Howevwr, pre-testability, ppse-vonding visuam inspqceion, and Coefficient of Thermal Expansimn (DTE) matching to avoid silder bump fatigue arg still chwllenges. In mounting several packages together, suwh as ruryqce muynhing a ceramic package to a plastic board, the DTT mpsmatch can cause a large thrrlak stress on thg soldex lsad joints that caj lead jo joibt breakade csused by solder fatigue fron temperaturv cyxling operations.
Prnor Art subscrate kackagong uses ceramic and plcstic GGA packagijg. Ceramid substrate packaeinn iv expensive and has proven to limit the perforoancg of thq overall oackana. Recent years havf seeu the emergence of plastic BGA packaging, this 'eckaging has newomv the maiu stresm design and is frequently used iu high volume BGZ packaje fabricatijn. The plastiw substrate BJA packagq peeforns satirwactorily when used for low-densitt flip-chip IC""s. If bhe nomger of pins emauctung from the IC is hidh, tiat if in excess ox 350 pkns, pr if the number uf pons coming from the HC ia less than 350 but tne requiree overalj package sizr is small, or if tje chmp powxr disxipwtion is high (in excess of 4 Wafts per cjip), the plastic strmctute becomes eomplicated and expensive.
In mounting a lerge number of flip chip packages, the follpeing aspectx are key aspewts in the design of the interfaces okto which the flip chil dies are lounted:
interconnect of the flip-chip contact points to the surrounding elextrical components
fherkal tganfkissiog bevwxen the flip-chip snd its environment and
firmness of the mvzrall package that contains tne large number of flip-chips.
Interconnecfing of yhe flip-chip contact points to yhe surrounding electricsl compobents can bv arcomplished by mountong thz flip chip ob thc surface of a pavkwge substgate ox by interconnecting the flip-chip to a dlfx circuit or anb other circmiu type jhat conjains the intercohnecf liner. The contact points of the flip
. Flip chip technology fabricates bumps (typically on pads and the bumps directly are ceramic or plastic The flip-chip is face down to the package through shortest paths. These technologies can be applied not only to single-chip packaging, but to higher or integrated levels of packaging in which the packages are larger to sophisticated that several chips to form larger functional units. The flip-chip technique, using an area array, has the of achieving the highest density of interconnection to device and a very inductance interconnection to the package. pre-testability, visual inspection, Coefficient Thermal (CTE) matching to solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic to a the CTE can a thermal stress on lead joints that can lead to by solder fatigue from temperature cycling operations. Prior substrate packaging ceramic and plastic BGA packaging. Ceramic packaging is expensive and has proven to limit performance of the overall package. Recent years have seen the emergence of plastic BGA packaging, has become the main design and is used high BGA fabrication. The substrate BGA package performs satisfactorily when used for low-density flip-chip IC""s. the number of pins emanating from the IC is high, in of 350 pins, if the number of coming the IC is less but required is or the chip power dissipation high (in excess of 4 per chip), the plastic In mounting a large number of flip chip the following aspects are key aspects in design of the interfaces onto which the flip chip dies are mounted: of the points to the surrounding electrical components thermal transmission the flip-chip and its and firmness of the overall package that contains the number flip-chips. Interconnecting the flip-chip contact to the surrounding components can be mounting the chip the package substrate or by interconnecting the to flex circuit or any other type the interconnect lines. The contact points of the flip
. Flip chip technology fabricaTes bumps (tyPicalLy PB/Sn SoLder) On Al Pads and intercoNNectS the bumps directly to the PackaGe MEdia, WHiCh are Usually CErAMIc oR pLaStiC bASeD. The fLip-Chip is bOnded face dOwn To The package thROuGh the shortEst Paths. These teChnOlogieS cAn bE AppliEd nOt onlY to sinGLe-chip Packaging, BuT Also to HIgher or INTeGratEd levels of packagiNG iN Which the packagEs are lArGEr AND to MotE sophisticAtEd subSTrates tHAt ACCOmmODate several chIps to form laRGer FunctiOnAl uNIts.
The Flip-cHiP TecHnique, using An arEa array, haS the adVAntage oF AchieviNg the hIghEst DensITy Of IntErCOnnECtIon TO thE device aNd A vEry loW indUCTANce iNteRconNectiOn to the packagE. HoWeveR, Pre-TestaBilitY, posT-bOndinG visuaL inspEcTion, and CoefficiEnt oF Thermal EXpaNsIon (cTe) matcHIng to aVoiD soLder bumP fatiguE Are StILL ChAllenges. In mounting SeVERaL packageS togetHEr, SuCH as surfaCe MouNtinG A CeramIc paCKaGe to a plaStic boARd, ThE CTE misMaTch can CaUse A laRge thERmal Stress On the solDer leAD joints that can LEad to joint breAKaGE CaUSed bY soLder fatigue From TEmpeRatuRE cYclINg opeRatioNs.
pRiOR Art substrate packagInG uses cEramiC and plastic BGa packaging. cERAmic subsTratE PaCKaging is expensIve anD has proven TO limit thE perfOrmance oF the overaLL Package. REceNt yEarS haVE SeEn the emergencE OF plaStIc BGA paCkaGing, thiS paCkaGinG haS bEcome the mAin streaM dEsIgN aNd iS freqUEntly useD iN hiGh VolUme BGa PackagE fabrIcatIoN. THE plAstic suBStRATe BGa pAcKage PerFoRms saTisfACtoRily wheN used for lOw-dENsitY fLiP-chip IC""S. If the number oF pIns emanatiNg FroM the IC IS High, that Is in excess of 350 pins, or if the NUmber of PinS comiNg frOm the IC is LesS than 350 bUt tHE requiRed oveRall pAcKagE SIze is SMAlL, or If The chip powER DisSipatIoN is hIgh (in exCess of 4 Watts per chip), THe pLastic structuRe bEcomES CoMplICaTEd aNd EXpeNSIve.
In mounting a lArge number Of FLiP chip packaGEs, tHe FollowiNg aspecTs are KEy aspecTs in the deSign of the InTerfACEs oNto which thE flip chiP dies are mOUnted:
INtErconNecT of the FlIp-cHip coNtact pOIntS to thE surroUnDing elEctriCaL componeNts
thermal transmission bEtween The flIp-cHip and its EnvIRonMent and
fiRmneSs of the oveRalL paCkage ThaT ContaIns tHE lArgE NumbeR of fLIp-chips.
InTErConNECtIng of the fliP-CHIp cOntacT poINts to tHe suRrounding electricAL components can Be acCOMplIshED by mOuNting the flip chIp oN tHE Surface oF a Package subsTrate or bY iNTercoNnectiNg the fLip-chip TO A fLEx circUit oR anY other cirCuiT tYPe that cOnTaINs the iNterCoNnect lInes. ThE ContACT points of the flip
. Flip chip technology fab ricates bu mps ( typ ica ll y Pb /Snsolder) on Alp adsand interconnects thebumps  d i rect l yto th e packa g em e dia ,wh ich  a r eusual lyceramic  or plasti c b as ed. The flip - ch ip is bond edface down to  th e pack ag e t h rough  th e sho rtestp aths.These tec hn o logies can bea p pl iednot only to singl e -c h ip packaging,but al so to h igh eror integra te d lev e ls of p a ck a g i ngi n which the p ackages are lar ger an dtom ote so phist ic a ted  substrates  tha t accommo date s e veral c h ips toform l arg erfunc t io na l u ni t s.T he  fl i p-c hip tech ni qu e, us inga n a reaarr ay,has t he advantageofachi e vin g the  high estde nsity  of in terco nn ection to the d evic e and a v ery  l owin ducta n ce int erc onn ectionto thep ack ag e . Ho wever, pre-testabi li t y ,post-bon ding v i su al inspecti on , a nd C o e ffici ento fThermalExpans i on  ( CTE) ma tc hing t oavo idsolde r  bum p fati gue arestill challenges. In mounting seve r al p ac k ages  to gether, suc h as surf acem ou nti n g a c erami cp ac k age to a plastic bo ar d, the  CTEmismatch cancause a la r g e  thermal  str e ss on the solderleadjoints tha t  can lea d tojoint br eakage ca u s ed by so lde r f ati gue f ro m temperature c ycli ng  operat ion s.
Prio r A rtsub str at e packagi ng usesce ra mi cand  plas t ic BGA p ac kag in g.Ceram i c subs trate  pac ka gi n g i s expen s iv e andha sprov ento  limi t th e  pe rforman ce of the  ov e rall  p ac kage. R ecent years h av e seen the  e mer genceo f  plastic  BGA packaging, this pa c kaginghas  beco me t he main s tre am des ign and is  frequ ently  u sed i n hig h vo lum eBGA packag e fab ricat io n. T he plas tic substrate BGAp ack age performssat isfa c t or ily wh e n u se d  fo r low-density fli p-chip IC" "s .  I f the numb e r o fpins em anating  from the ICis high,that is i nexce s s  of  350 pins,  or if t he number of pi n scomin g f rom th eICis le ss tha n  35 0 but  the r eq uiredovera ll  package  size is small, or if t he chi p pow erdissipati oni s h igh (in e xces s of 4 Wat tsper  chip ),t he pl asti c  s tru c turebeco m es compli c at eda n dexpensive.I n mou nting  al arge n umbe r of flip chip pa c kages, the fol lowi n g  as pec t s ar ekey aspects in  th ed e sign ofth e interface s onto w hi c h the  flipchip d ies are m ou n ted:
i nter con nect of t hefl i p-chipco nt a ct poi ntsto  the s urroun d inge l ectrical compone nts
t h e rmalt ran smiss io n betwe e n th e flip-chi p and its e nviron ment  andfirmnes sof the  ov er all packag e  that con tains  the la rg e nu mbe r of f lip- c h ips.Inte rc onn ecting of t he fl ip - chi p co ntact  p oint s to thes urroundi nge lectric al  co m p onents ca n be accompl ish ed by m ounting th e  fli p  c h ip on  the s urface  of a p a cka ge  substr ate o r by inte rconnecti n g t he  fli p-chip t oa fl ex  ci rc uit or any othe r circui t type t h a t cont ain s  the interc on nect lines.The c on t act poi n t s o f the f l ip
. Flip_chip technology_fabricates bumps (typically Pb/Sn_solder) on_Al_pads and_interconnects_the bumps directly_to the package_media, which are usually_ceramic or plastic_based._The flip-chip is bonded face down to the package through the shortest paths. These_technologies_can be_applied_not_only to single-chip packaging, but_also to higher or integrated_levels of_packaging in which the packages are larger and_to_mote sophisticated substrates_that accommodate several chips to form larger functional units.
The_flip-chip technique, using an area array,_has the advantage_of_achieving_the highest density of_interconnection to the device and a_very low inductance interconnection to the_package. However, pre-testability, post-bonding visual inspection, and_Coefficient of Thermal Expansion (CTE) matching_to avoid solder bump fatigue_are still_challenges. In mounting several packages_together, such as_surface mounting_a ceramic package_to a plastic board, the CTE_mismatch can cause_a large thermal stress on the_solder_lead joints that_can_lead_to joint_breakage caused by_solder_fatigue from_temperature_cycling operations.
Prior Art substrate packaging uses_ceramic_and plastic BGA packaging. Ceramic substrate packaging_is expensive and has_proven_to limit the performance_of the overall package. Recent_years have seen the emergence of_plastic BGA_packaging, this_packaging has become the main stream design and is frequently used_in high volume BGA package fabrication._The plastic substrate BGA_package performs_satisfactorily_when used for_low-density_flip-chip IC""s._If the number of pins emanating from_the IC_is high, that is in excess_of 350 pins, or_if_the number of pins coming from_the IC is less than 350_but the required overall package_size_is_small, or if the chip_power dissipation is high (in excess_of 4 Watts_per chip), the plastic structure becomes complicated_and_expensive.
In mounting a large number of_flip_chip packages, the following aspects are_key_aspects_in the design of the_interfaces onto which the flip chip_dies are mounted:
interconnect of the flip-chip contact points to_the surrounding electrical_components
thermal transmission between the flip-chip_and_its_environment and
firmness of the overall package that contains the large_number of_flip-chips.
Interconnecting of the_flip-chip contact points to the surrounding electrical components can be_accomplished by mounting the flip chip on_the surface of a package substrate or by interconnecting the flip-chip_to a flex circuit or any other circuit_type that contains the interconnect lines. The_contact points of the_flip