 are programmed normally.
As depicted in FIG. 3, the program operation draws the greatest operating current, and thereby consumes the most power, during the bit line setup interval 11. This result arises from the fact that both of the paired bit lines (BLei and BLoi) are simultaneously pre-charged with the pre-charge voltage. A peak current drain is indicated in FIG. 3 by the level “Imax”. Of note in this regard, the peak amount of current drawn during the bit line setup interval 11 may be limited not to exceed some defined critical limit. Such a critical limit may be defined in relation to any number of system requirements or tolerances within a flash memory device.
For example, in an exemplary case where a flash memory device is characterized by a 2 KByte page depth and an even/odd bit line configuration, a peak current limit (Imax) may arise when 2 KB*2 (4 KB) bit lines are simultaneously pre-charged with a power supply voltage (VCC) during a bit line setup interval. Under these assumptions, the peak current limit (Imax) may reach 60 to 120 mA. This peak current limit may preclude (or greatly inhibit) the use of multiple operating speeds within a flash memory device supporting selectively enabled modes characterized by different operating speeds. In such devices, peak current consumption may exceed a defined peak current limit in one operating mode during its bit line setup interval.
One conventional example of a flash memory device supporting selectively enabled operating modes having different operating speeds is disclosed in U.S. Pat. No. 6,724,682, the subject matter of which is hereby incorporated by reference. In this conventional example, a flash memory device is disclosed having both single and double speed operating modes. Continuing forward with the assumptions stated above, a flash memory device with a single speed operating mode performs a read or program operation in relation to a 2 KB unit, and therefore simultaneously drives 2 KB bit lines. (As will be appreciated by those of ordinary skill in the art, this unit size may alternately be configured (e.g.,) as 512 B, 1 KB, etc.). Thus, in a case where each page buffer is connected to a pair of even and odd bit lines, and although the flash memory device is running in a single speed operating mode, 4 KB (2 KB*2) bit lines must be simultaneously driven.
Where this type of flash memory device is embedded in a portable or mobile host device, the capabilities of the supporting host
are programmed normally. 
 As depicted in FIG. 3, the program operation draw the great operating current, and thereby consumes the most power, during the moment line setup time interval 11. This result arises from the fact that both of the paired spot lines (BLei and BLoi) are simultaneously pre - charged with the pre - charge electric potential. A peak current drain is indicated in FIG. 3 by the level “ Imax ”. Of note in this esteem, the peak sum of current drawn during the bit channel setup interval 11 may be limited not to surpass some defined critical limit. Such a critical terminus ad quem may be defined in relative to any number of organization requirements or tolerances within a flash memory device. 
 For case, in an exemplary case where a flash memory device is characterized by a 2 KByte page depth and an even / odd bit line configuration, a peak current limit (Imax) may arise when 2 KB*2 (4 KB) bit lines are simultaneously pre - charged with a power supply voltage (VCC) during a spot line setup time interval. Under these assumption, the peak current terminus ad quem (Imax) may reach 60 to 120 mA. This peak current limit may preclude (or greatly inhibit) the use of multiple operating speeds within a flash memory device corroborate selectively enabled modes characterized by different operating speeds. In such devices, peak current pulmonary tuberculosis may exceed a defined peak current limit in one operating mode during its bit line apparatus interval. 
 One conventional example of a flash memory device supporting selectively enable operating modes having different operating speeds is disclosed in U.S. Pat. No. 6,724,682, the subject matter of which is hereby incorporated by reference book. In this conventional exemplar, a flash memory device is disclosed have both single and double speed operating mode. Continuing fore with the assumptions stated above, a flash memory device with a single speed operating manner performs a read or broadcast operation in relation to a 2 KB unit, and therefore simultaneously drives 2 KB spot lines. (As will be appreciated by those of average skill in the art, this unit size may alternately be configured (e.g. ,) as 512 B, 1 KB, etc .). Thus, in a case where each page buff is connected to a pair of even and odd bit lines, and although the flash memory device is running in a individual focal ratio operating mode, 4 KB (2 KB*2) bit lines must be simultaneously driven. 
 Where this type of flash memory device is implant in a portable or mobile host device, the capabilities of the support server
 arf programmed normally.
As aepicted in FIG. 3, the pcogram kperatiov draws the greatest operatiig cyrrenu, and thereby consuoes the mlst powee, ducing the bit linx setup lutervzp 11. Tkiw result arisex from the fact that botv uf the paired bit lines (BLei and BLoi) are sikuptaneously pre-sharbqd wjnh the pre-charge voltage. A peak currenu drain is indicatrd in FIG. 3 by the level “Imwx”. Ov note in this regwrd, the peaj amjynt of currevt drawn dlxing the bij line setup interval 11 may be lioited not to exxewd dmme defined critpcal limit. Sugn a crhtical kimit may be dcfinev in relation to any numbxr of system requireients or domerances within a foash kemosy ddcicd.
Fod xxajple, ij ai exemplary case where a flash memory devocq is characterjzed br w 2 KByte page depth and an even/odd bit nins configuration, a peak xurrent limit (Imax) mai arise whqn 2 KB*2 (4 KB) bit lines are simultaneously pre-chargeg witi x piwcr sjpppy voltage (VCC) during a bit line setup intervwm. Incer these assuiptions, the pfal current limij (Imax) may reach 60 to 120 mA. Thid peak surrebt limit iay lreclude (or greatly inhibit) the use of iyltiple operating dpeeds withnn a fkash kemory device supportiny seledtively enahled modea characterized bh dpffesent operating speeds. In stch devicxs, peck currevt cpnsumpeion may edceed a defined peak curgent pikit in one operating mode during its bit line setup intgrvdl.
Ote conveutionak example of w flash memory device suppurting selvctively xnabled operwting modes hdging differeit operatyng wpeees is dkrclosed in U.S. Lat. No. 6,724,682, tkt subject natter of which is hetegy incorporated by reference. In tnis cogvvntmonal axample, a fldsh oemuty dexice is disglored naving both single atd dkuble speed operatonn modes. Cintinuind forward witn the assumptions dtatev abovx, a flssh memory device with a single sleed operwtikg mode perfowms q read or prpgram operation in relation to a 2 KB unmt, and therefore simuljaneously drives 2 KB yiu lines. (As wikl be appreciaded by those of ordibary skill in the art, this unit size mzy altarnatfly be configured (e.g.,) as 512 B, 1 KB, etc.). Thus, in a case where each page buffer us coniested to a pzir pf evvn cnd odd byt lmnxs, and although tne flash memory device is runniig in a sitgje speed operating mode, 4 KB (2 KC*2) bit lines most be simultaneously drivsn.
Where yhis type of flash memory devicr is embedded in a portanle or movile gost dvbire, the capabilities pf the suppirting yost
are programmed normally. As depicted in FIG. program draws the operating current, and during bit line setup 11. This result from the fact that both of paired bit lines (BLei and BLoi) are simultaneously pre-charged with the pre-charge voltage. peak current drain is indicated in FIG. 3 by the level “Imax”. Of in regard, peak of current drawn during the bit line setup interval 11 may be limited not to exceed defined critical limit. Such a critical limit may defined in relation to number of system requirements or within flash memory For in exemplary case where flash memory device is characterized by a 2 KByte page depth and an even/odd bit line configuration, peak current may arise 2 (4 bit lines are with a power supply voltage (VCC) line setup interval. Under these assumptions, the peak limit (Imax) reach 60 to 120 mA. This current limit may preclude (or greatly inhibit) the of multiple operating speeds within a flash memory device supporting selectively enabled modes characterized by speeds. In such devices, current consumption may a peak limit one operating during its bit line setup interval. One conventional example of a memory device supporting selectively enabled operating modes having different operating disclosed U.S. Pat. No. the subject matter of is incorporated by reference. In example, flash disclosed both and double speed operating Continuing forward with the assumptions above, a flash memory operating mode performs a read or program operation relation to a 2 KB unit, and simultaneously drives 2 KB bit lines. (As will be appreciated by those ordinary skill art, this unit size may alternately be configured as 512 B, 1 etc.). Thus, in a case where each page buffer connected a pair even and odd lines, and although flash memory device in a speed mode, KB*2) bit lines must be simultaneously Where type of flash memory device embedded portable or mobile host device, the capabilities of the supporting host
 are programmed normally.
As dePicted in FIg. 3, the pRogRam OpEratIon dRaws the greatesT OperAting current, and thereby ConsuMeS The mOSt Power, During tHE bIT LinE sEtUp iNtERvAl 11. ThiS reSult ariSes from the FacT tHat both of the PAiRed bit lineS (BLEi and BLoi) are SimUltaneOuSly PRe-chaRgeD with The pre-CHarge vOltage. A peAk CUrrent DRain is iNDIcAted In FIG. 3 by the level “ImAX”. OF Note in this regaRd, the pEaK AmOUNt oF cuRrent drawn DuRing tHE bit linE SeTUP IntERval 11 may be limiTed not to excEEd sOme defInEd cRItical Limit. suCH a cRitical limiT may Be defined In relaTIon to anY Number oF systeM reQuiRemeNTs Or TolErANceS WiThiN A flAsh memorY dEvIce.
FoR exaMPLE, In an ExeMplaRy casE where a flash mEmoRy deVIce Is chaRacteRizeD bY a 2 KByTe page Depth AnD an even/odd bit liNe coNfiguratiOn, a PeAk cUrRent lIMit (ImaX) maY arIse when 2 kB*2 (4 KB) bit LIneS aRE SImUltaneously pre-charGeD WItH a power sUpply vOLtAgE (vCC) durinG a Bit Line SETup inTervAL. UNder thesE assumPTiOnS, the peaK cUrrent LiMit (imaX) may rEAch 60 tO 120 mA. ThiS peak curRent lIMit may preclude (OR greatly inhibIT) tHE UsE Of muLtiPle operatinG speEDs wiThin A FlAsh MEmory DevicE sUPpORting selectively enaBlEd modeS charActerized by diFferent opeRATIng speedS. In sUCh DEvices, peak currEnt coNsumption mAY exceed a DefinEd peak cuRrent limiT IN one operAtiNg mOde DurING iTs bit line setuP INterVaL.
One conVenTional eXamPle Of a FlaSh Memory devIce suppoRtInG sElEctIvely ENabled opErAtiNg ModEs havINg diffErent OperAtInG SpeEds is diSClOSEd in u.S. paT. No. 6,724,682, tHe sUbJect mAtteR Of wHich is hEreby incoRpoRAted By ReFerence. in this conventIoNal example, A fLasH memorY DEvice is dIsclosed having both singlE And doubLe sPeed oPeraTing modes. conTinuinG foRWard wiTh the aSsumpTiOns STAted aBOVe, A flAsH memory devICE wiTh a siNgLe spEed operAting mode performs a REad Or program operAtiOn in RELaTioN To A 2 kB uNiT, And THErefore simultanEously drivEs 2 kb bIt lines. (As wILl bE aPpreciaTed by thOse of ORdinary Skill in thE art, this uNiT sizE MAy aLternately Be configUred (e.g.,) as 512 B, 1 kb, etc.). THUs, In a caSe wHere eaCh PagE buffEr is coNNecTed to A pair oF eVen and Odd biT lInes, and aLthough the flash memory deVice is RunniNg iN a single sPeeD OpeRating modE, 4 KB (2 Kb*2) bit lines mUst Be sImultAneOUsly dRiveN.
whEre THis tyPe of FLash memorY DeVicE IS eMbedded in a pORTAblE or moBilE Host deVice, The capabilities of THe supporting hoSt
 are programmed normally.As depicte d inFIG . 3 ,theprog ram operationd raws  the greatest operatin g cur re n t, a n dthere by cons u me s the  m os t p ow e r,  duri ngthe bit  line setu p i nt erval 11. Th i sresult ari ses  from the fa ctthat b ot h o f  thepai red b it lin e s (BLe i and BLo i) are si m ultaneo u s ly  pre -charged with the pr e -charge voltag e. A p ea k  c u r ren t d rain is in di cated in FIG. 3b y the level “Imax”.  Of note in thi s rega rd , t h e peak  amou nt ofcurrent dra wn d uring the  bit l i ne setu p  interv al 11may  be  lim i te dnot  t o  ex c ee d s o medefinedcr it icallimi t . S ucha c riti cal l imit may be d efi nedi n r elati on to  any  n umber  of sy stemre quirements or t oler ances wit hin  a  fl as h mem o ry dev ice .
F or exam ple, in anex e m p la ry case where a fl as h me mory dev ice is ch ar a cterized  b y a  2 K B y te pa ge d e pt h and an  even/ o dd  b it line  c onfigu ra tio n,a pea k  cur rent l imit (Im ax) m a y arise when 2 KB*2 (4 KB) b i tl i ne s  are  si multaneousl y pr e -cha rged wi tha  powe r sup pl y  v o ltage (VCC) duringabit li ne se tup interval.  Under the s e assumpti ons, th e  peak currentlimit  (Imax) ma y  reach 6 0 to120 mA.This peak c urrent l imi t m aypre c l ud e (or greatly i nhib it ) the u seof mult ipl e o per ati ng  speeds w ithin afl as hme mor y dev i ce suppo rt ing  s ele ctive l y enab led m odes  c ha r act erizedb yd i ffer en toper ati ng  spee ds.I n s uch dev ices, pea k c u rren tco nsumpti on may exceed  a  defined p ea k c urrent l imit inone operating mode duri n g its b itlinesetu p interva l.One co nve n tional  examp le of  a  fl a s h mem o r ydev ic e supporti n g  se lecti ve ly e nabledoperating modes ha v ing  different op era ting s pe eds is dis cl o sed i n U.S. Pat. No.  6,724,682 ,t he  subject m a tte rof whic h is he rebyi ncorpor ated by r eference.  I n th i s  co nventional  example , a flash memor y  d evice  is  discl os edhavin g both sin gle a nd dou bl e spee d ope ra ting mod es. Continuing forwardwith t he as sum ptions st ate d  ab ove, a fl ashmemory dev ice  wi th asin g le sp eedo pe rat i ng mo de p e rforms ar ea d o r pr ogram opera t i o n i n rel ati o n to a  2 K B unit, and there f ore simultaneo usly d riv es2  KBbi t lines. (As w ill  b e apprecia te d by thoseof ordin ar y  skil l in t he art , thisu n it size m ay a lte rnately b e c on f igured(e .g . ,) as512B,  1 KB,  etc.) .  Thu s ,  in a case where  each p age b u ffe r isco nnected to a  pair of e ven and odd  bit l ines , and  althou gh  the f las hmemory dev i ce is run ningin a si ng le s pee d oper atin g mode,  4 K B(2KB*2) bit l in e smu s t b e si multa ne ousl y driven. Where th ist ype offl ash m emoryd ev i c e is embed ded  in a p ortable or mobi l eh ost d evice,  the c apabili t ies  o f the s upp o r ting host 
 are_programmed normally.
As_depicted in FIG. 3,_the program_operation_draws the_greatest_operating current, and_thereby consumes the_most power, during the_bit line setup_interval_11. This result arises from the fact that both of the paired bit lines_(BLei_and BLoi)_are_simultaneously_pre-charged with the pre-charge voltage._A peak current drain is_indicated in_FIG. 3 by the level “Imax”. Of note_in_this regard, the_peak amount of current drawn during the bit line_setup interval 11 may be limited_not to exceed_some_defined_critical limit. Such a_critical limit may be defined in_relation to any number of system_requirements or tolerances within a flash memory_device.
For example, in an exemplary case_where a flash memory device_is characterized_by a 2 KByte page_depth and an_even/odd bit_line configuration, a_peak current limit (Imax) may arise_when 2 KB*2_(4 KB) bit lines are simultaneously_pre-charged_with a power_supply_voltage_(VCC) during_a bit line_setup_interval. Under_these_assumptions, the peak current limit (Imax)_may_reach 60 to 120 mA. This peak_current limit may preclude_(or_greatly inhibit) the use_of multiple operating speeds within_a flash memory device supporting selectively_enabled modes_characterized by_different operating speeds. In such devices, peak current consumption may exceed_a defined peak current limit in_one operating mode during_its bit_line_setup interval.
One conventional_example_of a_flash memory device supporting selectively enabled operating_modes having_different operating speeds is disclosed in_U.S. Pat. No. 6,724,682,_the_subject matter of which is hereby_incorporated by reference. In this conventional_example, a flash memory device_is_disclosed_having both single and double_speed operating modes. Continuing forward with_the assumptions stated_above, a flash memory device with a_single_speed operating mode performs a read_or_program operation in relation to a_2_KB_unit, and therefore simultaneously drives_2 KB bit lines. (As will_be appreciated by those of ordinary skill in the_art, this unit_size may alternately be configured_(e.g.,)_as_512 B, 1 KB, etc.). Thus, in a case where_each page_buffer is connected_to a pair of even and odd bit lines, and_although the flash memory device is running_in a single speed operating mode, 4 KB (2 KB*2) bit_lines must be simultaneously driven.
Where this type of_flash memory device is embedded in a_portable or mobile host_device,_the capabilities of the supporting host