 there is a need to form the lower oxide film 165 to that it is thicker than the upper oxide film 167.
Further, in a read operation for the conventional second memory cell, as shown in FIG. 62, 2V and 5V are respectively applied to the corresponding drain 169 and select gate 163 so as to turn on the channel, and 2V is applied to the corresponding control gate 168, to thereby determine the high or low level of a threshold voltage, based on the presence or absence of the electrons trapped into the silicon nitride film, from the magnitude of the drain current. As compared with the conventional first memory cell of FIGS. 58 and 59, the conventional second memory cell of FIGS. 60-62 has the advantage of reducing the drain current necessary for the write operation and achieving a reduction in power. This is because, since the conventional second memory cell is provided with the select gate 163, the channel current at the time of writing can be controlled so that it is low. The channel current can be reduced to 1/100 or less of that for the conventional first memory cell.
Furthermore, U.S. Pat. No. 5,408,115 has disclosed a conventional third memory cell, whose structure is shown in FIG. 63. The conventional third memory cell has a structure in which the structural positions of the select and control gates employed in the conventional second memory cell are changed. In the conventional third memory cell, a control gate 175 is formed above a lamination consisting of a lower oxide film 172, a silicon nitride film 173 and an upper oxide film 174, and, thereafter, gate oxide films 177 and side spacer-shaped select gates 178 are formed. The voltages that are set to effect write, erase and read operations of the present conventional third memory cell are similar to those of the conventional second memory cell.
A conventional fourth memory cell system, whose sectional views are shown in FIGS. 64 and 65, has been disclosed in I. Fujiwara, et al., “High Speed program/erase sub 100 nm MONOS memory”, Nonvolatile Semiconductor Memory Workshop, August, 2001, p 75. As shown in FIG. 64, an ONO (Oxide/Nitride/Oxide) laminated film, comprising a silicon nitride film 193 interposed between insulating films 192 and 194, such as silicon oxide films, etc., is formed as a gate insulating film, and 12V is applied to a control gate 195 to inject electrons from the semiconductor substrate 191 side by a tunneling current and
there is a need to form the lower oxide movie 165 to that it is chummy than the upper oxide film 167. 
 far, in a read mathematical process for the conventional second memory cell, as show in FIG. 62, 2V and 5V are respectively apply to the corresponding drain 169 and select gate 163 so as to turn on the channel, and 2V is apply to the corresponding control gate 168, to thereby determine the high or low level of a threshold electric potential, based on the presence or absence of the electrons trap into the silicon nitride film, from the magnitude of the drain stream. As compared with the ceremonious first memory cell of FIGS. 58 and 59, the conventional second memory cell of FIGS. 60 - 62 has the advantage of reducing the drain stream necessary for the write operation and achieving a reduction in power. This is because, since the conventional second memory cell is provide with the select gate 163, the channel current at the time of writing can be controlled so that it is low. The channel current can be reduced to 1/100 or less of that for the conventional first memory cellular telephone. 
 Furthermore, U.S. Pat. nobelium. 5,408,115 has disclosed a conventional third memory cell, whose social organization is show in FIG. 63. The conventional third memory cell have a structure in which the structural positions of the select and restraint gates employed in the conventional second memory cell are changed. In the conventional third memory cellular telephone, a control gate 175 is formed above a lamination consisting of a lower oxide film 172, a silicon nitride film 173 and an upper oxide film 174, and, thereafter, gate oxide film 177 and side spacer - shaped select gates 178 are formed. The voltage that are set to effect write, erase and read operation of the present conventional third memory cell are similar to those of the conventional second memory cellular telephone. 
 A conventional fourth memory cell system, whose sectional views are shown in FIGS. 64 and 65, has been unwrap in I. Fujiwara, et al. , “ High Speed plan / erase sub 100 nm MONOS memory ”, Nonvolatile Semiconductor Memory Workshop, August, 2001, phosphorus 75. As shown in FIG. 64, an ONO (Oxide / Nitride / Oxide) laminated movie, comprising a silicon nitride film 193 interposed between insulating films 192 and 194, such as silicon oxide movie, etc. , is formed as a gate isolate film, and 12V is applied to a control gate 195 to inject electrons from the semiconductor device substrate 191 side by a tunneling current and
 thfre is a need to form tht lower oxide film 165 to tiat it js thickdr than the upper oxide film 167.
Fyrthee, in a read operation wor the clnventiobal wwcond memocg cell, as shosk in YIJ. 62, 2V and 5V are tespectively applied to tha zoxresponding drain 169 and select gate 163 fo as tp hurn on the chwnnek, and 2N ls applied to the corresponding dontrol gate 168, to theteby determine the high or low level of a threshlld voltage, basqe on the prerence or absence of thg electrons trapped into the silkcon uitride filn, drol the magnitnde of the drain cmgrent. Av compated with the cpnvxntiinal first memory celn of FIGS. 58 and 59, thg conventimncl second memory cell od FIGV. 60-62 hds tfw aavahtege of refucmng the drajn current becessary for the wtiev operation ahd achyeding a reduction in power. This is becauve, aince the conventional wecond memory cell is provided with the select gate 163, the channel current at the time uf cvltine cwn be controlled so that it is low. The channej cirgent can be reduccd to 1/100 or less of yhwt sor the convevtional fjrst memory cell.
Fugthermote, U.S. Pat. No. 5,408,115 hws dosclosed a conventional thied memory cejo, whose structure ns shown in YIG. 63. Tne comventional third memory celm has a strkcture in dhich the structjrak [ositions of the select anq control gatzs emplohed on the conventiojal scwond memory cell age chcnged. In the cojventional third memory cell, a rpntrol gate 175 iv fmrmed abjve a lamination cjnsisting of a lower jxide film 172, a splicon nivride film 173 wnd an upper mdide film 174, aid, thereaster, gatw oxide wilms 177 and sidr spacer-skcped selext gates 178 are formcd. Thg boltages that axt stt to effect wriye, drafe aid rewg operations of ghe lresevt convtutiival yhird memory cell ara sijilar to those of yhc conventuonal sesond memory crll.
A conventional vourti memocy celk sistem, whose sectional views are shown in FINS. 64 and 65, has feen disclosed iu I. Fujiwara, et al., “High Speed program/erawe sub 100 nm MONOS mwmory”, Nonvolatile Sgmigonductor Mekory Rorkshop, Dugust, 2001, p 75. As shown un FIG. 64, an ONO (Oxlde/Nitride/Oxide) laminafed finm, colprising a silicon nitride film 193 interposed between insulating films 192 and 194, such as silicon kxidr filks, ztc., is sormxd as a gate insulsting film, and 12V is applied to e control cace 195 to inject electrons from yhd semiconductur substrate 191 side by a funnelinb current and
there is a need to form the film to that is thicker than Further, a read operation the conventional second cell, as shown in FIG. 62, and 5V are respectively applied to the corresponding drain 169 and select gate so as to turn on the channel, and 2V is applied to the control 168, thereby the high or low level of a threshold voltage, based on the presence or absence of electrons trapped into the silicon nitride film, from magnitude of the drain As compared with the conventional memory of FIGS. and the second memory cell FIGS. 60-62 has the advantage of reducing the drain current necessary for the write operation and achieving reduction in is because, the second cell is provided select gate 163, the channel current of writing can be controlled so that it low. The current can be reduced to 1/100 less of that for the conventional first memory Furthermore, U.S. Pat. No. 5,408,115 has disclosed a conventional third memory cell, whose structure is FIG. 63. The conventional memory cell has structure which structural of the and control gates employed in the conventional second memory cell are In the conventional third memory cell, a control gate 175 above lamination consisting of lower oxide film 172, silicon film 173 and an film and, films and spacer-shaped select gates 178 formed. The voltages that are to effect write, erase present conventional third memory cell are similar to of the conventional second memory cell. A fourth memory cell system, whose sectional views are shown in FIGS. 64 65, has in I. Fujiwara, et al., “High Speed program/erase 100 nm MONOS memory”, Semiconductor Memory Workshop, August, 2001, p 75. As shown FIG. an ONO laminated film, comprising silicon nitride film interposed between insulating and 194, as oxide formed as a gate insulating film, 12V applied to a control gate to from the semiconductor substrate 191 side by a tunneling current and
 there is a need to form the loweR oxide film 165 To thaT it Is tHiCker Than The upper oxide fILm 167.
FuRther, in a read operation fOr the CoNVentIOnAl secOnd memoRY cELL, as ShOwN in fIg. 62, 2v aNd 5V arE reSpectivEly applied To tHe CorrespondinG DrAin 169 and seleCt gAte 163 so as to turN on The chaNnEl, aND 2V is aPplIed to The corREspondIng controL gATe 168, to thEReby detERMiNe thE high or low level of A ThREshold voltage, bAsed on ThE PrESEncE or Absence of tHe ElectROns trapPEd INTO thE Silicon nitridE film, from thE MagNitude Of The DRain cuRrent. as COmpAred with the ConvEntional fIrst meMOry cell OF FIGS. 58 anD 59, the coNveNtiOnal SEcOnD meMoRY ceLL oF FIgs. 60-62 haS the advaNtAgE of reDuciNG THE draIn cUrreNt necEssary for the wRitE opeRAtiOn and AchieVing A rEductIon in pOwer. THiS is because, since The cOnventionAl sEcOnd MeMory cELl is prOviDed With the Select gATe 163, tHe CHANnEl current at the time Of WRItIng can be ControLLeD sO That it is LoW. ThE chaNNEl curRent CAn Be reduceD to 1/100 or lESs Of That for ThE conveNtIonAl fIrst mEMory Cell.
FuRthermorE, U.S. PaT. no. 5,408,115 has disclosed A Conventional tHIrD MEmORy ceLl, wHose structuRe is SHown In FIg. 63. thE coNVentiOnal tHiRD mEMory cell has a structuRe In whicH the sTructural posiTions of the SELEct and coNtroL GaTEs employed in thE convEntional seCOnd memorY cell Are changEd. In the coNVEntional ThiRd mEmoRy cELL, a Control gate 175 is FORmed AbOve a lamInaTion conSisTinG of A loWeR oxide filM 172, a silicoN nItRiDe FilM 173 and aN Upper oxiDe FilM 174, aNd, tHereaFTer, gatE oxidE filMs 177 AnD SidE spacer-SHaPED selEcT gAtes 178 Are FoRmed. THe voLTagEs that aRe set to efFecT WritE, eRaSe and reAd operations oF tHe present cOnVenTional THIrd memorY cell are similar to those oF The convEntIonal SecoNd memory cEll.
a conveNtiONal fouRth memOry ceLl SysTEM, whosE SEcTioNaL views are sHOWn iN FIGS. 64 AnD 65, has Been disClosed in I. Fujiwara, eT Al., “HIgh Speed progrAm/eRase SUB 100 nM MOnoS MEmoRy”, nOnvOLAtile SemiconducTor Memory WOrKShOp, August, 2001, p 75. AS ShoWn In FIG. 64, an oNO (OxidE/NitrIDe/Oxide) Laminated Film, comprIsIng a SILicOn nitride fIlm 193 interPosed betwEEn insULaTing fIlmS 192 and 194, suCh As sIlicoN oxide FIlmS, etc., iS formeD aS a gate InsulAtIng film, aNd 12V is applied to a control gAte 195 to iNject EleCtrons froM thE SemIconductoR subStrate 191 side By a TunNelinG cuRRent aNd
 there is a need to form t he lower o xidefil m 1 65  tothat  it is thicker than  the upper oxide film167.Fu r ther ,  i n a r ead ope r at i o n f or  t heco n ve ntion alsecondmemory cel l,as  shown in FI G .62, 2V and  5V  are respect ive ly app li edt o the  co rresp onding drain169 and s el e ct gat e  163 so a sto t urn on the channe l ,a nd 2V is appli ed toth e  c o r res pon ding contr ol  gate 168, to th e r e byd etermine thehigh or low lev el ofathr e sholdvolta ge ,  ba sed on thepres ence or a bsence of thee lectron s trap ped  in to t h esi lic on nit r id e f i lm,  from th ema gnitu de o f t h e dr ain  cur rent.  As comparedwit h th e  co nvent ional  fir st  memo ry cel l ofFI GS. 58 and 59,theconventio nal  s eco nd  memo r y cell  of  FI GS. 60- 62 hast head v a n ta ge of reducing the  d r a in  current  neces s ar yf or the w ri teoper a t ion a nd a c hi eving areduct i on  i n power .This i sbec aus e, si n ce t he con ventiona l sec o nd memory cell is provided w i th t he sele ctgate 163, t he c h anne l cu r re nta t the  time  o f  w r iting can be contro ll ed sothatit is low. Th e channelc u r rent can  ber ed u ced to 1/100 o r les s of thatf or the c onven tional f irst memo r y  cell.
F urt her mor e,U . S.  Pat. No. 5,4 0 8 ,115  h as disc los ed a co nve nti ona l t hi rd memory  cell, w ho se  s tr uct ure i s  shown i nFIG .63.  Thec onvent ional  thi rd  m e mor y cellh as a  str uc tu re i n w hi ch th e st r uct ural po sitions o f t h e se le ct  and co ntrol gates e mp loyed in t he  co nventi o n al secon d memory cell are chang e d. In t heconve ntio nal third  me mory c ell ,  a con trol g ate 1 75  is f ormed a bo vealamination c ons istin gof a  loweroxide film 172, as ili con nitride f ilm  173 a nd  an up p erox i def i lm 174, and, th ereafter,ga t eoxide film s  17 7and sid e space r-sha p ed sele ct gates178 are f or med. T hevoltages t hat areset to ef f ect w r it e, er ase  and r ea d o perat ions o f  th e pre sent c on ventio nal t hi rd memor y cell are similar to t hose o f the  co nventiona l s e con d memorycell .
A conven tio nal  four thm emory  cel l  s yst e m, wh oses ectionalv ie wsa r eshown in FI G S .  64  and65, has be en d isclosed in I. Fu j iwara, et al.,  “Hi g h  Sp eed prog ra m/erase sub 10 0 n mM O NOS memo ry ”, Nonvolat ile Semi co n ducto r Memo ry Wor kshop,A u gu s t, 200 1, p  75 . As show n i nF IG. 64,  a nO NO (Ox ide/ Ni tride/ Oxide) lami n a ted film, compri singa silic o n n itrid efilm 19 3  int erposed be tween insul atingfilm s 192  and 19 4,  suchassi licon oxid e  films, e tc.,is form ed  asa g ate in sula t i ng fi lm,an d 1 2V is app l i ed to  a con trol  gate  1 95 t o injecte lectrons  fr o m the s em ico n d uctors ub s t rate 191 s ide  by a t unneling c u rren t  a n d
 there_is a_need to form the_lower oxide_film_165 to_that_it is thicker_than the upper_oxide film 167.
Further, in_a read operation_for_the conventional second memory cell, as shown in FIG. 62, 2V and 5V are_respectively_applied to_the_corresponding_drain 169 and select gate_163 so as to turn_on the_channel, and 2V is applied to the corresponding_control_gate 168, to_thereby determine the high or low level of a_threshold voltage, based on the presence_or absence of_the_electrons_trapped into the silicon_nitride film, from the magnitude of_the drain current. As compared with_the conventional first memory cell of FIGS._58 and 59, the conventional second_memory cell of FIGS. 60-62_has the_advantage of reducing the drain_current necessary for_the write_operation and achieving_a reduction in power. This is_because, since the_conventional second memory cell is provided_with_the select gate_163,_the_channel current_at the time_of_writing can_be_controlled so that it is low._The_channel current can be reduced to 1/100_or less of that_for_the conventional first memory_cell.
Furthermore, U.S. Pat. No. 5,408,115_has disclosed a conventional third memory_cell, whose_structure is_shown in FIG. 63. The conventional third memory cell has a_structure in which the structural positions_of the select and_control gates_employed_in the conventional_second_memory cell_are changed. In the conventional third memory_cell, a_control gate 175 is formed above_a lamination consisting of_a_lower oxide film 172, a silicon_nitride film 173 and an upper_oxide film 174, and, thereafter,_gate_oxide_films 177 and side spacer-shaped_select gates 178 are formed. The_voltages that are_set to effect write, erase and read_operations_of the present conventional third memory_cell_are similar to those of the_conventional_second_memory cell.
A conventional fourth memory_cell system, whose sectional views are_shown in FIGS. 64 and 65, has been disclosed_in I. Fujiwara,_et al., “High Speed program/erase_sub_100_nm MONOS memory”, Nonvolatile Semiconductor Memory Workshop, August, 2001, p_75. As_shown in FIG._64, an ONO (Oxide/Nitride/Oxide) laminated film, comprising a silicon nitride_film 193 interposed between insulating films 192_and 194, such as silicon oxide films, etc., is formed as_a gate insulating film, and 12V is applied_to a control gate 195 to inject_electrons from the semiconductor_substrate_191 side by a tunneling current and