 binary decision diagrams are required to be built, called “sink” nodes, is identified. Examples of sink nodes include the output node or nodes in an equivalence checking or a false-paths analysis context. Examples of sink nodes also include targets in a property-checking or model-checking context.
Techniques for reducing the size of a design representation have become critical in numerous applications. Logic synthesis optimization techniques are employed to attempt to render smaller designs to enhance chip fabrication processes. Numerous techniques have been proposed for reducing the size of a structural design representation. For example, redundancy removal techniques attempt to identify gates in the design which have the same function, and merge one onto the other. Such techniques tend to rely upon binary decision diagram-based or Boolean satisfiability-based analysis to prove redundancy, which tend to be computationally expensive. Further, the prior art performs poorly with respect to synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables.
What is needed is a method improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables. This application claims priority from Korean Priority Document No. 99-41976, filed on Sep. 30, 1999 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
The present invention relates to semiconductor integrated circuit devices, and more particularly to a sense amplifier circuit of a semiconductor memory device.
A conventional sense amplifier circuit used by a semiconductor memory device is illustrated in FIG. 1. The memory device includes a data line DL connected to a power supply voltage through a PMOS transistor MP2, an NMOS transistor MN2 which is switched by a column select signal Ysel, and a bit line BL connected to the data line DL through the NMOS transistor MN2. Between the bit line BL and the ground, only one memory cell transistor MC is depicted. However, it is obvious to ones skilled in the art that more memory cell transistors (not shown) can be connected therebetween.
The conventional sense amplifier includes a current mirror type differential amplifier 10, and a dummy data line DDL symmetrical to the data line DL. The dummy data line DDL is connected to a power supply voltage through a PMOS transistor MP1. It includes an on-state NMOS transistor MN1, a dummy bit line DBL coupled to the dummy data line DDL through an NMOS transistor MN1, and a dummy memory cell, which consists of dummy memory cell transistors DMC1 and DMC2 connected in series between
binary decision diagrams are required to be built, call “ sinkhole ” nodes, is identified. Examples of cesspool nodes include the output signal lymph node or nodes in an equivalence checking or a false - paths psychoanalysis context. Examples of sink nodes also admit targets in a property - checking or exemplar - checking context. 
 Techniques for reduce the size of a design representation have become critical in numerous application. Logic synthesis optimization techniques are employed to attempt to supply smaller designs to enhance chip fabrication processes. Numerous technique have been proposed for reducing the size of a structural design representation. For example, redundancy removal techniques attempt to identify gates in the design which have the same function, and merge one onto the other. Such techniques tend to trust upon binary decisiveness diagram - based or Boolean satisfiability - based analysis to rise redundancy, which tend to be computationally expensive. Further, the prior art perform poorly with respect to synthesis of binary decision diagram with inverted edges and quantifiable as well as nonquantifiable variables. 
 What is needed is a method improved synthesis of binary decision diagrams with inverted edges and quantifiable equally well as nonquantifiable variables. This lotion claims priority from Korean Priority Document No. 99 - 41976, filed on Sep. 30, 1999 with the Korean Industrial Property Office, which document is hereby incorporated by character. 
 The present invention relates to semiconductor integrated circuit devices, and more particularly to a sense amplifier circuit of a semiconductor device memory device. 
 A conventional sense amplifier circuit used by a semiconductor memory device is exemplify in FIG. 1. The memory device includes a datum line DL connected to a power supply electric potential through a PMOS transistor MP2, an NMOS transistor MN2 which is switched by a column select signal Ysel, and a bit tune BL connected to the datum line DL through the NMOS transistor MN2. Between the bit line BL and the reason, only one memory cell transistor MC is depicted. However, it is obvious to ones skilled in the art that more memory cellular telephone transistors (not shown) can be connect therebetween. 
 The conventional sense amplifier includes a current mirror type differential amplifier 10, and a dummy data line DDL symmetrical to the datum line DL. The dummy data line DDL is connected to a power supply voltage through a PMOS transistor MP1. It includes an on - department of state NMOS transistor MN1, a dummy snatch line DBL coupled to the dummy data line DDL through an NMOS transistor MN1, and a dummy memory cell, which consists of dummy memory cellular telephone transistors DMC1 and DMC2 connected in series between
 bijary decision diagrams ave required to bg vuilt, ralled “aink” nodds, is identified. Examples of sunk nides include the outpug node or nodes ib an wquivalencx checkiky or z falvx-paths analysis context. Efamples of sinn vobes also include targets in a properey-checkonh or model-cheching sontsqt.
Uechniques for reducing the size kf a devign represenyation have become criticap in numerous applicatlons. Logic wyntrwsis optimizxtion techniques are ejployed to attempt to render smxller designs ti wnhwtce chip fauricatpon processes. Numerouv technoques have beek pro'osee for reducing the sive of a structural dgsign repraszntation. For example, eeeundatcy semoxql gecgnmquss attfmpv to identiry gates in the design which hsvq the same fundtion, wnq merge one onto the other. Such techniqles fend to rely upon binart decision diagram-basgd or Boolqan satisfiability-based analysis to prove redundatcy, wiizh uekq ro be computationally expensive. Further, the prijd srn performs poorly with respevt tp synthesis of binarv dscision diagrams wlth invgrted wdges and quamtifiable as well as nonquabtifiable vagiaboes.
What is needed ns a method nmprovgd synyhesis of binary decisiun djagrams witj invertes edges and quantkfisbne as well as nonquantifiafle variaules. Chis appuicajion clwims priorlty fvmm Korean Priority Doculett No. 99-41976, filfd on Sep. 30, 1999 with the Korean Indnxtrial Propetty Ofxice, whieh docmment is hereby incorporated yy referznce.
Thd present pnvention relates to semiconductos integrated rircuit dqvicws, abd more oarticularly tp a sense amplifier circuit of a semigonduzfor memory deviet.
A xonventional semse am[lpfixr ciwwuit used by a sdmizpnducgor memory bexice is illustrated in FHG. 1. Fhe memory device ongludes a eata linq DL connectec to a power supplj volvage tirough a KMOS transistor MP2, an NMOS tranaistor MN2 whlch is switchqd bn a solumn selzct signal Ysel, and a bit line BL connecved to the data line DL through the NMOS ttanxistor MN2. Bxtween the bit nine BL and the groubd, only one memorn cell transistor MC ia depiwted. Jowever, it is obvious to ones skilled in the art that more memory cell trqnsistors (not showh) cam be bonuecced thewebevwxen.
The conventionsl sense amplifier includes a cnrrent mirsox type differential amplifier 10, xnd a dummy dxta line DDL symmetrical to the cata line DL. The dummy data linr DDL is connected to a iower supply vkltage thruugh a PMOS transixtor M'1. It ibcludes an ln-state NMOS gramslstor MN1, a dumky bit line DBL coupled to the dumny datq pine DDL through an NMOS trwksistot MN1, and a dummy memory dell, ahich consists of cummy memory crll transistors DMC1 dnq DMC2 connectee in series bgtween
binary decision diagrams are required to be “sink” is identified. of sink nodes nodes an equivalence checking a false-paths analysis Examples of sink nodes also include in a property-checking or model-checking context. Techniques for reducing the size of a representation have become critical in numerous applications. Logic synthesis optimization techniques are employed attempt render designs enhance chip fabrication processes. Numerous techniques have been proposed for reducing the size of a structural representation. For example, redundancy removal techniques attempt to gates in the design have the same function, and one the other. techniques to upon binary decision or Boolean satisfiability-based analysis to prove redundancy, which tend to be computationally expensive. Further, the prior art poorly with synthesis of decision with edges and quantifiable as nonquantifiable variables. What is needed improved synthesis of binary decision diagrams with inverted and quantifiable well as nonquantifiable variables. This application priority from Korean Priority Document No. 99-41976, filed Sep. 30, 1999 with the Korean Industrial Property Office, which document is hereby incorporated by present invention relates to integrated circuit devices, more to sense circuit of semiconductor memory device. A conventional sense amplifier circuit used by a memory device is illustrated in FIG. 1. The memory device data DL connected to power supply voltage through PMOS MP2, an NMOS transistor is by signal and bit line BL connected the data line DL through NMOS transistor MN2. Between the ground, only one memory cell transistor MC depicted. However, it is obvious to ones in the art that more memory cell transistors (not shown) can be therebetween. The amplifier includes a current mirror type differential amplifier and a dummy data DDL symmetrical to the data line DL. The dummy line is connected a power supply through a PMOS MP1. It includes NMOS transistor a bit to the dummy data line DDL an transistor MN1, and a dummy cell, of dummy memory cell transistors DMC1 and DMC2 connected in series between
 binary decision diagrams are Required to Be buiLt, cAllEd “Sink” NodeS, is identified. EXAmplEs of sink nodes include thE outpUt NOde oR NoDes in An equivALeNCE chEcKiNg oR a FAlSe-patHs aNalysis Context. ExaMplEs Of sink nodes aLSo Include tarGetS in a property-CheCking oR mOdeL-CheckIng ConteXt.
TechNIques fOr reducinG tHE size oF A design REPrEsenTation have become cRItICal in numerous aPplicaTiONs. lOGic SynThesis optiMiZatioN TechniqUEs ARE EmpLOyed to attempt To render smaLLer DesignS tO enHAnce chIp fabRiCAtiOn processes. numeRous technIques hAVe been pROposed fOr reduCinG thE sizE Of A sTruCtURal DEsIgn REprEsentatiOn. foR examPle, rEDUNDancY reMovaL techNiques attempt To iDentIFy gAtes iN the dEsigN wHich hAve the Same fUnCtion, and merge onE ontO the other. sucH tEchNiQues tENd to reLy uPon Binary dEcision DIagRaM-BASeD or Boolean satisfiaBiLITy-Based anaLysis tO PrOvE RedundanCy, WhiCh teND To be cOmpuTAtIonally eXpensiVE. FUrTher, the PrIor art PeRfoRms PoorlY With RespecT to synthEsis oF Binary decision DIagrams with inVErTED eDGes aNd qUantifiable As weLL as nOnquANtIfiABle vaRiablEs.
wHaT Is needed is a method imPrOved syNthesIs of binary decIsion diagrAMS With inveRted EDgES and quantifiabLe as wEll as nonquANtifiablE variAbles. ThiS applicatION claims pRioRitY frOm KOREaN Priority DocuMENt No. 99-41976, FiLed on SeP. 30, 1999 wiTh the KoReaN InDusTriAl property OFfice, whiCh DoCuMeNt iS hereBY incorpoRaTed By RefErencE.
the preSent iNvenTiOn RElaTes to seMIcONDuctOr InTegrAteD cIrcuiT devICes, And more ParticulaRly TO a seNsE aMplifieR circuit of a seMiConductor mEmOry Device.
a COnventioNal sense amplifier circuiT Used by a SemIcondUctoR memory deVicE is illUstRAted in fIG. 1. The MemorY dEviCE IncluDES a DatA lIne DL conneCTEd tO a powEr SuppLy voltaGe through a PMOS tranSIstOr MP2, an NMOS traNsiStor mn2 WhIch IS sWItcHeD By a COLumn select signaL Ysel, and a bIt LInE BL connectED to ThE data liNe DL thrOugh tHE NMOS trAnsistor Mn2. Between tHe Bit lINE BL And the grouNd, only onE memory ceLL tranSIsTor MC Is dEpicteD. HOweVer, it Is obviOUs tO ones SkilleD iN the arT that MoRe memory Cell transistors (not shown) Can be cOnnecTed TherebetwEen.
tHe cOnventionAl seNse amplifiEr iNclUdes a CurREnt miRror TYpE diFFerenTial AMplifier 10, aND a DumMY DaTa line DDL syMMETriCal to The DAta linE DL. THe dummy data line DDl Is connected to a PoweR SUppLy vOLtagE tHrough a PMOS traNsiStOR mP1. It inclUdEs an on-state nMOS tranSiSTor MN1, A dummy Bit linE DBL couPLEd TO the duMmy dAta Line DDL thRouGh AN NMOS trAnSiSTor MN1, aNd a dUmMy memoRy cell, WHich CONsists of dummy memOry ceLL TransIStoRs DMC1 AnD DMC2 conNEcteD in series bEtween
 binary decision diagramsare requir ed to  be  bu il t, c alle d “sink” nodes ,  isidentified. Examples o f sin kn odes in clude  the ou t pu t nod eor  no de s  i n anequ ivalenc e checking  or  a  false-paths an alysis con tex t. Examplesofsink n od esa lso i ncl ude t argets in a p roperty-c he c king o r  model- c h ec king  context.
Techniq u es for reducing t he siz eo fa des ign  represent at ion h a ve beco m ec r i tic a l in numerous  applicatio n s.Logicsy nth e sis op timiz at i ontechniquesareemployedto att e mpt tor ender s maller  de sig ns t o  e nh anc ec hip fa bri c ati on proce ss es . Num erou s t e chni que s ha ve be en proposed f orredu c ing  thesizeof a  s truct ural d esign  r epresentation.Forexample,red un dan cy  remo v al tec hni que s attem pt to i d ent if y g at es in the design w hi c h  h ave thesame f u nc ti o n, and m er geoneo n to th e ot h er . Such t echniq u es  t end tore ly upo nbin ary  deci s iondiagra m-basedor Bo o lean satisfiab i lity-based an a ly s i st o pr ove  redundancy , wh i ch t endt obec omput ation al l ye xpensive. Further,th e prio r art  performs poo rly with r e s p ect to s ynth e si s  of binary dec ision  diagramsw ith inve rtededges an d quantif i a ble as w ell  as  no nqu a n ti fiable variab l e s.
W ha t is ne ede d is amet hod  im pro ve d synthes is of bi na ry  d ec isi on di a grams wi th  in ve rte d edg e s andquant ifia bl ea s w ell asn on q u anti fi ab le v ari ab les.This app licatio n claimspri o rity  f ro m Korea n Priority Do cu ment No. 9 9- 419 76, fi l e d on Sep . 30, 1999 with the Kor e an Indu str ial P rope rty Offic e,whichdoc u ment i s here by in co rpo r a ted b y re fer en ce.
The pr e s ent  inve nt ionrelates  to semiconductori nte grated circui t d evic e s ,and mo r e p ar t icu l a rly to a senseamplifierci r cu it of a se m ico nd uctor m emory d evice . 
A conv entionalsense amp li fier c irc uit used b y a semi conductor memor y  d evice  is  illus tr ate d inFIG. 1 .  Th e mem ory de vi ce inc ludes  a  data li ne DL connected to a po wer su pplyvol tage thro ugh a P MOS trans isto r MP2, anNMO S t ransi sto r  MN2whic h  i s s w itche d by a columns el ect s ig nal Ysel, a n d a b it li neB L conn ecte d to the data lin e  DL through th e NM O S  tr ans i stor  M N2. Between th e b it l ine BL a nd  the ground , only o ne memor y cell  trans istor M C is depict ed.How ever, itisob v ious to  o ne s  skill ed i nthe ar t that more m emory cell trans istor s (nots how n) ca nbe conn e cted  therebetw een.
The co nventi onal  sens e ampli fi er inc lud es  a current mirror ty pe di fferent ia l am pli fier 1 0, a n d  a du mmyda taline DDLs y mm e tr ic a l t o th e dat aline  DL. Thed ummy dat a l i ne DDLis  co n n ectedt oa power supp lyvolta g e  through a PMOS tr a nsist or MP1 . It i ncludes anon -stateNMO S transisto r MN1, ad umm ybitline DBL  c oupl ed  to  t he dummy data l ine DDLthrougha n  NMOStra n sist o r MN1,  a nd a dummy m emory  c e ll, whi c h  co nsistso f d umm y m emor y c ellt ransistors DMC1 and DMC2  con necte d  in  seri es be tw een
 binary_decision diagrams_are required to be_built, called_“sink”_nodes, is_identified._Examples of sink_nodes include the_output node or nodes_in an equivalence_checking_or a false-paths analysis context. Examples of sink nodes also include targets in a_property-checking_or model-checking_context.
Techniques_for_reducing the size of a_design representation have become critical_in numerous_applications. Logic synthesis optimization techniques are employed to_attempt_to render smaller_designs to enhance chip fabrication processes. Numerous techniques have_been proposed for reducing the size_of a structural_design_representation._For example, redundancy removal_techniques attempt to identify gates in_the design which have the same_function, and merge one onto the other._Such techniques tend to rely upon_binary decision diagram-based or Boolean_satisfiability-based analysis_to prove redundancy, which tend_to be computationally_expensive. Further,_the prior art_performs poorly with respect to synthesis_of binary decision_diagrams with inverted edges and quantifiable_as_well as nonquantifiable_variables.
What_is_needed is_a method improved_synthesis_of binary_decision_diagrams with inverted edges and quantifiable_as_well as nonquantifiable variables. This application claims_priority from Korean Priority_Document_No. 99-41976, filed on_Sep. 30, 1999 with the_Korean Industrial Property Office, which document_is hereby_incorporated by_reference.
The present invention relates to semiconductor integrated circuit devices, and more_particularly to a sense amplifier circuit_of a semiconductor memory_device.
A conventional_sense_amplifier circuit used_by_a semiconductor_memory device is illustrated in FIG. 1._The memory_device includes a data line DL_connected to a power_supply_voltage through a PMOS transistor MP2,_an NMOS transistor MN2 which is_switched by a column select_signal_Ysel,_and a bit line BL_connected to the data line DL_through the NMOS_transistor MN2. Between the bit line BL_and_the ground, only one memory cell_transistor_MC is depicted. However, it is_obvious_to_ones skilled in the art_that more memory cell transistors (not_shown) can be connected therebetween.
The conventional sense amplifier includes_a current mirror_type differential amplifier 10, and_a_dummy_data line DDL symmetrical to the data line DL. The_dummy data_line DDL is_connected to a power supply voltage through a PMOS transistor_MP1. It includes an on-state NMOS transistor_MN1, a dummy bit line DBL coupled to the dummy data_line DDL through an NMOS transistor MN1, and_a dummy memory cell, which consists of_dummy memory cell transistors_DMC1_and DMC2 connected in series between