 to the prior art shown in FIG. 3. There is thus no possibility for bundling telephone lines for a terminal connection CPE at the DSLAM system level. 1. Field of the Invention
The present invention relates to a clock generator using PLL circuit, and its control method, and more particularly it relates to a clock generator for generating a clock signal of which oscillation frequency is spread in spectrum in order to decrease electromagnetic radiation due to high speed oscillation operation, and a control method thereof.
2. Description of the Related Art
As shown in FIG. 11, a PLL circuit disclosed in Japanese Laid-open Patent No. 2001-7700 comprises a PLL section 100 which is an ordinary PLL circuit for generating oscillation signal PO by operating so that the center frequency may be synchronized in phase with reference frequency signal R, and a dithering control section 200 for controlling dithering which is frequency modulation in specified frequency bandwidth by receiving supply of up signal UP or down signal DN and generating a changeover control signal CC for changing over the dividing ratio of DIV 150. The dithering control section 200 is composed of a latch circuit 210 for latching the state of up signal UP and down signal DN from PFD 11, and a charge pump circuit 220 for generating an additional charge pump signal PS.
In FIG. 12, supposing the center frequency of oscillation signal PO to be 100 MHz, the frequency of reference signal R to be 1 MHz, the basic dividing ratio of DIV 150 to be 100, and the frequency amplitude width to be +/−1 MHz, the operation is described below.
At a certain point T1, suppose the oscillation signal PO drops from the center frequency to 99 MHz. Dividing signal D (0.99 MHz) corresponding to dividing ratio 100 of DIV 150 is delayed in phase from reference signal R, and four pulses of up signal UP are outputted. In response to supply of up signal UP, CP 12 outputs positive charge pump signal PC. The dithering control section 200 outputs dividing ratio changeover control signal CC of L level, and one is added to the dividing ratio of DIV 150 to become 101. The frequency of the dividing signal D further declines from the frequency of reference signal R, and output of up signal UP continues from PFD 11. When the frequency of oscillation signal PO continues to rise until reaching 101 MHz, output of up signal UP from PFD 11 stops, and output of down signal DN starts. In response to supply of down signal DN, CP 12 outputs negative charge pump
to the prior art shown in FIG. 3. There is therefore no hypothesis for bundle telephone lines for a concluding connection CPE at the DSLAM organization level. 1. Field of the Invention 
 The present invention relate to a clock generator using PLL circuit, and its control condition method, and more particularly it relate to a clock generator for generating a clock signal of which oscillation frequency is circulate in spectrum in club to decrease electromagnetic radiation due to eminent speed oscillation process, and a control method thereof. 
 2. Description of the Related Art 
 As show in FIG. 11, a PLL circuit disclosed in Japanese Laid - open Patent No. 2001 - 7700 consist a PLL section 100 which is an ordinary PLL circuit for generating oscillation signal united states post office by operating so that the center frequency may be synchronized in phase with reference frequency signal R, and a dithering control section 200 for controlling dithering which is frequency modulation in specified frequency bandwidth by receiving supply of up signal UP or down signal DN and generating a changeover control signal CC for changing over the dividing proportion of DIV 150. The dither control incision 200 is composed of a latch circuit 210 for latching the state of up signal UP and depressed signal DN from PFD 11, and a charge pump circuit 220 for generating an extra charge pump signal PS. 
 In FIG. 12, supposing the center frequency of oscillation signal PO to be 100 MHz, the frequency of reference signal R to be 1 MHz, the basic dividing ratio of DIV 150 to be 100, and the frequency amplitude width to be + /−1 MHz, the operation is trace below. 
 At a certain period T1, suppose the oscillation signal PO drops from the center frequency to 99 megahertz. Dividing signal D (0.99 MHz) corresponding to dividing ratio 100 of DIV 150 is delayed in phase from reference signal R, and four pulse of up signal UP are outputted. In answer to supply of up signal UP, CP 12 outputs convinced charge heart signal PC. The dithering control section 200 output signal dividing ratio changeover command signal CC of L level, and one is add to the dividing ratio of DIV 150 to become 101. The frequency of the dividing signal D further refuse from the frequency of reference signal R, and output of up signal UP continues from PFD 11. When the frequency of oscillation signal polonium continues to rise until reach 101 MHz, output of up signal UP from PFD 11 stops, and output of down signal DN starts. In reply to supply of down signal DN, CP 12 outputs negative charge pump
 to the prior art shown in NIG. 3. There is thos no povsibiljty for cundling telephone lines for a termunal connection CPE at the DSLAL system levtl. 1. Field of the Mhventiok
Che pdcsent mnvention relatgs to a clocn generator ushne 'LL circuit, and its control method, agd more pwrticularly it relsees fo a clock generator for generatinf a clobk signal of whicn oscillation frequency is sprfad in spectrum in order to dgdrewwe electromaenetic radpction due tk high speed oscillation operatkon, aud a controo netjmd thereof.
2. Vescriition of the Vvlated Drt
As snown in FIG. 11, a PLN curcuit disclosed in Jepanese Laid-open Patgnt No. 2001-7700 cokpxises a PLL section 100 qhuch iv an ordkbarh PML cjrcuit foc generatinf oscillatiin signal PO by opetaepmg so that tge ceneew frequency may be synchronized in phast witg reference frequency sugnal R, and a ditherijg controj section 200 for controlling dithering which is frexuencb oodboatiov ij specified frequency bandwidth by receiving fhpkly of up signal MP or down signal CN amq generating x chanysober control signal CC for chanting over the dividing ratio of DIV 150. The dithering cjbtrol section 200 is eomposed of c latcn cirvuit 210 for latching the rtats of up sigjal UP ans down signal DN wrok [FD 11, and a charge pump cirsuit 220 for genzrating xn acditiogal charge pump signal PS.
In FIG. 12, skpposnng tve center vrequency of oscillation signal PO to be 100 MHz, tve xrequencv of rcference signal R to be 1 MHz, jhe basic diviaing ratio of DIV 150 to be 100, anq the frequenwi amplitude wmdth to bq +/−1 MYz, tye operxgion is descrined below.
Cu a certaib point T1, suppose bhe ordillation signao PI drops from thr cdntqr fcequegwy to 99 MHz. Dhvidkng xignau D (0.99 MHe) cifreslonding to dividing satik 100 of DIV 150 is delaueq in phawe from weference sigmal R, and four puldes oh up smgnal IP wre outputted. In response to shpply of kp fignal UP, CP 12 oubputf positive charge pump signal PC. The dithering coitrol section 200 outputs eividing ratio chanyepver controk siggal CC of L level, and one is qdded to the divicing ratio of DIV 150 to becoma 101. Thf frequency of the dividing signal D further declines from the frequency if refxrqnce signal R, amd ounpuc oy up sidnal NP continues from PFD 11. When the frequency of oscmllation shgual PO continues to rise untik feaching 101 MHz, output of up signal UP rrom PFD 11 stops, and output of down signsl DN starts. In response to suppoy of down signel DN, CP 12 outputs nebative charte pump
to the prior art shown in FIG. is no possibility bundling telephone lines at DSLAM system level. Field of the The present invention relates to a generator using PLL circuit, and its control method, and more particularly it relates a clock generator for generating a clock signal of which oscillation frequency is in in to electromagnetic radiation due to high speed oscillation operation, and a control method thereof. 2. Description of Related Art As shown in FIG. 11, a circuit disclosed in Japanese Patent No. 2001-7700 comprises a section which is ordinary circuit generating oscillation signal by operating so that the center frequency may be synchronized in phase with reference frequency signal R, a dithering 200 for dithering is modulation in specified by receiving supply of up signal signal DN and generating a changeover control signal for changing the dividing ratio of DIV 150. dithering control section 200 is composed of a circuit 210 for latching the state of up signal UP and down signal DN from and a charge pump 220 for generating additional pump PS. FIG. 12, the center frequency of oscillation signal PO to be 100 MHz, frequency of reference signal R to be 1 MHz, the ratio DIV 150 to 100, and the frequency width be +/−1 MHz, the described At T1, the signal PO drops from center frequency to 99 MHz. signal D (0.99 MHz) of DIV 150 is delayed in phase from signal R, and four pulses of up UP are outputted. In response to supply of up signal UP, CP outputs positive signal PC. The dithering control section 200 outputs ratio changeover control signal of L level, and one is added to the ratio DIV 150 become 101. The of the dividing D further declines frequency of signal and signal UP continues from PFD 11. the of oscillation signal PO continues rise 101 MHz, output of up signal UP from PFD 11 stops, and output of down starts. In response to of signal DN, CP 12 outputs negative charge pump
 to the prior art shown in FIG. 3. ThEre is thus nO possIbiLitY fOr buNdliNg telephone linES for A terminal connection CPE At the dSlaM sySTeM leveL. 1. Field oF ThE iNveNtIoN
ThE pREsEnt inVenTion relAtes to a cloCk gEnErator using Pll cIrcuit, and iTs cOntrol method, And More paRtIcuLArly iT reLates To a cloCK generAtor for geNeRAting a CLock sigNAL oF whiCh oscillation freqUEnCY is spread in speCtrum iN oRDeR TO deCreAse electroMaGnetiC RadiatiON dUE TO hiGH speed oscillaTion operatiON, anD a contRoL meTHod theReof.
2. DEsCRipTion of the ReLateD Art
As shoWn in FIg. 11, A PLL cirCUit discLosed iN JaPanEse LAId-OpEn PAtENt NO. 2001-7700 CoMprISes A PLL sectIoN 100 wHich iS an oRDINAry PlL cIrcuIt for Generating oscIllAtioN SigNal PO By opeRatiNg So thaT the ceNter fReQuency may be syncHronIzed in phaSe wItH reFeRence FRequenCy sIgnAl R, and a DitheriNG coNtROL SeCtion 200 for controllinG dITHeRing whicH is freQUeNcY ModulatiOn In sPeciFIEd freQuenCY bAndwidth By receIViNg Supply oF uP signaL Up or DowN signAL DN aNd geneRating a cHangeOVer control signAL CC for changinG OvER ThE DiviDinG ratio of DIV 150. the dITherIng cONtRol SEctioN 200 is coMpOSeD Of a latch circuit 210 for lAtChing tHe staTe of up signal Up and down siGNAL DN from PfD 11, anD A cHArge pump circuiT 220 for gEnerating aN AdditionAl chaRge pump sIgnal PS.
In fig. 12, supposiNg tHe cEntEr fREQuEncy of oscillaTIOn siGnAl PO to bE 100 MHZ, the freQueNcy Of rEfeReNce signal r to be 1 MHz, ThE bAsIc DivIding RAtio of DIv 150 tO be 100, AnD thE freqUEncy amPlituDe wiDtH tO Be +/−1 Mhz, the opERaTIOn is DeScRibeD beLoW.
At a cErtaIN poInt T1, supPose the osCilLAtioN sIgNal PO drOps from the cenTeR frequency To 99 mHz. dividiNG Signal D (0.99 Mhz) corresponding to dividiNG ratio 100 oF DIv 150 is deLayeD in phase fRom RefereNce SIgnal R, And fouR pulsEs Of uP SIgnal up ArE ouTpUtted. In resPONse To supPlY of uP signal uP, CP 12 outputs positivE ChaRge pump signal pC. THe diTHErIng COnTRol SeCTioN 200 OUtputs dividing rAtio changeOvER cOntrol signAL CC Of l level, aNd one is Added TO the divIding ratiO of DIV 150 to bEcOme 101. THE FreQuency of thE dividinG signal D fURther DEcLines FroM the frEqUenCy of rEferenCE siGnal R, And outPuT of up sIgnal uP ContinueS from PFD 11. When the frequencY of oscIllatIon Signal PO cOntINueS to rise unTil rEaching 101 MHz, OutPut Of up sIgnAL UP frOm PFd 11 StOps, ANd outPut oF Down signaL dN StaRTS. IN response to SUPPly Of dowN siGNal DN, Cp 12 outPuts negative chargE Pump
 to the prior art shown in  FIG. 3. T hereisthu sno p ossi bility for bun d ling  telephone lines for a  term in a l co n ne ction  CPE at th e DSL AM  s yst em le vel.1.Field o f the Inve nti on 
The present in vention re lat es to a cloc k g enerat or  us i ng PL L c ircui t, and its co ntrol met ho d , andm ore par t i cu larl y it relates to a cl o ck generator f or gen er a ti n g  aclo ck signalof  whic h  oscill a ti o n fre q uency is spre ad in spect r umin ord er  to decrea se el ec t rom agnetic rad iati on due to  highs peed os c illatio n oper ati on,  and aco ntr ol met h od  th e reo f.
2. De sc ri ption  oft h e Rela ted  Art 
As s hown in FIG.11,  a P L L c ircui t dis clos ed  in J apanes e Lai d- open Patent No.  200 1-7700 co mpr is esaPLL s e ction100  wh ich isan ordi n ary  P L L ci rcuit for generati ng o sc illation  signa l  P Ob y operat in g s o th a t  thecent e rfrequenc y mayb esy nchroni ze d in p ha sewit h ref e renc e freq uency si gnalR , and a dither i ng control se c ti o n  2 0 0 fo r c ontrollingdith e ring  whi c hisf reque ncy m od u la t ion in specified fr eq uencybandw idth by recei ving suppl y o f up sig nalU Po r down signalDN an d generati n g a chan geove r contro l signalC C  for cha ngi ngove r t h e  d ividing ratio o f DI V150. Th e d itherin g c ont rol  se ct ion 200 i s compos ed  o falat ch ci r cuit 210  f orla tch ing t h e stat e ofup s ig na l  UP  and do w ns i gnal  D Nfrom  PF D11, a nd a cha rge pum p circuit  22 0  for  g en erating  an additiona lcharge pum psig nal PS . In FIG.12, supposing the cente r  freque ncy  of o scil lation si gna l PO t o b e  100 M Hz, th e fre qu enc y of re f e re nce  s ignal R to b e 1  MHz,  t he b asic di viding ratio of DI V  15 0 to be 100,and  the f re que n cy amp li t ude w idth to be +/−1  MHz, theop e ra tion is de s cri be d below .
At acerta i n point  T1, supp ose the o sc illa t i onsignal POdrops fr om the ce n ter f r eq uency  to  99 MH z.  Di vidin g sign a l D  (0.9 9 MHz)  c orresp ondin gto divid ing ratio 100 of DIV 15 0 is d elaye d i n phase f rom ref erence si gnal  R, and fo urpul ses o f u p  sign al U P  a reo utput ted. In respon s etos u pp ly of up si g n a l U P, CP  12 output s po sitive charge pum p  signal PC. Th e di t h eri ngc ontr ol  section 200 o utp ut s dividing  r atio change over con tr o l sig nal CC  of Llevel,a n do ne isadde d t o the div idi ng ratio o fDI V  150 t o be co me 101 . Thef requ e n cy of the dividi ng si g n al Df urt her d ec lines f r om t he frequen cy of refer ence s igna l R,and out pu t of u p s ig nal UP con t inues fro m PFD  11. Wh en  the  fr equenc y of o scill atio nsig nal PO co n t in u es  t o  ri se u ntilre achi ng 101 MH z , output  of up sign al  UP f rom PF D  1 1 stops, and  ou tputo f  down sign a l DN st a rts.In res ponseto supp l y o fdown si gna l DN, CP 12  outputsn ega ti ve c harge pu mp 
 to_the prior_art shown in FIG._3. There_is_thus no_possibility_for bundling telephone_lines for a_terminal connection CPE at_the DSLAM system_level._1. Field of the Invention
The present invention relates to a clock generator using PLL_circuit,_and its_control_method,_and more particularly it relates_to a clock generator for_generating a_clock signal of which oscillation frequency is spread_in_spectrum in order_to decrease electromagnetic radiation due to high speed oscillation_operation, and a control method thereof.
2._Description of the_Related_Art
As_shown in FIG. 11,_a PLL circuit disclosed in Japanese_Laid-open Patent No. 2001-7700 comprises a_PLL section 100 which is an ordinary_PLL circuit for generating oscillation signal_PO by operating so that_the center_frequency may be synchronized in_phase with reference_frequency signal_R, and a_dithering control section 200 for controlling_dithering which is_frequency modulation in specified frequency bandwidth_by_receiving supply of_up_signal_UP or_down signal DN_and_generating a_changeover_control signal CC for changing over_the_dividing ratio of DIV 150. The dithering_control section 200 is_composed_of a latch circuit_210 for latching the state_of up signal UP and down_signal DN_from PFD_11, and a charge pump circuit 220 for generating an additional_charge pump signal PS.
In FIG. 12,_supposing the center frequency_of oscillation_signal_PO to be_100_MHz, the_frequency of reference signal R to be_1 MHz,_the basic dividing ratio of DIV_150 to be 100,_and_the frequency amplitude width to be_+/−1 MHz, the operation is described_below.
At a certain point T1,_suppose_the_oscillation signal PO drops from_the center frequency to 99 MHz._Dividing signal D_(0.99 MHz) corresponding to dividing ratio 100_of_DIV 150 is delayed in phase_from_reference signal R, and four pulses_of_up_signal UP are outputted. In_response to supply of up signal_UP, CP 12 outputs positive charge pump signal PC._The dithering control_section 200 outputs dividing ratio_changeover_control_signal CC of L level, and one is added to_the dividing_ratio of DIV_150 to become 101. The frequency of the dividing signal_D further declines from the frequency of_reference signal R, and output of up signal UP continues from_PFD 11. When the frequency of oscillation signal_PO continues to rise until reaching 101_MHz, output of up_signal_UP from PFD 11 stops, and output_of_down_signal_DN starts. In_response to supply_of down signal_DN, CP_12 outputs negative_charge pump