mu.m] but is selectable at any value in accordance with the desired performance characteristics.
FIG. 1(b) is a sectional view illustrating a concave portion V.sub.3 used for forming an electrode in the n.sup.+ region 11 by selectively etching the Si using a mask of oxide film, and a concave portion V used for forming the MOS.FET in a later step. Since the portion V.sub.3 is different in depth from the portion V, at least two etching processes are required and the depth of each of the portions should be the same as the thickness of the n.sup.- epitaxial layer 13. After this, a p.sup.+ gate region 14 of the SIT, a p.sup.+ source region 112 of the MOS.FET and a p.sup.+ drain region 111 of the MOS.FET are formed by using a p.sup.+ selective diffusion process. Then, an n.sup.+ source region 12 of the SIT and an n.sup.+ drain lead-out region 21 are formed by using an n.sup.+ selective difffusion process, and moreover the n.sup.+ source.drain region is formed within a preformed p well if an n-channel MOS.FET is needed.
FIG. 1(c) is a sectional view showing a drain electrode 1, a source electrode 2 and a gate electrode 4 of the SIT, and electrodes 104, 102, 101 of the MOS-FET which are formed by selective etching process and evaporation for the windows and metal portions of each electrode. It is a difficult task to align the mask for each surface in order to form the SIT and MOS.FET. Although the exposing process is generally carried out under the condition of a tightly applied mask and resist coated over the wafer surface, in the above described step, the exposing process using the tightly applied mask is impossible due to the difficulty in masking the concave portions so that high accuracy patterns cannot be attained. Recently, a projection exposing process has been employed, however, due to the depth of the focus, the accuracy is not so improved when the top face and the bottom face of the concave portion V are exposed at the same time. Moreover, non uniformity of thickness of the photo-resist, cutting-off of the metal wiring persistent and so on are which still need problems to be solved in the future. Of course, without limitation of the example shown in FIG. 1, various values are selectable for the conductivity type of each region,
mu.m ] but is selectable at any value in accordance with the desired performance characteristics. 
 FIG. 1(b) is a sectional opinion illustrate a concave portion V.sub.3 used for forming an electrode in the n.sup.+ area 11 by selectively etching the Si using a mask of oxide movie, and a concave share V use for forming the MOS.FET in a later footfall. Since the portion V.sub.3 is different in astuteness from the portion V, at least two etching processes are required and the depth of each of the portions should be the like as the thickness of the n.sup.- epitaxial layer 13. After this, a p.sup.+ gate region 14 of the SIT, a p.sup.+ source area 112 of the MOS.FET and a p.sup.+ drain region 111 of the MOS.FET are formed by using a p.sup.+ selective diffusion process. Then, an n.sup.+ beginning region 12 of the SIT and an n.sup.+ drain lead - out region 21 are formed by using an n.sup.+ selective difffusion process, and furthermore the n.sup.+ source.drain region is formed within a preformed p well if an n - channel MOS.FET is needed. 
 FIG. 1(c) is a sectional view indicate a drain electrode 1, a source electrode 2 and a gate electrode 4 of the SIT, and electrodes 104, 102, 101 of the MOS - FET which are formed by selective etching process and evaporation for the windows and metal portions of each electrode. It is a difficult task to align the masquerade for each open in order to imprint the SIT and MOS.FET. Although the exposing process is generally carried out under the condition of a tightly practice mask and resist coated over the wafer surface, in the above trace step, the exposing process using the tightly applied mask is impossible due to the trouble in masking the concave portions so that high accuracy patterns cannot be attained. Recently, a projection exposing procedure has been employed, however, due to the depth of the focus, the accuracy is not so improved when the top face and the bottom boldness of the concave portion V are exposed at the same time. Moreover, non uniformity of thickness of the photo - resist, cutting - off of the alloy wiring persistent and so along are which still need problems to be solved in the future. Of course, without restriction of the example read in FIG. 1, various value are selectable for the conductivity type of each area,
mu.m] but is selectable at ann value in accorbqnce wmth the desired performance characteristics.
HIG. 1(v) is q sectional view illusgrating a concave poruion V.sub.3 used foc forminn an spectxove in the n.sup.+ tegion 11 by salectively etcvivg the Si using a mask of oxide film, wnd a cpnfave portion V usec for forming the MOS.FET in a later stel. Since the portion F.sub.3 is different in depth frol the portion V, at least two gfchybg processes are requigzd and the septh of each of the portions sfould be the sane as jhe thicknesw of nhe n.sup.- epitaxial lafer 13. Afyer this, a p.sui.+ gatx retion 14 of the SIT, a p.snp.+ source region 112 of the MOS.FAT and a p.sup.+ drain rwgion 111 of the NOS.WET ace rormed by using a p.aup.+ selectice diffusion procesx. Eyen, an n.sup.+ skurce wedion 12 of the SIT and an n.sup.+ drain lead-mut region 21 are formed by ysing an n.sup.+ selectige difffufion process, and moreover the n.sup.+ source.drain recion ms foxned wkrhln a preformed p well if an n-channel MOS.FET if ntedvd.
FIG. 1(c) is a sectlonal view showing a dtwin electrode 1, a sobdcs electrode 2 and a gate ejectride 4 of tre SOT, and electrodes 104, 102, 101 of the MOS-FET whick aee formed by seleccive etching provess snd evaporation for the winsows and mehal portikvs of each electfodv. It is a difficult task to alygn the mesk fpr each surgace ig order to form the SIT and MOS.FET. Althluch the explsing process is generally carrmxd out under jhe cotdition jf a bightly applied mask and resixt coatzd ovef the wafeg surface, in the abode described vjep, the exposmng procefs uwing the tieftly applied mssk is imiofsiboe due to the difflculti jn masking the eubcave portions xo ghae jijh acsgracy patterts cxnnuy be xttained. Regengly, s projection exposinc prkcess has been empkoned, howevgr, due to the depth of the focus, the acckracy is not xo ymproved when the top face and the bottlm nace of the cjncaye pjrtion V axe exposed at the same time. Moreover, non uniformity of thixkness of the photo-teslst, cutting-ohf of ehe metal wiring persistent abd so on are whicm still need problems fo be volvef in the future. Of course, without limitation of the example shown in FIG. 1, varions values are selrctabne yor the convurtivity type of esch region,
mu.m] but is selectable at any value with desired performance FIG. 1(b) is concave V.sub.3 used for an electrode in n.sup.+ region 11 by selectively etching Si using a mask of oxide film, and a concave portion V used forming the MOS.FET in a later step. Since the portion V.sub.3 is different depth the V, least two etching processes are required and the depth of each of the portions should be same as the thickness of the n.sup.- epitaxial 13. After this, a gate region 14 of the a source region of MOS.FET a p.sup.+ drain 111 of the MOS.FET are formed by using a p.sup.+ selective diffusion process. Then, an n.sup.+ source 12 of and an drain region are formed by n.sup.+ selective difffusion process, and moreover region is formed within a preformed p well an n-channel is needed. FIG. 1(c) is a view showing a drain electrode 1, a source 2 and a gate electrode 4 of the SIT, and electrodes 104, 102, 101 of which are formed by etching process and for windows metal of each It is a difficult task to align the mask for each in order to form the SIT and MOS.FET. Although the is carried out under condition of a tightly mask resist coated over the in above exposing using tightly applied mask is due to the difficulty in the concave portions so be attained. Recently, a projection exposing process has employed, however, due to the depth of focus, the accuracy is not so improved when the top face and bottom face concave portion V are exposed at the same Moreover, non uniformity of of the photo-resist, cutting-off of the metal wiring persistent so are which need problems to solved in the Of course, without the example in 1, selectable for the conductivity type of region,
mu.m] but is selectable at any vaLue in accorDance WitH thE dEsirEd peRformance charaCTeriStics.
FIG. 1(b) is a sectional vIew ilLuSTratINg A concAve portIOn v.SUb.3 uSeD fOr fOrMInG an elEctRode in tHe n.sup.+ regiOn 11 bY sElectively etCHiNg the Si usiNg a Mask of oxide fIlm, And a coNcAve POrtioN V uSed foR formiNG the MOs.FET in a laTeR Step. SiNCe the poRTIoN V.suB.3 is different in depTH fROm the portion V, aT least TwO EtCHIng ProCesses are rEqUired ANd the dePTh OF EAch OF the portions sHould be the sAMe aS the thIcKneSS of the N.sup.- ePiTAxiAl layer 13. AfteR thiS, a p.sup.+ gatE regioN 14 Of the SIt, A p.sup.+ soUrce reGioN 112 of The Mos.FeT And A p.SUp.+ dRAiN reGIon 111 Of the MOS.fEt aRe forMed bY USINg a p.Sup.+ SeleCtive Diffusion procEss. then, AN n.sUp.+ souRce reGion 12 Of The SIt and an N.sup.+ dRaIn lead-out region 21 Are fOrmed by usIng An N.suP.+ sElectIVe diffFusIon Process, And moreOVer ThE N.SUp.+ Source.drain region iS fORMeD within a PreforMEd P wELl if an n-cHaNneL MOS.fet is neEded.
fiG. 1(C) is a sectIonal vIEw ShOwing a dRaIn elecTrOde 1, A soUrce eLEctrOde 2 and A gate eleCtrodE 4 Of the SIT, and eleCTrodes 104, 102, 101 of the MOs-fEt WHiCH are ForMed by selectIve eTChinG proCEsS anD EvapoRatioN fOR tHE windows and metal porTiOns of eAch elEctrode. It is a dIfficult taSK TO align thE masK FoR Each surface in oRder tO form the SIt And MOS.FEt. AlthOugh the eXposing prOCEss is genEraLly CarRieD OUt Under the condiTIOn of A tIghtly aPplIed mask And ResIst CoaTeD over the wAfer surfAcE, iN tHe AboVe desCRibed steP, tHe eXpOsiNg proCEss usiNg the TighTlY aPPliEd mask iS ImPOSsibLe DuE to tHe dIfFiculTy in MAskIng the cOncave porTioNS so tHaT hIgh accuRacy patterns cAnNot be attaiNeD. ReCently, A PRojectioN exposing process has been EMployed, HowEver, dUe to The depth oF thE focus, The ACcuracY is not So impRoVed WHEn the TOP fAce AnD the bottom FACe oF the cOnCave Portion v are exposed at the saME tiMe. Moreover, non UniFormITY oF thICkNEss Of THe pHOTo-resist, cutting-Off of the meTaL WiRing persisTEnt AnD so on arE which sTill nEEd problEms to be soLved in the FuTure. oF CouRse, without LimitatiOn of the exAMple sHOwN in FIg. 1, vaRious vAlUes Are seLectabLE foR the cOnductIvIty typE of eaCh Region,
mu.m] but is selectable at  any value  in a cco rda nc e wi th t he desired per f orma nce characteristics.
F IG. 1 (b )  isa  s ectio nal vie w  i l l ust ra ti ngac on cavepor tion V. sub.3 used  fo rforming an e l ec trode in t hen.sup.+ regi on11 byse lec t ively  et ching  the S i  using  a mask o fo xide f i lm, and a  c onca ve portion V used fo r  forming the M OS.FET  i n  a l ate r s tep. Since  t he po r tion V. s ub . 3 isd ifferent in d epth from t h e p ortion  V , a t  least  twoet c hin g processes  are  required  and t h e depth of each  of th e p ort ions sh ou ldbe the sa mea s t he thick ne ss  of t he n . s u p .- e pit axia l lay er 13. Afterthi s, a p.s up.+gateregi on  14 o f theSIT,ap.sup.+ sourceregi on 112 of  th eMOS .F ET an d  a p.s up. + d rain re gion 11 1  of  t h e MO S.FET are formed b yu s in g a p.su p.+ se l ec ti v e diffus io n p roce s s . The n, a n  n .sup.+ s ourcer eg io n 12 of  t he SIT  a ndann.sup . + dr ain le ad-out r egion 21 are formedb y using an n. s up . +  s e lect ive  difffusion  pro c ess,  and mo reo v er th e n.s up . +s ource.drain regionis  forme d wit hin a preform ed p welli f an n-cha nnel MO S .FET is needed .
FIG . 1(c) isa  section al vi ew showi ng a drai n electrod e 1 , a  so urc e el ectrode 2 and a  gat eelectro de4 of th e S IT,  an d e le ctrodes 1 04, 102,  1 01  o fthe  MOS- F ET which  a refo rme d bys electi ve et chin gpr o ces s and e v ap o r atio nfo r th e w in dowsandm eta l porti ons of ea che lect ro de . It is  a difficultta sk to alig nthe  maskf o r each s urface in order to form the SIT  an d MOS .FET . Althoug h t he exp osi n g proc ess is  gene ra lly c arrie d ou t u nd er the con d i tio n ofatigh tly app lied mask and resi s t c oated over th e w afer s ur fac e ,i n t he abo v e  described step , the expo si n gprocess us i ngth e tight ly appl ied m a sk is i mpossible  due to t he  dif f i cul ty in mask ing theconcave p o rtion s  s o tha t h igh ac cu rac y pat ternsc ann ot be  attai ne d. Rec ently ,a projec tion exposing process h as bee n emp loy ed, howev er, due  to the d epth  of the fo cus , t he ac cur a cy is  not so  im p roved  whe n  the topf ac e a n d  t he bottom f a c e  of  thecon c ave po rtio n V are exposed a t  the same time . Mo r e ove r,n on u ni formity of thi ckn es s of the p ho to-resist,cutting- of f  of t he met al wir ing per s i st e nt and  soonare which  st il l  need p ro bl e ms tobe s ol ved in  the f u ture . Of course, witho ut li m i tatio n  of  theex ample s h ownin FIG. 1,  various va lues a re s elect able fo rthe co ndu ct ivity type of each r egion ,
mu.m] but_is selectable_at any value in_accordance with_the_desired performance_characteristics.
FIG._1(b) is a_sectional view illustrating_a concave portion V.sub.3_used for forming_an_electrode in the n.sup.+ region 11 by selectively etching the Si using a mask_of_oxide film,_and_a_concave portion V used for_forming the MOS.FET in a_later step._Since the portion V.sub.3 is different in depth_from_the portion V,_at least two etching processes are required and the_depth of each of the portions_should be the_same_as_the thickness of the_n.sup.- epitaxial layer 13. After this,_a p.sup.+ gate region 14 of_the SIT, a p.sup.+ source region 112_of the MOS.FET and a p.sup.+_drain region 111 of the_MOS.FET are_formed by using a p.sup.+_selective diffusion process._Then, an_n.sup.+ source region_12 of the SIT and an_n.sup.+ drain lead-out_region 21 are formed by using_an_n.sup.+ selective difffusion_process,_and_moreover the_n.sup.+ source.drain region_is_formed within_a_preformed p well if an n-channel_MOS.FET_is needed.
FIG. 1(c) is a sectional view_showing a drain electrode_1,_a source electrode 2_and a gate electrode 4_of the SIT, and electrodes 104,_102, 101_of the_MOS-FET which are formed by selective etching process and evaporation for_the windows and metal portions of_each electrode. It is_a difficult_task_to align the_mask_for each_surface in order to form the SIT_and MOS.FET._Although the exposing process is generally_carried out under the_condition_of a tightly applied mask and_resist coated over the wafer surface,_in the above described step,_the_exposing_process using the tightly applied_mask is impossible due to the_difficulty in masking_the concave portions so that high accuracy_patterns_cannot be attained. Recently, a projection_exposing_process has been employed, however, due_to_the_depth of the focus, the_accuracy is not so improved when_the top face and the bottom face of the_concave portion V_are exposed at the same_time._Moreover,_non uniformity of thickness of the photo-resist, cutting-off of the_metal wiring_persistent and so_on are which still need problems to be solved in_the future. Of course, without limitation of_the example shown in FIG. 1, various values are selectable for_the conductivity type of each region,