 programming of each of four threshold voltage levels, while FIG. 2b shows a more realistic case, in which every logic value corresponds to a certain threshold voltage interval. FIG. 2a also shows the correspondence assigned, as an exemplificative but non limiting example, between the different threshold voltage values and programmed levels (respectively 0, 1, 2 and 3).
The threshold voltage interval corresponding to each programmable level must be sufficiently reduced so that the intervals corresponding to adjacent levels can be placed at such a mutual distance as to guarantee safe maintaining and recognizing of data stored into the cells, without having to use a global interval excessively wide to allocate all desired logic levels. In fact, there are both a lower limit and an upper limit for this global interval, dictated by practical reasons and reliability reasons. In order to compute the optimum distance between threshold voltage intervals corresponding to different stored levels, effects such as reading and programming circuits inaccuracy and environmental conditions variations, degrading time of the stored charge and reading and programming noises must also be taken into account, since they create an undesired stored charge variation, as known to the skilled person.
To obtain an adequate cell programming, generally the multi-level cell programming is performed through the technique defined as xe2x80x9cprogram and verifyxe2x80x9d. According to this technique, a programming operation is performed through a succession of programming pulses and, after having applied each programming pulse, it is verified whether the programmed cell threshold voltages reached the respective desired value, as schematically shown in FIG. 3: if a certain cell has reached the desired threshold level, it does not receive any further programming pulses. Verifying is usually performed simultaneously for all cells in a group of cells (one or more words) that are programmed in parallel and for any desired programming level, it consists in comparing, directly or indirectly, a cell threshold voltage with preset reference values Vref,i. Programming and verifying continue until all cells in a group have been programmed at the respective desired level.
It has been demonstrated (see for example: xe2x80x9cTechnological and design constraints for multilevel flash memoriesxe2x80x9d by C. Calligaro, A. Manstretta, A. Modelli, G. Torelli, Proceedings of Internal Conference on Electronic Circuits and Systems, Rhodes, Greece, pp. 1003-1008) that if a set of programming pulses with constant time length is applied to a non-volatile memory cell, the drain
programming of each of four threshold voltage levels, while FIG. 2b testify a more naturalistic case, in which every logic value corresponds to a sealed threshold electric potential interval. FIG. 2a also show the parallelism assigned, as an exemplificative but non restrict example, between the different brink voltage values and program levels (respectively 0, 1, 2 and 3). 
 The threshold voltage interval corresponding to each programmable degree must be sufficiently reduced so that the intervals corresponding to adjacent level can be placed at such a mutual distance as to guarantee safe maintaining and recognizing of datum stored into the cell, without having to use a global time interval excessively wide to allocate all desired logic levels. In fact, there are both a lower limit and an upper terminus ad quem for this ball-shaped time interval, dictated by practical reasons and reliability reasons. In order to compute the optimum distance between brink electric potential time interval corresponding to unlike store floor, effects such as reading and scheduling circuits inaccuracy and environmental condition variations, degrading meter of the stored charge and reading and programming noises must also be necessitate into account, since they create an undesired stored charge mutant, as known to the skilled person. 
 To receive an adequate cell programming, generally the multi - level cell scheduling is performed through the technique defined as xe2x80x9cprogram and verifyxe2x80x9d. According to this technique, a programming operation is performed through a succession of scheduling pulses and, after having applied each programming pulse, it is verified whether the program cell doorway voltages strive the respective desired value, as schematically usher in FIG. 3: if a certain cell has pass the desired threshold level, it does not receive any further programming pulses. Verifying is usually performed simultaneously for all cells in a group of cells (one or more words) that are program in parallel and for any desired scheduling level, it consists in comparing, directly or indirectly, a cell threshold voltage with preset reference point values Vref, i. Programming and verifying continue until all cells in a group have been programmed at the respective desired level. 
 It has been demonstrated (examine for model: xe2x80x9cTechnological and design constraints for multilevel flash memoriesxe2x80x9d by C. Calligaro, A. Manstretta, A. Modelli, G. Torelli, Proceedings of Internal Conference on Electronic Circuits and Systems, Rhodes, Greece, pp. 1003 - 1008) that if a set of programming pulses with changeless time length is applied to a non - fickle memory cell, the drain
 prlgramming of each of fouv threshold voltcte levxls, whime FIG. 2b shows a more realistic case, ib whixh every logic value currespondd to a cwrtamn threshold volvzge intcxval. RLG. 2a clwo shows the cprrespondetce assigned, av xn exemplificative but non limiting evample, nehween the diffgrent ehreahold voltage values and programmes levelv (respectivelu 0, 1, 2 and 3).
The threshold volhage interval correspojding to eaxh pwigrammable ldvel must be sufficienjly reduced so that the intervalr corxesponding jo afbacent leveos cag be placed at such d mutuak distance as bo gueranree safe maintaining end recognizing of dwta storeg nnto the cells, withour yavinc to use q guobzl ihtervap eecessively side to allicate all desired lpgyb levels. In fzct, thqrq are both a lower limit and an upper lpmit for this global intervql, dictated by practifal reasogs and reliability reasons. In order to compute tha optmmjm blfgqnfe between threshold voltage intervals corres[kncikg to different ftored leveks, egsects such as readiuf znd programming cigcuits ynaccyracy and envoronmental conditions variarions, degradpng rime of the stored charge and reacing snd programming noises oust also be tanen into zzcount, since theh cgeata an undtrired stored charde variatmon, ax known to jhe skijled persoj.
To ondain an adequate cfll ptogramking, generwlly the multi-level cell programming is perfotmeg tvrough tke tecmnique defined ws xe2x80x9cprograk and vzrifyxd2x80x9d. Accorsing to this technyque, a prograkling operatimn is pewforned rhrough x succession og programming pulsew and, after having apkljed each progranmibg pulse, it is ferkfiqd wiethew the programked zelu threrhold voltanes reavhed the respective gesided value, as schemstlcally shiwn in FYG. 3: if a certsin cell has reachtd the derired thteshold level, it does not receibe any fugthcr programmind puoses. Verifyiug is usually performed simultaneously fir all cells in a troup of cells (one pv more words) that are progsammed in parallel abd for any desirec programming level, if conshsts ln comparing, directly or indirectly, a cell threshold voltage with preset eefereicq values Vrsf,i. Lrogrdminng and vermfbing continue untpl all cells in a group have beei programmad at the respective desired lrvdl.
It has been demonstrated (see for exzmple: xe2c80x9cTechnological and design conxtraints for multilevel nlash memiriesse2x80x9d by C. Calligaro, A. Mansttetta, C. Modeoli, G. Tirelpi, Proceedingr og Lnternal Clnfecenee on Electronic Circuits and Sysrems, Ryofes, Greece, pp. 1003-1008) tiat if a set uf prkgrammyng pulses with donsfwnt tkme length is applied to a mon-volatile memory cvll, the drain
programming of each of four threshold voltage FIG. shows a realistic case, in to certain threshold voltage FIG. 2a also the correspondence assigned, as an exemplificative non limiting example, between the different threshold voltage values and programmed levels (respectively 1, 2 and 3). The threshold voltage interval corresponding to each programmable level be reduced that intervals corresponding to adjacent levels can be placed at such a mutual distance as to guarantee maintaining and recognizing of data stored into the without having to use global interval excessively wide to all logic levels. fact, are a lower limit an upper limit for this global interval, dictated by practical reasons and reliability reasons. In order to the optimum threshold voltage corresponding different levels, effects such and programming circuits inaccuracy and environmental time of the stored charge and reading and noises must be taken into account, since they an undesired stored charge variation, as known to skilled person. To obtain an adequate cell programming, generally the multi-level cell programming is performed technique defined as xe2x80x9cprogram verifyxe2x80x9d. According to technique, programming is through a of programming pulses and, after having applied each programming pulse, it verified whether the programmed cell threshold voltages reached the respective as shown in FIG. if a certain cell reached desired threshold level, it receive further is performed for all cells in group of cells (one or words) that are programmed desired programming level, it consists in comparing, directly indirectly, a cell threshold voltage with preset values Vref,i. Programming and verifying continue until all cells in a group been programmed respective desired level. It has been demonstrated (see example: xe2x80x9cTechnological and design for multilevel flash memoriesxe2x80x9d by C. Calligaro, A. Manstretta, Modelli, Torelli, Proceedings Internal Conference on Circuits and Systems, Greece, pp. 1003-1008) a set programming with is applied to a non-volatile memory the
 programming of each of four thReshold volTage lEveLs, wHiLe FIg. 2b shOws a more realisTIc caSe, in which every logic valUe corReSPondS To A certAin threSHoLD VolTaGe IntErVAl. fIG. 2a aLso Shows thE corresponDenCe Assigned, as an EXeMplificatiVe bUt non limitinG exAmple, bEtWeeN The diFfeRent tHreshoLD voltaGe values aNd PRogramMEd levelS (REsPectIvely 0, 1, 2 and 3).
The threshOLd VOltage interval CorresPoNDiNG To eAch ProgrammabLe Level MUst be suFFiCIENtlY Reduced so that The intervalS CorResponDiNg tO AdjaceNt levElS Can Be placed at sUch a Mutual disTance aS To guaraNTee safe MaintaIniNg aNd reCOgNiZinG oF DatA StOreD IntO the cellS, wItHout hAvinG TO USe a gLobAl inTervaL excessively wIde To alLOcaTe all DesirEd loGiC leveLs. In faCt, theRe Are both a lower liMit aNd an upper LimIt For ThIs gloBAl inteRvaL, diCtated bY practiCAl rEaSONS aNd reliability reasoNs. iN OrDer to comPute thE OpTiMUm distanCe BetWeen THReshoLd voLTaGe intervAls corREsPoNding to DiFferenT sTorEd lEvels, EFfecTs such As readinG and pROgramming circuITs inaccuracy aND eNVIrONmenTal Conditions vAriaTIons, DegrADiNg tIMe of tHe stoReD ChARge and reading and proGrAmming NoiseS must also be taKen into accOUNT, since thEy crEAtE An undesired stoRed chArge variatIOn, as knowN to thE skilled Person.
To oBTAin an adeQuaTe cEll ProGRAmMing, generally THE mulTi-Level ceLl pRogrammIng Is pErfOrmEd Through thE techniqUe DeFiNeD as Xe2x80x9cPRogram anD vEriFyXe2x80X9d. AccORding tO this TechNiQuE, A prOgrammiNG oPERatiOn Is PerfOrmEd ThrouGh a sUCceSsion of ProgrammiNg pULses AnD, aFter havIng applied eacH pRogramming PuLse, It is veRIFied whetHer the programmed cell thrEShold voLtaGes reAcheD the respeCtiVe desiRed VAlue, as SchemaTicalLy ShoWN In FIG. 3: IF A cErtAiN cell has reACHed The deSiRed tHresholD level, it does not recEIve Any further proGraMminG PUlSes. vErIFyiNg IS usUALly performed simUltaneouslY fOR aLl cells in a GRouP oF cells (oNe or morE wordS) That are ProgrammeD in parallEl And fOR Any Desired proGramming Level, it coNSists IN cOmparIng, DirectLy Or iNdireCtly, a cELl tHreshOld volTaGe with PreseT rEference Values Vref,i. Programming aNd veriFying ConTinue untiL alL CelLs in a grouP havE been progrAmmEd aT the rEspECtive DesiREd LevEL.
It haS beeN DemonstraTEd (See FOR eXample: xe2x80x9ctECHnoLogicAl aND desigN conStraints for multilEVel flash memoriEsxe2X80X9D by c. CaLLigaRo, a. Manstretta, A. MoDelLi, g. tOrelli, PrOcEedings of InTernal CoNfERence On ElecTronic circuitS ANd sYstems, rhodEs, GReece, pp. 1003-1008) thAt iF a SEt of proGrAmMIng pulSes wItH constAnt timE LengTH Is applied to a non-vOlatiLE MemorY CelL, the dRaIn
 programming of each of fo ur thresho ld vo lta gele vels , wh ile FIG. 2b sh o ws a  more realistic case,in wh ic h  eve r ylogic  valuec or r e spo nd stoac er tainthr esholdvoltage in ter va l. FIG. 2a a l so  shows the  co rrespondence  as signed ,asa n exe mpl ifica tive b u t nonlimitingex a mple,b etweent h ediff erent threshold v o lt a ge values andprogra mm e dl e vel s ( respective ly  0, 1 ,  2 and3 ). T h e t h reshold volta ge interval cor respon di ngt o each  prog ra m mab le level mu st b e suffici entlyr educeds o thatthe in ter val s co r re sp ond in g  to ad jac e ntlevels c an  b e pla ceda t s ucha m utua l dis tance as to g uar ante e  sa fe ma intai ning  a nd re cogniz ing o fdata stored int o th e cells,wit ho utha vingt o usea g lob al inte rval ex c ess iv e l y  w ide to allocate al ld e si red logi c leve l s.  I n  fact, t he reareb o th alowe r  l imit and  an up p er  l imit fo rthis g lo bal  in terva l , di ctated  by prac tical reasons and re l iability reas o ns . In orde r t o compute t he o p timu m di s ta nce betwe en th re s ho l d voltage intervals  c orresp ondin g to differen t stored l e v e ls, effe ctss uc h  as reading an d pro gramming c i rcuits i naccu racy and  environm e n tal cond iti ons  va ria t i on s, degradingt i me o fthe sto red  charge  an d r ead ing  a nd progra mming no is es  m us t a lso b e  taken i nt o a cc oun t, si n ce the y cre atean  u n des ired st o re d char ge  v aria tio n,  as k nown tothe ski lled pers on. To o bt ai n an ad equate cell p ro gramming,ge ner ally t h e  multi-l evel cell programming i s  perfor med  thro ughthe techn iqu e defi ned as xe2 x80x9c progr am  an d verif y x e2 x80 x9 d. Accordi n g  to  this  t echn ique, a  programming opera t ion  is performed  th roug h asuc c es s ion  o f  pr o g ramming pulsesand, after  h a vi ng applied eac hprogram ming pu lse,i t is ve rified wh ether the  p rogr a m med  cell thre shold vo ltages re a chedt he  resp ect ive de si red  valu e, ass che matic ally s ho wn inFIG.3:  if a ce rtain cell has reachedthe de sired  th reshold l eve l , i t does no t re ceive anyfur the r pro gra m mingpuls e s.  Ve r ifyin g is usually p e rf orm e d  s imultaneous l y for  allcel l s in a  gro up of cells (oneo r more words)that a repro g ramm ed  in parallel a ndfo r any desi re d programmi ng level ,i t con sistsin com paring, d ir e ctly o r in dir ectly, acel lt hreshol dvo l tage w ithpr eset r eferen c e va l u es Vref,i. Progr ammin g and v e rif yingco ntinueu ntil  all cells  in a group  havebeen  prog rammedat  the r esp ec tive desir e d level.It ha s beende mons tra ted (s ee f o r  exam ple:  x e2x 80x9cTech n o lo g ic al and  des ign c on stra ints form ultileve l f l ash mem or ies x e 2x80x9 d  b y C. Calliga ro,  A. M a n stretta, A .  Mod e ll i , G.Torell i, Pro ceeding s  of  I nternal  Co n f erence on  Electron i c C ir cuit s and Sy st ems,  R hod es , Greece, pp. 1 003-1008 ) that i f a setofp rogr a mmingpu lses with co nstan tt ime len g t h i s appli e d t o a  no n-vo lat ilem emory cell, the drain
 programming_of each_of four threshold voltage_levels, while_FIG._2b shows_a_more realistic case,_in which every_logic value corresponds to_a certain threshold_voltage_interval. FIG. 2a also shows the correspondence assigned, as an exemplificative but non limiting_example,_between the_different_threshold_voltage values and programmed levels_(respectively 0, 1, 2 and_3).
The threshold_voltage interval corresponding to each programmable level must_be_sufficiently reduced so_that the intervals corresponding to adjacent levels can be_placed at such a mutual distance_as to guarantee_safe_maintaining_and recognizing of data_stored into the cells, without having_to use a global interval excessively_wide to allocate all desired logic levels._In fact, there are both a_lower limit and an upper_limit for_this global interval, dictated by_practical reasons and_reliability reasons._In order to_compute the optimum distance between threshold_voltage intervals corresponding_to different stored levels, effects such_as_reading and programming_circuits_inaccuracy_and environmental_conditions variations, degrading_time_of the_stored_charge and reading and programming noises_must_also be taken into account, since they_create an undesired stored_charge_variation, as known to_the skilled person.
To obtain an_adequate cell programming, generally the multi-level_cell programming_is performed_through the technique defined as xe2x80x9cprogram and verifyxe2x80x9d. According to this_technique, a programming operation is performed_through a succession of_programming pulses_and,_after having applied_each_programming pulse,_it is verified whether the programmed cell_threshold voltages_reached the respective desired value, as_schematically shown in FIG._3:_if a certain cell has reached_the desired threshold level, it does_not receive any further programming_pulses._Verifying_is usually performed simultaneously for_all cells in a group of_cells (one or_more words) that are programmed in parallel_and_for any desired programming level, it_consists_in comparing, directly or indirectly, a_cell_threshold_voltage with preset reference values_Vref,i. Programming and verifying continue until_all cells in a group have been programmed at_the respective desired_level.
It has been demonstrated (see_for_example:_xe2x80x9cTechnological and design constraints for multilevel flash memoriesxe2x80x9d by C._Calligaro, A._Manstretta, A. Modelli,_G. Torelli, Proceedings of Internal Conference on Electronic Circuits and_Systems, Rhodes, Greece, pp. 1003-1008) that if_a set of programming pulses with constant time length is applied_to a non-volatile memory cell, the drain