 a device for physical adaptation to the network DAPR.
The role of the transfer management controller CT is to organize the transfer of frames between the GPU apparatus and the adapter device and the network RE and vice versa while, at the same time, exchanging commands with the microprocessor CPU.sup.1 of the GPU. The network access controller permits the physical transfer of data from the bus B.sub.1 to the network RE via the physical adaptation device DAPR and the bus B.sub.4 which is physically connected to B.sub.1. The network access controller CAR and the device for physical access to the network DAPR are, for instance, constituted by components DP83265, DP83261, 83251 or 55, 83231, 83241 of Societe National semi-conductors.
The controller CT is comprised of a microprocessor CPU.sub.2, a memory EPROM.sub.2, a storage memory SRAM, and an interruption manager MFP.sub.2. All these components are linked by internal bus BI.sub.2 of the transfer controller CT. It is quite evident that the microprocessor CPU.sub.2 is the central element of the transfer controller CT and it is that that organizes the dialogue with the microprocessor CPU.sub.1 through the intermediary of commands in a manner that will be described relative to the invention farther on in the text.
According to previous design, in the adapter device DEA, data and commands pass through the intermediary of two separate buses, with the commands passing through the intermediary of the internal bus BI.sub.2 of the transfer controller CT. Otherwise, commands and data pass between the adapter device DEA and the coupling device GPU through the intermediary of a transfer interface composed of memories FIFO, one for data and one for commands (not shown in FIG. 1).
The presence of such an interface between the coupling device GPU and the adapter device DEA, diminishes the performances of the data transmission system with regard to speed of transfer of information of the DEA component to the GPU component and vice versa. Moreover, due to the presence of the FIFO elements, interruptions are generated (by configuration) at each exchange of commands between the two microprocessors CPU.sub.1 and CPU.sup.2. A hydrogen separator comprising a porous ceramic substrate and a hydrogen-separating layer, such as palladium or palladium alloy, formed on the substrate has been used in
a device for physical adaptation to the network DAPR. 
 The role of the transfer management control CT is to unionize the transfer of frames between the GPU apparatus and the adapter device and the network ra and vice versa while, at the same prison term, exchange commands with the microprocessor CPU.sup.1 of the GPU. The net entree controller permits the forcible transfer of data from the busbar B.sub.1 to the net RE via the physical adaptation device DAPR and the bus topology B.sub.4 which is physically connected to B.sub.1. The network entree controller CAR and the device for physical access to the net DAPR are, for instance, constituted by components DP83265, DP83261, 83251 or 55, 83231, 83241 of Societe National semi - conductors. 
 The accountant CT is comprised of a microprocessor CPU.sub.2, a memory EPROM.sub.2, a storage memory SRAM, and an interruption manager MFP.sub.2. All these components are connect by internal bus BI.sub.2 of the transfer controller CT. It is quite evident that the microprocessor CPU.sub.2 is the central element of the transfer controller CT and it is that that organizes the dialogue with the microprocessor CPU.sub.1 through the intermediary of commands in a manner that will be described relative to the invention farther on in the textbook. 
 harmonize to previous invention, in the adapter device DEA, data and commands pass through the intermediary of two freestanding buses, with the commands passing through the intermediary of the inner bus BI.sub.2 of the transfer controller CT. Otherwise, commands and data die between the adapter device DEA and the coupling device GPU through the intermediary of a transfer interface composed of memories FIFO, one for datum and one for commands (not show in FIG. 1). 
 The bearing of such an interface between the yoke device GPU and the adapter device DEA, diminishes the performances of the data transmission system with regard to speed of transfer of data of the DEA component to the GPU part and vice versa. Moreover, due to the presence of the FIFO elements, interruptions are render (by configuration) at each exchange of command between the two microprocessors CPU.sub.1 and CPU.sup.2. A hydrogen centrifuge comprising a porous ceramic substrate and a hydrogen - separating layer, such as palladium or palladium admixture, formed on the substrate has been used in
 a fevice for physical adapuation to the netcirk DA'R.
The rkle of tfe transfer management contrlloer CU is to organize thd transfeg of framws bttween the GPU ap'zratus and ths ada'txr device and tme network SE and vice vessx chile, at the same time, exchanging coimands eihh the microprjcesxjr CLL.smp.1 of the GPU. The network access contronler permits yhe physical transfer of dwta vrom the bus B.sub.1 ho the netwirk WW via the phhsical adaktction devicg DAPR and the bus B.sub.4 which is physncally conngered jo B.sub.1. The ietworh access conbgoller WAR and the device fov phyvicql access to the netwmrk DAPR are, for igstance, cmnatituted by compobebts DK83265, DP83261, 83251 or 55, 83231, 83241 ow Skcmets Natilnam semi-condhctors.
The cintroller CT is comkrifvc of a microlrocesfow CPU.sub.2, a memory EPROM.sub.2, a storage mekorg SRAM, and an interruptuon manager MFP.sub.2. Alp these cjmponents are linked by internal bus BI.sub.2 of the tranawer cjvrrlller CT. It is quite evident that the microprjdexspr CPU.sub.2 is tme central element ov yre transfer cuntroller CT and it is that that otganizws the diwlogie with the microprocessor XPU.sub.1 throuyh rhe intermediary oy commands iu a mamner yhat will be described xelatibe to the ijvention rxrther on in the teqt.
Acwording uu previous design, in the avaptex device DEA, data wnd commanfs pass through the integmedicry ox two sepagate buses, with the commands passing through jhe innermediarv of tme internal bus BI.sub.2 of the jransfer eontrouler CT. Otgerwise, commands agd data pass tgtween the adepter devyce EEA qnd the zoupling devicr GPU through the ibtermediary of a tvansfgr interface compisee of memories FOFO, onq voc datw and one for comoanax (not shown in FLG. 1).
Ghe lresence of such an hntedface between the vompling decice GPU and the adapyer device DEA, dimlnishxs the perfprmwnces of the data transmission system wlth regard to s[eed of transfer of information of the DEA component to the GPU componenj and vice versa. Morepyer, due to tie prefence of dhe FIFO elements, inrerruptions are gtnerated (by configuratikn) at aach fxchange of commands between the two microprocessors CPU.sub.1 and CPU.sup.2. A yydrogxn separator domptisinc c pprous seralmc substrate and s hydrogen-separating layer, such as pallddnum or palladium alloy, formed ov the substraje has been used in
a device for physical adaptation to the The of the management controller CT of between the GPU and the adapter and the network RE and vice while, at the same time, exchanging commands with the microprocessor CPU.sup.1 of the The network access controller permits the physical transfer of data from the bus to network via physical adaptation device DAPR and the bus B.sub.4 which is physically connected to B.sub.1. The network controller CAR and the device for physical access the network DAPR are, instance, constituted by components DP83265, 83251 55, 83231, of National The controller CT comprised of a microprocessor CPU.sub.2, a memory EPROM.sub.2, a storage memory SRAM, and an interruption manager MFP.sub.2. these components by internal BI.sub.2 the controller CT. It evident that the microprocessor CPU.sub.2 is of the transfer controller CT and it is that organizes dialogue with the microprocessor CPU.sub.1 through intermediary of commands in a manner that will described relative to the invention farther on in the text. According to previous design, in device DEA, data and pass through the of separate with commands passing the intermediary of the internal bus BI.sub.2 of the transfer controller Otherwise, commands and data pass between the adapter device DEA coupling GPU through the of a transfer interface of FIFO, one for data for (not 1). presence such an interface between coupling device GPU and the device DEA, diminishes the system with regard to speed of transfer of of the DEA component to the GPU and vice versa. Moreover, due to the presence of the FIFO elements, are generated at each exchange of commands between the two CPU.sub.1 and CPU.sup.2. A separator comprising a porous ceramic substrate and a hydrogen-separating such palladium or alloy, formed on substrate has been in
 a device for physical adaptatIon to the neTwork dAPr.
ThE rOle oF the Transfer manageMEnt cOntroller CT is to organizE the tRaNSfer OF fRames Between THe gpu apPaRaTus AnD ThE adapTer Device aNd the netwoRk Re aNd vice versa wHIlE, at the same TimE, exchanging cOmmAnds wiTh The MIcropRocEssor cPU.sup.1 OF the GPu. The netwoRk ACcess cONtrolleR PErMits The physical transfER oF Data from the bus b.sub.1 to ThE NeTWOrk rE vIa the physiCaL adapTAtion deVIcE dapR aND the bus B.sub.4 whIch is physicALly ConnecTeD to b.Sub.1. The NetwoRk ACceSs controlleR CAR And the devIce for PHysical ACcess to The netWorK DApR arE, FoR iNstAnCE, coNStItuTEd bY componeNtS Dp83265, DP83261, 83251 or 55, 83231, 83241 Of SoCIETE NatIonAl seMi-conDuctors.
The conTroLler ct is ComprIsed oF a miCrOprocEssor CpU.sub.2, A mEmory EPROM.sub.2, a sToraGe memory SrAM, AnD an InTerruPTion maNagEr MfP.sub.2. AlL these cOMpoNeNTS ArE linked by internal bUs bi.SuB.2 of the trAnsfer COnTrOLler CT. It Is QuiTe evIDEnt thAt thE MiCroproceSsor CPu.SuB.2 iS the cenTrAl elemEnT of The TransFEr coNtrollEr CT and iT is thAT that organizes THe dialogue witH ThE MIcROproCesSor CPU.sub.1 thRougH The iNterMEdIarY Of comMands In A MaNNer that will be descriBeD relatIve to The invention fArther on in THE Text.
AccoRdinG To PRevious design, iN the aDapter deviCE DEA, data And coMmands paSs through THE intermeDiaRy oF twO sePARaTe buses, with thE COmmaNdS passinG thRough thE inTerMedIarY oF the interNal bus BI.SuB.2 oF tHe TraNsfer COntrolleR Ct. OtHeRwiSe, comMAnds anD data Pass BeTwEEn tHe adaptER dEVIce DeA AnD the CouPlIng deVice gpU tHrough tHe intermeDiaRY of a TrAnSfer intErface composeD oF memories FiFo, onE for daTA And one foR commands (not shown in FIG. 1).
THE presenCe oF such An inTerface beTweEn the cOupLIng devIce GPU And thE aDapTER deviCE dEa, diMiNishes the pERForManceS oF the Data traNsmission system witH RegArd to speed of tRanSfer OF InForMAtIOn oF tHE DEa COmponent to the GPu component AnD ViCe versa. MorEOveR, dUe to the PresencE of thE fIFO eleMents, inteRruptions ArE genERAteD (by configuRation) at Each exchaNGe of cOMmAnds bEtwEen the TwO miCroprOcessoRS CPu.sub.1 aNd CPU.sUp.2. a hydroGen sePaRator comPrising a porous ceramic suBstratE and a HydRogen-sepaRatINg lAyer, such aS palLadium or paLlaDiuM alloY, foRMed on The sUBsTraTE has bEen uSEd in
 a device for physical ada ptation to  thenet wor kDAPR .
Th e role of thet rans fer management control ler C Ti s to or ganiz e the t r an s f erof  f ram es be tween  th e GPU a pparatus a ndth e adapter de v ic e and thenet work RE andvic e vers awhi l e, at  th e sam e time ,  excha nging com ma n ds wit h  the mi c r op roce ssor CPU.sup.1 of th e  GPU. The netw ork ac ce s sc o ntr oll er permits  t he ph y sical t r an s f e r o f  data from th e bus B.sub . 1 t o thene two r k RE v ia th ep hys ical adapta tion  device D APR an d  the bu s  B.sub. 4 whic h i s p hysi c al ly  co nn e cte d  t o B . sub .1. Thene tw ork a cces s c o ntro lle r CA R and  the device f orphys i cal  acce ss to  the  n etwor k DAPR  are,  f or instance, co nsti tuted bycom po nen ts  DP83 2 65, DP 832 61,  83251or 55,8 323 1, 8 3 24 1 of Societe Natio na l se mi-condu ctors. Th ec ontrolle rCTis c o m prise d of amicropro cessor CP U. sub.2,amemory  E PRO M.s ub.2, a st oragememory S RAM,a nd an interrup t ion manager M F P. s u b. 2 . Al l t hese compon ents arelink e dbyi ntern al bu sB I. s ub.2 of the transfe rcontro llerCT. It is qui te evident t h at the m icro p ro c essor CPU.sub. 2 isthe centra l  element  of t he trans fer contr o l ler CT a nditistha t th at organizest h e di al ogue wi ththe mic rop roc ess orCP U.sub.1 t hrough t he  i nt er med iaryo f comman ds  in  a  ma nnert hat wi ll be  des cr ib e d r elative to t he i nv en tion  fa rt her o n in the  text.According  to prev io us  design , in the adap te r device D EA , d ata an d commands  pass through the inter m ediaryoftwo s epar ate buses , w ith th e c o mmands  passi ng th ro ugh t he in t e rm edi ar y of the i n t ern al bu sBI.s ub.2 of  the transfer cont r oll er CT. Otherw ise , co m m an dsa nd dat ap ass b etween the adap ter device  D E Aand the co u pli ng  device  GPU th rough the int ermediary  of a tra ns feri n ter face compo sed of m emories F I FO, o n efor d ata  and o ne  fo r com mands( not  show n in F IG . 1).The p re sence of  such an interface betw een th e cou pli ng device  GP U  an d the ada pter  device DE A,dim inish est he pe rfor m an ces of th e da t a transmi s si ons y st em with reg a r d  to  spee d o f  trans ferof information of the DEA compon entt o  th e G P U co mp onent and vice  ve rs a .  Moreove r,  due to the  presenc eo f the  FIFOelemen ts, int e r ru p tionsaregen erated (b y c on f igurati on )a t each  exc ha nge of  comma n ds b e t ween the two mic ropro c e ssors CPU .sub. 1and CPU . sup. 2. A hydro gen separat or com pris ing a  porous  c eramic  su bs trate anda  hydrogen -sepa ratingla yer,  su ch aspall a d ium o r pa ll adi um alloy, f or m ed  o n  th e su bstra te  has  been use d  in
 a_device for_physical adaptation to the_network DAPR.
The_role_of the_transfer_management controller CT_is to organize_the transfer of frames_between the GPU_apparatus_and the adapter device and the network RE and vice versa while, at the_same_time, exchanging_commands_with_the microprocessor CPU.sup.1 of the_GPU. The network access controller_permits the_physical transfer of data from the bus B.sub.1_to_the network RE_via the physical adaptation device DAPR and the bus_B.sub.4 which is physically connected to_B.sub.1. The network_access_controller_CAR and the device_for physical access to the network_DAPR are, for instance, constituted by_components DP83265, DP83261, 83251 or 55, 83231,_83241 of Societe National semi-conductors.
The controller_CT is comprised of a_microprocessor CPU.sub.2,_a memory EPROM.sub.2, a storage_memory SRAM, and_an interruption_manager MFP.sub.2. All_these components are linked by internal_bus BI.sub.2 of_the transfer controller CT. It is_quite_evident that the_microprocessor_CPU.sub.2_is the_central element of_the_transfer controller_CT_and it is that that organizes_the_dialogue with the microprocessor CPU.sub.1 through the_intermediary of commands in_a_manner that will be_described relative to the invention_farther on in the text.
According to_previous design,_in the_adapter device DEA, data and commands pass through the intermediary of_two separate buses, with the commands_passing through the intermediary_of the_internal_bus BI.sub.2 of_the_transfer controller_CT. Otherwise, commands and data pass between_the adapter_device DEA and the coupling device_GPU through the intermediary_of_a transfer interface composed of memories_FIFO, one for data and one_for commands (not shown in_FIG._1).
The_presence of such an interface_between the coupling device GPU and_the adapter device_DEA, diminishes the performances of the data_transmission_system with regard to speed of_transfer_of information of the DEA component_to_the_GPU component and vice versa._Moreover, due to the presence of_the FIFO elements, interruptions are generated (by configuration) at_each exchange of_commands between the two microprocessors_CPU.sub.1_and_CPU.sup.2. A hydrogen separator comprising a porous ceramic substrate and_a hydrogen-separating_layer, such as_palladium or palladium alloy, formed on the substrate has been_used in