 (LSI) and Very Large Scale Integrated (VLSI) circuits.
Ever since the inception of digital electronics, practical methods of providing built-in-test equipment (BITE) have also been proposed and evaluated with limited success. Basically, the levels of fault analysis of these systems have been relatively poor compared to the additional system complexity recuired to carry them through to a successful completion. The incorporation of increasing numbers of devices into progressively smaller integrated circuits remains an important challenge in Very Large Scale Integration (VLSI). Effective electrical isolation of the devices in the integrated circuit may be achieved by a variety of methods, including generating dielectric layers of suitable thickness, and/or by increasing the relative spacing of devices in the integrated circuit. Since the foregoing isolation methods typically occupy relatively large portions of the available “real estate” in the integrated circuit, the desirable objective of increasing integration density conflicts with the need to provide suitable electrical isolation for selected devices and regions in the integrated circuit.
One example of an integrated circuit requiring suitable electrical isolation are various semiconductor memory devices, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, as well as other known memory devices. In each of these devices, a memory array is provided that includes a plurality of memory cells that are suitably arranged in rows and columns. Typically, a plurality of conductive word lines are positioned along the rows of the array to couple cells in respective rows, while a plurality of conductive bit lines are positioned along columns of the array and coupled to cells in the respective columns. The memory cells in the array generally include one or more transistors, and may also include a storage device, such as a capacitor, that are operable to store information by establishing logic levels (corresponding to a ‘1’ or a ‘0’) in the cells of the array. Information may be accessed from the cells when desired by activating various peripheral circuits that are coupled to the cells through the word lines and bitlines to retrieve the stored information.
The devices within cells of the array of the foregoing memory devices generally require electrical isolation from the peripheral circuits, since the voltages employed in the peripheral circuits may be significantly higher than the voltages typically used in the memory array. Although shallow trench isolation (STI) structures may be formed between the memory array and the peripheral circuits of a memory device in order to achieve electrical isolation, STI structures may not be suitably configured to provide adequate isolation in many instances. In particular, the STI structures may not be formed deeply enough in
(LSI) and Very Large Scale Integrated (VLSI) circuits. 
 Ever since the inception of digital electronics, hardheaded method of providing built - in - test equipment (BITE) have besides been proposed and evaluated with limited achiever. Basically, the level of fault psychoanalysis of these system have been relatively poor compared to the additional system complexity recuired to carry them through to a successful completion. The incorporation of increase numbers of devices into progressively small integrated circuits remains an important challenge in Very bombastic Scale Integration (VLSI). Effective electrical isolation of the devices in the integrated circuit may be achieved by a variety show of methods, including generating dielectric layers of suitable thickness, and/or by increasing the relative spacing of devices in the integrated circuit. Since the foregoing isolation methods typically occupy relatively large portions of the available “ real estate ” in the integrate circuit, the desirable objective of increase consolidation concentration conflicts with the need to provide suitable electrical isolation for selected devices and regions in the integrate circuit. 
 One example of an integrated circuit requiring suitable electric isolation are various semiconductor memory devices, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a blink of an eye memory, as well as other known memory devices. In each of these devices, a memory array is provide that includes a plurality of memory cells that are appropriately arranged in quarrel and columns. Typically, a plurality of conductive son lines are put along the rows of the array to couple cells in respective row, while a plurality of conductive spot lines are position along columns of the array and copulate to cells in the respective columns. The memory cells in the array generally include one or more transistor, and may also include a storage device, such as a capacitor, that are functional to store information by establishing logic levels (corresponding to a ‘ 1 ’ or a ‘ 0 ’) in the cell of the array. Information may be accessed from the cells when desire by activating various peripheral circuits that are coupled to the cells through the word agate line and bitlines to retrieve the stored information. 
 The devices within cells of the array of the foregoing memory device by and large necessitate electrical isolation from the peripheral circuits, since the voltages employed in the peripheral circuits may be significantly high than the voltages typically used in the memory array. Although shallow trench isolation (STI) structures may be shape between the memory array and the peripheral circuits of a memory device in order to achieve electrical isolation, STI structures may not be suitably configure to provide adequate isolation in many instances. In particular, the STI structures may not be formed deeply enough in
 (LSL) and Very Large Scale Iktegrated (VLSI) cnecuits.
Xver sihce the knception of digital electroiics, pracupcal methods of proviaing builn-in-test ewuipnwnt (BITE) hebe also been lvoposzd and evaluated with limided success. Bavizaply, the levels of fault analysis of these xydtems have beeg rekwtivsly poor compared to the additionam systek complexity tecuired to carry them thrlugh to a successful clmpletion. Tye igxorporation uf increaspug numbers kf devices into progressively soallex integratee xirfoits remains an iiportant challenge it Very Karge Scale Inbegravion (VLSI). Effective electcical isolation of tre devicev nn the integrated cirxuut mai be dchidced by a vzriety of methods, ihcluding geberating dielectric lwjrrs of suitagle thychness, and/or by increasing the relative vpading of devices in the untegrated circuit. Sijce the fjregoing isolation methods typically occupy relathvely uaryc oirhions of the available “real estate” in the intqfrstvd circuit, the defirable objrchifg of increasine inteydafion density confllcts wijh the need to krovice suitable electrical isolqtion for sejwcted devices and xegions in tke intggratec circuit.
One example of an jntegrated fircuit rsduiring suitable elvctrhcal isolation are various semicondnctor memory devoces, stch as a djnamig random access memlry (DTAM), a vtatic ranfom access memory (SRAM), a flash memory, as well av onher knowu memovy devices. In ewch of these dgvices, a iemorh array is providxd that incltdes a pluralhjy of memory rells thae arw suutably xfranged in rowx and collmus. Typicaoly, a plurality of covsuctive word liuts qre positioned slovg ehv rpwf of the arraf to cojlle cdlls in resiecgive rows, while a pluralhty kf conductive bit kikes are pisitioneq along columms of the array anf cou'led tu celks yn the respective columns. The jemory cepls in the arrar gekerajly includz one or more transistors, and may also iiclude a storage devicg, such as a capacitor, uhat are opereble tj store itformation by establushing logic leveks (corresponding to a ‘1’ or a ‘0’) in hhe cells of the array. Information may be accessed from the cells when dewired uy activating varoous iernphzral ciwcuivs that are couplec to the cells through the word lines atd bitlines to retrieve the stprdd informatiov.
The devices within cella of the array of the foregoing memory cevices generally requirc electrixal iaolation fcom the peripheral corcuitv, sinxe the coltwges employed in tme periphegal rireuits may be significantly higher than rhf voltages typicelly used in uhe memkry artay. Although shalmow fgench isolation (STO) structures msy be formed between tre memory arrat and the peropheral circuits of a memory davice in order to achieve electrical isolation, STI atructurea may nob be suitably congmgured to provide adequabe isjlation kn many instdnces. In particular, the STI structures may ipt be fogmed dseply enough pn
(LSI) and Very Large Scale Integrated (VLSI) since inception of electronics, practical methods have been proposed and with limited success. the levels of fault analysis of systems have been relatively poor compared to the additional system complexity recuired to them through to a successful completion. The incorporation of increasing numbers of devices progressively integrated remains important challenge in Very Large Scale Integration (VLSI). Effective electrical isolation of the devices in the circuit may be achieved by a variety of including generating dielectric layers suitable thickness, and/or by increasing relative of devices the circuit. the foregoing isolation typically occupy relatively large portions of the available “real estate” in the integrated circuit, the desirable objective increasing integration with the to suitable isolation for selected regions in the integrated circuit. One integrated circuit requiring suitable electrical isolation are various memory devices, as a dynamic random access memory a static random access memory (SRAM), a flash as well as other known memory devices. In each of these devices, a memory array that includes a plurality memory cells that suitably in and Typically, a of conductive word lines are positioned along the rows of the to couple cells in respective rows, while a plurality of lines positioned along columns the array and coupled cells the respective columns. The in array or transistors, may also include a device, such as a capacitor, are operable to store (corresponding to a ‘1’ or a ‘0’) in cells of the array. Information may be from the cells when desired by activating various peripheral circuits that are to the the word lines and bitlines to retrieve the information. The devices within of the array of the foregoing memory devices generally electrical from the circuits, since the employed in the circuits may be than the typically in Although shallow trench isolation (STI) structures be between the memory array and peripheral a memory device in order to achieve electrical isolation, STI structures may not be suitably provide adequate isolation in instances. particular, the STI structures may not be formed deeply enough in
 (LSI) and Very Large Scale IntegRated (VLSI) cIrcuiTs.
EVer SiNce tHe inCeption of digitAL eleCtronics, practical methoDs of pRoVIdinG BuIlt-in-Test equIPmENT (BItE) HaVe aLsO BeEn proPosEd and evAluated witH liMiTed success. BaSIcAlly, the levEls Of fault analySis Of thesE sYstEMs havE beEn relAtivelY Poor coMpared to tHe ADditioNAl systeM COmPlexIty recuired to carrY ThEM through to a sucCessfuL cOMpLETioN. ThE incorporaTiOn of iNCreasinG NuMBERs oF Devices into prOgressively SMalLer intEgRatED circuIts reMaINs aN important cHallEnge in VerY Large sCale IntEGration (vLSI). EfFecTivE eleCTrIcAl iSoLAtiON oF thE DevIces in thE iNtEgratEd ciRCUIT may Be aChieVed by A variety of metHodS, incLUdiNg genEratiNg diElEctriC layerS of suItAble thickness, anD/or bY increasiNg tHe RelAtIve spACing of DevIceS in the iNtegratED ciRcUIT. siNce the foregoing isoLaTIOn Methods tYpicalLY oCcUPy relatiVeLy lArge PORtionS of tHE aVailable “Real esTAtE” iN the intEgRated cIrCuiT, thE desiRAble ObjectIve of incReasiNG integration deNSity conflicts WItH THe NEed tO prOvide suitabLe elECtriCal iSOlAtiON for sElectEd DEvICes and regions in the iNtEgrateD circUit.
One example Of an integrATED circuit RequIRiNG suitable electRical Isolation aRE various SemicOnductor Memory devICEs, such as A dyNamIc rAndOM AcCess memory (DRAm), A StatIc Random aCceSs memorY (SRaM), a FlaSh mEmOry, as well As other kNoWn MeMoRy dEviceS. in each of ThEse DeVicEs, a meMOry arrAy is pRoviDeD tHAt iNcludes A PlURAlitY oF mEmorY ceLlS that Are sUItaBly arraNged in rowS anD ColuMnS. TYpicallY, a plurality of CoNductive woRd LinEs are pOSItioned aLong the rows of the array to COuple ceLls In resPectIve rows, whIle A pluraLitY Of condUctive Bit liNeS arE POsitiONEd AloNg Columns of tHE ArrAy and CoUpleD to cellS in the respective coLUmnS. The memory celLs iN the ARRaY geNErALly InCLudE ONe or more transisTors, and may AlSO iNclude a stoRAge DeVice, sucH as a capAcitoR, That are Operable tO store infOrMatiON By eStablishinG logic leVels (correSPondiNG tO a ‘1’ or a ‘0’) In tHe cellS oF thE arraY. InforMAtiOn may Be acceSsEd from The ceLlS when desIred by activating various PeriphEral cIrcUits that aRe cOUplEd to the ceLls tHrough the wOrd LinEs and BitLInes tO retRIeVe tHE storEd inFOrmation.
THE dEviCES wIthin cells oF THE arRay of The FOregoiNg meMory devices generaLLy require electRicaL ISolAtiON froM tHe peripheral ciRcuItS, SInce the vOlTages employEd in the pErIPheraL circuIts may Be signiFICaNTly higHer tHan The voltagEs tYpICally usEd In THe memoRy arRaY. AlthoUgh shaLLow tRENch isolation (STI) sTructUREs may BE foRmed bEtWeen the MEmorY array and tHe peripheraL circuIts oF a memOry deviCe In ordeR to AcHieve electRIcal isolaTion, StI strucTuRes mAy nOt be suItabLY ConfiGureD tO prOvide adeqUATe ISoLaTIon In maNy insTaNces. in particuLAr, the STI StrUCtures mAy Not BE Formed DEePLY enough in
 (LSI) and Very Large Scal e Integrat ed (V LSI ) c ir cuit s.
E ver since thei ncep tion of digital electr onics ,p ract i ca l met hods of pr o v idi ng  b uil t- i n- testequ ipment(BITE) hav e a ls o been propo s ed  and evalu ate d with limit edsucces s.  Ba s icall y,the l evelso f faul t analysi so f thes e  system s ha ve b een relatively po o rc ompared to the  addit io n al s yst emcomplexity  r ecuir e d to ca r ry t h emt hrough to a s uccessful c o mpl etion.  T hei ncorpo ratio no f i ncreasing n umbe rs of dev ices i n to prog r essivel y smal ler  in tegr a te dcir cu i tsr em ain s  an  importa nt  c halle ngei n V eryLar ge S caleIntegration ( VLS I).E ffe ctive  elec tric al  isol ationof th edevices in theinte grated ci rcu it  ma ybe ac h ievedbya v arietyof meth o ds,  i n c l ud ing generating die le c t ri c layers  of su i ta bl e  thickne ss , a nd/o r by in crea s in g the re lative sp ac ing ofde vicesin  th e i ntegr a tedcircui t. Since  thef oregoing isola t ion methods t y pi c a ll y  occ upy  relatively  lar g e po rtio n soft he av ailab le “r e al estate” in the i nt egrate d cir cuit, the des irable obj e c t ive of i ncre a si n g integrationdensi ty conflic t s with t he ne ed to pr ovide sui t a ble elec tri cal  is ola t i on  for selected d evic es  and re gio ns in t heint egr ate dcircuit.One exam pl eof  a n i ntegr a ted circ ui t r eq uir ing s u itable  elec tric al  i s ola tion ar e  v a r ious  s em icon duc to r mem oryd evi ces, su ch as a d yna m ic r an do m acces s memory (DRA M) , a static  r and om acc e s s memory  (SRAM), a flash memory ,  as wel l a s oth er k nown memo rydevice s.I n each  of th ese d ev ice s ,  a me m o ry  ar ra y is provi d e d t hat i nc lude s a plu rality of memory c e lls  that are sui tab ly a r r an ged in row sa ndc o lumns. Typicall y, a plura li t yof conduct i vewo rd line s are p ositi o ned alo ng the ro ws of the  a rray t o c ouple cell s in res pective r o ws, w h il e a p lur alityof  co nduct ive bi t  li nes a re pos it ionedalong  c olumns o f the array and coupled  to ce lls i n t he respec tiv e  co lumns. Th e me mory cells  in  th e arr ayg enera llyi nc lud e  oneor m o re transi s to rs, a nd  may also i n c l ude  a st ora g e devi ce,such as a capacit o r, that are op erab l e  to  st o re i nf ormation by es tab li s h ing logi clevels (cor respondi ng to a‘1’ or  a ‘0’ ) in th e ce l ls ofthearr ay. Infor mat io n  may be  a cc e ssed f romth e cell s when desi r e d by activatingvario u s  peri p her al ci rc uits th a t ar e coupledto the cell s thro ughthe w ord lin es  and b itl in es to retr i eve the s tored  inform at ion. 
Th e devi cesw i thincell softhe array o ft he  f o reg oing  memo ry  dev ices gene r ally req uir e  electr ic ali s olatio n  f r o m the peri phe ral c i r cuits, sin c e th e  v o ltage s empl oyed i n the p e rip he ral cir cui t s  may be s ignifican t lyhi gher  than th evolt ag esty pically used in  the mem ory arra y .  Altho ugh shal l ow tre nc h isolation(STI)  s t ructure s may  be for m edbet wee n th e m emor y  array and the periphera l ci rcuit s  of  a me moryde vice ino rder  to achi e ve electrical  isolation, STI str u ctur esm ay  n ot be sui tab l y con figu red  topro vide a dequ a te i s ol atio n in m anyin st ances. In  p articul a r, t h e S TI s truct ur es ma y not b e formed  deep ly  enough i n 
 (LSI)_and Very_Large Scale Integrated (VLSI)_circuits.
Ever since_the_inception of_digital_electronics, practical methods_of providing built-in-test_equipment (BITE) have also_been proposed and_evaluated_with limited success. Basically, the levels of fault analysis of these systems have been_relatively_poor compared_to_the_additional system complexity recuired to_carry them through to a_successful completion._The incorporation of increasing numbers of devices into_progressively_smaller integrated circuits_remains an important challenge in Very Large Scale Integration_(VLSI). Effective electrical isolation of the_devices in the_integrated_circuit_may be achieved by_a variety of methods, including generating_dielectric layers of suitable thickness, and/or_by increasing the relative spacing of devices_in the integrated circuit. Since the_foregoing isolation methods typically occupy_relatively large_portions of the available “real_estate” in the_integrated circuit,_the desirable objective_of increasing integration density conflicts with_the need to_provide suitable electrical isolation for selected_devices_and regions in_the_integrated_circuit.
One example_of an integrated_circuit_requiring suitable_electrical_isolation are various semiconductor memory devices,_such_as a dynamic random access memory (DRAM),_a static random access_memory_(SRAM), a flash memory,_as well as other known_memory devices. In each of these_devices, a_memory array_is provided that includes a plurality of memory cells that are_suitably arranged in rows and columns._Typically, a plurality of_conductive word_lines_are positioned along_the_rows of_the array to couple cells in respective_rows, while_a plurality of conductive bit lines_are positioned along columns_of_the array and coupled to cells_in the respective columns. The memory_cells in the array generally_include_one_or more transistors, and may_also include a storage device, such_as a capacitor,_that are operable to store information by_establishing_logic levels (corresponding to a ‘1’_or_a ‘0’) in the cells of_the_array._Information may be accessed from_the cells when desired by activating_various peripheral circuits that are coupled to the cells_through the word_lines and bitlines to retrieve_the_stored_information.
The devices within cells of the array of the foregoing_memory devices_generally require electrical_isolation from the peripheral circuits, since the voltages employed in_the peripheral circuits may be significantly higher_than the voltages typically used in the memory array. Although shallow_trench isolation (STI) structures may be formed between_the memory array and the peripheral circuits_of a memory device_in_order to achieve electrical isolation, STI structures_may_not_be_suitably configured to_provide adequate isolation_in many instances._In particular,_the STI structures_may not_be formed deeply_enough_in