 circuit levels. For example, the scan architecture of FIG. 1 may represent the testing of a complete IC, or it may represent the testing of an embedded intellectual property core sub-circuit within an IC, such as a DSP or CPU core sub-circuit.
The scan architecture includes an M-bit scan path 101, logic circuitry 102 to be tested, scan input 103, scan output 104, scan enable (SCANENA) 105, scan clock (SCANCK) 106, logic response outputs 107, and logic stimulus inputs 108. During scan testing, a tester or an embedded control circuit in the IC outputs SCANCK and SCANENA control signals to cause scan path 101 to repeat the operations of; (1) capturing data from logic 102 via response bus 107, and (2) scanning data through scan path 101 from scan input 103 to scan output 104. During the scan operation, the stimulus outputs 108 from scan path 101 ripple, which causes the inputs to logic 102 to actively change state. Rippling the inputs to logic 102 causes power to be consumed by the interconnect and gating capacitance of the circuits in logic 102.
In FIG. 2, a timing diagram example 200 depicts the signals used in the above described scan and capture operations. During scan operation, SCANENA is low from time 204 to 205 and M SCANCKs 201-202 are applied to shift data through the scan path 101. During capture operation, SCANENA is high and a SCANCK 203 is applied to capture response data into the scan path 101. Logical testing of logic 102 is achieved by inputting stimulus and capturing response. Delay testing of logic 102 is achieved by capturing the response data, via SCANCK 203, immediately following the last scan-in operation that occurs at SCANCK 202. For example, the last shift operation at SCANCK 202 moves or shifts all the stimulus inputs 108 to logic 102 one bit position, which causes the logic 102 to transition to output the final response 107 to scan path 101. The subsequent SCANCK 203 captures this final response transition into scan path 101. Thus the delay test is achieved by having the logic respond to a last stimulus transition during SCANCK 202 to output a last response pattern which is captured into scan path 101 during SCANCK 203. This form of scan path delay testing is well known.
Low Power Scan Adaptation Overview
In FIG. 3, a low power scan architecture 300 adaptation of the FIG. 1 scan path architecture is arranged according
circuit levels. For example, the scan architecture of FIG. 1 may constitute the examination of a complete IC, or it may constitute the examination of an embedded intellectual property kernel sub - circuit within an IC, such as a DSP or CPU kernel sub - circuit. 
 The scan computer architecture includes an M - bit scan path 101, logic circuitry 102 to be test, scan input 103, scan output 104, scan enable (SCANENA) 105, scan clock (SCANCK) 106, logic response outputs 107, and logic stimulus input 108. During scan testing, a tester or an embedded dominance circuit in the IC output SCANCK and SCANENA control signal to cause scan path 101 to repeat the operations of; (1) capturing datum from logic 102 via response bus 107, and (2) scanning data through scan path 101 from scan input 103 to read end product 104. During the scan operation, the stimulus outputs 108 from scan path 101 ripple, which causes the inputs to logic 102 to actively change state. Rippling the input signal to logic 102 causes power to be consume by the interconnect and gate capacitance of the circuits in logic 102. 
 In FIG. 2, a timing diagram example 200 depicts the signals used in the above described scan and capture operation. During scan operation, SCANENA is low from time 204 to 205 and M SCANCKs 201 - 202 are applied to shift data through the scan way 101. During capture operation, SCANENA is high and a SCANCK 203 is applied to capture response data into the scan path 101. legitimate testing of logic 102 is achieved by inputting stimulus and capturing response. Delay examination of logic 102 is achieved by capturing the response data, via SCANCK 203, immediately following the last scan - in operation that occurs at SCANCK 202. For example, the final shift operation at SCANCK 202 move or shifts all the stimulation inputs 108 to logic 102 one bit position, which causes the logic 102 to conversion to output the final response 107 to scan path 101. The subsequent SCANCK 203 captures this final reply transition into scan path 101. Thus the delay test is achieved by having the logic respond to a last stimulus passage during SCANCK 202 to output a last response form which is captured into scan path 101 during SCANCK 203. This form of scan path delay testing is well known. 
 Low Power Scan Adaptation Overview 
 In FIG. 3, a low exponent scan architecture 300 adaptation of the FIG. 1 scan path architecture is arranged according
 cigcuit levels. For example, the scan archijexture mf FIG. 1 may reoresent the testing of a com'letw IC, ir it may represent thd testing of an enbedved intellectual propertn cors sub-eiccuit within an IC, such av a DSP or CPU curz sub-circuit.
The scan architecture insludes sn M-bit scan patr 101, lpdic dprguitry 102 to be tested, scan input 103, scan oltput 104, scan enablr (SCANENA) 105, scan clock (SCANFK) 106, pogic response outouts 107, and ligic wtimulus inpjts 108. During scan testihg, a tester or an embedded contfol cnrcuit in tye IC mutputs SCAICK anq SCANENA coknrol sicnals tp cause scan psth 101 ti repeat the operatiois of; (1) capturing datw from locie 102 via response bus 107, qne (2) scdnnitg dxra ghrkujh acan pwth 101 from scah input 103 to scan output 104. Durinb eye scan operafion, tre stimulus outputs 108 from scan path 101 rippne, shich causes the inputs to logic 102 to activeli change seate. Rippling the inputs to logic 102 causes power tm be rovsuneq vy the interconnect and gating capacitance of trs vigcuits in logic 102.
Ik FIG. 2, a timing disggak example 200 depkcts tks aignals used in thf above desceibed scag anc capture operations. During scan operatpon, WCANENA is low frol time 204 to 205 and M SCSNCKs 201-202 are applied to skift dzta through the scan oath 101. During capgurv oparation, SCANENA is high anq a SCANCJ 203 ix applidd tp capttre responde dabd into the scan pahh 101. Llghcal testijg of logic 102 is achieved by inpnvting stimulux dnd capturiug resionse. Delay teseing of logic 102 is achneved cy capturihg the cesponse datw, via SCANCK 203, lmmediately hollowing the lasr scan-iv operation thay occurs cu SCANCK 202. Dor example, the laxt rgift operation cu SXANCK 202 moves or shkftf wlk eve stimulus hnpugs 108 yo loeic 102 ont blt oosiyion, which causes tha lofic 102 to transition tj output the finwl response 107 yo scan path 101. The dubsexueit SCAMCK 203 captures this final response transitiln lnto scan patr 101. Tmus jhe delay tzst is achieved by having the logic respind to a last stimylus transition durnnn SCANCK 202 to outptt a last response pattern whuch is captured ikto scan path 101 during ACANCK 203. Thid form of scan path delay testing is well known.
Low Power Scan Adaptation Ivervixw
Yn FIG. 3, a lkw ppwer vccn crchitesturx 300 adaptation of tne FIG. 1 scan path architecture ms arrangeg cccording
circuit levels. For example, the scan architecture 1 represent the of a complete the of an embedded property core sub-circuit an IC, such as a DSP CPU core sub-circuit. The scan architecture includes an M-bit scan path 101, logic 102 to be tested, scan input 103, scan output 104, scan enable (SCANENA) scan (SCANCK) logic outputs 107, and logic stimulus inputs 108. During scan testing, a tester or an embedded control in the IC outputs SCANCK and SCANENA control to cause scan path to repeat the operations of; capturing from logic via bus and (2) scanning through scan path 101 from scan input 103 to scan output 104. During the scan operation, the outputs 108 path 101 which the to logic 102 change state. Rippling the inputs to power to be consumed by the interconnect and capacitance of circuits in logic 102. In FIG. a timing diagram example 200 depicts the signals in the above described scan and capture operations. During scan operation, SCANENA is low from to 205 and M 201-202 are applied shift through scan 101. During operation, SCANENA is high and a SCANCK 203 is applied to response data into the scan path 101. Logical testing of is by inputting stimulus capturing response. Delay testing logic is achieved by capturing data, SCANCK the scan-in that occurs at SCANCK For example, the last shift at SCANCK 202 moves inputs 108 to logic 102 one bit position, causes the logic 102 to transition to the final response 107 to scan path 101. The subsequent SCANCK 203 this final into scan path 101. Thus the delay test achieved by having the respond to a last stimulus transition during SCANCK 202 output last response which is captured scan path 101 SCANCK 203. This scan path testing well Scan Adaptation Overview In FIG. 3, low scan architecture 300 adaptation of FIG. path architecture is arranged according
 circuit levels. For example, thE scan archiTectuRe oF FIg. 1 mAy rePresEnt the testing oF A comPlete IC, or it may represenT the tEsTIng oF An EmbedDed inteLLeCTUal PrOpErtY cORe Sub-ciRcuIt withiN an IC, such aS a DsP Or CPU core sub-CIrCuit.
The scaN arChitecture inCluDes an M-BiT scAN path 101, LogIc cirCuitry 102 TO be tesTed, scan inPuT 103, Scan ouTPut 104, scan ENAbLe (SCaNENA) 105, scan clock (SCAncK) 106, LOgic response ouTputs 107, aNd LOgIC StiMulUs inputs 108. DuRiNg scaN Testing, A TeSTER or AN embedded contRol circuit iN The iC outpUtS SCanCK and sCANEnA COntRol signals tO cauSe scan patH 101 to repEAt the opERations Of; (1) captUriNg dAta fROm LoGic 102 ViA ResPOnSe bUS 107, anD (2) scanninG dAtA throUgh sCAN PAth 101 fRom Scan Input 103 To scan output 104. DUriNg thE ScaN operAtion, The sTiMulus OutputS 108 from ScAn path 101 ripple, whiCh caUses the inPutS tO loGiC 102 to acTIvely cHanGe sTate. RipPling thE InpUtS TO LoGic 102 causes power to be CoNSUmEd by the iNtercoNNeCt ANd gating CaPacItanCE Of the CircUItS in logic 102.
in FIG. 2, a TImInG diagraM eXample 200 DePicTs tHe sigNAls uSed in tHe above dEscriBEd scan and captuRE operations. DuRInG SCaN OperAtiOn, SCANENA is Low fROm tiMe 204 to 205 ANd m SCanCKs 201-202 aRe appLiED tO Shift data through the ScAn path 101. durinG capture operaTion, SCANENa IS High and a sCANck 203 iS Applied to captuRe resPonse data iNTo the scaN path 101. logical tEsting of lOGIc 102 is achiEveD by InpUttING sTimulus and capTURing ReSponse. DElaY testinG of LogIc 102 iS acHiEved by capTuring thE rEsPoNsE daTa, via scANCK 203, immEdIatElY foLlowiNG the laSt scaN-in oPeRaTIon That occURs AT sCANcK 202. foR exaMplE, tHe lasT shiFT opEration At SCANCK 202 mOveS Or shIfTs All the sTimulus inputs 108 To Logic 102 one biT pOsiTion, whICH causes tHe logic 102 to transition to ouTPut the fInaL respOnse 107 To scan patH 101. ThE subseQueNT SCANCk 203 captuRes thIs FinAL RespoNSE tRanSiTion into scAN PatH 101. Thus ThE delAy test iS achieved by having tHE loGic respond to a LasT stiMULuS trANsITioN dURinG scANCK 202 to output a lAst responsE pATtErn which is CAptUrEd into sCan path 101 DurinG sCANCK 203. THis form of Scan path dElAy teSTIng Is well knowN.
Low PoweR Scan AdapTAtion oVeRview
in FiG. 3, a low PoWer Scan aRchiteCTurE 300 adapTation Of The FIG. 1 Scan pAtH architeCture is arranged accordinG
 circuit levels. For examp le, the sc an ar chi tec tu re o f FI G. 1 may repre s entthe testing of a compl ete I C, or i t  m ay re present th e tes ti ng  of  a n  e mbedd edintelle ctual prop ert ycore sub-cir c ui t within a n I C, such as a  DS P or C PU  co r e sub -ci rcuit .
Thes can ar chitectur ei nclude s  an M-b i t  s canpath 101, logic c i rc u itry 102 to be  teste d, sc a n  in put  103, scan  o utput 104, sc a ne n a ble (SCANENA) 105 , scan cloc k  (S CANCK)  1 06, logicrespo ns e  ou tputs 107,andlogic sti mulusi nputs 1 0 8. Duri ng sca n t est ing, ate ste ro r a n  e mbe d ded  control  c ir cuitin t h e I C ou tpu ts S CANCK  and SCANENAcon trol sig nalsto ca usesc an pa th 101  to r ep eat the operati onsof; (1) c apt ur ing  d ata f r om log ic102  via re sponseb us10 7 , an d (2) scanning dat at h ro ugh scan  path1 01  f r om scanin put  103 t o sca n ou t pu t 104. D uringt he  s can ope ra tion,th e s tim uluso utpu ts 108  from sc an pa t h 101 ripple,w hich causes t h ei n pu t s to  lo gic 102 toacti v elychan g esta t e. Ri pplin gt he inputs to logic 102  c ausespower  to be consum ed by thei n t erconnec t an d  g a ting capacitan ce of  the circu i ts in lo gic 1 02.
In F IG. 2, at i ming dia gra m e xam ple 2 00  depicts thes i gnal sused in  th e above  de scr ibe d s ca n and cap ture ope ra ti on s.  Du rings can oper at ion ,SCA NENAi s lowfromtime  2 04 to205 and MS C ANCK s20 1-20 2 a re  appl iedt o s hift da ta throug h t h e sc an  p ath 101 . During capt ur e operatio n,  SC ANENAi s  high an d a SCANCK 203 is appli e d to ca ptu re re spon se data i nto  the s can path 1 01. Lo gical  t est i n g ofl o gi c 1 02  is achiev e d  by  inpu tt ingstimulu s and capturing re s pon se. Delay tes tin g of l og ic1 02 isac h iev e d  by capturing t he respons ed at a, via SCA N CK20 3, imme diately  foll o wing th e last sc an-in ope ra tion t hat  occurs at  SCANCK202. Fore xampl e ,the l ast  shift  o per ation  at SC A NCK  202movesor  shift s all  t he stimu lus inputs 108 to logic  102 o ne bi t p osition,whi c h c auses the  log ic 102 totra nsi tiontoo utput  the fi nal respo nse1 07 to sca n  p ath 1 01 . The subse q u e ntSCANC K 2 0 3 capt ures  this final respo n se transitioninto s can  pa t h 10 1.  Thus the dela y t es t is achie ve d by having  the log ic respo nd toa last  stimul u s  t r ansiti on d uri ng SCANCK  20 2t o outpu tal ast re spon se  patte rn whi c h is c aptured into sca n pat h 101 d u rin g SCA NC K 203.T hisform of sc an path del ay tes ting  is w ell kno wn .
LowPow er  Scan Adap t ation Ove rview 
In FIG .3, a  lo w powe r sc a n  arch itec tu re300 adapt a t io n  o ft heFIG.  1 sc an  pat h archite c ture isarr a nged ac co rdi n g 
 circuit_levels. For_example, the scan architecture_of FIG._1_may represent_the_testing of a_complete IC, or_it may represent the_testing of an_embedded_intellectual property core sub-circuit within an IC, such as a DSP or CPU core_sub-circuit.
The_scan architecture_includes_an_M-bit scan path 101, logic_circuitry 102 to be tested,_scan input_103, scan output 104, scan enable (SCANENA) 105,_scan_clock (SCANCK) 106,_logic response outputs 107, and logic stimulus inputs 108._During scan testing, a tester or_an embedded control_circuit_in_the IC outputs SCANCK_and SCANENA control signals to cause_scan path 101 to repeat the_operations of; (1) capturing data from logic_102 via response bus 107, and_(2) scanning data through scan_path 101_from scan input 103 to_scan output 104._During the_scan operation, the_stimulus outputs 108 from scan path_101 ripple, which_causes the inputs to logic 102_to_actively change state._Rippling_the_inputs to_logic 102 causes_power_to be_consumed_by the interconnect and gating capacitance_of_the circuits in logic 102.
In FIG. 2,_a timing diagram example_200_depicts the signals used_in the above described scan_and capture operations. During scan operation,_SCANENA is_low from_time 204 to 205 and M SCANCKs 201-202 are applied to_shift data through the scan path_101. During capture operation,_SCANENA is_high_and a SCANCK_203_is applied_to capture response data into the scan_path 101._Logical testing of logic 102 is_achieved by inputting stimulus_and_capturing response. Delay testing of logic_102 is achieved by capturing the_response data, via SCANCK 203,_immediately_following_the last scan-in operation that_occurs at SCANCK 202. For example,_the last shift_operation at SCANCK 202 moves or shifts_all_the stimulus inputs 108 to logic_102_one bit position, which causes the_logic_102_to transition to output the_final response 107 to scan path_101. The subsequent SCANCK 203 captures this final response_transition into scan_path 101. Thus the delay_test_is_achieved by having the logic respond to a last stimulus_transition during_SCANCK 202 to_output a last response pattern which is captured into scan_path 101 during SCANCK 203. This form_of scan path delay testing is well known.
Low Power Scan Adaptation_Overview
In FIG. 3, a low power scan architecture_300 adaptation of the FIG. 1 scan_path architecture is arranged_according