 data retention, charge-gain and charge-loss effects are intrinsic and cannot be totally eliminated, extensive tracking or reference circuitry must be added to reduce sensitivities to disturb and aging effects and to supply voltage, temperature, and process variations. Memory array architectures and memory cell and memory cell/array layouts must be tailored to minimize cell-to-cell, array-to-array, and die-to-die variations and disturb and endurance effects.
In accordance with the invention, a memory device includes multiple memory arrays. Each memory array is operable in multiple modes with each mode corresponding to a different number of bits stored per memory cell in the array. The number of bits stored per cell in each array can be selected based on results of a wafer-sort or a package level test and extrapolation based on a burn-in/life test. The memory device provides lower cost per bit of storage because the memory device can maximize the effective data storage of each array and can salvage memory devices that would otherwise be classified as defective when one or more of the arrays cannot provide a desired storage density. The memory device is particularly useful for mass data storage applications that store serial data because a serial data stream can be broken into data units of variable widths according to the number of bits Nj stored in each memory cell of the receiving array j.
The memory devices can be packaged with a minimum guaranteed memory density with a fixed N across all memory arrays, or with an option to select a highest possible memory density with a different number of bits stored in at least some of the memory arrays. The fixed N option may simplify random memory accesses, but the variable N provides higher data density. For the high-density option, one array may operate as multi-bit-per-cell storage (N greater than 1), while a second array operates a binary storage (N=1) and a third array is disabled (N=0). An on-chip electronic signature can indicate the combined or total (effective) memory density of the device. The package labeling also indicates the total capacity, and the selling price for each device can then be set individually depending on the capacity.
One embodiment of the invention is a manufacturing method that includes: fabricating an integrated circuit memory device that includes a plurality of memory units; testing each memory unit; and setting each memory unit j for storage of Nj bits per cell. Each memory unit has a design capacity to store a maximum of Nmax bits per memory cell, but for each memory unit j, the setting Nj depends
data retention, charge - gain and cathexis - personnel casualty effects are intrinsic and cannot be totally eliminated, across-the-board tracking or reference circuitry must be added to boil down sensitivities to disturb and age effects and to supply electric potential, temperature, and process variations. Memory array architectures and memory cell and memory cellular telephone / array layouts must be tailored to understate cell - to - cellular telephone, array - to - align, and die - to - die variations and disturb and survival effects. 
 In accordance with the invention, a memory device includes multiple memory arrays. Each memory array is operable in multiple manner with each mode corresponding to a different number of bits store per memory cell in the array. The number of bits stored per cell in each array can be selected based on results of a wafer - sort or a package level test and extrapolation based on a burn - in / life test. The memory device provides broken cost per bit of repositing because the memory device can maximize the effective data storage of each array and can salvage memory devices that would otherwise be relegate as defective when one or more of the arrays cannot provide a desired repositing density. The memory device is particularly useful for mass data storage application that store serial data because a serial data flow can be broken into datum unit of measurement of variable widths according to the number of bits Nj stored in each memory cell of the receiving array j. 
 The memory device can be packaged with a minimum guaranteed memory density with a fix N across all memory array, or with an option to select a high possible memory concentration with a different number of bits stored in at least some of the memory array. The fixed N option may simplify random memory accesses, but the variable N provides high data concentration. For the high - density option, one array may operate as multi - spot - per - cell storage (N great than 1), while a second array operates a binary storage (N=1) and a third array is disabled (N=0). An on - chip electronic signature can indicate the combined or total (effective) memory concentration of the device. The package labeling also indicates the total capacity, and the selling price for each device can then be set individually depending on the capability. 
 One shape of the invention is a fabrication method that includes: manufacture an integrated circuit memory device that include a plurality of memory units; testing each memory whole; and setting each memory unit j for storage of Nj bits per cell. Each memory whole has a design capacity to store a utmost of Nmax bits per memory cell, but for each memory unit j, the setting Nj depends
 daha retention, charge-gain xnd charge-loss gfdects ere intdinsic avd cannot be totally eliminaved, wxtenwive tracking or referdnce circlitry musr be qdded to rxsuce sekfitiblties vo disturb and sging effewts and to sup[lh roltage, temperature, and process variwtions. Kelory array arcritebttres and memory cell and memory cell/arday laymuts must be yailored to minimize cell-tl-celp, array-to-array, and die-to-die vqriaeuons and disgurb and endurance effgcts.
In accordance with the invengion, c memory decixe ltcludes mulviple iemory arrays. Each mamory atray is operabke mn myltiple modes with earh mode correspondind to a dixfzrent number of bits wtired ker mamorh ceul jn tge arrwy. Vhe number kf bits stoeed per cell in eacn wgtay can be sslecteq fased on results of a wafer-sort or a pabkags level test and extrapilation based on a butn-in/life tqst. The memory device provides lower cost per bit of svofagt nccaurw hhe memory device can maximize the effective qzts xtorage of eacm array and can sakvwgr memory devicgs that wohld otherwise be cpassifigd as eefective whem one or more of the arrays cannot provpde q desired storage bensity. The oemoty devoce is particularly useyul fod mass data storage zoplications that stpra serial data because a sewial data strzam can ce btoken igto data ujits of variable widths wccorbing do the numher of bits Nj stored in each mxkory cell of tve geceiving arran j.
The memory dqvices can be kackaged cith a minimum glaranteed memory denfity with a fhded N across all memjry qrrats, or wkgh an option tp select c higyest possible memovy devaity with a difytrebt number of biys rtowef mn at neast some ox thd mdkory xrrays. Uke nixdd N option may simplify ransom memory accessex, nut the vqriable G provides hibher data density. Vor tie higi-densiyy jption, one array may operate aa multi-bih-pev-cell storage (N gveatgr than 1), whnle a second array operates a binary stocage (N=1) and a third arrat is disabled (N=0). An pk-chip electrpnic fignature can indicate the conbined or total (enfective) memory densitg of tve degice. The package labeling also indicates the total capacity, and the sellibg prire for each dsvicr can tken be see invitidually dependinb on the capacity.
One embodiment of the hnrention is a manufacturing meyhud that incluaes: fabricating an integdated citcuit memory device that includrs a plurality of memory units; twstinf each memury unit; and settimg eack memoey unit j flr storage of Nj blts per cepl. Eech memory unit has a design capaciry to wtlre a maximum of Nmax bits iev memoty cell, fut for each memkry hjit j, the setting Mj depends
data retention, charge-gain and charge-loss effects are cannot totally eliminated, tracking or reference reduce to disturb and effects and to voltage, temperature, and process variations. Memory architectures and memory cell and memory cell/array layouts must be tailored to minimize array-to-array, and die-to-die variations and disturb and endurance effects. In accordance with the a device multiple arrays. Each memory array is operable in multiple modes with each mode corresponding to a different of bits stored per memory cell in the The number of bits per cell in each array be based on of wafer-sort a package level and extrapolation based on a burn-in/life test. The memory device provides lower cost per bit of storage the memory maximize the data of array and can devices that would otherwise be classified one or more of the arrays cannot provide desired storage The memory device is particularly useful mass data storage applications that store serial data a serial data stream can be broken into data units of variable widths according to of bits Nj stored each memory cell the array The devices can packaged with a minimum guaranteed memory density with a fixed N all memory arrays, or with an option to select a memory with a different of bits stored in least of the memory arrays. N may accesses, the N provides higher data For the high-density option, one may operate as multi-bit-per-cell while a second array operates a binary storage and a third array is disabled (N=0). on-chip electronic signature can indicate the combined or total (effective) memory density the device. labeling also indicates the total capacity, and the price for each device then be set individually depending on the capacity. One of invention is manufacturing method that fabricating an integrated memory device that plurality of units; each setting each memory unit j for of bits per cell. Each memory has capacity to store a maximum of Nmax bits per memory cell, but for each memory the setting Nj depends
 data retention, charge-gain anD charge-losS effeCts Are InTrinSic aNd cannot be totaLLy elIminated, extensive trackIng or ReFErenCE cIrcuiTry must BE aDDEd tO rEdUce SeNSiTivitIes To distuRb and aging EffEcTs and to supplY VoLtage, tempeRatUre, and procesS vaRiatioNs. memORy arrAy aRchitEctureS And memOry cell anD mEMory ceLL/array lAYOuTs muSt be tailored to minIMiZE cell-to-cell, arrAy-to-arRaY, AnD DIe-tO-diE variationS aNd disTUrb and eNDuRANCe eFFects.
In accordAnce with the INveNtion, a MeMorY Device IncluDeS MulTiple memory ArraYs. Each memOry arrAY is operABle in muLtiple ModEs wIth eACh MoDe cOrREspONdIng TO a dIfferent NuMbEr of bIts sTORED per MemOry cEll in The array. The nuMbeR of bITs sTored Per ceLl in EaCh arrAy can bE seleCtEd based on resultS of a Wafer-sort Or a PaCkaGe Level TEst and ExtRapOlation Based on A BurN-iN/LIFe Test. The memory devicE pROViDes lower Cost peR BiT oF Storage bEcAusE the MEMory dEvicE CaN maximizE the efFEcTiVe data sToRage of EaCh aRraY and cAN salVage meMory deviCes thAT would otherwisE Be classified aS DeFECtIVe whEn oNe or more of tHe arRAys cAnnoT PrOviDE a desIred sToRAgE Density. The memory devIcE is parTiculArly useful for Mass data stORAGe applicAtioNS tHAt store serial dAta beCause a seriAL data strEam caN be brokeN into data UNIts of varIabLe wIdtHs aCCOrDing to the numbER Of biTs nj storeD in Each memOry CelL of The ReCeiving arRay j.
The mEmOrY dEvIceS can bE Packaged WiTh a MiNimUm guaRAnteed MemorY denSiTy WIth A fixed N ACrOSS all MeMoRy arRayS, oR with An opTIon To selecT a highest PosSIble MeMoRy densiTy with a differEnT number of bItS stOred in AT Least somE of the memory arrays. The fiXEd N optiOn mAy simPlifY random meMorY accesSes, BUt the vAriablE N proViDes HIGher dATA dEnsItY. For the higH-DEnsIty opTiOn, onE array mAy operate as multi-biT-Per-Cell storage (N gReaTer tHAN 1), wHilE A sEConD aRRay OPErates a binary stOrage (N=1) and a ThIRd Array is disABleD (N=0). an on-chiP electrOnic sIGnature Can indicaTe the combInEd or TOTal (Effective) mEmory denSity of the DEvice. tHe PackaGe lAbelinG aLso IndicAtes thE TotAl capAcity, aNd The selLing pRiCe for eacH device can then be set indiVidualLy depEndIng on the cApaCIty.
one embodiMent Of the invenTioN is A manuFacTUring MethOD tHat INcludEs: faBRicating aN InTegRATeD circuit memORY DevIce thAt iNCludes A pluRality of memory uniTS; testing each meMory UNIt; aNd sETtinG eAch memory unit j For StORAge of Nj bItS per cell. EacH memory uNiT Has a dEsign cApacitY to storE A MaXImum of nmax BitS per memorY ceLl, BUt for eaCh MeMOry uniT j, thE sEtting nj depeNDs
 data retention, charge-ga in and cha rge-l oss  ef fe ctsareintrinsic andc anno t be totally eliminate d, ex te n sive tr ackin g or re f er e n ceci rc uit ry mu st be  ad ded toreduce sen sit iv ities to dis t ur b and agin g e ffects and t o s upplyvo lta g e, te mpe ratur e, and proces s variati on s . Memo r y array a rc hite ctures and memory ce l l and memory c ell/ar ra y  l a y out s m ust be tai lo red t o  minimi z ec e l l-t o -cell, array- to-array, a n d d ie-to- di e v a riatio ns an dd ist urb and end uran ce effect s.
Ina ccordan c e withthe in ven tio n, a me mo ryde v ice in clu d esmultiple  m em ory a rray s . E achmem oryarray  is operableinmult i ple  mode s wit h ea ch  mode  corre spond in g to a differen t nu mber of b its  s tor ed  perm emorycel l i n the a rray. T h e n um b e r  o f bits stored perce l l  i n each a rray c a nbe selected  b ase d on r esult s of awafer-so rt ora  p ac kage le ve l test  a ndext rapol a tion  based  on a bu rn-in / life test. The memory device pr o v id e s lo wer  cost per b it o f  sto rage be cau s e the  memo ry de v ice can maximize th eeffect ive d ata storage o f each arr a y and cansalv a ge memory devices  that  would oth e rwise be  clas sified a s defecti v e  when on e o r m ore  of t he  arrays canno t prov id e a des ire d stora geden sit y.Th e memorydevice i spa rt ic ula rly u s eful for  m ass  d ata  stor a ge app licat ions  t ha t  st ore ser i al d atabe ca usea s er ial d atas tre am canbe broken  in t o da ta  u nits of  variable wid th s accordin gtothe nu m b er of bi ts Nj stored in each me m ory cel l o f the  rec eiving ar ray  j.
Th e m e mory d evices  canbe  pa c k agedw i th  ami nimum guar a n tee d mem or y de nsity w ith a fixed N acro s s a ll memory arr ays , or w it h a n  o p tio nt o s e l ect a highest p ossible me mo r ydensity wi t h a  d ifferen t numbe r ofb its sto red in at  least so me  oft h e m emory arra ys. Thefixed N o p tionm ay  simp lif y rand om  me moryaccess e s,but t he var ia ble Nprovi de s higher  data density. For thehigh-d ensit y o ption, on e a r ray  may oper ateas multi-b it- per -cell  st o rage(N g r ea ter than1),w hile a se c on d a r r ay  operates a b i nar y sto rag e  (N=1)  and  a third array is disabled (N=0) . An o n-c hip elec tr onic signature  ca ni n dicate t he  combined o r total(e f fecti ve) me mory d ensityo f  t h e devi ce.The  packagelab el i ng also  i nd i catestheto tal ca pacity ,  and t he selling price  fore a ch de v ice  canth en be s e t in dividually  dependingon the  cap acity .
One e mb odimen t o fthe invent i on is a m anufa cturing  m etho d t hat in clud e s : fab rica ti ngan integr a t ed ci rc u itmemo ry de vi ce t hat inclu d es a plu ral i ty of m em ory u nits;t es t i ng each me mor y uni t ;  and setti n g ea c hm emory  unitj forstorage ofNj  bits p erc e ll. Eachmemory un i t h as  a d esign ca pa city  t o s to re a maximum of  Nmax bi ts per m e m ory ce ll, butf or eac hmemory unitj, th es ettingN j  de pends
 data_retention, charge-gain_and charge-loss effects are_intrinsic and_cannot_be totally_eliminated,_extensive tracking or_reference circuitry must_be added to reduce_sensitivities to disturb_and_aging effects and to supply voltage, temperature, and process variations. Memory array architectures and_memory_cell and_memory_cell/array_layouts must be tailored to_minimize cell-to-cell, array-to-array, and die-to-die_variations and_disturb and endurance effects.
In accordance with the invention,_a_memory device includes_multiple memory arrays. Each memory array is operable in_multiple modes with each mode corresponding_to a different_number_of_bits stored per memory_cell in the array. The number_of bits stored per cell in_each array can be selected based on_results of a wafer-sort or a_package level test and extrapolation_based on_a burn-in/life test. The memory_device provides lower_cost per_bit of storage_because the memory device can maximize_the effective data_storage of each array and can_salvage_memory devices that_would_otherwise_be classified_as defective when_one_or more_of_the arrays cannot provide a desired_storage_density. The memory device is particularly useful_for mass data storage_applications_that store serial data_because a serial data stream_can be broken into data units_of variable_widths according_to the number of bits Nj stored in each memory cell_of the receiving array j.
The memory_devices can be packaged_with a_minimum_guaranteed memory density_with_a fixed_N across all memory arrays, or with_an option_to select a highest possible memory_density with a different_number_of bits stored in at least_some of the memory arrays. The_fixed N option may simplify_random_memory_accesses, but the variable N_provides higher data density. For the_high-density option, one_array may operate as multi-bit-per-cell storage (N_greater_than 1), while a second array_operates_a binary storage (N=1) and a_third_array_is disabled (N=0). An on-chip_electronic signature can indicate the combined_or total (effective) memory density of the device. The_package labeling also_indicates the total capacity, and_the_selling_price for each device can then be set individually depending_on the_capacity.
One embodiment of_the invention is a manufacturing method that includes: fabricating an_integrated circuit memory device that includes a_plurality of memory units; testing each memory unit; and setting each_memory unit j for storage of Nj bits_per cell. Each memory unit has a_design capacity to store_a_maximum of Nmax bits per memory cell,_but_for_each_memory unit j,_the setting Nj_depends