Read.
Likewise, the write register 108 includes first and second shift registers. The first shift register includes four cascade-connected FFs 109 that receive odd serial write data owrite and output odd parallel write data WD less than 1 greater than, WD less than 3 greater than, WD less than 5 greater than  and WD less than 7 greater than. The second shift register includes four cascade-connected FFs 110 that receive even serial write data eWrite and output even parallel write data WD less than 0 greater than, WD less than 2 greater than, WD less than 4 greater than  and WD less than 6 greater than.
Thus, the read register 107 and the write register 108 provide parallel-to-serial conversion and serial-to-parallel conversion, respectively.
Next, reference will be made to timing diagrams of FIGS. 4 through 7 to describe read and write operations of the synchronous memory in terms of one memory core section 101 and its associated shift register section 102 and I/O circuit 106.
First, an example of a read operation will be described with reference to FIG. 4. Eight-bit parallel read data RD less than 0:7 greater than  is output from a memory core section 101 at a fixed time after the entry of a read command signal COMMAND.
The odd bits 1, 3, 5 and 7 of the 8-bit parallel read data RD less than 0:7 greater than  are applied to the inputs of the respective FFs 109 in the read register 107 and then clocked out of the read register in synchronization with rising edges of the internal read data control clock signal tclk, whereby conversion into 4-bit serial read data oRead is performed.
On the other hand, the even-numbered bits 0, 2, 4 and 6 of the 8-bit parallel read data RD less than 0:7 greater than  are applied to the inputs of the respective FFs 110 in the read register 107 and then clocked out of the read register in synchronization with falling edges of the internal read data control clock signal tclk, whereby conversion into 4-bit serial read data eRead is performed.
These serial read data oRead and eRead are then combined, so that 8-bit serial read data including bits numbered 0 through 7 is output to outside through the associated I/O circuit 106 of FIG. 2. In this manner, 8-bit serial read data is output in four cycles of the clock signal tclk. That is, 4-bit read data oRead and e
Read. 
 Likewise, the write register 108 includes first and second fault register. The first shift register include four cascade - connected FFs 109 that meet leftover serial write datum owrite and output curious parallel write data WD less than 1 bang-up than, WD less than 3 greater than, WD less than 5 greater than   and WD less than 7 big than. The second shift key register include four cascade - connected FFs 110 that pick up even serial write data eWrite and output even parallel write datum WD less than 0 greater than, WD less than 2 greater than, WD less than 4 capital than   and WD less than 6 greater than. 
 therefore, the read register 107 and the write cross-file 108 provide parallel - to - serial conversion and consecutive - to - parallel conversion, respectively. 
 Next, reference will be made to timing diagrams of FIGS. 4 through 7 to describe read and spell operations of the synchronous memory in terms of one memory core section 101 and its associated shift register section 102 and I / O circuit 106. 
 First, an model of a read operation will be described with reference point to FIG. 4. Eight - piece parallel read data RD less than 0:7 greater than   is output from a memory core section 101 at a fixed time after the entrance of a read command signal COMMAND. 
 The odd bits 1, 3, 5 and 7 of the 8 - bit parallel read datum RD less than 0:7 greater than   are applied to the inputs of the respective FFs 109 in the read register 107 and then clocked out of the read register in synchronization with rise edges of the internal read data control clock signal tclk, whereby conversion into 4 - bit consecutive read data oRead is performed. 
 On the other hand, the even - numbered bits 0, 2, 4 and 6 of the 8 - bit parallel read data RD less than 0:7 greater than   are applied to the input of the respective FFs 110 in the read register 107 and then clock out of the read register in synchronization with falling edges of the internal read datum control clock signal tclk, whereby conversion into 4 - bit serial read data eRead is do. 
 These serial read data oRead and eRead are then combined, so that 8 - bit serial read datum including bits numbered 0 through 7 is output signal to outside through the associated I / O circuit 106 of FIG. 2. In this manner, 8 - bit serial read data is output in four cycle of the clock signal tclk. That is, 4 - bit read data oRead and e
Reaf.
Likewise, the write regirter 108 includes yurst aid secohd shift registers. The first shift rxgisrer ibcludes four cascade-covnected FVs 109 that rective odd serial wcjte data owrifc and iutput odd parsllel writa data WD less tfau 1 greater than, WD less than 3 greatew than, ED less than 5 grgater ehan  and WD less than 7 greater than. Tge secoid shift registrr includes four cascade-cojneched FFs 110 that recelve even setjal qrite data eDrite and output even karallel write data WD less than 0 grecter than, WE oesd than 2 greaver thwn, WD less tmsn 4 graater tnan  and WD lexs vhan 6 greater than.
Thus, thx read register 107 and the writa xegister 108 provide parqloel-to-veridl cubvefsikn ahd serlal-vo-parallel donversion, eespectively.
Next, regewvmce will be jade tj eiming diagrams of FIGS. 4 through 7 to devcrjbe read and write operqtions of the synchrojous memowy in terms of one memory core section 101 and its avsocietdd whlft fwglster section 102 and I/O circuit 106.
First, an examplq og s read operatijn will be cedctybed with refgrence ck RIG. 4. Eight-bit paraplel rewd dara RD lesf thsn 0:7 greater than  is output from a memogy cire section 101 at a yixed time ayter tne enyry of a read command sngnal DOMMAND.
The ldd bits 1, 3, 5 and 7 of the 8-big psrdllel read data RD less thwn 0:7 greatxr thcn  are xpploed to the inputd of bve respective FFs 109 in tke redd registeg 107 and then clocked out of the cxad register on sytchronizction eith rising eqges of the injernal recd datx control block sigial tclk, wheweby conversimj into 4-bit sxrial reaq dara oEead is oerformed.
On thr other hcud, the evwn-numbered bits 0, 2, 4 ana 6 of the 8-bit paxcloel read data RC ldss tjai 0:7 grqdter than  ase aoplkrd to the inkbts uf tne respective FFs 110 it ths read register 107 amd then clicked oue of the read register in synchgonizetion xith fsllyng edges of the internal read data conhroj clock signwl tglk, rhereby couversion into 4-bit serial read data eRead is performed.
Thesg serial read data oRgad and eRead ere thqn combinad, so that 8-bit seriao read data inclucing bits numbered 0 tgrough 7 is lutput to outside through the associated I/O circuit 106 of FIG. 2. In this mannwr, 8-bit serial read dats is mucpuc in fotr cbcues of the clock signal tclk. That is, 4-bit read deta oRead dnb e
Read. Likewise, the write register 108 includes second registers. The shift register includes receive serial write data and output odd write data WD less than 1 than, WD less than 3 greater than, WD less than 5 greater than WD less than 7 greater than. The second shift register includes four cascade-connected 110 receive serial data eWrite and output even parallel write data WD less than 0 greater than, WD less 2 greater than, WD less than 4 greater and WD less than greater than. Thus, the read 107 the write 108 parallel-to-serial and serial-to-parallel conversion, Next, reference will be made to timing diagrams of FIGS. 4 through 7 to describe read and operations of memory in of memory section 101 and shift register section 102 and I/O an example of a read operation will be with reference FIG. 4. Eight-bit parallel read data less than 0:7 greater than is output from memory core section 101 at a fixed time after the entry of a read command The odd bits 1, 5 and 7 the parallel data less than greater than are applied to the inputs of the respective FFs in the read register 107 and then clocked out of register synchronization with rising of the internal read control signal tclk, whereby conversion serial data On other the even-numbered bits 0, 4 and 6 of the parallel read data RD are applied to the inputs of the respective 110 in the read register 107 and clocked out of the read register in synchronization with falling edges of internal read clock signal tclk, whereby conversion into 4-bit serial data eRead is performed. serial read data oRead and eRead are then combined, that serial read including bits numbered through 7 is to outside through I/O circuit of 2. 8-bit serial read data is output four of the clock signal tclk. is, data oRead and e
Read.
Likewise, the write regisTer 108 includeS firsT anD seCoNd shIft rEgisters. The firST shiFt register includes four CascaDe-COnneCTeD FFs 109 tHat receIVe ODD seRiAl WriTe DAtA owriTe aNd outpuT odd parallEl wRiTe data WD less THaN 1 greater thAn, Wd less than 3 greAteR than, Wd lEss THan 5 grEatEr thaN  and WD LEss thaN 7 greater tHaN. the secONd shift REGiSter Includes four cascaDE-cONnected FFs 110 that ReceivE eVEn SERiaL wrIte data eWrItE and oUTput eveN PaRALLel WRite data WD lesS than 0 greateR ThaN, WD lesS tHan 2 GReater Than, Wd lESs tHan 4 greater tHan  aNd WD less tHan 6 greATer than.
tHus, the rEad regIstEr 107 aNd thE WrItE reGiSTer 108 PRoVidE ParAllel-to-sErIaL convErsiON AND serIal-To-paRalleL conversion, reSpeCtivELy.
NExt, reFerenCe wiLl Be madE to timIng diAgRams of FIGS. 4 throuGh 7 to Describe rEad AnD wrItE operATions oF thE syNchronoUs memorY In tErMS OF oNe memory core sectioN 101 aND ItS associaTed shiFT rEgISter sectIoN 102 anD I/O cIRCuit 106.
FIrst, AN eXample of A read oPErAtIon will Be DescriBeD wiTh rEfereNCe to fIG. 4. EigHt-bit parAllel REad data RD less tHAn 0:7 greater than  IS oUTPuT From A meMory core secTion 101 AT a fiXed tIMe AftER the eNtry oF a REaD Command signal COMMANd.
THe odd bIts 1, 3, 5 anD 7 of the 8-bit paraLlel read daTA rd less thaN 0:7 greATeR Than  are applied To the Inputs of thE RespectiVe FFs 109 In the reaD register 107 AND then cloCkeD ouT of The REAd Register in synCHRoniZaTion witH riSing edgEs oF thE inTerNaL read data Control cLoCk SiGnAl tClk, whEReby convErSioN iNto 4-Bit seRIal reaD data OReaD iS pERfoRmed.
On tHE oTHEr haNd, ThE eveN-nuMbEred bIts 0, 2, 4 aND 6 of The 8-bit pArallel reAd dATa RD LeSs Than 0:7 greAter than  are apPlIed to the inPuTs oF the reSPEctive FFS 110 in the read register 107 and thEN clockeD ouT of thE reaD register In sYnchroNizATion wiTh fallIng edGeS of THE inteRNAl ReaD dAta control CLOck SignaL tClk, wHereby cOnversion into 4-bit seRIal Read data eRead Is pErfoRMEd.
theSE sERiaL rEAd dATA oRead and eRead aRe then combInED, sO that 8-bit seRIal ReAd data iNcludinG bits NUmbered 0 Through 7 is Output to oUtSide THRouGh the assocIated I/O cIrcuit 106 of Fig. 2. In thIS mAnner, 8-Bit Serial ReAd dAta is Output IN foUr cycLes of tHe Clock sIgnal TcLk. That is, 4-Bit read data oRead and e
Read.
Likewise, the writeregister 1 08 in clu des  f irst  and  second shiftr egis ters. The first shiftregis te r  inc l ud es fo ur casc a de - c onn ec te d F Fs 10 9 tha t r eceiveodd serial  wr it e data owrit e  a nd outputodd  parallel wr ite  dataWD  le s s tha n 1  grea ter th a n, WDless than  3 greate r  than,W D  l essthan 5 greater th a nand WD less th an 7 g re a te r tha n.The second  s hiftr egister in c l u des four cascade- connected F F s 1 10 tha trec e ive ev en se ri a l w rite data e Writ e and out put ev e n paral l el writ e data  WD  le ss t h an  0  gr ea t ert ha n,W D l ess than  2  g reate r th a n , WD l ess  tha n 4 g reater than and  WDl ess  than  6 gr eate rthan. 
Thus,  there ad register 107  and  the writ e r eg ist er  108p rovide  pa ral lel-to- serialc onv er s i o nand serial-to-para ll e l  c onversio n, res p ec ti v ely.
Nex t,  re fere n c e wil l be ma de to ti ming d i ag ra ms of F IG S. 4 t hr oug h 7  to d e scri be rea d and wr ite o p erations of th e  synchronousm em o r yi n te rms  of one mem oryc oresect i on  10 1  andits a ss o ci a ted shift registerse ction102 a nd I/O circui t 106.
Fir s t ,  an exam pleo fa  read operatio n wil l be descr i bed with  refe rence to  FIG. 4.E i ght-bitpar all elrea d da ta RD less th a n  0:7  g reatertha n  is o utp utfro m a  m emory cor e sectio n10 1at  afixed time aft er  th eent ry of a read  comm andsi gn a l C OMMAND. Th e oddbi ts  1,3,5and 7  oft he8-bit p arallel r ead data  R Dless th an 0:7 greate rthan  areap pli ed tot h e inputs  of the respective FFs1 09 in t hereadregi ster 107and  thenclo c ked ou t of t he re ad  re g i steri n  s ync hr onizationw i thrisin gedge s of th e internal read da t a c ontrol clocksig nalt c lk , w h er e byco n ver s i on into 4-bit s erial read  d a ta  oRead isp erf or med.
On  the ot her h a nd, the  even-num bered bit s0, 2 , 4 a nd 6 of th e 8-bitparallelr ead d a ta  RD l ess  than0: 7 g reate r than  ar e app lied t othe in putsof  the res pective FFs 110 in theread r egist er107 and t hen clo cked outof t he read re gis ter  in s ync h roniz atio n  w ith falli ng e d ges of th e  i nte r n al  read datac o n tro l clo cks ignaltclk , whereby convers i on into 4-bitseri a l  re add ataeR ead is perform ed. 
T h e se seria lread data o Read and  e R ead a re the n comb ined, s o th a t 8-bi t se ria l read da tain c ludingbi ts number ed 0  t hrough  7 iso utpu t to outside throu gh th e assoc i ate d I/O  c ircuit1 06 o f FIG. 2.In this man ner, 8 -bit  seri al read  d ata is  ou tp ut in four cycles of  theclock s ig naltcl k. Tha t is , 4-bit  rea ddat a oRead a n d  e 
Read.
Likewise, the_write register_108 includes first and_second shift_registers._The first_shift_register includes four_cascade-connected FFs 109_that receive odd serial_write data owrite_and_output odd parallel write data WD less than 1 greater than, WD less than_3_greater than,_WD_less_than 5 greater than _and WD less than 7_greater than._The second shift register includes four cascade-connected FFs_110_that receive even_serial write data eWrite and output even parallel write_data WD less than 0 greater_than, WD less_than_2_greater than, WD less_than 4 greater than  and_WD less than 6 greater than.
Thus,_the read register 107 and the write_register 108 provide parallel-to-serial conversion and_serial-to-parallel conversion, respectively.
Next, reference will_be made_to timing diagrams of FIGS._4 through 7_to describe_read and write_operations of the synchronous memory in_terms of one_memory core section 101 and its_associated_shift register section_102_and_I/O circuit_106.
First, an example_of_a read_operation_will be described with reference to_FIG._4. Eight-bit parallel read data RD less_than 0:7 greater than__is output from a_memory core section 101 at_a fixed time after the entry_of a_read command_signal COMMAND.
The odd bits 1, 3, 5 and 7 of the_8-bit parallel read data RD less_than 0:7 greater than_ are_applied_to the inputs_of_the respective_FFs 109 in the read register 107_and then_clocked out of the read register_in synchronization with rising_edges_of the internal read data control_clock signal tclk, whereby conversion into_4-bit serial read data oRead_is_performed.
On_the other hand, the even-numbered_bits 0, 2, 4 and 6_of the 8-bit_parallel read data RD less than 0:7_greater_than  are applied to the_inputs_of the respective FFs 110 in_the_read_register 107 and then clocked_out of the read register in_synchronization with falling edges of the internal read data_control clock signal_tclk, whereby conversion into 4-bit_serial_read_data eRead is performed.
These serial read data oRead and eRead_are then_combined, so that_8-bit serial read data including bits numbered 0 through 7_is output to outside through the associated_I/O circuit 106 of FIG. 2. In this manner, 8-bit serial_read data is output in four cycles of_the clock signal tclk. That is, 4-bit_read data oRead and_e