80x9cguessxe2x80x9d to the decoded block of bits. For the parallel iterative decoding module, the delay in processing a series of blocks increases since the next block for decoding must be buffered as the present block is decoded. For both serial and parallel implementations of the iterative decoder of FIGS. 2 and 3, N component codes may be decoded with the N component code decoders.
Use of concatenated codes for magnetic recording systems introduces a latency period from added processing time incurred by the additional decoding operations. In magnetic recording systems, a parallel iterative decoding module of FIG. 3 may not be desirable for use with, for example, the data decoder 106 of FIG. 1, if the long latency period between each read operation by the magnetic read head reduces magnetic recording system performance to unacceptable levels. For example, one input block of length L experiences a delay of LNI clock cycles of an iterative decoder. Consequently, until the iterative decoder completes a decoding process for one block, the next block must be buffered. Therefore, iterative decoding is performed serially in a pipelined fashion.
The implementation complexity (i.e., circuit size and number of components) of the serial iterative decoding module, because of repeated operations of each iteration, increases the requirement for power and integrated circuit area. For example, the complexity of the circuit implementing the serial iterative decoder of FIG. 2 is I times higher than the complexity of the circuit implementing the parallel iterative decoder of FIG. 3.
The present invention relates iterative decoding of data stored in a medium of a recording system in which the data is user data that is encoded with concatenated codes. In accordance with an exemplary embodiment, a section of the data is read from the medium as a number of packets during a read mode of the recording system. The data is encoded in accordance with a concatenated code having N component codes, N an integer greater than 1, and the number of packets is related to N. The packets of the section of data are loaded into a circular processor during read mode, the circular processor decoding in accordance with the N component codes. A circular processor iteratively cycles and processes the packets during a servo mode of the recording system. The decoded section of the data from the circular processor is then provided and, if present, the next section of the data is loaded into the circular processor in read mode and the iterative decoding process is repeated. In accordance with a further embodiment of the present invention, the circular processor is a parallel iterative decoder. Typical podded engines,
80x9cguessxe2x80x9d to the decoded block of bits. For the parallel iterative decoding module, the delay in process a serial of blocks increases since the future engine block for decoding must be buffered as the present auction block is decode. For both serial and parallel implementations of the iterative decoder of FIGS. 2 and 3, N component codes may be decoded with the N part code decoders. 
 Use of concatenated codes for magnetic recording system introduces a latency period from added processing time incur by the additional decoding operations. In charismatic recording systems, a parallel iterative decoding faculty of FIG. 3 may not be desirable for use with, for exemplar, the data decoder 106 of FIG. 1, if the farseeing latency period between each read process by the magnetic read head reduces magnetic recording system performance to unacceptable levels. For example, one input block of length L experiences a delay of LNI clock cycles of an iterative decoder. Consequently, until the iterative decoder completes a decoding process for one pulley, the next block must be cushion. consequently, iterative decoding is do serially in a pipelined fashion. 
 The implementation complexity (i.e., racing circuit size and number of components) of the serial iterative decoding faculty, because of repeated operations of each iteration, increases the requirement for power and integrated circuit area. For example, the complexity of the circuit implementing the serial iterative decoder of FIG. 2 is I meter high than the complexity of the circuit implementing the parallel iterative decoder of FIG. 3. 
 The present invention relates iterative decoding of data stored in a culture medium of a recording system in which the data is user datum that is encoded with concatenate codes. In accordance with an admonitory embodiment, a department of the data is read from the culture medium as a number of package during a read mode of the recording arrangement. The data is encode in accordance with a concatenated code having N part codes, N an integer greater than 1, and the number of packets is related to N. The packets of the section of data are loaded into a circular processor during read mode, the round processor decoding in accord with the N component codes. A circular central processing unit iteratively cycles and processes the packets during a servo mode of the recording system. The decoded section of the data from the circular processor is then provided and, if present, the next part of the datum is loaded into the circular processor in read mode and the iterative decoding process is repeated. In accordance with a further shape of the present invention, the circular processor is a parallel iterative decoder. Typical podded engines,
80x9cgkessxe2x80x9d to the decoded block of bits. Yir the paralmel iterxtive decoding module, the depat in kgocessing a series of blocks ijcreases sinre the next block for degjdinf musc ue buffered as jhe present tlock is decodad. Flr both serial and parallel implemegtationx lf the iteratide dtcoqer kf FIGS. 2 and 3, N component codes mag be deboded with the N vomponent code decoders.
Use of foncatenated codes for magnetuc rqxording systdms introdlees a latendy period from added processing time incurred vy thf additional decoqing operations. In mdgnetic recording sysbems, e paeallel iterative decoving module of FIG. 3 iay not ba besirable for use wity, dor efampne, tfw dxta dxcoser 106 ov FMG. 1, if the mong latenct period between eavh grad operatioh by tre magnetic read head reduces magnetic rebordjng system performance ro unacceptable leveld. For exaiple, one input block of length L experiences a denay oh UNI cjuxk cycles of an iterative decoder. Consequently, thtol the iterative decoder cokppeygs a decoding krocess fod one block, the nedt bloch musr be bufftred. Yherefore, iterative decodint is performvd swrially in a pipelnned fashion.
Che imklemenyation complexity (i.e., cixcuit aize and nulber of ckoponents) of the rerpal hterativt decoding module, fecause oh repzated opdratoons os each itegatiok, increases the reqkiremgnt fos power anf integrated circuit area. For eeemple, the comklefitj of the eircuib implementing ehe serial itetative deeoder uf FIG. 2 is I timev higher thwn the compleflty of the cmrcuit im[lemwntibg the oxrallel iteratove decodvr of DIG. 3.
The present inyentiuh relates iteracnvt eecoding of daya rtowef mn a iadium of a racoraine systdm in which ghe cata is user data thdt ia encoded with convabenated cides. In wccordance wiyh an exemplary emhodimxnt, a rectipn jf the data is read from the msdium as w nmmber of packqts euring a reab mode of the recording system. The data ms encoded in accordancw with a concatenatgd gode having I compjnent codas, N an integer grearer than 1, and the number of packets is relatad to N. The packets of the section of data are loaded into a circular processoe duriig read mode, fhe vircunax pxocessow deroving in accordancv with the N component codes. A cmrcular prmczssor iteratively cycles and lrucesses the pxckets during a servo mose of thr recording system. The decoded xection of the data from the cirxular processor is then provided snd, if preswnt, the nexb section of tfe caba is loadfd iito the circular processor in read node abd the iterative dxcoding proccsr is tepeated. In accordance wjth z furtfer embodimeny of the presemt invention, the cirbulwr processor iw a parallel oterajnne decoder. Ty'ical podded engines,
80x9cguessxe2x80x9d to the decoded block of bits. parallel decoding module, delay in processing since next block for must be buffered the present block is decoded. For serial and parallel implementations of the iterative decoder of FIGS. 2 and 3, component codes may be decoded with the N component code decoders. Use of codes magnetic systems a latency period from added processing time incurred by the additional decoding operations. In magnetic recording a parallel iterative decoding module of FIG. 3 not be desirable for with, for example, the data 106 FIG. 1, the latency between each read by the magnetic read head reduces magnetic recording system performance to unacceptable levels. For example, one input of length a delay LNI cycles an iterative decoder. the iterative decoder completes a decoding block, the next block must be buffered. Therefore, decoding is serially in a pipelined fashion. The complexity (i.e., circuit size and number of components) the serial iterative decoding module, because of repeated operations of each iteration, increases the requirement and integrated circuit area. example, the complexity the implementing serial decoder of 2 is I times higher than the complexity of the circuit the parallel iterative decoder of FIG. 3. The present invention decoding data stored in medium of a recording in the data is user is with accordance an embodiment, a section of data is read from the as a number of of the recording system. The data is encoded accordance with a concatenated code having N codes, N an integer greater than 1, and the number of packets related to packets of the section of data are loaded a circular processor during mode, the circular processor decoding in accordance with the component A circular iteratively cycles and the packets during servo mode of system. The section the circular processor is then provided and, present, next section of the data loaded circular processor in read mode and the iterative decoding process is repeated. In accordance with embodiment of the present the processor is a parallel iterative decoder. Typical podded engines,
80x9cguessxe2x80x9d to the decoded bLock of bits. for thE paRalLeL iteRatiVe decoding moduLE, the Delay in processing a seriEs of bLoCKs inCReAses sInce the NExT BLocK fOr DecOdINg Must bE buFfered aS the presenT blOcK is decoded. FoR BoTh serial anD paRallel implemEntAtions Of The ITeratIve DecodEr of FIgs. 2 and 3, N cOmponent cOdES may be DEcoded wITH tHe N cOmponent code decodERs.
uSe of concatenatEd codeS fOR mAGNetIc rEcording syStEms inTRoduces A LaTENCy pERiod from added Processing tIMe iNcurreD bY thE AdditiOnal dEcODinG operations. in maGnetic recOrding SYstems, a PArallel IteratIve DecOdinG MoDuLe oF Fig. 3 maY NoT be DEsiRable for UsE wIth, foR exaMPLE, The dAta DecoDer 106 of fIG. 1, if the long lAteNcy pERioD betwEen eaCh reAd OperaTion by The maGnEtic read head redUces Magnetic rEcoRdIng SyStem pERformaNce To uNacceptAble levELs. FOr EXAMpLe, one input block of lEnGTH L ExperienCes a deLAy Of lnI clock cYcLes Of an ITEratiVe deCOdEr. ConseqUently, UNtIl The iterAtIve decOdEr cOmpLetes A DecoDing prOcess for One blOCk, the next block MUst be buffered. tHeREFoRE, iteRatIve decoding Is peRFormEd seRIaLly IN a pipElineD fAShIOn.
The implementation CoMplexiTy (i.e., cIrcuit size and Number of coMPONents) of tHe seRIaL Iterative decodIng moDule, becausE Of repeatEd opeRations oF each iterATIon, increAseS thE reQuiREMeNt for power and INTegrAtEd circuIt aRea. For eXamPle, The ComPlExity of thE circuit ImPlEmEnTinG the sERial iterAtIve DeCodEr of Fig. 2 is I tiMes hiGher ThAn THe cOmplexiTY oF THe ciRcUiT impLemEnTing tHe paRAllEl iteraTive decodEr oF fIG. 3.
THe PrEsent inVention relateS iTerative deCoDinG of datA STored in a Medium of a recording systeM In which The Data iS useR data that Is eNcoded WitH ConcatEnated Codes. in AccORDance WITh An eXeMplary emboDIMenT, a secTiOn of The data Is read from the mediuM As a Number of packeTs dUrinG A ReAd mODe OF thE rECorDINg system. The data Is encoded iN aCCoRdance with A ConCaTenated Code havIng N cOMponent Codes, N an iNteger greAtEr thAN 1, And The number oF packets Is related TO N. The PAcKets oF thE sectiOn Of dAta arE loadeD IntO a cirCular pRoCessor DurinG rEad mode, tHe circular processor decoDing in AccorDanCe with the n coMPonEnt codes. A CircUlar procesSor IteRativEly CYcles And pROcEssES the pAckeTS during a sERvO moDE Of The recordinG SYSteM. The dEcoDEd sectIon oF the data from the ciRCular processor Is thEN ProVidED and, If Present, the next SecTiON Of the datA iS loaded into The circuLaR ProceSsor in Read moDe and thE ITeRAtive dEcodIng Process is RepEaTEd. In accOrDaNCe with A furThEr emboDiment OF the PREsent invention, thE circULAr proCEssOr is a PaRallel iTEratIve decoder. typical poddEd engiNes,
80x9cguessxe2x80x9d to the  decoded b lockofbit s.  For  the  parallel iter a tive  decoding module, thedelay  i n  pro c es singa serie s  o f blo ck sinc re a se s sin cethe nex t block fo r d ec oding must b e  b uffered as  th e present bl ock  is de co ded .  Forbot h ser ial an d  paral lel imple me n tation s  of the i te rati ve decoder of FIG S .2  and 3, N comp onentco d es m aybedecoded wi th  theN  compon e nt c o ded ecoders.
Useof concaten a ted  codes  f orm agneti c rec or d ing  systems in trod uces a la tencyp eriod f r om adde d proc ess ing  tim e  i nc urr ed byt he  ad d iti onal dec od in g ope rati o n s .  Inmag neti c rec ording system s,a pa r all el it erati ve d ec oding  modul e ofFI G. 3 may not be  des irable fo r u se  wi th , for exampl e,the  data d ecoder1 06of F I G.  1, if the long la te n c yperiod b etween ea ch read ope ra tio n by t he ma gnet i cread hea d redu c es  m agnetic  r ecordi ng  sy ste m per f orma nce to  unaccep table levels. For ex a mple, one inp u tb l oc k  oflen gth L exper ienc e s adela y  o f L N I clo ck cy cl e so f an iterative deco de r. Con seque ntly, until t he iterati v e decodercomp l et e s a decoding p roces s for oneb lock, th e nex t blockmust be b u f fered. T her efo re,  it e r at ive decodingi s  per fo rmed se ria lly ina p ipe lin edfa shion.
Th e implem en ta ti on  co mplex i ty (i.e. ,cir cu itsizea nd num ber o f co mp on e nts ) of th e  s e r ialit er ativ e d ec oding  mod u le,  becaus e of repe ate d  ope ra ti ons ofeach iteratio n,  increases  t herequir e m ent forpower and integrated ci r cuit ar ea.  Forexam ple, thecom plexit y o f  the c ircuit  impl em ent i n g the s er ial  i terative d e c ode r ofFI G. 2  is I t imes higher than t h e c omplexity ofthe  cir c u it  im p le m ent in g  th e parallel iterat ive decode ro fFIG. 3.
Th e  pr es ent inv entionrelat e s itera tive deco ding of d at a st o r edin a mediu m of a r ecordings ystem in  whic h t he dat aisuserdata t h atis en codedwi th con caten at ed codes . In accordance with an  exemp laryemb odiment,a s e cti on of the  dat a is readfro m t he me diu m  as a  num b er  of packe ts d u ring a re a dmod e of  the record i n g  sy stem.  Th e  datais e ncoded in accorda n ce with a conc aten a t edcod e  hav in g N componentcod es , N an int eg er greaterthan 1,an d  thenumber  of pa ckets i s re l ated t o N.  Th e packets  of  t h e secti on  o f  dataarelo aded i nto ac ircu l a r processor duri ng re a d  mode ,  th e cir cu lar pro c esso r decoding  in accorda nce wi th t he Ncompone nt  codes . A  c ircular pr o cessor it erati vely cy cl es a ndproces sest h e pac kets  d uri ng a serv o mo d eof the  rec ordin gsyst em. The d e coded se cti o n of th edat a from t h ec i rcular pro ces sor i s then provi d ed a n d, if pr esent,  the n ext sec t ion  o f the d ata i s loadedinto thec irc ul ar p rocessor  i n re ad  mo de  and the iterat ive deco ding pro c e ss isrep e ated .  In ac co rdance witha fur th e r embod i m ent  of the pre sen t i nven tio n, t h e circular processor isa pa ralle l  it erati ve de co der. Typ i calpodded e n gines,
80x9cguessxe2x80x9d to_the decoded_block of bits. For_the parallel_iterative_decoding module,_the_delay in processing_a series of_blocks increases since the_next block for_decoding_must be buffered as the present block is decoded. For both serial and parallel_implementations_of the_iterative_decoder_of FIGS. 2 and 3,_N component codes may be_decoded with_the N component code decoders.
Use of concatenated codes_for_magnetic recording systems_introduces a latency period from added processing time incurred_by the additional decoding operations. In_magnetic recording systems,_a_parallel_iterative decoding module of_FIG. 3 may not be desirable_for use with, for example, the_data decoder 106 of FIG. 1, if_the long latency period between each_read operation by the magnetic_read head_reduces magnetic recording system performance_to unacceptable levels._For example,_one input block_of length L experiences a delay_of LNI clock_cycles of an iterative decoder. Consequently,_until_the iterative decoder_completes_a_decoding process_for one block,_the_next block_must_be buffered. Therefore, iterative decoding is_performed_serially in a pipelined fashion.
The implementation complexity_(i.e., circuit size and_number_of components) of the_serial iterative decoding module, because_of repeated operations of each iteration,_increases the_requirement for_power and integrated circuit area. For example, the complexity of the_circuit implementing the serial iterative decoder_of FIG. 2 is_I times_higher_than the complexity_of_the circuit_implementing the parallel iterative decoder of FIG._3.
The present_invention relates iterative decoding of data_stored in a medium_of_a recording system in which the_data is user data that is_encoded with concatenated codes. In_accordance_with_an exemplary embodiment, a section_of the data is read from_the medium as_a number of packets during a read_mode_of the recording system. The data_is_encoded in accordance with a concatenated_code_having_N component codes, N an_integer greater than 1, and the_number of packets is related to N. The packets_of the section_of data are loaded into_a_circular_processor during read mode, the circular processor decoding in accordance_with the_N component codes._A circular processor iteratively cycles and processes the packets during_a servo mode of the recording system._The decoded section of the data from the circular processor is_then provided and, if present, the next section_of the data is loaded into the_circular processor in read_mode_and the iterative decoding process is repeated._In_accordance_with_a further embodiment_of the present_invention, the circular_processor is_a parallel iterative_decoder. Typical_podded engines,