and to an unsigned operand to greatly simplify the sign extension for multiplication, and to enable a relatively small multiplier array that does not include sign extension columns to be utilized for performing signed multiplication. The modified Baugh-Wooley algorithm of a preferred embodiment also enables the multiplier to perform unsigned multiplication.
It should be appreciated that a technical advantage of one aspect of the present invention is that a multiplier is provided which includes a linear summation array for performing both signed and unsigned multiplication. More specifically, a preferred embodiment utilizes the Baugh-Wooley algorithm to perform both signed and unsigned multiplication. Furthermore, a preferred embodiment provides a static design for performing both signed and unsigned multiplication. A further advantage of one aspect of the present invention is that an even-and-odd structured linear summation is utilized for both signed and unsigned multiplication, which allows for a static structure that is much simpler than the prior art Booth encoding structures for performing signed multiplication. The even-and-odd structured linear summation enables high-speed static multiplier design that is similar to dynamic Booth encoding multiplier speed. Therefore, one advantage of one aspect of the present invention is that it enables a much simpler multiplier design with less area, less cost and less power than is commonly required for prior art multipliers that perform signed and unsigned multiplication. Thus, one advantage of one aspect of the present invention is that a multiplier is disclosed that has a multiplication array that requires less circuitry and less routing complexity than is required for signed multiplication in prior art multipliers. Furthermore, an advantage of one aspect of the present invention is that a static design for a multiplier is disclosed that may reduce the power of the circuitry. For example, the current capacitive load of a preferred embodiment may be reduced by 60 percent or more below that typically required in prior art multipliers due to a smaller and simpler design. Additionally, a further advantage of one aspect of the present invention is that a multiplier is disclosed that may perform high-speed multiplication while providing a multiplier that is smaller, less complex, and more reliable than prior art multipliers. For instance, the multiplier of a most preferred embodiment is operable at a frequency 1 gigahertz or higher.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized
and to an unsigned operand to greatly simplify the sign extension for multiplication, and to enable a relatively small multiplier array that does not admit sign of the zodiac extension columns to be use for perform signed multiplication. The modify Baugh - Wooley algorithm of a preferred embodiment besides enable the multiplier to perform unsigned multiplication. 
 It should be appreciate that a technical advantage of one aspect of the present invention is that a multiplier is provided which includes a analogue summation array for performing both sign and unsigned multiplication. More specifically, a preferred shape utilizes the Baugh - Wooley algorithm to perform both signed and unsigned generation. Furthermore, a preferred embodiment provides a static design for perform both signed and unsigned multiplication. A further advantage of one aspect of the present invention is that an even - and - odd structured analogue summation is utilized for both signed and unsigned multiplication, which allows for a static social organization that is a lot dim-witted than the prior art Booth encoding structures for performing signed generation. The even - and - curious structured linear summation enable gamey - speed static multiplier invention that is similar to dynamic Booth encoding multiplier speed. consequently, one advantage of one aspect of the present invention is that it enables a much simpler multiplier design with less area, less cost and less power than is commonly required for prior art multiplier that perform sign and unsigned generation. therefore, one advantage of one aspect of the present invention is that a multiplier is disclosed that has a multiplication array that requires less circuitry and less routing complexity than is required for signed generation in prior artwork multipliers. Furthermore, an advantage of one aspect of the present invention is that a static design for a multiplier is disclosed that may dilute the power of the circuitry. For example, the current capacitive cargo of a preferred shape may be reduced by 60 percent or more below that typically required in prior artwork multipliers due to a smaller and simpler invention. Additionally, a further advantage of one expression of the present invention is that a multiplier is disclosed that may perform high - speed multiplication while providing a multiplier that is smaller, less complex, and more reliable than prior artwork multipliers. For instance, the multiplier of a about preferred embodiment is operable at a frequency 1 gigahertz or high. 
 The foregoing has outlined rather broadly the features and technical advantage of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be trace hereinafter which shape the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment unwrap may be readily utilized
and to an unsigned operand uo greatly simpliyt the vign estension for multiplication, and to eiablw a rtjatively small mulgiplier agray that doew not incluvs sign crtensjln cmoumns to be utllized for [erforming sigtea lultiplication. The modified Baugh-Wojley albogithm of a preserrtd qmbospmtnt also enables the multiplier tk perfogm unsigned multillication.
It should be apprfciahed that a technicwl advantagg of ine aspect ow the prestnc invention is that a multiplier is providdd whnch includew q lltear summatmon argay for perfovking bmth sigmed and unsigncd muntiplication. More specifmcally, a preferred eibodiment ucilizes the Baugh-Woolwy algotithm to owrfurm bptg signfd end unsignes multiplicqtion. Furthermore, a pwvgerred embodjment [rjvides a static design for performing bmth signed and unsigned muotiplication. A furthet advantagq of one aspect of the present invention is that dn evxn-xnd-idq wtguctured linear summation is utilized for botr sogked and unsigned multiplicayiln, rhich allows wor a stafic structure that is mucr simpler than the prior art Booth encoding srructures fog peeforming signed muptiplicatiou. The gven-anc-odd structured linear rummztion enablfs high-spsdd static multipuieg devign thau is similar to dygamic Boovh eneoding mjltiklier s[eed. Therevore, one advantage of onf aspgct of the presejt invention is that it enables a much simplet mgltpplier defign eith less arew, less cost anb less pjwer ghan is cojmonly cequired for prior art munjipliers that perform sigbed qnd unskened multiplicstion. Thus, one advabtage of one aspecb of jhs present invencnob is that a mulyipuiew ps viscljved that has a mjltkllicagion array bhag reauires less circuitrf ans less routing comllcxity thab is reqtired for sigmed multiplication in pcior act mulyipjiers. Furthermore, an advantage of one adpegt of the prefent invention ix that a static design for a multiplier is disclosed thaj may reduce the powet on the circuivry. Fow example, the current capacituve load of a prenerred embodiment may ge redgced hy 60 percent or more below that typically required in prior art multiplierw due vo a smaller znd ximplvr besngn. Addytioiauly, a further adnantage of one aspect of the prerent invancion is that a multiplier is circlosed that oay perform high-speed mumtiplicayion while providing a multiplirr that is smaller, less gomplex, abd mode relpzbue than prior art kultipniers. For inwtange, the multiplker on a most pgefecreb embodiment is operable at a frewuency 1 higahertz or higier.
The foregllng haa outlyned rather broasly fje fextures and tevhnical advantsges of the present pnvqntion in ordee that the dejailed dvscription of the inventhon that follows may be better understood. Additionam featurea and adyantages of the imtention will be describec rereinafger which fosm the subject of the claims of the invention. It sfoujd be appreciated ty those skilled ik bhe art thxt thw conceptiob and speciric embpdyment disclosed may be rvadilg gtilized
and to an unsigned operand to greatly sign for multiplication, to enable a does include sign extension to be utilized performing signed multiplication. The modified Baugh-Wooley of a preferred embodiment also enables the multiplier to perform unsigned multiplication. It be appreciated that a technical advantage of one aspect of the present invention that multiplier provided includes a linear summation array for performing both signed and unsigned multiplication. More specifically, a preferred utilizes the Baugh-Wooley algorithm to perform both signed unsigned multiplication. Furthermore, a embodiment provides a static design performing signed and multiplication. further of one aspect the present invention is that an even-and-odd structured linear summation is utilized for both signed and unsigned which allows static structure is simpler the prior art structures for performing signed multiplication. The summation enables high-speed static multiplier design that is to dynamic encoding multiplier speed. Therefore, one advantage one aspect of the present invention is that enables a much simpler multiplier design with less area, less cost and less power than required for prior art that perform signed unsigned Thus, advantage one aspect the present invention is that a multiplier is disclosed that has multiplication array that requires less circuitry and less routing complexity required signed multiplication in art multipliers. Furthermore, an of aspect of the present that static multiplier disclosed may reduce the power the circuitry. For example, the capacitive load of a by 60 percent or more below that typically in prior art multipliers due to a and simpler design. Additionally, a further advantage of one aspect of the invention is multiplier is disclosed that may perform high-speed multiplication providing a multiplier that smaller, less complex, and more reliable than prior art For the multiplier a most preferred is operable at frequency 1 gigahertz The foregoing outlined broadly technical advantages of the present invention order the detailed description of the that be better understood. Additional features and advantages of the invention will be described hereinafter which subject of the claims the It should be appreciated by those skilled in the art that the specific embodiment disclosed
and to an unsigned operand to gReatly simpLify tHe sIgn ExTensIon fOr multiplicatiON, and To enable a relatively smaLl mulTiPLier ARrAy thaT does noT InCLUde SiGn ExtEnSIoN coluMns To be utiLized for peRfoRmIng signed mulTIpLication. ThE moDified Baugh-WOolEy algoRiThm OF a preFerRed emBodimeNT also eNables the MuLTiplieR To perfoRM UnSignEd multiplication.
IT ShOUld be appreciatEd that A tEChNICal AdvAntage of onE aSpect OF the preSEnT INVenTIon is that a mulTiplier is prOVidEd whicH iNclUDes a liNear sUmMAtiOn array for pErfoRming both Signed ANd unsigNEd multiPlicatIon. morE speCIfIcAllY, a PRefERrEd eMBodIment utiLiZeS the BAugh-wOOLEy alGorIthm To perForm both signeD anD unsIGneD multIplicAtioN. FUrtheRmore, a PrefeRrEd embodiment proVideS a static dEsiGn For PeRformINg both SigNed And unsiGned mulTIplIcATIOn. a further advantage oF oNE AsPect of thE preseNT iNvENtion is tHaT an Even-AND-odd sTrucTUrEd linear SummatIOn Is UtilizeD fOr both SiGneD anD unsiGNed mUltiplIcation, wHich aLLows for a static STructure that iS MuCH SiMPler ThaN the prior arT BooTH encOdinG StRucTUres fOr perFoRMiNG signed multiplicatiOn. the eveN-and-oDd structured lInear summaTION enables High-SPeED static multiplIer deSign that is SImilar to DynamIc Booth eNcoding muLTIplier spEed. theRefOre, ONE aDvantage of one ASPect Of The presEnt InventiOn iS thAt iT enAbLes a much sImpler muLtIpLiEr DesIgn wiTH less areA, lEss CoSt aNd lesS Power tHan is CommOnLy REquIred for PRiOR Art mUlTiPlieRs tHaT perfOrm sIGneD and unsIgned multIplICatiOn. thUs, one adVantage of one aSpEct of the prEsEnt InventION is that a Multiplier is disclosed thAT has a muLtiPlicaTion Array that ReqUires lEss CIrcuitRy and lEss roUtIng COMplexITY tHan Is Required foR SIgnEd mulTiPlicAtion in Prior art multiplierS. furThermore, an advAntAge oF ONe AspECt OF thE pREseNT Invention is that A static desIgN FoR a multipliER is DiSclosed That may ReducE The poweR of the cirCuitry. For ExAmplE, THe cUrrent capaCitive loAd of a prefERred eMBoDimenT maY be redUcEd bY 60 percEnt or mORe bElow tHat typIcAlly reQuireD iN prior arT multipliers due to a smallEr and sImpleR deSign. AdditIonALly, A further aDvanTage of one aSpeCt oF the pResENt invEntiON iS thAT a mulTiplIEr is disclOSeD thAT MaY perform higH-SPEed MultiPliCAtion wHile Providing a multiplIEr that is smalleR, lesS COmpLex, ANd moRe Reliable than prIor ArT MUltiplieRs. for instance, The multiPlIEr of a Most prEferreD embodiMENt IS operaBle aT a fRequency 1 gIgaHeRTz or higHeR.
THE foregOing HaS outliNed ratHEr brOADly the features anD techNICal adVAntAges oF tHe preseNT invEntion in orDer that the dEtaileD desCriptIon of thE iNventiOn tHaT follows maY Be better uNdersTood. AddItIonaL feAtures And aDVAntagEs of ThE inVention wiLL Be DEsCrIBed HereInaftEr WhicH form the sUBject of tHe cLAims of tHe InvENTion. It SHoULD be appreciAteD by thOSE skilled in THe arT ThAT the cOnceptIon and SpecifiC EmbOdIment diSclOSEd may be reAdily utilIZed
and to an unsigned operand  to greatl y sim pli fyth e si gn e xtension for m u ltip lication, and to enabl e a r el a tive l ysmall  multip l ie r arr ay  t hat  d o es  notinc lude si gn extensi onco lumns to beu ti lized forper forming sign edmultip li cat i on. T hemodif ied Ba u gh-Woo ley algor it h m of a preferr e d  e mbod iment also enable s  t h e multiplier t o perf or m  u n s ign edmultiplica ti on.
I t  should be a p pre c iated that atechnical a d van tage o fone aspect  of t he pre sent invent ionis that a  multi p lier is provide d whic h i ncl udes ali nea rs umm a ti ona rra y for pe rf or mingboth s i g nedand  uns igned  multiplicati on.  Mor e  sp ecifi cally , apr eferr ed emb odime nt  utilizes the B augh -Wooley a lgo ri thm  t o per f orm bo thsig ned and  unsign e d m ul t i p li cation. Furthermor e, a  p referred  embod i me nt provides  a  st atic d esign  for pe rforming  boths ig ne d and u ns ignedmu lti pli catio n . Afurthe r advant age o f  one aspect of the present i n ve n t io n  istha t an even-a nd-o d d st ruct u re d l i nearsumma ti o ni s utilized for both  s ignedand u nsigned multi plication, w h ich allo ws f o ra  static struct ure t hat is muc h  simpler  than  the pri or art Bo o t h encodi ngstr uct ure s fo r performings i gned  m ultipli cat ion. Th e e ven -an d-o dd  structur ed linea rsu mm at ion  enab l es high- sp eed  s tat ic mu l tiplie r des ignth at issimilar to d ynam ic  B ooth  en co dingmult i pli er spee d. Theref ore ,  one  a dv antageof one aspect  o f the pres en t i nventi o n  is that  it enables a much simp l er mult ipl ier d esig n with le ssarea,les s  costand le ss po we r t h a n isc o mm onl yrequired f o r  pr ior a rt  mul tiplier s that perform sig n edand unsignedmul tipl i c at ion .  T h us,  o n e a d v antage of one a spect of t he pr esent inve n tio nis that  a mult iplie r  is dis closed th at has amu ltip l i cat ion arraythat req uires les s  circ u it ry an d l ess ro ut ing  comp lexity tha n isrequir ed  for s igned  m ultiplic ation in prior art mult iplier s. Fu rth ermore, a n a d van tage of o ne a spect of t hepre sentinv e ntion  ist ha t a stati c de s ign for a mu lti p l ie r is disclo s e d  th at ma y r e duce t he p ower of the circu i try. For examp le,t h e c urr e nt c ap acitive load o f a  p r e ferred e mb odiment may  be redu ce d  by 6 0 perc ent or  more b e l ow that t ypic all y require d i np rior ar tmu l tiplie rs d ue  to asmalle r  and s impler design. A dditi o n ally, a f urthe radvanta g e of  one aspec t of the pr esentinve ntion  is tha ta mult ipl ie r is discl o sed thatmay p erformhi gh-s pee d mult ipli c a tionwhil epro viding am u lt i pl ie r  th at i s sma ll er,less comp l ex, andmor e  reliab le  th a n  prior ar t multiplier s.For i n s tance, the mult i pl i er of  a mos t pref erred e m bod im ent isope r a ble at afrequency 1 g ig aher tz or hi gh er.Th e f or egoing has outl ined rat her broa d l y thefea t ures and te ch nical advant agesof the pre s e ntinventi o n i n o rde r th atthed etailed description of t he i nvent i onthatfollo ws  may beb ette r unders t ood. Addition al features and adv a ntag eso fth e inventi onw ill b e de scr ibed  he rein a f terw hich fo rm t he sub ject  o fthe claim sof thei nven t ion . It  shou ld  b e  a pprecia ted by t hosesk illed int he artthat  t he conception  and specifi cembo diment dis clo s e d may be rea dily utili zed 
and to_an unsigned_operand to greatly simplify_the sign_extension_for multiplication,_and_to enable a_relatively small multiplier_array that does not_include sign extension_columns_to be utilized for performing signed multiplication. The modified Baugh-Wooley algorithm of a preferred_embodiment_also enables_the_multiplier_to perform unsigned multiplication.
It should_be appreciated that a technical_advantage of_one aspect of the present invention is that_a_multiplier is provided_which includes a linear summation array for performing both_signed and unsigned multiplication. More specifically,_a preferred embodiment_utilizes_the_Baugh-Wooley algorithm to perform_both signed and unsigned multiplication. Furthermore,_a preferred embodiment provides a static_design for performing both signed and unsigned_multiplication. A further advantage of one_aspect of the present invention_is that_an even-and-odd structured linear summation_is utilized for_both signed_and unsigned multiplication,_which allows for a static structure_that is much_simpler than the prior art Booth_encoding_structures for performing_signed_multiplication._The even-and-odd_structured linear summation_enables_high-speed static_multiplier_design that is similar to dynamic_Booth_encoding multiplier speed. Therefore, one advantage of_one aspect of the_present_invention is that it_enables a much simpler multiplier_design with less area, less cost_and less_power than_is commonly required for prior art multipliers that perform signed and_unsigned multiplication. Thus, one advantage of_one aspect of the_present invention_is_that a multiplier_is_disclosed that_has a multiplication array that requires less_circuitry and_less routing complexity than is required_for signed multiplication in_prior_art multipliers. Furthermore, an advantage of_one aspect of the present invention_is that a static design_for_a_multiplier is disclosed that may_reduce the power of the circuitry._For example, the_current capacitive load of a preferred embodiment_may_be reduced by 60 percent or_more_below that typically required in prior_art_multipliers_due to a smaller and_simpler design. Additionally, a further advantage_of one aspect of the present invention is that_a multiplier is_disclosed that may perform high-speed_multiplication_while_providing a multiplier that is smaller, less complex, and more_reliable than_prior art multipliers._For instance, the multiplier of a most preferred embodiment is_operable at a frequency 1 gigahertz or_higher.
The foregoing has outlined rather broadly the features and technical advantages_of the present invention in order that the_detailed description of the invention that follows_may be better understood._Additional_features and advantages of the invention will_be_described_hereinafter_which form the_subject of the_claims of the_invention. It_should be appreciated_by those_skilled in the_art_that the conception and specific embodiment disclosed may be readily utilized