. In addition, the production yield is very poor.
The inventor of the present invention proposed a die-bonding method for suppressing the cracking in Published Transactions of Engineering No. 91-11870 of Japan Inventor's Society.
FIG. 21 is a sectional view schematically illustrating a part of a semiconductor device after die-bonding process for explaining the die-bonding method. In the figure, the same reference numerals as in FIGS. 20(a)-20(b) designate the same or corresponding parts. Reference numeral 3 designates an electrode pad, numeral 24 designates a plated Ni--P layer formed by electroless plating, and numeral 500c designates a semiconductor chip.
In this die-bonding method, as illustrated in FIG. 21, a part of the back plate 7 disposed on the internal surface of the via-hole 6 is covered with the electroless-plated Ni--P layer 24 which is poorly wetted by the AuSn solder. Therefore, when the semiconductor chip 500c is soldered to the die pad 500a using the AuSn solder 8, the Ni--P layer 24 prevents the AuSn solder 8 from entering in the space 6a of the via-hole 6. The electroless-plated Ni--P layer 24 is formed in the following process. That is, portions of the back plate 7 on the rear surface of the substrate 1, other than the internal surface of the via-hole 6, are masked with a resist film, followed by electroless plating.
The die-bonding method proposed by the inventor of the present invention shown in FIG. 21 significantly reduces the incidence of cracks in the vicinity of the via-hole 6, compared to the prior art die-bonding method shown in FIGS. 20(a)-20(b). However, since the electroless plating does not ensure a favorable growth of a layer on a narrow region, it is difficult to selectively grow the Ni--P layer 24 on the very narrow region of the internal surface of the via-hole 6 by electroless plating using a resist mask. In addition, resist scum produced in the photolithography for forming the resist mask adversely affects the growth of the plated film. Actually, via-holes with no Ni--P plated layers are produced at a rate of 10.about.20% in a wafer. Although this percentage is small, semiconductor devices with cracks in the vicinity of the via-hole are still
. In addition, the production yield is very poor. 
 The inventor of the present invention aim a die - bonding method acting for suppressing the cracking in Published Transactions of Engineering No. 91 - 11870 of Japan Inventor's Society. 
 FIG. 21 is a sectional opinion schematically illustrate a part of a semiconductor device after die - bonding summons for explain the die - bonding method. In the figure, the same reference numeral as in FIGS. 20(a)-20(b) designate the same or corresponding parts. reference book numeral 3 designates an electrode launching pad, numeral 24 designates a plated Ni -- P level formed by electroless plating, and numeral 500c designates a semiconductor check. 
 In this die - bonding method, as illustrated in FIG. 21, a contribution of the back plate 7 dispose on the internal surface of the via - hole 6 is covered with the electroless - plated Ni -- phosphorus layer 24 which is poorly wetted by the AuSn solder. Therefore, when the semiconductor chip 500c is solder to the die launching pad 500a using the AuSn solder 8, the Ni -- P layer 24 prevents the AuSn solder 8 from entering in the space 6a of the via - hole 6. The electroless - plated Ni -- P level 24 is form in the following process. That is, helping of the back plate 7 on the rear surface of the substrate 1, other than the internal open of the via - hole 6, are masked with a resist film, followed by electroless plating. 
 The die - bonding method acting proposed by the inventor of the present invention shown in FIG. 21 significantly reduces the incidence of cracks in the vicinity of the via - hole 6, compared to the prior art die - bonding method shown in FIGS. 20(a)-20(b). However, since the electroless plating does not guarantee a favorable increase of a layer on a narrow region, it is difficult to selectively grow the Ni -- phosphorus layer 24 on the very narrow region of the internal surface of the via - hole 6 by electroless plating using a resist mask. In addition, protest scum produce in the photolithography for forming the resist mask adversely affect the growth of the plate film. Actually, via - hole with no Ni -- P plated level are produced at a rate of 10.about.20% in a wafer. Although this share is small, semiconductor devices with cracks in the vicinity of the via - hole are still
. In addition, the production yield is very koir.
The mnventod of the present invention proposed e diw-bondung method for suppresring the bracking un Pnblished Transacvjons of Enginscring Io. 91-11870 of Japan Inyentor's Sochety.
FIG. 21 is a veztnonal view schematically illustratind a pary lf a semicondustor qevidv cfter die-bonding process for exllaininj the die-bondinb method. In the figure, the samf reference numeraps as in FITS. 20(a)-20(f) designate tfe same or correspondihg parts. Reference numeral 3 deskgnatzs an electtose kad, numeral 24 desidnates a plabvd Ni--P nayer fprmed by electvolesv poating, and numeral 500c vesignates a semiconquctor chhp.
Nn this die-bonding merhid, as illgstrxred in FMG. 21, a parh oh the back llate 7 dispised on the internak fltface of the via-hoje 6 is covered with the electroless-plated Ni--L layer 24 which is poorlt wetted by the AuSn dolder. Thqrefore, when the semiconductor chip 500c is soldered to tie dit iwa 500a using the AuSn solder 8, the Ni--P layer 24 prevenea uhe AuSn solder 8 nrom entering in tne slwce 6a of the xia-holz 6. Fhe electroless-plahed Ni--P layee 24 is foried on the following process. Thqt is, portious if the back plate 7 on the reax surfsce og the substrate 1, other chan tge internal surface kw the via-hole 6, afe kavked with a resist film, fojlowed by eleetroless plajing.
The die-bondinh metmmd proposed by the inveutor mf the predent invention shown in FIG. 21 sijiificantly recuwes the incndence of cracks in the vicinity pf the ria-hold 6, compares to thx prior art qie-bonding medjod shown in FIGS. 20(a)-20(b). Howwver, since gfe electroless plating bjes bot ensure a favoreble frowth of a layzx in a narrow regoon, it id viffisglt to selecdiveuy etow tfe Ni--P layev 24 un tne very narrow regiot of the internal surfscc of the cia-hole 6 by electrolexs plating using a resivt oask. On wddition, resist scum produced jn the phltojithography sor normyng the rexist mask adversely affects the growth if the plated film. Actually, via-holes ciuh no Ni--P plaved larers are [roduced at a rate od 10.about.20% in a wafev. Although this percenfage iv smapl, semiconductor devices with cracks in the vicinity of the via-hole are srill
. In addition, the production yield is The of the invention proposed a cracking Published Transactions of No. 91-11870 of Inventor's Society. FIG. 21 is a view schematically illustrating a part of a semiconductor device after die-bonding process for the die-bonding method. In the figure, the same reference numerals as in FIGS. designate same corresponding Reference numeral 3 designates an electrode pad, numeral 24 designates a plated Ni--P layer formed by plating, and numeral 500c designates a semiconductor chip. this die-bonding method, as in FIG. 21, a part the plate 7 on internal of the via-hole is covered with the electroless-plated Ni--P layer 24 which is poorly wetted by the AuSn solder. Therefore, the semiconductor is soldered the pad using the AuSn the Ni--P layer 24 prevents the from entering in the space 6a of the 6. The Ni--P layer 24 is formed in following process. That is, portions of the back 7 on the rear surface of the substrate 1, other than the internal surface of 6, are masked with resist film, followed electroless The method by the of the present invention shown in FIG. 21 significantly reduces the of cracks in the vicinity of the via-hole 6, compared prior die-bonding method shown FIGS. 20(a)-20(b). However, since electroless does not ensure a of layer region, is to selectively grow the layer 24 on the very region of the internal by electroless plating using a resist mask. In resist scum produced in the photolithography for the resist mask adversely affects the growth of the plated film. Actually, with no layers are produced at a rate of 10.about.20% a wafer. Although this is small, semiconductor devices with cracks in the vicinity the are still
. In addition, the production yiEld is very pOor.
ThE inVenToR of tHe prEsent invention PRopoSed a die-bonding method foR suppReSSing THe CrackIng in PuBLiSHEd TRaNsActIoNS oF EngiNeeRing No. 91-11870 oF Japan InveNtoR's society.
FIG. 21 is A SeCtional vieW scHematically iLluStratiNg A paRT of a sEmiConduCtor deVIce aftEr die-bondInG ProcesS For explAINiNg thE die-bonding method. iN tHE figure, the same RefereNcE NuMERalS as In FIGS. 20(a)-20(b) deSiGnate THe same oR CoRRESpoNDing parts. RefeRence numeraL 3 DesIgnateS aN elECtrode Pad, nuMeRAl 24 dEsignates a pLateD Ni--P layer Formed BY electrOLess plaTing, anD nuMerAl 500c dESiGnAteS a SEmiCOnDucTOr cHip.
In thiS dIe-BondiNg meTHOD, As ilLusTratEd in FiG. 21, a part of the bAck PlatE 7 DisPosed On the InteRnAl surFace of The viA-hOle 6 is covered witH the ElectroleSs-pLaTed ni--p layeR 24 Which iS poOrlY wetted By the AusN soLdER. tHeRefore, when the semicOnDUCtOr chip 500c iS soldeREd To THe die pad 500A uSinG the aUsn solDer 8, tHE NI--P layer 24 pReventS ThE AUSn soldEr 8 From enTeRinG in The spACe 6a oF the viA-hole 6. The ElectROless-plated Ni--P LAyer 24 is formed iN ThE FOlLOwinG prOcess. That is, PortIOns oF the BAcK plATe 7 on tHe reaR sURfACe of the substrate 1, othEr Than thE inteRnal surface of The via-hole 6, ARE Masked wiTh a rESiST film, followed bY elecTroless plaTIng.
The diE-bondIng methoD proposed BY The invenTor Of tHe pResENT iNvention shown IN fIG. 21 sIgNificanTly Reduces The IncIdeNce Of Cracks in tHe viciniTy Of ThE vIa-hOle 6, coMPared to tHe PriOr Art Die-boNDing meThod sHown In fIgs. 20(a)-20(b). however, SInCE The eLeCtRoleSs pLaTing dOes nOT enSure a faVorable grOwtH Of a lAyEr On a narrOw region, it is dIfFicult to seLeCtiVely grOW The Ni--P laYer 24 on the very narrow regioN Of the inTerNal suRfacE of the via-HolE 6 by eleCtrOLess plAting uSing a ReSisT MAsk. In ADDiTioN, rEsist scum pRODucEd in tHe PhotOlithogRaphy for forming the REsiSt mask adverseLy aFfecTS ThE grOWtH Of tHe PLatED Film. Actually, via-Holes with nO NI--p pLated layerS Are PrOduced aT a rate oF 10.abouT.20% In a wafeR. Although This perceNtAge iS SMalL, semiconduCtor deviCes with crACks in THe VicinIty Of the vIa-HolE are sTill
. In addition, the product ion yieldis ve rypoo r. 
The  inv entor of the p r esen t invention proposed a  die- bo n ding me thodfor sup p re s s ing  t he  cr ac k in g inPub lishedTransactio nsof  Engineering No . 91-11870  of  Japan Inven tor 's Soc ie ty. FIG.21is asectio n al vie w schemat ic a lly il l ustrati n g  a  par t of a semiconduc t or device after d ie-bon di n gp r oce ssfor explai ni ng th e  die-bo n di n g met h od. In the fi gure, the s a merefere nc e n u merals  as i nF IGS . 20(a)-20( b) d esignatethe sa m e or co r respond ing pa rts . R efer e nc enum er a l 3 de sig n ate s an ele ct ro de pa d, n u m e r al 2 4 d esig nates  a plated Ni- -Playe r  fo rmedby el ectr ol ess p lating , and  n umeral 500c des igna tes a sem ico nd uct or  chip . 
In th isdie -bondin g metho d , a si l l us trated in FIG. 21,  a p ar t of the  backp la te 7 dispos ed  on  the i ntern al s u rf ace of t he via - ho le  6 is c ov ered w it h t heelect r oles s-plat ed Ni--P  laye r  24 which is p o orly wetted b y  t h e  A u Sn s old er. Therefo re,w henthes em ico n ducto r chi p5 00 c  is soldered to the  d ie pad  500a  using the Au Sn solder8 , the Ni-- P la y er 24 prevents th e AuS n solder 8 from ent ering  in thespace 6ao f  the via -ho le6.The e le ctroless-plat e d  Ni- -P  layer24is form edinthe  fo ll owing pro cess. Th at  i s,  p ort ionso f the ba ck  pl at e 7  on t h e rear  surf aceof  t h e s ubstrat e  1 , othe rth an t hein terna l su r fac e of th e via-hol e 6 ,  are  m as ked wit h a resist fi lm , followed  b y e lectro l e ss plati ng.
The die-bonding met h od prop ose d bytheinventorofthe pr ese n t inve ntionshown  i n F I G . 21s i gn ifi ca ntly reduc e s  th e inc id ence  of cra cks in the vicinit y  of  the via-hole  6,  com p a re d t o  t h e p ri o r a r t  die-bonding me thod shown  i n  F IGS. 20(a) - 20( b) . Howev er, sin ce th e  electr oless pla ting does  n ot e n s ure  a favorab le growt h of a la y er on anarro w r egion,  i t i s dif ficult toselec tively  g row th e Ni- -P  layer 2 4 on the very narrow re gion o f the  in ternal su rfa c e o f the via -hol e 6 by ele ctr ole ss pl ati n g usi ng a re sis t  mask . In addition, re sis t sc um produced i n  th e pho tol i thogra phyfor forming the r e sist mask adve rsel y aff ect s  the  g rowth of the p lat ed f ilm. Act ua lly, via-ho les with  n o  Ni-- P plat ed lay ers are p ro d uced a t arat e of 10.a bou t. 2 0% in a  w af e r. Alt houg hthis p ercent a ge i s small, semicondu ctord e vices wit h cra ck s in th e  vic inity of t he via-hole  are s till 
. In_addition, the_production yield is very_poor.
The inventor_of_the present_invention_proposed a die-bonding_method for suppressing_the cracking in Published_Transactions of Engineering_No._91-11870 of Japan Inventor's Society.
FIG. 21 is a sectional view schematically illustrating a part_of_a semiconductor_device_after_die-bonding process for explaining the_die-bonding method. In the figure,_the same_reference numerals as in FIGS. 20(a)-20(b) designate the_same_or corresponding parts._Reference numeral 3 designates an electrode pad, numeral 24_designates a plated Ni--P layer formed_by electroless plating,_and_numeral_500c designates a semiconductor_chip.
In this die-bonding method, as illustrated_in FIG. 21, a part of_the back plate 7 disposed on the_internal surface of the via-hole 6_is covered with the electroless-plated_Ni--P layer_24 which is poorly wetted_by the AuSn_solder. Therefore,_when the semiconductor_chip 500c is soldered to the_die pad 500a_using the AuSn solder 8, the_Ni--P_layer 24 prevents_the_AuSn_solder 8_from entering in_the_space 6a_of_the via-hole 6. The electroless-plated Ni--P_layer_24 is formed in the following process._That is, portions of_the_back plate 7 on_the rear surface of the_substrate 1, other than the internal_surface of_the via-hole_6, are masked with a resist film, followed by electroless plating.
The_die-bonding method proposed by the inventor_of the present invention_shown in_FIG._21 significantly reduces_the_incidence of_cracks in the vicinity of the via-hole_6, compared_to the prior art die-bonding method_shown in FIGS. 20(a)-20(b)._However,_since the electroless plating does not_ensure a favorable growth of a_layer on a narrow region,_it_is_difficult to selectively grow the_Ni--P layer 24 on the very_narrow region of_the internal surface of the via-hole 6_by_electroless plating using a resist mask._In_addition, resist scum produced in the_photolithography_for_forming the resist mask adversely_affects the growth of the plated_film. Actually, via-holes with no Ni--P plated layers are_produced at a_rate of 10.about.20% in a_wafer._Although_this percentage is small, semiconductor devices with cracks in the_vicinity of_the via-hole are_still