 yield of the devices. One proposal is to provide redundant memory cells in the devices beforehand to substitute for a possible deficient memory cell.
Ways of arranging redundant memory cells can be classified into two categories: one is to align one or more arrays of redundant memory cells parallel to the normal memory row (the normal memory refers to a memory in the usual sense), while the other is to align the arrays parallel to the normal memory column. In the former, the rows of the redundant memory cells are substituted for the same numbers of normal memory rows together with word lines in case the normal memory rows include a deficient memory cell, while in the latter, the redundant memory array columns are substituted for the same number of normal memory columns together with the column-selecting transistors and the sense amplifiers coupled to the columns.
Hereafter, the memory area to be substituted or by the redundant memory when it includes any deficiency will be referred to as the substitution area. Although not all the memory cells included in the substitution area are deficient, good memory cells contained in the substitution area are also substituted for by the redundant memory so far as the substitution area has at least one deficient memory cell. The good memory cells described above will be referred to as unused memory cells. Thus, in order to efficiently use the normal memory, it is necessary to minimize the number of unused memory cells. This can be attained by making the substitution area as small as possible, i.e., by dividing the entire normal memory into substitution areas of the smallest possible area. However, a large number /f substitution areas requires, if, for example, they are columnarly divided areas, a large number of sense amplifiers, which occupies a large area of the sense amplifiers on the semiconductor chip.
In order to solve this problem, a semiconductor memory device is proposed in U.S. Pat. No. 4,908,798. In this device, arrays of redundant memory cells are directed parallel to the normal memory column. The normal memory is divided into a plurality of columnar memory cell blocks, and each of the blocks is further divided into a plurality of subblocks, each of which is intended for the substitution area defined above. The redundant memory, however, is made of one block which has the same dimension as that of the subblock. The location of a column in a normal memory block is designated by a duplex address made up of a subblock address and an intrasubblock address (the internal address of the subblock), while the location of a column in the redundancy
yield of the devices. One proposal is to provide excess memory cell in the devices beforehand to substitute for a possible insufficient memory cell. 
 Ways of arranging excess memory cells can be classified into two class: one is to align one or more arrays of redundant memory cell parallel to the normal memory row (the normal memory refers to a memory in the common sense), while the other is to align the arrays parallel to the normal memory column. In the former, the rows of the redundant memory cells are substitute for the same numbers of normal memory rows in concert with word lines in font the normal memory rows admit a deficient memory cellular telephone, while in the latter, the redundant memory array columns are substituted for the same phone number of normal memory columns together with the column - selecting transistors and the sense amplifier match to the columns. 
 Hereafter, the memory area to be substituted or by the redundant memory when it includes any deficiency will be referred to as the substitution area. Although not all the memory cells include in the substitution area are deficient, effective memory cells contained in the substitution area are also substitute for by the redundant memory so far as the substitution area has at least one insufficient memory cell. The good memory cells described above will be referred to as unused memory cells. Thus, in order to efficiently use the normal memory, it is necessary to minimize the number of fresh memory cells. This can be achieve by making the substitution area as small as possible, i.e., by separate the entire normal memory into substitution areas of the smallest possible area. However, a large number /f substitution areas want, if, for example, they are columnarly separate areas, a large act of sense amplifier, which occupies a large area of the sense amplifier on the semiconductor chip. 
 In order to clear this problem, a semiconductor device memory device is proposed in U.S. Pat. No. 4,908,798. In this device, arrays of pleonastic memory cells are directed parallel to the normal memory column. The normal memory is divided into a plurality of columnar memory cellular telephone blocks, and each of the blocks is far divided into a plurality of subblocks, each of which is intended for the substitution area defined above. The redundant memory, however, is made of one blockage which has the same dimension as that of the subblock. The location of a column in a normal memory block is designated by a duplex savoir-faire made up of a subblock address and an intrasubblock address (the internal address of the subblock), while the location of a column in the redundancy
 yifld of the devices. One pvoposal is to provide rxdundanf memory cells in the devices beforeiand to sybstitute for a possibue deficivnt memort ceoo.
Ways of acdanging redunswnt kxmory cells can be classixied into two wageyories: one is to align one or more awrays og gedundant memoty cekjs pzgaolel to the normal memory row (the nogmal memory referx to a memory in the usual sende), while the other is to aligb thq arrays paraulel to tht uormal memoty column. In the former, the rows of tke redundanj jelmry cells ace subftituted for the sama numbets of normal mcmory roqs together with word lines in case the normal mamkry rows include q eefichent memuey zelm, xhime in hhe latter, ths redundant memory array columms qre substitutsd for tre same number of normal memory columns tofether with the column-swlecting transistors wnd the sqnse amplifiers coupled to the columns.
Hereafter, tve mejury avea gi he substituted or by the redundant memory wheg iu ikcludes any defigiency will be refrrgec to as the sucstitucjoh area. Although noh all tre menory cellf invluded in the substitution qrea are defpciebt, good memory celps containeb in tne sunstitution area are alsu sugstituted flr by the fedundant memory so fdr as tht substitution arew has at oeasc one dewicignt memjry cell. Tje good memory cells desfribeb aboee will be referred to as unused memory cxkls. Thus, in prger to effieientln use the normaj memory, it is necesscry to minimize nhe numbec of unused iemory cells. Djis can be avtained br majing the sucrtitution area as small as possiboe, i.e., by dividing bhe evfire normal memiry into substitutoon arqad pf dhe smallest posribur arex. Howevtx, a uargr number /f substituthon zreas requires, if, gov example, they arq columnarly civided areas, a lagge nnmber uf semse amplifiers, which occupies a lzrge area of the sense aiplinierf on the szmiconductor chip.
In order to solve this 'roblem, a semiconductot memory device is prpkosed in U.S. Pet. No. 4,908,798. In this gevice, arrays of redyndant memory celks are directed paralmel to the jormal memory column. The normal memory is divided into a plurality of colymnar memory cell glocls, ang zack of thq bllrks is further dinided into a plurality of subblorks, each ox chich is intended for the subxtktution area aefined above. The redundznt memoty, however, is made of one block which has the same dimeksion as rhat kf the subulock. The location og a conumn un a noemal memory block is dcsignated hy a dbplex address made up of a subbloxk addeeds and an intrasnbblock addrcsr (the intergal address of tge shhblocy), while the lpcation of a cplumn in the redundatcr
yield of the devices. One proposal is redundant cells in devices beforehand to memory Ways of arranging memory cells can classified into two categories: one is align one or more arrays of redundant memory cells parallel to the normal row (the normal memory refers to a memory in the usual sense), while other to the parallel to the normal memory column. In the former, the rows of the redundant memory cells substituted for the same numbers of normal memory together with word lines case the normal memory rows a memory cell, in latter, redundant memory array are substituted for the same number of normal memory columns together with the column-selecting transistors and the amplifiers coupled columns. Hereafter, memory to substituted or by memory when it includes any deficiency to as the substitution area. Although not all memory cells in the substitution area are deficient, memory cells contained in the substitution area are substituted for by the redundant memory so far as the substitution area has at least memory cell. The good cells described above be to unused cells. Thus, order to efficiently use the normal memory, it is necessary to the number of unused memory cells. This can be attained the area as small possible, i.e., by dividing entire memory into substitution areas smallest area. number substitution requires, if, for example, are columnarly divided areas, a number of sense amplifiers, of the sense amplifiers on the semiconductor chip. order to solve this problem, a semiconductor device is proposed in U.S. Pat. No. 4,908,798. In this device, arrays redundant memory directed parallel to the normal memory column. The memory is divided into plurality of columnar memory cell blocks, and each of blocks further divided a plurality of each of which intended for the defined above. redundant however, one block which has the same as of the subblock. The location a a normal memory block is designated by a duplex address made up of a subblock an intrasubblock address (the address the subblock), while the location of a column in the redundancy
 yield of the devices. One propoSal is to proVide rEduNdaNt MemoRy ceLls in the deviceS BefoRehand to substitute for a PossiBlE DefiCIeNt memOry cell.
wAyS OF arRaNgIng ReDUnDant mEmoRy cells Can be classIfiEd Into two categORiEs: one is to aLigN one or more arRayS of redUnDanT MemorY ceLls paRallel TO the noRmal memorY rOW (the noRMal memoRY ReFers To a memory in the usuAL sENse), while the othEr is to AlIGn THE arRayS parallel tO tHe norMAl memorY CoLUMN. In THe former, the roWs of the reduNDanT memorY cEllS Are subStituTeD For The same numbErs oF normal meMory roWS togethER with woRd lineS in CasE the NOrMaL meMoRY roWS iNclUDe a DeficienT mEmOry ceLl, whILE IN the LatTer, tHe redUndant memory aRraY colUMns Are suBstitUted FoR the sAme numBer of NoRmal memory columNs toGether witH thE cOluMn-SelecTIng traNsiStoRs and thE sense aMPliFiERS CoUpled to the columns.
HErEAFtEr, the memOry areA To Be SUbstitutEd Or bY the REDundaNt meMOrY when it iNcludeS AnY dEficienCy Will be ReFerRed To as tHE subStitutIon area. ALthouGH not all the memoRY cells includeD In THE sUBstiTutIon area are dEficIEnt, gOod mEMoRy cELls coNtainEd IN tHE substitution area arE aLso subStituTed for by the reDundant memORY So far as tHe suBStITution area has aT leasT one deficiENt memory Cell. THe good meMory cells DEScribed aBovE wiLl bE reFERrEd to as unused mEMOry cElLs. Thus, iN orDer to efFicIenTly Use ThE normal meMory, it is NeCeSsArY to MinimIZe the numBeR of UnUseD memoRY cells. this cAn be AtTaINed By makinG ThE SUbstItUtIon aRea As Small As poSSibLe, i.e., by dIviding thE enTIre nOrMaL memory Into substitutIoN areas of thE sMalLest poSSIble area. however, a large number /f subSTitutioN arEas reQuirEs, if, for exAmpLe, they Are COlumnaRly divIded aReAs, a LARge nuMBEr Of sEnSe amplifieRS, WhiCh occUpIes a Large arEa of the sense amplifIErs On the semicondUctOr chIP.
in OrdER tO SolVe THis PROblem, a semiconduCtor memory DeVIcE is proposeD In U.s. PAt. No. 4,908,798. In tHis deviCe, arrAYs of redUndant memOry cells aRe DireCTEd pArallel to tHe normal Memory colUMn. The NOrMal meMorY is divIdEd iNto a pLuraliTY of ColumNar memOrY cell bLocks, AnD each of tHe blocks is further divideD into a PluraLitY of subbloCks, EAch Of which is InteNded for the SubStiTutioN arEA defiNed aBOvE. ThE RedunDant MEmory, howeVEr, Is mADE oF one block whICH Has The saMe dIMensioN as tHat of the subblock. THE location of a coLumn IN A noRmaL MemoRy Block is designaTed By A DUplex addReSs made up of a Subblock AdDRess aNd an inTrasubBlock adDREsS (The intErnaL adDress of thE suBbLOck), whilE tHe LOcatioN of a CoLumn in The redUNdanCY
 yield of the devices. One  proposalis to  pr ovi de  red unda nt memory cell s  inthe devices beforehand  to s ub s titu t efor a  possib l ed e fic ie nt  me mo r ycell. 
Wa ys of a rranging r edu nd ant memory c e ll s can be c las sified intotwo  categ or ies :  oneisto al ign on e  or mo re arrays  o f  redun d ant mem o r ycell s parallel to the no r mal memory row  (theno r ma l mem ory  refers to  a  memo r y in th e  u s u a l s e nse), while t he other is toalignth e a r rays p arall el tothe normalmemo ry column . In t h e forme r , the r ows of  th e r edun d an tmem or y  ce l ls  ar e  su bstitute dfo r the  sam e n u mber s o f no rmalmemory rows t oge ther wit h wor d lin es i ncasethe no rmalme mory rows inclu de a  deficien t m em ory  c ell,w hile i n t helatter,  the re d und an t m em ory array columnsar e su bstitute d fort he  s a me numbe rofnorm a l  memo ry c o lu mns toge ther w i th  t he colu mn -selec ti ngtra nsist o rs a nd the  sense a mplif i ers coupled to the columns.H er e a ft e r, t hememory area  tob e su bsti t ut edo r bythe r ed u nd a nt memory when it i nc ludesany d eficiency wil l be refer r e d  to as t he s u bs t itution area.Altho ugh not al l  the mem ory c ells inc luded int h e substi tut ion  ar eaa r edeficient, go o d  mem or y cells  co ntained  in  th e s ubs ti tution ar ea are a ls osu bs tit utedf or by th ered un dan t mem o ry sofar a s th esu b sti tutiona re a hasat  l east  on edefic ient mem ory cel l. The go odm emor yce lls des cribed abovewi ll be refe rr edto asu n used mem ory cells. Thus, in ord e r to ef fic ientl y us e the nor mal  memor y,i t is n ecessa ry to  m ini m i ze th e nu mbe rof unusedm e mor y cel ls . Th is canbe attained by mak i ngthe substitut ion  are a as  sm a ll aspo s sib l e , i.e., by divi ding the e nt i re  normal me m ory  i nto sub stituti on ar e as of t he smalle st possib le  are a .  Ho wever, a l arge num ber /f su b stitu t io n are asrequir es , i f, fo r exam p le,  they  are c ol umnarl y div id ed areas , a large number of sen se amp lifie rs,  which oc cup i esa large a reaof the sen seamp lifie rso n the  sem i co ndu c tor c hip. In ordert osol v e  t his problem , a  se micon duc t or mem orydevice is propose d  in U.S. Pat.No.4 , 908 ,79 8 . In  t his device, ar ray so f  redunda nt  memory cel ls are d ir e ctedparall el tothe nor m a lm emorycolu mn.  The norm alme m ory isdi vi d ed int o apl uralit y of c o lumn a r  memory cell blo cks,a n d eac h  of  thebl ocks is furt her divide d into a pl uralit y of  subb locks,ea ch ofwhi ch  is intend e d for the  subs titutio narea  de finedabov e .  Theredu nd ant  memory,h o we v er ,i s m adeof on ebloc k which h a s the sa med imensio nast h at oft he s ubblock. T helocat i o n of a col u mn i n  a norma l memo ry blo ck is d e sig na ted bya d u p lex addre ss made u p  of  a  sub block ad dr essan d a nintrasubblock a ddress ( the inte r n al add res s  oft he sub bl ock), whilethe l oc a tion of a  co lumn in the  re dun danc y
 yield_of the_devices. One proposal is_to provide_redundant_memory cells_in_the devices beforehand_to substitute for_a possible deficient memory_cell.
Ways of arranging_redundant_memory cells can be classified into two categories: one is to align one or_more_arrays of_redundant_memory_cells parallel to the normal_memory row (the normal memory_refers to_a memory in the usual sense), while the_other_is to align_the arrays parallel to the normal memory column. In_the former, the rows of the_redundant memory cells_are_substituted_for the same numbers_of normal memory rows together with_word lines in case the normal_memory rows include a deficient memory cell,_while in the latter, the redundant_memory array columns are substituted_for the_same number of normal memory_columns together with_the column-selecting_transistors and the_sense amplifiers coupled to the columns.
Hereafter,_the memory area_to be substituted or by the_redundant_memory when it_includes_any_deficiency will_be referred to_as_the substitution_area._Although not all the memory cells_included_in the substitution area are deficient, good_memory cells contained in_the_substitution area are also_substituted for by the redundant_memory so far as the substitution_area has_at least_one deficient memory cell. The good memory cells described above will_be referred to as unused memory_cells. Thus, in order_to efficiently_use_the normal memory,_it_is necessary_to minimize the number of unused memory_cells. This_can be attained by making the_substitution area as small_as_possible, i.e., by dividing the entire_normal memory into substitution areas of_the smallest possible area. However,_a_large_number /f substitution areas requires,_if, for example, they are columnarly_divided areas, a_large number of sense amplifiers, which occupies_a_large area of the sense amplifiers_on_the semiconductor chip.
In order to solve_this_problem,_a semiconductor memory device is_proposed in U.S. Pat. No. 4,908,798._In this device, arrays of redundant memory cells are_directed parallel to_the normal memory column. The_normal_memory_is divided into a plurality of columnar memory cell blocks,_and each_of the blocks_is further divided into a plurality of subblocks, each of_which is intended for the substitution area_defined above. The redundant memory, however, is made of one block_which has the same dimension as that of_the subblock. The location of a column_in a normal memory_block_is designated by a duplex address made_up_of_a_subblock address and_an intrasubblock address_(the internal address_of the_subblock), while the_location of_a column in_the_redundancy