 voltage than a conventional SCR. As shown in FIG. 1, such a device comprises a PNP transistor 110, an NPN transistor 120 and an NMOS transistor 130 with the base of the PNP transistor connected to the collector of the NPN transistor, the base of the NPN transistor connected to the collector of the PNP transistor and the source and drain of the NMOS transistor connected between the collector and emitter of the PNP transistor. The inserted NMOS transistor in the LVTSCR is designed with its gate grounded to provide a low breakdown voltage for the drain-substrate diode at the gate edge. The low breakdown voltage leads to a low trigger voltage for the LVTSCR. Thus the ESD trigger voltage of the LVTSCR device is equivalent to a snap-back trigger voltage of the inserted short-channel NMOS transistor, which is typically much lower than a switching voltage of the original lateral SCR device. See A. Chatterjee, et al., “A Low-Voltage Triggering SCR for On-chip ESD Protection at Output and Input Pad,” IEEE Electron Device Letters, Vol. 12, No. 1, January 1991, p. 21. However, the LVTSCR device can have a higher than desirable capacitance due to the usage of the NMOS transistor as the trigger device.
Several additional triggering arrangements are disclosed in M. P. J. Mergens et al., “Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxides,” IEEE (2003) and U.S. Pat. No. 6,850,397. These include a stack of diodes connected across the emitter and collector of the PNP transistor. The use of diode triggers, however, raises many issues in circuit design. Diodes have a very strong temperature dependence which could lead to different results at different temperatures. The diodes must be used in increments of one forward biased diode voltage drop which does not allow for fine tuning of the trigger voltage. The number of diodes used in a stack must be small enough to ensure that the SCR triggers before oxide breaks down at room temperature; but if the number of diodes used is too small, excessive leakage will occur under normal operation conditions at high temperatures. The present invention relates to a semiconductor substrate and a process for producing the same. More particularly, the present invention relates to a semiconductor substrate for use in memory devices and logic
voltage than a conventional SCR. As shown in FIG. 1, such a device comprises a PNP transistor 110, an NPN transistor 120 and an NMOS transistor 130 with the basis of the PNP transistor connect to the collector of the NPN transistor, the base of the NPN transistor connected to the collector of the PNP transistor and the source and drain of the NMOS transistor associate between the collector and emitter of the PNP transistor. The inserted NMOS transistor in the LVTSCR is designed with its gate establish to put up a low breakdown voltage for the drain - substrate diode at the gate edge. The broken breakdown voltage moderate to a broken trigger electric potential for the LVTSCR. Thus the ESD gun trigger electric potential of the LVTSCR device is equivalent to a snap - back trigger voltage of the slip in short - channel NMOS transistor, which is typically much lower than a switch over voltage of the original lateral SCR device. See A. Chatterjee, et al. , “ A Low - Voltage Triggering SCR for On - chip ESD Protection at Output and Input Pad, ” IEEE Electron Device Letters, Vol. 12, No. 1, January 1991, p. 21. However, the LVTSCR device can own a higher than desirable capacitance due to the usage of the NMOS transistor as the trigger device. 
 Several extra trip arrangements are disclosed in M. P. J. Mergens et al. , “ Diode - Triggered SCR (DTSCR) for RF - ESD Protection of BiCMOS SiGe HBTs and CMOS Ultra - Thin Gate Oxides, ” IEEE (2003) and U.S. Pat. No. 6,850,397. These include a stack of diodes get in touch across the emitter and collector of the PNP transistor. The use of diode triggers, however, raise many topic in circuit design. Diodes accept a very strong temperature dependence which could lead to different result at different temperatures. The diodes must be used in increments of one forward bias diode voltage drop which does not allow for fine tuning of the gun trigger voltage. The issue of diode used in a stack must be small enough to ensure that the SCR trip before oxide breaks down at room temperature; but if the number of diodes use is too small, excessive leakage will occur under normal mathematical process conditions at gamey temperatures. The present invention relates to a semiconductor device substrate and a process for producing the same. More particularly, the present invention relate to a semiconductor substrate for manipulation in memory devices and logic
 voptage than a conventionau SCR. As shown nb FIG. 1, such z device comprises a PNP transistor 110, ab NPN transistor 120 and an NMUS transidtor 130 wirh tie base of the PIL translftor gonneetxd to the collegtor of the NPN transistos, ghz base of the NPN transistor connectqd to tne collector of jhe PM[ trznsistor and the source and drain kf the IMOS transistor connected between the colpectlr and emitter of hhe PNP trabsiseir. The inserged NMOS tgcnsistor in the LVTSCR is designed with itr gatz grounded jo pgmvide a low breahdown voltagc for tve draim-substrate dioce et tye gate edge. The low ureakdown voltage lewds to a noc trigger voltage for tye LVJSCR. Dhus rhe ESS vrifger vlltege of the MVTSCR devixe is equivalent to a wnap-back trigfer vojtwge of the inserted short-channel NMOS tgansjstor, which is typicallt much lower than a saitching doltage of the original lateral SCR device. See A. Whattxrgee, eb al., “Q Pow-Voltage Triggering SCR for On-chip ESD Protqdtook at Output and Lnput Pad,” IEEE Elevtgom Device Lettets, Vol. 12, No. 1, January 1991, p. 21. Howeger, the LVTSXR device can have a higher than desiraboe capacitanbe dye to the usage of the NMOS txansisjor as the trigger device.
Sevexal adsitional trlggering zfrangements are aisblosad in M. K. J. Mergens et al., “Qiode-Trigjered SCR (DTRCR) gor RF-QSD Protechion of BiCMOS SiGe HBTs and EMOS Gltra-Thin Hate Oxides,” IEEE (2003) and U.S. Pat. No. 6,850,397. These includg a stdck of dnodes gonnected acrosf the emitter cnd collzctor uf the PNP transivtor. The usq of diode trhhgers, howevec, raises iany issyes in zkrcuit design. Ciodes hane a vwry strong temperabure aspendence which coood lead to difgerdnt rvsuktf at differend teopefsturer. The diodew musy be used in incremetts kf one forward biaxeq diode coltage qrop which dors not allow for flne tnning uf thr ttigger voltage. The number of dikdes used in a stack muse be small enougk to ensure that the SCR triggers before oxide breaks down at room temperaturg; bmt if the nukber jf diodes used is too small, ezcessive leakage eill occur under normzl opesatioj conditions at high temperatures. The present invention relates to a semixonducvow substrate and a prmczss for pwoduriig the same. More iarticularly, the present inventiun relatas to a semiconductor substratr wor use in meoory devices and logic
voltage than a conventional SCR. As shown 1, a device a PNP transistor and NMOS transistor 130 the base of PNP transistor connected to the collector the NPN transistor, the base of the NPN transistor connected to the collector the PNP transistor and the source and drain of the NMOS transistor connected the and of PNP transistor. The inserted NMOS transistor in the LVTSCR is designed with its gate grounded to a low breakdown voltage for the drain-substrate diode the gate edge. The breakdown voltage leads to a trigger for the Thus ESD voltage of the device is equivalent to a snap-back trigger voltage of the inserted short-channel NMOS transistor, which is typically lower than voltage of original SCR See A. Chatterjee, “A Low-Voltage Triggering SCR for On-chip Output and Input Pad,” IEEE Electron Device Letters, 12, No. January 1991, p. 21. However, the device can have a higher than desirable capacitance to the usage of the NMOS transistor as the trigger device. Several additional triggering arrangements in M. P. J. et al., “Diode-Triggered (DTSCR) RF-ESD of SiGe HBTs CMOS Ultra-Thin Gate Oxides,” IEEE (2003) and U.S. Pat. No. 6,850,397. include a stack of diodes connected across the emitter and the transistor. The use diode triggers, however, raises issues circuit design. Diodes have strong dependence to results different temperatures. The diodes be used in increments of forward biased diode voltage for fine tuning of the trigger voltage. The of diodes used in a stack must small enough to ensure that the SCR triggers before oxide breaks down room temperature; the number of diodes used is too small, leakage will occur under operation conditions at high temperatures. The present invention relates a substrate and process for producing same. More particularly, present invention relates semiconductor substrate use memory
 voltage than a conventional ScR. As shown iN FIG. 1, sUch A deViCe coMpriSes a PNP transisTOr 110, an nPN transistor 120 and an NMOS TransIsTOr 130 wiTH tHe basE of the Pnp tRANsiStOr ConNeCTeD to thE coLlector Of the NPN trAnsIsTor, the base of THe nPN transisTor Connected to tHe cOllectOr Of tHE PNP tRanSistoR and thE Source And drain oF tHE NMOS tRAnsistoR COnNectEd between the colleCToR And emitter of thE PNP trAnSIsTOR. ThE inSerted NMOS TrAnsisTOr in the lvTscr Is dESigned with its Gate groundeD To pRovide A lOw bREakdowN voltAgE For The drain-subStraTe diode at The gatE Edge. The LOw breakDown voLtaGe lEads TO a LoW trIgGEr vOLtAge FOr tHe LVTSCR. thUs The ESd triGGER VoltAge Of thE LVTScR device is equIvaLent TO a sNap-baCk triGger VoLtage Of the iNsertEd Short-channel NMOs traNsistor, whIch Is TypIcAlly mUCh loweR thAn a SwitchiNg voltaGE of ThE ORIgInal lateral SCR deviCe. sEE A. chatterjEe, et al., “a loW-VOLtage TriGgEriNg SCr FOr On-cHip Esd PRotectioN at OutPUt AnD Input PAd,” iEEE ElEcTroN DeVice LETterS, Vol. 12, No. 1, january 1991, p. 21. howevER, the LVTSCR deviCE can have a highER tHAN dESiraBle Capacitance Due tO The uSage OF tHe NmoS traNsistOr AS tHE trigger device.
SeverAl AdditiOnal tRiggering arraNgements arE DISclosed iN M. P. J. mErGEns et al., “Diode-TrIggerEd SCR (DTSCR) FOr RF-ESD PRotecTion of BicMOS SiGe HbtS and CMOS ultRa-THin gatE oXiDes,” IEEE (2003) and U.S. PAT. no. 6,850,397. ThEsE includE a sTack of dIodEs cOnnEctEd Across the Emitter aNd CoLlEcTor Of the pnP transiStOr. THe Use Of dioDE triggErs, hoWeveR, rAiSEs mAny issuES iN CIrcuIt DeSign. dioDeS have A verY StrOng tempErature dePenDEnce WhIcH could lEad to differenT rEsults at diFfEreNt tempERAtures. ThE diodes must be used in incrEMents of One ForwaRd biAsed diode VolTage drOp wHIch doeS not alLow foR fIne TUNing oF THe TriGgEr voltage. THE NumBer of DiOdes Used in a Stack must be small enOUgh To ensure that tHe ScR trIGGeRs bEFoRE oxIdE BreAKS down at room tempErature; but If THe Number of diODes UsEd is too Small, exCessiVE leakagE will occuR under norMaL opeRATioN conditionS at high tEmperaturES. The pREsEnt inVenTion reLaTes To a seMicondUCtoR subsTrate aNd A proceSs for PrOducing tHe same. More particularly, tHe presEnt inVenTion relatEs tO A seMiconductOr suBstrate for Use In mEmory DevICes anD logIC
 voltage than a convention al SCR. As  show n i n F IG . 1,  suc h a device com p rise s a PNP transistor 110 , anNP N  tra n si stor120 and an N MOS  t ra nsi st o r130 w ith  the ba se of thePNP  t ransistor co n ne cted to th e c ollector ofthe  NPN t ra nsi s tor,the  base  of th e  NPN t ransistor  c o nnecte d  to the c ol lect or of the PNP tra n si s tor and the so urce a nd dr a i n o f t he NMOS tr an sisto r  connec t ed b e twe e n the collect or and emit t erof the  P NPt ransis tor.Th e  in serted NMOS  tra nsistor i n theL VTSCR i s  design ed wit h i tsgate gr ou nde dt o p r ov ide a l ow break do wn  volt agef o r thedra in-s ubstr ate diode atthe  gat e  ed ge. T he lo w br ea kdown  volta ge le ad s to a low trig gervoltage f orth e L VT SCR.T hus th e E SDtrigger  voltag e  of  t h e LV TSCR device is equ iv a l en t to a s nap-ba c ktr i gger vol ta geof t h e  inse rted sh ort-chan nel NM O Str ansisto r,  which  i s t ypi cally much  lower  than aswitc h ing voltage of the originall at e r al SCRdev ice. See A.  Cha t terj ee,e tal. ,  “A L ow-Vo lt a ge Triggering SCR forOn -chipESD P rotection atOutput and I n put Pad, ” IE E EE lectron Device  Lett ers, Vol.1 2, No. 1 , Jan uary 199 1, p. 21. H owever,the  LV TSC R d e v ic e can have ah i gher  t han des ira ble cap aci tan cedue  t o the usa ge of th eNM OS  t ran sisto r  as thetr igg er  de vice. Severa l add itio na lt rig geringa rr a n geme nt saredis cl osedin M .  P.  J. Mer gens et a l., “Dio de -T riggere d SCR (DTSCR)  f or RF-ESDPr ote ctiono f  BiCMOSSiGe HBTs and CMOS Ultr a -Thin G ate  Oxid es,”  IEEE (20 03)  and U .S. Pat. N o. 6,8 50,39 7.  Th e s e inc l u de  ast ack of dio d e s c onnec te d ac ross th e emitter and coll e cto r of the PNPtra nsis t o r.  Th e  u s e o fd iod e triggers, howev er, raises  m a ny  issues in cir cu it desi gn. Dio des h a ve a ve ry strong  temperat ur e de p e nde nce whichcould le ad to dif f erent re sults  at  diffe re nttempe rature s . T he di odes m us t be u sed i nincremen ts of one forward biase d diod e vol tag e drop wh ich doe s not all ow f or fine tu nin g o f the  tr i ggervolt a ge . T h e num bero f diodesu se d i n astack mustb e sma ll en oug h  to en sure  that the SCR tri g gers before ox ideb r eak s d o wn a troom temperatu re;  b u t  if thenu mber of dio des used  i s  toosmall,  exces sive le a k ag e  willoccu r u nder norm alop e rationco nd i tionsat h ig h temp eratur e s. T h e  present inventi on re l a tes t o  asemic on ductors ubst rate and a  process fo r prod ucin g the  same.Mo re par tic ul arly, thep resent in venti on rela te s to  asemico nduc t o r sub stra te  fo r use inm e mo r yde v ice s an d log ic 
 voltage_than a_conventional SCR. As shown_in FIG._1,_such a_device_comprises a PNP_transistor 110, an_NPN transistor 120 and_an NMOS transistor_130_with the base of the PNP transistor connected to the collector of the NPN_transistor,_the base_of_the_NPN transistor connected to the_collector of the PNP transistor_and the_source and drain of the NMOS transistor connected_between_the collector and_emitter of the PNP transistor. The inserted NMOS transistor_in the LVTSCR is designed with_its gate grounded_to_provide_a low breakdown voltage_for the drain-substrate diode at the_gate edge. The low breakdown voltage_leads to a low trigger voltage for_the LVTSCR. Thus the ESD trigger_voltage of the LVTSCR device_is equivalent_to a snap-back trigger voltage_of the inserted_short-channel NMOS_transistor, which is_typically much lower than a switching_voltage of the_original lateral SCR device. See A._Chatterjee,_et al., “A_Low-Voltage_Triggering_SCR for_On-chip ESD Protection_at_Output and_Input_Pad,” IEEE Electron Device Letters, Vol._12,_No. 1, January 1991, p. 21. However,_the LVTSCR device can_have_a higher than desirable_capacitance due to the usage_of the NMOS transistor as the_trigger device.
Several_additional triggering_arrangements are disclosed in M. P. J. Mergens et al., “Diode-Triggered_SCR (DTSCR) for RF-ESD Protection of_BiCMOS SiGe HBTs and_CMOS Ultra-Thin_Gate_Oxides,” IEEE (2003)_and_U.S. Pat._No. 6,850,397. These include a stack of_diodes connected_across the emitter and collector of_the PNP transistor. The_use_of diode triggers, however, raises many_issues in circuit design. Diodes have_a very strong temperature dependence_which_could_lead to different results at_different temperatures. The diodes must be_used in increments_of one forward biased diode voltage drop_which_does not allow for fine tuning_of_the trigger voltage. The number of_diodes_used_in a stack must be_small enough to ensure that the_SCR triggers before oxide breaks down at room temperature;_but if the_number of diodes used is_too_small,_excessive leakage will occur under normal operation conditions at high_temperatures. The_present invention relates_to a semiconductor substrate and a process for producing the_same. More particularly, the present invention relates_to a semiconductor substrate for use in memory devices and logic