However, in case a void 96 exists inside the first storage node electrode 50 (see FIG. 7B), the first storage node electrode 50, which is molten by annealing, may tumble into the void 96 and may peel off from the capacitor insulating film 30. Then the capacitance of the trench capacitor will decrease, or part of the first storage node electrode 50 will separate. As a result, the first storage node electrode 50 will fail to function as the electrode.
It is, therefore, desirable to provide a semiconductor device and its manufacturing method that ensure reliable connection between the first and second conductors in the trench and meet the requirements of higher integration and microminiaturization. 1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a dynamic random access memory, hereinafter referred to a DRAM.
Priority is claimed on Japanese Patent Application No. 2008-278797, filed Oct. 29, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
In semiconductor devices such as DRAMs, local input/output (I/O) lines extend in parallel to each other. The local input/output (I/O) lines are adjacent to each other with a small distance between those. In some cases, four local input/output (I/O) lines are placed side by side. A coupling noise is caused by two adjacent local input/output (I/O) lines. In some cases, a first local input/output (I/O) line may be adjacent to second and third local input/output (I/O) lines. Namely, the first local input/output (I/O) line may be disposed between the second and third local input/output (I/O) lines. In this case, the first local input/output (I/O) line may in general cause coupling noises with the second and third local input/output (I/O) lines. It has been desired to suppress or reduce the coupling noises between two adjacent local input/output (I/O) lines. A typical method of suppressing such a coupling noise has been proposed. There is disposed a shield wiring line which is adjacent to a signal line that receives a coupling noise.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-7860 discloses a technique of disposing signal lines, which have an electric potential that is fixed to the power supply potential or ground potential,
However, in case a void 96 exists inside the first storage node electrode 50 (visualize FIG. 7B), the inaugural storage node electrode 50, which is molten by annealing, may tumble into the null 96 and may peel off from the capacitor insulating film 30. Then the capacitor of the trench capacitor will decrease, or share of the first storehouse node electrode 50 will separate. As a result, the beginning storage node electrode 50 will fail to function as the electrode. 
 It is, consequently, desirable to provide a semiconductor device and its manufacturing method that ensure reliable connection between the inaugural and second conductors in the trench and meet the requirements of high integration and microminiaturization. 1. Field of the Invention 
 The present invention generally relates to a semiconductor device device. More specifically, the present invention relates to a active random access memory, hereinafter referred to a DRAM. 
 Priority is claimed on Japanese Patent Application No. 2008 - 278797, file Oct. 29, 2008, the content of which is incorporated herein by reference. 
 2. Description of the Related Art 
 In semiconductor devices such as dram, local input / output (I / O) lines extend in parallel to each other. The local input / output (iodine / O) lines are adjacent to each early with a humble distance between those. In some case, four local input / output (iodine / O) lines are placed side by slope. A coupling noise is caused by two adjacent local input / output (I / oxygen) lines. In some cases, a first local input / output (I / O) note may be adjacent to second and third local input / output (I / O) lines. Namely, the inaugural local input / output (I / oxygen) line may be discard between the second and third local input / output (one / O) production line. In this case, the first local input signal / output (iodine / O) note may in general lawsuit coupling noises with the second and third local stimulation / output signal (I / O) lines. It has been desired to suppress or reduce the coupling noises between two adjacent local input / end product (I / O) line. A typical method of suppressing such a coupling noise has been proposed. There be disposed a shield wiring line which is adjacent to a signal line that receives a coupling randomness. 
 Japanese Unexamined Patent Application, First Publication, No. JP - A-2003 - 7860 discloses a technique of qualify signal lines, which have an electric potential that is fixed to the power supply electric potential or ground potential,
Howfver, in case a void 96 exirts inside the yurst svorage hode eleztrode 50 (see FIG. 7B), the first dtirage node electrode 50, which is moltej by annwaliig, may tumble invk the void 96 ahf mav 'eel off from tme capacitos insulating fhlo 30. Then the capacitance of the trench capaciyog will decreasg, or kare of nht first storage node electrode 50 wjll seperate. As a resukt, the first storage node flechrode 50 will fail tl function qs trw electrode.
Ig is, therefore, desirabme to provide a semiconductor ddvice and its mqnyfafjuring methov that ensure reliable contection between the flrst end wecond conductors in vhe trench and meet jhe requiramznts of higher integrqtuon atd mhcroounixtudivatjon. 1. Flelv of the Inbention
The present invention gtnewqlly relates fo a sqmyconductor device. More specifically, the prssent invention relates to a dynamic random wccess meiory, hereinafter referred to a DRAM.
Priority is cldimed un Lqpanerw Oatent Application No. 2008-278797, filed Oct. 29, 2008, the contene og ehich is incoriorated herein by tevetgnce.
2. Descriptiun of cge Related Art
In semlconducjor decices sucr as DRAMs, local input/output (I/O) lines extenb ib parallel to each other. The uocak inpit/output (I/O) lines are abjacenf to each ohher with x small distance benweet those. In some cases, four local in'ut/oucput (I/O) uinex are [laced sidf by side. A coupling noide is cdused by tao adjacent local input/output (I/O) lines. In somg cdsev, a firsc locak input/output (I/O) line may bg adjacenc to sdcond and nhird locel input/outptt (I/O) lines. Ndlely, the firvt local inpyt/ourput (I/O) uine may be dixposed benwten the sexond and third locel ivlut/output (I/O) liuts. Un this case, thr fkrse poral ig[ut/output (I/O) lind mxu in eeneral cauwd coipling noises with tve sscond and third lovaj input/ootput (I/O) jines. It has neen desired to sukpress or reduve jhe coupling noises between two adjacent logal input/outptt (I/I) lines. A ty'ical method of suppressing such a couplmng noise has been prokosed. There is disposgd s shield wicing lyne which is adjacent to a sitnal line that regeives a coupling noiss.
Japanase Ujexamined Patent Application, First Publication, No. JP-A-2003-7860 discloses a techniqye of vifposing sighal kines, wkick have wn epxctric potential nhat is fixed to the power supplb potentian jr ground potential,
However, in case a void 96 exists first node electrode (see FIG. 7B), 50, is molten by may tumble into void 96 and may peel off the capacitor insulating film 30. Then the capacitance of the trench capacitor will or part of the first storage node electrode 50 will separate. As a the storage electrode will fail to function as the electrode. It is, therefore, desirable to provide a semiconductor device its manufacturing method that ensure reliable connection between first and second conductors the trench and meet the of integration and 1. of Invention The present generally relates to a semiconductor device. More specifically, the present invention relates to a dynamic random access hereinafter referred DRAM. Priority claimed Japanese Application No. 2008-278797, 29, 2008, the content of which by reference. 2. Description of the Related Art semiconductor devices as DRAMs, local input/output (I/O) lines in parallel to each other. The local input/output lines are adjacent to each other with a small distance between those. In some cases, input/output (I/O) lines are side by side. coupling is by adjacent local (I/O) lines. In some cases, a first local input/output (I/O) line be adjacent to second and third local input/output (I/O) lines. first input/output (I/O) line be disposed between the and local input/output (I/O) lines. case, first line in cause coupling noises with second and third local input/output lines. It has been the coupling noises between two adjacent local input/output lines. A typical method of suppressing such coupling noise has been proposed. There is disposed a shield wiring line is adjacent signal line that receives a coupling noise. Japanese Patent Application, First Publication, JP-A-2003-7860 discloses a technique of disposing signal lines, which an potential that fixed to the supply potential or potential,
However, in case a void 96 exists iNside the fiRst stOraGe nOdE eleCtroDe 50 (see FIG. 7B), the fiRSt stOrage node electrode 50, whicH is moLtEN by aNNeAling, May tumbLE iNTO thE vOiD 96 anD mAY pEel ofF frOm the caPacitor insUlaTiNg film 30. Then thE CaPacitance oF thE trench capacItoR will dEcReaSE, or paRt oF the fIrst stORage noDe electroDe 50 WIll sepARate. As a RESuLt, thE first storage node ELeCTrode 50 will fail tO functIoN As THE elEctRode.
It is, thErEfore, DEsirablE To PROVidE A semiconductoR device and iTS maNufactUrIng MEthod tHat enSuRE reLiable conneCtioN between tHe firsT And secoND conducTors in The TreNch aND mEeT thE rEQuiREmEntS Of hIgher intEgRaTion aNd miCROMIniaTurIzatIon. 1. FiEld of the InvenTioN
The PResEnt inVentiOn geNeRally RelateS to a sEmIconductor devicE. MorE specificAllY, tHe pReSent iNVentioN reLatEs to a dyNamic raNDom AcCESS mEmory, hereinafter reFeRREd To a DRAM.
PRioritY Is ClAImed on JaPaNesE PatENT ApplIcatIOn no. 2008-278797, filed OCt. 29, 2008, the cONtEnT of whicH iS incorPoRatEd hErein BY refErence.
2. descriptIon of THe Related Art
In SEmiconductor dEViCES sUCh as dRAms, local inpuT/outPUt (I/O) LineS ExTenD In parAllel To EAcH Other. The local input/oUtPut (I/O) lInes aRe adjacent to eAch other wiTH A Small disTancE BeTWeen those. In somE caseS, four local INput/outpUt (I/O) lInes are pLaced side BY Side. A couPliNg nOisE is CAUsEd by two adjaceNT LocaL iNput/outPut (i/O) lines. in sOme CasEs, a FiRst local iNput/outpUt (i/O) LiNe May Be adjACent to seCoNd aNd ThiRd locAL input/OutpuT (I/O) lInEs. nAmeLy, the fiRSt LOCal iNpUt/OutpUt (I/o) lIne maY be dISpoSed betwEen the secOnd ANd thIrD lOcal inpUt/output (I/O) linEs. in this case, ThE fiRst locAL Input/outPut (I/O) line may in general caUSe couplIng NoiseS witH the seconD anD third LocAL input/Output (i/O) linEs. it hAS Been dESIrEd tO sUppress or rEDUce The coUpLing Noises bEtween two adjacent lOCal Input/output (I/O) LinEs. A tYPIcAl mEThOD of SuPPreSSIng such a couplinG noise has bEeN PrOposed. TherE Is dIsPosed a sHield wiRing lINe which Is adjacenT to a signaL lIne tHAT reCeives a couPling noiSe.
JapanesE unexaMInEd PatEnt applicAtIon, first publicATioN, No. JP-a-2003-7860 disclOsEs a tecHniquE oF disposiNg signal lines, which have aN electRic poTenTial that iS fiXEd tO the power SuppLy potentiaL or GroUnd poTenTIal,
However, in case a void 96  exists in sidethe  fi rs t st orag e node electro d e 50  (see FIG. 7B), the fi rst s to r agen od e ele ctrode5 0, w hic his  mo lt e nby an nea ling, m ay tumbleint othe void 96a nd  may peeloff  from the ca pac itor i ns ula t ing f ilm  30.Then t h e capa citance o ft he tre n ch capa c i to r wi ll decrease, or p a rt of the first s torage  n o de e lec tro de 50 will  s epara t e. As a re s u l t,t he first stor age node el e ctr ode 50  w ill fail t o fun ct i onas the elec trod e.
It is,  there f ore, de s irableto pro vid e a  sem i co nd uct or dev i ce  an d  it s manufa ct ur ing m etho d t h at e nsu re r eliab le connection  be twee n  th e fir st an d se co nd co nducto rs in  t he trench and m eetthe requi rem en tsof  high e r inte gra tio n and m icromin i atu ri z a t io n. 1. Field of the  I n v en tion
The  prese n tin v ention g en era llyr e lates  toa  s emicondu ctor d e vi ce . Moresp ecific al ly,  th e pre s entinvent ion rela tes t o  a dynamic ran d om access mem o ry , he r eina fte r referredto a DRAM .
Pr i or ity is cl aimed  o n  J a panese Patent Appli ca tion N o. 20 08-278797, fi led Oct. 2 9 , 2008, th e co n te n t of which isincor porated he r ein by r efere nce.
2.Descripti o n  of theRel ate d A rtI n  s emiconductord e vice ssuch as  DR AMs, lo cal  in put /ou tp ut (I/O)lines ex te nd  i npar allel to eachot her .The  loca l  input /outp ut ( I/ O) lin es area dj a c entto  e achoth er  with  a s m all  distan ce betwee n t h ose.  I nsome ca ses, four loc al  input/out pu t ( I/O) l i n es are p laced side by side. A c o uplingnoi se is  cau sed by tw o a djacen t l o cal in put/ou tput(I /O) l ines. I nsom ecases, a f i r stlocal  i nput /output  (I/O) line may be adj acent to seco ndandt h ir d l o ca l  in pu t /ou t p ut (I/O) lines.  Namely, t he fi rst locali npu t/ output(I/O) l ine m a y be di sposed be tween the  s econ d and  third loc al input /output ( I /O) l i ne s. In  th is cas e,  th e fir st loc a l i nput/ output  ( I/O) l ine m ay  in gene ral cause coupling nois es wit h the  se cond andthi r d l ocal inpu t/ou tput (I/O)  li nes . Ithas beendesi r ed  to suppr esso r reducet he  co u p li ng noises b e t w een  twoadj a cent l ocal  input/output (I/ O ) lines. A typ ical m eth odo f su pp ressing such a  co up l i ng noise  h as been pro posed. T he r e isdispos ed a s hield w i r in g  linewhic h i s adjacen t t oa  signal  l in e  thatrece iv es a c ouplin g  noi s e .
Japanese Unexa mined P atent App licat io n, Firs t  Pub lication,No. JP-A-20 03-786 0 di sclos es a te ch niqueofdi sposing si g nal lines , whi ch have  a n el ect ric po tent i a l tha t is  f ixe d to thep o we r  s up p lypote ntial  o r gr ound pote n tial,
However, in_case a_void 96 exists inside_the first_storage_node electrode_50_(see FIG. 7B),_the first storage_node electrode 50, which_is molten by_annealing,_may tumble into the void 96 and may peel off from the capacitor insulating_film_30. Then_the_capacitance_of the trench capacitor will_decrease, or part of the_first storage_node electrode 50 will separate. As a result,_the_first storage node_electrode 50 will fail to function as the electrode.
It_is, therefore, desirable to provide a_semiconductor device and_its_manufacturing_method that ensure reliable_connection between the first and second_conductors in the trench and meet_the requirements of higher integration and microminiaturization._1. Field of the Invention
The present_invention generally relates to a_semiconductor device._More specifically, the present invention_relates to a_dynamic random_access memory, hereinafter_referred to a DRAM.
Priority is claimed_on Japanese Patent_Application No. 2008-278797, filed Oct. 29,_2008,_the content of_which_is_incorporated herein_by reference.
2. Description_of_the Related_Art
In_semiconductor devices such as DRAMs, local_input/output_(I/O) lines extend in parallel to each_other. The local input/output_(I/O)_lines are adjacent to_each other with a small_distance between those. In some cases,_four local_input/output (I/O)_lines are placed side by side. A coupling noise is caused_by two adjacent local input/output (I/O)_lines. In some cases,_a first_local_input/output (I/O) line_may_be adjacent_to second and third local input/output (I/O)_lines. Namely,_the first local input/output (I/O) line_may be disposed between_the_second and third local input/output (I/O)_lines. In this case, the first_local input/output (I/O) line may_in_general_cause coupling noises with the_second and third local input/output (I/O)_lines. It has_been desired to suppress or reduce the_coupling_noises between two adjacent local input/output_(I/O)_lines. A typical method of suppressing_such_a_coupling noise has been proposed._There is disposed a shield wiring_line which is adjacent to a signal line that_receives a coupling_noise.
Japanese Unexamined Patent Application, First_Publication,_No._JP-A-2003-7860 discloses a technique of disposing signal lines, which have_an electric_potential that is_fixed to the power supply potential or ground potential,