 one another. An orthogonal grid of "scribe line" (kerf) areas extends between adjacent dies, and sometimes contain test structures, for evaluating the fabrication process. These scribe lines areas, and anything contained within them, will be destroyed when the dies are singulated from the wafer. The singulated (separated) dies are then individually packaged, and may be tested after packaging.
Under ordinary circumstances, pressure to maximize the useful, or productive area of a wafer dictates that scribe line area be kept as small as possible. Dies are laid out on a wafer in a pattern that is packed as tightly as possible. Scribe line widths are only large enough to ensure that the dies can be separated without damage to the area of the dies.
Circuits and active elements on the dies are created while the dies are still together (un-singulated) on the wafer by ion deposition, electron beam lithography, plasma etching, mechanical polishing, sputtering, and numerous other methods which are well known to those skilled in the art of semiconductor fabrication. These processes are highly developed and are capable of producing extremely complicated circuits on the dies at a relatively low cost.
The complexity of integrated circuits is limited, in part, by the purity of the semiconductor wafers available. These wafers contain minuscule defects which may be distributed randomly throughout the wafer, especially the surface where integrated circuit elements are fabricated. The larger the integrated circuit (i.e., the greater its "die size"), the greater the probability that it will be affected by such a defect. Integrated circuits which intersect a defect on the semiconductor wafer are generally rendered non-functional, and therefore useless. Improvements in the wafer production process are yielding purer wafers with smaller defect sizes and densities.
By reducing the size of individual circuit elements, e.g. transistors, it has become possible to place more circuitry in the same area (e.g., die site) which would previously have been occupied by larger circuit elements of lesser complexity. However, the same size reductions which enable greater circuit complexity also render the resulting smaller circuits more sensitive to more minuscule defects in the semiconductor wafer.
Trade-offs between circuit complexity (i.e., number of transistors and circuit area) and anticipated yield (i.e., the number of "good" circuits per wafer) are made by integrated circuit manufacturers based upon a number of factors. The higher the yield, the less a circuit costs the manufacturer to produce, permitting a lower market price.
Among the problems faced by integrated circuit manufacturers are
one another. An orthogonal grid of " scribe line " (kerf) areas unfold between adjacent dies, and sometimes contain trial structure, for evaluating the fabrication summons. These scribe wrinkle areas, and anything incorporate within them, will be destroyed when the dies are singulated from the wafer. The singulated (separate) dies are then individually packaged, and may be test after promotion. 
 Under ordinary circumstances, atmospheric pressure to maximize the useful, or productive sphere of a wafer dictates that scribe line area be continue as small as potential. Dies are put out on a wafer in a pattern that is packed as tightly as possible. Scribe line width are only large enough to ensure that the dies can be separated without damage to the sphere of the die. 
 Circuits and active elements on the dies are created while the dies are still together (un - singulated) on the wafer by ion deposition, electron beam lithography, plasma etch, mechanical polishing, sputtering, and numerous early method which are well known to those skilled in the artwork of semiconductor fabrication. These processes are highly developed and are capable of producing extremely complicated circuits on the dies at a relatively gloomy cost. 
 The complexity of integrated circuits is limited, in character, by the purity of the semiconductor wafers available. These wafers contain minuscule defect which may be distributed randomly throughout the wafer, especially the surface where integrated circuit element are fabricated. The larger the integrated racing circuit (i.e., the greater its " die size "), the greater the probability that it will be affected by such a defect. incorporate circuits which intersect a defect on the semiconductor wafer are generally rendered non - running, and therefore useless. Improvements in the wafer production process are yield purer wafers with small defect sizes and densities. 
 By reducing the size of individual circuit elements, for example transistors, it has become possible to place more circuitry in the like area (e.g., die site) which would previously have been occupied by big tour elements of lesser complexity. However, the like size reductions which enable greater circuit complexity also render the resulting smaller circuit more sensitive to more minuscule defects in the semiconductor wafer. 
 Trade - offs between circuit complexity (i.e., number of transistor and circuit area) and anticipated yield (i.e., the number of " good " circuits per wafer) are made by incorporate circuit manufacturers based upon a number of factors. The higher the yield, the less a circuit costs the manufacturer to produce, permit a lower market price. 
 Among the problems faced by integrated tour manufacturers are
 onf another. An orthogonal nrid of "scribe lnbe" (kerh) areas extends between adjacent dies, and slmwtimew contain test structufes, for enaluating the dabricatioi process. Thess scrnbx lines areas, akd anything contained witviv chem, will be destroyed when the dies are simgklated from thg waftr. Ehe apnnulated (separated) dies are then jndividlally packaged, anc may be tested after packwginh.
Under ordinary cigcumstances, prefwure to maxioize the useful, or prosuctive area of a wafer dictater thac scribe libe arfd be kept aw smajl as possible. Dies dre laic out on a wafcr in a pattern that is packev as tightly as possyble. Scrite line widths are inoy latge etougf to enauce fhat tje vies can be separated qithout damage to tne qrea of the djes.
Cirsuyts and active elements on the dies are crsated while the dies arw still together (un-sijgulated) jn the wafer by ion deposition, electron beam lithmgrapiy, plcwma egxhlng, mechanical polishing, sputtering, and numerjhs onher methods whicm are well known tp hhpfe skilled in the axf kf semiconductor fwbricatyon. Tyese proctsses are highly developed and aee capable oy peoducing extremely complicateb circoits om the dies at a relativzly los cost.
The clmplexity uf integrated cifcupts hs limitta, in part, by the [urity of the semicovducjor wafqrs availahle. Tmase wafers contain minudcgle defectd which may be distributed randomly throughouj tve fafer, es'ecialky the surfacq where integrcted cireuit euements arv fabricaved. The largqr the integrdjed circuit (i.x., the grewter its "die sixd"), the greater yhe probaynlity thar it will be affecbed bi auch a defect. Iuuegtqted circuits ehizh ynnerxesd a defect ot thd sdkiconauctor wafev afe grnerally rendered not-fundtional, and therefprc useless. Improveients in the eafer production pgocesv ace yiekdigg purer wafers with smaller dsfect sizfs wnd densitief.
By vedusing the snze of individual circuit elements, e.g. trensistors, it has becomg possible to place mpve circuitry in tre same asea (e.g., die site) whicy would previousln have been occupied bg largar cigcuit elements of lesser complexity. However, the same size reductions whicy enable greater cjrcuot cokpjzxity ajso ceider the resultinb smaller circuits more sensitite to more mnnuscule defects in the semicpnauctor wafer.
Ttade-offs between circuit ckmplexitu (i.e., number of transistors and vircuit area) and anticipsted yieod (i.e., the nljbxr of "good" circuits ler wayer) arw made vy iktegrated circjit mwnufacturfrs uaszd upon a number of factors. The hugher rhf yield, the less a circuit gorts tge manofacturer to prodhce, lfrmitjing a lower msrket price.
Amomg the problems faceg fy integrated xprcuit manufavturetw are
one another. An orthogonal grid of "scribe areas between adjacent and sometimes contain fabrication These scribe lines and anything contained them, will be destroyed when the are singulated from the wafer. The singulated (separated) dies are then individually packaged, may be tested after packaging. Under ordinary circumstances, pressure to maximize the useful, productive of wafer that scribe line area be kept as small as possible. Dies are laid out on a in a pattern that is packed as tightly possible. Scribe line widths only large enough to ensure the can be without to area of the Circuits and active elements on the dies are created while the dies are still together (un-singulated) on wafer by electron beam plasma mechanical sputtering, and numerous which are well known to those art of semiconductor fabrication. These processes are highly and are of producing extremely complicated circuits on dies at a relatively low cost. The complexity integrated circuits is limited, in part, by the purity of the semiconductor wafers available. These minuscule defects which may distributed randomly throughout wafer, the where circuit elements fabricated. The larger the integrated circuit (i.e., the greater its "die the greater the probability that it will be affected by defect. circuits which intersect defect on the semiconductor are rendered non-functional, and therefore in wafer yielding wafers smaller defect sizes and By reducing the size of circuit elements, e.g. transistors, place more circuitry in the same area (e.g., site) which would previously have been occupied larger circuit elements of lesser complexity. However, the same size reductions which greater circuit render the resulting smaller circuits more sensitive to minuscule defects in the wafer. Trade-offs between circuit complexity (i.e., number of transistors circuit and anticipated (i.e., the number "good" circuits per are made by manufacturers based a of the yield, the less a circuit the to produce, permitting a lower price. problems faced by integrated circuit manufacturers are
 one another. An orthogonal griD of "scribe lIne" (keRf) aReaS eXtenDs beTween adjacent dIEs, anD sometimes contain test sTructUrES, for EVaLuatiNg the faBRiCATioN pRoCesS. THEsE scriBe lInes areAs, and anythIng CoNtained withiN ThEm, will be deStrOyed when the dIes Are sinGuLatED from The Wafer. the sinGUlated (Separated) DiES are thEN indiviDUAlLy paCkaged, and may be tesTEd AFter packaging.
UNder orDiNArY CIrcUmsTances, presSuRe to mAXimize tHE uSEFUl, oR Productive areA of a wafer diCTatEs that ScRibE Line arEa be kEpT As sMall as possiBle. DIes are laiD out on A Wafer in A Pattern That is PacKed As tiGHtLy As pOsSIblE. scRibE LinE widths aRe OnLy larGe enOUGH To enSurE thaT the dIes can be separAteD witHOut DamagE to thE areA oF the dIes.
CirCuits AnD active elements On thE dies are cReaTeD whIlE the dIEs are sTilL toGether (uN-singulATed) On THE WaFer by ion deposition, ElECTrOn beam liThograPHy, PlASma etchiNg, MecHaniCAL poliShinG, SpUttering, And numERoUs Other meThOds whiCh Are WelL knowN To thOse skiLled in thE art oF Semiconductor fABrication. ThesE PrOCEsSEs arE hiGhly developEd anD Are cApabLE oF prODucinG extrEmELy COmplicated circuits oN tHe dies At a reLatively low coSt.
The complEXITy of inteGratED cIRcuits is limiteD, in paRt, by the purITy of the sEmicoNductor wAfers avaiLABle. These WafErs ConTaiN MInUscule defects WHIch mAy Be distrIbuTed randOmlY thRouGhoUt The wafer, eSpeciallY tHe SuRfAce Where INtegrateD cIrcUiT elEmentS Are fabRicatEd. ThE lArGEr tHe integRAtED CircUiT (i.E., the GreAtEr its "Die sIZe"), tHe greatEr the probAbiLIty tHaT iT will be Affected by sucH a Defect. InteGrAteD circuITS which inTersect a defect on the semiCOnductoR waFer arE genErally renDerEd non-fUncTIonal, aNd therEfore UsEleSS. improVEMeNts In The wafer prODUctIon prOcEss aRe yieldIng purer wafers with SMalLer defect sizeS anD denSITiEs.
BY ReDUciNg THe sIZE of individual ciRcuit elemeNtS, E.g. TransistorS, It hAs Become pOssible To plaCE more ciRcuitry in The same arEa (E.g., diE SIte) Which would PreviousLy have beeN OccupIEd By larGer CircuiT eLemEnts oF lesseR ComPlexiTy. HoweVeR, the saMe sizE rEductionS which enable greater circUit comPlexiTy aLso render The REsuLting smalLer cIrcuits morE seNsiTive tO moRE minuSculE DeFecTS in thE semIConductor WAfEr.
TRADe-Offs between CIRCuiT compLexITy (i.e., nuMber Of transistors and cIRcuit area) and anTiciPATed YieLD (i.e., tHe Number of "good" ciRcuItS PEr wafer) aRe Made by integRated cirCuIT manuFacturErs basEd upon a NUMbER of facTors. the Higher the YieLd, THe less a CiRcUIt costS the MaNufactUrer to PRoduCE, Permitting a lower MarkeT PRice.
AMOng The prObLems facED by iNtegrated cIrcuit manufActureRs arE
 one another. An orthogona l grid of"scri belin e"  (ke rf)areas extendsb etwe en adjacent dies, andsomet im e s co n ta in te st stru c tu r e s,fo reva lu a ti ng th e f abricat ion proces s.Th ese scribe l i ne s areas, a ndanything con tai ned wi th int hem,wil l bedestro y ed whe n the die sa re sin g ulatedf r om  the  wafer. The singu l at e d (separated)dies a re th e n  in div idually pa ck aged, and may be t e ste d  after packag ing.
Undero rdi nary c ir cum s tances , pre ss u reto maximize  the  useful,or pro d uctivea rea ofa wafe r d ict ates th at  sc ri b e l i ne  ar e a b e kept a ssm all a s po s s i b le.Die s ar e lai d out on a wa fer  ina  pa ttern  that  ispa ckedas tig htlyas  possible. Scri be l ine width s a re  on ly  larg e  enoug h t o e nsure t hat the die sc a n  b e separated withou td a ma ge to th e area of  t h e dies.Ci rcu itsa n d act ivee le ments on  the d i es  a re crea te d whil ethe  di es ar e  sti ll tog ether (u n-sin g ulated) on the wafer by iond ep o s it i on,ele ctron beamlith o grap hy,p la sma etchi ng, m ec h an i cal polishing, sput te ring,and n umerous other  methods w h i c h are we ll k n ow n  to those skil led i n the arto f semico nduct or fabri cation. T h e se proce sse s a rehig h l ydeveloped and a re c ap able of  pr oducing  ex tre mel y c om plicatedcircuits  o nth edie s ata  relativ el y l ow  co st.
T h e comp lexit y of  i nt e gra ted cir c ui t s  isli mi ted,  in  p art,by t h e p urity o f the sem ico n duct or  w afers a vailable. The se  wafers co nt ain  minus c u le defec ts which may be distrib u ted ran dom ly th roug hout thewaf er, es pec i ally t he sur facewh ere i ntegr a t ed  ci rc uit elemen t s  ar e fab ri cate d. Thelarger the integra t edcircuit (i.e. , t he g r e at eri ts "di es ize " ) , the greater t he probabi li t ythat it wi l l b eaffecte d by su ch ad efect.Integrate d circuit swhic h int ersect a d efect on  the semi c onduc t or  wafe r a re gen er all y ren deredn on- funct ional,  a nd the refor euseless.  Improvements in the wa fer pr oduct ion  processare yie lding pur er w afers with  sm all er de fec t  size s an d  d ens i ties. 
Byr educing t h esiz e of  individual c i rcu it el eme n ts, e. g. t ransistors, it ha s  become possib le t o pla cem oreci rcuitry in the  sa me a rea (e.g .,  die site)which wo ul d  prev iously  havebeen oc c u pi e d by l arge r c ircuit el eme nt s  of les se rc omplex ity.  H owever , thes ames i ze reductions wh ich e n a ble g r eat er ci rc uit com p lexi ty also re nder the re sultin g sm aller  circui ts  moresen si tive to mo r e minuscu le de fects i nthesem icondu ctor w afer. 
Tra de -of fs betwee n ci r cu it com plex ity ( i. e.,number of transist ors and cir cu ita r ea) an d  a n t icipated y iel d (i. e . , the numb e r of "g o od" c ircuit s perwafer)a rema de by i nte g r ated circ uit manuf a ctu re rs b ased upo na nu mb erof  factors. The h igher th e yield, t he les s a circ u it cos ts  the manufac turer  t o  produc e ,  pe rmittin g  alow ermark etpric e .
Among the problems fac ed b y int e gra ted c ircui tmanufact u rers  are
 one_another. An_orthogonal grid of "scribe_line" (kerf)_areas_extends between_adjacent_dies, and sometimes_contain test structures,_for evaluating the fabrication_process. These scribe_lines_areas, and anything contained within them, will be destroyed when the dies are singulated_from_the wafer._The_singulated_(separated) dies are then individually_packaged, and may be tested_after packaging.
Under_ordinary circumstances, pressure to maximize the useful, or_productive_area of a_wafer dictates that scribe line area be kept as_small as possible. Dies are laid_out on a_wafer_in_a pattern that is_packed as tightly as possible. Scribe_line widths are only large enough_to ensure that the dies can be_separated without damage to the area_of the dies.
Circuits and active_elements on_the dies are created while_the dies are_still together_(un-singulated) on the_wafer by ion deposition, electron beam_lithography, plasma etching,_mechanical polishing, sputtering, and numerous other_methods_which are well_known_to_those skilled_in the art_of_semiconductor fabrication._These_processes are highly developed and are_capable_of producing extremely complicated circuits on the_dies at a relatively_low_cost.
The complexity of integrated_circuits is limited, in part,_by the purity of the semiconductor_wafers available._These wafers_contain minuscule defects which may be distributed randomly throughout the wafer,_especially the surface where integrated circuit_elements are fabricated. The_larger the_integrated_circuit (i.e., the_greater_its "die_size"), the greater the probability that it_will be_affected by such a defect. Integrated_circuits which intersect a_defect_on the semiconductor wafer are generally_rendered non-functional, and therefore useless. Improvements_in the wafer production process_are_yielding_purer wafers with smaller defect_sizes and densities.
By reducing the size_of individual circuit_elements, e.g. transistors, it has become possible_to_place more circuitry in the same_area_(e.g., die site) which would previously_have_been_occupied by larger circuit elements_of lesser complexity. However, the same_size reductions which enable greater circuit complexity also render_the resulting smaller_circuits more sensitive to more_minuscule_defects_in the semiconductor wafer.
Trade-offs between circuit complexity (i.e., number of_transistors and_circuit area) and_anticipated yield (i.e., the number of "good" circuits per wafer)_are made by integrated circuit manufacturers based_upon a number of factors. The higher the yield, the less_a circuit costs the manufacturer to produce, permitting_a lower market price.
Among the problems faced_by integrated circuit manufacturers_are