 combination having a frame and removable steps, which may be converted into a ramp. Technical Field
The present invention concerns a turbine for a hydroelectric power plant and a hydroelectric power plant.
Description of the Related Art
WO 2010/026072 A2 discloses a hydroelectric power plant with a flow passage and a turbine in the flow passage, the turbine being connected to a generator by way of a shaft. The flow passage has a first portion with a first narrowing and a second portion of a diameter smaller than that of the enlargement, wherein the turbine is provided in the second portion.
U.S. 2009/0214343 A1 discloses a turbine for a hydroelectric power plant. The turbine has a rotor having a plurality of turbine blades and a guide apparatus which is arranged downstream of the rotor and which functions as a support apparatus. The turbine has a substantially spherical hub and the pitch angle of the turbine blades is adapted to be adjustable. This invention generally relates to data processing systems, and more specifically, the invention relates to data processing systems including hardware accelerators.
Accelerators are special hardware functional units designed to perform certain operations efficiently, as compared to a general purpose processor, and hardware accelerators are often included in processor-based systems such as computer systems to perform specific, predefined tasks in hardware rather than in software. Traditionally, accelerators perform complex parallel transformations on relatively small input data, which makes the accelerators very attractive for performance enhancement. Additionally, in some cases, the hardware acceleration can be more power-efficient than performing the same tasks in software. Power efficiency can be even greater if the hardware accelerators are incorporated on the same semiconductor substrate (“on-chip”) as the processors. Particularly, integrating hardware accelerators onto multi-core chips such as chip multiprocessors (CMP) and/or chip multithreaded (CMT) processors can be efficient, because the accelerator can be shared among the cores/threads.
Currently, there is a large amount of software over-head associated with dispatching a task to a shared hardware accelerator (e.g. on the order of tens of thousands of processor clock cycles). Access to the hardware accelerator is typically managed by the lowest-level and most-privileged layer of software in the system. Managing access in this fashion helps ensure that the hardware accelerator is shared in a secure fashion (preventing one thread/core from disrupting, and particularly corrupting, the task issued by another thread/core to the hardware accelerator), and also
combination having a frame and removable steps, which may be convert into a ramp. Technical Field 
 The present invention refer a turbine for a hydroelectric power plant and a hydroelectric power plant. 
 Description of the Related Art 
 WO 2010/026072 A2 discloses a hydroelectric office plant with a flow passage and a turbine in the stream passage, the turbine being connected to a generator by manner of a shaft. The flow passing has a first dowry with a inaugural narrowing and a second portion of a diameter smaller than that of the enlargement, wherein the turbine is provided in the second portion. 
 U.S. 2009/0214343 A1 unwrap a turbine for a hydroelectric power plant. The turbine has a rotor having a battalion of turbine blades and a guide apparatus which is dress downstream of the rotor and which functions as a documentation apparatus. The turbine has a substantially spherical hub and the pitch angle of the turbine blade is adapted to be adjustable. This invention generally relates to data processing systems, and more specifically, the invention relate to datum processing systems including hardware accelerators. 
 Accelerators are special hardware functional units design to do sealed operations efficiently, as compared to a general function processor, and hardware accelerators are often include in processor - based systems such as computer system to perform specific, predefined tasks in hardware rather than in software. Traditionally, accelerators perform complex parallel transformations on relatively modest input data, which makes the accelerators very attractive for operation enhancement. Additionally, in some cases, the hardware acceleration can be more might - effective than perform the same tasks in software. Power efficiency can be even capital if the hardware accelerators are incorporated on the same semiconductor substrate (“ on - chip ”) as the processors. Particularly, integrating hardware accelerator onto multi - core chips such as check multiprocessors (CMP) and/or chip multithreaded (CMT) processors can be effective, because the accelerator can be shared among the cores / threads. 
 presently, there is a large sum of software over - head associated with dispatch a task to a share hardware accelerator (for example on the order of tens of thousands of processor clock cycle). Access to the hardware accelerator is typically managed by the last - level and most - privileged layer of software in the system. Managing entree in this fashion helps ensure that the hardware accelerator is shared in a secure fashion (preventing one screw thread / kernel from disrupting, and particularly corrupting, the task issued by another thread / kernel to the hardware accelerator), and also
 colbination having a frame and removable steps, wiich mag be conxerted into a ramp. Technical Fueld
Tye present invention cuncerns a turbine for q hydroelerfric power plzkt anb e hydroelectric power platt.
Description mf tke Related Art
WO 2010/026072 A2 discloses a hydrjelectroc power plant wyth s flos passage and a turbine in the flos passaje, the turbine neing connected to a generwtor by way of a shaft. The flow pqssadw has a firsg portion with a first narrowing and a second portion of a diameter wmqllft than that if thv enlargement, wherein the tutbine is proviced in the second portion.
U.S. 2009/0214343 A1 discloses a tutbine for d kydroelectric power poabt. Thg turtine yas a dovor havinh a plurality of turbine blades and a guide a[isratus which is arwagged downstream of the rotor and which xundtions as a support appqratus. The turbine had a substwntially spherical hub and the pitch angle of the turbmnd boaqdw ls adapted to be adjustable. This invention gegsrslky relates to bata processing xydtris, and more skecificcmlg, the invention repates tj datq processyng xystems including hardware qccelerators.
Cccwlerators are specnal hardware funvtionsl units designed to pexform dertain opegations erwiciently, as comoarvd tm a general purpose procesfor, and herdwaxe acceldratprs arq often influded in processor-based systgms suwh as compkter systems to perform specifir, predefined jasns pn hardwaxe ratmer than in sofeware. Traditioually, aceeleragors perfogm complee parallel twansformationv on relativeny small inpyt dqta, whizf makes the acvelerators very atteactive for perforkanzs enhancement. Abbiuiinally, in some cares, tje hwsdware accelaratkon van bd more kjwcr-ewficoent than performing the same tasks in sofywwre. Powet efficiegcy can be evrn greater if the jardwere acrelerayorf are incorporated on the same semicondkctjr substrate (“on-cmip”) ws the proeessors. Particularly, integrating hardwarx accelerators onto mulri-core chips such ax chip multi'rocesfors (CMP) dnd/or chip multithreqded (CMT) processovs can be efficient, bedause dhe afcelerator can be shared among the cores/threads.
Currently, there is a large amounv jf software ovet-head afxociatqd wmti dispatching a tssk to a shared hardware accelecator (e.g. ot che order of tens of thousandx uf processor zlock cycles). Access to tge hardwsre accelerator is typically mamaged by the lowest-level and mosr-privjleged layxr of software in thr systzm. Manqging axcesd in this fasfiom melps ensuge tiat the hardware accelerator is shaeed in a secure fashion ('reventing oke threzd/core from disrupting, and oartizularly corrulting, the task issued by another tvrqad/core to the gardware accglerator), and also
combination having a frame and removable steps, be into a Technical Field The for hydroelectric power plant a hydroelectric power Description of the Related Art WO A2 discloses a hydroelectric power plant with a flow passage and a turbine the flow passage, the turbine being connected to a generator by way of shaft. flow has first portion with a first narrowing and a second portion of a diameter smaller than that the enlargement, wherein the turbine is provided in second portion. U.S. 2009/0214343 discloses a turbine for a power The turbine a having plurality of turbine and a guide apparatus which is arranged downstream of the rotor and which functions as a support The turbine substantially spherical and pitch of the turbine adapted to be adjustable. This invention data processing systems, and more specifically, the invention to data systems including hardware accelerators. Accelerators are hardware functional units designed to perform certain operations as compared to a general purpose processor, and hardware accelerators are often included in processor-based as computer systems to specific, predefined tasks hardware than software. accelerators perform parallel transformations on relatively small input data, which makes the accelerators attractive for performance enhancement. Additionally, in some cases, the hardware be power-efficient than performing same tasks in software. efficiency be even greater if accelerators incorporated semiconductor (“on-chip”) the processors. Particularly, integrating accelerators onto multi-core chips such chip multiprocessors (CMP) and/or be efficient, because the accelerator can be shared the cores/threads. Currently, there is a large of software over-head associated with dispatching a task to a shared hardware (e.g. on of tens of thousands of processor clock cycles). to the hardware accelerator typically managed by the lowest-level and most-privileged layer of in system. Managing in this fashion ensure that the accelerator is shared secure fashion one from corrupting, the task issued by another to hardware accelerator), and also
 combination having a frame anD removable Steps, WhiCh mAy Be coNverTed into a ramp. TeCHnicAl Field
The present invenTion cOnCErns A TuRbine For a hydROeLECtrIc PoWer PlANt And a hYdrOelectrIc power plaNt.
DEsCription of thE reLated Art
WO 2010/026072 a2 diScloses a hydrOelEctric PoWer PLant wIth A flow PassagE And a tuRbine in thE fLOw passAGe, the tuRBInE beiNg connected to a genERaTOr by way of a shafT. The flOw PAsSAGe hAs a First portiOn With a FIrst narROwING And A Second portion Of a diameter SMalLer thaN tHat OF the enLargeMeNT, whErein the turBine Is provideD in the SEcond poRTion.
U.S. 2009/0214343 A1 DiscloSes A tuRbinE FoR a HydRoELecTRiC poWEr pLant. The tUrBiNe has A rotOR HAVing A plUralIty of Turbine blades And A guiDE apParatUs whiCh is ArRangeD downsTream Of The rotor and whicH funCtions as a SupPoRt aPpAratuS. the turBinE haS a substAntiallY SphErICAL hUb and the pitch angle Of THE tUrbine blAdes is ADaPtED to be adjUsTabLe. ThIS InvenTion GEnErally reLates tO DaTa ProcessInG systeMs, And MorE specIFicaLly, the InventioN relaTEs to data procesSIng systems incLUdING hARdwaRe aCcelerators.
acceLEratOrs aRE sPecIAl harDware FuNCtIOnal units designed to PeRform cErtaiN operations efFiciently, aS COMpared to A genERaL Purpose processOr, and Hardware acCEleratorS are oFten inclUded in proCESsor-baseD sySteMs sUch AS CoMputer systems TO PerfOrM specifIc, pRedefinEd tAskS in HarDwAre rather Than in soFtWaRe. trAdiTionaLLy, acceleRaTorS pErfOrm coMPlex paRalleL traNsFoRMatIons on rELaTIVely SmAlL inpUt dAtA, whicH makES thE acceleRators verY atTRactIvE fOr perfoRmance enhanceMeNt. AdditionAlLy, iN some cASEs, the harDware acceleration can be mORe power-EffIcienT thaN performiNg tHe same TasKS in sofTware. POwer eFfIciENCy can BE EvEn gReAter if the hARDwaRe accElEratOrs are iNcorporated on the saME seMiconductor suBstRate (“ON-ChIp”) aS ThE ProCeSSorS. pArticularly, inteGrating harDwARe AcceleratoRS onTo Multi-coRe chips Such aS Chip mulTiprocessOrs (CMP) and/Or Chip MULtiThreaded (CMt) processOrs can be eFFicieNT, bEcausE thE accelErAtoR can bE shareD AmoNg the Cores/tHrEads.
CuRrentLy, There is a Large amount of software ovEr-head AssocIatEd with disPatCHinG a task to a SharEd hardware AccEleRator (E.g. oN The orDer oF TeNs oF ThousAnds OF processoR ClOck CYClEs). Access to tHE HArdWare aCceLErator Is tyPically managed by tHE lowest-level anD mosT-PRivIleGEd laYeR of software in tHe sYsTEM. ManaginG aCcess in this Fashion hElPS ensuRe that The harDware acCELeRAtor is SharEd iN a secure fAshIoN (PreventInG oNE threaD/corE fRom disRuptinG, And pARTicularly corruptIng, thE TAsk isSUed By anoThEr threaD/Core To the hardwAre acceleraTor), and Also
 combination having a fram e and remo vable  st eps ,whic h ma y be converted into  a ramp. Technical Fie ld
Th ep rese n tinven tion co n ce r n s a  t ur bin ef or  a hy dro electri c power pl ant  a nd a hydroel e ct ric powerpla nt.
Descript ion  of th eRel a ted A rtWO 20 10/026 0 72 A2discloses  a hydroe l ectricp o we r pl ant with a flow p a ss a ge and a turbi ne inth e  f l o w p ass age, the t ur bineb eing co n ne c t e d t o  a generatorby way of a sha ft. Th eflo w  passa ge ha sa  fi rst portion  wit h a first  narro w ing and a secon d port ion  of  a d i am et ersm a lle r  t han tha t of the  e nl argem ent, w h e rein  th e tu rbine  is providedinthes eco nd po rtion .
U. S.  2009 /02143 43 A1  d iscloses a turb inefor a hyd roe le ctr ic  powe r  plant . T heturbine  has ar oto rh a v in g a plurality of t ur b i ne  bladesand ag ui de apparatu swhi ch i s arran gedd ow nstreamof the ro to r and w hi ch fun ct ion s a s a s u ppor t appa ratus. T he tu r bine has a sub s tantially sph e ri c a lh ub a ndthe pitch a ngle of t he t u rb ine blade s isad a pt e d to be adjustable.  T his in venti on generallyrelates to d a ta proce ssin g  s y stems, and mor e spe cifically, the inve ntion  relates  to datap r ocessing  sy ste msinc l u di ng hardware a c c eler at ors.
Ac cel erators  ar e s pec ial  h ardware f unctiona lun it sdes igned to perfo rm  ce rt ain  oper a tionseffic ient ly ,a s c ompared to a  gen er al  pur pos eproce ssor ,  an d hardw are accel era t orsar eoften i ncluded in pr oc essor-base dsys tems s u c h as com puter systems to perfor m  specif ic,  pred efin ed tasksinhardwa rer atherthan i n sof tw are . Tradi t i on all y,  accelerat o r s p erfor mcomp lex par allel transformati o nson relatively  sm alli n pu t d a ta ,  wh ic h  ma k e s the accelerat ors very a tt r ac tive for p e rfo rm ance en hanceme nt. A d ditiona lly, in s ome cases ,theh a rdw are accele ration c an be mor e  powe r -e ffici ent  thanpe rfo rming  the s a metasks  in so ft ware.Power  e fficienc y can be even greater i f thehardw are  accelera tor s  ar e incorpo rate d on the s ame  se micon duc t or su bstr a te  (“ o n-chi p”)a s the pro c es sor s .  P articularly , i nte grati ngh ardwar e ac celerators onto m u lti-core chips  suc h aschi p  mul ti processors (CM P)an d / or chipmu ltithreaded  (CMT) p ro c essor s canbe eff icient, b ec a use th e ac cel erator ca n b es hared a mo ng the co res/ th reads. 
Curre n tly, t here is a largeamoun t of so f twa re ov er -head a s soci ated withdispatching  a tas k to  a sh ared ha rd ware a cce le rator (e.g .  on the o rderof tens  o f th ous ands o f pr o c essor  clo ck  cy cles). Ac c e ss to  t h e h ardw are a cc eler ator is t y picallyman a ged byth e l o w est-le v el a nd most-pr ivi leged l ayer of so f twar e  i n  thesystem . Mana ging ac c ess  i n thisfas h i on helpsensure th a t t he  har dware ac ce lera to r i sshared in a sec ure fash ion (pre v e ntingone thre a d/core  f rom disrupti ng, a nd particu l a rly  corrup t ing , t hetask  is sued by another thread/core t o th e har d war e acc elera to r), anda lso
 combination_having a_frame and removable steps,_which may_be_converted into_a_ramp. Technical Field
The_present invention concerns_a turbine for a_hydroelectric power plant_and_a hydroelectric power plant.
Description of the Related Art
WO 2010/026072 A2 discloses a hydroelectric power_plant_with a_flow_passage_and a turbine in the_flow passage, the turbine being_connected to_a generator by way of a shaft. The_flow_passage has a_first portion with a first narrowing and a second_portion of a diameter smaller than_that of the_enlargement,_wherein_the turbine is provided_in the second portion.
U.S. 2009/0214343 A1_discloses a turbine for a hydroelectric_power plant. The turbine has a rotor_having a plurality of turbine blades_and a guide apparatus which_is arranged_downstream of the rotor and_which functions as_a support_apparatus. The turbine_has a substantially spherical hub and_the pitch angle_of the turbine blades is adapted_to_be adjustable. This_invention_generally_relates to_data processing systems,_and_more specifically,_the_invention relates to data processing systems_including_hardware accelerators.
Accelerators are special hardware functional units_designed to perform certain_operations_efficiently, as compared to_a general purpose processor, and_hardware accelerators are often included in_processor-based systems_such as_computer systems to perform specific, predefined tasks in hardware rather than_in software. Traditionally, accelerators perform complex_parallel transformations on relatively_small input_data,_which makes the_accelerators_very attractive_for performance enhancement. Additionally, in some cases,_the hardware_acceleration can be more power-efficient than_performing the same tasks_in_software. Power efficiency can be even_greater if the hardware accelerators are_incorporated on the same semiconductor_substrate_(“on-chip”)_as the processors. Particularly, integrating_hardware accelerators onto multi-core chips such_as chip multiprocessors_(CMP) and/or chip multithreaded (CMT) processors can_be_efficient, because the accelerator can be_shared_among the cores/threads.
Currently, there is a_large_amount_of software over-head associated with_dispatching a task to a shared_hardware accelerator (e.g. on the order of tens of_thousands of processor_clock cycles). Access to the_hardware_accelerator_is typically managed by the lowest-level and most-privileged layer of_software in_the system. Managing_access in this fashion helps ensure that the hardware accelerator_is shared in a secure fashion (preventing_one thread/core from disrupting, and particularly corrupting, the task issued by_another thread/core to the hardware accelerator), and also