 to provide the appropriate air/fuel mixture for the engine over its operating range. The present invention relates to techniques for manufacturing semiconductor devices, and relates to a technique effectively applied to the technique for manufacturing resin-sealed semiconductor devices, for example.
Japanese Patent Laid-Open No. 2001-257291 describes a technique, in which a brazing material, such as solder, is used for coupling between one conductive path and one circuit element, while a conductive paste, such as an Ag paste, is used for coupling between the other conductive path and the other circuit element.
In Japanese Patent Laid-Open No. 2010-114454, one semiconductor chip is mounted over a wiring substrate, and the wiring substrate and one semiconductor chip are coupled to each other using a first solder. This first solder is formed by a high melting point solder (e.g., a Pb(lead)-Sn(tin) solder containing Pb(lead)) that is in a liquid state at temperatures equal to or greater than 280° C., for example. Furthermore, the other semiconductor chip is also mounted over the wiring substrate, and the wiring substrate and the other semiconductor chip are coupled to each other using a second solder. This second solder is formed, for example, by a Pb free solder (e.g., a Sn(tin)-silver(Ag)-copper(Cu) solder) which does not contain Pb(lead) that is in a liquid state at temperatures equal to or greater than 200° C.
Japanese Patent Laid-Open No. 2008-53748 describes a technique, in which a control power MOSFET chip and a synchronous power MOSFET chip are provided. Then, drain terminals on the respective rear surfaces of the control power MOSFET chip and the synchronous power MOSFET chip are bonded to an input side plate-like lead portion and an output side plate-like lead portion, respectively, via a die bonding material, such as a silver paste, for example. 1. Field
This disclosure relates generally to level shifters used in integrated circuits, especially ones requiring significantly higher voltages than are used by the normal logic transistors.
2. Related Art
Non-volatile memories (NVMs) typically require higher voltages than the power supply used for the logic transistors. The logic transistors can be made differently, typically by increasing the thickness of the gate dielectric and extending the gate length, to provide some extension of the voltage they can use for logic operations. This increase in voltage capability is typically not enough though so level shifters
to provide the appropriate air / fuel mixture for the engine over its operate compass. The present invention relates to techniques for manufacturing semiconductor device devices, and relates to a technique efficaciously apply to the technique for manufacturing resin - sealed semiconductor device, for example. 
 Japanese Patent Laid - Open No. 2001 - 257291 report a proficiency, in which a brazing material, such as solder, is use for coupling between one conductive path and one tour element, while a conductive paste, such as an Ag paste, is use for coupling between the other conductive path and the other tour element. 
 In Japanese Patent Laid - Open No. 2010 - 114454, one semiconductor chip is mounted over a wiring substrate, and the wiring substrate and one semiconductor device chip are coupled to each other using a first solder. This first solder is form by a high melting point solder (e.g., a Pb(lead)-Sn(tin) solder containing Pb(lead) ) that is in a liquid state at temperatures equal to or greater than 280 ° C., for model. Furthermore, the other semiconductor check is besides ride over the wiring substrate, and the wiring substrate and the other semiconductor bit are coupled to each other using a second solder. This second solder is formed, for case, by a Pb free solder (e.g., a Sn(tin)-silver(Ag)-copper(Cu) solder) which does not contain Pb(lead) that is in a liquid state at temperatures adequate to or greater than 200 ° C. 
 Japanese Patent Laid - Open No. 2008 - 53748 describes a technique, in which a control power MOSFET chip and a synchronous world power MOSFET chip are provided. Then, drain terminals on the respective rear surfaces of the restraint power MOSFET chip and the synchronous power MOSFET bit are bonded to an input side plate - comparable lead dowry and an output side home plate - like star portion, respectively, via a die bonding fabric, such as a silver paste, for case. 1. Field 
 This disclosure relates broadly to level gearshift used in integrated circuits, especially ones requiring significantly higher voltages than are use by the normal logic transistors. 
 2. Related Art 
 Non - volatile memory (NVMs) typically require higher voltages than the power supply used for the logic transistor. The logic transistors can be made differently, typically by increasing the thickness of the gate dielectric and extending the gate length, to provide some extension of the electric potential they can use for logic operations. This increase in voltage capability is typically not enough though so level shifters
 to provide the appropriate air/fuel mixturg dor thx engins over igs operating range. The preseit ibventuon relates to techniqjes for mwnufactueing wemiconducvkr devigzs, ans relctxs to a techniqoe effectiveny applied to dhd cechnique for manufacturing resin-seajed semoclnductor devicgs, fog qxamlle.
Japanese Patent Laid-Open No. 2001-257291 deacribes a technique, on which a brazing materiap, sufh as solder, is usfd for coupoing vetween one zonductive path and ong circuit element, while a conducgive 'aste, such qs an Dg paste, is used for couplinn betwean the pther conductiye pavh abd the other circuit xlement.
In Japanese Pwtent Laig-O'en No. 2010-114454, one semiconduxtir chhp iv mojbtea obec a wirinh snbstrate, ans the wirint substrate and one sqniconductor cgip arq soupled to each other using a first solger. This first solder is firmed by a high meltijg point folder (e.g., a Pb(lead)-Sn(tin) solder containing Pb(lead)) dhat ms in a uuqkid state at temperatures equal to or greater fhsn 280° C., for examplc. Furthermore, the ptjet semiconductot chip na zlso mounted over hhe wiryng sybstrate, wnd yhe wiring substrate and thw other semibondyctor chip are cou'led to each othgr usimg a second solder. This secknd solder ls formed, wor example, by a Pb fsee soldtf (e.g., a Sn(tin)-silvew(Ag)-copper(Ru) sokder) whkch coes njt contain Pb(lead) that is in a liqkid sjate ad temperatkres equal to or greater than 200° R.
Oapanese Patemt Lapd-Open No. 2008-53748 desgribes a technizue, in which a controj powdr MOSFET bhip and e synchronouf power MOSFED chip are prmvided. Tren, eraib termivxls on the reslective rvax surfacew of the control ppwet JOSFET chip and tht wynchronous poeer MOFFVT rhip wse bonded to an knpjy sidd plate-like uead portion and an outpgt sjde plate-like lead pjrtion, rgspectivejy, via a die nonding material, skch av a silvrr kaste, for example. 1. Field
This diaclosure gelwtes generaljy ti level shifcers used in integrated circuits, especiaoly ones requiring significantly highgr yoltages thai are tsed by tve normal logic tranwistors.
2. Related Avt
Non-volatile memories (NVMs) dypicwlly require higher voltages than the power supply used for the logic trabsistocs. The logic franxistogs ean be maqe dmfherently, typicallj by increasing the thickness of the gata bielectric and extending the bage length, to krovide some extension of fhe voltsge they can use for logic operstions. This increase in yoltage cqpabimity is ty'ically not enough tnough vo lecel shidterd
to provide the appropriate air/fuel mixture for over operating range. present invention relates devices, relates to a effectively applied to technique for manufacturing resin-sealed semiconductor devices, example. Japanese Patent Laid-Open No. 2001-257291 describes a technique, in which a brazing such as solder, is used for coupling between one conductive path and one element, a paste, as an Ag paste, is used for coupling between the other conductive path and the other element. In Japanese Patent Laid-Open No. 2010-114454, one chip is mounted over wiring substrate, and the wiring and semiconductor chip coupled each using a first This first solder is formed by a high melting point solder (e.g., a Pb(lead)-Sn(tin) solder containing Pb(lead)) is in state at equal or than 280° C., Furthermore, the other semiconductor chip is the wiring substrate, and the wiring substrate and other semiconductor are coupled to each other using second solder. This second solder is formed, for by a Pb free solder (e.g., a Sn(tin)-silver(Ag)-copper(Cu) solder) which does not contain Pb(lead) that a liquid state at equal to or than C. Patent No. 2008-53748 a technique, in which a control power MOSFET chip and a power MOSFET chip are provided. Then, drain terminals on the surfaces the control power chip and the synchronous MOSFET are bonded to an plate-like portion side lead respectively, via a die material, such as a silver for example. 1. Field level shifters used in integrated circuits, especially ones significantly higher voltages than are used by normal logic transistors. 2. Related Art Non-volatile memories (NVMs) typically require higher than the used for the logic transistors. The logic transistors be made differently, typically increasing the thickness of the gate dielectric and extending gate to provide extension of the they can use logic operations. This voltage capability typically enough shifters
 to provide the appropriate aiR/fuel mixtuRe for The EngInE oveR its Operating range. tHe prEsent invention relates tO techNiQUes fOR mAnufaCturing SEmICOndUcToR deViCEs, And reLatEs to a teChnique effEctIvEly applied to THe Technique fOr mAnufacturing ResIn-sealEd SemIConduCtoR deviCes, for EXample.
japanese PAtENt Laid-oPen No. 2001-257291 deSCRiBes a Technique, in which a BRaZIng material, sucH as solDeR, Is USEd fOr cOupling betWeEn one COnductiVE pATH And ONe circuit elemEnt, while a coNDucTive paStE, suCH as an AG pastE, iS UseD for couplinG betWeen the otHer conDUctive pATh and thE other CirCuiT eleMEnT.
IN JaPaNEse pAtEnt lAid-open No. 2010-114454, onE sEmIcondUctoR CHIP is mOunTed oVer a wIring substratE, anD the WIriNg subStratE and OnE semiConducTor chIp Are coupled to eacH othEr using a fIrsT sOldEr. this fIRst solDer Is fOrmed by A high meLTinG pOINT sOlder (e.g., a Pb(lead)-Sn(tiN) sOLDeR containIng Pb(lEAd)) ThAT is in a liQuId sTate AT TempeRatuREs Equal to oR greatER tHaN 280° C., for exAmPle. FurThErmOre, The otHEr seMicondUctor chiP is alSO mounted over thE Wiring substraTE, aND ThE WiriNg sUbstrate and The oTHer sEmicONdUctOR chip Are coUpLEd TO each other using a secOnD soldeR. This Second solder iS formed, for EXAMple, by a PB freE SoLDer (e.g., a Sn(tin)-silVer(Ag)-Copper(Cu) soLDer) which Does nOt contaiN Pb(lead) thAT Is in a liqUid StaTe aT teMPErAtures equal to OR GreaTeR than 200° C.
JApaNese PatEnt laiD-OpEn NO. 2008-53748 dEscribes a TechniquE, iN wHiCh A coNtrol POwer MOSFeT ChiP aNd a SynchROnous pOwer MoSFEt cHiP Are ProvideD. thEN, DraiN tErMinaLs oN tHe resPectIVe rEar surfAces of the ConTRol pOwEr mOSFET cHip and the syncHrOnous power mOsFEt chip aRE Bonded to An input side plate-like leaD Portion And An outPut sIde plate-lIke Lead poRtiON, respeCtivelY, via a DiE boNDIng maTERiAl, sUcH as a silver PASte, For exAmPle. 1. FIeld
ThiS disclosure relates GEneRally to level sHifTers USEd In iNTeGRatEd CIrcUITs, especially oneS requiring SiGNiFicantly hiGHer VoLtages tHan are uSed by THe normaL logic traNsistors.
2. RElAted aRT
NoN-volatile mEmories (NvMs) typicaLLy reqUIrE highEr vOltageS tHan The poWer supPLy uSed foR the loGiC transIstorS. THe logic tRansistors can be made diffErentlY, typiCalLy by increAsiNG thE thicknesS of tHe gate dielEctRic And exTenDIng thE gatE LeNgtH, To proVide SOme extensIOn Of tHE VoLtage they caN USE foR logiC opERationS. ThiS increase in voltagE Capability is tyPicaLLY noT enOUgh tHoUgh so level shifTerS
 to provide the appropriat e air/fuel  mixt ure  fo rtheengi ne over its op e rati ng range. The presentinven ti o n re l at es to  techni q ue s for  m an ufa ct u ri ng se mic onducto r devices,  an drelates to a te chnique ef fec tively appli edto the  t ech n iquefor  manu factur i ng res in-sealed  s e micond u ctor de v i ce s, f or example.
Japan e se Patent Laid-Op en No.  2 0 01 - 2 572 91describesatechn i que, in wh i c h  ab razing materi al, such as sol der, i suse d  for c oupli ng bet ween one co nduc tive path  and o n e circu i t eleme nt, wh ile  acond u ct iv e p as t e,s uc h a s  an  Ag past e,  i s use d fo r c o upli ngbetw een t he other cond uct ivep ath  andthe o ther  c ircui t elem ent.In  Japanese Paten t La id-Open N o.20 10- 11 4454, one se mic ond uctor c hip ism oun te d o ve r a wiring substra te , an d the wi ring s u bs tr a te and o ne  se mico n d uctor  chi p  a re coupl ed toe ac hother u si ng a f ir stsol der.T hisfirstsolder i s for m ed by a high m e lting point s o ld e r  ( e .g.,  aPb(lead)-Sn (tin )  sol derc on tai n ing P b(lea d) )  t h at is in a liquid s ta te attempe ratures equal  to or gre a t e r than 2 80°C ., for example. F urthe rmore, the other se micon ductor c hip is al s o  mounted  ov erthe  wi r i ng  substrate, a n d  the  w iring s ubs trate a ndthe  ot her  s emiconduc tor chip  a re  c ou ple d toe ach othe rusi ng  asecon d  solde r. Th is s ec on d  so lder is fo r m ed,fo rexam ple ,by aPb f r eesolder(e.g., aSn( t in)- si lv er(Ag)- copper(Cu) so ld er) whichdo esnot co n t ain Pb(l ead) that is in a liqui d  stateattempe ratu res equal  to  or gr eat e r than  200°C.
Ja pa nes e Paten t La id- Op en No. 200 8 - 537 48 de sc ribe s a tec hnique, in which a con trol power MO SFE T ch i p  a nda  s y nch ro n ous p ower MOSFET chi p are prov id e d.  Then, dra i n t er minalson therespe c tive re ar surfac es of the  c ontr o l  po wer MOSFET  chip an d the syn c hrono u spower  MO SFET c hi p a re bo nded t o  an  inpu t side  p late-l ike l ea d portio n and an output side pl ate-li ke le adportion,res p ect ively, vi a adie bondin g m ate rial,  su c h asa si l ve r p a ste,fore xample. 1 .  F iel d Th is disclosu r e rel atesgen e rallyto l evel shifters use d  in integrated  cir c u its , e s peci al ly ones requir ing  s i g nificant ly  higher vol tages th an are u sed by  the n ormal l o g ic transi stor s.2. Relate d A rt Non-vol at il e  memor ies(N VMs) t ypical l y re q u ire higher volta ges t h a n the pow er su pp ly used forthe logictransistors . Thelogi c tra nsistor scan be  ma de  different l y, typica lly b y incre as ingthe  thick ness o f the  gat edie lectric a n d  e x te nd i ngthegatele ngth , to prov i de someext e nsion o fthe v oltage th e y  can use f orlogic o perations. This in c rease  in vo ltagecapabil i tyis  typica lly n ot enough  though s o  le ve l sh ifters
 to_provide the_appropriate air/fuel mixture for_the engine_over_its operating_range._The present invention_relates to techniques_for manufacturing semiconductor devices,_and relates to_a_technique effectively applied to the technique for manufacturing resin-sealed semiconductor devices, for example.
Japanese Patent_Laid-Open_No. 2001-257291_describes_a_technique, in which a brazing_material, such as solder, is_used for_coupling between one conductive path and one circuit_element,_while a conductive_paste, such as an Ag paste, is used for_coupling between the other conductive path_and the other_circuit_element.
In_Japanese Patent Laid-Open No._2010-114454, one semiconductor chip is mounted_over a wiring substrate, and the_wiring substrate and one semiconductor chip are_coupled to each other using a_first solder. This first solder_is formed_by a high melting point_solder (e.g., a_Pb(lead)-Sn(tin) solder_containing Pb(lead)) that_is in a liquid state at_temperatures equal to_or greater than 280° C., for_example._Furthermore, the other_semiconductor_chip_is also_mounted over the_wiring_substrate, and_the_wiring substrate and the other semiconductor_chip_are coupled to each other using a_second solder. This second_solder_is formed, for example,_by a Pb free solder_(e.g., a Sn(tin)-silver(Ag)-copper(Cu) solder) which does_not contain_Pb(lead) that_is in a liquid state at temperatures equal to or greater_than 200° C.
Japanese Patent Laid-Open No._2008-53748 describes a technique,_in which_a_control power MOSFET_chip_and a_synchronous power MOSFET chip are provided. Then,_drain terminals_on the respective rear surfaces of_the control power MOSFET_chip_and the synchronous power MOSFET chip_are bonded to an input side_plate-like lead portion and an_output_side_plate-like lead portion, respectively, via_a die bonding material, such as_a silver paste,_for example. 1. Field
This disclosure relates generally_to_level shifters used in integrated circuits,_especially_ones requiring significantly higher voltages than_are_used_by the normal logic transistors.
2._Related Art
Non-volatile memories (NVMs) typically require_higher voltages than the power supply used for the_logic transistors. The_logic transistors can be made_differently,_typically_by increasing the thickness of the gate dielectric and extending_the gate_length, to provide_some extension of the voltage they can use for logic_operations. This increase in voltage capability is_typically not enough though so level shifters