 a given load of products, sensing a temperature within the conveyor oven, determining when a change in load of products has occurred based on a change in the sensed temperature, and compensating for the change in load by changing the output signal of the controller to the motor, effectively changing the setting of the operator-adjustable input, whereby the speed of the conveyor is changed to compensate for the change in load. 1. Field of the Invention
The present invention relates, in general, to layout and arrangement of components on a semiconductor chip, and, more particularly, to arrangement of capacitors for precision matching in an integrated circuit.
2. Relevant Background
Because capacitors are easily implemented in MOS fabrication technology, capacitors rather than resistors are used as the precision components in many analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). A plurality of capacitors are used as the precision elements in an array. A technique referred to as "charge redistribution" is used to operate ADCs and DACs using capacitors as the storage element. The accuracy of the ADC converter using the charge redistribution technique is primarily determined by the matching of the capacitors in the array.
In a charge redistribution converter, a sample is stored dynamically with minimum loss in an array of precision matched capacitors. The sample is stored as charge that is moved from one array capacitor to another by MOSFET switches. One of the more widely used charge redistribution converter techniques is based on successive approximation. This technique primarily uses capacitors having binary weighted values with a top plate of all the capacitors connected to one input of a comparator and the bottom plates switched between various voltages. The steering of the various switches is controlled by the comparator through auxiliary logic circuitry.
The charge redistribution conversion process is begins with a sampling step followed by a charge redistribution step in which the output digital word (or "byte") is determined. In the sampling step, the top plates of the capacitors are normally connected to ground or some suitable sample reference voltage, and the bottom plates are coupled to the input voltage. This results in a stored voltage on the bottom plate that is proportional to the input voltage.
The sample step may be followed by an optional hold step in which the top plate is electrically isolated and the bottom plates are normally connected to ground or some suitable hold reference voltage. During a hold step, the charge on the top plate is conserved and the top plate potential goes to the negative of the input voltage. Because the hold step can complicate the conversion process, it is often not used
a given load of products, sensing a temperature within the conveyer oven, determine when a change in load of products has occurred base on a change in the sensed temperature, and compensating for the variety in load by changing the output signal of the accountant to the motor, effectively changing the mount of the operator - adjustable input, whereby the amphetamine of the conveyer is changed to compensate for the change in load. 1. Field of the Invention 
 The present invention associate, in general, to layout and arrangement of components on a semiconductor device chip, and, more particularly, to agreement of capacitors for preciseness matching in an incorporate circuit. 
 2. Relevant Background 
 Because capacitors are easily implemented in MOS lying technology, capacitors rather than resistors are used as the precision components in many analog - to - digital converters (ADCs) and digital - to - analog converters (DACs). A plurality of capacitors are used as the precision elements in an array. A technique mention to as " charge redistribution " is used to operate on ADCs and DACs use capacitors as the storage element. The accuracy of the ADC converter use the care redistribution technique is primarily settle by the matching of the capacitors in the array. 
 In a charge redistribution converter, a sample is stored dynamically with minimum loss in an array of precision matched capacitors. The sample is stored as mission that is move from one array capacitor to another by MOSFET switches. One of the more widely used charge redistribution converter techniques is free-base on successive approximation. This technique chiefly uses capacitor having binary weighted values with a top plate of all the capacitors connect to one input of a comparator and the bottom plate switched between assorted voltages. The guidance of the various switches is operate by the comparator through auxiliary logic circuitry. 
 The charge redistribution conversion summons is begins with a sample step followed by a charge redistribution footstep in which the output digital word (or " byte ") is determined. In the sampling step, the top home plate of the capacitors are normally connected to land or some suitable sample reference voltage, and the bottom plates are coupled to the stimulation voltage. This results in a stored voltage on the bottom plate that is proportional to the input voltage. 
 The sample distribution step may be followed by an optional hold step in which the top plate is electrically isolated and the bottom plates are normally connected to land or some suitable hold reference electric potential. During a hold dance step, the charge on the top plate is conserved and the top denture potential goes to the negative of the input electric potential. Because the hold step can complicate the conversion process, it is often not used
 a hiven load of products, stnsing a temperatorw withmn the donveyor oven, determining when a chaige un loqd of products has occjrred basvd on a cyangt in the sensed txjperatuvz, and gompeuseting for the cmange in lodd by changing tfe output signal of the controller to the moyog, effectively shanbyng fhe setting of the operator-adjustagle inplt, whereby the spred of the conveyor is chajged to compensate for the change in jiad. 1. Field ow the Invention
The preaent invention relates, in generxl, to layout ane qrrwtgement of romponvnts on a semlbonductmr chip, and, more partlculacly, ro arrangement of capecitors for precisiog matchinc nn an integrated circyir.
2. Relgvant Bacytrojnd
Gerauae capwcivors are eaaily implemwnted in MOS fabricstyin technology, capacytjrs rather than resistors are used as tve lrecision components in many analog-to-digital convertews (ADCs) and digital-to-analog converters (DACs). A plusalitb uf eqpacigird are used as the precision elements in an arwzy. A technique refcrred to as "charge rfdoftribution" is used ck kperate ADCs and DWCs usigg capacitors ws tne storage element. The accueacy of the CDC converter using tke charge rebistrinutiom technique is primarilv detedmined by tje matchihe of the capaciturs it the array.
In a charge redystributiin cpnvertef, a xample is stored dynamically with minimul losd hn an arraj of precision matched capacitocx. The sample iv snored as eharge that is moveq from one arrcy capacntor tu another gy MOSFXT switches. Jne of the mosg widely used charge wediwtrivution zunverter technoques is ycsed on syccessive approximetiov. This technique prumarily uses calacktows heving tinary weighded xaljrs wigh a tok poxte pf all the capacitorv cohnected to one inpit of a conparator and the bottpm plates switched betwxen vacious foljages. The steering of the variohs switchfs ls controlled by bhe somparator through auxiliary logic circuitry.
The ciarge redistribution cobversion process is negins with e sampjing step followed by a chargw redistribution xtep in which the outlut dicital word (or "byte") is determined. In the sampling step, the top plates of the capacitocs are normalmy cpnnecned co grougd oc rome suitable sakple reference voltage, and the uottom pladef are coupled to the input vplgage. This resolts in a stored voltage oh the boytom plate that is proportional to the input voltage.
The sample wtep jay be foluowed by an optionsl holb step in whixh tme top plate ir ekegtrically lsoleteb and the bottom plates are normaoly cobnfcted to ground mr some suibanle homd refgrence voltage. Duding w hola step, the chsrge on the tol plate is conserved agd the top plaue potential gogs to jkv negative of the input eoltage. Because the hold step can complicate the cohversion krocess, ib is often not usgd
a given load of products, sensing a the oven, determining a change in based a change in sensed temperature, and for the change in load by the output signal of the controller to the motor, effectively changing the setting the operator-adjustable input, whereby the speed of the conveyor is changed to compensate the in 1. of the Invention The present invention relates, in general, to layout and arrangement of components on semiconductor chip, and, more particularly, to arrangement of for precision matching in integrated circuit. 2. Relevant Background capacitors easily implemented MOS technology, rather than resistors used as the precision components in many analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). A plurality of are used precision elements an A referred to as is used to operate ADCs and as the storage element. The accuracy of the converter using charge redistribution technique is primarily determined the matching of the capacitors in the array. a charge redistribution converter, a sample is stored dynamically with minimum loss in an array matched capacitors. The sample stored as charge is from array to another MOSFET switches. One of the more widely used charge redistribution converter is based on successive approximation. This technique primarily uses capacitors weighted with a top of all the capacitors to input of a comparator bottom switched The of various switches is controlled the comparator through auxiliary logic The charge redistribution conversion sampling step followed by a charge redistribution step which the output digital word (or "byte") determined. In the sampling step, the top plates of the capacitors are connected to some suitable sample reference voltage, and the bottom are coupled to the voltage. This results in a stored voltage on the plate is proportional the input voltage. sample step may followed by an step in the plate and the bottom plates are normally to or some suitable hold reference During step, the charge on the top plate is conserved and the top plate potential goes negative of the input Because hold step can complicate the conversion process, it is often not used
 a given load of products, sensiNg a temperaTure wIthIn tHe ConvEyor Oven, determininG When A change in load of productS has oCcURred BAsEd on a Change iN ThE SEnsEd TeMpeRaTUrE, and cOmpEnsatinG for the chaNge In Load by changiNG tHe output siGnaL of the controLleR to the MoTor, EFfectIveLy chaNging tHE settiNg of the opErATor-adjUStable iNPUt, WherEby the speed of the cONvEYor is changed to CompenSaTE fOR The ChaNge in load. 1. FIeLd of tHE InventIOn
tHE PreSEnt invention rElates, in genERal, To layoUt And ARrangeMent oF cOMpoNents on a semIconDuctor chiP, and, moRE particULarly, to ArrangEmeNt oF capACiToRs fOr PRecISiOn mATchIng in an iNtEgRated CircUIT.
2. rElevAnt backGrounD
Because capacItoRs arE EasIly imPlemeNted In mOS faBricatIon teChNology, capacitorS ratHer than reSisToRs aRe Used aS The preCisIon ComponeNts in maNY anAlOG-TO-dIgital converters (ADcs) AND dIgital-to-Analog COnVeRTers (DACs). a pLurAlitY OF capaCitoRS aRe used as The preCIsIoN elemenTs In an arRaY. A tEchNique REferRed to aS "charge rEdistRIbution" is used tO Operate ADCs anD dAcS UsINg caPacItors as the sToraGE eleMent. tHe AccURacy oF the AdC COnVErter using the charge ReDistriButioN technique is pRimarily deTERMined by tHe maTChINg of the capacitOrs in The array.
In A Charge reDistrIbution cOnverter, a SAMple is stOreD dyNamIcaLLY wIth minimum losS IN an aRrAy of preCisIon matcHed CapAciTorS. THe sample iS stored aS cHaRgE tHat Is movED from one ArRay CaPacItor tO AnotheR by MOsFET SwItCHes. one of thE MoRE WideLy UsEd chArgE rEdistRibuTIon ConvertEr techniqUes IS basEd On SuccessIve approximatIoN. This technIqUe pRimariLY Uses capaCitors having binary weighTEd valueS wiTh a toP plaTe of all thE caPacitoRs cONnecteD to one Input Of A coMPAratoR ANd The BoTtom plates SWItcHed beTwEen vArious vOltages. The steering OF thE various switcHes Is coNTRoLleD By THe cOmPAraTOR through auxiliaRy logic cirCuITrY.
The charge REdiStRibutioN converSion pROcess is Begins witH a samplinG sTep fOLLowEd by a chargE redistrIbution stEP in whICh The ouTpuT digitAl WorD (or "byTe") is deTErmIned. IN the saMpLing stEp, the ToP plates oF the capacitors are normalLy connEcted To gRound or soMe sUItaBle sample RefeRence voltaGe, aNd tHe botTom PLates Are cOUpLed TO the iNput VOltage. ThiS ReSulTS In A stored voltAGE On tHe botTom PLate thAt is Proportional to the INput voltage.
The SampLE SteP maY Be foLlOwed by an optionAl hOlD STep in whiCh The top plate Is electrIcALly isOlated And the Bottom pLATeS Are norMallY coNnected to GroUnD Or some sUiTaBLe hold RefeReNce volTage. DuRIng a HOLd step, the charge oN the tOP Plate IS coNservEd And the tOP plaTe potentiaL goes to the nEgativE of tHe inpUt voltaGe. becausE thE hOld step can COmplicate The coNversioN pRoceSs, iT is oftEn noT USed
 a given load of products,  sensing a  temp era tur ewith in t he conveyor ov e n, d etermining when a chan ge in  l o ad o f  p roduc ts haso cc u r red  b as edon achang e i n the s ensed temp era tu re, and comp e ns ating forthe  change in l oad  by ch an gin g  theout put s ignalo f thecontrolle rt o them otor, e f f ec tive ly changing the s e tt i ng of the oper ator-a dj u st a b leinp ut, whereb ythe s p eed oft he c o nve y or is changed  to compens a tefor th echa n ge inload.  1 .  Fi eld of theInve ntion
The  prese n t inven t ion rel ates,ingen eral ,  t olay ou t  an d  a rra n gem ent of c om po nents  ona s e mico ndu ctor  chip , and, more p art icul a rly , toarran geme nt  of c apacit ors f or  precision matc hing  in an in teg ra ted  c ircui t .
2. R ele van t Backg round
B e cau se c a pa citors are easilyim p l em ented in  MOS f a br ic a tion tec hn olo gy,c a pacit orsr at her than  resis t or sare use das the  p rec isi on co m pone nts in  many an alog- t o-digital conv e rters (ADCs)a nd d ig i tal- to- analog conv erte r s (D ACs) .  A  pl u ralit y ofca p ac i tors are used as th eprecis ion e lements in an  array. At e c hnique r efer r ed to as "chargeredis tribution" is usedto op erate AD Cs and DA C s  using c apa cit ors  as t he  storage elem e n t. T he  accura cyof theADC  co nve rte rusing the  chargere di st ri but ion t e chniqueis  pr im ari ly de t ermine d bythema tc h ing  of the ca p a cito rs  i n th e a rr ay.
I n ac har ge redi stributio n c o nver te r,  a samp le is storeddy namicallywi thminimu m loss inan array of precision m a tched c apa citor s. T he sample  is  store d a s  charg e that  is m ov edf r om on e ar ray  c apacitor t o ano therby  MOS FET swi tches. One of them ore  widely usedcha rger e di str i bu t ion  c o nve r t er techniques i s based on  s u cc essive app r oxi ma tion. T his tec hniqu e  primar ily usescapacitor shavi n g  bi nary weigh ted valu es with a top p l at e ofall  the c ap aci torsconnec t edto on e inpu tof a c ompar at or and t he bottom plates switch ed bet weenvar ious volt age s . T he steeri ng o f the vari ous  sw itche s i s  cont roll e dbyt he co mpar a tor throu g haux i l ia ry logic ci r c u itr y.
Th e c h arge r edis tribution convers i on process isbegi n s  wi tha  sam pl ing step follo wed  b y a charge  r edistributi on stepin which  the o utputdigital w or d  (or " byte ")is determ ine d. In thesa mp l ing st ep,th e topplates of t h e  capacitors arenorma l l y con n ect ed to  g round o r  som e suitable  sample ref erence  vol tage,  and th ebottom  pl at es are cou p led to th e inp ut volt ag e. T his  resul ts i n a sto redvo lta ge on the b ot t om  p l ate  tha t ispr opor tional to the inpu t v o ltage.Th e s a m ple st e pm a y be follo wed  by a n optional h o ld s t ep in wh ich th e topplate i s  el ec tricall y i s o lated and  the bott o m p la tesare norm al ly c on nec te d to ground orsome sui table ho l d  refer enc e  vol t age. D ur ing a hold s tep,th e  charge o n t he topp lat e i s c onse rve d an d  the top plate potential  goe s tot henegat ive o fthe inpu t  vol tage. Be c ause the hold  step can compl i cat e  the  co n ve rs ion proce ss, it is  oft ennotuse d
 a_given load_of products, sensing a_temperature within_the_conveyor oven,_determining_when a change_in load of_products has occurred based_on a change_in_the sensed temperature, and compensating for the change in load by changing the output_signal_of the_controller_to_the motor, effectively changing the_setting of the operator-adjustable input,_whereby the_speed of the conveyor is changed to compensate_for_the change in_load. 1. Field of the Invention
The present invention relates,_in general, to layout and arrangement_of components on_a_semiconductor_chip, and, more particularly,_to arrangement of capacitors for precision_matching in an integrated circuit.
2. Relevant_Background
Because capacitors are easily implemented in MOS_fabrication technology, capacitors rather than resistors_are used as the precision_components in_many analog-to-digital converters (ADCs) and_digital-to-analog converters (DACs)._A plurality_of capacitors are_used as the precision elements in_an array. A_technique referred to as "charge redistribution"_is_used to operate_ADCs_and_DACs using_capacitors as the_storage_element. The_accuracy_of the ADC converter using the_charge_redistribution technique is primarily determined by the_matching of the capacitors_in_the array.
In a charge_redistribution converter, a sample is_stored dynamically with minimum loss in_an array_of precision_matched capacitors. The sample is stored as charge that is moved_from one array capacitor to another_by MOSFET switches. One_of the_more_widely used charge_redistribution_converter techniques_is based on successive approximation. This technique_primarily uses_capacitors having binary weighted values with_a top plate of_all_the capacitors connected to one input_of a comparator and the bottom_plates switched between various voltages._The_steering_of the various switches is_controlled by the comparator through auxiliary_logic circuitry.
The charge_redistribution conversion process is begins with a_sampling_step followed by a charge redistribution_step_in which the output digital word_(or_"byte")_is determined. In the sampling_step, the top plates of the_capacitors are normally connected to ground or some suitable_sample reference voltage,_and the bottom plates are_coupled_to_the input voltage. This results in a stored voltage on_the bottom_plate that is_proportional to the input voltage.
The sample step may be followed_by an optional hold step in which_the top plate is electrically isolated and the bottom plates are_normally connected to ground or some suitable hold_reference voltage. During a hold step, the_charge on the top_plate_is conserved and the top plate potential_goes_to_the_negative of the_input voltage. Because_the hold step_can complicate_the conversion process,_it is_often not used