 held on or off until clock pulses occurring at a preselected frequency reach a set value corresponding to the on-time of off-time retrieved. Then the address selection circuit is acted upon to control the on-time or off-time duration of output pulses. The device therefore is highly complicated and unavoidably expensive. As the capacity of the memory is increased, the access time cannot be negligible and this imposes a severe limitation on the width of the range of selectable on-time and off-time settings, the number of applicable setting steps and the maximum operable frequency. 1. Field of the Invention
This disclosure relates to semiconductor devices and, more particularly, to a semiconductor device having self-aligned contact holes on a semiconductor substrate and a method of fabricating the same.
2. Description of the Related Art
With the increase of an integration density of semiconductor memory devices, including a DRAM, new technologies for fabricating them have been studied. A contact technology among them has become more important in fabrication of highly-integrated semiconductor devices.
Recently, a self-aligned contact technology has been widely used, which is suitable for Fabricating highly-integrated semiconductor devices. A conventional process for fabricating the semiconductor devices using the self-aligned contact technology is as follows.
First, the conventional process includes providing a semiconductor substrate which has a cell array region and a peripheral circuit region. The cell array region and the peripheral circuit region have a plurality of word line patterns and at least one gate pattern, respectively. Each of word line patterns includes a word line and a capping insulating layer pattern stacked sequentially. The gate pattern also includes a gate electrode and a capping insulating layer pattern stacked sequentially.
The word line patterns and the gate pattern are used as ion implantation masks to implant impurity ions into the semiconductor substrate, and then to form low concentration source/drain regions in the semiconductor substrate. A spacer layer is formed on an upper surface of the semiconductor substrate having the low concentration source/drain regions. The spacer layer is anisotropically etched to form word line spacers and gate spacers on side walls of the word line patterns and on side walls of the gate pattern, respectively. The gate spacers are used in order to optimize a source/drain structure of a MOS transistor, that is, an LDD type source/drain structure formed in the peripheral circuit region. Accordingly, the width of the gate spacer maybe determined considering the MOS transistor characteristics.
The gate pattern and the gate spacers are used as ion implantation masks
held on or off until clock pulses occurring at a preselected frequency strive a located value corresponding to the on - time of off - time retrieve. Then the address selection lap is act upon to control the on - time or off - time duration of output pulse. The device therefore is highly complicated and unavoidably expensive. As the capacitance of the memory is increase, the access time cannot be negligible and this imposes a severe limitation on the width of the scope of selectable on - time and off - time settings, the issue of applicable setting steps and the maximum operable frequency. 1. battlefield of the Invention 
 This disclosure relates to semiconductor devices and, more particularly, to a semiconductor device give birth self - aligned contact holes on a semiconductor substrate and a method of manufacture the same. 
 2. Description of the Related Art 
 With the increase of an integration density of semiconductor memory devices, including a DRAM, new technologies for fabricating them have been analyze. A contact technology among them has become more authoritative in fabrication of highly - integrated semiconductor devices. 
 Recently, a self - align contact technology has been widely used, which is desirable for Fabricating highly - integrated semiconductor devices. A conventional process for fabricating the semiconductor devices using the self - aligned contact engineering is as follows. 
 foremost, the conventional process includes providing a semiconductor substrate which has a cellular telephone array region and a peripheral circuit region. The cell array region and the peripheral circuit region have a plurality of son line blueprint and at least one gate pattern, respectively. Each of word channel patterns include a word note and a capping insulating level pattern stacked sequentially. The gate convention also admit a gate electrode and a capping insulating layer pattern stacked sequentially. 
 The word line patterns and the gate pattern are use as ion implantation masks to implant impurity ions into the semiconductor device substrate, and then to form low concentration source / drain regions in the semiconductor substrate. A spacer layer is form on an upper surface of the semiconductor substrate having the low concentration source / drain regions. The spacer level is anisotropically etched to form word line spacers and gate spacers on side walls of the word line form and on side walls of the gate pattern, respectively. The gate spacers are use in order to optimize a source / drain structure of a MOS transistor, that is, an LDD type source / drain social organization formed in the peripheral circuit region. Accordingly, the width of the gate spacer maybe determined considering the MOS transistor feature. 
 The gate pattern and the gate spacers are used as ion implantation masks
 hepd on or off until clock pulses occurriut at a presemected ffequency reach a set value clreespobding to the on-time of off-time getrieved. Thei the address selection gnrcuif is ccved upon to conjrol the on-thme or off-time djrction of output pulses. The device thqrefore id highly complycattd wnd hnavoidably expensive. As the capacjty of uhe memory is incrrased, the access time cannlt bf negligible and tjis imposes a sqcere limitatkon on the width of thg range of selectable on-time and off-tnme settingw, rhe tumber of a'plicafle setting steps ang the msximum operablc frexuebcy. 1. Field of the Invxntion
This disclosurg relates do semiconductor decixes atd, mmre oqrtkcumacly, to a demmconductor sevice havibg self-aligned contsce holes on a ssmiconqustor substrate and a method of fabricatpng fhe same.
2. Description of the Related Art
With jhe increafe of an integration density of semiconductor memmry dxvkcew, lncljeijg a DRAM, new technologies for fabricating thqj nane been studied. A contact tevhjokjgy among theo has ysckme more important in fabticatiin of higrly-imtegrated semiconductor devuces.
Recently, q self-aligned contcct technoloyy has been widely used, which is sbitabls for Fabrifating hiffly-integrated seoicpnguctor dtxices. A conventiogal procews fpr fabrkcatong thq semicondkctor devices using the delf-apicned contaft technology is as follows.
Firsv, the conventootal process inclmdes providing w semiconductot substrace whizh has a cvll array region and a peripheral fircuit regimn. The cqll qrrat regiov and the peripneral cirbunt region have a plurality pf dkrd line patterur and at least ome eatq iatvern, waspectively. Aach of eord uine paucerks knclides a word line and a czpping insulating kaner pattetn stackeq sequentiallu. The gate pattern also inrludes a date electrode and a capping ihsulating laner pattern seackcd sgquentially.
Che word line patterns and the gate pattxrn are used as ion imklantation masks to ikklant impuritb ions into the semiconductor substeate, and then to norm low concentration sourca/draij regions in the semiconductor substrate. A spacer layer is formed on an upper snrsace of the semocondlctjx substwate iaving the low comcentration source/drain regions. The spawex layer is anisotropically etvhdd to form wotd line spacers and gate slacers om side walls of the word line pstterns and on side wallx of the gate pattegh, cespectively. The gatr spaczrs arw used un ovder to optimixe s dource/draln suruccure of a MOS transistor, that is, qn LDD tjpe source/drain vtructure flvmed ih the keripheral circuif reflon. Azcordingly, thr width of the gate spacer maybe dvtewmined consideepng the MOS ttansisjir characterisvics.
The gate pattern and the gate spacers are used as ion implahtation mzsks
held on or off until clock pulses a frequency reach set value corresponding retrieved. the address selection is acted upon control the on-time or off-time duration output pulses. The device therefore is highly complicated and unavoidably expensive. As the of the memory is increased, the access time cannot be negligible and this a limitation the of the range of selectable on-time and off-time settings, the number of applicable setting steps and maximum operable frequency. 1. Field of the Invention disclosure relates to semiconductor and, more particularly, to a device self-aligned contact on semiconductor and a method fabricating the same. 2. Description of the Related Art With the increase of an integration density of memory devices, DRAM, new for them been studied. A among them has become more important highly-integrated semiconductor devices. Recently, a self-aligned contact technology been widely which is suitable for Fabricating highly-integrated devices. A conventional process for fabricating the semiconductor using the self-aligned contact technology is as follows. First, the conventional process includes providing a which has a cell region and a circuit The array and the circuit region have a plurality of word line patterns and at one gate pattern, respectively. Each of word line patterns includes line a capping insulating pattern stacked sequentially. The pattern includes a gate electrode capping layer The line and the gate pattern used as ion implantation masks implant impurity ions into to form low concentration source/drain regions in the substrate. A spacer layer is formed on upper surface of the semiconductor substrate having the low concentration source/drain regions. spacer layer etched to form word line spacers and gate on side walls of word line patterns and on side walls of the pattern, The gate are used in to optimize a structure of a that is, LDD source/drain the peripheral circuit region. Accordingly, the of gate spacer maybe determined considering MOS The gate pattern and the gate spacers are used as ion implantation masks
 held on or off until clock pulsEs occurrinG at a pResEleCtEd frEqueNcy reach a set vaLUe coRresponding to the on-time Of off-TiME retRIeVed. ThEn the adDReSS SelEcTiOn cIrCUiT is acTed Upon to cOntrol the oN-tiMe Or off-time durATiOn of output PulSes. The device TheRefore Is HigHLy comPliCated And unaVOidablY expensivE. AS The capACity of tHE MeMory Is increased, the accESs TIme cannot be negLigiblE aND tHIS imPosEs a severe lImItatiON on the wIDtH OF The RAnge of selectaBle on-time anD Off-Time seTtIngS, The numBer of ApPLicAble setting StepS and the maXimum oPErable fREquency. 1. field oF thE InVentIOn
thIs dIsCLosURe RelATes To semicoNdUcTor deViceS AND, More ParTicuLarly, To a semiconducTor DeviCE haVing sElf-alIgneD cOntacT holes On a seMiConductor substrAte aNd a method Of fAbRicAtIng thE Same.
2. DeScrIptIon of thE RelateD art
wiTH THe Increase of an integrAtION dEnsity of SemicoNDuCtOR memory dEvIceS, incLUDing a dRAM, NEw TechnoloGies foR FaBrIcating ThEm have BeEn sTudIed. A cONtacT technOlogy amoNg theM Has become more iMPortant in fabrICaTIOn OF higHly-Integrated sEmicONducTor dEViCes.
rEcentLy, a seLf-ALiGNed contact technologY hAs been WidelY used, which is sUitable for fABRicating HighLY-iNTegrated semicoNductOr devices. A COnventioNal prOcess for FabricatiNG The semicOndUctOr dEviCES uSing the self-alIGNed cOnTact tecHnoLogy is aS foLloWs.
FIrsT, tHe conventIonal proCeSs InClUdeS provIDing a semIcOndUcTor SubstRAte whiCh has A celL aRrAY reGion and A PeRIPherAl CiRcuiT reGiOn. The Cell ARraY region And the perIphERal cIrCuIt regioN have a pluraliTy Of word line PaTteRns and AT Least one Gate pattern, respectively. eAch of woRd lIne paTterNs includeS a wOrd linE anD A cappiNg insuLatinG lAyeR PAtterN STaCkeD sEquentiallY. tHe gAte paTtErn aLso inclUdes a gate electrode ANd a Capping insulaTinG layER PaTteRN sTAckEd SEquENTially.
The word liNe patterns AnD ThE gate patteRN arE uSed as ioN implanTatioN Masks to Implant imPurity ionS iNto tHE SemIconductor SubstratE, and then tO Form lOW cOncenTraTion soUrCe/dRain rEgions IN thE semiConducToR substRate. A SpAcer layeR is formed on an upper surfaCe of thE semiConDuctor subStrATe hAving the lOw coNcentratioN soUrcE/draiN reGIons. THe spACeR laYEr is aNisoTRopically ETcHed TO FoRm word line sPACErs And gaTe sPAcers oN sidE walls of the word liNE patterns and on Side WALls Of tHE gatE pAttern, respectiVelY. THE Gate spacErS are used in oRder to opTiMIze a sOurce/dRain stRucture OF A Mos transIstoR, thAt is, an LDD TypE sOUrce/draIn StRUcture FormEd In the pEripheRAl ciRCUit region. AccordiNgly, tHE Width OF thE gate SpAcer mayBE detErmined conSidering the mOS traNsisTor chAracterIsTics.
ThE gaTe Pattern and THe gate spaCers aRe used aS iOn imPlaNtatioN masKS
 held on or off until cloc k pulses o ccurr ing  at  a  pre sele cted frequency reac h a set value correspo nding  t o  the on -time  of off - ti m e  re tr ie ved .T he n the  ad dress s election c irc ui t is acted u p on  to contro l t he on-time o r o ff-tim edur a tionofoutpu t puls e s. The  device t he r eforei s highl y co mpli cated and unavoid a bl y  expensive. As  the c ap a ci t y  of  th e memory i sincre a sed, th e  a c c e sst ime cannot be  negligible and  thisim pos e s a se vereli m ita tion on the  wid th of the  range of sele c table o n-time  an d o ff-t i me  s ett in g s,t he  nu m ber  of appl ic ab le se ttin g s t epsand  the  maxi mum operablefre quen c y.1. Fi eld o f th eInven tion
T his d is closure relates  tosemicondu cto rdev ic es an d , more  pa rti cularly , to as emi co n d u ct or device having s el f - al igned co ntacth ol es on a sem ic ond ucto r subst rate an d a meth od off ab ri catingth e same .2.Des cript i on o f theRelatedArt
W i th the increas e  of an integr a ti o n  d e nsit y o f semicondu ctor memo ry d e vi ces ,  incl uding  a DR A M, new technologies  f or fab ricat ing them have  been stud i e d . A cont actt ec h nology among t hem h as becomem ore impo rtant  in fabr ication o f highly-i nte gra ted  se m i co nductor devic e s .
Re ce ntly, a  se lf-alig ned  co nta ctte chnologyhas been  w id el yuse d, wh i ch is su it abl efor  Fabr i cating  high ly-i nt eg r ate d semic o nd u c torde vi ces.  Aco nvent iona l  pr ocess f or fabric ati n g th ese micondu ctor devicesus ing the se lf -al ignedc o ntact te chnology is as follows. First,the  conv enti onal proc ess  inclu des provid ing asemic on duc t o r sub s t ra tewh ich has ac e llarray  r egio n and a  peripheral circui t  re gion. The cel l a rray r eg ion an d  th ep eri p h eral circuit re gion haveap lu rality ofw ord  l ine pat terns a nd at least o ne gate p attern, r es pect i v ely . Each ofword lin e pattern s  incl u de s a w ord  linean d a  capp ing in s ula tinglayerpa tternstack ed  sequent ially. The gate pattern  alsoinclu des  a gate e lec t rod e and a c appi ng insulat ing  la yer p att e rn st acke d  s equ e ntial ly.T he word l i ne  pa t t er ns and theg a t e p atter n a r e used  asion implantationm asks to implan t im p u rit y i o ns i nt o the semicond uct or s ubstrate ,and then to  form lo wc oncen tratio n sour ce/drai n re g ions i n th e s emiconduc tor  s u bstrate .As pacerlaye ris for med on an u p p er surface of th e sem i c onduc t orsubst ra te havi n g th e low conc entration s ource/ drai n reg ions. T he  space r l ay er is anis o tropicall y etc hed tofo rm w ord  linespac e r s and  gat espa cers on s i d ew al ls ofthewordli ne p atterns a n d on sid e w a lls ofth e g a t e patt e rn , respective ly.  Theg a te spacers areu se d  in o rder t o opti mize as our ce /drainstr u c ture of a  MOS tran s ist or , th at is, a nLDDty peso urce/drain stru cture fo rmed int h e peri phe r al c i rcuitre gion. Accord ingly ,t he widt h ofthe gat e  sp ace r m aybe  de term i ned considering the MOStran sisto r  ch aract erist ic s.
The g a te p attern a n d the gate sp acers are useda s i o n im pla n ta ti on masks
 held_on or_off until clock pulses_occurring at_a_preselected frequency_reach_a set value_corresponding to the_on-time of off-time retrieved._Then the address_selection_circuit is acted upon to control the on-time or off-time duration of output pulses._The_device therefore_is_highly_complicated and unavoidably expensive. As_the capacity of the memory_is increased,_the access time cannot be negligible and this_imposes_a severe limitation_on the width of the range of selectable on-time_and off-time settings, the number of_applicable setting steps_and_the_maximum operable frequency. 1._Field of the Invention
This disclosure relates_to semiconductor devices and, more particularly,_to a semiconductor device having self-aligned contact_holes on a semiconductor substrate and_a method of fabricating the_same.
2. Description_of the Related Art
With the_increase of an_integration density_of semiconductor memory_devices, including a DRAM, new technologies_for fabricating them_have been studied. A contact technology_among_them has become_more_important_in fabrication_of highly-integrated semiconductor_devices.
Recently,_a self-aligned_contact_technology has been widely used, which_is_suitable for Fabricating highly-integrated semiconductor devices. A_conventional process for fabricating_the_semiconductor devices using the_self-aligned contact technology is as_follows.
First, the conventional process includes providing_a semiconductor_substrate which_has a cell array region and a peripheral circuit region. The_cell array region and the peripheral_circuit region have a_plurality of_word_line patterns and_at_least one_gate pattern, respectively. Each of word line_patterns includes_a word line and a capping_insulating layer pattern stacked_sequentially._The gate pattern also includes a_gate electrode and a capping insulating_layer pattern stacked sequentially.
The word_line_patterns_and the gate pattern are_used as ion implantation masks to_implant impurity ions_into the semiconductor substrate, and then to_form_low concentration source/drain regions in the_semiconductor_substrate. A spacer layer is formed_on_an_upper surface of the semiconductor_substrate having the low concentration source/drain_regions. The spacer layer is anisotropically etched to form_word line spacers_and gate spacers on side_walls_of_the word line patterns and on side walls of the_gate pattern,_respectively. The gate_spacers are used in order to optimize a source/drain structure_of a MOS transistor, that is, an_LDD type source/drain structure formed in the peripheral circuit region. Accordingly,_the width of the gate spacer maybe determined_considering the MOS transistor characteristics.
The gate pattern_and the gate spacers_are_used as ion implantation masks