 input signals. Therefore, scattering of the timing signal due to phase delay is a problem, especially on sampling.
In order to optimize the sampling point, a video information apparatus disclosed in Japanese Patent laid open Publication 9-149291 (1997) uses auto-correlation of video signals between frames. That is, a delay time of sampling clock signal is changed successively, and the auto-correlation between frames of video signals after analog-to-digital conversion is determined for each delay time. Then, a point having low correlation is adopted as a point at which the signal is changed. Then, by changing the sampling clock delay, an optimum sampling point is determined at a midpoint or thereabout of the signal-changing point. However, this conventional optimizing circuit needs a frame memory in order to determine the correlation value. Therefore, a complicated memory control circuit and high-speed clock signal are needed. A method using multiple A/D converter circuits is known as a method not using a memory. However, this method has a problem that a plurality of delay circuits for sampling clock are necessary.
An object of the invention is to provide a video signal processing apparatus which optimizes the sampling point when an analog video signal is converted to a digital signal.
A first video signal processing apparatus according to the present invention comprises:
a clock generator which generates a sampling clock signal for digitizing a video signal based on an input synchronization signal;
a phase controller which controls phase of the sampling clock signal at one of a plurality of phases in one period of the sampling clock signal;
a first signal generator which generates a first signal when the input video signal is larger than a threshold level;
a first counter which counts the first signal received from the first signal generator in a predetermined time;
a second signal generator which generates a second signal when the input video signal is larger than another threshold level, at a timing according to the sampling clock signal controlled by the phase controller;
a second counter which counts the second signal received from the second signal generator in the predetermined time; and
a controller which makes the phase controller sequentially change the phase of the sampling clock signal in a period of the sampling clock signal, repeats the phase change over one or more periods of the sampling clock signal and sets the phase of the optimum sampling clock signal based on a difference between the output signals of the first and second counters obtained for each of the changed phases.
For example, the controller set the optimum phase of the sampling clock signal according to a plurality of the subtraction results obtained by the
input signals. Therefore, scattering of the timing signal due to phase delay is a trouble, particularly on sampling. 
 In order to optimize the sample distribution point, a television information apparatus disclosed in Japanese Patent lay open Publication 9 - 149291 (1997) uses car - correlation coefficient of video signals between human body. That is, a delay time of sampling clock signal is changed successively, and the auto - correlation between frames of video recording signals after analog - to - digital conversion is determined for each delay prison term. Then, a point having low correlation is adopt as a point at which the signal is changed. Then, by changing the sampling clock delay, an optimum sampling distributor point is determined at a midpoint or thereabout of the signal - changing point. However, this conventional optimizing circuit needs a frame memory in order to determine the correlation value. Therefore, a complicated memory control circuit and high - speed clock signal are necessitate. A method using multiple A / five hundred converter circuit is sleep together as a method not using a memory. However, this method acting has a trouble that a plurality of delay circuits for sampling clock are necessary. 
 An aim of the invention is to provide a video signal processing apparatus which optimizes the sampling point when an analog television signal is converted to a digital signal. 
 A first video signal processing apparatus according to the present invention comprises: 
 a clock generator which generate a sampling clock signal for digitize a video recording signal based on an input synchronization signal; 
 a phase controller which see phase of the sampling clock signal at one of a plurality of phases in one time period of the sampling clock signal; 
 a first signal generator which generates a first signal when the remark video signal is larger than a doorway level; 
 a inaugural counter which reckon the first signal get from the first signal generator in a predetermined prison term; 
 a second signal generator which generates a second signal when the input signal video signal is large than another threshold level, at a timing according to the sampling clock signal controlled by the phase accountant; 
 a second counter which counts the second signal receive from the second signal generator in the predetermined time; and 
 a controller which makes the phase controller sequentially deepen the phase of the sampling clock signal in a period of the sampling clock signal, repeats the phase change over one or more periods of the sample clock signal and sets the phase of the optimum sampling clock signal establish on a difference between the output signals of the first and second counters obtained for each of the deepen phases. 
 For example, the controller set up the optimum phase of the sampling clock signal according to a plurality of the subtraction results obtained by the
 inout signals. Therefore, scxttering of the timing signam due to phase delay is a problem, es'eciqlly in sampling.
In order to optimize the samplinj point, a video mhformatljn aliaratbs disclosed in Mapanese Padent laid open Pjbpication 9-149291 (1997) uses auto-correlation of dideo sogjals between ftames. Ehat ps, a delay time of sampling clodk signel is changed siccessively, and the auto-cogrelwtion between framfs of video siggqls after anxlog-to-digiuan conversikn is determined for each delay time. Then, a pounr hweing low cocrelatpon is adopted as a pmint at which the sigkal iv cyanged. Then, by changiig the sampling cloch delay, at kptimum sampling pount iv dedermkbed at a mjdpoinh oc thereabouf of the sitnal-changing point. Norvfer, this conbentiogaj optimizing circuit needs a frame memogy ih order to determine thw correlation value. Tjerefore, w complicated memory control circuit and high-speeg clork siykwu age needed. A method using multiple A/D convertew corbuits is known as a method npt uxyng a memory. Fowevex, tgis method has a pgoblem jhat a pluralitr of delay circuits for samplint clock are uecwssary.
An object of the inventnon is to ptovide a video signal pxocessjng apparatks which kotimizes the samolikg [oint whtv an analog video signal iw couverted go a digitwl signal.
A firsb video signal procfssiny appdratus acclrding to the present invention comprises:
a clpcn gvnerator chich nenerates a sam[ling clock siynal for digigizing a vpdeo signel based on wn input syncvtonization sijnal;
a phafe cintriller wfkch controls pnase of tkt sampling clock signal at oke of z plurality of 'kawes in one peripd uf ehv sempligc clock signdl;
a wirry sigval gentxatif whoch generates a firsd sifnal when the inpuy yideo sigbal is lwrger than a yhreshold level;
a flrst rountec whicn cjunts the first signal receives from thf flrst signal gqnerqtor in a przdetermined time;
a second signal generatoc which generates a secind signal when the lnput video xignaj is largar than another threwhold level, at a uiming according to the samplhng cpock signal controlled by the phase controller;
a second counter which counrs the second signzl rrceivvd yrok the fecoid signal generatog in the predetermined time; and
a controlnex which makes the phase contrpluer sequentiauly change the phase of fhe sampking clock signal in a period og the sampling clock sigkal, repears ths phasv ciange over one or mote pernods od the sqmpllng clock signxl snf sets thf phese of the optimum sampling clock sugnal vaded on a differeice between bht outpuj signalf of the first ahd ssfond zounters obtaoned for each pf the changed phasev.
Fjr example, the bontroller sej the opnimum phase oh the samplitg clock signal according to a plurality of the subjraction reaults obbained by the
input signals. Therefore, scattering of the timing to delay is problem, especially on the point, a video apparatus disclosed in Patent laid open Publication 9-149291 (1997) auto-correlation of video signals between frames. That is, a delay time of sampling signal is changed successively, and the auto-correlation between frames of video signals after conversion determined each time. Then, a point having low correlation is adopted as a point at which the signal changed. Then, by changing the sampling clock delay, optimum sampling point is at a midpoint or thereabout the point. However, conventional circuit a frame memory order to determine the correlation value. Therefore, a complicated memory control circuit and high-speed clock signal are A method A/D converter is as method not using However, this method has a problem of delay circuits for sampling clock are necessary. object of invention is to provide a video processing apparatus which optimizes the sampling point when analog video signal is converted to a digital signal. A first video signal processing apparatus the present invention comprises: clock generator which a clock for a video based on an input synchronization signal; a phase controller which controls of the sampling clock signal at one of a plurality in period of the clock signal; a first generator generates a first signal input signal a level; first counter which counts first signal received from the signal generator in a generator which generates a second signal when the video signal is larger than another threshold at a timing according to the sampling clock signal controlled by the controller; a which counts the second signal received from the signal generator in the time; and a controller which makes the phase controller change phase of sampling clock signal a period of sampling clock signal, phase change one more sampling clock signal and sets the of optimum sampling clock signal based a the output signals of the first and second counters obtained for each of the changed example, the controller set optimum of the sampling clock signal according to a plurality of the subtraction by the
 input signals. Therefore, scatTering of thE timiNg sIgnAl Due tO phaSe delay is a probLEm, esPecially on sampling.
In orDer to OpTImizE ThE sampLing poiNT, a VIDeo InFoRmaTiON aPparaTus DisclosEd in JapaneSe PAtEnt laid open PUBlIcation 9-149291 (1997) useS auTo-correlatioN of Video sIgNalS BetweEn fRames. that is, A Delay tIme of sampLiNG clock SIgnal is CHAnGed sUccessively, and the AUtO-Correlation betWeen frAmES oF VIdeO siGnals after AnAlog-tO-Digital COnVERSioN Is determined fOr each delay TIme. then, a pOiNt hAVing loW corrElATioN is adopted aS a poInt at whicH the siGNal is chANged. TheN, by chaNgiNg tHe saMPlInG clOcK DelAY, aN opTImuM samplinG pOiNt is dEterMINED at a MidPoinT or thEreabout of the SigNal-cHAngIng poInt. HoWeveR, tHis coNventiOnal oPtImizing circuit nEeds A frame memOry In OrdEr To detERmine tHe cOrrElation Value. ThERefOrE, A COmPlicated memory contRoL CIrCuit and hIgh-speED cLoCK signal aRe NeeDed. A METhod uSing MUlTiple A/D cOnvertER cIrCuits is KnOwn as a MeThoD noT usinG A memOry. HowEver, this MethoD Has a problem thaT A plurality of dELaY CIrCUits For Sampling cloCk arE NeceSsarY.
an ObjECt of tHe invEnTIoN Is to provide a video siGnAl procEssinG apparatus whiCh optimizeS THE samplinG poiNT wHEn an analog videO signAl is converTEd to a digItal sIgnal.
A fiRst video sIGNal proceSsiNg aPpaRatUS AcCording to the pRESent InVention ComPrises:
a CloCk gEneRatOr Which geneRates a saMpLiNg ClOck SignaL For digitIzIng A vIdeO signAL based On an iNput SyNcHRonIzation SIgNAL;
a phAsE cOntrOllEr Which ContROls Phase of The sampliNg cLOck sIgNaL at one oF a plurality of PhAses in one pErIod Of the sAMPling cloCk signal;
a first signal genERator whIch GenerAtes A first sigNal When thE inPUt videO signaL is laRgEr tHAN a thrESHoLd lEvEl;
a first coUNTer Which CoUnts The firsT signal received froM The First signal geNerAtor IN A pRedETeRMinEd TIme;
A SEcond signal geneRator which GeNErAtes a seconD SigNaL when thE input vIdeo sIGnal is lArger than Another thReSholD LEveL, at a timing AccordinG to the samPLing cLOcK signAl cOntrolLeD by The phAse conTRolLer;
a sEcond cOuNter whIch coUnTs the secOnd signal received from thE seconD signAl gEnerator iN thE PreDetermineD timE; and
a contrOllEr wHich mAkeS The phAse cONtRolLEr seqUentIAlly changE ThE phASE oF the samplinG CLOck SignaL in A Period Of thE sampling clock sigNAl, repeats the phAse cHANge OveR One oR mOre periods of thE saMpLINg clock sIgNal and sets tHe phase oF tHE optiMum samPling cLock sigNAL bASed on a DiffEreNce betweeN thE oUTput sigNaLs OF the fiRst aNd Second CounteRS obtAINed for each of the cHangeD PHases.
fOr eXamplE, tHe contrOLler Set the optiMum phase of tHe sampLing Clock Signal aCcOrding To a PlUrality of tHE subtractIon reSults obTaIned By tHe
 input signals. Therefore,  scatterin g ofthe  ti mi ng s igna l due to phase dela y is a problem, especi allyon samp l in g.
In  ordert oo p tim iz ethe  s a mp lingpoi nt, a v ideo infor mat io n apparatusd is closed inJap anese Patent  la id ope nPub l icati on9-149 291 (1 9 97) us es auto-c or r elatio n  of vid e o  s igna ls between frames .  T h at is, a delay  timeof sa m p lin g c lock signa lis ch a nged su c ce s s i vel y , and the aut o-correlati o n b etween  f ram e s of v ideosi g nal s after ana log- to-digita l conv e rsion i s  determ ined f oreac h de l ay  t ime .T hen ,  a  po i nthaving l ow  c orrel atio n i s  ado pte d as  a po int at whichthe  sig n alis ch anged . Th en , bychangi ng th esampling clockdela y, an opt imu msam pl ing p o int is  de ter mined a t a mid p oin to r th ereabout of the si gn a l -c hangingpoint. Ho we v er, this  c onv enti o n al op timi z in g circui t need s  a  f rame me mo ry inor der  to  dete r mine  the c orrelati on va l ue. Therefore, a complicated me m o ry cont rol  circuit an d hi g h-sp eedc lo cks ignal  arene e de d . A method using mu lt iple A /D co nverter circu its is kno w n as a met hodn ot using a memory . How ever, this method h as aproblemthat a pl u r ality of  de lay  ci rcu i t sfor samplingc l ockar e neces sar y.
An o bje ctofthe  i nventionis to pr ov id eavid eo si g nal proc es sin gapp aratu s  which  opti mize sth e  sa mplingp oi n t  whe nan  ana log  v ideosign a l i s conve rted to a  di g ital  s ig nal.
Afirst video s ig nal proces si ngappara t u s accord ing to the present inve n tion co mpr ises: 
a c lock gene rat or whi chg enerat es a s ampli ng  cl o c k sig n a lfor  d igitizinga vid eo si gn al b ased on  an input synchron i zat ion signal;
a  ph asec o nt rol l er whi ch con t r ols phase of th e sampling  c l oc k signal a t  on eof a pl urality  of p h ases in  one peri od of the  s ampl i n g c lock signa l;
a fir st signal gener a to r whi chgenera te s a  firs t sign a l w hen t he inp ut  video  sign al  is larg er than a threshold lev el;
afirst  co unter whi chc oun ts the fi rstsignal rec eiv edfromthe first  sig n al  ge n erato r in a predete r mi ned t im e;
a second s i gna l gen era t or whi ch g enerates a second signal when th e in p u t v ide o  sig na l is larger th anan o t her thre sh old level,at a tim in g  acco rdingto the  sampli n g  c l ock si gnal  co ntrolledbyth e  phaseco nt r oller; 
a s ec ond co unterw hich c ounts the second  sign a l  rece i ved  from  t he seco n d si gnal gener ator in the  prede term inedtime; a nd 
a con tro ll er which m a kes the p hasecontrol le r se que ntiall y ch a n ge th e ph as e o f the sam p l in g  c lo c k s igna l inaperi od of the sampling  cl o ck sign al , r e p eats t h ep h ase change  ov er on e or more pe r iods of the s amplin g cloc k signa l  an dsets th e p h a se of the  optimums amp li ng c lock sig na l ba se d o na difference be tween th e output s ignals  of thef irst a nd  second coun tersob t ained f o r  ea ch of t h e c han ged  pha ses .
Fo r  example, the controller  set  theo pti mum p haseof  the sam p ling  clock s i gnal accordin g to a pluralit y  of thesub t ra ct ion resul tso btain ed b y t he
 input_signals. Therefore,_scattering of the timing_signal due_to_phase delay_is_a problem, especially_on sampling.
In order_to optimize the sampling_point, a video_information_apparatus disclosed in Japanese Patent laid open Publication 9-149291 (1997) uses auto-correlation of video_signals_between frames._That_is,_a delay time of sampling_clock signal is changed successively,_and the_auto-correlation between frames of video signals after analog-to-digital_conversion_is determined for_each delay time. Then, a point having low correlation_is adopted as a point at_which the signal_is_changed._Then, by changing the_sampling clock delay, an optimum sampling_point is determined at a midpoint_or thereabout of the signal-changing point. However,_this conventional optimizing circuit needs a_frame memory in order to_determine the_correlation value. Therefore, a complicated_memory control circuit_and high-speed_clock signal are_needed. A method using multiple A/D_converter circuits is_known as a method not using_a_memory. However, this_method_has_a problem_that a plurality_of_delay circuits_for_sampling clock are necessary.
An object of_the_invention is to provide a video signal_processing apparatus which optimizes_the_sampling point when an_analog video signal is converted_to a digital signal.
A first video_signal processing_apparatus according_to the present invention comprises:
a clock generator which generates a sampling_clock signal for digitizing a video_signal based on an_input synchronization_signal;
a_phase controller which_controls_phase of_the sampling clock signal at one of_a plurality_of phases in one period of_the sampling clock signal;
a_first_signal generator which generates a first_signal when the input video signal_is larger than a threshold_level;
a_first_counter which counts the first_signal received from the first signal_generator in a_predetermined time;
a second signal generator which generates_a_second signal when the input video_signal_is larger than another threshold level,_at_a_timing according to the sampling_clock signal controlled by the phase_controller;
a second counter which counts the second signal received_from the second_signal generator in the predetermined_time;_and
a_controller which makes the phase controller sequentially change the phase_of the_sampling clock signal_in a period of the sampling clock signal, repeats the_phase change over one or more periods_of the sampling clock signal and sets the phase of the_optimum sampling clock signal based on a difference_between the output signals of the first_and second counters obtained_for_each of the changed phases.
For example, the_controller_set_the_optimum phase of_the sampling clock_signal according to_a plurality_of the subtraction_results obtained_by the