 in FIG. 1, I.sub.DDQ 108 would drop back to the initial low level once the inverter circuit 101 stabilized. With the gate-oxide defect 103, however, I.sub.DDQ 109 Current remains abnormally high.
An interesting point to note is that these types of faults, which result in an abnormally high I.sub.DDQ, do not necessarily result in a functional circuit failure. Instead, defects often materialize as infant mortality or reliability problems in CMOS circuits. One explanation for the lack of functional failures is that gate-oxide shorts are often high resistance defects which cause only small leakage currents. In addition, CMOS circuits usually have a large noise margin. As a result, small amounts of leakage current may not effect the ultimate output value of the circuit. Since these types of faults to do not always result in functional failures, these defects will not always be identified with traditional stuck-at fault testing.
To detect chips with high resistance caused leakage problems, burn-in is often used as an acceleration technique. Burn-in is a method used to accelerate failures in a device if there is a weak feature or defect that is sensitive to extended operation of the device. Defects such as weak oxides, narrow silicon or metal lines, small resistive contacts, or other similar defects usually become more apparent with burn-in and are therefore more readily identified and may, therefore, fail "stuck at" testing. A tradeoff with burn-in, however, is the substantial time and cost that may be involved depending on the type of device being burned-in.
I.sub.DDQ test measurements are used on CMOS circuits as a supplemental technique to identify these defects. To conduct I.sub.DDQ current measurements, testers use a variety of techniques. First, off-chip equipment is connected to the CMOS circuits to measure electric current. These methods may include interfacing automated testing equipment (ATE) precision measuring units to the device under test. A problem using these techniques, however, is that test times are slow. Long pauses are often necessary for currents to settle and for the measurement systems to recover from the high switching currents. Depending on some of the capacitance values involved, up to 40 milliseconds may be required to make a single I.sub.DDQ measurement. Since thousands of tests may be needed to screen modern VLSI chips effectively, these current measurements may add many seconds to overall test time.
Another off-chip test method used to measure I.sub.
in FIG. 1, I.sub. DDQ 108 would drop back to the initial low level once the inverter circuit 101 stabilize. With the gate - oxide blemish 103, however, I.sub. DDQ 109 Current remains abnormally high. 
 An interesting item to notice is that these types of faults, which result in an abnormally eminent I.sub. DDQ, do not necessarily result in a running racing circuit failure. rather, defects often happen as infant mortality or reliability problems in CMOS circuits. One explanation for the lack of functional failures is that gate - oxide short pants are often high resistance blemish which cause only small leakage current. In addition, CMOS circuits usually have a large randomness margin. As a result, small amounts of leakage current may not effect the ultimate end product value of the circuit. Since these types of faults to do not always result in functional failures, these defects will not always be identified with traditional stick - at fault testing. 
 To detect chip with eminent resistance caused leakage trouble, burn - in is often used as an acceleration proficiency. Burn - in is a method used to accelerate failures in a device if there is a weak feature or defect that is sensitive to extended operation of the device. Defects such as unaccented oxide, narrow-minded silicon or metal lines, small resistive contact, or other similar defects normally become more apparent with burn - in and are consequently more readily identified and may, therefore, fail " stuck at " testing. A tradeoff with burn - in, however, is the hearty time and cost that may be involve depending on the character of device being burned - in. 
 I.sub. DDQ test measurements are used on CMOS circuit as a supplemental technique to name these defects. To conduct I.sub. DDQ current measurements, testers use a variety of techniques. First, off - chip equipment is connected to the CMOS circuits to measure electric stream. These methods may include interfacing automatize testing equipment (ATE) precision measuring unit to the device under test. A problem using these proficiency, however, is that test times are slow. Long pauses are often necessary for current to sink and for the measurement system to recover from the high switch currents. Depending on some of the capacitor values involved, up to 40 milliseconds may be required to make a single I.sub. DDQ measurement. Since thousands of tests may be needed to screen advanced VLSI chips effectively, these current measurements may total many seconds to overall test clock time. 
 Another off - chip test method used to measure I.sub.
 in FIG. 1, I.sub.DDQ 108 would drok back to the inijiql low level once thd inverter circuit 101 stabilizxd. Wuth tye gate-oxide defect 103, huwever, I.slb.DDQ 109 Cuerenu remains abnormally high.
An intsvestiug point to note is that tvese types of xajlcs, which result in an abnormally higr I.sub.DCQ, do not necesswrilj wesumn ln a functional circuit failure. Jnstead, defects oftem materialize as infant mogtallty or reliability problems ib CMJW circuits. Ove explanauimn for the lack of functional failures is that gate-oxide syorhv are often high resistance defects fhich csuse only smalk lxakate currents. In additimn, CMOS circuits ufually haee a large noise maegun. As a rasulg, smxll akohnts ov lxakage currsnt may not effect the ultimatt otnlut value of the cyrsuit. Since these types of faults to do tot always result in functuonal failures, these fefects wyll not always be identified with traditional stuwk-at hajlt tcstivt.
Tl detect chips with high resistance caused lewiabe problems, burn-ln is often used ax wn wcceleration jechniqbs. Gurn-in is a method used tj accwlerate fwilutes in a device if there is a weak featlre ir defect that is densitive tu exjended operation of the devicz. Defedts such as weak oxisds, narrow silicov og medal lines, small resistive sontacts, ir ocher simklar defeces usually become more apparent wihh butn-in atd are thegefore more readily identified eid may, therefpra, fdil "stuch at" besting. A tradejff with burn-iu, howevex, is tfe substannial time and cost trat may be inellved dependmng on thq type od devicd being burned-im.
I.sub.DDQ neft mwasurements are uscd on DMOS circuits aw a supplemental trchviqte tp ygentify thesa dewecgx. To zonduct I.sun.DDD cutrent measurements, tasteds use a variety og bechniquew. First, jff-chip equipkent is connected uo the CMUS citcuyts to measure electric currenf. These mfthjds may incltde lntetfacing autpmated testing equipment (ATE) precision neasuring units to the device under tgst. A problem nsing ehese tecvniques, however, is tyat test times art slow. Long pauses are kften tecesdary for currents to settle and for the measurement systems to recover frim the high switchjng vurrettf. Depenqing un some of the cspacitance values involved, up tu 40 milliveeonds may be required to make a single I.sub.DAQ measurement. Since thohsands og tests may be needed to screen modern VLSI chips effecbively, thwse chrrent mearurements may add kany szconds to oveeall test time.
Anoghet lff-chip tfst kechod used to measure I.sub.
in FIG. 1, I.sub.DDQ 108 would drop the low level the inverter circuit defect however, I.sub.DDQ 109 remains abnormally high. interesting point to note is that types of faults, which result in an abnormally high I.sub.DDQ, do not necessarily in a functional circuit failure. Instead, defects often materialize as infant mortality or problems CMOS One for the lack of functional failures is that gate-oxide shorts are often high resistance defects which only small leakage currents. In addition, CMOS circuits have a large noise As a result, small amounts leakage may not the output of the circuit. these types of faults to do not always result in functional failures, these defects will not always identified with fault testing. detect with resistance caused leakage is often used as an acceleration a method used to accelerate failures in a if there a weak feature or defect that sensitive to extended operation of the device. Defects as weak oxides, narrow silicon or metal lines, small resistive contacts, or other similar defects more apparent with burn-in are therefore more identified may, fail at" testing. tradeoff with burn-in, however, is the substantial time and cost that be involved depending on the type of device being burned-in. measurements used on CMOS as a supplemental technique identify defects. To conduct I.sub.DDQ testers a First, equipment connected to the CMOS to measure electric current. These may include interfacing automated units to the device under test. A problem these techniques, however, is that test times slow. Long pauses are often necessary for currents to settle and for measurement systems from the high switching currents. Depending on some the capacitance values involved, to 40 milliseconds may be required to make a I.sub.DDQ Since thousands tests may be to screen modern chips effectively, these may add seconds overall off-chip test method used to measure
 in FIG. 1, I.sub.DDQ 108 would drop back To the initiAl low LevEl oNcE the InveRter circuit 101 staBIlizEd. With the gate-oxide defeCt 103, howEvER, I.suB.dDq 109 CurrEnt remaINs ABNorMaLlY hiGh.
aN iNtereStiNg point To note is thAt tHeSe types of fauLTs, Which resulT in An abnormally HigH I.sub.DdQ, Do nOT neceSsaRily rEsult iN A functIonal circUiT FailurE. instead, DEFeCts oFten materialize as INfANt mortality or rEliabiLiTY pROBleMs iN CMOS circuItS. One eXPlanatiON fOR THe lACk of functionaL failures is THat Gate-oxIdE shORts are Often HiGH reSistance defEcts Which causE only sMAll leakAGe curreNts. In aDdiTioN, CMOs CiRcUitS uSUalLY hAve A LarGe noise mArGiN. As a rEsulT, SMALl amOunTs of LeakaGe current may nOt eFfecT The UltimAte ouTput VaLue of The cirCuit. SInCe these types of fAultS to do not aLwaYs ResUlT in fuNCtionaL faIluRes, thesE defectS WilL nOT ALwAys be identified witH tRADiTional stUck-at fAUlT tESting.
To dEtEct ChipS WIth hiGh reSIsTance cauSed leaKAgE pRoblems, BuRn-in is OfTen UseD as an ACcelEratioN techniqUe. BurN-In is a method useD To accelerate fAIlUREs IN a deVicE if there is a Weak FEatuRe or DEfEct THat is SensiTiVE tO Extended operation of ThE devicE. DefeCts such as weak Oxides, narrOW SIlicon or MetaL LiNEs, small resistiVe conTacts, or othER similar DefecTs usuallY become moRE Apparent WitH buRn-iN anD ARe Therefore more REAdilY iDentifiEd aNd may, thEreForE, faIl "sTuCk at" testiNg. A tradeOfF wItH bUrn-In, howEVer, is the SuBstAnTiaL time ANd cost That mAy be InVoLVed DependiNG oN THe tyPe Of DeviCe bEiNg burNed-iN.
i.suB.DDQ tesT measuremEntS Are uSeD oN CMOS ciRcuits as a suppLeMental techNiQue To idenTIFy these dEfects. To conduct I.sub.DDQ cURrent meAsuRemenTs, teSters use a VarIety of TecHNiques. first, oFf-chiP eQuiPMEnt is CONnEctEd To the CMOS cIRCuiTs to mEaSure ElectriC current. These methoDS maY include interFacIng aUTOmAteD TeSTinG eQUipMENt (ATE) precision mEasuring unItS To The device uNDer TeSt. A probLem usinG thesE TechniqUes, howeveR, is that teSt TimeS ARe sLow. Long pauSes are ofTen necessARy for CUrRents To sEttle aNd For The meAsuremENt sYstemS to recOvEr from The hiGh SwitchinG currents. Depending on somE of the CapacItaNce values InvOLveD, up to 40 millIsecOnds may be rEquIreD to maKe a SIngle i.sub.ddQ MeaSUremeNt. SiNCe thousanDS oF teSTS mAy be needed tO SCReeN modeRn VlsI chipS effEctively, these currENt measurements May aDD ManY seCOnds To Overall test timE.
AnOtHER off-chip TeSt method useD to measuRe i.Sub.
 in FIG. 1, I.sub.DDQ 108would drop  back  to  th einit iallow level once theinverter circuit 101 s tabil iz e d. W i th  thegate-ox i de d efe ct  1 03,  h o we ver,I.s ub.DDQ109 Curren t r em ains abnorma l ly  high.
Anint eresting poi ntto not eist hat t hes e typ es off aults,  which re su l t in a n  abnorm a l ly  hig h I.sub.DDQ, do n o tn ecessarily res ult in  a fu n c tio nal  circuit f ai lure. Instead ,  d e f e cts often materia lize as inf a ntmortal it y o r  relia bilit yp rob lems in CMO S ci rcuits. O ne exp l anation for the  lackoffun ctio n al  f ail ur e s i s  t hat gat e-oxidesh or ts ar e of t e n high  re sist ancedefects which  ca useo nly  smal l lea kage  c urren ts. In  addi ti on, CMOS circui ts u sually ha vealar ge  nois e  margi n.Asa resul t, smal l  am ou n t s  o f leakage currentma y no t effect  the u l ti ma t e output  v alu e of t he ci rcui t .Since th ese ty p es  o f fault sto dono t a lwa ys re s ultin fun ctionalfailu r es, these defe c ts will not a l wa y s  b e  ide nti fied with t radi t iona l st u ck -at fault  test in g .T o detect chips with  h igh re sista nce caused le akage prob l e m s, burn- in i s  o f ten used as an  acce leration t e chnique.  Burn -in is a  method u s e d to acc ele rat e f ail u r es  in a devicei f  the re  is a w eak  featur e o r d efe ctth at is sen sitive t oex te nd edopera t ion of t he  de vi ce.  Defe c ts suc h asweak  o xi d es,  narrow si l i conor  m etal  li ne s, sm allr esi stive c ontacts,oro ther  s im ilar de fects usually  b ecome more  a ppa rent w i t h burn-i n and are therefore mor e  readil y i denti fied  and may,  th erefor e,f ail "s tuck a t" te st ing . A tra d e of f w it h burn-in, h owe ver,is  the  substa ntial time and cos t  th at may be inv olv ed d e p en din g  o n  th et ype o f device beingburned-in. 
I . su b.DDQ test mea su rements  are us ed on CMOS ci rcuits as  a supple me ntal t ech nique to i dentifythese def e cts.T ocondu ctI.sub. DD Q c urren t meas u rem ents,  teste rs  use a  vari et y of tec hniques. First, off-chi p equi pment  is  connecte d t o  th e CMOS ci rcui ts to meas ure  el ectri c c u rrent . Th e se  me t hodsmayi nclude in t er fac i n gautomated t e s t ing  equi pme n t (ATE ) pr ecision measuring units to the d evic e und ert est.  A  problem using  th es e techniqu es , however,is thatte s t tim es are  slow.  Long p a u se s  are o ften  ne cessary f orcu r rents t ose t tle an d fo rthe me asurem e nt s y s tems to recoverfromt h e hig h  sw itchi ng  curren t s. D epending o n some of t he cap acit ancevaluesin volved , u pto 40 mill i seconds m ay be  requir ed  tomak e a si ngle I .sub. DDQme asu rement. S i n ce th ou s and s of  test smaybe needed to scree n m o dern VL SI  ch i p s effe c ti v e ly, thesecur rentm e asurements maya dd manysecond s to o verallt est  t ime.
An oth e r  off-chip  test met h odus ed t o measur eI.su b. 
 in_FIG. 1,_I.sub.DDQ 108 would drop_back to_the_initial low_level_once the inverter_circuit 101 stabilized._With the gate-oxide defect_103, however, I.sub.DDQ_109_Current remains abnormally high.
An interesting point to note is that these types of faults,_which_result in_an_abnormally_high I.sub.DDQ, do not necessarily_result in a functional circuit_failure. Instead,_defects often materialize as infant mortality or reliability_problems_in CMOS circuits._One explanation for the lack of functional failures is_that gate-oxide shorts are often high_resistance defects which_cause_only_small leakage currents. In_addition, CMOS circuits usually have a_large noise margin. As a result,_small amounts of leakage current may not_effect the ultimate output value of_the circuit. Since these types_of faults_to do not always result_in functional failures,_these defects_will not always_be identified with traditional stuck-at fault_testing.
To detect chips_with high resistance caused leakage problems,_burn-in_is often used_as_an_acceleration technique._Burn-in is a_method_used to_accelerate_failures in a device if there_is_a weak feature or defect that is_sensitive to extended operation_of_the device. Defects such_as weak oxides, narrow silicon_or metal lines, small resistive contacts,_or other_similar defects_usually become more apparent with burn-in and are therefore more readily_identified and may, therefore, fail "stuck_at" testing. A tradeoff_with burn-in,_however,_is the substantial_time_and cost_that may be involved depending on the_type of_device being burned-in.
I.sub.DDQ test measurements are_used on CMOS circuits_as_a supplemental technique to identify these_defects. To conduct I.sub.DDQ current measurements,_testers use a variety of_techniques._First,_off-chip equipment is connected to_the CMOS circuits to measure electric_current. These methods_may include interfacing automated testing equipment (ATE)_precision_measuring units to the device under_test._A problem using these techniques, however,_is_that_test times are slow. Long_pauses are often necessary for currents_to settle and for the measurement systems to recover_from the high_switching currents. Depending on some_of_the_capacitance values involved, up to 40 milliseconds may be required_to make_a single I.sub.DDQ_measurement. Since thousands of tests may be needed to screen_modern VLSI chips effectively, these current measurements_may add many seconds to overall test time.
Another off-chip test method_used to measure I.sub.