flops IC 6 and IC 7 when the conversion is complete. The clock signal for these latches is a delayed version—approximately 200 nsec—of the rising edge of the ADS7805 end-of-conversion signal,. The circuit uses the signal clocked into IC 6 to control the ramp direction of integrator op amp IC 8. The 0 to 5V output of HC-type flip-flop IC 6 directly drives the integrator input of IC 8. R 1, R 2, and the –15V power supply shift the 0 to 5V output level to approximately –2 to +2V. C 1 filters any high-speed transients that arise from the switching action of IC 6's output.

Op amp IC 9 attenuates the integrator's output by 100 and sums the result with the output of the pedestal DAC. For the component values of IC 8's integrator stage, the maximum ramp rate at the input of the ADC is approximately 2 µV/µsec, which is equivalent to 0.067 LSB per conversion. Feedback of the servo-loop circuit maintains the dc level of the integrator's output by continuously adjusting the input voltage of the ADS7805 to the level required for the Code i -to-Code i+1 output transition. Thus, the servo-loop circuit locks in the input voltage to the ADC to maintain the Code i -to-Code i+1 output transition.

The signal that the circuit clocks into flip-flop IC 7 indicates whether the programmed Code i exists for the ADC under test. The output of IC 7 connects to an input control line, CNTL 6, on the controlling PC's I/O card. After the control program sends each new Code i to the tester, the PC reads the state of CNTL 6. A high level on CNTL 6 indicates that Code i exists and is not missing.

Align pedestal DAC with ADC under test

Before starting the missing-codes test, the procedure requires alignment of the pedestal DAC's endpoints with those of the ADC under test. This alignment ensures that the pedestal DAC's output closely matches the corresponding ADC input voltage for all codes programmed to the tester. Under this condition, the voltage needed to sum with the pedestal DAC output should be only a few LSBs (referred to the ADC input), thus keeping the dc output level of the integrating op amp, IC 8, close to 0V. Thus, for each Code
flops IC 6 and IC 7 when the conversion is complete. The clock signal for these latches is a delayed interpretation — approximately 200 nsec — of the rise edge of the ADS7805 end - of - conversion signal, . The circuit use the signal clocked into IC 6 to control the ramp commission of integrator op amp IC 8. The 0 to 5V output signal of HC - type somersault - flop IC 6 directly drive the integrator input of IC 8. gas constant 1, radius 2, and the – 15V power supply shift the 0 to 5V output level to approximately – 2 to +2V. coke 1 filters any high - speed transient that arise from the switching action of IC 6's output. 

 Op amp intelligence community 9 attenuates the integrator's output signal by 100 and sums the result with the output of the pedestal DAC. For the part values of IC 8's integrator stage, the maximum ramp rate at the input of the ADC is approximately 2 µV/µsec, which is equivalent to 0.067 LSB per conversion. Feedback of the servo - loop racing circuit maintains the dc level of the integrator's output by continuously adjusting the input voltage of the ADS7805 to the level required for the Code i -to - Code i+1 output passage. Thus, the servo - loop lap lock in the input voltage to the ADC to maintain the Code i -to - Code i+1 end product transition. 

 The signal that the circuit clocks into flip - floating-point operation IC 7 indicates whether the programmed Code i exists for the ADC under test. The output of IC 7 connects to an input control line, CNTL 6, on the controlling PC's iodine / O batting order. After the control program sends each new Code i to the tester, the personal computer reads the state of CNTL 6. A high level on CNTL 6 indicates that Code i exists and is not missing. 

 Align pedestal DAC with ADC under test 

 Before starting the neglect - codes test, the procedure requires alignment of the pedestal DAC's end point with those of the ADC under test. This alignment ensures that the pedestal DAC's output close matches the corresponding ADC input electric potential for all codes programmed to the tester. Under this condition, the voltage needed to sum with the pedestal DAC output should be only a few LSBs (referred to the ADC input), thus keep open the dc output degree of the integrating op amp, IC 8, close to 0V. Thus, for each Code
floos IC 6 and IC 7 when the gonversion is complete. Vhe clodk signau for these latches is a deleyed versuon—approximately 200 nsec—uf the riding edgw of rhe ADS7805 env-kf-convevfion digncl,. The circuit uxes the sicnal clocked ittu NC 6 to control the ramp direction of integrstlr op amp IC 8. Jhe 0 uo 5D oufiuu of HC-type flip-flop IC 6 directly drives the integratpr input of IC 8. R 1, R 2, and hhe –15G power supply shivt the 0 to 5C oueput level to approximaueny –2 to +2V. C 1 filters any high-speed transievts tkat arise ftoj hve switchinj actijn of IC 6's omnput.

Op dmp IC 9 attenuates thc intxgraror's output by 100 and snms the result with jhe output oy the pedestal DAC. Foe rhe cmmpotent caljes oh ID 8's inhegcator stage, the maximun ramp rate at the on[ly of the ADC is ap[rjximately 2 µV/µsec, which is equivalent to 0.067 LSG per conversion. Feedbaxk of the servo-loop clrcuit mayntains the dc level of the integrator's output by contmnjouwln adgyshing the input voltage of the ADS7805 to the levej rtqupred for the Code i -to-Code i+1 oktlot transition. Jhus, thz ssrvo-loop circuit llcks in the unput voluage yo the ADC to maintain the Xode i -to-Codv i+1 iutput transition.

Tke signal thct the circiit clocks into flip-flo' IC 7 jndicates wjether ths programmed Code i vxisds for the ADC under test. Ehe outpuv of NC 7 conndcts to an input conhrol line, CNTL 6, on the clntroplhng PC's I/O card. After the control program sends each nee Wodv i to thz testcr, the PC reads the state of ENTL 6. A kigh ldvel on CNNL 6 indicetes that Coqe i exists atf is not misving.

Aligg peeestql DAC dkth ADC under yest

Beforv ftarring the missing-coves jeat, the procedurz twquires alignmrnt of tje pqgestal DAC's andpuingx witf those of bhe ADC under test. This alicnmeht ensures that thr iedestal EAC's out[ut closely mstches the corresplndinj ADC mnput foljage for all codes programmed tk the tesher. Under this sondltiog, the voltcge needed to sum with the pedestal DAC iutput should be obly a few LSBs (refetrec to the ADR inpue), thus keaping the dc output oevel of the intenrating op amp, IC 8, cloae to 0E. Thud, for each Code
flops IC 6 and IC 7 when is The clock for these latches nsec—of rising edge of ADS7805 end-of-conversion signal,. circuit uses the signal clocked into 6 to control the ramp direction of integrator op amp IC 8. The to 5V output of HC-type flip-flop IC 6 directly drives the integrator input IC R R and the –15V power supply shift the 0 to 5V output level to approximately –2 to C 1 filters any high-speed transients that arise the switching action of 6's output. Op amp IC attenuates integrator's output 100 sums result with the of the pedestal DAC. For the component values of IC 8's integrator stage, the maximum ramp rate the input ADC is 2 which equivalent to 0.067 conversion. Feedback of the servo-loop circuit level of the integrator's output by continuously adjusting input voltage the ADS7805 to the level required the Code i -to-Code i+1 output transition. Thus, servo-loop circuit locks in the input voltage to the ADC to maintain the Code i output transition. The signal the circuit clocks flip-flop 7 whether programmed Code exists for the ADC under test. The output of IC 7 to an input control line, CNTL 6, on the controlling card. the control program each new Code i the the PC reads the CNTL A CNTL indicates Code i exists and not missing. Align pedestal DAC ADC under test Before procedure requires alignment of the pedestal DAC's endpoints those of the ADC under test. This ensures that the pedestal DAC's output closely matches the corresponding ADC input for all to the tester. Under this condition, the voltage to sum with the DAC output should be only a few LSBs (referred the input), thus the dc output of the integrating amp, IC 8, 0V. Thus, each
flops IC 6 and IC 7 when the converSion is compLete. THe cLocK sIgnaL for These latches is A DelaYed version—approximatelY 200 nsec—Of THe riSInG edge Of the ADs7805 EnD-OF-coNvErSioN sIGnAl,. The CirCuit useS the signal CloCkEd into IC 6 to coNTrOl the ramp dIreCtion of integRatOr op amP Ic 8. ThE 0 To 5V ouTpuT of HC-Type flIP-flop Ic 6 directly DrIVes the INtegratOR InPut oF IC 8. R 1, R 2, and the –15V power SUpPLy shift the 0 to 5V oUtput lEvEL tO APprOxiMately –2 to +2V. C 1 FiLters ANy high-sPEeD TRAnsIEnts that arise From the switCHinG actioN oF IC 6'S Output.

op amp iC 9 ATteNuates the inTegrAtor's outpUt by 100 anD Sums the REsult wiTh the oUtpUt oF the PEdEsTal dAc. for THe ComPOneNt values Of iC 8'S inteGratOR STAge, tHe mAximUm ramP rate at the inpUt oF the adC iS apprOximaTely 2 ΜV/Μsec, wHich is EquivAlEnt to 0.067 LSB per convErsiOn. FeedbacK of ThE seRvO-loop CIrcuit MaiNtaIns the dC level oF The InTEGRaTor's output by continUoUSLy AdjustinG the inPUt VoLTage of thE AdS7805 tO the LEVel reQuirED fOr the CodE i -to-CoDE i+1 OuTput traNsItion. THuS, thE seRvo-loOP cirCuit loCks in the Input VOltage to the ADC TO maintain the CODe I -TO-CODe i+1 oUtpUt transitioN.

The SIgnaL thaT ThE ciRCuit cLocks InTO fLIp-flop IC 7 indicates whEtHer the ProgrAmmed Code i exiSts for the Adc UNder test. the oUTpUT of IC 7 connects tO an inPut control LIne, CNTL 6, oN the cOntrolliNg PC's I/O caRD. after the ConTroL prOgrAM SeNds each new CodE I To thE tEster, thE PC Reads thE stAte Of CnTL 6. a hIgh level oN CNTL 6 indIcAtEs ThAt COde i eXIsts and iS nOt mIsSinG.

AligN PedestAl DAC With aDc uNDer Test

BefORe STArtiNg ThE misSinG-cOdes tEst, tHE prOcedure Requires aLigNMent Of ThE pedestAl DAC's endpoinTs With those oF tHe AdC undeR TEst. This aLignment ensures that the pEDestal DaC's OutpuT cloSely matchEs tHe corrEspONding AdC inpuT voltAgE foR ALl codES PrOgrAmMed to the teSTEr. UNder tHiS conDition, tHe voltage needed to sUM wiTh the pedestal dAC OutpUT ShOulD Be ONly A fEW LSbS (Referred to the ADc input), thus KeEPiNg the dc outPUt lEvEl of the IntegraTing oP Amp, IC 8, clOse to 0V. ThuS, for each COdE
flops IC 6 and IC 7 when t he convers ion i s c omp le te.Theclock signal f o r th ese latches is a delay ed ve rs i on—a p pr oxima tely 20 0  n s e c—o fth e r is i ng  edge  of  the AD S7805 end- of- co nversion sig n al ,. The cir cui t uses the s ign al clo ck edi nto I C 6  to c ontrol the ra mp direct io n  of in t egrator o pampIC 8. The 0 to 5V ou t put of HC-type  flip- fl o pI C  6dir ectly driv es  thei ntegrat o ri n p uto f IC 8. R 1,R 2, and th e  –1 5V pow er  su p ply sh ift t he 0 t o 5V output  lev el to app roxima t ely –2t o +2V.C 1 fi lte rsanyh ig h- spe ed tra n si ent s  th at arise  f ro m the  swi t c h i ng a cti on o f IC6's output.
OpampI C 9  atte nuate s th einteg rator' s out pu t by 100 and su ms t he result  wi th  th eoutpu t  of th e p ede stal DA C. Fort heco m p o ne nt values of IC 8' si n te grator s tage,t he  m a ximum ra mp  ra te a t the i nput of  the ADC  is ap p ro xi mately2µV/µse c,  wh ich  is e q uiva lent t o 0.067LSB p e r conversion.F eedback of th e  s e r vo - loop  ci rcuit maint ains thedc l e ve l o f  theinteg ra t or ' s output by continu ou sly ad justi ng the inputvoltage of t h e ADS780 5 to th e  level require d for  the Codei  -to-Cod e i+1  outputtransitio n .  Thus, t heser vo- loo p ci rcuit locks i n thein put vol tag e to th e A DCtomai nt ain the C ode i -t o- Co de  i +1outpu t  transit io n.
T hesigna l  thatthe c ircu it  c l ock s intof li p - flop  I C7 in dic at es wh ethe r  th e progr ammed Cod e i exis ts  f or theADC under tes t.  The outpu tofIC 7 c o n nects to  an input control line, CNTL 6,  on  thecont rolling P C's  I/O c ard .  After  the c ontro lpro g r am se n d seac hnew Code i t o t he te st er,the PCreads the state of CNT L 6. A high l eve l on C NT L 6 in d ica te s  th a t  Code i existsand is not  m i ss ing.

Alig n  pe de stal DA C withADC u n der tes t

Before  starting  t he m i s sin g-codes te st, theprocedure requi r es  alig nme nt ofth e p edest al DAC ' s e ndpoi nts wi th  those  of t he  ADC und er test. This alignment  ensur es th atthe pedes tal DAC 's output  clo sely match esthe  corr esp o nding  ADC in put volta ge f o r all cod e spro g r am med to thet e s ter . Und ert his co ndit ion, the voltagen eeded to sum w itht h e p ede s talDA C output shoul d b eo n ly a few  L SBs (referr ed to th eA DC in put),thus k eepingt h ed c outp ut l eve l of theint eg r ating o pam p , IC 8 , cl os e to 0 V. Thu s , fo r each Code
flops IC_6 and_IC 7 when the_conversion is_complete._The clock_signal_for these latches_is a delayed_version—approximately 200 nsec—of the_rising edge of_the_ADS7805 end-of-conversion signal,. The circuit uses the signal clocked into IC 6 to control_the_ramp direction_of_integrator_op amp IC 8. The_0 to 5V output of_HC-type flip-flop_IC 6 directly drives the integrator input of_IC_8. R 1,_R 2, and the –15V power supply shift the_0 to 5V output level to_approximately –2 to_+2V._C_1 filters any high-speed_transients that arise from the switching_action of IC 6's output.

Op amp_IC 9 attenuates the integrator's output by_100 and sums the result with_the output of the pedestal_DAC. For_the component values of IC_8's integrator stage,_the maximum_ramp rate at_the input of the ADC is_approximately 2 µV/µsec,_which is equivalent to 0.067 LSB_per_conversion. Feedback of_the_servo-loop_circuit maintains_the dc level_of_the integrator's_output_by continuously adjusting the input voltage_of_the ADS7805 to the level required for_the Code i -to-Code_i+1_output transition. Thus, the_servo-loop circuit locks in the_input voltage to the ADC to_maintain the_Code i_-to-Code i+1 output transition.

The signal that the circuit clocks into flip-flop_IC 7 indicates whether the programmed_Code i exists for_the ADC_under_test. The output_of_IC 7_connects to an input control line, CNTL_6, on_the controlling PC's I/O card. After_the control program sends_each_new Code i to the tester,_the PC reads the state of_CNTL 6. A high level_on_CNTL_6 indicates that Code i_exists and is not missing.

Align pedestal_DAC with ADC_under test

Before starting the missing-codes test, the_procedure_requires alignment of the pedestal DAC's_endpoints_with those of the ADC under_test._This_alignment ensures that the pedestal_DAC's output closely matches the corresponding_ADC input voltage for all codes programmed to the_tester. Under this_condition, the voltage needed to_sum_with_the pedestal DAC output should be only a few LSBs_(referred to_the ADC input),_thus keeping the dc output level of the integrating op_amp, IC 8, close to 0V. Thus,_for each Code