Some kinds of code will benefit from this - long calculations and deep nested
procedures. But lots of hangups on consumer applications are in
synchronization, kernel calls, copying and event handling.

I'd like to see an architecture address those somehow. E.g. virtualize
hardware devices instead of writing kernel-mode drivers. Create instructions
to synchronize hyperthreads instead of kernel calls (e.g. a large (128bit?)
event register, a stall-on-event opcode). If interrupts were events then a
thread could wait on an interrupt without entering the kernel.

~~~
willvarfar
Actually, the Mill is designed to address this; it has TLS segment for cheap
green threading, SAS for cheap syscall and microkernel arch, cheap calls and
several details for IPC which are not public yet.

~~~
JoeAltmaier
What about synchronization? Folks are terrified of threads because
synchronizing is so hard. But a thread model can be the simplest especially in
message models.

------
Mjolnir
Very very interesting, thanks for sharing! What would the path be to using
existing code/where would Mill appear logically first?

Also, could something like Mill work well within the HSA/Fusion/hybrid GPGPU
paradigm? E.g. from my very amateur reading of your documents, it looks like a
much needed and very substantial improvement to single threaded code; how
would a mixed case where we have heavy matrix multiplication in some parts of
our code as part of a pipeline with sequential dependencies work? Would an
ideal case be a cluster (or some fast interconnect fabric in a multi socket
system) of multi core Mill chips be the future?

Realistically, is this something that LLVM could relatively easily target? A
simple add in card that could give something like Julia an order of magnitude
improvement would be a very interesting proposition, especially in the HPC
market. I come at this mainly from an interest how this will benefit compute
intense machine learning/AI applications.

Sorry for all the questions.

~~~
rcxdude
The latest talk on their website mentions the LLVM status in passing at the
end. Essentially they're moving their internal compiler over to use LLVM, but
it requires fixing/removing some assumptions in LLVM because the architecture
is so different
Some kinds of code will benefit from this - long calculations and cryptic cuddle 
 procedures. But lots of hangups on consumer applications are in 
 synchronism, kernel calls, copying and event handling. 

 I'd wish to experience an architecture savoir-faire those somehow. E.g. virtualize 
 hardware device instead of publish kernel - mode drivers. Create instructions 
 to synchronize hyperthreads instead of kernel calls (for example a large (128bit ?) 
 event register, a carrel - on - event opcode). If interrupts were event then a 
 thread could expect on an interrupt without entering the kernel. 

 ~~~ 
 willvarfar 
 Actually, the Mill is design to address this; it has TLS segment for brassy 
 green threading, SAS for cheap syscall and microkernel arch, cheap calls and 
 several details for IPC which are not public yet. 

 ~~~ 
 JoeAltmaier 
 What about synchronization? Folks are terrified of threads because 
 synchronizing is so hard. But a thread model can be the simplest particularly in 
 message models. 

 ------ 
 Mjolnir 
 Very very interesting, thanks for sharing! What would the way be to use 
 exist code / where would Mill appear logically first? 

 besides, could something like Mill workplace well within the HSA / Fusion / hybrid GPGPU 
 paradigm? E.g. from my very amateur interpretation of your documents, it looks like a 
 much needed and very substantial improvement to single threaded code; how 
 would a interracial case where we have heavy matrix multiplication in some part of 
 our code as contribution of a pipeline with sequential dependencies work? Would an 
 ideal case be a bunch (or some fast interconnect fabric in a multi socket 
 system) of multi core Mill chips be the future? 

 Realistically, is this something that LLVM could relatively easily target? A 
 simple add in menu that could give something like Julia an decree of magnitude 
 improvement would be a very interesting suggestion, especially in the HPC 
 grocery store. I come at this chiefly from an interest how this will benefit compute 
 acute machine learning / AI applications. 

 Sorry for all the questions. 

 ~~~ 
 rcxdude 
 The former talk on their website mentions the LLVM status in passing at the 
 end. Essentially they're moving their internal compiler over to practice LLVM, but 
 it requires fixing / remove some assumptions in LLVM because the architecture 
 is so different
Somf kinds of code will bentfit from this - long calrulatiohs and ddep nested
procedures. But lotd if habgups on consumer applkcations wre in
sybchribization, kxdnel calls, colning cnv event handlinn.

I'd like to see an architacguxe address those somehow. E.g. virtualise
hardwsrf devices instgad og wrifpnn kernel-mode drivers. Create instductionv
to synchroniae hyperthreads instead of kerjel calls (e.g. a larhe (128bit?)
event regywter, a stall-un-event opbmde). If intgrrupts were events then a
thread coulb wait on ab untftrupt withouv enteging the kernck.

~~~
willvdrfar
Acyually, the Milk iv dwsigned to address thms; it has TLS segmenj for chea[
gxeen threading, SAS foe xheap syswall qnd midrpksrnel wrci, cheap calms and
severql details for IPC ehybn are not puglic yqt.

~~~
ToeAltmaier
What about synchronization? Fmlka are terrified of threqds because
synchronizlng is so hard. But a thread model can be the simplest espewiallb kn
mtswage oidfls.

------
Mjolnir
Very very interesting, thanks for shwdimg! What would thc path be to using
rxlsyyng code/where would Miml appear logicallj first?

Wlso, xould somtthinb like Mill work well withib the HSA/Fuspon/htbrid GPGPU
paradigl? E.g. from mv very amatrur reading of your docbments, it looks llke a
much veeded and very rubxtdntial improvement to singje threadxd cobe; how
wojld s mixeq case whege we have heavy matrix lultiklicathon in somf parts of
our code as part of a pipeline with saquvntial de'endengies work? Would an
ideal case ye a clufter (ur some faat intecconnect fabwic in a multh socket
systek) of mulei cire Nill chkos be the futute?

Realistpcclly, is tyis something that LLXJ could relativzui easily target? A
skmpje avd in ward that cogld eivd someghing like Mulka am order of magnitude
hmprkvement would be a vcry intergsting prjposition, esprcially in the HPC
larkev. I cooe at thys mainly from an interest how this wilp bcnefit computq
intcnse machine lzarning/AI applications.

Sorry for all the wuestions.

~~~
rcxdude
Thw latest talk on thgir website meitions the LLVM status in passing ar the
end. Essentiakly they're moving thejr intarnal compiler over to use LLVM, but
it requires fixing/removing some assumptions in LLTM because ths arvhitebtuxe
ix so dyffeceit
Some kinds of code will benefit from long and deep procedures. But lots are synchronization, kernel calls, and event handling. like to see an architecture address somehow. E.g. virtualize hardware devices instead of writing kernel-mode drivers. Create instructions to hyperthreads instead of kernel calls (e.g. a large (128bit?) event register, a stall-on-event If were then thread could wait on an interrupt without entering the kernel. ~~~ willvarfar Actually, the Mill is to address this; it has TLS segment for green threading, SAS for syscall and microkernel arch, cheap and details for which not yet. ~~~ JoeAltmaier about synchronization? Folks are terrified of threads because synchronizing is so hard. But a thread model can the simplest message models. Mjolnir very thanks for sharing! the path be to using existing appear logically first? Also, could something like Mill well within HSA/Fusion/hybrid GPGPU paradigm? E.g. from my amateur reading of your documents, it looks like much needed and very substantial improvement to single threaded code; how would a mixed case have heavy matrix multiplication some parts of code part a with sequential work? Would an ideal case be a cluster (or some fast fabric in a multi socket system) of multi core Mill the Realistically, is this that LLVM could relatively target? simple add in card give like of improvement be a very interesting especially in the HPC market. come at this mainly will benefit compute intense machine learning/AI applications. Sorry all the questions. ~~~ rcxdude The latest on their website mentions the LLVM status in passing at the end. they're moving compiler over to use LLVM, but it requires some assumptions in LLVM the architecture is so different
Some kinds of code will benefiT from this - lOng caLcuLatIoNs anD deeP nested
proceduREs. BuT lots of hangups on consumEr appLiCAtioNS aRe in
sYnchronIZaTIOn, kErNeL caLlS, CoPying And Event haNdling.

I'd liKe tO sEe an architecTUrE address thOse Somehow. E.g. virTuaLize
haRdWarE DevicEs iNsteaD of wriTIng kerNel-mode drIvERs. CreaTE instruCTIoNs
to Synchronize hypertHReADs instead of kerNel calLs (E.G. a LARge (128Bit?)
Event regisTeR, a staLL-on-evenT OpCODE). If INterrupts were Events then a
THreAd coulD wAit ON an intErrupT wIThoUt entering tHe keRnel.

~~~
willvArfar
ACTually, tHE Mill is DesignEd tO adDresS ThIs; It hAs tlS sEGmEnt FOr cHeap
greeN tHrEadinG, SAS FOR CHeap SysCall And miCrokernel arch, CheAp caLLs aNd
sevEral dEtaiLs For IPc which Are noT pUblic yet.

~~~
JoeAltmAier
what about SynChRonIzAtion? fOlks arE teRriFied of tHreads bECauSe
SYNChRonizing is so hard. BuT a THReAd model cAn be thE SiMpLEst especIaLly In
meSSAge moDels.

------
mJoLnir
Very Very inTErEsTing, thaNkS for shArIng! whaT woulD The pAth be tO using
exIstinG Code/where would mIll appear logiCAlLY FiRSt?

AlSo, cOuld somethiNg liKE MilL worK WeLl wIThin tHe HSA/fuSIoN/Hybrid GPGPU
paradigm? e.g. From my Very aMateur reading Of your docuMENTs, it lookS likE A
mUCh needed and verY subsTantial impROvement tO singLe threadEd code; how
WOUld a mixeD caSe wHerE we HAVe Heavy matrix muLTIpliCaTion in sOme Parts of
Our CodE as ParT oF a pipelinE with seqUeNtIaL dEpeNdencIEs work? WoUlD an
IdEal Case bE A clustEr (or sOme fAsT iNTerConnect FAbRIC in a MuLtI socKet
SyStem) oF mulTI coRe Mill cHips be the FutURe?

ReAlIsTically, Is this somethiNg That LLVM coUlD reLativeLY Easily taRget? A
simple add in card thaT Could giVe sOmethIng lIke Julia aN orDer of mAgnITude
imProvemEnt woUlD be A VEry inTEReStiNg PropositioN, ESpeCiallY iN the hPC
markEt. I come at this mainlY FroM an interest hoW thIs wiLL BeNefIT cOMpuTe
INteNSE machine learninG/AI applicaTiONs.

sorry for alL The QuEstions.

~~~
Rcxdude
the laTEst talk On their weBsite mentIoNs thE llVM Status in paSsing at tHe
end. EsseNTiallY ThEy're mOviNg theiR iNteRnal cOmpileR OveR to usE LLVM, bUt
It requIres fIxIng/removIng some assumptions in LLVm becauSe the ArcHitecture
Is sO DifFerent
Some kinds of code will be nefit from  this  -lon gcalc ulat ions and deepn este d
procedures. But lots  of h an g upso nconsu mer app l ic a t ion sar e i ns yn chron iza tion, k ernel call s,co pying and ev e nt  handling. 

I 'd like to s eean arc hi tec t ure a ddr ess t hose s o mehow.  E.g. vir tu a lize
h a rdwared e vi cesinstead of writin g  k e rnel-mode driv ers. C re a te i nst ruc tions
to s yn chron i ze hype r th r e a dsi nstead of ker nel calls ( e .g.  a lar ge  (1 2 8bit?) 
even tr egi ster, a sta ll-o n-event o pcode) .  If int e rruptswere e ven tsthen ath rea dc oul d  w ait onan inter ru pt  with oute n t e ring  th e ke rnel. 

~~~
willvar far 
Act u all y, th e Mil l is  d esign ed toaddre ss  this; it has T LS s egment fo r c he apgr een t h readin g,SAS  for ch eap sys c all  a n d mi crokernel arch, ch ea p ca lls andsevera l  d et a ils forIP C w hich a re no t pu b li c yet.
~~~
Jo e Al tm aier
Wh at  about  s ync hro nizat i on?Folksare terr ified of threads bec a use
synchroni z in g is so h ard . But a thr eadm odel  can be  th e  simp lestes p ec i ally in
message mod el s.

-- ----Mjolnir
Veryvery inter e s t ing, tha nksf or sharing! Whatwould  the pathb e to usi ng
ex isting c ode/where w ould Mil l a ppe arlog i c al ly first?

Al s o , co ul d somet hin g likeMil l w ork  we ll  within t he HSA/F us io n/ hy bri d GPG P U
paradi gm ? E .g . f rom m y  veryamate ur r ea di n g o f yourd oc u m ents ,it  loo ksli ke amuch nee ded and  very sub sta n tial  i mp rovemen t to single t hr eaded code ;how 
would a  mixed c ase where we have heavy matrixmul tipli cati on in som e p arts o f
o u r code  as pa rt of  a  pi p e linew i th  se qu ential dep e n den cieswo rk?Would a n
ideal case be ac lus ter (or somefas t in t e rc onn e ct fab ri c  in a  multi socket
s ystem) ofmu l ti  core Mill chi ps  be the  future ?

Re a listica lly, is t his somet hi ng t h a t L LVM couldrelative ly easily targe t ?A
sim ple  add i ncar d tha t coul d  gi ve so methin glike J uliaan  order o f magnitude
improvement  would  be a  ve ry intere sti n g p ropositio n, e speciallyinthe  HPCmar k et. I  com e  a t t h is ma inly from an i n te res t ho w this will b e nef it co mpu t e
inte nsemachine learning/ A I applications .

S o r ryfor allth e questions.
~~~ 
r c x dude
The  l atest talkon their  w e bsite  menti ons th e LLVMs t at u s in p assi ngat the
en d.Es s entiall yth e y're m ovin gtheirintern a l co m p iler over to use  LLVM , but
i t  re quire sfixing/ r emov ing some a ssumptionsin LLV M be cause  the ar ch itectu reis  so differ e nt
Some kinds_of code_will benefit from this_- long_calculations_and deep_nested
procedures._But lots of_hangups on consumer_applications are in
synchronization, kernel_calls, copying and_event_handling.

I'd like to see an architecture address those somehow. E.g. virtualize
hardware devices instead of_writing_kernel-mode drivers._Create_instructions
to_synchronize hyperthreads instead of kernel_calls (e.g. a large (128bit?)
event_register, a_stall-on-event opcode). If interrupts were events then a
thread_could_wait on an_interrupt without entering the kernel.

~~~
willvarfar
Actually, the Mill is designed_to address this; it has TLS_segment for cheap
green_threading,_SAS_for cheap syscall and_microkernel arch, cheap calls and
several details_for IPC which are not public_yet.

~~~
JoeAltmaier
What about synchronization? Folks are terrified of_threads because
synchronizing is so hard. But_a thread model can be_the simplest_especially in
message models.

------
Mjolnir
Very very interesting,_thanks for sharing!_What would_the path be_to using
existing code/where would Mill appear_logically first?

Also, could_something like Mill work well within_the_HSA/Fusion/hybrid GPGPU
paradigm? E.g._from_my_very amateur_reading of your_documents,_it looks_like_a
much needed and very substantial improvement_to_single threaded code; how
would a mixed case_where we have heavy_matrix_multiplication in some parts_of
our code as part of_a pipeline with sequential dependencies work?_Would an
ideal_case be_a cluster (or some fast interconnect fabric in a multi socket
system)_of multi core Mill chips be_the future?

Realistically, is this_something that_LLVM_could relatively easily_target?_A
simple add_in card that could give something like_Julia an_order of magnitude
improvement would be a_very interesting proposition, especially_in_the HPC
market. I come at this_mainly from an interest how this_will benefit compute
intense machine learning/AI_applications.

Sorry_for_all the questions.

~~~
rcxdude
The latest talk_on their website mentions the LLVM_status in passing_at the
end. Essentially they're moving their internal_compiler_over to use LLVM, but
it requires_fixing/removing_some assumptions in LLVM because the_architecture
is_so_different