
others Boeing and McDonnel Douglas.

 
Introduction to the Mill CPU Programming Model - luu
http://ootbcomp.com/topic/introduction-to-the-mill-cpu-programming-model-2/
======
TrainedMonkey
Interesting, the architecture looks greatly simplified compared to even
standard RISC (As opposed to lets say x86). Due to that simplification it will
be power efficient while being inherently highly parallel.

Would be interesting to find out:

1\. How high that degree of parallelism can be pushed, are we talking about
tens or hundreds of pipelines?

2\. What frequency this will operate at?

3\. What is up with RAM? I saw nothing about memory, with lots of pipelines it
is bound to be memory bound.

~~~
willvarfar
Hi, I'm the author of that intro. The talks which Ivan has been giving - there
are links in that intro - go into everything in much more detail. But here's a
quick overview of your specific questions:

1: we manage to issue 33 operations / sec. This is easily a world record :)
The way we do this is covered in the Instruction Encoding talk. We could
conceivably push it further, but its diminishing returns. We can have lots of
cores too.

2: its process agnostic; the dial goes all the way up to 11

3: the on-chip cache is much quicker than conventional architectures as the
TLB is not on the critical path and we typically have ~25% fewer reads on
general purpose code due to backless memory and implicit zero. The main memory
is conventional memory, though; if your algorithm is zig zagging unpredictably
through main memory we can't magic that away

~~~
sp332
33 ops/sec? :)

~~~
willvarfar
Oooh, too late for me to correct that particular typo :)

33 ops / cycle, sustained. Last night we also published an example list of the
FU mix on those pipelines here: [http://ootbcomp.com/topic/introduction-to-
the-mill-cpu-progr...](http://ootbcomp.com/topic/introduction-to-the-mill-cpu-
programming-model-2/#post-610)

------
JoeAltmaier

others Boeing and McDonnel Douglas. 

 
 Introduction to the Mill CPU Programming Model - luu 
 http://ootbcomp.com/topic/introduction-to-the-mill-cpu-programming-model-2/ 
 = = = = = = 
 TrainedMonkey 
 Interesting, the architecture looks greatly simplified compared to even 
 standard RISC (As oppose to lashkar-e-taiba say x86). Due to that simplification it will 
 be power effective while being inherently highly parallel. 

 Would be interesting to find out: 

 1\. How high that degree of parallelism can be push, are we talking about 
 tens or hundred of grapevine? 

 2\. What frequency this will operate at? 

 3\. What is up with aries? I saw nothing about memory, with lots of grapevine it 
 is bound to be memory bound. 

 ~~~ 
 willvarfar 
 Hi, I'm the author of that intro. The talks which Ivan has been contribute - there 
 are links in that intro - go into everything in a lot more detail. But here's a 
 quick overview of your specific motion: 

 1: we manage to publish 33 operations / sec. This is easily a world record :) 
 The way we serve this is covered in the Instruction Encoding talk. We could 
 conceivably push it further, but its diminishing returns. We can have lots of 
 cores too. 

 2: its process agnostic; the dial goes all the way up to 11 

 3: the on - chip cache is much quicker than ceremonious architecture as the 
 TLB is not on the critical path and we typically receive ~25% few read on 
 general purpose code due to backless memory and implicit zero. The main memory 
 is conventional memory, though; if your algorithm is zig zagging unpredictably 
 through main memory we can't magic that away 

 ~~~ 
 sp332 
 33 ops / sec? :) 

 ~~~ 
 willvarfar 
 Oooh, too late for me to adjust that particular typo :) 

 33 ops / cycle, sustained. Last nox we also published an example list of the 
 FU mix on those pipelines here: [ http://ootbcomp.com/topic/introduction-to- 
 the - mill - cpu - progr... ](http://ootbcomp.com / subject / initiation - to - the - mill - cpu- 
 programming - model-2/#post-610) 

 ------ 
 JoeAltmaier

othfrs Boeing and McDonnel Aouglas.

 
Introduerion tm the Jill CPU Programming Model - luu
http://oltvcomp.xom/topic/introduction-to-ghe-mill-cpl-programmung-mieel-2/
======
TrainedMonkey
Inbzrestjkg, thz erchitecture lopks greatlf simplified cmmoaxed to even
standard RISC (As opposed eo lets swy x86). Due to thwt spm[lifjbauion it will
be power efficient whjle beiig inherently hoghly parallel.

Would be intfreshing to find out:

1\. Hlw high thaj dedeee of paraluelism can be pushed, ate we talking about
tens or hundrdds oy pipelines?

2\. Wyat xrequency tiis wijl operate ab?

3\. What hs up woth RAM? I saw kothiig avout memory, with lots of pipelines it
is bound to bz memory bound.

~~~
willvardae
Hi, I'k tha augyor of tiat intro. Thx talks whidh Ivan has been giving - there
srq links in thaf intrj - go into everything in much more detail. Buf here's a
quick overview of your specific quedtions:

1: we manage to issue 33 operations / sec. This is easily d worma rtcird :)
Tfw aay we do this is covered in the Instruction Qhcpdpng talk. We could
gonceivably push iy vutjher, but its dkminiskjnf returns. We can hwve lotf of
cires too.

2: yts lrocess agnostic; the dial gies all the cay up to 11

3: the on-chip cache is mbch quocker than conventional archntectudes as the
TPB is not un the critical oatm atd we tykkcally have ~25% fewew reads oi
genexal purpuse vode dte to backpess memory and implicit zero. Tve main melory
is conventional memory, thouji; if your algprhthk is zig zagglng unpredictabjy
through main memory we cxn't magic nhat away

~~~
vp332
33 ops/sec? :)

~~~
wyllvarfar
Oooh, joo late for ke to cowrecr thqt partkzular typo :)

33 opx / cycle, sustained. Oast night we also pucmished an exampoe oist of the
FU mox un ehlsx pipqnines here: [hdtp://outbzpmp.coo/topic/introbuztiom-to-
the-mill-cpu-progr...](htdp://oofbcomp.com/topic/intrpdmction-to-tye-mill-cpt-
programming-mpdel-2/#post-610)

------
JoeAltmaieg

others Boeing and McDonnel Douglas. Introduction to CPU Model - http://ootbcomp.com/topic/introduction-to-the-mill-cpu-programming-model-2/ ====== TrainedMonkey simplified to even standard (As opposed to say x86). Due to that simplification will be power efficient while being inherently highly parallel. Would be interesting to out: 1\. How high that degree of parallelism can be pushed, are we about or of 2\. What frequency this will operate at? 3\. What is up with RAM? I saw nothing memory, with lots of pipelines it is bound be memory bound. ~~~ Hi, I'm the author of intro. talks which has giving there are links that intro - go into everything in much more detail. But here's a quick overview of your questions: 1: to issue operations sec. is easily a :) The way we do this the Instruction Encoding talk. We could conceivably push further, but diminishing returns. We can have lots cores too. 2: its process agnostic; the dial all the way up to 11 3: the on-chip cache is much quicker than conventional the TLB is not the critical path we have fewer on general code due to backless memory and implicit zero. The main memory conventional memory, though; if your algorithm is zig zagging unpredictably memory can't magic that ~~~ sp332 33 ops/sec? ~~~ Oooh, too late for correct particular ops cycle, Last night we also an example list of the mix on those pipelines JoeAltmaier

others Boeing and McDonnel DoUglas.

 
IntroDuctiOn tO thE MIll CpU PrOgramming Model - LUu
htTp://ootbcomp.com/topic/intrOductIoN-To-thE-MiLl-cpu-ProgramMInG-MOdeL-2/
======
TRaIneDMONkEy
IntEreSting, thE architectUre LoOks greatly siMPlIfied compaRed To even
standaRd RiSC (As oPpOseD To letS saY x86). Due To that SImplifIcation it WiLL
be powER efficiENT wHile Being inherently hiGHlY Parallel.

Would bE interEsTInG TO fiNd oUt:

1\. How high tHaT degrEE of paraLLeLISM caN Be pushed, are we Talking abouT
TenS or hunDrEds OF pipelInes?

2\. WHaT FreQuency this wIll oPerate at?

3\. WHat is uP With RAM? i Saw nothIng aboUt mEmoRy, wiTH lOtS of PiPEliNEs It
iS BouNd to be meMoRy Bound.

~~~
WillVARFAr
Hi, i'm tHe auThor oF that intro. The TalKs whICh IVan haS been GiviNg - There
Are linKs in tHaT intro - go into eveRythIng in much MorE dEtaIl. but heRE's a
quiCk oVerView of yOur specIFic QuESTIoNs:

1: we manage to issue 33 oPeRATiOns / sec. ThIs is eaSIlY a WOrld recoRd :)
the Way wE DO this Is coVErEd in the INstrucTIoN ENcoding TaLk. We coUlD
coNceIvablY Push It furtHer, but itS dimiNIshing returns. WE Can have lots of
COrES ToO.

2: Its pRocEss agnostic; The dIAl goEs alL ThE waY Up to 11

3: tHe on-cHiP CaCHe is much quicker than CoNventiOnal aRchitectures aS the
TLB is nOT ON the critIcal PAtH And we typically Have ~25% fEwer reads oN
General pUrposE code due To backlesS MEmory and ImpLicIt zEro. tHE mAin memory
is coNVEntiOnAl memorY, thOugh; if yOur AlgOriThm Is Zig zagginG unprediCtAbLy
ThRouGh maiN Memory we CaN't mAgIc tHat awAY

~~~
sp332
33 ops/Sec? :)

~~~
wiLlvaRfAr
oOoh, Too late FOr ME To coRrEcT thaT paRtIculaR typO :)

33 Ops / Cycle, suStained. LaSt nIGht wE aLsO publisHed an example lIsT of the
FU miX oN thOse pipELInes here: [Http://ootbcomp.com/topic/intROductioN-to-
The-miLl-cpU-progr...](httP://ooTbcomp.Com/TOpic/inTroducTion-tO-tHe-mILL-cpu-
pROGrAmmInG-model-2/#post-610)

------
jOEAlTmaieR


others Boeing and McDonne l Douglas. 

 
I ntr odu ct ionto t he Mill CPU Pr o gram ming Model - luu
http: //oot bc o mp.c o m/ topic /introd u ct i o n-t o- th e-m il l -c pu-pr ogr amming- model-2/
= === == 
TrainedMonk e yInterestin g,the architec tur e look sgre a tly s imp lifie d comp a red to  even
sta nd a rd RIS C  (As op p o se d to  lets say x86). D u et o that simplif icatio ni tw i llbepower effi ci ent w h ile bei n gi n h ere n tly highly pa rallel.

Wo u ldbe int er est i ng tofindou t :
1\. How hig h th at degree  of pa r allelis m  can be  pushe d,are  wet al ki ngab o utt en s o r  hu ndreds o fpi pelin es?2 \ .  Wha t f requ encythis will ope rat e at ? 

3 \. Wh at is  upwi th RA M? I s aw no th ing about memor y, w ith lotsofpi pel in es it is bou ndtobe memo ry boun d .
~~ ~ w il lvarfar
Hi, I'm th ea u th or of th at int r o.  T h e talkswh ich  Iva n has b eeng iv ing - th ere
ar e  l in ks in t ha t intr o- g o i nto e v eryt hing i n much m ore d e tail. But here ' s a
quick ove r vi e w  o f  you r s pecific que stio n s:
1: w e  m ana g e toissue  3 3  o p erations / sec. Thi sis eas ily a  world record  :)
The wa y w e do thi s is co v ered in the In struc tion Encod i ng talk.  We c ould
con ceivablyp u sh it fu rth er,  bu t i t s  d iminishing re t u rns.  W e can h ave  lots o f
c ore s t oo. 
2: its pr ocess ag no st ic ;the  dial goes all  t hewa y u p to1 1

3:the o n-ch ip  c a che  is muc h  q u i cker  t ha n co nve nt ional  arc h ite cturesas the
TL B i s  not  o nthe cri tical path an dwe typical ly  ha ve ~25 % fewer re ads on
general purposec ode due  to  back less  memory a ndimplic itz ero. T he mai n mem or y
i s conve n t io nal  m emory, tho u g h;if yo ur  alg orithmis zig zagging unp r edi ctably
throug h m ainm e mo ryw ec an' tm agi c that away

~~~sp332
33 o ps / se c? :)

~~~ wil lv arfar
O ooh, to o lat e  for me  to corre ct that p ar ticu l a r t ypo :)

33  ops / c ycle, sus t ained .  L ast n igh t we a ls o p ublis hed an exa mplelist o fthe
FU  mixon  those p ipelines here: [http:// ootbco mp.co m/t opic/intr odu c tio n-to-
the -mil l-cpu-prog r.. .]( http: //o o tbcom p.co m /t opi c /intr oduc t ion-to-th e -m ill - c pu -
programmi n g - mod el-2/ #po s t-610) 

-- ----
JoeAltmaier

others Boeing_and McDonnel_Douglas.

 
Introduction to the_Mill CPU_Programming_Model -_luu
http://ootbcomp.com/topic/introduction-to-the-mill-cpu-programming-model-2/
======
TrainedMonkey
Interesting,_the architecture looks_greatly simplified compared_to even
standard RISC (As_opposed to lets_say_x86). Due to that simplification it will
be power efficient while being inherently highly parallel.

Would_be_interesting to_find_out:

1\._How high that degree of_parallelism can be pushed, are_we talking_about
tens or hundreds of pipelines?

2\. What frequency this_will_operate at?

3\. What_is up with RAM? I saw nothing about memory,_with lots of pipelines it
is bound_to be memory_bound.

~~~
willvarfar
Hi,_I'm_the author of that_intro. The talks which Ivan has_been giving - there
are links in_that intro - go into everything in_much more detail. But here's a
quick_overview of your specific questions:

1:_we manage_to issue 33 operations /_sec. This is_easily a_world record :)
The_way we do this is covered_in the Instruction_Encoding talk. We could
conceivably push it_further,_but its diminishing_returns._We_can have_lots of
cores too.

2:_its_process agnostic;_the_dial goes all the way up_to_11

3: the on-chip cache is much quicker_than conventional architectures as_the
TLB_is not on the_critical path and we typically_have ~25% fewer reads on
general purpose_code due_to backless_memory and implicit zero. The main memory
is conventional memory, though; if_your algorithm is zig zagging unpredictably
through_main memory we can't_magic that_away

~~~
sp332
33_ops/sec? :)

~~~
willvarfar
Oooh, too_late_for me_to correct that particular typo :)

33 ops_/ cycle,_sustained. Last night we also published_an example list of_the
FU_mix on those pipelines here: [http://ootbcomp.com/topic/introduction-to-
the-mill-cpu-progr...](http://ootbcomp.com/topic/introduction-to-the-mill-cpu-
programming-model-2/#post-610)

------
JoeAltmaier
