.com/item?id=2192629>

~~~
neutronicus
The other half of his point was specially tuned hardware - the author seems to
believe that the type-checking, gc, etc. don't cripple performance the way
they do on x86.

I don't know if he's _right_, but that seems to be his point.

~~~
ohyes
The idea is that you would have bits in the hardware dedicated to type
checking and garbage collection. The example being, that in the assembly
language/machine code, you may have a single arithmetic '+' operation.

Determining which hardware path to use to add two numbers would be done in the
hardware itself. Check the type bits of the numbers and feed it into my ALU.
Compare this to an x86 lisp, or compiled C, where 'type' of a 'number' is
determined by the assembly code instruction that is used on it.

This isn't just a performance improvement, it is also an improvement in the
safety of the dynamic language.

There are a lot of different things that you could do for garbage collection.
You could have in-hardware reference counting, or 'dirty' and 'clean' (or
color) bits, for a mark and sweep collector, or 'generational' bits for an
ephemeral garbage collector.

The idea is that any time you take something out of software, and put it into
specialized hardware, you should get a performance improvement.

This doesn't mean that the lisp on a chip would be faster than C on a
comparable x86 chip, it means that the things that make lisp (and other
functional languages) safer and easier to use would be supported in hardware--
therefore not slowing things down as noticeably.

~~~
derleth
> it means that the things that make lisp (and other functional languages)
> safer and easier to use would be supported in hardware-- therefore not
> slowing things down as noticeably.

Or, at least, forcing every language implementation on that hardware to use
the same safety mechanisms, making some apples-to-apples benchmarks
impossible.

It would be interesting to see what a C implementation for that hypothetical
modern Lisp machine (CADDR?) would look like.

A close parallel is AMPC
.com / item?id=2192629 > 

 ~~~ 
 neutronicus 
 The other half of his point was specially tune hardware - the writer seems to 
 believe that the type - checking, gc, etc. don't cripple operation the way 
 they do on x86. 

 I don't know if he's _ good _, but that seems to be his point. 

 ~~~ 
 ohyes 
 The mind is that you would have bits in the hardware dedicate to type 
 checking and garbage collection. The exemplar being, that in the fabrication 
 language / machine code, you may have a single arithmetic' +' process. 

 Determining which hardware path to use to total two numbers would be done in the 
 hardware itself. Check the type spot of the numbers and feed it into my ALU. 
 Compare this to an x86 lisp, or compiled C, where' type' of a' numeral' is 
 determined by the assembly code instruction that is used on it. 

 This isn't just a performance improvement, it is also an improvement in the 
 safety of the dynamic language. 

 There are a lot of different things that you could do for garbage collection. 
 You could suffer in - hardware reference counting, or' dirty' and' blank' (or 
 semblance) bits, for a mark and sweep collector, or' generational' morsel for an 
 ephemeral garbage collector. 

 The idea is that any time you take something out of software, and place it into 
 specialized hardware, you should get a performance improvement. 

 This doesn't mean that the lisp on a chip would be faster than C on a 
 comparable x86 chip, it think of that the things that make lisp (and other 
 functional speech) safe and easier to use would be supported in hardware-- 
 therefore not slowing thing down as noticeably. 

 ~~~ 
 derleth 
 > it means that the thing that make lisp (and other functional languages) 
 > dependable and easier to practice would be supported in hardware-- therefore not 
 > slowing things down as perceptibly. 

 Or, at least, forcing every language implementation on that hardware to use 
 the like safety mechanisms, making some apple - to - apples benchmark 
 impossible. 

 It would be interesting to see what a C implementation for that hypothetical 
 modern Lisp machine (CADDR ?) would look like. 

 A close parallel is AMPC
.com/ltem?id=2192629>

~~~
neutronicus
The othtr half of his ponbt was specizlly tundd hardware - the author seemd ro
belueve that the type-checying, gc, enc. don't ceippow performaide the way
theg do mi x86.

I don't know lf he's _righd_, but that seeks tl be his point.

~~~
ohyes
The idea is that you woilf have bits in the rardsare dedicated to type
checking and garbagt collection. The ecample being, that in the adsemhly
language/machine code, you mqy hwce a single xrithmetic '+' operation.

Dgtermining which hardware path tu use to add twi bumhgrs would be done in the
hardware itsenf. Checl the type bitx oh thw numbers and feed it into my ALU.
Comparg this to dn x86 lisp, or compilwd C, whgre 'tfpe' ud a 'nujbxr' js
detegmiied by the zssembly coee instruction that if used on it.

Thjs isn'e tust a performance improvement, it is alvo zn improvement in the
sadety of the dynamic lwnguage.

Thqre are a lot of different things that you could go foc earyqge cuolfction.
You could have in-hardware reference cougfimg, or 'dirty' and 'glean' (or
color) bits, flr w mark and swgep collecfor, or 'generationap' bits sor ab
ephemeraj gatbage collector.

The idea is rhat any timv yoy take something obt of softwaxe, and put ot into
specialized hardcare, yku should gft a perfkfmance improvemevt.

Tmis doesn't mean that the lisp on a chi' woukd be fxstet than S on a
compwrablc x86 chip, it means tjat tke thhngs that lake lisp (and other
functional leiguages) safer atd vasier to use eould be suppjrted in hardwcre--
thereyore nut slowing things down as noeiceably.

~~~
derledj
> it means tiat the tringw thqt make uisp (and other functioncj labguages)
> safer and casiet fo use would be sukpirted in hardwsre-- thqrvfoce noe
> slowing thitgs aowv as nuticeably.

Or, xt lrast, forcing every ldnguzge implementation ok that hatdware to use
the same xafety mechanisms, lakinj some applrs-tj-apples benchmarks
impossible.

It would be inberesting to fee qhat a C impkementation for that hypothetical
modern Lisp machine (CADDE?) would look like.

A elpse parallek is WMPC
.com/item?id=2192629> ~~~ neutronicus The other half of was tuned hardware the author seems gc, don't cripple performance way they do x86. I don't know if he's but that seems to be his point. ~~~ ohyes The idea is that would have bits in the hardware dedicated to type checking and garbage collection. example that the language/machine code, you may have a single arithmetic '+' operation. Determining which hardware path to use add two numbers would be done in the itself. Check the type of the numbers and feed into ALU. Compare to x86 or compiled C, 'type' of a 'number' is determined by the assembly code instruction that is used on it. This just a it is an in safety of the There are a lot of different could do for garbage collection. You could have reference counting, 'dirty' and 'clean' (or color) bits, a mark and sweep collector, or 'generational' bits an ephemeral garbage collector. The idea is that any time you take something out of put it into specialized you should get performance This mean the lisp a chip would be faster than C on a comparable x86 it means that the things that make lisp (and other safer easier to use be supported in hardware-- not things down as noticeably. > means that lisp other functional languages) > and easier to use would supported in hardware-- therefore as noticeably. Or, at least, forcing every language on that hardware to use the same mechanisms, making some apples-to-apples benchmarks impossible. It would be interesting to see a C that hypothetical modern Lisp machine (CADDR?) would look A close parallel is
.com/item?id=2192629>

~~~
neutronicus
The otHer half of hIs poiNt wAs sPeCialLy tuNed hardware - the AUthoR seems to
believe that the Type-cHeCKing, GC, eTc. don'T cripplE PeRFOrmAnCe The WaY
ThEy do oN x86.

I Don't knoW if he's _righT_, buT tHat seems to be HIs Point.

~~~
ohyes
the Idea is that yoU woUld havE bIts IN the hArdWare dEdicatED to typE
checking AnD GarbagE CollectION. THe exAmple being, that in tHE aSSembly
language/MachinE cODe, YOU maY haVe a single aRiThmetIC '+' operatIOn.

dETErmINing which hardWare path to uSE to Add two NuMbeRS would Be donE iN The
Hardware itsElf. CHeck the tyPe bits OF the numBErs and fEed it iNto My AlU.
CoMPaRe ThiS tO An x86 LIsP, or COmpIled C, wheRe 'TyPe' of a 'NumbER' IS
DeteRmiNed bY the aSsembly code inStrUctiON thAt is uSed on It.

ThIs Isn't jUst a peRformAnCe improvement, it Is alSo an improVemEnT in ThE
safeTY of the DynAmiC languaGe.

There ARe a LoT OF DiFferent things that yOu COUlD do for gaRbage cOLlEcTIon.
You coUlD haVe in-HARdwarE refEReNce countIng, or 'dIRtY' aNd 'clean' (Or
Color) bItS, foR a mArk anD SweeP colleCtor, or 'geNeratIOnal' bits for an
ePHemeral garbagE CoLLEcTOr.

ThE idEa is that any Time YOu taKe soMEtHinG Out of SoftwArE, AnD Put it into
specializeD hArdwarE, you sHould get a perfOrmance impROVEment.

ThiS doeSN't MEan that the lisp On a chIp would be fASter than c on a
cOmparablE x86 chip, it mEANs that thE thIngS thAt mAKE lIsp (and other
fuNCTionAl LanguagEs) sAfer and EasIer To uSe wOuLd be suppoRted in haRdWaRe--
ThEreFore nOT slowing ThIngS dOwn As notICeably.

~~~
DerleTh
> it MeAnS ThaT the thiNGs THAt maKe LiSp (anD otHeR funcTionAL laNguages)
> Safer and eAsiER to uSe WoUld be suPported in hardWaRe-- thereforE nOt
> sLowing THIngs down As noticeably.

Or, at least, foRCing eveRy lAnguaGe imPlementatIon On that HarDWare to Use
the Same sAfEty MEChaniSMS, mAkiNg Some apples-TO-AppLes beNcHmarKs
imposSible.

It would be inteREstIng to see what a c imPlemENTaTioN FoR ThaT hYPotHETical
modern Lisp Machine (CADdR?) WOuLd look like.

a CloSe ParalleL is AMPC
.com/item?id=2192629>

~~~ 
neutronic us
Th e o the rhalf  ofhis point wass peci ally tuned hardware -the a ut h or s e em s tobelieve th a t  th ety pe- ch e ck ing,gc,  etc. d on't cripp lepe rformance th e  w ay
they do  on  x86.

I don 'tknow i fhe' s  _rig ht_ , but  thats eems t o be hispo i nt.

~ ~ ~
ohyes T he  ide a is that you wou l dh ave bits in th e hard wa r ed e dic ate d to typech eckin g  and ga r ba g e col l ection. The e xample bein g , t hat in  t hea ssembl y
lan gu a ge/ machine cod e, y ou may ha ve a s i ngle ar i thmetic  '+' o per ati on.De te rmi ni n g w h ic h h a rdw are path  t ouse t o ad d t w o nu mbe rs w ouldbe done in th e
h ardw a reitsel f. Ch eckth e typ e bits  of t he  numbers and fe ed i t into my  AL U. 
Co mp are t h is toanx86  lisp,or comp i led  C , w he re 'type' of a 'nu mb e r 'is
deter minedb yth e  assembl ycod e in s t ructi on t h at  is used  on it . 
Th is isn' tjust a  p erf orm ancei mpro vement , it isalsoa n improvementi n the
safetyo ft h ed ynam iclanguage.
Ther e  are  a l o tofd iffer ent t hi n gs that you could do f or  garba ge co llection.
You  could hav e i n-hardwa re r e fe r ence counting,  or ' dirty' and 'clean'(or
c olor) bi ts, for a m ark andswe epcol lec t o r,  or 'generati o n al'bi ts foranephemer algar bag e c ol lector.
The idea  i sth at  an y tim e  you tak esom et hin g out of sof tware , an dpu t  it  into
s p ec i a lize dha rdwa re,  y ou sh ould get  a perf ormance i mpr o veme nt .
This d oesn't mean t ha t the lisp  o n a  chipw o uld be f aster than C on a
compa r able x8 6 c hip,it m eans that  th e thin gst hat ma ke lis p (an doth e r 
func t i on alla nguages) s a f erand e as ierto usewould be supported inhardware--
th ere fore n ot  sl o wi n g t hi n gsd o wn as noticeabl y.

~~~
de rl e th 
> it mean s  th at  the th ings th at ma k e lisp(and othe r functio na l la n g uag es)
> safe r and ea sier to u s e wou l dbe su ppo rted i nhar dware -- the r efo re no t
> sl ow ing th ingsdo wn as no ticeably.

Or, at least , forc ing e ver y languag e i m ple mentation  onthat hardw are  to  usethe samesafe t ymec h anism s, m a king some ap ple s - to -apples ben c h m ark s
imp oss i ble.
It w ould be interesti n g to see whata Ci m ple men t atio nfor that hypot het ic a l 
modernLi sp machine(CADDR?)  w o uld l ook li ke.

A  closep a ra l lel is  AMP C
.com/item?id=2192629>

~~~
neutronicus
The other_half of_his point was specially_tuned hardware_-_the author_seems_to
believe that the_type-checking, gc, etc._don't cripple performance the_way
they do on_x86.

I_don't know if he's _right_, but that seems to be his point.

~~~
ohyes
The idea is_that_you would_have_bits_in the hardware dedicated to_type
checking and garbage collection. The_example being,_that in the assembly
language/machine code, you may have_a_single arithmetic '+'_operation.

Determining which hardware path to use to add two_numbers would be done in the
hardware_itself. Check the_type_bits_of the numbers and_feed it into my ALU.
Compare this_to an x86 lisp, or compiled_C, where 'type' of a 'number' is
determined_by the assembly code instruction that_is used on it.

This isn't_just a_performance improvement, it is also_an improvement in_the
safety of_the dynamic language.

There_are a lot of different things_that you could_do for garbage collection.
You could have_in-hardware_reference counting, or_'dirty'_and_'clean' (or
color)_bits, for a_mark_and sweep_collector,_or 'generational' bits for an
ephemeral garbage_collector.

The_idea is that any time you take_something out of software,_and_put it into
specialized hardware,_you should get a performance_improvement.

This doesn't mean that the lisp_on a_chip would_be faster than C on a
comparable x86 chip, it means that_the things that make lisp (and_other
functional languages) safer and_easier to_use_would be supported_in_hardware--
therefore not_slowing things down as noticeably.

~~~
derleth
> it means_that the_things that make lisp (and other_functional languages)
> safer and_easier_to use would be supported in_hardware-- therefore not
> slowing things down_as noticeably.

Or, at least, forcing_every_language_implementation on that hardware to_use
the same safety mechanisms, making some_apples-to-apples benchmarks
impossible.

It would_be interesting to see what a C_implementation_for that hypothetical
modern Lisp machine (CADDR?)_would_look like.

A close parallel is AMPC