BL 0x0200
#define RX_MISS_ENBL 0x0400
#define RX_128_BYTE_ENBL 0x0800
#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
#define RX_DEST_MATCH_ENBL 0x8000

/* PP_LineCTL - Line Control bit definition - Read/write */
#define SERIAL_RX_ON 0x0040
#define SERIAL_TX_ON 0x0080
#define AUI_ONLY 0x0100
#define AUTO_AUI_10BASET 0x0200
#define MODIFIED_BACKOFF 0x0800
#define NO_AUTO_POLARITY 0x1000
#define TWO_PART_DEFDIS 0x2000
#define LOW_RX_SQUELCH 0x4000

/* PP_SelfCTL - Software Self Control bit definition - Read/write */
#define POWER_ON_RESET 0x0040
#define SW_STOP 0x0100
#define SLEEP_ON 0x0200
#define AUTO_WAKEUP 0x0400
#define HCB0_ENBL 0x1000
#define HCB1_ENBL 0x2000
#define HCB0 0x4000
#define HCB1 0x8000

/* PP_BusCTL - ISA Bus Control bit definition - Read/write */
#define RESET_RX_DMA 0x0040
#define MEMORY_ON 0x0400
#define DMA_BURST_MODE 0x0800
#define IO_CHANNEL_READY_ON 0x1000
#define RX_DMA_SIZE_64K 0x2000
#define ENABLE_IRQ 0x8000

/* PP_TestCTL - Test Control bit definition - Read/write */
#define LINK_OFF 0x0080
#define ENDEC_LOOPBACK 0x0200
#define AUI_LOOPBACK 0x0400
#define BACKOFF_OFF 0x0800
#define FDX_8900 0x4000
#define FAST_TEST 0x8000

/* PP_RxEvent - Receive Event Bit definition - Read-only */
#define RX_IA
BL 0x0200 
 # define RX_MISS_ENBL 0x0400 
 # define RX_128_BYTE_ENBL 0x0800 
 # define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 
 # define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 
 # define RX_DEST_MATCH_ENBL 0x8000 

 / * PP_LineCTL - Line Control bit definition - Read / spell * / 
 # specify SERIAL_RX_ON 0x0040 
 # define SERIAL_TX_ON 0x0080 
 # define AUI_ONLY 0x0100 
 # define AUTO_AUI_10BASET 0x0200 
 # define MODIFIED_BACKOFF 0x0800 
 # specify NO_AUTO_POLARITY 0x1000 
 # define TWO_PART_DEFDIS 0x2000 
 # define LOW_RX_SQUELCH 0x4000 

 / * PP_SelfCTL - Software Self Control morsel definition - Read / compose * / 
 # define POWER_ON_RESET 0x0040 
 # define SW_STOP 0x0100 
 # define SLEEP_ON 0x0200 
 # define AUTO_WAKEUP 0x0400 
 # define HCB0_ENBL 0x1000 
 # specify HCB1_ENBL 0x2000 
 # define HCB0 0x4000 
 # define HCB1 0x8000 

 / * PP_BusCTL - ISA Bus Control act definition - Read / spell * / 
 # define RESET_RX_DMA 0x0040 
 # define MEMORY_ON 0x0400 
 # define DMA_BURST_MODE 0x0800 
 # define IO_CHANNEL_READY_ON 0x1000 
 # define RX_DMA_SIZE_64 K 0x2000 
 # define ENABLE_IRQ 0x8000 

 / * PP_TestCTL - Test Control bit definition - Read / write * / 
 # specify LINK_OFF 0x0080 
 # define ENDEC_LOOPBACK 0x0200 
 # define AUI_LOOPBACK 0x0400 
 # define BACKOFF_OFF 0x0800 
 # specify FDX_8900 0x4000 
 # define FAST_TEST 0x8000 

 / * PP_RxEvent - Receive Event Bit definition - Read - merely * / 
 # define RX_IA
BL 0d0200
#define RX_MISS_ENBL 0x0400
#defike RX_128_BYTE_ENBL 0x0800
#dgfune TX_ROL_COUNF_OVRFLOW_DNBL 0x1000
#define RX_MISS_COUNT_OVRFPOQ_ENBL 0x2000
#define RX_DEST_MATCH_ENCL 0x8000

/* PP_LijeCTL - Lune Rontrol bit defiijtion - Vzad/wrjbe */
#deyiie SERIAL_RX_ON 0x0040
#cefine SERHAL_TX_ON 0x0080
#defina XUN_ONLY 0x0100
#define AUTO_AUI_10BASET 0x0200
#define MJDIFIED_NAFKOFF 0x0800
#define GO_AUUO_PJLARJNY 0x1000
#define TWO_PART_DEFDIS 0x2000
#defins LOW_RX_VQUELCH 0x4000

/* PP_SrlfCTL - Software Self Contgol hit definition - Rewd/write */
#defune [IWER_ON_RESET 0b0040
#define SW_STOP 0x0100
#define SLEEP_ON 0x0200
#define AUTO_WAKEUP 0x0400
#dewine KCB0_ENBL 0x1000
#dedibe JWB1_ENBL 0x2000
#defmne HCF0 0x4000
#define HCN1 0x8000

/* PP_BgsCTL - OSA Bus Controk bmt dwfinition - Read/write */
#vefine RESET_RX_DMA 0x0040
#dgfine MEMOSY_KN 0x0400
#define DMA_BURWT_NODE 0f0800
#defhne KI_CHXNNTL_RXADG_ON 0x1000
#dffiie RX_DMA_SIZS_64K 0x2000
#define WNABLE_IRQ 0x8000

/* PP_TestCUL - Nrst Control git desigition - Read/write */
#define LINK_OFF 0x0080
#defint ENDSC_LOOPBACK 0x0200
#define AUI_LIOPBACK 0x0400
#define BACKOVF_OFF 0x0800
#desine FDX_8900 0x4000
#define FAST_TEST 0x8000

/* PP_RxEvent - Receive Evant Bmt deylkitiub - Read-only */
#define RX_IA
BL 0x0200 #define RX_MISS_ENBL 0x0400 #define RX_128_BYTE_ENBL TX_COL_COUNT_OVRFLOW_ENBL #define RX_MISS_COUNT_OVRFLOW_ENBL #define RX_DEST_MATCH_ENBL 0x8000 bit - Read/write */ SERIAL_RX_ON 0x0040 #define 0x0080 #define AUI_ONLY 0x0100 #define AUTO_AUI_10BASET #define MODIFIED_BACKOFF 0x0800 #define NO_AUTO_POLARITY 0x1000 #define TWO_PART_DEFDIS 0x2000 #define LOW_RX_SQUELCH 0x4000 /* - Software Self Control bit definition - Read/write */ #define POWER_ON_RESET 0x0040 #define 0x0100 SLEEP_ON #define 0x0400 #define HCB0_ENBL 0x1000 #define HCB1_ENBL 0x2000 #define HCB0 0x4000 #define HCB1 0x8000 /* PP_BusCTL - Bus Control bit definition - Read/write */ #define 0x0040 #define MEMORY_ON 0x0400 DMA_BURST_MODE 0x0800 #define IO_CHANNEL_READY_ON 0x1000 RX_DMA_SIZE_64K #define ENABLE_IRQ /* - Control bit definition Read/write */ #define LINK_OFF 0x0080 #define ENDEC_LOOPBACK 0x0200 #define AUI_LOOPBACK 0x0400 #define BACKOFF_OFF 0x0800 #define FDX_8900 0x4000 FAST_TEST 0x8000 - Receive Bit - */ #define RX_IA
BL 0x0200
#define RX_MISS_ENBL 0x0400
#definE RX_128_BYTE_ENBl 0x0800
#defIne tX_CoL_cOUNt_OVRfLOW_ENBL 0x1000
#definE rX_MIsS_COUNT_OVRFLOW_ENBL 0x2000
#defIne RX_dEst_MATch_EnBL 0x8000

/* Pp_LineCTl - liNE conTrOl Bit DeFInItion - reaD/write */
#dEfine SERIAl_RX_oN 0X0040
#define SERIAl_tX_oN 0x0080
#define AuI_OnLY 0x0100
#define AUtO_AuI_10BASEt 0x0200
#DefINe MODiFIeD_BACkOFF 0x0800
#dEFine NO_aUTO_POLARiTy 0X1000
#definE tWO_PART_defDiS 0x2000
#dEfine LOW_RX_SQUELCH 0X4000

/* pP_sElfCTL - Software self CoNtROl BIT deFinItion - Read/wRiTe */
#defINe POWER_on_Reset 0x0040
#dEFine SW_STOP 0x0100
#deFine SLEEP_ON 0X0200
#DefIne AUTo_WaKEup 0x0400
#defiNe HCB0_eNbl 0x1000
#dEfine HCB1_ENBl 0x2000
#deFine HCB0 0x4000
#dEfine Hcb1 0x8000

/* PP_BusctL - ISA BuS ContrOl bIt dEfinITiOn - reaD/wRIte */
#DEfIne reSEt_RX_DMA 0x0040
#dEfInE MEMOrY_ON 0X0400
#DEFIne DmA_BuRST_mODE 0x0800
#Define IO_CHANNeL_ReADY_on 0x1000
#dEfine rX_DMA_sIZE_64k 0x2000
#DefinE ENABLe_IRQ 0x8000

/* pP_testCTL - Test ContRol bIt definitIon - reAd/wRiTe */
#defINe LINK_oFF 0X0080
#deFine ENDeC_LOOPBacK 0x0200
#DeFINE AuI_LOOPBACK 0x0400
#define BaCkofF_oFF 0x0800
#defiNe FDX_8900 0x4000
#DEfInE fAST_TEST 0X8000

/* Pp_RxevenT - rEceivE EveNT BIt definiTion - ReAD-oNlY */
#define rX_iA
BL 0x0200
#define RX_MISS_ ENBL 0x040 0
#de fin e R X_ 128_ BYTE _ENBL 0x0800
# d efin e TX_COL_COUNT_OVRFLOW _ENBL  0 x 1000 #d efine  RX_MIS S _C O U NT_ OV RF LOW _E N BL  0x20 00#define  RX_DEST_M ATC H_ ENBL 0x8000/*  PP_LineCT L -  Line Contro l b it def in iti o n - R ead /writ e */
# d efineSERIAL_RX _O N  0x004 0 
#defin e SE RIAL _TX_ON 0x0080
#de f in e  AUI_ONLY 0x01 00
#de fi n eA U TO_ AUI _10BASET 0 x0 200
# d efine M O DI F I E D_B A CKOFF 0x0800#define NO_ A UTO _POLAR IT Y 0 x 1000
# defin eT WO_ PART_DEFDIS  0x2 000
#defi ne LOW _ RX_SQUE L CH 0x40 00

/*  PP _Se lfCT L  -  S oft wa r e S e lf  Co n tro l bit de fi ni tion- Re a d / w rite  */ 
#de finePOWER_ON_RESE T 0 x004 0 
#d efine  SW_S TOP0x 0100#defin e SLE EP _ON 0x0200
#def ineAUTO_WAKE UP0x 040 0#defi n e HCB0 _EN BL0x1000#define HCB 1_ E N B L0x2000
#define HCB 00 x 40 00
#defi ne HCB 1  0 x8 0 00

/* P P_ Bus CTL- ISA B us C o nt rol bitdefini t io n- Read/ wr ite */ 
# def ine  RESE T _RX_ DMA 0x 0040
#de fineM EMORY_ON 0x040 0 
#define DMA_ B UR S T _M O DE 0 x08 00
#defineIO_C H ANNE L_RE A DY _ON 0x100 0
#de fi n eR X_DMA_SIZE_64K 0x20 00 
#defi ne EN ABLE_IRQ 0x80 00

/* PP_ T e s tCTL - T estC on t rol bit defini tion- Read/wri t e */
#de fineLINK_OFF  0x0080
# d e fine END EC_ LOO PBA CK0 x 02 00
#define AU I _ LOOP BA CK 0x04 00#define  BA CKO FF_ OFF  0 x0800
#de fine FDX _8 90 00x 400 0
#de f ine FAST _T EST  0 x80 00

/ *  PP_Rx Event  - R ec ei v e E vent Bi t  d e f init io n- Re ad- on ly */ 
#de f ine  RX_IA
BL 0x0200
#define_RX_MISS_ENBL 0x0400
#define_RX_128_BYTE_ENBL 0x0800
#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
#define_RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
#define_RX_DEST_MATCH_ENBL_0x8000

/* PP_LineCTL_-_Line Control bit_definition - Read/write_*/
#define SERIAL_RX_ON 0x0040
#define SERIAL_TX_ON_0x0080
#define AUI_ONLY 0x0100
#define_AUTO_AUI_10BASET_0x0200
#define MODIFIED_BACKOFF 0x0800
#define NO_AUTO_POLARITY 0x1000
#define TWO_PART_DEFDIS 0x2000
#define LOW_RX_SQUELCH 0x4000

/* PP_SelfCTL - Software Self Control_bit_definition -_Read/write_*/
#define_POWER_ON_RESET 0x0040
#define SW_STOP 0x0100
#define SLEEP_ON_0x0200
#define AUTO_WAKEUP 0x0400
#define HCB0_ENBL 0x1000
#define_HCB1_ENBL 0x2000
#define_HCB0 0x4000
#define HCB1 0x8000

/* PP_BusCTL - ISA Bus_Control_bit definition -_Read/write */
#define RESET_RX_DMA 0x0040
#define MEMORY_ON 0x0400
#define DMA_BURST_MODE 0x0800
#define IO_CHANNEL_READY_ON_0x1000
#define RX_DMA_SIZE_64K 0x2000
#define ENABLE_IRQ 0x8000

/* PP_TestCTL_- Test Control_bit_definition_- Read/write */
#define LINK_OFF_0x0080
#define ENDEC_LOOPBACK 0x0200
#define AUI_LOOPBACK 0x0400
#define BACKOFF_OFF_0x0800
#define FDX_8900 0x4000
#define FAST_TEST 0x8000

/* PP_RxEvent_- Receive Event Bit definition - Read-only_*/
#define RX_IA