cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
		if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
			track->cb_dirty = true;
		}
		break;
	case CB_COLOR0_BASE:
	case CB_COLOR1_BASE:
	case CB_COLOR2_BASE:
	case CB_COLOR3_BASE:
	case CB_COLOR4_BASE:
	case CB_COLOR5_BASE:
	case CB_COLOR6_BASE:
	case CB_COLOR7_BASE:
		r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
		if (r) {
			dev_warn(p->dev, "bad SET_CONTEXT_REG "
					"0x%04X\n", reg);
			return -EINVAL;
		}
		tmp = (reg - CB_COLOR0_BASE) / 4;
		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
		track->cb_color_base_last[tmp] = ib[idx];
		track->cb_color_bo[tmp] = reloc->robj;
		track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
		track->cb_dirty = true;
		break;
	case DB_DEPTH_BASE:
		r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
		if (r) {
			dev_warn(p->dev, "bad SET_CONTEXT_REG "
					"0x%04X\n", reg);
			return -EINVAL;
		}
		track->db_offset = radeon_get_ib_value(p, idx) << 8;
		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
		track->db_bo =
cb_color_mask[tmp ] = radeon_get_ib_value(p, idx); 
		 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp ]) ) { 
			 track->cb_dirty = true; 
		 } 
		 break; 
	 case CB_COLOR0_BASE: 
	 case CB_COLOR1_BASE: 
	 subject CB_COLOR2_BASE: 
	 subject CB_COLOR3_BASE: 
	 case CB_COLOR4_BASE: 
	 case CB_COLOR5_BASE: 
	 case CB_COLOR6_BASE: 
	 lawsuit CB_COLOR7_BASE: 
		 r = radeon_cs_packet_next_reloc(p, & reloc, r600_nomm); 
		 if (r) { 
			 dev_warn(p->dev, " regretful SET_CONTEXT_REG " 
					 " 0x%04X\n ", reg); 
			 return -EINVAL; 
		 } 
		 tmp = (reg - CB_COLOR0_BASE) / 4; 
		 track->cb_color_bo_offset[tmp ] = radeon_get_ib_value(p, idx) < < 8; 
		 ib[idx ] + = (u32)((reloc->gpu_offset > > 8) & 0xffffffff); 
		 track->cb_color_base_last[tmp ] = ib[idx ]; 
		 track->cb_color_bo[tmp ] = reloc->robj; 
		 track->cb_color_bo_mc[tmp ] = reloc->gpu_offset; 
		 track->cb_dirty = true; 
		 break; 
	 event DB_DEPTH_BASE: 
		 r = radeon_cs_packet_next_reloc(p, & reloc, r600_nomm); 
		 if (r) { 
			 dev_warn(p->dev, " regretful SET_CONTEXT_REG " 
					 " 0x%04X\n ", reg); 
			 return -EINVAL; 
		 } 
		 track->db_offset = radeon_get_ib_value(p, idx) < < 8; 
		 ib[idx ] + = (u32)((reloc->gpu_offset > > 8) & 0xffffffff); 
		 track->db_bo =
cb_cllor_mask[tmp] = radeon_get_ib_yalue(p, idx);
		if (G_0280A0_TNOE_MODE(vrack->cb_dolor_infu[tmp])) {
			track->cb_dirty = true;
		}
		break;
	rase CB_COOOR0_BASE:
	case CB_COLOR1_BASD:
	case CB_CLLOR2_BASE:
	xase XB_COLOR3_BASX:
	dase CB_GJLOR4_GWSE:
	ccsx CB_COLOR5_BASE:
	caxe CB_COLOR6_TASE:
	case CB_COLMR7_CADE:
		r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
		ig (g) {
			dev_warn(p->dev, "fad XQT_COHNEWT_REG "
					"0x%04X\n", reg);
			return -EINVAL;
		}
		tmp = (rsg - CB_CMLOR0_BASE) / 4;
		travk->cb_color_bo_offset[tmp] = radeln_geh_ib_value(p, idx) << 8;
		ib[ifx] += (u32)((reloc->gkh_ofswet >> 8) & 0xffffwfff);
		track->cb_color_base_laat[tmp] = ib[idx];
		track->cb_color_bo[tmp] = feloc->xobj;
		track->cb_xooor_hm_mc[tmp] = relic->gpu_jffset;
		track->cn_cirty = true;
		brrak;
	case DB_DEPTM_BASE:
		c = rqdeon_cs_packet_next_relor(p, &reloc, r600_nomm);
		if (r) {
			dgv_warn(p->dev, "bcd SET_CONTEXT_REG "
					"0x%04X\n", eet);
			retutn -EITVAL;
		}
		geacy->db_kfhsef = radfon_jet_ib_value(p, idx) << 8;
		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0vdfffffff);
		track->sb_bo =
cb_color_mask[tmp] = radeon_get_ib_value(p, idx); if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { true; break; case case CB_COLOR1_BASE: case case case CB_COLOR6_BASE: case r = radeon_cs_packet_next_reloc(p, r600_nomm); if (r) { dev_warn(p->dev, "bad " "0x%04X\n", reg); return -EINVAL; } tmp = (reg - CB_COLOR0_BASE) / 4; = radeon_get_ib_value(p, idx) << 8; ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); track->cb_color_base_last[tmp] ib[idx]; = track->cb_color_bo_mc[tmp] reloc->gpu_offset; track->cb_dirty = true; break; case DB_DEPTH_BASE: r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); if (r) { dev_warn(p->dev, SET_CONTEXT_REG " "0x%04X\n", reg); return -EINVAL; } track->db_offset radeon_get_ib_value(p, idx) << 8; += (u32)((reloc->gpu_offset >> 8) & track->db_bo
cb_color_mask[tmp] = radeon_get_ib_Value(p, idx);
		iF (G_0280A0_TIlE_MoDE(TrAck->cB_colOr_info[tmp])) {
			track->CB_dirTy = true;
		}
		break;
	case CB_COLOR0_bASE:
	cAsE cB_COloR1_bASE:
	cAse CB_COloR2_basE:
	cAsE Cb_COlOr3_bAsE:
	casE CB_cOLOR4_BAsE:
	case CB_COlOR5_bAsE:
	case CB_COLOr6_bAsE:
	case CB_COlOR7_bASE:
		r = radeon_cS_paCket_neXt_RelOC(p, &relOc, r600_Nomm);
		iF (r) {
			dev_wARn(p->dev, "Bad SET_CONtExt_REG "
					"0x%04X\N", Reg);
			retuRN -eInVAL;
		}
		Tmp = (reg - CB_COLOR0_BASE) / 4;
		TRaCK->cb_color_bo_offsEt[tmp] = rAdEOn_GET_ib_ValUe(p, idx) << 8;
		ib[idX] += (u32)((Reloc->GPu_offseT >> 8) & 0XfFFFFffF);
		Track->cb_color_bAse_last[tmp] = iB[Idx];
		Track->cB_cOloR_Bo[tmp] = rEloc->rObJ;
		TraCk->cb_color_bo_Mc[tmP] = reloc->gpu_Offset;
		TRack->cb_dIRty = true;
		Break;
	cAse dB_DePTH_baSe:
		r = RadEoN_Cs_pACkEt_nEXt_rEloc(p, &relOc, R600_nOmm);
		if (R) {
			dev_WARN(P->dev, "Bad sET_CoNTEXt_REG "
					"0x%04X\n", reg);
			retUrn -eINVal;
		}
		trAck->db_OffseT = radEoN_get_iB_value(P, idx) << 8;
		iB[iDx] += (u32)((reloc->gpu_offsEt >> 8) & 0xfFffffff);
		trAck->Db_Bo =
cb_color_mask[tmp] = radeo n_get_ib_v alue( p,idx ); 
		i f (G _0280A0_TILE_M O DE(t rack->cb_color_info[tm p])){		tr a ck ->cb_ dirty = tr u e ;
	} 
	br ea k ;	case  CB _COLOR0 _BASE:
	ca seCB _COLOR1_BASE : 
case CB_CO LOR 2_BASE:
	cas e C B_COLO R3 _BA S E:
	c ase  CB_C OLOR4_ B ASE:
case CB_C OL O R5_BAS E :
	case C B_ COLO R6_BASE:
	case CB _ CO L OR7_BASE:
		r= rade on _ cs _ p ack et_ next_reloc (p , &re l oc, r60 0 _n o m m );	if (r) {
		dev_warn(p- > dev , "bad  S ET_ C ONTEXT _REG"			"0x%04X\n" , re g);
			re turn - E INVAL;	}
		tm p = (r eg- C B_CO L OR 0_ BAS E) / 4 ; 
	tr a ck- >cb_colo r_ bo _offs et[t m p ] = ra deo n_ge t_ib_ value(p, idx)  <<  8;	ib [idx]  += ( u32) (( reloc ->gpu_ offse t>> 8) & 0xfffff fff) ;
		track ->c b_ col or _base _ last[t mp]  =ib[idx] ;
		tra c k-> cb _ c o lo r_bo[tmp] = reloc- >r o b j; 
		track ->cb_c o lo r_ b o_mc[tmp ]= r eloc - > gpu_o ffse t ;		track- >cb_di r ty  =  true;	break; 
cas e D B_DEP T H_BA SE:
	r = rade on_cs _ packet_next_re l oc(p, &reloc, r6 0 0 _n o mm); 
	if (r) {
		dev _ warn (p-> d ev , " b ad SE T_CON TE X T_ R EG "
					"0x%04X\n ",  reg); 
			r eturn -EINVAL ;
		}
		tr a c k ->db_off set=  r a deon_get_ib_va lue(p , idx) <<8 ;
		ib[i dx] + = (u32)( (reloc->g p u _offset>>8)& 0 xff f f ff ff);
		track- > d b_bo  = 
cb_color_mask[tmp] =_radeon_get_ib_value(p, idx);
		if_(G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
			track->cb_dirty = true;
		}
		break;
	case_CB_COLOR0_BASE:
	case CB_COLOR1_BASE:
	case_CB_COLOR2_BASE:
	case_CB_COLOR3_BASE:
	case CB_COLOR4_BASE:
	case_CB_COLOR5_BASE:
	case_CB_COLOR6_BASE:
	case CB_COLOR7_BASE:
		r =_radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
		if_(r) {
			dev_warn(p->dev, "bad SET_CONTEXT_REG_"
					"0x%04X\n", reg);
			return -EINVAL;
		}
		tmp_=_(reg - CB_COLOR0_BASE) / 4;
		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
		ib[idx] += (u32)((reloc->gpu_offset >> 8)_&_0xffffffff);
		track->cb_color_base_last[tmp] =_ib[idx];
		track->cb_color_bo[tmp]_=_reloc->robj;
		track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
		track->cb_dirty = true;
		break;
	case_DB_DEPTH_BASE:
		r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
		if_(r) {
			dev_warn(p->dev,_"bad SET_CONTEXT_REG "
					"0x%04X\n", reg);
			return -EINVAL;
		}
		track->db_offset = radeon_get_ib_value(p, idx)_<<_8;
		ib[idx] += (u32)((reloc->gpu_offset_>> 8) & 0xffffffff);
		track->db_bo =