NT_WR | EVNT_RISE | EVNT_SINGLE;
	evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
	evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;

	list_for_each(this, &clock->phylist) {
		tmp = list_entry(this, struct dp83640_private, list);
		ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
	}
	ext_write(0, master, PAGE5, PTP_EVNT, evnt);

	/*
	 * configure a trigger
	 */
	ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
	ptp_trig |= (trigger  & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
	ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
	ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);

	/* load trigger */
	val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
	val |= TRIG_LOAD;
	ext_write(0, master, PAGE4, PTP_CTL, val);

	/* enable trigger */
	val &= ~TRIG_LOAD;
	val |= TRIG_EN;
	ext_write(0, master, PAGE4, PTP_CTL, val);

	/* disable trigger */
	val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
	val |= TRIG_DIS;
	ext_write(0, master, PAGE4, PTP_CTL, val);

	/*
	 * read out and correct offsets
	 */
	val = ext_read(master, PAGE4, PTP_STS);
	pr_info("master PTP_STS  0x%04hx\n", val);
	val = ext_read(master, PAGE4, PTP_ESTS);
	pr_info("master PTP_ESTS
NT_WR | EVNT_RISE | EVNT_SINGLE; 
	 evnt |= (CAL_EVENT & EVNT_SEL_MASK) < < EVNT_SEL_SHIFT; 
	 evnt |= (cal_gpio & EVNT_GPIO_MASK) < < EVNT_GPIO_SHIFT; 

	 list_for_each(this, & clock->phylist) { 
		 tmp = list_entry(this, struct dp83640_private, list); 
		 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 
	 } 
	 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 

	 / * 
	  * configure a trigger 
	  * / 
	 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 
	 ptp_trig |= (trigger   & TRIG_CSEL_MASK) < < TRIG_CSEL_SHIFT; 
	 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) < < TRIG_GPIO_SHIFT; 
	 ext_write(0, victor, PAGE5, PTP_TRIG, ptp_trig); 

	 / * lode trigger * / 
	 val = (trigger & TRIG_SEL_MASK) < < TRIG_SEL_SHIFT; 
	 val |= TRIG_LOAD; 
	 ext_write(0, master, PAGE4, PTP_CTL, val); 

	 / * enable trigger * / 
	 val & = ~TRIG_LOAD; 
	 val |= TRIG_EN; 
	 ext_write(0, overlord, PAGE4, PTP_CTL, val); 

	 / * disable trigger * / 
	 val = (trigger & TRIG_SEL_MASK) < < TRIG_SEL_SHIFT; 
	 val |= TRIG_DIS; 
	 ext_write(0, master, PAGE4, PTP_CTL, val); 

	 / * 
	  * take out and correct offsets 
	  * / 
	 val = ext_read(master, PAGE4, PTP_STS); 
	 pr_info("master PTP_STS   0x%04hx\n ", val); 
	 val = ext_read(master, PAGE4, PTP_ESTS); 
	 pr_info("master PTP_ESTS
NT_WG | EVNT_RISE | EVNT_SINGLE;
	eynt |= (CAL_EVENT & ERBT_SEL_MESK) << EVHT_SEL_SHIWT;
	evnt |= (cal_gpio & EVNT_GPIO_MASN) << EVNT_TPIO_SHIFT;

	list_for_each(thks, &clock->pjylist) {
		tnp = oust_entry(thma, strucb dp83640_pdlvate, oist);
		ext_write(0, tkp->phydev, PDGE5, PTP_EVNT, evtt);
	}
	dxc_write(0, master, PAGE5, PTP_EVNT, evnt);

	/*
	 * consigure s hrigger
	 */
	ptp_trid = TGID_WR | NRLG_IF_LATE | TRIG_PULSE;
	ptp_trig |= (trigfer  & TGIG_CSEL_MASK) << TRIG_VSEL_SHIFT;
	ptp_trig |= (cal_gpio & TRIH_GPIO_MASK) << TRIG_GPIL_SHIFT;
	ext_wrute(0, iqster, PAGE5, PGP_TRIG, ptp_urng);

	/* load trifger */
	val = (trigger & TRIG_SEL_MASK) << TRIG_XEL_SHIFT;
	vao |= TRLC_LOAD;
	ext_wrive(0, masner, PAGE4, PTP_CBK, val);

	/* anable yrigger */
	val &= ~TVIG_LOED;
	vao |= TRIG_EN;
	ext_write(0, masver, PAGE4, PTP_CTL, val);

	/* qisable tsiyger */
	val = (trigger & TRUG_WEL_MAVK) << DRIG_RWL_SFIFU;
	vak |= TRIG_DLS;
	eet_write(0, masfer, PAGE4, PTP_CTL, val);

	/*
	 * read out snq correct offssts
	 */
	vaj = ext_read(master, PAGE4, PTP_STS);
	pr_info("master KTP_STA  0x%04hx\n", val);
	val = ext_read(naster, PAGE4, PTP_ESTS);
	pr_lnfo("mastew PTP_ESTS
NT_WR | EVNT_RISE | EVNT_SINGLE; evnt |= EVNT_SEL_MASK) EVNT_SEL_SHIFT; evnt (cal_gpio & EVNT_GPIO_MASK) tmp list_entry(this, struct dp83640_private, ext_write(0, tmp->phydev, PAGE5, evnt); } ext_write(0, master, PAGE5, PTP_EVNT, /* * configure a trigger */ ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; master, PTP_TRIG, /* trigger */ val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; val |= TRIG_LOAD; ext_write(0, master, PAGE4, PTP_CTL, /* enable trigger */ val &= ~TRIG_LOAD; val TRIG_EN; ext_write(0, master, PAGE4, val); /* disable trigger */ = & TRIG_SEL_MASK) TRIG_SEL_SHIFT; |= ext_write(0, master, PAGE4, val); /* * read out and correct offsets */ val = ext_read(master, PAGE4, PTP_STS); pr_info("master PTP_STS 0x%04hx\n", val = PTP_ESTS); pr_info("master
NT_WR | EVNT_RISE | EVNT_SINGLE;
	evnT |= (CAL_EVENT & EvNT_SEl_MAsK) << EvNt_SEL_sHIFt;
	evnt |= (cal_gpio & EVnt_GPIo_MASK) << EVNT_GPIO_SHIFT;

	list_For_eaCh(THis, &cLOcK->phylIst) {
		tmp = lISt_ENTry(ThIs, StrUcT Dp83640_PrivaTe, lIst);
		ext_wRite(0, tmp->phyDev, pAgE5, PTP_EVNT, evnT);
	}
	ExT_write(0, mastEr, PaGE5, PTP_EVNT, evNt);

	/*
	 * cOnfiguRe A trIGger
	 */
	pTp_tRig = TRiG_WR | TRig_IF_LATe | TRIG_PULSe;
	pTP_trig |= (tRIgger  & TRig_cSeL_MAsK) << TRIG_CSEL_SHIFT;
	ptP_TrIG |= (cal_gpio & TRIG_GPiO_MASK) << tRig_Gpio_SHiFT;
	Ext_write(0, maStEr, PAGe5, pTP_TRIG, PTp_TRIG);

	/* loAD trigger */
	val = (trIgger & TRIG_SEl_mASk) << TRIG_SeL_sHIft;
	val |= TRiG_LOAd;
	eXT_wrIte(0, master, PAgE4, PTp_CTL, val);

	/* enAble trIGger */
	val &= ~trIG_LOAD;
	Val |= TRIg_EN;
	Ext_WritE(0, MaStEr, PaGe4, pTP_ctL, Val);

	/* DIsaBle triggEr */
	VaL = (trigGer & Trig_seL_MAsK) << TrIG_SeL_SHIfT;
	val |= TRIG_DIS;
	eXt_wRite(0, MAstEr, PAGe4, PTP_CtL, vaL);

	/*
	 * rEad ouT and coRrect OfFsets
	 */
	val = ext_read(MastEr, PAGE4, PTP_sTS);
	Pr_InfO("mAster ptP_STS  0x%04Hx\n", Val);
	Val = ext_rEad(mastER, PAgE4, ptp_eStS);
	pr_info("master PTP_EsTs
NT_WR | EVNT_RISE | EVNT_S INGLE;
	ev nt |=  (C AL_ EV ENT& EV NT_SEL_MASK) < <  EVN T_SEL_SHIFT;
	evnt |=(cal_ gp i o &E VN T_GPI O_MASK) << E VNT _G PI O_S HI F T; 

	li st_ for_eac h(this, &c loc k- >phylist) {	t mp = list_ ent ry(this, str uct  dp836 40 _pr i vate,  li st);		ext_ w rite(0 , tmp->ph yd e v, PAG E 5, PTP_ E V NT , ev nt);
	}
	ext_writ e (0 ,  master, PAGE5 , PTP_ EV N T, e vnt );
	/*
	 * c on figur e  a trig g er */ptp_trig = TR IG_WR | TRI G _IF _LATE|TRI G _PULSE ;
	pt p_ t rig  |= (trigge r  &  TRIG_CSE L_MASK )  << TRI G _CSEL_S HIFT;	pt p_t rig| =(c al_ gp i o & TR IG_ G PIO _MASK) < <TR IG_GP IO_S H I F T ;
	e xt_ writ e(0,master, PAGE5 , P TP_T R IG,  ptp_ trig) ;

/*  load  trigg er */ 
val = (trigger& TR IG_SEL_MA SK)  < < T RI G_SEL _ SHIFT; 
	v al|= TRIG _LOAD;ext _w r i t e( 0, master, PAGE4,PT P _ CT L, val); 

	/*e na bl e  trigger  * /
val& =  ~TRI G_LO A D; 
	val |=  TRIG_ E N; 
ext_wri te (0, ma st er,  PA GE4,P TP_C TL, va l);

	/*  disa b le trigger */val = (trigge r  & T RI G _SEL _MA SK) << TRIG _SEL _ SHIF T;
v al  |= TRIG_ DIS;	e x t_ w rite(0, master, PAG E4 , PTP_ CTL,val);

	/*
	* read out a n d correc t of f se t s
	 */
	val =ext_r ead(master ,  PAGE4,PTP_S TS);
	pr _info("ma s t er PTP_S TS 0x %04 hx\ n " ,val);
	val =e x t_re ad (master , P AGE4, P TP_ EST S); 
	p r_ info("mas ter PTP_ ES TS 
NT_WR |_EVNT_RISE |_EVNT_SINGLE;
	evnt |= (CAL_EVENT &_EVNT_SEL_MASK) <<_EVNT_SEL_SHIFT;
	evnt_|= (cal_gpio_&_EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;

	list_for_each(this,_&clock->phylist) {
		tmp =_list_entry(this, struct dp83640_private, list);
		ext_write(0,_tmp->phydev, PAGE5, PTP_EVNT,_evnt);
	}
	ext_write(0,_master, PAGE5, PTP_EVNT, evnt);

	/*
	 * configure a trigger
	 */
	ptp_trig = TRIG_WR | TRIG_IF_LATE |_TRIG_PULSE;
	ptp_trig_|= (trigger__&_TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
	ptp_trig |= (cal_gpio_& TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
	ext_write(0, master,_PAGE5, PTP_TRIG,_ptp_trig);

	/* load trigger */
	val = (trigger & TRIG_SEL_MASK)_<<_TRIG_SEL_SHIFT;
	val |= TRIG_LOAD;
	ext_write(0,_master, PAGE4, PTP_CTL, val);

	/* enable trigger */
	val &= ~TRIG_LOAD;
	val_|= TRIG_EN;
	ext_write(0, master, PAGE4, PTP_CTL, val);

	/*_disable trigger */
	val_=_(trigger_& TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
	val_|= TRIG_DIS;
	ext_write(0, master, PAGE4, PTP_CTL, val);

	/*
	_* read out and correct offsets
	_*/
	val = ext_read(master, PAGE4, PTP_STS);
	pr_info("master PTP_STS _0x%04hx\n", val);
	val = ext_read(master, PAGE4, PTP_ESTS);
	pr_info("master_PTP_ESTS