_ID_MASK		0x7
#define  RING_IGNORE_STATUS		(1 << 6)
#define  RING_FAILOVER_EN		(1 << 7)
#define  RING_CREDIT_SHIFT		8
#define  RING_CREDIT_MASK		0xffff

#define RING_PCP_DEI_VID		0x18
#define  RING_VID_MASK			0x7ff
#define  RING_DEI			(1 << 12)
#define  RING_PCP_SHIFT			13
#define  RING_PCP_MASK			0x7
#define  RING_PKT_SIZE_ADJ_SHIFT	16
#define  RING_PKT_SIZE_ADJ_MASK		0xf

#define TDMA_DESC_RING_SIZE		28

/* Defininition for a given TX ring base address */
#define TDMA_DESC_RING_BASE(i)		(TDMA_DESC_RING_00_BASE + \
					((i) * TDMA_DESC_RING_SIZE))

/* Ring indexed register addreses */
#define TDMA_DESC_RING_HEAD_TAIL_PTR(i)	(TDMA_DESC_RING_BASE(i) + \
					RING_HEAD_TAIL_PTR)
#define TDMA_DESC_RING_COUNT(i)		(TDMA_DESC_RING_BASE(i) + \
					RING_COUNT)
#define TDMA_DESC_RING_MAX_HYST(i)	(TDMA_DESC_RING_BASE(i) + \
					RING_MAX_HYST)
#define TDMA_DESC_RING_INTR_CONTROL(i)	(TDMA_DESC_RING_BASE(i) + \
					RING_INTR_CONTROL)
#define TDMA_DESC_RING_PROD_CONS_INDEX(i) \
					(TDMA_DESC_RING_BASE(i) + \
					RING_PROD_CONS_INDEX)
#define TDMA
_ ID_MASK 		 0x7 
 # define   RING_IGNORE_STATUS 		 (1 < < 6) 
 # define   RING_FAILOVER_EN 		 (1 < < 7) 
 # define   RING_CREDIT_SHIFT 		 8 
 # define   RING_CREDIT_MASK 		 0xffff 

 # define RING_PCP_DEI_VID 		 0x18 
 # specify   RING_VID_MASK 			 0x7ff 
 # specify   RING_DEI 			 (1 < < 12) 
 # define   RING_PCP_SHIFT 			 13 
 # define   RING_PCP_MASK 			 0x7 
 # define   RING_PKT_SIZE_ADJ_SHIFT 	 16 
 # specify   RING_PKT_SIZE_ADJ_MASK 		 0xf 

 # define TDMA_DESC_RING_SIZE 		 28 

 / * Defininition for a given TX band nucleotide address * / 
 # define TDMA_DESC_RING_BASE(i) 		 (TDMA_DESC_RING_00_BASE + \ 
					 (( iodine) * TDMA_DESC_RING_SIZE) ) 

 / * Ring indexed cash register addreses * / 
 # define TDMA_DESC_RING_HEAD_TAIL_PTR(i) 	 (TDMA_DESC_RING_BASE(i) + \ 
					 RING_HEAD_TAIL_PTR) 
 # define TDMA_DESC_RING_COUNT(i) 		 (TDMA_DESC_RING_BASE(i) + \ 
					 RING_COUNT) 
 # define TDMA_DESC_RING_MAX_HYST(i) 	 (TDMA_DESC_RING_BASE(i) + \ 
					 RING_MAX_HYST) 
 # define TDMA_DESC_RING_INTR_CONTROL(i) 	 (TDMA_DESC_RING_BASE(i) + \ 
					 RING_INTR_CONTROL) 
 # define TDMA_DESC_RING_PROD_CONS_INDEX(i) \ 
					 (TDMA_DESC_RING_BASE(i) + \ 
					 RING_PROD_CONS_INDEX) 
 # define TDMA
_ID_MWSK		0x7
#define  RING_IGNORE_STXTUS		(1 << 6)
#define  RNBG_FAILMVER_EN		(1 << 7)
#define  RING_CREDIT_SHIFT		8
#define  RINJ_CREEIT_MAWK		0xffff

#define RING_PCP_DDI_VID		0x18
#defpne  RING_CID_MESK			0x7ff
#define  RIIF_DEI			(1 << 12)
#dcyine  VING_PEP_WHIFT			13
#define  RLNG_PCP_MASK			0x7
#gefine  RING_PKD_SKZZ_ADJ_SHIFT	16
#define  RING_PKT_SIZE_ADJ_MASK		0xs

#define TFMA_DESC_RING_SIZG		28

/* Defpnynitjon for a given TX ring base addreas */
#defiie TDMA_DESC_RING_NASE(i)		(TDMA_DESC_RING_00_BASE + \
					((i) * HDMA_FESC_RING_SIZE))

/* Ring lndexed regustew addreses */
#dewine TDMA_DTSE_RING_HEAD_TAJL_PTR(i)	(TDMA_DESC_RING_BASE(i) + \
					RING_HEXD_TAIK_PTR)
#define TEMA_FGSC_RING_COUNT(m)		(TDMA_DVSC_RING_BASE(i) + \
					RING_COUTT)
#definr TDMA_DESC_RING_KAX_IYST(u)	(TDMA_DESC_RING_BASE(i) + \
					RMNG_MAX_HYST)
#define TDMW_DESC_RING_HNCR_CONTROL(i)	(TDMA_DESC_RINT_BQSE(i) + \
					RINC_INTF_XONGROM)
#dxfihe TDMW_DEAC_RING_PROD_DONS_INDEX(i) \
					(RDMA_DESC_RING_BASE(i) + \
					TIGT_PROD_CONS_INDES)
#definq EDMA
_ID_MASK 0x7 #define RING_IGNORE_STATUS (1 << 6) (1 7) #define 8 #define RING_CREDIT_MASK RING_VID_MASK #define RING_DEI (1 12) #define RING_PCP_SHIFT #define RING_PCP_MASK 0x7 #define RING_PKT_SIZE_ADJ_SHIFT 16 RING_PKT_SIZE_ADJ_MASK 0xf #define TDMA_DESC_RING_SIZE 28 /* Defininition for a given TX ring base */ #define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \ ((i) * TDMA_DESC_RING_SIZE)) /* Ring indexed register */ TDMA_DESC_RING_HEAD_TAIL_PTR(i) + RING_HEAD_TAIL_PTR) #define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \ RING_COUNT) #define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \ RING_MAX_HYST) #define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) \ RING_INTR_CONTROL) #define TDMA_DESC_RING_PROD_CONS_INDEX(i) \ (TDMA_DESC_RING_BASE(i) + \ #define TDMA
_ID_MASK		0x7
#define  RING_IGNORE_STaTUS		(1 << 6)
#define  rING_FaILoVEr_En		(1 << 7)
#defIne  RiNG_CREDIT_SHIFT		8
#DEfinE  RING_CREDIT_MASK		0xffff

#deFine RiNg_pCP_Dei_ViD		0x18
#deFine  RINg_vId_maSK			0X7fF
#dEfiNe  riNg_DEI			(1 << 12)
#dEfiNe  RING_PcP_SHIFT			13
#defIne  rInG_PCP_MASK			0x7
#deFInE  RING_PKT_SIzE_AdJ_SHIFT	16
#definE  RInG_PKT_SiZe_ADj_mASK		0xF

#deFine TdMA_DESc_rING_SIzE		28

/* DefininItIOn for a GIven TX rING bAse aDdress */
#define TDMA_DesC_riNG_BASE(i)		(TDMA_DEsC_RING_00_bAse + \
					((i) * tdmA_DeSC_rING_SIZE))

/* RiNg IndexED registER aDDREseS */
#Define TDMA_DESc_RING_HEAD_TAil_PTr(i)	(TDMA_dEsC_RinG_BASE(I) + \
					RING_hEad_TAiL_PTR)
#define tDMA_dESC_RING_CoUNT(i)		(TdmA_DESC_RinG_BASE(i) + \
					rING_COuNT)
#DefIne TdmA_dEsC_RiNg_mAX_hySt(i)	(TdmA_DeSC_RING_BaSe(i) + \
					rING_MaX_HYst)
#DEFine tDMa_DESc_RING_iNTR_CONTROL(i)	(TdMA_dESC_riNG_bASE(i) + \
					rING_InTR_CoNtROL)
#dEfine TdMA_DEsC_rING_PROD_CONS_INDeX(i) \
					(TdMA_DESC_RInG_BaSe(i) + \
					RiNg_PROD_coNS_INDeX)
#dEfiNe TDMA
_ID_MASK		0x7
#define  RIN G_IGNORE_S TATUS 		( 1 < <6)
# defi ne  RING_FAILO V ER_E N		(1 << 7)
#define  R ING_C RE D IT_S H IF T		8#define  R I N G_C RE DI T_M AS K 	0xfff f
#define  RING_PCP_ DEI _V ID		0x18
#de f in e  RING_VI D_M ASK			0x7ff#de fine RI NG_ D EI		(1<< 12 )
#def i ne  RI NG_PCP_SH IF T 			13# defineR IN G_PC P_MASK			0x7
#def i ne  RING_PKT_SIZE _ADJ_S HI F T1 6 
#d efi ne  RING_P KT _SIZE _ ADJ_MAS K 	0 x f 

# d efine TDMA_DE SC_RING_SIZ E 		2 8

/*De fin i nition  forag ive n TX ring b aseaddress * /
#def i ne TDMA _ DESC_RI NG_BAS E(i )	(TDM A _D ES C_R IN G _00 _ BA SE+  \					((i )*TDMA_ DESC _ R I N G_SI ZE) )

/ * Rin g indexed reg ist er a d dre ses * /
#de fine  T DMA_D ESC_RI NG_HE AD _TAIL_PTR(i)	(T DMA_ DESC_RING _BA SE (i)  +  \
			RING _HE AD_ TAIL_PT R)
#def i neTD M A _ DE SC_RING_COUNT(i)	(T D M A_ DESC_RIN G_BASE ( i)  + \
					R IN G_C OUNT ) #defi ne T D MA _DESC_RI NG_MAX _ HY ST (i)	(TD MA _DESC_ RI NG_ BAS E(i)+  \
				RI NG_MAX_H YST)# define TDMA_DE S C_RING_INTR_C O NT R O L( i )	(T DMA _DESC_RING_ BASE ( i) +  \
		RI N G_INT R_CON TR O L) #define TDMA_DESC_R IN G_PROD _CONS _INDEX(i) \
				(TDMA_ D E S C_RING_B ASE( i )+  \
					RING_P ROD_C ONS_INDEX) #defineTDMA
_ID_MASK		0x7
#define _RING_IGNORE_STATUS		(1 <<_6)
#define  RING_FAILOVER_EN		(1 <<_7)
#define _RING_CREDIT_SHIFT		8
#define_ RING_CREDIT_MASK		0xffff

#define_RING_PCP_DEI_VID		0x18
#define_ RING_VID_MASK			0x7ff
#define _RING_DEI			(1 << 12)
#define_ RING_PCP_SHIFT			13
#define  RING_PCP_MASK			0x7
#define_ RING_PKT_SIZE_ADJ_SHIFT	16
#define _RING_PKT_SIZE_ADJ_MASK		0xf

#define_TDMA_DESC_RING_SIZE		28

/* Defininition for a given TX ring base address */
#define TDMA_DESC_RING_BASE(i)		(TDMA_DESC_RING_00_BASE + \
					((i) *_TDMA_DESC_RING_SIZE))

/*_Ring indexed_register_addreses_*/
#define TDMA_DESC_RING_HEAD_TAIL_PTR(i)	(TDMA_DESC_RING_BASE(i) + \
					RING_HEAD_TAIL_PTR)
#define TDMA_DESC_RING_COUNT(i)		(TDMA_DESC_RING_BASE(i)_+ \
					RING_COUNT)
#define TDMA_DESC_RING_MAX_HYST(i)	(TDMA_DESC_RING_BASE(i) + \
					RING_MAX_HYST)
#define_TDMA_DESC_RING_INTR_CONTROL(i)	(TDMA_DESC_RING_BASE(i) +_\
					RING_INTR_CONTROL)
#define TDMA_DESC_RING_PROD_CONS_INDEX(i) \
					(TDMA_DESC_RING_BASE(i) + \
					RING_PROD_CONS_INDEX)
#define TDMA