/* some bits reserved */
	/* these STS_* flags are also intr_enable bits (USBINTR) */
#define STS_IAA		(1<<5)		/* Interrupted on async advance */
#define STS_FATAL	(1<<4)		/* such as some PCI access errors */
#define STS_FLR		(1<<3)		/* frame list rolled over */
#define STS_PCD		(1<<2)		/* port change detect */
#define STS_ERR		(1<<1)		/* "error" completion (overflow,...) */
#define STS_INT		(1<<0)		/* "normal" completion (short,...) */

	/* USBINTR: offset 0x08 */
	u32		intr_enable;

	/* FRINDEX: offset 0x0C */
	u32		frame_index;	/* current microframe number */
	/* CTRLDSSEGMENT: offset 0x10 */
	u32		segment;	/* address bits 63:32 if needed */
	/* PERIODICLISTBASE: offset 0x14 */
	u32		frame_list;	/* points to periodic list */
	/* ASYNCLISTADDR: offset 0x18 */
	u32		async_next;	/* address of next async queue head */

	u32	reserved1;
	/* PORTSC: offset 0x20 */
	u32	port_status;
/* 31:23 reserved */
#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))	/* USB 1.1 device */
#define PORT_RESET	(1<<8)		/* reset port */
#define PORT_SUSPEND	(1<<7)		/* suspend port */
#define PORT_RESUME	(1<<6)		/* resume it */
#define PORT_PEC	(1<<3)		/* port enable change */
#define PORT_PE		(1<<2)		/* port enable */
#define PORT_CSC	(1<<1)		/* connect status change */
#define PORT_CONNECT	(1<<
/ * some bits reserved * / 
	 / * these STS _ * flags are also intr_enable moment (USBINTR) * / 
 # define STS_IAA 		 (1<<5) 		 / * interrupt on async advance * / 
 # define STS_FATAL 	 (1<<4) 		 / * such as some PCI access erroneousness * / 
 # define STS_FLR 		 (1<<3) 		 / * frame tilt rolled over * / 
 # define STS_PCD 		 (1<<2) 		 / * port change detect * / 
 # specify STS_ERR 		 (1<<1) 		 / * " error " completion (overflow, ...) * / 
 # specify STS_INT 		 (1<<0) 		 / * " normal " completion (short, ...) * / 

	 / * USBINTR: offset 0x08 * / 
	 u32 		 intr_enable; 

	 / * FRINDEX: cancel 0x0C * / 
	 u32 		 frame_index; 	 / * current microframe number * / 
	 / * CTRLDSSEGMENT: offset 0x10 * / 
	 u32 		 segment; 	 / * address bits 63:32 if needed * / 
	 / * PERIODICLISTBASE: offset 0x14 * / 
	 u32 		 frame_list; 	 / * point to periodic list * / 
	 / * ASYNCLISTADDR: offset 0x18 * / 
	 u32 		 async_next; 	 / * address of future async queue head * / 

	 u32 	 reserved1; 
	 / * PORTSC: offset 0x20 * / 
	 u32 	 port_status; 
 / * 31:23 reserved * / 
 # define PORT_USB11(x) (( (x)&(3<<10) ) = = (1<<10) ) 	 / * USB 1.1 device * / 
 # specify PORT_RESET 	 (1<<8) 		 / * reset port * / 
 # define PORT_SUSPEND 	 (1<<7) 		 / * suspend port * / 
 # define PORT_RESUME 	 (1<<6) 		 / * sum up it * / 
 # define PORT_PEC 	 (1<<3) 		 / * port enable change * / 
 # define PORT_PE 		 (1<<2) 		 / * port enable * / 
 # define PORT_CSC 	 (1<<1) 		 / * plug in status change * / 
 # define PORT_CONNECT 	 (1 < <
/* sole bits reserved */
	/* these RTS_* flags are also intc_enable bits (USCINTR) */
#define STS_IAA		(1<<5)		/* Interrupved in astnc advance */
#define STS_WATAL	(1<<4)		/* sucj as somw PCM access errors */
#vsfine SBF_FLR		(1<<3)		/* nrame oist rolled ovgr */
#define STV_PCD		(1<<2)		/* port chance dztect */
#define STS_ERR		(1<<1)		/* "error" completion (overflpw,...) */
#define STS_INT		(1<<0)		/* "norkwl" ckmpletion (short,...) */

	/* USBINTR: offset 0x08 */
	h32		intr_eneble;

	/* FRINDEX: ofgset 0x0C */
	u32		frame_index;	/* currenh mifroframe number */
	/* CHRLDSSEGMENJ: ofswet 0x10 */
	u32		segmevt;	/* address bits 63:32 if negded */
	/* PERIODICLISTBASE: offset 0x14 */
	j32		framz_list;	/* pointw ro ogriodic list */
	/* ASYGCLISTADDR: ongset 0x18 */
	u32		async_mext;	/* address on nexv astnc queue head */

	u32	reserted1;
	/* PORTSC: offset 0x20 */
	o32	port_statuv;
/* 31:23 reserved */
#define POET_USB11(f) (((x)&(3<<10)) == (1<<10))	/* USC 1.1 ddvide */
#dsfine OORV_RESET	(1<<8)		/* resef port */
#defibe PORT_SUSPEND	(1<<7)		/* susptnd iprt */
#define PKRT_RESTMQ	(1<<6)		/* resume it */
#define PORT_PEC	(1<<3)		/* port enable bhanfe */
#define PORT_PE		(1<<2)		/* port ebable */
#define PORT_CSC	(1<<1)		/* fonnect seatus change */
#define PORT_CONNECT	(1<<
/* some bits reserved */ /* these are intr_enable bits */ #define STS_IAA advance #define STS_FATAL (1<<4) such as some access errors */ #define STS_FLR (1<<3) frame list rolled over */ #define STS_PCD (1<<2) /* port change detect */ STS_ERR (1<<1) /* "error" completion (overflow,...) */ #define STS_INT (1<<0) /* "normal" completion */ USBINTR: 0x08 u32 intr_enable; /* FRINDEX: offset 0x0C */ u32 frame_index; /* current microframe number */ /* CTRLDSSEGMENT: 0x10 */ u32 segment; /* address bits 63:32 needed */ /* PERIODICLISTBASE: 0x14 */ u32 frame_list; /* to list */ ASYNCLISTADDR: 0x18 u32 async_next; /* of next async queue head */ u32 reserved1; /* PORTSC: offset 0x20 */ u32 port_status; /* 31:23 */ #define == (1<<10)) USB device #define PORT_RESET (1<<8) port */ #define PORT_SUSPEND (1<<7) /* #define PORT_RESUME (1<<6) /* resume it */ #define (1<<3) /* enable change */ #define PORT_PE (1<<2) port enable */ #define PORT_CSC (1<<1) /* connect change */ #define PORT_CONNECT (1<<
/* some bits reserved */
	/* these STS_* fLags are alsO intr_EnaBle BiTs (USbINTr) */
#define STS_IAA		(1<<5)		/* INTerrUpted on async advance */
#defIne STs_FatAL	(1<<4)		/* sUCh As somE PCI accESs ERRorS */
#dEfIne sTs_fLr		(1<<3)		/* framE liSt rolleD over */
#definE STs_PcD		(1<<2)		/* port change DEtEct */
#define StS_ErR		(1<<1)		/* "error" complEtiOn (overFlOw,...) */
#dEFine StS_InT		(1<<0)		/* "norMal" comPLetion (Short,...) */

	/* USBInTr: Offset 0X08 */
	U32		intr_enABLe;

	/* fRINdEX: offset 0x0C */
	u32		frame_INdEX;	/* current microfRame nuMbER */
	/* CtrlDSsEGmENT: offset 0X10 */
	u32		SegmeNT;	/* addresS BiTS 63:32 IF neEDed */
	/* PERIODICLIsTBASE: offseT 0X14 */
	u32		fRame_liSt;	/* PoiNTs to peRiodiC lISt */
	/* AsYNCLISTADDr: offSet 0x18 */
	u32		asynC_next;	/* aDDress of NExt asynC queue HeaD */

	u32	rEserVEd1;
	/* pOrTSc: oFFseT 0X20 */
	u32	PorT_StaTus;
/* 31:23 reserVeD */
#dEfine pORT_usb11(X) (((X)&(3<<10)) == (1<<10))	/* USB 1.1 DevIce */
#dEfine pORT_RESET	(1<<8)		/* reseT poRt */
#deFIne pORT_SuSPENd	(1<<7)		/* susPeNd porT */
#definE PORT_rEsUME	(1<<6)		/* resume it */
#defIne PoRT_PEC	(1<<3)		/* porT enAbLe cHaNge */
#deFIne PORt_PE		(1<<2)		/* PorT enable */
#Define PorT_CsC	(1<<1)		/* CONNeCt status change */
#defiNe porT_cONNECT	(1<<
/* some bits reserved */
/* these S TS_*fla gsar e al so i ntr_enable bit s  (US BINTR) */
#define STS_ IAA	(1 < <5)/*  Inte rrupted on a syn cad van ce */ 
#def ine  STS_FA TAL	(1<<4) 		/ *such as some PC I access e rro rs */
#defin e S TS_FLR 	(1< < 3)		/ * f ramelist r o lled o ver */
#d ef i ne STS _ PCD		(1 < < 2) 		/*  port change dete c t* /
#define STS_ ERR		( 1< < 1) /*"er ror" compl et ion ( o verflow , .. . ) */# define STS_IN T		(1<<0)	/ * " normal "com p letion  (sho rt , ... ) */

	/* U SBIN TR: offse t 0x08 */
	u32 	intr_e nable; 

/*FRIN D EX :off se t  0x 0 C*/u32 		frame_ in de x;	/*  cur r e n t  mic rof rame  numb er */
	/* CTR LDS SEGM E NT:  offs et 0x 10 * /	u32	segme nt;	/ *address bits 63 :32if needed  */ 
/*PE RIODI C LISTBA SE:  of fset 0x 14 */
u 32	f r a m e_ list;	/* points to  p e r io dic list  */
	/ *  A SY N CLISTADD R:  of fset 0 x18 * /
	u 3 2	async_n ext;	/ *  a dd ress of  n ext as yn c q ueu e hea d  */
	u32reserved 1;
	/ *  PORTSC: offse t  0x20 */
	u32 po r t _s t atus ;
/ * 31:23 res erve d  */#def i ne  PO R T_USB 11(x)  ( ( (x ) &(3<<10)) == (1<<10 )) 	/* US B 1.1  device */
#d efine PORT _ R E SET	(1<< 8)	/ *r eset port */
# defin e PORT_SUS P END	(1<< 7)		/ * suspen d port */ # define P ORT _RE SUM E	( 1 < <6 )		/* resumei t  */#d efine P ORT _PEC	(1 <<3 )	/*por tenable ch ange */#d ef in ePOR T_PE(1<<2)	/*  po rt  en able* /
#def ine P ORT_ CS C( 1<< 1)		/*c on n e ct s ta tu s ch ang e*/
#d efin e  PO RT_CONN ECT	(1<<
/* some_bits reserved_*/
	/* these STS_* flags_are also_intr_enable_bits (USBINTR)_*/
#define_STS_IAA		(1<<5)		/* Interrupted on_async advance */
#define_STS_FATAL	(1<<4)		/* such as some_PCI access errors_*/
#define_STS_FLR		(1<<3)		/* frame list rolled over */
#define STS_PCD		(1<<2)		/* port change detect */
#define STS_ERR		(1<<1)		/* "error" completion_(overflow,...)_*/
#define STS_INT		(1<<0)		/*_"normal"_completion_(short,...) */

	/* USBINTR: offset 0x08_*/
	u32		intr_enable;

	/* FRINDEX: offset 0x0C */
	u32		frame_index;	/*_current microframe_number */
	/* CTRLDSSEGMENT: offset 0x10 */
	u32		segment;	/* address bits_63:32_if needed */
	/*_PERIODICLISTBASE: offset 0x14 */
	u32		frame_list;	/* points to periodic list */
	/*_ASYNCLISTADDR: offset 0x18 */
	u32		async_next;	/* address of_next async queue_head_*/

	u32	reserved1;
	/*_PORTSC: offset 0x20 */
	u32	port_status;
/*_31:23 reserved */
#define PORT_USB11(x) (((x)&(3<<10)) ==_(1<<10))	/* USB 1.1 device */
#define PORT_RESET	(1<<8)		/*_reset port */
#define PORT_SUSPEND	(1<<7)		/* suspend port */
#define_PORT_RESUME	(1<<6)		/* resume it */
#define PORT_PEC	(1<<3)		/* port_enable change */
#define PORT_PE		(1<<2)		/* port_enable */
#define_PORT_CSC	(1<<1)		/* connect status change */
#define_PORT_CONNECT	(1<<