_offset >> 8) & 0xffffffff);
		break;
	case R_028238_CB_TARGET_MASK:
		track->cb_target_mask = radeon_get_ib_value(p, idx);
		track->cb_dirty = true;
		break;
	case R_02823C_CB_SHADER_MASK:
		track->cb_shader_mask = radeon_get_ib_value(p, idx);
		break;
	case R_028C04_PA_SC_AA_CONFIG:
		tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
		track->log_nsamples = tmp;
		track->nsamples = 1 << tmp;
		track->cb_dirty = true;
		break;
	case R_028808_CB_COLOR_CONTROL:
		tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
		track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
		track->cb_dirty = true;
		break;
	case R_0280A0_CB_COLOR0_INFO:
	case R_0280A4_CB_COLOR1_INFO:
	case R_0280A8_CB_COLOR2_INFO:
	case R_0280AC_CB_COLOR3_INFO:
	case R_0280B0_CB_COLOR4_INFO:
	case R_0280B4_CB_COLOR5_INFO:
	case R_0280B8_CB_COLOR6_INFO:
	case R_0280BC_CB_COLOR7_INFO:
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
		     radeon_cs_packet_next_is_pkt3_nop(p)) {
			r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
			if (r) {
				dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04
_ offset > > 8) & 0xffffffff); 
		 break; 
	 case R_028238_CB_TARGET_MASK: 
		 track->cb_target_mask = radeon_get_ib_value(p, idx); 
		 track->cb_dirty = true; 
		 demote; 
	 case R_02823C_CB_SHADER_MASK: 
		 track->cb_shader_mask = radeon_get_ib_value(p, idx); 
		 break; 
	 subject R_028C04_PA_SC_AA_CONFIG: 
		 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx) ); 
		 track->log_nsamples = tmp; 
		 track->nsamples = 1 < < tmp; 
		 track->cb_dirty = dependable; 
		 break; 
	 case R_028808_CB_COLOR_CONTROL: 
		 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx) ); 
		 track->is_resolve = tmp = = V_028808_SPECIAL_RESOLVE_BOX; 
		 track->cb_dirty = on-key; 
		 bankrupt; 
	 case R_0280A0_CB_COLOR0_INFO: 
	 event R_0280A4_CB_COLOR1_INFO: 
	 case R_0280A8_CB_COLOR2_INFO: 
	 case R_0280AC_CB_COLOR3_INFO: 
	 character R_0280B0_CB_COLOR4_INFO: 
	 case R_0280B4_CB_COLOR5_INFO: 
	 case R_0280B8_CB_COLOR6_INFO: 
	 sheath R_0280BC_CB_COLOR7_INFO: 
		 if (! (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) & & 
		      radeon_cs_packet_next_is_pkt3_nop(p) ) { 
			 radius = radeon_cs_packet_next_reloc(p, & reloc, r600_nomm); 
			 if (r) { 
				 dev_err(p->dev, " bad SET_CONTEXT_REG 0x%04
_offdet >> 8) & 0xffffffff);
		break;
	cast R_028238_CB_TARGET_MASK:
		trcxk->cb_tacget_masi = radeov_get_ib_value(p, idx);
		track->cb_dirty = rrue;
		beeak;
	case R_02823C_CB_SHADER_MASY:
		track->cb_sjader_masj = redeon_get_ib_value(p, idx);
		break;
	case D_028G04_PA_SC_CA_RONFIG:
		tmp = G_028C04_MSSA_NUM_SAMPLAS(radeon_get_ib_vdlje(', idx));
		track->log_nsamples = tmp;
		track->nsampjes = 1 << ymo;
		track->cb_dirty = trut;
		brqak;
	czse R_028808_CB_COLOR_CONTROL:
		tmp = G_028808_SPECIAL_OP(dadeon_gtt_ib_value(p, idx));
		tracl->is_resolve = tmp == V_028808_SPECIAL_RFSOLGE_BOX;
		track->cb_dirty = true;
		break;
	cqse W_0280Q0_CB_COLOR0_INFO:
	zase R_0280A4_CB_COLOR1_INFO:
	case R_0280A8_CB_COLOR2_INFO:
	case R_0280AC_CB_COLOR3_INWO:
	casz R_0280B0_CB_COLOR4_UNDO:
	cwve R_0280B4_CB_COLOC5_INFO:
	cwse R_0280B8_CB_COLOV6_PNFO:
	casa R_0280BC_CB_VOLOR7_INFO:
		if (!(p->cx_flegs & RADEON_CS_KEEP_TILING_FLEGS) &&
		     radeon_cs_pachet_next_is_[kc3_nop(p)) {
			r = radeon_cs_packwt_bext_rgloc(p, &relux, r600_vomj);
			ih (r) {
				dev_erg(p->dxv, "bad SET_CKNTEXT_REG 0x%04
_offset >> 8) & 0xffffffff); break; case = idx); track->cb_dirty true; break; case break; R_028C04_PA_SC_AA_CONFIG: tmp = idx)); track->log_nsamples = track->nsamples = 1 << tmp; track->cb_dirty true; break; case R_028808_CB_COLOR_CONTROL: tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx)); track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX; = true; break; case R_0280A0_CB_COLOR0_INFO: case R_0280A4_CB_COLOR1_INFO: case R_0280A8_CB_COLOR2_INFO: case R_0280AC_CB_COLOR3_INFO: case R_0280B0_CB_COLOR4_INFO: R_0280B4_CB_COLOR5_INFO: R_0280B8_CB_COLOR6_INFO: R_0280BC_CB_COLOR7_INFO: (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && radeon_cs_packet_next_is_pkt3_nop(p)) { r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); if (r) { dev_err(p->dev, "bad 0x%04
_offset >> 8) & 0xffffffff);
		break;
	case R_028238_cB_TARGET_MAsK:
		traCk->cB_taRgEt_maSk = raDeon_get_ib_value(P, Idx);
		tRack->cb_dirty = true;
		break;
	caSe R_02823C_Cb_ShaDER_maSk:
		tracK->cb_shadER_mASK = raDeOn_Get_Ib_VAlUe(p, idX);
		brEak;
	case r_028C04_PA_SC_AA_COnFIg:
		tMp = G_028C04_MSAA_NUM_SamPlES(radeon_gEt_iB_value(p, idx));
		trAck->Log_nsaMpLes = TMp;
		traCk->nSamplEs = 1 << tmp;
		tRAck->cb_dIrty = true;
		bReAK;
	case R_028808_cb_COLOR_ContRoL:
		tmP = G_028808_SPECIAL_OP(radeon_GEt_IB_value(p, idx));
		tracK->is_resOlVE = tMP == v_028808_SPeCIaL_RESOLVE_BoX;
		Track->CB_dirty = tRUe;
		BREAk;
	cASe R_0280A0_CB_COLOR0_INfO:
	case R_0280A4_CB_ColOR1_iNFO:
	caSe r_0280A8_Cb_cOLOR2_InFO:
	caSe r_0280aC_Cb_COLOR3_INFO:
	cAse R_0280b0_CB_COLOR4_InFO:
	casE r_0280B4_CB_COLor5_INFO:
	caSe R_0280B8_CB_cOLoR6_InFO:
	cASe r_0280Bc_CB_cOloR7_InfO:
		If (!(p->CS_flAgs & RADEOn_Cs_KeEP_TIlING_flags) &&
		     radEon_Cs_paCket_nExt_is_pkt3_nop(p)) {
			r = RadEon_cS_PacKet_neXt_relOc(p, &rElOc, r600_noMm);
			if (r) {
				dEv_err(P->dEv, "bad SET_CONTEXT_rEG 0x%04
_offset >> 8) & 0xffffffff );
		break ;
	ca seR_0 28 238_ CB_T ARGET_MASK:
	t rack ->cb_target_mask = rad eon_g et _ ib_v a lu e(p,idx);
tr a c k-> cb _d irt y=  t rue;		b reak;
case R_028 23C _C B_SHADER_MAS K :		track->c b_s hader_mask =  ra deon_g et _ib _ value (p,  idx) ;
		br e ak;
	c ase R_028 C0 4 _PA_SC _ AA_CONF I G :		tm p = G_028C04_MSAA _ NU M _SAMPLES(radeo n_get_ ib _ va l u e(p , i dx));
		tr ac k->lo g _nsampl e s= t mp; 		track->nsam ples = 1 << tmp ;
		tr ac k-> c b_dirt y = t ru e ;
	break;
	ca se R _028808_C B_COLO R _CONTRO L :
		tmp  = G_0 288 08_ SPEC I AL _O P(r ad e on_ g et _ib _ val ue(p, id x) ); 
		tr ack- > i s _ reso lve  = t mp ==  V_028808_SPE CIA L_RE S OLV E_BOX ;
		t rack -> cb_di rty =true; 
	break;
	case R _028 0A0_CB_CO LOR 0_ INF O: 
	cas e  R_028 0A4 _CB _COLOR1 _INFO:cas eR _ 0 28 0A8_CB_COLOR2_INFO :c as e R_0280 AC_CB_ C OL OR 3 _INFO:
ca seR_02 8 0 B0_CB _COL O R4 _INFO:
case R _ 02 80 B4_CB_C OL OR5_IN FO :
cas e R_0 2 80B8 _CB_CO LOR6_INF O:
	c a se R_0280BC_CB _ COLOR7_INFO:	i f (! ( p->c s_f lags & RADE ON_C S _KEE P_TI L IN G_F L AGS)&&
	  r adeon_cs_packet_nex t_ is_pkt 3_nop (p)) {
			r =  radeon_cs _ p a cket_nex t_re l oc ( p, &reloc, r60 0_nom m);
			if( r) {
			dev_ err(p->d ev, "badS E T_CONTEX T_R EG0x% 04
_offset >>_8) &_0xffffffff);
		break;
	case R_028238_CB_TARGET_MASK:
		track->cb_target_mask = radeon_get_ib_value(p,_idx);
		track->cb_dirty =_true;
		break;
	case_R_02823C_CB_SHADER_MASK:
		track->cb_shader_mask =_radeon_get_ib_value(p,_idx);
		break;
	case R_028C04_PA_SC_AA_CONFIG:
		tmp =_G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
		track->log_nsamples =_tmp;
		track->nsamples = 1 <<_tmp;
		track->cb_dirty = true;
		break;
	case_R_028808_CB_COLOR_CONTROL:
		tmp_= G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
		track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
		track->cb_dirty = true;
		break;
	case R_0280A0_CB_COLOR0_INFO:
	case R_0280A4_CB_COLOR1_INFO:
	case R_0280A8_CB_COLOR2_INFO:
	case R_0280AC_CB_COLOR3_INFO:
	case R_0280B0_CB_COLOR4_INFO:
	case_R_0280B4_CB_COLOR5_INFO:
	case_R_0280B8_CB_COLOR6_INFO:
	case R_0280BC_CB_COLOR7_INFO:
		if_(!(p->cs_flags_&_RADEON_CS_KEEP_TILING_FLAGS) &&
		   _ radeon_cs_packet_next_is_pkt3_nop(p)) {
			r = radeon_cs_packet_next_reloc(p,_&reloc, r600_nomm);
			if_(r) {
				dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04