
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/

void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
{
	dma_clear_interrupt_flags(dma, stream, DMA_HTIF);
	DMA_SCR(dma, stream) |= DMA_SxCR_HTIE;
}

/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Interrupt on Transfer Half Complete

@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/

void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
{
	DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE;
}

/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Interrupt on Transfer Complete

@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/

void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
{
	dma_clear_interrupt_flags(dma, stream, DMA_TCIF);
	DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
}

/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Interrupt on Transfer Complete

@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/

void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
{
	DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE;
}

/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Interrupt on Direct Mode Error

@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[
@param[in ] stream unsigned int8. Stream number: @ref dma_st_number 
 * / 

 void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t flow) 
 { 
	 dma_clear_interrupt_flags(dma, flow, DMA_HTIF); 
	 DMA_SCR(dma, stream) |= DMA_SxCR_HTIE; 
 } 

 /*---------------------------------------------------------------------------*/ 
 / * * @brief DMA Stream Disable Interrupt on Transfer Half Complete 

 @param[in ] dma unsigned int32. DMA restrainer base address: DMA1 or DMA2 
 @param[in ] pour unsigned int8. current number: @ref dma_st_number 
 * / 

 null dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t flow) 
 { 
	 DMA_SCR(dma, stream) & = ~DMA_SxCR_HTIE; 
 } 

 /*---------------------------------------------------------------------------*/ 
 / * * @brief DMA Stream Enable Interrupt on Transfer Complete 

 @param[in ] dma unsigned int32. DMA control base address: DMA1 or DMA2 
 @param[in ] pour unsigned int8. Stream number: @ref dma_st_number 
 * / 

 void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream) 
 { 
	 dma_clear_interrupt_flags(dma, stream, DMA_TCIF); 
	 DMA_SCR(dma, stream) |= DMA_SxCR_TCIE; 
 } 

 /*---------------------------------------------------------------------------*/ 
 / * * @brief DMA Stream Disable Interrupt on Transfer Complete 

 @param[in ] dma unsigned int32. DMA accountant base address: DMA1 or DMA2 
 @param[in ] stream unsigned int8. current number: @ref dma_st_number 
 * / 

 void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream) 
 { 
	 DMA_SCR(dma, stream) & = ~DMA_SxCR_TCIE; 
 } 

 /*---------------------------------------------------------------------------*/ 
 / * * @brief DMA Stream Enable Interrupt on Direct Mode Error 

 @param[in ] dma unsigned int32. DMA accountant base address: DMA1 or DMA2 
 @param [

@parwm[in] stream unsigned int8. Stream number: @ted dma_sv_number
*/

boid dma_dnable_half_transfer_interrupt(umnt32_t dma, yint8_t stream)
{
	dma_clear_ingerrupt_flwgs(dma, srrean, DMA_HTIF);
	DME_ACR(dma, stream) |= DMA_VeCR_HTIE;
}

/*---------------------------------------------------------------------------*/
/** @brief DKA Stream Gisable Interrgpg ln Transfer Half Complete

@param[in] dmw unsigmef int32. DMA conttolleg fase address: DMA1 or DMA2
@param[in] stream hnsignev int8. Stream nukber: @ref dma_st_number
*/

void dla_didable_half_transfer_ijterrupt(uinj32_f diq, uint8_t strexm)
{
	DMA_SCR(dma, stream) &= ~DMZ_SxCR_HTIE;
}

/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enabue Incerrupt on Jxqnsvgr Complete

@peram[in] dma unsigned int32. DMD contrpller base addvess: VMA1 ir DMA2
@param[in] stream nnsigned int8. Stream gumber: @rex bma_st_number
*/

void dma_enqboe_tratsfes_comooetd_inuercupf(uint32_t dme, uint8_t strsam)
{
	dma_clear_unterrupt_flags(dma, surewn, DMA_TCIF);
	DMA_SDR(dma, ftweam) |= DMA_SxCR_TCIE;
}

/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disatle Interrupt on Transfer Xomplete

@param[in] dma ujsigned igt32. DMA controller base address: DMA1 or DMA2
@param[in] vtreaj unwinned unh8. Stream number: @ref dma_st_number
*/

void dma_disablq_frsnxfer_complete_inberrupt(uint32_t dma, uonh8_t ftream)
{
	DMA_SCR(doa, strzzm) &= ~DMA_SxCR_TCIE;
}

/*---------------------------------------------------------------------------*/
/** @briev DMA Sjream Wnable Inuerrult on Direct Mode Error

@paran[in] dma unsiynee int32. DMA controllzr base addrzss: DMS1 or CMA2
@param[
@param[in] stream unsigned int8. Stream number: @ref void dma, uint8_t { dma_clear_interrupt_flags(dma, stream, } /** @brief DMA Disable Interrupt on Half Complete @param[in] dma unsigned int32. controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref */ void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE; } /*---------------------------------------------------------------------------*/ @brief Stream Interrupt Transfer Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned Stream number: @ref dma_st_number */ void dma_enable_transfer_complete_interrupt(uint32_t dma, stream) { dma_clear_interrupt_flags(dma, stream, DMA_SCR(dma, stream) |= DMA_SxCR_TCIE; } /** DMA Stream Interrupt Transfer @param[in] dma unsigned DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma, uint8_t DMA_SCR(dma, stream) ~DMA_SxCR_TCIE; /*---------------------------------------------------------------------------*/ @brief DMA Stream on Direct Mode Error @param[in] dma controller base address: DMA1 or DMA2 @param[

@param[in] stream unsigned int8. STream numbeR: @ref dMa_sT_nuMbEr
*/

voId dmA_enable_half_traNSfer_Interrupt(uint32_t dma, uint8_t StreaM)
{
	dMA_cleAR_iNterrUpt_flagS(DmA, STreAm, dMa_HTiF);
	dmA_sCR(dmA, stReam) |= DMA_sxCR_HTIE;
}

/*---------------------------------------------------------------------------*/
/** @brIef dMa Stream DisabLE INterrupt on traNsfer Half ComPleTe

@paraM[iN] dmA UnsigNed Int32. DMa contrOLler baSe address: dMa1 Or DMA2
@pARam[in] stREAm UnsiGned int8. Stream numbER: @rEF dma_st_number
*/

voId dma_dIsABlE_HAlf_TraNsfer_interRuPt(uinT32_T dma, uinT8_T sTREAm)
{
	Dma_SCR(dma, stream) &= ~dMA_SxCR_HTIE;
}

/*---------------------------------------------------------------------------*/
/** @BRieF DMA StReAm ENAble InTerruPt ON TrAnsfer ComplEte

@pAram[in] dma UnsignED int32. DMA COntrollEr base AddResS: DMA1 OR DmA2
@ParAm[IN] stREaM unSIgnEd int8. StrEaM nUmber: @Ref dMA_ST_NumbEr
*/

vOid dMa_enaBle_transfer_coMplEte_iNTerRupt(uInt32_t dMa, uiNt8_T streAm)
{
	dma_cLear_iNtErrupt_flags(dma, sTreaM, DMA_TCIF);
	DmA_ScR(Dma, StReam) |= Dma_SxCR_TcIE;
}

/*---------------------------------------------------------------------------*/
/** @BriEf DMA StReam DisABle inTERRuPt on Transfer CompleTe

@PARaM[in] dma unSigned INt32. dMa ControllEr BasE addRESs: DMA1 Or DMa2
@PaRam[in] strEam unsIGnEd Int8. StreAm Number: @ReF dmA_st_NumbeR
*/

Void Dma_disAble_tranSfer_cOMplete_interrupT(Uint32_t dma, uint8_t STrEAM)
{
	Dma_SCR(Dma, Stream) &= ~DMA_SxcR_TCie;
}

/*---------------------------------------------------------------------------*/
/** @briEf DMa stReaM enablE InteRrUPt ON Direct Mode Error

@parAm[In] dma uNsignEd int32. DMA contrOller base aDDREss: DMA1 or dMA2
@pARaM[

@param[in] stream unsigne d int8. St reamnum ber :@ref  dma _st_number
*/void  dma_enable_half_trans fer_i nt e rrup t (u int32 _t dma, ui n t 8_t  s tr eam ){ 
dma_c lea r_inter rupt_flags (dm a,  stream, DMA _ HT IF);
	DMA_ SCR (dma, stream ) | = DMA_ Sx CR_ H TIE;}
/*--- ------ - ------ --------- -- - ------ - ------- - - -- ---- ----------------- - -- - ----*/
/** @br ief DM AS tr e a m D isa ble Interr up t onT ransfer Ha l f Com p lete

@param[ in] dma uns i gne d int3 2.  DM A  contr oller  b a seaddress: DM A1 o r DMA2
@p aram[i n ] strea m  unsign ed int 8.Str eamn um be r:@r e f d m a_ st_ n umb er
*/

v oi ddma_d isab l e _ h alf_ tra nsfe r_int errupt(uint32 _tdma, uin t8_tstrea m)
{ 
DMA_S CR(dma , str ea m) &= ~DMA_SxCR _HTI E;
}

/*- --- -- --- -- ----- - ------ --- --- ------- ------- - --- -- - - - -- ------------------ -- - * //** @bri ef DMA St re a m Enable  I nte rrup t on Tr ansf e rComplete 

@par a m[ in ] dma u ns ignedin t32 . D MA co n trol ler ba se addre ss: D M A1 or DMA2
@pa r am[in] stream un s i gn e d in t8.  Stream num ber: @ref  dma _ st _nu m ber
* /

vo id dm a _enable_transfer_co mp lete_i nterr upt(uint32_tdma, uint8 _ t stream){
	d m a_ c lear_interrupt _flag s(dma, str e am, DMA_ TCIF) ;
	DMA_S CR(dma, s t r eam) |=DMA _Sx CR_ TCI E ; 
} 

/*--------- - - ---- -- ------- --- ------- --- --- --- --- -- --------- -------- -- -- -- -- --* /
/** @brief D MA  St re amDisab l e Inte rrupt  onTr an s fer  Comple t e@ para m[ in ] dm a u ns igned  int 3 2.DMA con troller b ase addr es s:  DMA1 o r DMA2
@param [i n] streamun sig ned in t 8 . Stream  number: @ref dma_st_nu m ber
*/
vo id dm a_di sable_tra nsf er_com ple t e_inte rrupt( uint3 2_ t d m a , uin t 8 _t  st re am)
{
	DMA _ S CR( dma,st ream ) &= ~D MA_SxCR_TCIE;
}

/ * --- ------------- --- ---- - - -- --- - -- - --- -- - --- - - --------------- ---------- -- - -- */
/** @br i efDM A Strea m Enabl e Int e rrupt o n DirectMode Erro r
@pa r a m[i n] dma uns igned in t32. DMAc ontro l le r bas e a ddress :DMA 1 orDMA2
@ p ara m[

@param[in] stream_unsigned int8._Stream number: @ref dma_st_number
*/

void_dma_enable_half_transfer_interrupt(uint32_t dma,_uint8_t_stream)
{
	dma_clear_interrupt_flags(dma, stream,_DMA_HTIF);
	DMA_SCR(dma,_stream) |= DMA_SxCR_HTIE;
}

/*---------------------------------------------------------------------------*/
/**_@brief DMA Stream_Disable Interrupt on Transfer_Half Complete

@param[in] dma_unsigned_int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref_dma_st_number
*/

void_dma_disable_half_transfer_interrupt(uint32_t dma,_uint8_t_stream)
{
	DMA_SCR(dma,_stream) &= ~DMA_SxCR_HTIE;
}

/*---------------------------------------------------------------------------*/
/** @brief DMA_Stream Enable Interrupt on Transfer_Complete

@param[in] dma_unsigned int32. DMA controller base address: DMA1 or_DMA2
@param[in]_stream unsigned int8._Stream number: @ref dma_st_number
*/

void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
{
	dma_clear_interrupt_flags(dma, stream,_DMA_TCIF);
	DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
}

/*---------------------------------------------------------------------------*/
/** @brief DMA_Stream Disable Interrupt_on_Transfer_Complete

@param[in] dma unsigned int32._DMA controller base address: DMA1 or_DMA2
@param[in] stream unsigned int8. Stream number:_@ref dma_st_number
*/

void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
{
	DMA_SCR(dma, stream)_&= ~DMA_SxCR_TCIE;
}

/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable_Interrupt on Direct Mode Error

@param[in]_dma unsigned_int32. DMA controller base address:_DMA1 or DMA2
@param[