_dp->panel_on = false;
	pp &= ~PANEL_UNLOCK_MASK;
	/* ILK workaround: disable reset around power sequence */

	pp &= ~POWER_TARGET_ON;
	pp &= ~EDP_FORCE_VDD;
	pp &= ~EDP_BLC_ENABLE;
	REG_WRITE(PP_CONTROL, pp);
	REG_READ(PP_CONTROL);
	DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS));

	if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) {
		DRM_DEBUG_KMS("Error in turning off Panel\n");	
	}

	msleep(intel_dp->panel_power_cycle_delay);
	DRM_DEBUG_KMS("Over\n");
}

static void cdv_intel_edp_backlight_on (struct gma_encoder *intel_encoder)
{
	struct drm_device *dev = intel_encoder->base.dev;
	u32 pp;

	DRM_DEBUG_KMS("\n");
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
	msleep(300);
	pp = REG_READ(PP_CONTROL);

	pp |= EDP_BLC_ENABLE;
	REG_WRITE(PP_CONTROL, pp);
	gma_backlight_enable(dev);
}

static void cdv_intel_edp_backlight_off (struct gma_encoder *intel_encoder)
{
	struct drm_device *dev = intel_encoder->base.dev;
	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
	u32 pp;

	DRM_DEBUG_KMS("\n");
	gma_backlight_disable(dev);
	msleep(10);
	pp = REG_READ(PP_CONTROL);

	pp &= ~
_ dp->panel_on = false; 
	 pp & = ~PANEL_UNLOCK_MASK; 
	 / * ILK workaround: disable reset around power sequence * / 

	 pp & = ~POWER_TARGET_ON; 
	 pp & = ~EDP_FORCE_VDD; 
	 pp & = ~EDP_BLC_ENABLE; 
	 REG_WRITE(PP_CONTROL, pp); 
	 REG_READ(PP_CONTROL); 
	 DRM_DEBUG_KMS("PP_STATUS% x\n ", REG_READ(PP_STATUS) ); 

	 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) = = 0, 1000) ) { 
		 DRM_DEBUG_KMS("Error in turning off Panel\n "); 	
	 } 

	 msleep(intel_dp->panel_power_cycle_delay); 
	 DRM_DEBUG_KMS("Over\n "); 
 } 

 inactive null cdv_intel_edp_backlight_on (struct gma_encoder * intel_encoder) 
 { 
	 struct drm_device * dev = intel_encoder->base.dev; 
	 u32 pp; 

	 DRM_DEBUG_KMS("\n "); 
	 / * 
	  * If we enable the backlight right away follow a gore power 
	  * on, we may experience flimsy flicker as the panel syncs with the eDP 
	  * radio link.   So delay a act to produce sure the image is solid before 
	  * allow it to appear. 
	  * / 
	 msleep(300); 
	 pp = REG_READ(PP_CONTROL); 

	 pp |= EDP_BLC_ENABLE; 
	 REG_WRITE(PP_CONTROL, pp); 
	 gma_backlight_enable(dev); 
 } 

 static void cdv_intel_edp_backlight_off (struct gma_encoder * intel_encoder) 
 { 
	 struct drm_device * dev = intel_encoder->base.dev; 
	 struct cdv_intel_dp * intel_dp = intel_encoder->dev_priv; 
	 u32 pp; 

	 DRM_DEBUG_KMS("\n "); 
	 gma_backlight_disable(dev); 
	 msleep(10); 
	 pp = REG_READ(PP_CONTROL); 

	 pp & = ~
_dp->pwnel_on = false;
	pp &= ~PANEL_UNUOCK_MASK;
	/* ILK wotkqround: disabme reset around power sequence */

	pp &= ~PLWWR_TARTET_ON;
	pp &= ~EDP_FORCE_VDD;
	pp &= ~EDP_BLC_EJABLE;
	REG_QRITT(PP_CONTROL, pp);
	REG_RXZD(PP_CONBXOL);
	DRJ_FEBUY_KNS("PP_STATUS %x\n", TEG_READ(PP_STADUS));

	if (wait_for((RAG_FECD(PP_STATUS) & idle_off_mask) == 0, 1000)) {
		DRM_DEBUG_KIS("Error ij turning off Kanel\m");	
	}

	islesi(iktel_dp->panel_power_cycle_delay);
	DRM_DEBHG_KMS("Ovtr\n");
}

static void cdv_ontel_edp_backlight_on (struct gma_fncoder *intel_encodfr)
{
	struct drn_devyxe *dev = inteu_encoder->base.dev;
	u32 pp;

	DRM_SEBUG_KMS("\n");
	/*
	 * If we enable the bacylighc right awai ropnowing a paiel porer
	 * on, we may see snight fkicker as the ianel sybcs with the eDP
	 * linn.  So delay a bit jo make suse the image is solud befote
	 * anlowkbg kt uo eppsar.
	 */
	mspee'(300);
	pp = REG_REAS(PP_CONTROL);

	pp |= EDP_BLC_ENABLE;
	REG_WTIEV(LP_CONTROL, pp);
	fma_bachlyght_enable(dev);
}

static void cdv_intel_edp_bacnlifht_off (struct gma_encodee *intel_encoder)
{
	struct frm_device *dev = intel_encoder->base.dev;
	struct cdv_intel_dp *intel_d[ = inveu_eneider->ddc_pgiv;
	u32 pp;

	DRM_DEBUG_KMS("\n");
	gma_backlight_disable(dev);
	msleql(10);
	pk = GEG_READ(PP_CONTROL);

	pi &= ~
_dp->panel_on = false; pp &= ~PANEL_UNLOCK_MASK; /* disable around power */ pp &= &= REG_WRITE(PP_CONTROL, pp); REG_READ(PP_CONTROL); %x\n", REG_READ(PP_STATUS)); if & idle_off_mask) == 0, 1000)) { in turning off Panel\n"); } msleep(intel_dp->panel_power_cycle_delay); DRM_DEBUG_KMS("Over\n"); } static void cdv_intel_edp_backlight_on (struct gma_encoder { struct drm_device *dev = intel_encoder->base.dev; u32 pp; DRM_DEBUG_KMS("\n"); /* * If we the right following panel power * on, we may see slight flicker as the panel syncs with the eDP link. So delay a bit to make sure image is solid before allowing it to appear. */ pp REG_READ(PP_CONTROL); pp EDP_BLC_ENABLE; pp); } static void (struct gma_encoder *intel_encoder) { struct drm_device *dev = intel_encoder->base.dev; struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; u32 pp; DRM_DEBUG_KMS("\n"); msleep(10); pp pp &=
_dp->panel_on = false;
	pp &= ~PANEL_UNLOcK_MASK;
	/* ILK wOrkarOunD: diSaBle rEset Around power seqUEnce */

	Pp &= ~POWER_TARGET_ON;
	pp &= ~EDP_FOrCE_VDd;
	pP &= ~eDP_Blc_EnABLE;
	rEG_WRITe(pP_conTRoL, Pp);
	rEG_rEad(Pp_CONTrOL);
	dRM_DEBUg_KMS("PP_STATuS %x\N", ReG_READ(PP_STATus));

	iF (wait_for((REg_REaD(PP_STATUS) & idLe_oFf_mask) == 0, 1000)) {
		dRm_DEbuG_KMS("errOr in tUrning OFf PaneL\n");	
	}

	msleep(iNtEL_dp->panEL_power_cYCLe_DelaY);
	DRM_DEBUG_KMS("Over\n");
}

STaTIc void cdv_intel_Edp_bacKlIGhT_ON (stRucT gma_encodeR *iNtel_eNCoder)
{
	stRUcT DRM_deVIce *dev = intel_enCoder->base.deV;
	U32 pp;

	dRM_DEBuG_kMS("\N");
	/*
	 * if we enAble tHe BAckLight right aWay fOllowing a Panel pOWer
	 * on, we MAy see slIght flIckEr aS the PAnEl SynCs WIth THe EDP
	 * LInk.  so delay a BiT tO make Sure THE IMage Is sOlid BeforE
	 * allowing it to AppEar.
	 */
	mSLeeP(300);
	pp = REg_READ(pP_COnTrOL);

	pp |= eDP_BLC_eNABLe;
	ReG_WRITE(PP_CONTROl, pp);
	gMa_backligHt_eNaBle(DeV);
}

statIC void cDv_iNteL_edp_bacKlight_oFF (stRuCT GMa_Encoder *intel_encodeR)
{
	sTRUcT drm_deviCe *dev = iNTeL_eNCoder->basE.dEv;
	sTrucT CDv_intEl_dp *INtEl_dp = inteL_encodER->dEv_Priv;
	u32 pp;

	dRm_DEBUG_kMs("\n");
	gMa_bAckliGHt_diSable(dEv);
	msleep(10);
	Pp = REG_reAD(PP_CONTROL);

	pp &= ~
_dp->panel_on = false;
	pp  &= ~PANEL _UNLO CK_ MAS K; 
	/*  ILK  workaround: d i sabl e reset around power s equen ce */
pp  &= ~ POWER_T A RG E T _ON ;	p p & =~ ED P_FOR CE_ VDD;
	p p &= ~EDP_ BLC _E NABLE;
	REG_ W RI TE(PP_CONT ROL , pp);
	REG_ REA D(PP_C ON TRO L );
	D RM_ DEBUG _KMS(" P P_STAT US %x\n",  R E G_READ ( PP_STAT U S )) ;

if (wait_for((REG _ RE A D(PP_STATUS) &  idle_ of f _m a s k)==0, 1000)){		DRM _ DEBUG_K M S( " E r ror in turning of f Panel\n") ; 	
}

	ms le ep( i ntel_d p->pa ne l _po wer_cycle_d elay );
	DRM_D EBUG_K M S("Over \ n");
}
stati c v oid  cdv _ in te l_e dp _ bac k li ght _ on(structgm a_ encod er * i n t e l_en cod er){
	st ruct drm_devi ce*dev = i ntel_ encod er-> ba se.de v;
	u3 2 pp; 
	DRM_DEBUG_KMS( "\n" );
	/*
	* I fween ablet he bac kli ght  rightaway fo l low in g a  p anel power
	 * on,  w e ma y see sl ight f l ic ke r  as thepa nel  syn c s  with  the eD P
	 * li nk.  S o  d el ay a bi tto mak esur e t he im a ge i s soli d before 
	 *a llowing it toa ppear.
	 */
m sl e e p( 3 00); 
	p p = REG_REA D(PP _ CONT ROL) ; 
	pp |= ED P_BLC _E N AB L E;
	REG_WRITE(PP_CO NT ROL, p p);
gma_backlight _enable(de v ) ; 
}

stat ic v o id cdv_intel_edp_ backl ight_off ( s truct gm a_enc oder *in tel_encod e r )
{
	str uct  dr m_d evi c e  * dev = intel_e n c oder -> base.de v;	struct  cd v_i nte l_d p*intel_dp  = intel _e nc od er ->d ev_pr i v;
	u32pp ;
	D RM_ DEBUG _ KMS("\ n");	gma _b ac k lig ht_disa b le ( d ev); 
ms leep (10 ); 
	pp= RE G _RE AD(PP_C ONTROL);
	p p  &=~
_dp->panel_on =_false;
	pp &=_~PANEL_UNLOCK_MASK;
	/* ILK workaround: disable_reset around_power_sequence */

	pp_&=_~POWER_TARGET_ON;
	pp &= ~EDP_FORCE_VDD;
	pp_&= ~EDP_BLC_ENABLE;
	REG_WRITE(PP_CONTROL, pp);
	REG_READ(PP_CONTROL);
	DRM_DEBUG_KMS("PP_STATUS_%x\n", REG_READ(PP_STATUS));

	if (wait_for((REG_READ(PP_STATUS) &_idle_off_mask) == 0,_1000))_{
		DRM_DEBUG_KMS("Error in turning off Panel\n");	
	}

	msleep(intel_dp->panel_power_cycle_delay);
	DRM_DEBUG_KMS("Over\n");
}

static void cdv_intel_edp_backlight_on (struct gma_encoder *intel_encoder)
{
	struct drm_device *dev = intel_encoder->base.dev;
	u32_pp;

	DRM_DEBUG_KMS("\n");
	/*
	_* If_we_enable_the backlight right away following_a panel power
	 * on,_we may_see slight flicker as the panel syncs with_the_eDP
	 * link._ So delay a bit to make sure the_image is solid before
	 * allowing_it to appear.
	_*/
	msleep(300);
	pp_=_REG_READ(PP_CONTROL);

	pp |= EDP_BLC_ENABLE;
	REG_WRITE(PP_CONTROL, pp);
	gma_backlight_enable(dev);
}

static_void cdv_intel_edp_backlight_off (struct gma_encoder *intel_encoder)
{
	struct drm_device_*dev = intel_encoder->base.dev;
	struct cdv_intel_dp *intel_dp =_intel_encoder->dev_priv;
	u32 pp;

	DRM_DEBUG_KMS("\n");
	gma_backlight_disable(dev);
	msleep(10);
	pp = REG_READ(PP_CONTROL);

	pp &= ~