XmmRegister result;
  BxPackedMmxRegister op;

  // use MMX register as 64-bit value with convinient accessors
  MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());

  result.xmm64u(0) = int32_to_float64(MMXSD0(op));
  result.xmm64u(1) = int32_to_float64(MMXSD1(op));

  BX_WRITE_XMM_REG(i->dst(), result);
#endif

  BX_NEXT_INSTR(i);
}

/*
 * Opcode: 0F 2E
 * Compare two single precision FP numbers and set EFLAGS accordintly.
 * Possible floating point exceptions: #I, #D
 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISS_VssWssR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
  float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->dst()), op2 = BX_READ_XMM_REG_LO_DWORD(i->src());

  float_status_t status;
  mxcsr_to_softfloat_status_word(status, MXCSR);
  softfloat_status_word_rc_override(status, i);
  int rc = float32_compare_quiet(op1, op2, status);
  check_exceptionsSSE(get_exception_flags(status));
  BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
#endif

  BX_NEXT_INSTR(i);
}

/*
 * Opcode: 66 0F 2E
 * Compare two double precision FP numbers and set EFLAGS accordintly.
 * Possible floating point exceptions: #I, #D
 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsdR(bxInstruction_c *i)            	
{
#if BX
XmmRegister result; 
   BxPackedMmxRegister op; 

   // use MMX register as 64 - bit value with convinient accessors 
   MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src ()); 

   result.xmm64u(0) = int32_to_float64(MMXSD0(op) ); 
   result.xmm64u(1) = int32_to_float64(MMXSD1(op) ); 

   BX_WRITE_XMM_REG(i->dst (), resultant role); 
 # endif 

   BX_NEXT_INSTR(i); 
 } 

 / * 
  * Opcode: 0F 2E 
  * Compare two individual precision FP numbers and set EFLAGS accordintly. 
  * potential floating point exceptions: # I, # vitamin d 
  * / 
 BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISS_VssWssR(bxInstruction_c * i) 
 { 
 # if BX_CPU_LEVEL > = 6 
   float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->dst ()), op2 = BX_READ_XMM_REG_LO_DWORD(i->src ()); 

   float_status_t status; 
   mxcsr_to_softfloat_status_word(status, MXCSR); 
   softfloat_status_word_rc_override(status, iodine); 
   int rc = float32_compare_quiet(op1, op2, status); 
   check_exceptionsSSE(get_exception_flags(status) ); 
   BX_CPU_THIS_PTR write_eflags_fpu_compare(rc); 
 # endif 

   BX_NEXT_INSTR(i); 
 } 

 / * 
  * Opcode: 66 0F 2E 
  * Compare two double preciseness FP numbers and set EFLAGS accordintly. 
  * Possible floating distributor point exceptions: # I, # D 
  * / 
 BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsdR(bxInstruction_c * i)            	
 { 
 # if BX
XmmGegister result;
  BxPackeaMmxRegister op;

  // use KMX refister ar 64-bit value with convinient eccewsors
  MMXUQ(op) = BX_READ_XMM_REE_LO_QWORD(i->drc());

  resylt.xnn64u(0) = int32_to_float64(MMXSD0(op));
  rsdult.rmn64u(1) = int32_to_float64(KMXSD1(op));

  BF_WRITE_XMM_REG(i->dvt(), rzsult);
#endif

  BX_NEXT_INSTR(i);
}

/*
 * Opcode: 0F 2E
 * Compate two single prgcisipg FP numbers and set EFLAGS accordintlg.
 * Posspble floating poimt exceptions: #I, #D
 */
BX_INSF_TYOE BD_CPP_AttrRegparmN(1) BD_CPU_C::UCOMISW_VssRwsR(bxInstrucgion_c *i)
{
#if BX_CPU_LEVEL >= 6
  float32 op1 = BX_READ_XMM_REG_LO_DWORD(k->dst()), pp2 = BX_READ_ZMN_REH_NO_DWORD(i->src());

  flowt_status_t status;
  mxwsr_to_sogtfloat_status_wprd(vtarus, MXCSR);
  softfloat_svatus_word_rc_override(sjatus, i);
  itt rc = float32_compare_wuuet(op1, op2, vtatjw);
  zhedk_xxcsptiondSSX(get_exceptikn_flags(statys));
  BX_CPU_THIS_PTR wrotq_vglags_fpu_compzre(rc);
#egdyf

  BX_NEXT_INSTR(i);
}

/*
 * Opcode: 66 0F 2E
 * Compare uwo dkuble precision FP numbwrs and set EFLAGS acfordintly.
 * Possible floating point exceptions: #I, #D
 */
BX_INSF_TY[E BX_RPO_AturVcgpafnN(1) BX_CPU_C::UCOMISD_VsdWsdR(bxInstruction_c *i)            	
{
#in BX
XmmRegister result; BxPackedMmxRegister op; // use MMX 64-bit with convinient MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src()); int32_to_float64(MMXSD1(op)); result); #endif BX_NEXT_INSTR(i); /* * Opcode: 2E * Compare two single precision numbers and set EFLAGS accordintly. * Possible floating point exceptions: #I, #D */ BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISS_VssWssR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 6 float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->dst()), op2 BX_READ_XMM_REG_LO_DWORD(i->src()); status; MXCSR); i); int rc = float32_compare_quiet(op1, op2, status); check_exceptionsSSE(get_exception_flags(status)); BX_CPU_THIS_PTR write_eflags_fpu_compare(rc); #endif BX_NEXT_INSTR(i); } /* * Opcode: 0F 2E * Compare two double precision FP and set EFLAGS accordintly. Possible floating point exceptions: #I, */ BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsdR(bxInstruction_c { BX
XmmRegister result;
  BxPackedmmxRegisteR op;

  // usE MMx reGiSter As 64-biT value with convINienT accessors
  MMXUQ(op) = BX_REAd_XMM_ReG_lo_QWOrd(i->Src());

  reSult.xmm64U(0) = InT32_TO_flOaT64(MmXSd0(oP));
  ReSult.xMm64u(1) = Int32_to_flOat64(MMXSD1(op));

  bX_WrItE_XMM_REG(i->dst(), REsUlt);
#endif

  BX_nEXt_INSTR(i);
}

/*
 * OpcodE: 0F 2E
 * comparE tWo sINgle pRecIsion fP numbERs and sEt EFLAGS aCcORdintlY.
 * possiblE FLoAtinG point exceptions: #I, #d
 */
bX_inSF_TYPE BX_CPP_AtTrRegpArMn(1) Bx_cpU_C::uCOmISS_VssWssr(bXInstRUction_c *I)
{
#If bx_cpU_LevEL >= 6
  float32 op1 = BX_ReAD_XMM_REG_LO_dwORd(i->dst()), oP2 = Bx_REad_XMM_REg_LO_DWoRd(I->srC());

  float_statuS_t stAtus;
  mxcsr_To_softFLoat_staTUs_word(sTatus, MxCSr);
  soFtflOAt_StAtuS_wORd_rC_OvErrIDe(sTatus, i);
  inT rC = fLoat32_cOmpaRE_QUIet(oP1, op2, StatUs);
  cheCk_exceptionsSsE(gEt_exCEptIon_flAgs(stAtus));
  bX_cPU_THiS_PTR wRite_eFlAgs_fpu_compare(rc);
#EndiF

  BX_NEXT_INsTR(I);
}

/*
 * OPcoDe: 66 0f 2E
 * ComPAre two DouBle PrecisiOn FP numBErs AnD SET EfLAGS accordintly.
 * PoSsIBLe Floating Point eXCePtIOns: #I, #D
 */
BX_InSf_TYpE BX_cpp_AttrregpARmn(1) BX_CPU_C::UcOMISD_vSdwsDR(bxInsTrUction_C *i)            	
{
#If Bx
XmmRegister result;
  BxPa ckedMmxReg ister  op ;
 // u se M MX register as 64-b it value with convinie nt ac ce s sors  MMXUQ (op) =B X_ R E AD_ XM M_ REG _L O _Q WORD( i-> src()); 

  result .xm m6 4u(0) = int3 2 _t o_float64( MMX SD0(op));
 res ult.xm m6 4u( 1 ) = i nt3 2_to_ float6 4 (MMXSD 1(op));
 B X_WRIT E _XMM_RE G ( i- >dst (), result);
#end i f  BX_NEXT_INST R(i);}/* * O pco de: 0F 2E *  Comp a re twos in g l e  pr e cision FP num bers and se t  EF LAGS a cc ord i ntly. * Po ss i ble  floating p oint  exceptio ns: #I ,  #D
 */ BX_INSF _TYPEBX_ CPP _Att r Re gp arm N( 1 ) B X _C PU_ C ::U COMISS_V ss Ws sR(bx Inst r u c t ion_ c * i)
{ 
#ifBX_CPU_LEVEL>=6
 f loa t32 o p1 =BX_R EA D_XMM _REG_L O_DWO RD (i->dst()), op2  = B X_READ_XM M_R EG _LO _D WORD( i ->src( )); 

 float_ status_ t  st at u s ; 
 mxcsr_to_softfloa t_ s t at us_word( status ,  M XC S R);
  so ft flo at_s t a tus_w ord_ r c_ override (statu s ,i) ;
  int  r c = fl oa t32 _co mpare _ quie t(op1,  op2, st atus) ; 
  check_excep t ionsSSE(get_e x ce p t io n _fla gs( status));
 BX_ C PU_T HIS_ P TR  wr i te_ef lags_ fp u _c o mpare(rc);
#endif
 BX_NEX T_INS TR(i);
}

/* * Opcode: 6 6  0F 2E
* Co m pa r e two double p recis ion FP num b ers andset E FLAGS ac cordintly .  * Possi ble  fl oat ing p oi nt exceptions : #I,#D 
 */
BX _IN SF_TYPE  BX _CP P_A ttr Re gparmN(1)  BX_CPU_ C: :U CO MI SD_ VsdWs d R(bxInst ru cti on _c*i)         	{
#i fBX 
XmmRegister result;
_ BxPackedMmxRegister_op;

  // use_MMX register_as_64-bit value_with_convinient accessors
 _MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());

_ result.xmm64u(0) = int32_to_float64(MMXSD0(op));
_ result.xmm64u(1) =_int32_to_float64(MMXSD1(op));

_ BX_WRITE_XMM_REG(i->dst(), result);
#endif

  BX_NEXT_INSTR(i);
}

/*
 * Opcode: 0F 2E
 * Compare two single precision_FP_numbers and_set_EFLAGS_accordintly.
 * Possible floating point_exceptions: #I, #D
 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1)_BX_CPU_C::UCOMISS_VssWssR(bxInstruction_c *i)
{
#if_BX_CPU_LEVEL >= 6
  float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->dst()),_op2_= BX_READ_XMM_REG_LO_DWORD(i->src());

 _float_status_t status;
  mxcsr_to_softfloat_status_word(status, MXCSR);
  softfloat_status_word_rc_override(status, i);
 _int rc = float32_compare_quiet(op1, op2, status);
_ check_exceptionsSSE(get_exception_flags(status));
 _BX_CPU_THIS_PTR_write_eflags_fpu_compare(rc);
#endif

_ BX_NEXT_INSTR(i);
}

/*
 * Opcode:_66 0F 2E
 * Compare two_double precision FP numbers and set_EFLAGS accordintly.
 * Possible floating point exceptions:_#I, #D
 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsdR(bxInstruction_c *i)_    _ _    	
{
#if_BX