dp->link_status,
					  DP_LANE_ALIGN_STATUS_UPDATED);
	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
		return false;
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
		lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
		if ((lane_status & CHANNEL_EQ_BITS)!= CHANNEL_EQ_BITS)
			return false;
	}
	return true;
}

static bool
cdv_intel_dp_set_link_train(struct gma_encoder *encoder,
			uint32_t dp_reg_value,
			uint8_t dp_train_pat)
{
	
	struct drm_device *dev = encoder->base.dev;
	int ret;
	struct cdv_intel_dp *intel_dp = encoder->dev_priv;

	REG_WRITE(intel_dp->output_reg, dp_reg_value);
	REG_READ(intel_dp->output_reg);

	ret = cdv_intel_dp_aux_native_write_1(encoder,
				    DP_TRAINING_PATTERN_SET,
				    dp_train_pat);

	if (ret!= 1) {
		DRM_DEBUG_KMS("Failure in setting link pattern %x\n",
				dp_train_pat);
		return false;
	}

	return true;
}


static bool
cdv_intel_dplink_set_level(struct gma_encoder *encoder,
			uint8_t dp_train_pat)
{
	
	int ret;
	struct cdv_intel_dp *intel_dp = encoder->dev_priv;

	ret = cdv_intel_dp_aux_native_write(encoder,
					DP_TRAINING_LANE0_SET,
					intel_dp->train_set,
					intel_dp->lane_count);

	if (ret!= intel_dp->lane_count) {
		DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d
dp->link_status, 
					   DP_LANE_ALIGN_STATUS_UPDATED); 
	 if (( lane_align & DP_INTERLANE_ALIGN_DONE) = = 0) 
		 return false; 
	 for (lane = 0; lane < intel_dp->lane_count; lane++) { 
		 lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane); 
		 if (( lane_status & CHANNEL_EQ_BITS)!= CHANNEL_EQ_BITS) 
			 return false; 
	 } 
	 hark back genuine; 
 } 

 static bool 
 cdv_intel_dp_set_link_train(struct gma_encoder * encoder, 
			 uint32_t dp_reg_value, 
			 uint8_t dp_train_pat) 
 { 
	
	 struct drm_device * dev = encoder->base.dev; 
	 int ret; 
	 struct cdv_intel_dp * intel_dp = encoder->dev_priv; 

	 REG_WRITE(intel_dp->output_reg, dp_reg_value); 
	 REG_READ(intel_dp->output_reg); 

	 ret = cdv_intel_dp_aux_native_write_1(encoder, 
				     DP_TRAINING_PATTERN_SET, 
				     dp_train_pat); 

	 if (ret!= 1) { 
		 DRM_DEBUG_KMS("Failure in setting link practice% x\n ", 
				 dp_train_pat); 
		 return false; 
	 } 

	 come back true; 
 } 


 static bool 
 cdv_intel_dplink_set_level(struct gma_encoder * encoder, 
			 uint8_t dp_train_pat) 
 { 
	
	 int ret; 
	 struct cdv_intel_dp * intel_dp = encoder->dev_priv; 

	 ret = cdv_intel_dp_aux_native_write(encoder, 
					 DP_TRAINING_LANE0_SET, 
					 intel_dp->train_set, 
					 intel_dp->lane_count); 

	 if (ret!= intel_dp->lane_count) { 
		 DRM_DEBUG_KMS("Failure in dress level% d, lane_cnt=% d
dp->llnk_status,
					  DP_LANE_ALIGN_STXTUS_UPDATED);
	if ((lcbe_aligi & DP_INFERLANE_AUIGN_DONE) == 0)
		return false;
	for (laie = 0; lane < intel_dp->lane_count; land++) {
		lane_stanus = cdv_ibtel_jet_lane_status(intxm_dp->link_status, pane);
		nf ((lane_status & CMANNEL_EQ_BITV)!= CHANNEL_EQ_BITV)
			rdtbrn false;
	}
	return true;
}

static bool
cdv_ineel_dp_sey_llnk_train(struct gma_tncjder *vngoder,
			uint32_t dp_reg_value,
			uint8_t dp_trajn_pat)
{
	
	stguct drm_device *def = encoder->base.dev;
	int ret;
	stguct cdv_intel_dp *intel_do = encoder->dgb_pryc;

	REG_WRITE(intdl_dp->output_gzg, dp_reg_valoe);
	REG_READ(intel_dp->output_reg);

	ret = cdx_intek_dp_aux_natice_qrihg_1(encoder,
				    VP_TRAIGING_PATTERN_SCN,
				    dp_drain_pay);

	if (ret!= 1) {
		DRM_DENUG_KMV("Faulure in setting link pattern %x\n",
				dp_train_kat);
		return xamse;
	}

	return true;
}


starix boon
cdv_hnteu_eplknk_aev_lebel(strkct gma_encoded *encoder,
			uibt8_t dp_train_pat)
{
	
	int rtt;
	segict cdv_intel_sp *intql_qp = encoder->dev_priv;

	ret = cdv_intel_dp_aux_natpve_wdite(encoder,
					DP_TRAINING_LABE0_SET,
					intel_dp->train_set,
					ijtel_dp->lanq_count);

	if (ret!= intel_dp->lane_count) {
		DRM_DEBUG_KMS("Failure hn sevtkng lcvel %e, pane_cnt= %d
dp->link_status, DP_LANE_ALIGN_STATUS_UPDATED); if ((lane_align & DP_INTERLANE_ALIGN_DONE) == false; (lane = lane < intel_dp->lane_count; lane); ((lane_status & CHANNEL_EQ_BITS)!= return false; } true; } static bool cdv_intel_dp_set_link_train(struct gma_encoder uint32_t dp_reg_value, uint8_t dp_train_pat) { struct drm_device *dev = encoder->base.dev; int ret; struct *intel_dp = encoder->dev_priv; REG_WRITE(intel_dp->output_reg, dp_reg_value); REG_READ(intel_dp->output_reg); ret = cdv_intel_dp_aux_native_write_1(encoder, DP_TRAINING_PATTERN_SET, dp_train_pat); if (ret!= { in link %x\n", dp_train_pat); return false; } return true; } static bool cdv_intel_dplink_set_level(struct gma_encoder *encoder, uint8_t dp_train_pat) { ret; struct cdv_intel_dp *intel_dp = encoder->dev_priv; ret = DP_TRAINING_LANE0_SET, intel_dp->train_set, intel_dp->lane_count); if intel_dp->lane_count) { DRM_DEBUG_KMS("Failure in setting %d, %d
dp->link_status,
					  DP_LANE_ALIGN_STaTUS_UPDATEd);
	if ((laNe_aLigN & Dp_INTeRLAnE_ALIGN_DONE) == 0)
		retURn faLse;
	for (lane = 0; lane < intel_dp->lAne_coUnT; Lane++) {
		LAnE_statUs = cdv_inTEl_GET_laNe_StAtuS(iNTeL_dp->liNk_sTatus, laNe);
		if ((lane_stAtuS & ChANNEL_EQ_BITS)!= chAnNEL_EQ_BITS)
			RetUrn false;
	}
	retuRn tRue;
}

staTiC boOL
cdv_iNteL_dp_seT_link_tRAin(strUct gma_encOdER *encodER,
			uint32_t dP_REg_ValuE,
			uint8_t dp_train_pat)
{
	
	sTRuCT drm_device *dev = eNcoder->BaSE.dEV;
	Int Ret;
	Struct cdv_iNtEl_dp *iNTel_dp = enCOdER->DEv_pRIv;

	REG_WRITE(intEl_dp->output_rEG, dp_Reg_valUe);
	rEG_reAD(intEl_dp->oUtPUt_rEg);

	ret = cdv_intEl_dp_Aux_native_Write_1(eNCoder,
				    DP_trAINING_pATTERn_SEt,
				    dp_TraiN_PaT);

	iF (reT!= 1) {
		Drm_DEbuG_kMS("fAilUre in setTiNg Link pAtteRN %X\N",
				Dp_trAin_Pat);
		rEturn False;
	}

	return trUe;
}


sTatiC BooL
cdv_iNtel_dPlinK_sEt_levEl(struCt gma_EnCoder *encoder,
			uinT8_t dp_Train_pat)
{
	
	iNt rEt;
	StrUcT cdv_iNTel_dp *iNteL_dp = Encoder->Dev_priv;

	REt = cDv_INTEl_Dp_aux_native_write(enCoDER,
					Dp_TRAININg_LANE0_Set,
					iNtEL_dp->train_SeT,
					inTel_dP->LAne_coUnt);

	iF (ReT!= intel_dp->Lane_coUNt) {
		dRm_DEBUG_KmS("failurE iN seTtiNg levEL %d, laNe_cnt= %d
dp->link_status,
					  DP _LANE_ALIG N_STA TUS _UP DA TED) ;
	i f ((lane_align & DP _INTERLANE_ALIGN_DONE)  == 0 )	ret u rn  fals e;
	for (l a n e =  0 ;lan e<  i ntel_ dp- >lane_c ount; lane ++)  { 
		lane_stat u s= cdv_inte l_g et_lane_stat us( intel_ dp ->l i nk_st atu s, la ne);
if ((l ane_statu s&  CHANN E L_EQ_BI T S )! = CH ANNEL_EQ_BITS)
	re t urn false;
	}	retur nt ru e ; 
}
st atic boolcd v_int e l_dp_se t _l i n k _tr a in(struct gma _encoder *e n cod er,
		u int 3 2_t dp _reg_ va l ue, 
			uint8_t  dp_ train_pat )
{
	structd rm_devi ce *de v =  en code r -> ba se. de v ;
i nt  re t ;
struct c dv _i ntel_ dp * i n t e l_dp  =enco der-> dev_priv;

	R EG_ WRIT E (in tel_d p->ou tput _r eg, d p_reg_ value ); 
	REG_READ(inte l_dp ->output_ reg ); 

re t = c d v_inte l_d p_a ux_nati ve_writ e _1( en c o d er ,
				    DP_TRAIN IN G _ PA TTERN_SE T,
		  d p_train_ pa t); 

	i f (ret! = 1) {		DRM_DE BUG_KM S (" Fa ilure i nsettin glin k p atter n  %x\ n",
			dp_tra in_pa t );
		return fa l se;
	}

	retu r nt r ue ; 
}

st atic bool
c dv_i n tel_ dpli n k_ set _ level (stru ct gm a _encoder *encoder,		uint8 _t dp _train_pat)
{ 
	
	int re t ; 	structcdv_ i nt e l_dp *intel_dp  = en coder->dev _ priv;

ret =  cdv_int el_dp_aux _ n ative_wr ite (en cod er, 			DP_TRAINING _ L ANE0 _S ET,
				i ntel_dp ->t rai n_s et, 
				intel _dp->lan e_ co un t) ;
	if ( r et!= int el _dp -> lan e_cou n t) {
	DRM_ DEBU G_ KM S ("F ailurei ns e ttin gle vel%d,  l ane_c nt=% d
dp->link_status,
					 _DP_LANE_ALIGN_STATUS_UPDATED);
	if ((lane_align_& DP_INTERLANE_ALIGN_DONE) == 0)
		return_false;
	for (lane_=_0; lane_<_intel_dp->lane_count; lane++) {
		lane_status_= cdv_intel_get_lane_status(intel_dp->link_status, lane);
		if_((lane_status & CHANNEL_EQ_BITS)!= CHANNEL_EQ_BITS)
			return_false;
	}
	return true;
}

static bool
cdv_intel_dp_set_link_train(struct_gma_encoder_*encoder,
			uint32_t dp_reg_value,
			uint8_t dp_train_pat)
{
	
	struct drm_device *dev = encoder->base.dev;
	int ret;
	struct cdv_intel_dp *intel_dp = encoder->dev_priv;

	REG_WRITE(intel_dp->output_reg, dp_reg_value);
	REG_READ(intel_dp->output_reg);

	ret =_cdv_intel_dp_aux_native_write_1(encoder,
				_ __DP_TRAINING_PATTERN_SET,
				_   dp_train_pat);

	if (ret!=_1) {
		DRM_DEBUG_KMS("Failure in setting link_pattern %x\n",
				dp_train_pat);
		return_false;
	}

	return true;
}


static bool
cdv_intel_dplink_set_level(struct gma_encoder *encoder,
			uint8_t dp_train_pat)
{
	
	int ret;
	struct cdv_intel_dp_*intel_dp_= encoder->dev_priv;

	ret =_cdv_intel_dp_aux_native_write(encoder,
					DP_TRAINING_LANE0_SET,
					intel_dp->train_set,
					intel_dp->lane_count);

	if (ret!= intel_dp->lane_count) {
		DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt=_%d