 on this.
	 */
	if (avg_wire_size <= 360) {
		/* Start at 250K ints/sec and gradually drop to 77K ints/sec */
		avg_wire_size *= 8;
		avg_wire_size += 376;
	} else if (avg_wire_size <= 1152) {
		/* 77K ints/sec to 45K ints/sec */
		avg_wire_size *= 3;
		avg_wire_size += 2176;
	} else if (avg_wire_size <= 1920) {
		/* 45K ints/sec to 38K ints/sec */
		avg_wire_size += 4480;
	} else {
		/* plateau at a limit of 38K ints/sec */
		avg_wire_size = 6656;
	}

	/* Perform final bitshift for division after rounding up to ensure
	 * that the calculation will never get below a 1. The bit shift
	 * accounts for changes in the ITR due to PCIe link speed.
	 */
	itr_round = READ_ONCE(ring_container->itr_scale) + 8;
	avg_wire_size += BIT(itr_round) - 1;
	avg_wire_size >>= itr_round;

	/* write back value and retain adaptive flag */
	ring_container->itr = avg_wire_size | FM10K_ITR_ADAPTIVE;

clear_counts:
	ring_container->total_bytes = 0;
	ring_container->total_packets = 0;
}

static void fm10k_qv_enable(struct fm10k_q_vector *q_vector)
{
	/* Enable auto-mask and clear the current mask */
	u32 itr = FM10K_ITR_ENABLE;

	/* Update Tx ITR */
	fm10k_update_itr(&q_vector->tx);

	/* Update Rx ITR */
	fm10k_update_itr(&q_vector->rx);

	/* Store Tx itr in timer slot 0 */
	itr |= (q_vector->tx.itr & FM10K_ITR_MAX
on this. 
	  * / 
	 if (avg_wire_size < = 360) { 
		 / * Start at 250 K ints / sec and gradually drop to 77 K ints / sec * / 
		 avg_wire_size * = 8; 
		 avg_wire_size + = 376; 
	 } else if (avg_wire_size < = 1152) { 
		 / * 77 K ints / sec to 45 K ints / sec * / 
		 avg_wire_size * = 3; 
		 avg_wire_size + = 2176; 
	 } else if (avg_wire_size < = 1920) { 
		 / * 45 K ints / sec to 38 K ints / sec * / 
		 avg_wire_size + = 4480; 
	 } else { 
		 / * plateau at a limit of 38 K ints / sec * / 
		 avg_wire_size = 6656; 
	 } 

	 / * do concluding bitshift for class after rounding up to guarantee 
	  * that the calculation will never receive below a 1. The bit shift 
	  * account for variety in the ITR due to PCIe link speed. 
	  * / 
	 itr_round = READ_ONCE(ring_container->itr_scale) + 8; 
	 avg_wire_size + = BIT(itr_round) - 1; 
	 avg_wire_size > > = itr_round; 

	 / * write back value and retain adaptive flag * / 
	 ring_container->itr = avg_wire_size | FM10K_ITR_ADAPTIVE; 

 clear_counts: 
	 ring_container->total_bytes = 0; 
	 ring_container->total_packets = 0; 
 } 

 electrostatic void fm10k_qv_enable(struct fm10k_q_vector * q_vector) 
 { 
	 / * Enable auto - masquerade and clear the current mask * / 
	 u32 itr = FM10K_ITR_ENABLE; 

	 / * Update Tx ITR * / 
	 fm10k_update_itr(&q_vector->tx); 

	 / * Update Rx ITR * / 
	 fm10k_update_itr(&q_vector->rx); 

	 / * Store Tx itr in timer slot 0 * / 
	 itr |= (q_vector->tx.itr & FM10K_ITR_MAX
 on this.
	 */
	if (avg_wire_size <= 360) {
		/* Rtart at 250K ints/sec and graduzlly droo to 77K ints/sec */
		avg_wire_size *= 8;
		evg_wure_siev += 376;
	} else if (avg_wire_sixe <= 1152) {
		/* 77K ijts/sec ti 45K mnts/sec */
		avg_wire_smae *= 3;
		avg_wire_siac += 2176;
	} enwe if (avg_wire_slze <= 1920) {
		/* 45K inds/sec to 38K intv/sdc */
		avg_wire_size += 4480;
	} else {
		/* plateau at a lymit of 38K ints/sec */
		avg_wite_sizt = 6656;
	}

	/* Perrorm final bitshift for division arter rolnding up to ensute
	 * that the calculation wlll jever get below a 1. The bit shuft
	 * qccounts for changes in the ITR dug to PCIe link speed.
	 */
	itr_round = RDAD_ONEE(ring_contaunwr->iht_scale) + 8;
	avg_wmre_sizv += BIT(itr_round) - 1;
	avg_wise_size >>= itr_round;

	/* writc bacn vqlue and retain adaptmve flag */
	ring_containgr->itr = avg_fixe_size | FM10K_ITR_ADAPTIVW;

coear_cmuntv:
	rine_xongaihec->tofal_bytfs = 0;
	ring_contajner->total_paxkets = 0;
}

static void gm10h_wv_enable(strucf fm10k_q_destor *q_vector)
{
	/* Enable auto-mask and clear uhe chrrent mask */
	u32 itr = FM10K_IRR_ENABLE;

	/* Update Tx ITT */
	fm10k_updatq_itr(&q_vector->tx);

	/* Update Rx ITR */
	fm10k_update_itr(&q_vector->rx);

	/* Storx Gx nbv in riler slot 0 */
	itr |= (q_vector->tx.itr & FM10K_ITR_MAX
on this. */ if (avg_wire_size <= 360) Start 250K ints/sec gradually drop to 8; += 376; } if (avg_wire_size <= { /* 77K ints/sec to 45K */ avg_wire_size *= 3; avg_wire_size += 2176; } else if (avg_wire_size <= 1920) /* 45K ints/sec to 38K ints/sec */ avg_wire_size += 4480; } else { plateau a of ints/sec */ avg_wire_size = 6656; } /* Perform final bitshift for division after rounding up to * that the calculation will never get below 1. The bit shift accounts for changes in the due PCIe link */ = + 8; avg_wire_size BIT(itr_round) - 1; avg_wire_size >>= itr_round; /* write back value and retain adaptive flag */ ring_container->itr = | FM10K_ITR_ADAPTIVE; = 0; = } void fm10k_qv_enable(struct fm10k_q_vector /* Enable auto-mask and clear the u32 itr = FM10K_ITR_ENABLE; /* Update Tx ITR fm10k_update_itr(&q_vector->tx); /* Rx ITR */ fm10k_update_itr(&q_vector->rx); /* Store itr in timer slot 0 */ itr |= & FM10K_ITR_MAX
 on this.
	 */
	if (avg_wire_size <= 360) {
		/* Start aT 250K ints/sec aNd graDuaLly DrOp to 77k intS/sec */
		avg_wire_sizE *= 8;
		Avg_wIre_size += 376;
	} else if (avg_wire_siZe <= 1152) {
		/* 77K inTs/SEc to 45k InTs/sec */
		Avg_wire_SIzE *= 3;
		AVg_wIrE_sIze += 2176;
	} ElSE iF (avg_wIre_Size <= 1920) {
		/* 45K inTs/sec to 38K inTs/sEc */
		Avg_wire_size += 4480;
	} eLSe {
		/* Plateau at a LimIt of 38K ints/sec */
		Avg_Wire_siZe = 6656;
	}

	/* perFOrm fiNal BitshIft for DIvisioN after rouNdINg up to ENsure
	 * thAT ThE calCulation will never GEt BElow a 1. The bit shiFt
	 * accoUnTS fOR ChaNgeS in the ITR dUe To PCIE Link speED.
	 */
	iTR_ROunD = rEAD_ONCE(ring_cOntainer->itr_SCalE) + 8;
	avg_wiRe_SizE += bIT(itr_Round) - 1;
	AvG_WirE_size >>= itr_rouNd;

	/* wrIte back vaLue and REtain adAPtive flAg */
	ring_ConTaiNer->iTR = aVg_WirE_sIZe | Fm10k_ItR_AdaPTiVE;

clear_CoUnTs:
	rinG_conTAINEr->toTal_ByteS = 0;
	ring_Container->totaL_paCketS = 0;
}

StaTic voId fm10k_Qv_enAbLe(strUct fm10k_Q_vectOr *Q_vector)
{
	/* Enable auTo-maSk and cleaR thE cUrrEnT mask */
	U32 Itr = FM10K_iTR_eNAbLE;

	/* UpdaTe Tx ITR */
	FM10k_uPdATE_ItR(&q_vector->tx);

	/* Update Rx iTr */
	FM10k_Update_itR(&q_vectOR->rX);

	/* STOre Tx itr In TimEr slOT 0 */
	Itr |= (q_vEctoR->Tx.Itr & FM10K_ITr_MAX
 on this.
	 */
	if (avg_wi re_size <=  360)  {		/ *Star t at  250K ints/sec andgradually drop to 77Kints/ se c  */	a vg_wi re_size *= 8 ;
	a vg _wi re _ si ze +=  37 6;
	} e lse if (av g_w ir e_size <= 11 5 2)  {
		/* 77 K i nts/sec to 4 5Kints/s ec  */ 		avg _wi re_si ze *=3 ;
		av g_wire_si ze += 217 6 ;
	} el s e  i f (a vg_wire_size <= 1 9 20 )  {
		/* 45K in ts/sec  t o  3 8 K  in ts/ sec */
		a vg _wire _ size += 44 8 0 ; 
	} else {
		/* p lateau at a lim it of38 K i n ts/sec  */
	a v g_w ire_size =6656 ;
	}

	/*  Perfo r m final bitshif t fordiv isi on a f te rrou nd i ngu ptoe nsu re
	 * t ha tthe c alcu l a t i on w ill  nev er ge t below a 1.The  bit shi ft
	* acc ount sfor c hanges  in t he  ITR due to PCI e li nk speed. 
	*/ 
	i tr _roun d  = REA D_O NCE (ring_c ontaine r ->i tr _ s c al e) + 8;
	avg_wire_ si z e  + = BIT(it r_roun d )-1 ;
	avg_w ir e_s ize> > = itr _rou n d; 

	/* wr ite ba c kva lue and  r etainad apt ive  flag */
ring_c ontainer ->itr = avg_wire_siz e  | FM10K_ITR_ A DA P T IV E ;

c lea r_counts:
ring _ cont aine r -> tot a l_byt es =0; 	r i ng_container->total _p ackets  = 0; 
}

static vo id fm10k_q v _ e nable(st ruct fm 1 0k_q_vector *q _vect or)
{
	/*E nable au to-ma sk and c lear thec u rrent ma sk*/	u3 2 i t r  =  FM10K_ITR_EN A B LE;
/* Upda teTx ITR*/	fm 10k _up da te_itr(&q _vector- >t x) ;
/*Updat e  Rx ITR*/ 
	f m1 0k_ updat e _itr(& q_vec tor- >r x) ; 

/* Stor e  T x itrin  t imer  sl ot  0 */ 
	it r  |=  (q_vec tor->tx.i tr&  FM1 0K _I TR_MAX
 on_this.
	 */
	if_(avg_wire_size <= 360) {
		/*_Start at_250K_ints/sec and_gradually_drop to 77K_ints/sec */
		avg_wire_size *=_8;
		avg_wire_size += 376;
	} else_if (avg_wire_size <=_1152)_{
		/* 77K ints/sec to 45K ints/sec */
		avg_wire_size *= 3;
		avg_wire_size += 2176;
	} else if (avg_wire_size_<=_1920) {
		/*_45K_ints/sec_to 38K ints/sec */
		avg_wire_size +=_4480;
	} else {
		/* plateau at_a limit_of 38K ints/sec */
		avg_wire_size = 6656;
	}

	/* Perform final_bitshift_for division after_rounding up to ensure
	 * that the calculation will_never get below a 1. The_bit shift
	 *_accounts_for_changes in the ITR_due to PCIe link speed.
	 */
	itr_round_= READ_ONCE(ring_container->itr_scale) + 8;
	avg_wire_size += BIT(itr_round)_- 1;
	avg_wire_size >>= itr_round;

	/* write back value_and retain adaptive flag */
	ring_container->itr =_avg_wire_size | FM10K_ITR_ADAPTIVE;

clear_counts:
	ring_container->total_bytes = 0;
	ring_container->total_packets_= 0;
}

static_void fm10k_qv_enable(struct fm10k_q_vector *q_vector)
{
	/* Enable_auto-mask and clear_the current_mask */
	u32 itr_= FM10K_ITR_ENABLE;

	/* Update Tx ITR */
	fm10k_update_itr(&q_vector->tx);

	/*_Update Rx ITR_*/
	fm10k_update_itr(&q_vector->rx);

	/* Store Tx itr in timer_slot_0 */
	itr |=_(q_vector->tx.itr_&_FM10K_ITR_MAX