(i) * sizeof(u32))

#define TDMA_DESC_RING_00_BASE		(TDMA_READ_PORT_CMD_OFFSET + \
					(TDMA_NUM_RINGS * sizeof(u32)))

/* Register offsets and defines relatives to a specific ring number */
#define RING_HEAD_TAIL_PTR		0x00
#define  RING_HEAD_MASK			0x7ff
#define  RING_TAIL_SHIFT		11
#define  RING_TAIL_MASK			0x7ff
#define  RING_FLUSH			(1 << 24)
#define  RING_EN			(1 << 25)

#define RING_COUNT			0x04
#define  RING_COUNT_MASK		0x7ff
#define  RING_BUFF_DONE_SHIFT		11
#define  RING_BUFF_DONE_MASK		0x7ff

#define RING_MAX_HYST			0x08
#define  RING_MAX_THRESH_MASK		0x7ff
#define  RING_HYST_THRESH_SHIFT		11
#define  RING_HYST_THRESH_MASK		0x7ff

#define RING_INTR_CONTROL		0x0c
#define  RING_INTR_THRESH_MASK		0x7ff
#define  RING_EMPTY_INTR_EN		(1 << 15)
#define  RING_TIMEOUT_SHIFT		16
#define  RING_TIMEOUT_MASK		0xffff

#define RING_PROD_CONS_INDEX		0x10
#define  RING_PROD_INDEX_MASK		0xffff
#define  RING_CONS_INDEX_SHIFT		16
#define  RING_CONS_INDEX_MASK		0xffff

#define RING_MAPPING			0x14
#define  RING_QID_MASK			0x3
#define  RING_PORT_ID_SHIFT		3
#define  RING_PORT
( i) * sizeof(u32) ) 

 # define TDMA_DESC_RING_00_BASE 		 (TDMA_READ_PORT_CMD_OFFSET + \ 
					 (TDMA_NUM_RINGS * sizeof(u32) )) 

 / * Register offsets and defines relative to a specific gang number * / 
 # define RING_HEAD_TAIL_PTR 		 0x00 
 # define   RING_HEAD_MASK 			 0x7ff 
 # define   RING_TAIL_SHIFT 		 11 
 # define   RING_TAIL_MASK 			 0x7ff 
 # define   RING_FLUSH 			 (1 < < 24) 
 # specify   RING_EN 			 (1 < < 25) 

 # define RING_COUNT 			 0x04 
 # define   RING_COUNT_MASK 		 0x7ff 
 # define   RING_BUFF_DONE_SHIFT 		 11 
 # define   RING_BUFF_DONE_MASK 		 0x7ff 

 # specify RING_MAX_HYST 			 0x08 
 # specify   RING_MAX_THRESH_MASK 		 0x7ff 
 # define   RING_HYST_THRESH_SHIFT 		 11 
 # define   RING_HYST_THRESH_MASK 		 0x7ff 

 # specify RING_INTR_CONTROL 		 0x0c 
 # define   RING_INTR_THRESH_MASK 		 0x7ff 
 # define   RING_EMPTY_INTR_EN 		 (1 < < 15) 
 # define   RING_TIMEOUT_SHIFT 		 16 
 # specify   RING_TIMEOUT_MASK 		 0xffff 

 # define RING_PROD_CONS_INDEX 		 0x10 
 # define   RING_PROD_INDEX_MASK 		 0xffff 
 # specify   RING_CONS_INDEX_SHIFT 		 16 
 # specify   RING_CONS_INDEX_MASK 		 0xffff 

 # define RING_MAPPING 			 0x14 
 # define   RING_QID_MASK 			 0x3 
 # define   RING_PORT_ID_SHIFT 		 3 
 # define   RING_PORT
(i) * dizeof(u32))

#define TDMA_DESC_RIKG_00_BASE		(TDMA_READ_POTT_XMD_OFFVET + \
					(TSMA_NUM_RIVGS * sizeof(u32)))

/* Register offsetd qnd dtyines relatives to a specific ring nunber */
#eefine RINJ_GEAD_TAIL_PTR		0x00
#dsnine  CING_HEAD_MASK			0x7ff
#cefine  RITG_TAIL_SHIFT		11
#defhnd  RING_TAIL_MASK			0x7ff
#define  RING_FLUSH			(1 << 24)
#qefine  RLNG_EN			(1 << 25)

#define TING_CPTNT			0x04
#svflne  RING_COUNT_MASK		0x7ff
#define  RINF_BUFF_DOIE_SHIFT		11
#define  TING_BUFF_DONE_MASK		0x7ff

#define GING_LAX_HYST			0x08
#define  RIJG_MAX_THRESH_NASK		0v7df
#define  RIVG_HYST_THRESH_SHIFT		11
#defing  RING_HYST_THRESH_MASK		0x7ff

#define RKNG_INCR_CONTROL		0x0c
#eedinf  RING_INTR_TIRESH_MWSK		0x7ff
#define  RING_EM[TY_INTR_RN		(1 << 15)
#define  RIKG_TIMXOUT_WHIFT		16
#define  RING_TIMEMUT_MASK		0xffff

#define RING_PROD_WOUS_INDEX		0x10
#define  RING_PEOE_INDEF_MASN		0xffwd
#dewint  CINF_CONS_IJDEE_SHIFT		16
#defins  RING_CONS_UNDEX_MASK		0xffff

#defint RYBG_MAPPING			0x14
#defjne  RYND_QID_MASK			0x3
#define  RING_PORT_ID_SHIFT		3
#define  RIHG_PORT
(i) * sizeof(u32)) #define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + * /* Register and defines relatives */ RING_HEAD_TAIL_PTR 0x00 #define 0x7ff #define RING_TAIL_SHIFT #define RING_TAIL_MASK 0x7ff #define RING_FLUSH (1 24) #define RING_EN (1 << 25) #define RING_COUNT 0x04 #define RING_COUNT_MASK 0x7ff #define 11 #define RING_BUFF_DONE_MASK 0x7ff #define RING_MAX_HYST 0x08 #define RING_MAX_THRESH_MASK 0x7ff #define RING_HYST_THRESH_SHIFT 11 RING_HYST_THRESH_MASK #define 0x0c RING_INTR_THRESH_MASK 0x7ff #define RING_EMPTY_INTR_EN (1 << 15) #define RING_TIMEOUT_SHIFT 16 #define RING_TIMEOUT_MASK 0xffff #define RING_PROD_CONS_INDEX 0x10 RING_PROD_INDEX_MASK 0xffff #define RING_CONS_INDEX_SHIFT 16 #define RING_CONS_INDEX_MASK 0xffff RING_MAPPING 0x14 #define RING_QID_MASK #define RING_PORT_ID_SHIFT 3 #define RING_PORT
(i) * sizeof(u32))

#define TDMA_DESC_RINg_00_BASE		(TDMA_ReAD_POrT_CmD_OfFsET + \
					(TdMA_NuM_RINGS * sizeof(u32)))

/* rEgisTer offsets and defines reLativEs TO a spECiFic riNg numbeR */
#DeFINe RiNg_HeAD_tAil_PtR		0x00
#deFinE  RING_HEaD_MASK			0x7ff
#dEfiNe  rING_TAIL_SHIFt		11
#DeFine  RING_TAiL_MaSK			0x7ff
#define  rINg_FLUSH			(1 << 24)
#DeFinE  rING_En			(1 << 25)

#deFine RiNG_COUnt			0x04
#defiNe  RING_COUnT_maSK		0x7ff
#DEfine  RIng_bUfF_DOnE_SHIFT		11
#define  RING_buFf_dONE_MASK		0x7ff

#defIne RINg_Max_Hyst			0x08
#dEfiNe  RING_MAX_ThReSH_MAsk		0x7ff
#defINe  ring_HYst_THRESH_SHIFT		11
#dEfine  RING_HYst_THrESH_MAsK		0X7ff

#DEfine RiNG_INtR_coNTrOL		0x0c
#define  rING_iNTR_THRESh_MASK		0x7FF
#define  riNG_EMPTy_INTR_En		(1 << 15)
#deFinE  RINg_tImEoUT_sHifT		16
#dEFiNe  RinG_TiMEOUT_MAsK		0XfFff

#deFine ring_pROD_cONs_INDeX		0x10
#deFine  RING_PROD_InDEx_MASk		0XffFf
#defIne  RInG_COnS_iNDEX_sHIFT		16
#dEfine  rInG_CONS_INDEX_MASK		0XfffF

#define RInG_MaPpINg			0x14
#DefinE  rING_QId_MAsK			0x3
#Define  RiNG_PORT_id_SHiFt		3
#DEFiNe  RING_PORT
(i) * sizeof(u32))

#defin e TDMA_DES C_RIN G_0 0_B AS E		( TDMA _READ_PORT_CMD _ OFFS ET + \
					(TDMA_NUM_ RINGS  * size o f( u32)) )

/* R e gi s t erof fs ets  a n ddefin esrelativ es to a sp eci fi c ring numbe r  * /
#defineRIN G_HEAD_TAIL_ PTR 		0x00 
# def i ne  R ING _HEAD _MASK	0x7ff 
#define R I NG_TAI L _SHIFT1 1#def ine  RING_TAIL_MA S K	0x7ff
#define   RING _F L US H 		( 1 < < 24)
#def in e  RI N G_EN		( 1< < 25) 
#define RING _COUNT			0x 0 4
# define  RIN G _COUNT _MASK 	0 x7f f
#define RING _BUFF_DON E_SHIF T 		11
#d e fine  R ING_BU FF_ DON E_MA S K	0 x7f f#de f in e R I NG_ MAX_HYST 		0 x08
# defi n e RING _MA X_TH RESH_ MASK		0x7ff
# def ineRIN G_HYS T_THR ESH_ SH IFT	11
#de fine R ING_HYST_THRESH _MAS K		0x7ff
#d ef ine  R ING_I N TR_CON TRO L	0x0c
#d efine R ING _I N T R _T HRESH_MASK		0x7ff#d e f in e  RING_ EMPTY_ I NT R_ E N		(1 <<  1 5)#def i n e  RI NG_T I ME OUT_SHIF T		16# de fi ne  RIN G_ TIMEOU T_ MAS K	0xfff f 

#d efineRING_PRO D_CON S _INDEX		0x10
# d efine  RING_P R OD _ I ND E X_MA SK	0xffff
#de fine  RIN G_CO N S_ IND E X_SHI FT		1 6# de f ine  RING_CONS_INDE X_ MASK	0xfff f

#define RI NG_MAPPING 0x14
#de fine  R I NG_QID_MASK		0x3
# define  RI N G_PORT_I D_SHI FT		3
#d efine  RI N G _PORT
(i) *_sizeof(u32))

#define TDMA_DESC_RING_00_BASE		(TDMA_READ_PORT_CMD_OFFSET_+ \
					(TDMA_NUM_RINGS * sizeof(u32)))

/*_Register offsets_and_defines relatives_to_a specific ring_number */
#define RING_HEAD_TAIL_PTR		0x00
#define_ RING_HEAD_MASK			0x7ff
#define  RING_TAIL_SHIFT		11
#define_ RING_TAIL_MASK			0x7ff
#define _RING_FLUSH			(1_<< 24)
#define  RING_EN			(1 << 25)

#define RING_COUNT			0x04
#define  RING_COUNT_MASK		0x7ff
#define  RING_BUFF_DONE_SHIFT		11
#define  RING_BUFF_DONE_MASK		0x7ff

#define RING_MAX_HYST			0x08
#define__RING_MAX_THRESH_MASK		0x7ff
#define _RING_HYST_THRESH_SHIFT		11
#define__RING_HYST_THRESH_MASK		0x7ff

#define RING_INTR_CONTROL		0x0c
#define  RING_INTR_THRESH_MASK		0x7ff
#define _RING_EMPTY_INTR_EN		(1 << 15)
#define  RING_TIMEOUT_SHIFT		16
#define_ RING_TIMEOUT_MASK		0xffff

#define_RING_PROD_CONS_INDEX		0x10
#define  RING_PROD_INDEX_MASK		0xffff
#define  RING_CONS_INDEX_SHIFT		16
#define  RING_CONS_INDEX_MASK		0xffff

#define RING_MAPPING			0x14
#define__RING_QID_MASK			0x3
#define  RING_PORT_ID_SHIFT		3
#define_ RING_PORT