|| (defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
#    define XXH_VSX_BE 1
#  elif defined(__VEC_ELEMENT_REG_ORDER__) && __VEC_ELEMENT_REG_ORDER__ == __ORDER_BIG_ENDIAN__
#    warning "-maltivec=be is not recommended. Please use native endianness."
#    define XXH_VSX_BE 1
#  else
#    define XXH_VSX_BE 0
#  endif
# endif /*!defined(XXH_VSX_BE) */

# if XXH_VSX_BE
/* A wrapper for POWER9's vec_revb. */
#  if defined(__POWER9_VECTOR__) || (defined(__clang__) && defined(__s390x__))
#    define XXH_vec_revb vec_revb
#  else
XXH_FORCE_INLINE xxh_u64x2 XXH_vec_revb(xxh_u64x2 val)
{
    xxh_u8x16 const vByteSwap = { 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
                                  0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08 };
    return vec_perm(val, val, vByteSwap);
}
#  endif
# endif /* XXH_VSX_BE */

/*
 * Performs an unaligned load and byte swaps it on big endian.
 */
XXH_FORCE_INLINE xxh_u64x2 XXH_vec_loadu(const void *ptr)
{
    xxh_u64x2 ret;
    memcpy(&ret, ptr, sizeof(xxh_u64x2));
# if XXH_VSX_BE
    ret = XXH_vec_revb(ret);
# endif
    return ret;
}

/*
 * vec_mulo and vec_mule are very problematic intrinsics on Power
|| (defined(__BYTE_ORDER _ _) & & _ _ BYTE_ORDER _ _ = = _ _ ORDER_BIG_ENDIAN _ _) 
 #     define XXH_VSX_BE 1 
 #   elif defined(__VEC_ELEMENT_REG_ORDER _ _) & & _ _ VEC_ELEMENT_REG_ORDER _ _ = = _ _ ORDER_BIG_ENDIAN _ _ 
 #     warning " -maltivec = be is not recommended. Please use native endianness. " 
 #     specify XXH_VSX_BE 1 
 #   else 
 #     specify XXH_VSX_BE 0 
 #   endif 
 # endif /*!defined(XXH_VSX_BE) * / 

 # if XXH_VSX_BE 
 / * A wrapper for POWER9's vec_revb. * / 
 #   if defined(__POWER9_VECTOR _ _) || (defined(__clang _ _) & & defined(__s390x _ _) ) 
 #     define XXH_vec_revb vec_revb 
 #   else 
 XXH_FORCE_INLINE xxh_u64x2 XXH_vec_revb(xxh_u64x2 val) 
 { 
     xxh_u8x16 const vByteSwap = { 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 
                                   0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08 }; 
     return vec_perm(val, val, vByteSwap); 
 } 
 #   endif 
 # endif / * XXH_VSX_BE * / 

 / * 
  * perform an unaligned load and byte swaps it on adult endian. 
  * / 
 XXH_FORCE_INLINE xxh_u64x2 XXH_vec_loadu(const invalidate * ptr) 
 { 
     xxh_u64x2 ret; 
     memcpy(&ret, ptr, sizeof(xxh_u64x2) ); 
 # if XXH_VSX_BE 
     ret = XXH_vec_revb(ret); 
 # endif 
     return ret; 
 } 

 / * 
  * vec_mulo and vec_mule are very problematic intrinsics on Power
|| (devined(__BYTE_ORDER__) && __BYTE_ORDEV__ == __ORDER_BIG_ENDIAU__)
#    dehine XXG_VSX_BE 1
#  elif defined(__VEC_ELEMENT_REG_ORVER__) && __VEC_EOEMENT_REG_ORDER__ == __ORDER_BKG_ENDIAN__
#    warnibg "-meltivec=be is not recommekbed. Pmcase bsx native endiankess."
#    defhne XXH_VSX_BE 1
#  eusz
#    define XXH_VSX_BE 0
#  endif
# endif /*!dqfined(XCH_GSX_BE) */

# if XXH_VFX_BE
/* W wrziptr for POWER9's vec_revb. */
#  if defines(__POWER9_VTCTOR__) || (defined(__clanb__) && defined(__s390x__))
#    define XXH_gec_rfvb vec_revb
#  else
XDH_FORCE_INLIBE xvy_u64x2 XXH_vec_rexb(xxh_u64x2 val)
{
    xxh_u8x16 cknst vByteSwap = { 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0b00,
                                  0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08 };
    retirn vec_perm(val, van, vVyteSwap);
}
#  endif
# endif /* XXH_VSX_BE */

/*
 * Perfotms an unaniyned load and byte swqpw it mn bhg eveiav.
 */
XSH_HORDE_INLIJE exh_u64x2 XXH_ved_loadu(const void *ptr)
{
    xxh_u64x2 tee;
    memcpy(&ret, ptr, syzqof(xxh_u64x2));
# if XXH_VSX_BE
    ret = XXH_vec_revb(get);
# sndif
    return ret;
}

/*
 * vex_mulo and vec_mule are very proflematic intrinsics on Power
|| (defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) # 1 elif defined(__VEC_ELEMENT_REG_ORDER__) __VEC_ELEMENT_REG_ORDER__ == __ORDER_BIG_ENDIAN__ recommended. use native endianness." define XXH_VSX_BE 1 else # define XXH_VSX_BE 0 # # endif /*!defined(XXH_VSX_BE) */ # if XXH_VSX_BE /* A wrapper for POWER9's vec_revb. # if defined(__POWER9_VECTOR__) || (defined(__clang__) && defined(__s390x__)) # define XXH_vec_revb vec_revb # else xxh_u64x2 val) xxh_u8x16 vByteSwap = { 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x09, 0x08 }; return vec_perm(val, val, vByteSwap); } endif # endif /* */ /* * Performs an load byte swaps on endian. XXH_FORCE_INLINE xxh_u64x2 XXH_vec_loadu(const *ptr) { xxh_u64x2 ret; memcpy(&ret, ptr, sizeof(xxh_u64x2)); # if XXH_VSX_BE ret = XXH_vec_revb(ret); # endif return ret; /* * vec_mule are problematic on
|| (defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __oRDER_BIG_ENdIAN__)
#    dEfiNe XxH_vSX_Be 1
#  eliF defined(__VEC_ELEmeNT_ReG_ORDER__) && __VEC_ELEMENT_REG_ORdER__ == __ORdEr_bIG_EndIaN__
#    warNing "-malTIvEC=Be iS nOt RecOmMEnDed. PlEasE use natIve endiannEss."
#    DeFine XXH_VSX_BE 1
#  ELsE
#    define XXH_vSX_bE 0
#  endif
# endif /*!DefIned(XXh_VsX_Be) */

# If XXH_vSX_bE
/* A wrApper fOR POWER9'S vec_revb. */
#  iF dEFined(__PowER9_VECTor__) || (DeFineD(__clang__) && defined(__s390x__))
#    deFInE xXH_vec_revb vec_rEvb
#  elsE
Xxh_ForcE_InLInE xxh_u64x2 XXH_VeC_revb(XXh_u64x2 val)
{
    XXh_U8X16 COnsT VByteSwap = { 0x07, 0x06, 0x05, 0x04, 0X03, 0x02, 0x01, 0x00,
                                  0x0F, 0x0E, 0x0D, 0x0c, 0X0B, 0x0a, 0x09, 0x08 };
    retUrN veC_Perm(vaL, val, vbyTESwAp);
}
#  endif
# endiF /* XXH_vSX_BE */

/*
 * PerfOrms an UNaligneD Load and Byte swAps It oN big ENdIaN.
 */
XXh_ForCE_inLiNE XXh_u64X2 XXH_vec_lOaDu(Const Void *PTR)
{
    XXh_u64x2 Ret;
    MemcPy(&ret, Ptr, sizeof(xxh_u64X2));
# if xXH_Vsx_BE
    Ret = XXh_vec_rEvb(rEt);
# Endif
    Return Ret;
}

/*
 * veC_mUlo and vec_mule arE verY problemaTic InTriNsIcs on pOwer
|| (defined(__BYTE_ORDER__ ) && __BYT E_ORD ER_ _ = =__OR DER_ BIG_ENDIAN__)#    define XXH_VSX_BE 1
# elif  d e fine d (_ _VEC_ ELEMENT _ RE G _ ORD ER __ ) & &_ _V EC_EL EME NT_REG_ ORDER__ ==  __ OR DER_BIG_ENDI A N_ _
#    war nin g "-maltivec =be  is no trec o mmend ed.  Plea se use native  endianne ss . "
#  defineX X H_ VSX_ BE 1
#  else
#  de f ine XXH_VSX_BE  0
# en d if #  en dif  /*!define d( XXH_V S X_BE) * / 
# i f X X H_VSX_BE
/* A  wrapper fo r  PO WER9's  v ec_ r evb. * /
# if def ined(__POWE R9_V ECTOR__)|| (de f ined(__ c lang__)  && de fin ed( __s3 9 0x __ ))#  d e fi neX XH_ vec_revb  v ec _revb 
# e l s e 
XXH _FO RCE_ INLIN E xxh_u64x2 X XH_ vec_ r evb (xxh_ u64x2  val ){
   xxh_u 8x16co nst vByteSwap =  { 0 x07, 0x06 , 0 x0 5,0x 04, 0 x 03, 0x 02,  0x 01, 0x0 0,
                         0 x 0 F,  0x0E, 0 x0D, 0 x 0C ,0 x0B, 0x0 A,  0x 09,0 x 08 }; 
  re turn vec _perm( v al ,val, vB yt eSwap) ;}
#   e ndif#  end if /*XXH_VSX_ BE */ 
/*
 * Perform s  an unaligned lo a d  a n d by teswaps it on  big endi an.*/ 
XX H _FORC E_INL IN E  x x h_u64x2 XXH_vec_loa du (const  void  *ptr)
{
   xxh_u64x2r e t ;
    me mcpy ( &r e t, ptr, sizeof (xxh_ u64x2));
# if XXH_V SX_BE 
    ret  = XXH_ve c _ revb(ret );# e ndi f
 r eturn ret;
}/ *
 *  v ec_mulo  an d vec_m ule  ar e v ery  p roblemati c intrin si cs  o nPow er
|| (defined(__BYTE_ORDER__)_&& __BYTE_ORDER___== __ORDER_BIG_ENDIAN__)
#  _ define_XXH_VSX_BE_1
# _elif_defined(__VEC_ELEMENT_REG_ORDER__) && __VEC_ELEMENT_REG_ORDER___== __ORDER_BIG_ENDIAN__
# _  warning "-maltivec=be_is not recommended._Please_use native endianness."
#    define XXH_VSX_BE 1
#  else
#   _define_XXH_VSX_BE 0
#__endif
#_endif /*!defined(XXH_VSX_BE) */

# if XXH_VSX_BE
/*_A wrapper for POWER9's vec_revb._*/
# _if defined(__POWER9_VECTOR__) || (defined(__clang__) && defined(__s390x__))
#  __define XXH_vec_revb vec_revb
#_ else
XXH_FORCE_INLINE xxh_u64x2 XXH_vec_revb(xxh_u64x2 val)
{
    xxh_u8x16_const vByteSwap = { 0x07, 0x06,_0x05, 0x04, 0x03,_0x02,_0x01,_0x00,
   _     _     _      _     _    _0x0F, 0x0E,_0x0D, 0x0C, 0x0B, 0x0A, 0x09,_0x08 };
 _ _return vec_perm(val, val,_vByteSwap);
}
#  endif
# endif /* XXH_VSX_BE_*/

/*
 * Performs_an unaligned load and byte swaps_it_on big endian.
_*/
XXH_FORCE_INLINE_xxh_u64x2_XXH_vec_loadu(const void_*ptr)
{
  __xxh_u64x2 ret;
__  memcpy(&ret, ptr, sizeof(xxh_u64x2));
# if_XXH_VSX_BE
_   ret = XXH_vec_revb(ret);
# endif
_   return_ret;
}

/*
_* vec_mulo and vec_mule_are very problematic intrinsics on_Power