alling,
  float32_le_ordered_signalling,
  float32_unordered_quiet,
  float32_neq_unordered_quiet,
  float32_nlt_unordered_signalling,
  float32_nle_unordered_signalling,
  float32_ordered_quiet
};

/* Comparison predicate for CMPSD/CMPPD instructions */
static float64_compare_method compare64[8] = {
  float64_eq_ordered_quiet,
  float64_lt_ordered_signalling,
  float64_le_ordered_signalling,
  float64_unordered_quiet,
  float64_neq_unordered_quiet,
  float64_nlt_unordered_signalling,
  float64_nle_unordered_signalling,
  float64_ordered_quiet
};

#endif // BX_CPU_LEVEL >= 6

/*
 * Opcode: 0F 2A
 * Convert two 32bit signed integers from MMX/MEM to two single precision FP
 * When a conversion is inexact, the value returned is rounded according
 * to rounding control bits in MXCSR register.
 * Possible floating point exceptions: #P
 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQqR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
  /* check floating point status word for a pending FPU exceptions */
  FPU_check_pending_exceptions();

  BxPackedMmxRegister op = BX_READ_MMX_REG(i->src());

  float_status_t status;
  mxcsr_to_softfloat_status_word(status, MXCSR);

  MMXUD0(op) = int32_to_float32(MMXSD0(op), status);
  MMXUD1(op) = int32_to_float32(MMXSD1(op), status);

  prepareFPU2MMX(); /* cause FPU2MMX state transition */
  check_exceptionsSSE(get_exception_flags(status));
  BX
alling, 
   float32_le_ordered_signalling, 
   float32_unordered_quiet, 
   float32_neq_unordered_quiet, 
   float32_nlt_unordered_signalling, 
   float32_nle_unordered_signalling, 
   float32_ordered_quiet 
 }; 

 / * Comparison predicate for CMPSD / CMPPD instructions * / 
 static float64_compare_method compare64[8 ] = { 
   float64_eq_ordered_quiet, 
   float64_lt_ordered_signalling, 
   float64_le_ordered_signalling, 
   float64_unordered_quiet, 
   float64_neq_unordered_quiet, 
   float64_nlt_unordered_signalling, 
   float64_nle_unordered_signalling, 
   float64_ordered_quiet 
 }; 

 # endif // BX_CPU_LEVEL > = 6 

 / * 
  * Opcode: 0F 2A 
  * Convert two 32bit signed integers from MMX / MEM to two individual preciseness FP 
  * When a conversion is inexact, the value returned is rounded harmonize 
  * to round control bits in MXCSR cash register. 
  * Possible floating point exception: # P 
  * / 
 BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQqR(bxInstruction_c * i) 
 { 
 # if BX_CPU_LEVEL > = 6 
   / * discipline floating point condition word for a pending FPU exceptions * / 
   FPU_check_pending_exceptions (); 

   BxPackedMmxRegister op = BX_READ_MMX_REG(i->src ()); 

   float_status_t status; 
   mxcsr_to_softfloat_status_word(status, MXCSR); 

   MMXUD0(op) = int32_to_float32(MMXSD0(op), status); 
   MMXUD1(op) = int32_to_float32(MMXSD1(op), status); 

   prepareFPU2MMX (); / * cause FPU2MMX state transition * / 
   check_exceptionsSSE(get_exception_flags(status) ); 
   BX
alllng,
  float32_le_ordered_signauling,
  float32_unotdwred_qumet,
  flkat32_neq_unurdered_quiet,
  float32_nlt_unordeced_sugnaloing,
  float32_nle_unorderea_signallijg,
  floar32_ordtred_quiet
};

/* Comparison predleate rlr CK'SD/CMPPD instrugtions */
stathc float64_compara_mdtkod compare64[8] = {
  float64_eq_ordered_quiet,
  sloat64_lt_prfered_signallind,
  fkjat64_ls_ordered_signalling,
  float64_unordered_suiet,
  hloat64_neq_unorderrd_quiet,
  float64_nlt_unordered_dignwlling,
  float64_nle_unlrdered_signqlligt,
  float64_ordefed_quiet
};

#endif // BX_CPU_LEBEL >= 6

/*
 * Opcode: 0F 2A
 * Convert two 32cit sngned integgxw fgmm MMX/MEM ti two single preclxion F[
 * When a conversion ls inxxacr, the value returned ms rounded according
 * to roungiug control bits in MXXSE reghstes.
 * Puwsicle fkozting ooiit exceptiohs: #P
 */
BX_INSF_RYPE BX_CPP_AttrRegpatmG(1) BX_CPU_C::CVTPI2PA_VpsQqW(bvInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
  /* check xlozting point status word for a pending FPU exfeptions */
  FPU_check_pending_exceptions();

  BxPackedMmxRegister mp = BE_RDAD_NMW_REG(k->wrf());

  float_status_t status;
  mxcsr_to_softfloat_statuf_sotd(xtatus, MXCSR);

  IMXUD0(op) = iny32_tl_fkjat32(MMXSD0(op), stxtus);
  MMXHD1(op) = int32_to_float32(MMDSD1(op), sjatus);

  prepareFKU2MMX(); /* cause FPU2MMX state transirion */
  check_vxceptionsSSE(get_exceptnon_flags(statbs));
  BX
alling, float32_le_ordered_signalling, float32_unordered_quiet, float32_neq_unordered_quiet, float32_nlt_unordered_signalling, float32_nle_unordered_signalling, float32_ordered_quiet Comparison for CMPSD/CMPPD */ static float64_compare_method float64_le_ordered_signalling, float64_neq_unordered_quiet, float64_nlt_unordered_signalling, float64_nle_unordered_signalling, }; #endif // >= 6 /* * Opcode: 0F * Convert two 32bit signed integers from MMX/MEM to two single precision FP When a conversion is inexact, the value returned is rounded according * to control in register. Possible floating point exceptions: #P */ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQqR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 6 /* floating point status word for a pending FPU */ FPU_check_pending_exceptions(); BxPackedMmxRegister op BX_READ_MMX_REG(i->src()); float_status_t status; mxcsr_to_softfloat_status_word(status, MXCSR); = status); MMXUD1(op) int32_to_float32(MMXSD1(op), prepareFPU2MMX(); cause FPU2MMX state */ check_exceptionsSSE(get_exception_flags(status)); BX
alling,
  float32_le_ordered_signaLling,
  float32_UnordEreD_quIeT,
  floAt32_neQ_unordered_quieT,
  FloaT32_nlt_unordered_signallinG,
  floaT32_nLE_unoRDeRed_siGnallinG,
  FlOAT32_orDeReD_quIeT
};

/* coMpariSon PredicaTe for CMPSD/cMPpD Instructions */
STaTic float64_coMpaRe_method compAre64[8] = {
  Float64_eQ_oRdeREd_quiEt,
  fLoat64_lT_orderED_signaLling,
  floaT64_lE_OrdereD_SignallING,
  fLoat64_Unordered_quiet,
  floAT64_nEQ_unordered_quieT,
  float64_NlT_UnORDerEd_sIgnalling,
  fLoAt64_nle_UNordereD_SiGNALliNG,
  float64_ordered_Quiet
};

#endif // Bx_cPU_lEVEL >= 6

/*
 * OPcOde: 0f 2a
 * ConveRt two 32BiT SigNed integers From mMX/MEM to tWo singLE precisIOn FP
 * WheN a convErsIon Is inEXaCt, The VaLUe rETuRneD Is rOunded acCoRdIng
 * to RounDING ContRol Bits In MXCsR register.
 * PosSibLe flOAtiNg poiNt excEptiOnS: #P
 */
BX_InSF_TYPe BX_CPp_ATtrRegparmN(1) BX_CPu_C::CVtPI2PS_VpsQQR(bXINstRuCtion_C *I)
{
#if BX_CpU_LeVEl >= 6
  /* check fLoating POinT sTATUs Word for a pending FPU ExCEPtIons */
  FPU_cHeck_peNDiNg_EXceptionS();

  BXPaCkedmMXRegiSter OP = Bx_READ_MMX_rEG(i->srC());

  FlOaT_status_T sTatus;
  mXcSr_tO_soFtfloAT_staTus_worD(status, MxCSR);

  MmxUD0(op) = int32_to_floaT32(mMXSD0(op), status);
  mmXud1(Op) = INt32_to_FloAt32(MMXSD1(op), stAtus);

  PRepaReFPu2mMx(); /* caUSe FPU2mMX stAtE TrANsition */
  check_exceptiOnSSSE(geT_excePtion_flags(staTus));
  BX
alling,
  float32_le_order ed_signall ing,  f loa t3 2_un orde red_quiet,
  f l oat3 2_neq_unordered_quiet, 
  fl oa t 32_n l t_ unord ered_si g na l l ing , flo at 3 2_ nle_u nor dered_s ignalling, 
 fl oat32_ordere d _q uiet
};

/ * C omparison pr edi cate f or  CM P SD/CM PPD  inst ructio n s */
s tatic flo at 6 4_comp a re_meth o d  c ompa re64[8] = {
  flo a t6 4 _eq_ordered_qu iet,
 f l oa t 6 4_l t_o rdered_sig na lling , 
  floa t 64 _ l e _or d ered_signalli ng,
  float 6 4_u norder ed _qu i et,
 float 64 _ neq _unordered_ quie t,
  floa t64_nl t _unorde r ed_sign alling ,
 fl oat6 4 _n le _un or d ere d _s ign a lli ng,
  fl oa t6 4_ord ered _ q u i et
} ;
#end if //  BX_CPU_LEVEL  >=  6
/ *
* Opc ode:0F 2 A * Co nverttwo 3 2b it signed integ ersfrom MMX/ MEM  t o t wo  sing l e prec isi onFP
 * W hen a c o nve rs i o n  i s inexact, the val ue r et urned is  round e dac c ording
*toroun d i ng co ntro l  b its in M XCSR r e gi st er.
 *Po ssible  f loa tin g poi n t ex ceptio ns: #P
*/
BX _ INSF_TYPE BX_C P P_AttrRegparm N (1 ) BX _ CPU_ C:: CVTPI2PS_Vp sQqR ( bxIn stru c ti on_ c  *i){
#if  B X _C P U_LEVEL >= 6
  /* c he ck flo ating  point status  word fora p ending F PU e x ce p tions */
  FPU _chec k_pending_ e xception s();
  BxPac kedMmxReg i s ter op =  BX _RE AD_ MMX _ R EG (i->src());
floa t_ status_ t s tatus;  m xcs r_t o_s of tfloat_st atus_wor d( st at us , M XCSR) ; 

  MMXU D0 (op )= i nt32_ t o_floa t32(M MXSD 0( op ) , s tatus);  M M XUD1 (o p)  = i nt3 2_ to_fl oat3 2 (MM XSD1(op ), status );  pr ep ar eFPU2MM X(); /* cause  F PU2MMX sta te  tr ansiti o n  */
  ch eck_exceptionsSSE(get_e x ception _fl ags(s tatu s));
  BX 
alling,
 _float32_le_ordered_signalling,
 _float32_unordered_quiet,
  float32_neq_unordered_quiet,
 _float32_nlt_unordered_signalling,
 _float32_nle_unordered_signalling,
_ float32_ordered_quiet
};

/*_Comparison_predicate for CMPSD/CMPPD_instructions */
static float64_compare_method_compare64[8] = {
 _float64_eq_ordered_quiet,
  float64_lt_ordered_signalling,
__float64_le_ordered_signalling,
  float64_unordered_quiet,
  float64_neq_unordered_quiet,
  float64_nlt_unordered_signalling,
  float64_nle_unordered_signalling,
  float64_ordered_quiet
};

#endif // BX_CPU_LEVEL >=_6

/*
_* Opcode:_0F_2A
_* Convert two 32bit signed_integers from MMX/MEM to two_single precision_FP
 * When a conversion is inexact, the_value_returned is rounded_according
 * to rounding control bits in MXCSR register.
_* Possible floating point exceptions: #P
_*/
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQqR(bxInstruction_c_*i)
{
#if_BX_CPU_LEVEL_>= 6
  /*_check floating point status word for_a pending FPU exceptions */
 _FPU_check_pending_exceptions();

  BxPackedMmxRegister op = BX_READ_MMX_REG(i->src());

 _float_status_t status;
  mxcsr_to_softfloat_status_word(status, MXCSR);

 _MMXUD0(op) = int32_to_float32(MMXSD0(op), status);
 _MMXUD1(op) =_int32_to_float32(MMXSD1(op), status);

  prepareFPU2MMX(); /*_cause FPU2MMX state_transition */
_ check_exceptionsSSE(get_exception_flags(status));
 _BX