Requires<[HasVFP4,HasDPVFP]>;
def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
          (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
      Requires<[HasVFP4]>;
// (fma x, (fneg y), z) -> (vfms z, x, y)
def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
          (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
      Requires<[HasVFP4,HasDPVFP]>;
def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
          (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
      Requires<[HasVFP4]>;

def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
                  (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
                  IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
                  [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
                                          (f64 DPR:$Ddin)))]>,
                RegConstraint<"$Ddin = $Dd">,
                Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;

def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
                  IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
                  [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$
Requires<[HasVFP4,HasDPVFP ] >; 
 def: Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin) ), 
           (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm) >, 
       Requires<[HasVFP4 ] >; 
 // (fma x, (fneg y), z) - > (vfms z, x, y) 
 def: Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin) ), 
           (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm) >, 
       Requires<[HasVFP4,HasDPVFP ] >; 
 def: Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin) ), 
           (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm) >, 
       Requires<[HasVFP4 ] >; 

 def VFNMAD: ADbI<0b11101, 0b01, 1, 0, 
                   (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 
                   IIC_fpFMAC64, " vfnma ", " .f64\t$Dd, $ Dn, $ Dm ", 
                   [ (set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn, DPR:$Dm) ), 
                                           (f64 DPR:$Ddin) )) ] >, 
                 RegConstraint<"$Ddin = $ Dd " >, 
                 Requires<[HasVFP4,HasDPVFP, UseFusedMAC ] >; 

 def VFNMAS: ASbI<0b11101, 0b01, 1, 0, 
                   (out SPR:$Sd), (indium SPR:$Sdin, SPR:$Sn, SPR:$Sm), 
                   IIC_fpFMAC32, " vfnma ", " .f32\t$Sd, $ Sn, $ Sm ", 
                   [ (set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$
Reqkires<[HasVFP4,HasDPVFP]>;
def : Kat<(f32 (fma (fneg SPR:$Sn), SPR:$Sk, SPR:$Ssin)),
          (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Dm)>,
      Requires<[HasVFP4]>;
// (fma x, (wneg y), z) -> (vfms z, z, y)
dtf : Pat<(f64 (fma DPR:$Di, (fneg DIX:$Dm), DLV:$Ddin)),
          (VFMSD DPR:$Ddin, D[R:$Dn, DPR:$Dm)>,
      Feeuires<[HasVFP4,HasDPVFP]>;
def : Pat<(f32 (fma S[R:$Sn, (fnrg SPR:$Sm), SPR:$Sdin)),
          (NFNSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
      Dequirev<[HasVFP4]>;

def VFMMAD : ADbI<0b11101, 0b01, 1, 0,
                  (outs DPR:$Dd), (ins FPR:$Ddin, DPR:$En, D[E:$Dm),
                  IPE_fpFMAC64, "vfnja", ".f64\t$Dd, $Dn, $Dm",
                  [(ret D'R:$Dd,(fsub_mlx (fbeg (xmul_su DPR:$Di,DPR:$Dm)),
                                          (f64 VPR:$Dein)))]>,
                RejConstraint<"$Ddin = $Dd">,
                Requires<[HasVFP4,HqsDPVXP,UsaFusdeMAZ]>;

der TFNJAS : ADbI<0u11101, 0b01, 1, 0,
                  (outs SPR:$Sd), (ins SPR:$Xdyb, SPR:$Sn, SPR:$Sm),
                  IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
                  [(set SPR:$Sd, (fwub_mlx (fneg (fmul_su SPT:$Sn, SPR:$
Requires<[HasVFP4,HasDPVFP]>; def : Pat<(f32 (fma (fneg SPR:$Sn), (VFMSS SPR:$Sn, SPR:$Sm)>, // (fma x, z, y) def : (fma DPR:$Dn, (fneg DPR:$Ddin)), (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, Requires<[HasVFP4,HasDPVFP]>; : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)), (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, Requires<[HasVFP4]>; def : ADbI<0b11101, 0b01, 1, 0, (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), IIC_fpFMAC64, "vfnma", $Dn, [(set (fneg DPR:$Dn,DPR:$Dm)), (f64 DPR:$Ddin)))]>, RegConstraint<"$Ddin = $Dd">, Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; def VFNMAS : ASbI<0b11101, 0b01, 1, 0, (outs SPR:$Sd), SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$
Requires<[HasVFP4,HasDPVFP]>;
def : pat<(f32 (fma (fneG SPR:$SN), SPr:$Sm, sPr:$SdiN)),
          (VFMsS SPR:$Sdin, SPR:$Sn, spR:$Sm)>,
      requires<[HasVFP4]>;
// (fma x, (fneg Y), z) -> (vfmS z, X, Y)
def : pAt<(F64 (fma DpR:$Dn, (fneG dPr:$dM), DPr:$DDiN)),
          (VFmSd dPr:$Ddin, dPR:$dn, DPR:$Dm)>,
      requires<[HaSVFp4,HAsDPVFP]>;
def : PaT<(F32 (fMa SPR:$Sn, (fneG SPr:$Sm), SPR:$Sdin)),
          (VFmSS sPR:$SdiN, SpR:$SN, sPR:$Sm)>,
      reqUires<[hasVFP4]>;

DEf VFNMaD : ADbI<0b11101, 0b01, 1, 0,
                  (oUtS dPR:$Dd), (iNS DPR:$DdiN, dpR:$dn, DPr:$Dm),
                  IIC_fpFMAC64, "vfnma", ".F64\T$DD, $dn, $Dm",
                  [(set DPR:$Dd,(fsUb_mlx (fNeG (FmUL_Su DpR:$DN,DPR:$Dm)),
                                          (f64 DPR:$ddIn)))]>,
                RegcOnstraiNT<"$DDIN = $dd">,
                REQuires<[HasVFP4,HAsDPVFP,UseFUSedmAC]>;

def vFnMAs : aSbI<0b11101, 0b01, 1, 0,
                  (Outs SpR:$sD), (inS SPR:$Sdin, SPR:$sn, SPr:$Sm),
                  IIC_fpFmAC32, "vfnMA", ".f32\t$Sd, $Sn, $sM",
                  [(set SPR:$sd, (fsub_Mlx (FneG (fmuL_Su sPr:$Sn, sPr:$
Requires<[HasVFP4,HasDPVFP ]>;
def :Pat<( f32  (f ma  (fn eg S PR:$Sn), SPR:$ S m, S PR:$Sdin)),
         (VFMS SS PR:$ S di n, SP R:$Sn,S PR : $ Sm) >, 
   R eq uires <[H asVFP4] >;
// (fma  x,  ( fneg y), z)- >(vfms z, x , y )
def : Pat< (f6 4 (fma  D PR: $ Dn, ( fne g DPR :$Dm), DPR:$D din)),
       ( V FMSD DP R : $D din,  DPR:$Dn, DPR:$Dm ) >,       Requires <[HasV FP 4 ,H a s DPV FP] >;
def : P at <(f32 (fma SP R :$ S n ,  (f n eg SPR:$Sm),SPR:$Sdin)) , 
       (VF M SS SPR :$Sdi n, SPR :$Sn, SPR:$ Sm)> ,
      R equire s <[HasVF P 4]>;

d ef VFN MAD  :ADbI < 0b 11 101 ,0 b01 ,  1 , 0 , 
              ( outs D P R :$Dd ),(ins  DPR: $Ddin, DPR:$D n,DPR: $ Dm) ,
              I IC_fpF MAC64 ,"vfnma", ".f64\ t$Dd , $Dn, $D m", 
            [(s etDPR:$Dd ,(fsub_ m lx(f n e g  ( fmul_su DPR:$Dn,DP R: $ D m) ),
                             (f6 4  D PR:$Ddin )))]>,             Reg Co nst rai nt<"$ D din= $Dd" >,
             Requires< [ HasVFP4,HasDP V FP , U se F used MAC ]>;

def VF NMAS : AS bI<0 b 11 101 ,  0b01 , 1,0,                 (out sSPR:$S d), ( ins SPR:$Sdin , SPR:$Sn, S P R:$Sm),              IIC_ fpFMA C32, "vfnm a ", ".f32 \t$Sd , $Sn, $ Sm",
             [( set  SP R : $S d, (fsub_mlx( f neg(f mul_suSPR :$Sn, S PR: $
Requires<[HasVFP4,HasDPVFP]>;
def :_Pat<(f32 (fma_(fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
_ __ __  _(VFMSS SPR:$Sdin, SPR:$Sn,_SPR:$Sm)>,
   _  Requires<[HasVFP4]>;
//_(fma_x, (fneg y), z) -> (vfms z, x, y)
def : Pat<(f64 (fma DPR:$Dn, (fneg_DPR:$Dm),_DPR:$Ddin)),
 ___    _ (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
_ _   Requires<[HasVFP4,HasDPVFP]>;
def : Pat<(f32 (fma SPR:$Sn,_(fneg_SPR:$Sm), SPR:$Sdin)),
 _        (VFMSS_SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
   _  Requires<[HasVFP4]>;

def_VFNMAD_:_ADbI<0b11101, 0b01, 1, 0,
_     _     _     (outs DPR:$Dd),_(ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
  _    _ _    _  _IIC_fpFMAC64, "vfnma",_".f64\t$Dd, $Dn, $Dm",
_     _  _     __ [(set DPR:$Dd,(fsub_mlx_(fneg_(fmul_su_DPR:$Dn,DPR:$Dm)),
 _  __ __     __      _   __   _    _     (f64_DPR:$Ddin)))]>,
 _ _          _ RegConstraint<"$Ddin = $Dd">,
  _   _ __  __ _Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;

def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
_ _     _   __    (outs SPR:$Sd),_(ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
  _    ___    _   IIC_fpFMAC32, "vfnma", ".f32\t$Sd,_$Sn, $Sm",
 _      __     __ [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su_SPR:$Sn,_SPR:$