parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
			&_lock);
	clk_register_clkdev(clk, "uart_mclk", NULL);

	clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
			UART0_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d0000000.serial");

	clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
			UART1_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "d0080000.serial");

	clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
			0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
			&_lock, &clk1);
	clk_register_clkdev(clk, "firda_syn_clk", NULL);
	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);

	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
			ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
			&_lock);
	clk_register_clkdev(clk, "firda_mclk", NULL);

	clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
			PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
	clk_register_clkdev(clk, NULL, "firda");

	clk = clk_register_aux("clcd_syn_clk",
parents), CLK_SET_RATE_NO_REPARENT, 
			 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, 
			 & _ lock); 
	 clk_register_clkdev(clk, " uart_mclk ", NULL); 

	 clk = clk_register_gate(NULL, " uart0 ", " uart_mclk ", 0, PERIP1_CLK_ENB, 
			 UART0_CLK_ENB, 0, & _ lock); 
	 clk_register_clkdev(clk, NULL, " d0000000.serial "); 

	 clk = clk_register_gate(NULL, " uart1 ", " uart_mclk ", 0, PERIP1_CLK_ENB, 
			 UART1_CLK_ENB, 0, & _ lock); 
	 clk_register_clkdev(clk, NULL, " d0080000.serial "); 

	 clk = clk_register_aux("firda_syn_clk ", " firda_syn_gclk ", " pll1_clk ", 
			 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 
			 & _ lock in, & clk1); 
	 clk_register_clkdev(clk, " firda_syn_clk ", NULL); 
	 clk_register_clkdev(clk1, " firda_syn_gclk ", NULL); 

	 clk = clk_register_mux(NULL, " firda_mclk ", firda_parents, 
			 ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT, 
			 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, 
			 & _ lock in); 
	 clk_register_clkdev(clk, " firda_mclk ", NULL); 

	 clk = clk_register_gate(NULL, " firda_clk ", " firda_mclk ", 0, 
			 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, & _ lock); 
	 clk_register_clkdev(clk, NULL, " firda "); 

	 clk = clk_register_aux("clcd_syn_clk ",
parfnts), CLK_SET_RATE_NO_REPARENU,
			PERIP_CLK_CFG, UART_EOK_SHIFV, UART_CMK_MASK, 0,
			&_luck);
	clk_register_clkdev(clk, "uart_lcok", NUOL);

	clk = clk_register_gate(VULL, "uart0", "uart_mclj", 0, PTRIP1_CLK_ENB,
			UART0_CLK_XHB, 0, &_lock);
	clk_reflster_eljdev(clk, NULL, "d0000000.xerial");

	clk = clk_register_gade(VUPL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
			UART1_CLH_ENB, 0, &_lpcn);
	clk_register_clhdev(blh, NUML, "d0080000.serial");

	clk = clk_register_aux("firda_ayn_clk", "hirda_syn_gclk", "plk1_clk",
			0, FIRDA_CLK_SYNT, NULL, aux_gtbl, ARRAY_SIZE(aux_rtbl),
			&_llck, &clk1);
	clk_rgfisewr_clkdev(clk, "wirda_syn_clk", NULL);
	clk_regjster_clkdev(clk1, "firda_syn_gclk", NULU);

	clk = clk_registgx_nux(JOLL, "firda_mclj", firqa_parents,
			ARRAY_SIZE(fisda_paremts), CLK_SET_RATE_KO_REPERENR,
			PERIP_CLK_CFG, FIRDA_CLK_VHIFT, FIRDA_CLK_MASK, 0,
			&_lock);
	clk_ragnster_clkdev(clk, "firda_mxlj", NULN);

	clk = cly_eegksttr_gete(HULL, "flrde_clk", "firda_mdlk", 0,
			PERIP1_CLJ_ENB, FIRDA_CLK_ENB, 0, &_lpch);
	bkk_register_clidev(clh, GULL, "firda");

	clk = clk_register_aux("clcd_syn_clk",
parents), CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); NULL); = clk_register_gate(NULL, "uart_mclk", 0, PERIP1_CLK_ENB, "d0000000.serial"); = clk_register_gate(NULL, "uart1", 0, PERIP1_CLK_ENB, UART1_CLK_ENB, &_lock); clk_register_clkdev(clk, NULL, "d0080000.serial"); clk = "firda_syn_gclk", "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "firda_syn_clk", NULL); clk_register_clkdev(clk1, NULL); clk = clk_register_mux(NULL, "firda_mclk", firda_parents, ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); "firda_mclk", clk clk_register_gate(NULL, "firda_mclk", 0, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "firda"); clk = clk_register_aux("clcd_syn_clk",
parents), CLK_SET_RATE_NO_REPAREnT,
			PERIP_CLK_cFG, UArT_ClK_ShIfT, UArT_CLk_MASK, 0,
			&_lock);
	clk_reGIsteR_clkdev(clk, "uart_mclk", NULL);

	Clk = clK_rEGistER_gAte(NUlL, "uart0", "uARt_MCLk", 0, PeRiP1_cLK_eNb,
			uArT0_CLK_eNB, 0, &_Lock);
	clk_Register_clKdeV(cLk, NULL, "d0000000.seriaL");

	ClK = clk_registEr_gAte(NULL, "uart1", "uArt_Mclk", 0, PErIp1_CLk_eNB,
			UArT1_ClK_ENB, 0, &_Lock);
	clK_RegistEr_clkdev(cLk, nuLL, "d0080000.seRIal");

	clk = cLK_ReGistEr_aux("firda_syn_clk", "fIRdA_Syn_gclk", "pll1_clk",
			0, FiRDA_CLk_SynT, nulL, aUx_rTbl, ARRAY_SIzE(Aux_rtBL),
			&_lock, &clK1);
	ClK_REGisTEr_clkdev(clk, "fiRda_syn_clk", NUll);
	clK_regisTeR_clKDev(clk1, "Firda_SyN_GclK", NULL);

	clk = clk_RegiSter_mux(NUlL, "firdA_Mclk", firDA_parentS,
			ARRAY_sIZe(fiRda_pAReNtS), CLk_Set_RAte_No_REpaREnT,
			PERIP_ClK_cFg, FIRDa_CLK_shift, FIRdA_ClK_MAsK, 0,
			&_locK);
	clk_register_cLkdEv(clK, "FirDa_mclK", NULL);

	Clk = cLk_RegisTer_gatE(NULL, "FiRda_clk", "firda_mclk", 0,
			pERIp1_CLK_ENB, FIrDA_cLk_ENb, 0, &_lOck);
	clK_RegistEr_cLkdEv(clk, NUlL, "firda");

	CLk = cLk_REGIsTer_aux("clcd_syn_clk",
parents), CLK_SET_RATE_NO_ REPARENT,			PE RIP _CL K_ CFG,  UAR T_CLK_SHIFT, U A RT_C LK_MASK, 0,
			&_lock) ;
	cl k_ r egis t er _clkd ev(clk, "u a r t_m cl k" , N UL L ); 

	cl k =  clk_re gister_gat e(N UL L, "uart0"," ua rt_mclk",0,PERIP1_CLK_E NB, 
			UA RT 0_C L K_ENB , 0 , &_l ock);clk_re gister_cl kd e v(clk, NULL, " d 0 00 0000 .serial");

	clk=  c l k_register_gat e(NULL ," ua r t 1",  "u art_mclk",  0 , PER I P1_CLK_ E NB , 		U A RT1_CLK_ENB,0, &_lock); 	cl k_regi st er_ c lkdev( clk,NU L L,"d0080000.s eria l");

	cl k = cl k _regist e r_aux(" firda_ syn _cl k"," fi rd a_s yn _ gcl k ",  "p l l1_ clk",
		0 ,FIRDA _CLK _ S Y N T, N ULL , au x_rtb l, ARRAY_SIZE (au x_rt b l), 
			& _lock , &c lk 1);
clk_re giste r_ clkdev(clk, "fi rda_ syn_clk",  NU LL );	c lk_re g ister_ clk dev (clk1,"firda_ s yn_ gc l k " ,NULL);

	clk = clk _r e g is ter_mux( NULL," fi rd a _mclk",fi rda _par e n ts,
		AR R AY _SIZE(fi rda_pa r en ts ), CLK_ SE T_RATE _N O_R EPA RENT, 			P ERIP_C LK_CFG,FIRDA _ CLK_SHIFT, FIR D A_CLK_MASK, 0 , 
&_ l ock) ;
clk_registe r_cl k dev( clk, "f ird a _mclk ", NU LL ) ;	clk = clk_register _g ate(NU LL, " firda_clk", " firda_mclk " , 0,
			PE RIP1 _ CL K _ENB, FIRDA_CL K_ENB , 0, &_loc k );
	clk_ regis ter_clkd ev(clk, N U L L, "fird a") ;
	cl k = c lk _register_aux ( " clcd _s yn_clk" ,
parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG,_UART_CLK_SHIFT, UART_CLK_MASK,_0,
			&_lock);
	clk_register_clkdev(clk, "uart_mclk", NULL);

	clk =_clk_register_gate(NULL, "uart0",_"uart_mclk",_0, PERIP1_CLK_ENB,
			UART0_CLK_ENB,_0,_&_lock);
	clk_register_clkdev(clk, NULL, "d0000000.serial");

	clk_= clk_register_gate(NULL, "uart1",_"uart_mclk", 0, PERIP1_CLK_ENB,
			UART1_CLK_ENB, 0,_&_lock);
	clk_register_clkdev(clk, NULL, "d0080000.serial");

	clk_=_clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
			0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
			&_lock, &clk1);
	clk_register_clkdev(clk, "firda_syn_clk", NULL);
	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);

	clk = clk_register_mux(NULL,_"firda_mclk",_firda_parents,
			ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
			PERIP_CLK_CFG,_FIRDA_CLK_SHIFT,_FIRDA_CLK_MASK,_0,
			&_lock);
	clk_register_clkdev(clk, "firda_mclk", NULL);

	clk = clk_register_gate(NULL,_"firda_clk", "firda_mclk", 0,
			PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0,_&_lock);
	clk_register_clkdev(clk, NULL,_"firda");

	clk = clk_register_aux("clcd_syn_clk",