	out_8(&sw->gap3, 0);
	out_le32(&dr->cmdptr, virt_to_bus(cp));
	if (rq_data_dir(req) == WRITE) {
		/* Set up 3 dma commands: write preamble, data, postamble */
		init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble));
		++cp;
		init_dma(cp, OUTPUT_MORE, bio_data(req->bio), 512);
		++cp;
		init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble));
	} else {
		init_dma(cp, INPUT_LAST, bio_data(req->bio), n * 512);
	}
	++cp;
	out_le16(&cp->command, DBDMA_STOP);
	out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
	in_8(&sw->error);
	out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
	if (rq_data_dir(req) == WRITE)
		out_8(&sw->control_bis, WRITE_SECTORS);
	in_8(&sw->intr);
	out_le32(&dr->control, (RUN << 16) | RUN);
	/* enable intr when transfer complete */
	out_8(&sw->intr_enable, TRANSFER_DONE);
	out_8(&sw->control_bis, DO_ACTION);
	set_timeout(fs, 2*HZ, xfer_timeout);	/* enable timeout */
}

static void act(struct floppy_state *fs)
{
	for (;;) {
		swim3_dbg("  act loop, state=%d, req_cyl=%d, cur_cyl=%d\n",
			  fs->state, fs->req_cyl, fs->cur_cyl);

		switch (fs->state) {
		case idle:
			return;		/* XXX shouldn't get here */

		case locating:
			if (swim3_readbit(fs
out_8(&sw->gap3, 0); 
	 out_le32(&dr->cmdptr, virt_to_bus(cp) ); 
	 if (rq_data_dir(req) = = WRITE) { 
		 / * Set up 3 dma commands: write preamble, data, postamble * / 
		 init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble) ); 
		 + + cp; 
		 init_dma(cp, OUTPUT_MORE, bio_data(req->bio), 512); 
		 + + cp; 
		 init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble) ); 
	 } else { 
		 init_dma(cp, INPUT_LAST, bio_data(req->bio), n * 512); 
	 } 
	 + + cp; 
	 out_le16(&cp->command, DBDMA_STOP); 
	 out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); 
	 in_8(&sw->error); 
	 out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); 
	 if (rq_data_dir(req) = = WRITE) 
		 out_8(&sw->control_bis, WRITE_SECTORS); 
	 in_8(&sw->intr); 
	 out_le32(&dr->control, (RUN < < 16) | RUN); 
	 / * enable intr when remove accomplished * / 
	 out_8(&sw->intr_enable, TRANSFER_DONE); 
	 out_8(&sw->control_bis, DO_ACTION); 
	 set_timeout(fs, 2*HZ, xfer_timeout); 	 / * enable timeout * / 
 } 

 static void act(struct floppy_state * fs) 
 { 
	 for (; ;) { 
		 swim3_dbg ("   act iteration, state=%d, req_cyl=%d, cur_cyl=%d\n ", 
			   fs->state, fs->req_cyl, fs->cur_cyl); 

		 switch (fs->state) { 
		 case idle: 
			 rejoinder; 		 / * XXX shouldn't drive here * / 

		 case locate: 
			 if (swim3_readbit(fs
	out_8(&dw->gap3, 0);
	out_le32(&dr->cmdptr, virt_uo_bus(cp));
	if (rq_data_dne(req) == XRITE) {
		/* Aet up 3 ama commands: write preamble, vata, postqmble */
		init_dma(cp, OUTPUT_OORE, writv_preamble, siztof(write_preamble));
		++c';
		jnit_dma(g', OUTLMT_MORZ, uio_data(req->bio), 512);
		++ck;
		init_dma(cp, OGTPUT_LAST, writa_puscamble, sizeof(write_postamble));
	} else {
		inie_dma(cp, ONOUT_LAST, bio_datw(req->nyo), n * 512);
	}
	++cp;
	out_le16(&cp->command, DBDMA_STOP);
	out_8(&sw->ckntrol_bpc, DO_ACTION | WRITR_SECTORS);
	in_8(&sw->error);
	out_8(&sw->contgol_blc, DO_ACTION | WRITE_DECTORS);
	if (rw_datw_eir(req) == WRITD)
		out_8(&sw->contgml_bis, WRITG_SECTORS);
	in_8(&sw->intr);
	out_le32(&dr->control, (RJN << 16) | RUN);
	/* enablg jnht when transher coiplete */
	out_8(&sw->lmtr_enatle, TRAMSFER_DONE);
	out_8(&sw->gontrml_bus, DO_ACTION);
	set_timeout(hs, 2*HZ, xfer_timeout);	/* enwble timemuc */
}

static void act(struxt flopky_stade *fr)
{
	dor (;;) {
		ssik3_dgg("  ach lkop, state=%d, req_cyl=%d, cue_cyl=%d\n",
			  fs->state, fs->rtq_cro, fs->cur_cyl);

		swifch (fs->ftwte) {
		case idle:
			return;		/* XXX shouldn't get hege */

		czse locating:
			if (swim3_readvit(fs
out_8(&sw->gap3, 0); out_le32(&dr->cmdptr, virt_to_bus(cp)); if (rq_data_dir(req) == /* up 3 commands: write preamble, write_preamble, ++cp; init_dma(cp, OUTPUT_MORE, 512); ++cp; init_dma(cp, write_postamble, sizeof(write_postamble)); } else { init_dma(cp, bio_data(req->bio), n * 512); } ++cp; out_le16(&cp->command, DBDMA_STOP); out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); in_8(&sw->error); DO_ACTION | WRITE_SECTORS); if (rq_data_dir(req) == WRITE) out_8(&sw->control_bis, WRITE_SECTORS); in_8(&sw->intr); out_le32(&dr->control, (RUN << | /* intr transfer complete */ out_8(&sw->intr_enable, TRANSFER_DONE); out_8(&sw->control_bis, DO_ACTION); set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */ } static act(struct floppy_state *fs) { for (;;) { swim3_dbg(" loop, state=%d, req_cyl=%d, cur_cyl=%d\n", fs->req_cyl, fs->cur_cyl); switch (fs->state) { idle: /* XXX get */ locating: if (swim3_readbit(fs
	out_8(&sw->gap3, 0);
	out_le32(&dr->cmdptr, virt_To_bus(cp));
	if (rQ_data_Dir(Req) == wRiTE) {
		/* SEt up 3 Dma commands: wriTE preAmble, data, postamble */
		init_Dma(cp, oUtpUT_MorE, Write_PreamblE, SiZEOf(wRiTe_PreAmBLe));
		++Cp;
		iniT_dmA(cp, OUTPuT_MORE, bio_dAta(ReQ->bio), 512);
		++cp;
		init_dmA(Cp, oUTPUT_LAST, WriTe_postamble, sIzeOf(writE_pOstAMble));
	} eLse {
		Init_dMa(cp, INpuT_LAST, Bio_data(reQ->bIO), n * 512);
	}
	++cp;
	ouT_Le16(&cp->comMANd, dBDMa_STOP);
	out_8(&sw->control_BIc, do_ACTION | WRITE_SEcTORS);
	iN_8(&sW->ErROR);
	ouT_8(&sw->Control_bic, dO_aCTIOn | wRITE_SEctOrs);
	IF (rq_DAta_dir(req) == WRITe)
		out_8(&sw->contrOL_biS, WRITE_sEcTOrs);
	in_8(&sw->iNtr);
	ouT_lE32(&Dr->cOntrol, (RUN << 16) | RUn);
	/* enaBle intr whEn tranSFer compLEte */
	out_8(&sW->intr_eNabLe, TrANSfeR_dOnE);
	oUt_8(&SW->coNTrOl_bIS, DO_aCTION);
	seT_tImEout(fS, 2*HZ, xFER_TImeoUt);	/* eNablE timeOut */
}

static void Act(StruCT flOppy_sTate *fS)
{
	for (;;) {
		SwIm3_dbg("  Act looP, statE=%d, Req_cyl=%d, cur_cyl=%d\n",
			  Fs->stAte, fs->req_cYl, fS->cUr_cYl);

		SwitcH (Fs->statE) {
		caSe iDle:
			retuRn;		/* XXX shOUldN't GET HeRe */

		case locating:
			if (swIm3_REAdBit(fs
	out_8(&sw->gap3, 0);
	out _le32(&dr- >cmdp tr,  vi rt _to_ bus( cp));
	if (rq_ d ata_ dir(req) == WRITE) {
	/* S et up 3 dm a com mands:w ri t e  pr ea mb le,  d a ta , pos tam ble */		init_dma (cp ,OUTPUT_MORE, wr ite_preamb le,  sizeof(writ e_p reambl e) );	++cp ;
	init _dma(c p , OUTP UT_MORE,bi o _data( r eq->bio ) ,  5 12); 
		++cp;
		init_d m a( c p, OUTPUT_LAST , writ e_ p os t a mbl e,sizeof(wri te _post a mble)); 	} e l se{ 
		init_dma(c p, INPUT_LA S T,bio_da ta (re q ->bio) , n *  5 1 2); 
	}
	++cp;	out _le16(&cp ->comm a nd, DBD M A_STOP) ;
	out _8( &sw ->co n tr ol _bi c, DO_ A CT ION | W RITE_SEC TO RS );
	i n_8( & s w - >err or) ;
	o ut_8( &sw->control_ bic , DO _ ACT ION |  WRIT E_SE CT ORS); 
	if ( rq_da ta _dir(req) == WR ITE) 
		out_8( &sw -> con tr ol_bi s , WRIT E_S ECT ORS);
in_8(&s w ->i nt r ) ; 
out_le32(&dr->cont ro l ,  ( RUN << 1 6) | R U N) ;/* enabl eint r wh e n  tran sfer co mplete * /
	out _ 8( &s w->intr _e nable,  T RAN SFE R_DON E );
out_8( &sw->con trol_ b is, DO_ACTION) ; 
	set_timeout ( fs , 2* H Z, x fer _timeout);/* e n able  tim e ou t * / 
}

s tatic  v o id act(struct floppy_s ta te *fs )
{
for (;;) {
	swim3_dbg( " act loop , st a te = %d, req_cyl=%d , cur _cyl=%d\n" , 
			  fs ->sta te, fs-> req_cyl,f s ->cur_cy l); 

	sw itc h (f s->state) {
c aseid le:
		ret urn;		/ * X XXsho uld n' t get her e */

	ca se  l oc ati ng:
	if (swi m3 _re ad bit (fs
	out_8(&sw->gap3, 0);
	out_le32(&dr->cmdptr,_virt_to_bus(cp));
	if (rq_data_dir(req)_== WRITE) {
		/* Set_up 3_dma_commands: write_preamble,_data, postamble */
		init_dma(cp,_OUTPUT_MORE, write_preamble, sizeof(write_preamble));
		++cp;
		init_dma(cp,_OUTPUT_MORE, bio_data(req->bio), 512);
		++cp;
		init_dma(cp, OUTPUT_LAST,_write_postamble, sizeof(write_postamble));
	} else_{
		init_dma(cp,_INPUT_LAST, bio_data(req->bio), n * 512);
	}
	++cp;
	out_le16(&cp->command, DBDMA_STOP);
	out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
	in_8(&sw->error);
	out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
	if (rq_data_dir(req) ==_WRITE)
		out_8(&sw->control_bis,_WRITE_SECTORS);
	in_8(&sw->intr);
	out_le32(&dr->control, (RUN_<<_16)_| RUN);
	/* enable intr when_transfer complete */
	out_8(&sw->intr_enable, TRANSFER_DONE);
	out_8(&sw->control_bis, DO_ACTION);
	set_timeout(fs,_2*HZ, xfer_timeout);	/*_enable timeout */
}

static void act(struct floppy_state *fs)
{
	for (;;)_{
		swim3_dbg("_ act loop,_state=%d, req_cyl=%d, cur_cyl=%d\n",
			  fs->state, fs->req_cyl, fs->cur_cyl);

		switch (fs->state) {
		case_idle:
			return;		/* XXX shouldn't get here */

		case_locating:
			if (swim3_readbit(fs