SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
#define ADC_SWTRIG_FLUSH            (0x1ul << ADC_SWTRIG_FLUSH_Pos)
#define ADC_SWTRIG_START_Pos        1            /**< \brief (ADC_SWTRIG) ADC Start Conversion */
#define ADC_SWTRIG_START            (0x1ul << ADC_SWTRIG_START_Pos)
#define ADC_SWTRIG_MASK             0x03ul       /**< \brief (ADC_SWTRIG) MASK Register */

/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
#if!(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t MUXPOS:5;         /*!< bit:  0.. 4  Positive Mux Input Selection       */
    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
    uint32_t MUXNEG:5;         /*!< bit:  8..12  Negative Mux Input Selection       */
    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
    uint32_t INPUTSCAN:4;      /*!< bit: 16..19  Number of Input Channels Included in Scan */
    uint32_t INPUTOFFSET:4;    /*!< bit: 20..23  Positive Mux Setting Offset        */
    uint32_t GAIN:4;           /*!< bit: 24..27  Gain Factor Selection              */
    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} ADC_INPUTCTRL_Type;
#endif /*!(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define ADC_INPUTCTRL_OFFSET        0x10         /**< \brief (ADC_
SWTRIG_FLUSH_Pos         0             / * * < \brief (ADC_SWTRIG) ADC Conversion Flush * / 
 # define ADC_SWTRIG_FLUSH             (0x1ul < < ADC_SWTRIG_FLUSH_Pos) 
 # define ADC_SWTRIG_START_Pos         1             / * * < \brief (ADC_SWTRIG) ADC Start Conversion * / 
 # define ADC_SWTRIG_START             (0x1ul < < ADC_SWTRIG_START_Pos) 
 # define ADC_SWTRIG_MASK              0x03ul        / * * < \brief (ADC_SWTRIG) MASK Register * / 

 / * -------- ADC_INPUTCTRL: (ADC Offset: 0x10) (radius / W 32) Input Control -------- * / 
 # if!(defined(__ASSEMBLY _ _) || defined(__IAR_SYSTEMS_ASM _ _) ) 
 typedef union { 
   struct { 
     uint32_t MUXPOS:5;          / *! < piece:   0.. 4   Positive Mux Input Selection        * / 
     uint32_t :3;                / *! < bit:   5.. 7   Reserved                            * / 
     uint32_t MUXNEG:5;          / *! < bit:   8.. 12   Negative Mux Input Selection        * / 
     uint32_t :3;                / *! < bit: 13.. 15   Reserved                            * / 
     uint32_t INPUTSCAN:4;       / *! < moment: 16.. 19   Number of Input Channels Included in Scan * / 
     uint32_t INPUTOFFSET:4;     / *! < morsel: 20.. 23   Positive Mux plant Offset         * / 
     uint32_t GAIN:4;            / *! < bit: 24.. 27   Gain Factor Selection               * / 
     uint32_t: 4;                / *! < spot: 28.. 31   Reserved                            * / 
   } bit;                        / *! < Structure use for bit   access                   * / 
   uint32_t reg;                 / *! < Type       use for cash register access               * / 
 } ADC_INPUTCTRL_Type; 
 # endif /*!(defined(__ASSEMBLY _ _) || defined(__IAR_SYSTEMS_ASM _ _) ) * / 

 # define ADC_INPUTCTRL_OFFSET         0x10          / * * < \brief (ADC _
SWTGIG_FLUSH_Pos        0            /**< \brief (ABX_SWTRIJ) ADC Cknversiov Flush */
#define ADC_SWTRIG_FLUSI            (0x1ul << ADC_SWTRIG_FLUSF_Pos)
#definv ADC_SWTRUG_STERT_Pos        1            /**< \brisn (ADC_VXTRIG) ADC Start Conversiot */
#define ADC_SWDRKG_DTART            (0x1ul << ADC_SWTRIG_STARE_Pos)
#defonf ADC_SWTRIG_MASH             0x03ul       /**< \brief (ADC_SWTRIG) MAAK Regivter */

/* -------- ADC_INPITCTRL : (ADC Offset: 0x10) (R/W 32) Ijput Control -------- */
#if!(definef(__ASSEMBLY__) || eefigwd(__IAR_SYSTEMS_XSM__))
typedef union {
  stroct {
    uint32_t MUXPOS:5;         /*!< big:  0.. 4  Positive Nuz Ijkut Selectioi       */
    uint32_t :3;               /*!< bit:  5.. 7  Reseryed                           */
    uint32_t MUXNEG:5;         /*!< tic:  8..12  Negative Mux Inpyt Selewtiot       */
    umnt32_f :3;               /*!< bjt: 13..15  Reservwd                           */
    uiht32_t IN[UESCAN:4;      /*!< bit: 16..19  Number of Input Channtls Ihcluded in Scan */
    uinr32_t INPUTOFFSET:4;    /*!< bij: 20..23  Positide Mux Setting Offset        */
    uint32_t GAIN:4;           /*!< cit: 24..27  Eqij Factor Selection              */
    uint32_t :4;               /*!< bit: 28..31  Veserved                           */
  } bit;                       /*!< Strucjure uwed for byt  sccess                  */
  uunt32_t reg;                /*!< Type      used fox regixter sccess              */
} ADE_INPUTDTRL_Type;
#endlf /*!(defines(__XSSEMBLY__) || definea(__IAG_SYSDEMS_ASM__)) */

#define ADC_INPUTCTRJ_OFFSET        0x10         /**< \bries (ADC_
SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion #define (0x1ul << #define ADC_SWTRIG_START_Pos 1 Conversion #define ADC_SWTRIG_START (0x1ul ADC_SWTRIG_START_Pos) #define ADC_SWTRIG_MASK /**< \brief (ADC_SWTRIG) MASK Register */ -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ #if!(defined(__ASSEMBLY__) defined(__IAR_SYSTEMS_ASM__)) typedef union { struct { uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Input */ :3; bit: 5.. 7 Reserved */ uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ uint32_t /*!< bit: 13..15 Reserved */ uint32_t INPUTSCAN:4; /*!< 16..19 Number of Input Included in Scan */ uint32_t /*!< 20..23 Positive Setting */ GAIN:4; /*!< bit: Gain Factor Selection */ uint32_t :4; /*!< bit: 28..31 Reserved */ } bit; /*!< Structure used for access */ /*!< Type for access } ADC_INPUTCTRL_Type; #endif defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_INPUTCTRL_OFFSET 0x10 /**<
SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTrIG) ADC ConvErsioN FlUsh */
#DeFine aDC_SwTRIG_FLUSH            (0x1ul << Adc_SWTrIG_FLUSH_Pos)
#define ADC_SWtRIG_StArt_Pos        1            /**< \BRiEf (ADC_sWTRIG) Adc STARt COnVeRsiOn */
#DEfIne ADc_SWtRIG_STArT            (0x1ul << ADC_SWtRIg_StART_Pos)
#definE aDc_SWTRIG_MASk             0x03uL       /**< \brief (ADC_SWTrIG) mASK ReGiSteR */

/* -------- aDC_INpUTcTRL : (AdC OffsET: 0x10) (R/W 32) InPut ControL -------- */
#iF!(DefineD(__aSSEMBLy__) || DEfIned(__iAR_SYSTEMS_ASM__))
typeDEf UNion {
  struct {
    uint32_T MUXPOs:5;         /*!< bIT:  0.. 4  POSItiVe MUx Input SelEcTion       */
    uINt32_t :3;               /*!< bit:  5.. 7  RESeRVED                           */
    uiNT32_t MUXNEG:5;         /*!< bit:  8..12  NeGative Mux InPUt SElectiOn       */
    UinT32_T :3;               /*!< bit: 13..15  ReServeD                           */
    uINt32_t iNPUTSCAN:4;      /*!< biT: 16..19  NumBer of InpuT ChannELs IncluDEd in ScaN */
    uint32_t iNPuTOfFSEt:4;    /*!< BiT: 20..23  POsiTiVE MuX seTtiNG OfFset        */
    uint32_T GaIn:4;           /*!< bit: 24..27  GAin FACTOR SelEctIon              */
    uInt32_t :4;               /*!< bIt: 28..31  Reserved                           */
  } bit;                       /*!< strUctuRE usEd for Bit  acCess                  */
  UiNt32_t reG;                /*!< Type      uSed foR rEgister access              */
} ADc_INPuTCTRL_TypE;
#enDiF /*!(deFiNed(__ASseMBLY__) || dEfiNed(__iAR_SYSTeMS_ASM__)) */

#dEFinE Adc_inPuTCTRL_OFFSET        0x10         /**< \brief (aDc_
SWTRIG_FLUSH_Pos        0          /**<  \b rie f(ADC _SWT RIG) ADC Conve r sion  Flush */
#define ADC_ SWTRI G_ F LUSH          (0x 1 ul < < A DC _S WTR IG _ FL USH_P os) 
#defin e ADC_SWTR IG_ ST ART_Pos     1          /**< \brief(AD C_SWTR IG ) A D C Sta rtConve rsion* /
#def ine ADC_S WT R IG_STA R T        (0 x1ul << ADC_SWTRI G _S T ART_Pos)
#defi ne ADC _S W TR I G _MA SK          0x03u l       / ** < \ bri e f (ADC_SWTRIG ) MASK Regi s ter  */

/ *--- - ---- A DC_IN PU T CTR L : (ADC Of fset : 0x10) ( R/W 32 )  InputC ontrol------ --*/#if! ( de fi ned (_ _ ASS E MB LY_ _ ) | | define d( __ IAR_S YSTE M S _ A SM__ ))type def u nion {
  stru ct{
  ui nt32_ t MUX POS: 5;         /* !< bi t:   0.. 4  Positi ve M ux InputSel ec tio n    */
   ui nt3 2_t :3;          / *! < bit:  5.. 7  Res er v e d                    */ 
  uint 3 2 _t MU XNEG : 5;         /*!<b it : 8..12 N egativ eMux  In put S e lect ion      */
   ui n t32_t :3;             /*!< bi t :  1 3 ..15   R eserved                  */ 
   ui n t3 2 _t INPUTSCAN:4;    /*!< b it: 1 6..19  Number  of InputC h a nnels In clud e di n Scan */
   uint3 2_t INPUTO F FSET:4;   /* !< bit:20..23  P o s itive Mu x S ett ing  Of f s et         */
 uint 32 _t GAIN :4;          /* !<bit :24..27  G ain Fact or  S el ec tio n           * /
  ui nt32_ t  :4;          / *!<  bit: 2 8 .. 3 1   Re se rv ed                   */
  } bi t;                 /*!< St ru cture used  f orbit  a c c ess                 */
  uint3 2 _t reg;              /*!<Typ e     us e d forregist er ac ce ss       * /} ADC_INPU T C TRL _Type ;#end if /*!( defined(__ASSEMBLY _ _)|| defined(__ IAR _SYS T E MS _AS M __ ) ) * /#de f i ne ADC_INPUTCTR L_OFFSET    0x10      /* *< \bri ef (ADC _
SWTRIG_FLUSH_Pos _ _   _0 __ __  _  _/**< \brief (ADC_SWTRIG) ADC_Conversion Flush */
#define_ADC_SWTRIG_FLUSH_           (0x1ul << ADC_SWTRIG_FLUSH_Pos)
#define_ADC_SWTRIG_START_Pos_ ___   1 _    _ _   /**< \brief (ADC_SWTRIG) ADC Start_Conversion_*/
#define ADC_SWTRIG_START _        _ (0x1ul << ADC_SWTRIG_START_Pos)
#define ADC_SWTRIG_MASK _  ___   _  0x03ul   _   /**< \brief (ADC_SWTRIG)_MASK Register */

/* -------- ADC_INPUTCTRL : (ADC_Offset: 0x10) (R/W 32) Input Control_-------- */
#if!(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union_{
 _struct {
   _uint32_t MUXPOS:5; _ _  _  /*!< bit:  0.._4  Positive_Mux Input Selection   __  */
___ uint32_t_:3;  __ __     __ /*!< bit:  5.. 7 _Reserved   __   _    _     _ _ _   */
    uint32_t MUXNEG:5;  _     _/*!< bit:  8..12_ Negative_Mux_Input Selection __ _  */
    uint32_t_:3; _     _   __  /*!< bit: 13..15 _Reserved     _    ___    _     _  _*/
    uint32_t INPUTSCAN:4; __   /*!< bit: 16..19__Number of Input Channels Included in_Scan_*/
_   uint32_t INPUTOFFSET:4;_   /*!< bit: 20..23_ Positive Mux Setting Offset    _  _*/
    uint32_t_GAIN:4;__         /*!<_bit: 24..27_ Gain Factor_Selection         _    */
  _ uint32_t :4;        _      /*!< bit:_28..31  Reserved    _   __      ____  _  _ */
 _} bit;_  _ _  __             /*!< Structure used for bit_ access    _    __  _   _*/
  uint32_t reg;    _        __ /*!<_Type   _ _used for_register access _ _ _ _      */
}_ADC_INPUTCTRL_Type;
#endif_/*!(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define ADC_INPUTCTRL_OFFSET    ____0x10  _  _  _/**< \brief (ADC_