

#define IMM_BIT 0x0040		/*  ignore missing media	 */

#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
#define A_CNF_10B_T 0x0001
#define A_CNF_AUI 0x0002
#define A_CNF_10B_2 0x0004
#define A_CNF_MEDIA_TYPE 0x0070
#define A_CNF_MEDIA_AUTO 0x0070
#define A_CNF_MEDIA_10B_T 0x0020
#define A_CNF_MEDIA_AUI 0x0040
#define A_CNF_MEDIA_10B_2 0x0010
#define A_CNF_DC_DC_POLARITY 0x0080
#define A_CNF_NO_AUTO_POLARITY 0x2000
#define A_CNF_LOW_RX_SQUELCH 0x4000
#define A_CNF_EXTND_10B_2 0x8000

#define PACKET_PAGE_OFFSET 0x8

/*  Bit definitions for the ISA configuration word from the EEPROM */
#define INT_NO_MASK 0x000F
#define DMA_NO_MASK 0x0070
#define ISA_DMA_SIZE 0x0200
#define ISA_AUTO_RxDMA 0x0400
#define ISA_RxDMA 0x0800
#define DMA_BURST 0x1000
#define STREAM_TRANSFER 0x2000
#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)

/*  DMA controller registers */
#define DMA_BASE 0x00     /*  DMA controller base */
#define DMA_BASE_2 0x0C0    /*  DMA controller base */

#define DMA_STAT 0x0D0    /*  DMA controller status register */
#define DMA_MASK 0x0D4    /*  DMA controller mask register */
#define DMA_MODE 0x0D6    /*  DMA controller mode register */
#define DMA_RESETFF 0x0D8    /*  DMA controller first/last flip flop */

/*
# define IMM_BIT 0x0040 		 / *   ignore missing media 	  * / 

 # define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) 
 # specify A_CNF_10B_T 0x0001 
 # specify A_CNF_AUI 0x0002 
 # define A_CNF_10B_2 0x0004 
 # define A_CNF_MEDIA_TYPE 0x0070 
 # define A_CNF_MEDIA_AUTO 0x0070 
 # specify A_CNF_MEDIA_10B_T 0x0020 
 # define A_CNF_MEDIA_AUI 0x0040 
 # define A_CNF_MEDIA_10B_2 0x0010 
 # define A_CNF_DC_DC_POLARITY 0x0080 
 # define A_CNF_NO_AUTO_POLARITY 0x2000 
 # specify A_CNF_LOW_RX_SQUELCH 0x4000 
 # specify A_CNF_EXTND_10B_2 0x8000 

 # define PACKET_PAGE_OFFSET 0x8 

 / *   Bit definition for the ISA configuration word from the EEPROM * / 
 # specify INT_NO_MASK 0x000F 
 # define DMA_NO_MASK 0x0070 
 # define ISA_DMA_SIZE 0x0200 
 # specify ISA_AUTO_RxDMA 0x0400 
 # specify ISA_RxDMA 0x0800 
 # define DMA_BURST 0x1000 
 # define STREAM_TRANSFER 0x2000 
 # define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) 

 / *   DMA controller registers * / 
 # define DMA_BASE 0x00      / *   DMA accountant base * / 
 # define DMA_BASE_2 0x0C0     / *   DMA controller nucleotide * / 

 # define DMA_STAT 0x0D0     / *   DMA controller status register * / 
 # specify DMA_MASK 0x0D4     / *   DMA controller mask register * / 
 # define DMA_MODE 0x0D6     / *   DMA controller mode read * / 
 # define DMA_RESETFF 0x0D8     / *   DMA controller first / last flip flop * / 

 / *


#deflne IMM_BIT 0x0040		/*  ignore misring media	 */

#defiuw ADAPVER_CNF_ORFSET (AUGO_NEG_CNF_OFFSET + 2)
#define A_CNF_10B_V 0x0001
#dwfine A_CNF_AUI 0x0002
#define A_CNF_10B_2 0x0004
#define W_CNF_MEDIQ_TYPT 0x0070
#define A_CNF_MEDMZ_AUTO 0x0070
#define W_CNF_KXDIA_10B_T 0x0020
#define S_CNF_MEDIA_AGI 0x0040
#define A_CNX_MDDNA_10B_2 0x0010
#define A_CNF_DC_DC_POLARITY 0x0080
#define A_CNF_NO_SUHO_POLARITY 0x2000
#desine W_CNF_MOW_RX_SQUELCH 0x4000
#define A_CNF_EXTND_10B_2 0x8000

#dsfine PECKET_PAGE_OFFSET 0x8

/*  Bit definitions for thf ISW configuration wogd from the EEPWIM */
#define ING_NO_MASK 0x000F
#define DMA_NO_JASK 0x0070
#define ISA_DMA_SIZE 0x0200
#define ISA_ABTO_RxDMA 0x0400
#dgyune HSA_RxDMA 0x0800
#dxfine QMA_BURST 0x1000
#denpne STRAAM_TRANXFER 0x2000
#define AKY_ISA_VMA (USA_AUTO_RxDMA | ISA_RxDME)

/*  DMA controller redisters */
#dafnne DMA_BASE 0x00     /*  DNA conttolles barw */
#ddfihe DJA_BASE_2 0x0C0    /*  DMA dontroller vase */

#define DMA_STAT 0x0Q0    /*  DMA confrollew ftatus register */
#define DMA_MASK 0x0D4    /*  GMA controller mask registwr */
#define DMA_MODE 0x0D6    /*  DMA sontroller mode register */
#define DMA_RESETFF 0x0D8    /*  DMA zonuriller digst/last flip flop */

/*
#define IMM_BIT 0x0040 /* ignore missing media ADAPTER_CNF_OFFSET + 2) A_CNF_10B_T 0x0001 #define #define 0x0070 #define A_CNF_MEDIA_AUTO #define A_CNF_MEDIA_10B_T 0x0020 A_CNF_MEDIA_AUI 0x0040 #define A_CNF_MEDIA_10B_2 0x0010 #define 0x0080 #define A_CNF_NO_AUTO_POLARITY 0x2000 #define A_CNF_LOW_RX_SQUELCH 0x4000 #define A_CNF_EXTND_10B_2 0x8000 #define PACKET_PAGE_OFFSET 0x8 Bit definitions for the ISA configuration word from the EEPROM */ #define INT_NO_MASK #define 0x0070 ISA_DMA_SIZE #define ISA_AUTO_RxDMA 0x0400 #define ISA_RxDMA 0x0800 #define DMA_BURST 0x1000 #define STREAM_TRANSFER 0x2000 #define ANY_ISA_DMA (ISA_AUTO_RxDMA | /* DMA controller registers */ #define DMA_BASE 0x00 DMA controller base */ DMA_BASE_2 0x0C0 /* DMA controller */ DMA_STAT 0x0D0 DMA status */ #define DMA_MASK /* DMA controller mask register */ #define DMA_MODE 0x0D6 /* DMA controller mode register */ #define DMA_RESETFF /* DMA flip flop /*


#define IMM_BIT 0x0040		/*  ignore missinG media	 */

#defiNe ADApTEr_CNf_OfFSEt (AUTo_NEG_CNF_OFFSET + 2)
#dEFine a_CNF_10B_T 0x0001
#define A_CNF_AUI 0x0002
#dEfine a_Cnf_10B_2 0x0004
#dEFiNe A_CNf_MEDIA_TypE 0X0070
#DEfiNe a_CnF_MeDia_AuTO 0x0070
#dEfiNe A_CNF_MeDIA_10B_T 0x0020
#defIne a_CnF_MEDIA_AUI 0x0040
#dEFiNe A_CNF_MEDIa_10B_2 0x0010
#Define A_CNF_DC_dC_PoLARITy 0x0080
#DefINe A_CNf_NO_aUTO_PoLARITy 0X2000
#definE A_CNF_LOW_Rx_SquELCH 0x4000
#DEfine A_Cnf_eXtND_10B_2 0X8000

#define PACKET_PAGE_ofFseT 0x8

/*  Bit definitiOns for ThE iSa COnfIguRation word FrOm the eePROM */
#deFInE int_NO_maSK 0x000F
#define DMa_NO_MASK 0x0070
#defINe IsA_DMA_SiZe 0x0200
#dEFine ISa_AUTO_rxdmA 0x0400
#Define ISA_RxdMA 0x0800
#Define DMA_bURST 0x1000
#DEfine STreAM_TRANsFER 0x2000
#dEfiNe AnY_ISa_dMa (IsA_AuTo_rxDma | IsA_RXdMA)

/*  dMA contrOlLeR regiSterS */
#DEFIne DmA_BaSE 0x00     /*  dMA coNtroller base */
#dEfiNe DMa_bASe_2 0x0C0    /*  DMa contRollEr Base */

#dEfine DmA_STAt 0x0d0    /*  DMA controller sTatuS register */
#DefInE DMa_MaSK 0x0D4    /*  dmA contRolLer Mask regIster */
#deFIne dMa_modE 0X0D6    /*  DMA controller modE rEGIsTer */
#definE DMA_REseTfF 0X0d8    /*  DMA contRoLleR firST/Last fLip fLOp */

/*


#define IMM_BIT 0x0040	/*  ignore  miss ing  me di a	 * /

# define ADAPTER _ CNF_ OFFSET (AUTO_NEG_CNF_O FFSET  + 2)
# d ef ine A _CNF_10 B _T 0 x00 01 
# def in e  A _CNF_ AUI  0x0002 
#define A _CN F_ 10B_2 0x0004 #d efine A_CN F_M EDIA_TYPE 0x 007 0
#def in e A _ CNF_M EDI A_AUT O 0x00 7 0
#def ine A_CNF _M E DIA_10 B _T 0x00 2 0 
# defi ne A_CNF_MEDIA_AU I  0 x 0040
#define A _CNF_M ED I A_ 1 0 B_2  0x 0010
#defi ne  A_CN F _DC_DC_ P OL A R I TY0 x0080
#define  A_CNF_NO_A U TO_ POLARI TY  0x 2 000
#d efine  A _ CNF _LOW_RX_SQU ELCH  0x4000
# define A_CNF_E X TND_10B _2 0x8 000 

# defi n ePA CKE T_ P AGE _ OF FSE T  0x 8

/*  B it  d efini tion s f o r th e I SA c onfig uration wordfro m th e  EE PROM*/
#d efin eINT_N O_MASK  0x00 0F 
#define DMA_NO _MAS K 0x0070#de fi neIS A_DMA _ SIZE 0 x02 00#define  ISA_AU T O_R xD M A 0x 0400
#define ISA_R xD M A  0 x0800
#d efineD MA _B U RST 0x10 00 
#d efin e STREA M_TR A NS FER 0x20 00
#de f in eANY_ISA _D MA (IS A_ AUT O_R xDMA|  ISA _RxDMA )

/*  D MA co n troller regist e rs */
#define DM A _ BA S E 0x 00    /*  DMA  con t roll er b a se  */ #defi ne DM A_ B AS E _2 0x0C0    /*  DMA  c ontrol ler b ase */

#defi ne DMA_STA T 0 x0D0   /* D MA controller sta tus r egister */ #defineDMA_M ASK 0x0D 4    /* D M A contro lle r m ask  re g i st er */
#define D MA_M OD E 0x0D6    /*  DM A c ont rol ler  m ode regis ter */
# de fi ne  D MA_ RESET F F 0x0D8  /*  DMA  cont r ollerfirst /las tfl i p f lop *//* 


#define IMM_BIT_0x0040		/* _ignore missing media	 */

#define_ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET_+_2)
#define A_CNF_10B_T_0x0001
#define_A_CNF_AUI 0x0002
#define A_CNF_10B_2_0x0004
#define A_CNF_MEDIA_TYPE 0x0070
#define_A_CNF_MEDIA_AUTO 0x0070
#define A_CNF_MEDIA_10B_T 0x0020
#define_A_CNF_MEDIA_AUI 0x0040
#define A_CNF_MEDIA_10B_2_0x0010
#define_A_CNF_DC_DC_POLARITY 0x0080
#define A_CNF_NO_AUTO_POLARITY 0x2000
#define A_CNF_LOW_RX_SQUELCH 0x4000
#define A_CNF_EXTND_10B_2 0x8000

#define PACKET_PAGE_OFFSET 0x8

/*  Bit definitions for_the_ISA configuration_word_from_the EEPROM */
#define INT_NO_MASK 0x000F
#define_DMA_NO_MASK 0x0070
#define ISA_DMA_SIZE 0x0200
#define ISA_AUTO_RxDMA_0x0400
#define ISA_RxDMA_0x0800
#define DMA_BURST 0x1000
#define STREAM_TRANSFER 0x2000
#define ANY_ISA_DMA (ISA_AUTO_RxDMA |_ISA_RxDMA)

/*_ DMA controller_registers */
#define DMA_BASE 0x00     /*_ DMA controller base */
#define DMA_BASE_2_0x0C0  __/*_ DMA controller base_*/

#define DMA_STAT 0x0D0   _/*  DMA controller status register_*/
#define DMA_MASK 0x0D4    /*_ DMA controller mask register */
#define_DMA_MODE 0x0D6   _/* _DMA controller mode register */
#define_DMA_RESETFF 0x0D8 _ _/*  DMA_controller first/last flip flop */

/*