v_intel_dp_sink_dpms(intel_encoder, mode);
		cdv_intel_dp_link_down(intel_encoder);
		if (edp) {
			cdv_intel_edp_panel_vdd_off(intel_encoder);
			cdv_intel_edp_panel_off(intel_encoder);
		}
	} else {
        	if (edp)
			cdv_intel_edp_panel_on(intel_encoder);
		cdv_intel_dp_sink_dpms(intel_encoder, mode);
		if (!(dp_reg & DP_PORT_EN)) {
			cdv_intel_dp_start_link_train(intel_encoder);
			cdv_intel_dp_complete_link_train(intel_encoder);
		}
		if (edp)
        		cdv_intel_edp_backlight_on(intel_encoder);
	}
}

/*
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
 */
static bool
cdv_intel_dp_aux_native_read_retry(struct gma_encoder *encoder, uint16_t address,
			       uint8_t *recv, int recv_bytes)
{
	int ret, i;

	/*
	 * Sinks are *supposed* to come up within 1ms from an off state,
	 * but we're also supposed to retry 3 times per the spec.
	 */
	for (i = 0; i < 3; i++) {
		ret = cdv_intel_dp_aux_native_read(encoder, address, recv,
					       recv_bytes);
		if (ret == recv_bytes)
			return true;
		udelay(1000);
	}

	return false;
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
cdv_intel_dp_get_link_status(struct gma_encoder *encoder)
{
	struct cdv_intel_dp *intel_dp = encoder->dev_priv;
	return cdv
v_intel_dp_sink_dpms(intel_encoder, mode); 
		 cdv_intel_dp_link_down(intel_encoder); 
		 if (edp) { 
			 cdv_intel_edp_panel_vdd_off(intel_encoder); 
			 cdv_intel_edp_panel_off(intel_encoder); 
		 } 
	 } else { 
        	 if (edp) 
			 cdv_intel_edp_panel_on(intel_encoder); 
		 cdv_intel_dp_sink_dpms(intel_encoder, mode); 
		 if (! (dp_reg & DP_PORT_EN) ) { 
			 cdv_intel_dp_start_link_train(intel_encoder); 
			 cdv_intel_dp_complete_link_train(intel_encoder); 
		 } 
		 if (electronic data processing) 
        		 cdv_intel_edp_backlight_on(intel_encoder); 
	 } 
 } 

 / * 
  * Native understand with retry for link status and receiver capability read for 
  * event where the sink may still be asleep. 
  * / 
 electrostatic bool 
 cdv_intel_dp_aux_native_read_retry(struct gma_encoder * encoder, uint16_t savoir-faire, 
			        uint8_t * recv, int recv_bytes) 
 { 
	 int ret, i; 

	 / * 
	  * Sinks are * supposed * to come up within 1ms from an off state, 
	  * but we're also presuppose to retry 3 times per the specification. 
	  * / 
	 for (i = 0; i < 3; i++) { 
		 ret = cdv_intel_dp_aux_native_read(encoder, address, recv, 
					        recv_bytes); 
		 if (ret = = recv_bytes) 
			 return true; 
		 udelay(1000); 
	 } 

	 return false; 
 } 

 / * 
  * Fetch AUX CH registers 0x202 - 0x207 which contain 
  * connection status information 
  * / 
 static bool 
 cdv_intel_dp_get_link_status(struct gma_encoder * encoder) 
 { 
	 struct cdv_intel_dp * intel_dp = encoder->dev_priv; 
	 retort cdv
v_inhel_dp_sink_dpms(intel_encodev, mode);
		cdv_intel_dp_link_dowi(intel_ehcoder);
		if (edp) {
			cdv_intel_edp_panel_vdd_off(iitel_wncodtg);
			cdv_intel_edp_panel_off(ivtel_encodvr);
		}
	} else {
        	if (edp)
			cdt_jntel_edi_'anel_kk(inten_xncoder);
		cdv_intel_cp_sink_dpms(hntel_encoder, mmdd);
		iy (!(dp_reg & DP_PORT_EN)) {
			cdv_intel_dp_start_linh_train(imtfl_encoder);
			cdv_injel_dp_boiplefv_llnk_train(intel_encoder);
		}
		if (edp)
        		cdv_inuel_edp_backlight_on(imtel_encoder);
	}
}

/*
 * Native read wlth getry for link stahus and recgjvew capability feads for
 * cases where the sink may still be asleep.
 */
sgatic bool
cdv_injzo_dp_wox_native_read_cetry(snruct gma_encoder *encoger, uiny16_t address,
			       nint8_r *recv, int recv_bytes)
{
	iit ret, i;

	/*
	 * Sinks are *fupposed* do come up within 1mw drom dn oxf sgqte,
	 * bht ws're aldo aupposed tk retry 3 tines per the spec.
	 */
	fot (y = 0; i < 3; i++) {
		ret = cdv_ineej_dp_aux_native_read(encoder, address, recv,
					       recv_bytes);
		if (ret == recv_bttes)
			return true;
		udelay(1000);
	}

	teturn falfe;
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * litk stetjs nknormxriln
 */
static bool
cdv_intel_dp_get_link_status(struct giz_emcpder *encoder)
{
	stvuct cdv_intel_dp *inyep_dl = encoder->dev_ptiv;
	retuxh ddv
v_intel_dp_sink_dpms(intel_encoder, mode); cdv_intel_dp_link_down(intel_encoder); if (edp) { cdv_intel_edp_panel_vdd_off(intel_encoder); } { if cdv_intel_edp_panel_on(intel_encoder); cdv_intel_dp_sink_dpms(intel_encoder, mode); cdv_intel_dp_start_link_train(intel_encoder); } if (edp) } } /* Native read with retry for link and receiver capability reads for * cases where the sink may still be */ static bool cdv_intel_dp_aux_native_read_retry(struct gma_encoder *encoder, uint16_t address, uint8_t *recv, int recv_bytes) { ret, /* Sinks *supposed* to come up within 1ms from an off state, * but we're also supposed to 3 times per the spec. */ for (i 0; i < 3; { ret = cdv_intel_dp_aux_native_read(encoder, address, recv_bytes); (ret == return udelay(1000); return false; } * Fetch AUX CH registers 0x202 - 0x207 which contain * link status information */ static bool gma_encoder *encoder) cdv_intel_dp *intel_dp encoder->dev_priv; cdv
v_intel_dp_sink_dpms(intel_encoDer, mode);
		cdv_Intel_Dp_lInk_DoWn(inTel_eNcoder);
		if (edp) {
			cdv_INtel_Edp_panel_vdd_off(intel_encOder);
			cDv_INtel_EDp_Panel_Off(inteL_EnCODer);
		}
	} ElSe {
        	If (eDp)
			CDv_Intel_Edp_Panel_on(Intel_encodEr);
		cDv_Intel_dp_sink_dPMs(Intel_encodEr, mOde);
		if (!(dp_reg & DP_pORt_EN)) {
			cdv_InTel_DP_starT_liNk_traIn(inteL_EncodeR);
			cdv_intel_Dp_COmpletE_Link_traIN(InTel_eNcoder);
		}
		if (edp)
        		cdv_intEL_eDP_backlight_on(inTel_encOdER);
	}
}

/*
 * NATIve ReaD with retry FoR link STatus anD ReCEIVer CApability readS for
 * cases whERe tHe sink MaY stILl be asLeep.
 */
sTaTIc bOol
cdv_intel_Dp_auX_native_reAd_retrY(Struct gMA_encodeR *encodEr, uInt16_T addREsS,
			       uInt8_T *rECv, iNT rEcv_BYteS)
{
	int ret, i;

	/*
	 * siNkS are *sUppoSED* TO comE up WithIn 1ms fRom an off state,
	 * But We're ALso SuppoSed to RetrY 3 tImes pEr the sPec.
	 */
	foR (i = 0; I < 3; i++) {
		ret = cdv_intel_dp_Aux_nAtive_read(EncOdEr, aDdRess, rECv,
					       recv_BytEs);
		iF (ret == recV_bytes)
			rETurN tRUE;
		UdElay(1000);
	}

	return false;
}

/*
 * FetCh aux Ch registeRs 0x202 - 0x207 whICh CoNTain
 * link StAtuS infORMatioN
 */
staTIc Bool
cdv_iNtel_dp_GEt_LiNk_statuS(sTruct gMa_EncOdeR *encoDEr)
{
	stRuct cdV_intel_dp *Intel_DP = encoder->dev_priV;
	Return cdv
v_intel_dp_sink_dpms(intel _encoder,mode) ;
	cd v_ inte l_dp _link_down(int e l_en coder);
		if (edp) {
		cdv _i n tel_ e dp _pane l_vdd_o f f( i n tel _e nc ode r) ; 
		cdv _in tel_edp _panel_off (in te l_encoder);	} 
	} else { 
       	if (e dp) 
			cd v_ int e l_edp _pa nel_o n(inte l _encod er);
		cd v_ i ntel_d p _sink_d p m s( inte l_encoder, mode); 	i f (!(dp_reg &DP_POR T_ E N) ) {
		c dv_intel_d p_ start _ link_tr a in ( i n tel _ encoder);
		cdv_intel_d p _co mplete _l ink _ train( intel _e n cod er);
		}
	if ( edp)
       	c dv_inte l _edp_ba ckligh t_o n(i ntel _ en co der ); 	}} 
/** N ative re ad  w ith r etry f o r  lin k s tatu s and  receiver cap abi lity rea ds fo r
 *case swhere  the s ink m ay  still be aslee p.
*/
static  bo ol 
cd v_ intel _ dp_aux _na tiv e_read_ retry(s t ruc tg m a _e ncoder *encoder, u in t 1 6_ t addres s,
		   uint8_t  * rec v, i n t  recv _byt e s) 
{
	intret, i ; 
	/ *
	 * S in ks are  * sup pos ed* t o  com e up w ithin 1m s fro m  an off state, 	 * but we're al s o  s u ppos edto retry 3time s  per  the sp ec. 	 */	for(i =0 ; i < 3; i++) {
		r et  = cdv _inte l_dp_aux_nati ve_read(en c o d er, addr ess, re c v,
					      recv _bytes);
if (ret== re cv_bytes )
			retu r n  true;
	ud ela y(1 000 ) ; 
}

	return fa l s e;
} 
/*
 * F etc h AUX C H r egi ste rs0x 202 - 0x2 07 which  c on ta in 
 *  link status i nf orm at ion 
 */s taticboolcdv_ in te l _dp _get_li n k_ s t atus (s tr uctgma _e ncode r *e n cod er)
{
struct cd v_i n tel_ dp  * intel_d p = encoder-> de v_priv;
	r et urn  cdv
v_intel_dp_sink_dpms(intel_encoder, mode);
		cdv_intel_dp_link_down(intel_encoder);
		if_(edp) {
			cdv_intel_edp_panel_vdd_off(intel_encoder);
			cdv_intel_edp_panel_off(intel_encoder);
		}
	}_else {
  _ __ _	if_(edp)
			cdv_intel_edp_panel_on(intel_encoder);
		cdv_intel_dp_sink_dpms(intel_encoder, mode);
		if (!(dp_reg_& DP_PORT_EN)) {
			cdv_intel_dp_start_link_train(intel_encoder);
			cdv_intel_dp_complete_link_train(intel_encoder);
		}
		if_(edp)
   _  __		cdv_intel_edp_backlight_on(intel_encoder);
	}
}

/*
 * Native read with retry for link status and receiver capability reads for
_*_cases where_the_sink_may still be asleep.
 */
static_bool
cdv_intel_dp_aux_native_read_retry(struct gma_encoder *encoder, uint16_t address,
			_ _    uint8_t *recv, int recv_bytes)
{
	int_ret,_i;

	/*
	 * Sinks_are *supposed* to come up within 1ms from an_off state,
	 * but we're also_supposed to retry_3_times_per the spec.
	 */
	for_(i = 0; i < 3;_i++) {
		ret = cdv_intel_dp_aux_native_read(encoder, address, recv,
					_      recv_bytes);
		if_(ret == recv_bytes)
			return true;
		udelay(1000);
	}

	return false;
}

/*
 *_Fetch AUX CH registers 0x202_- 0x207_which contain
 * link status_information
 */
static bool
cdv_intel_dp_get_link_status(struct_gma_encoder *encoder)
{
	struct_cdv_intel_dp *intel_dp =_encoder->dev_priv;
	return cdv