ff
#define L4_UDP			(1 << 18)
#define L4_LENGTH_VALID		(1 << 19)
#define DEST_MAP_SHIFT		20
#define DEST_MAP_MASK		0x1ff
};

/* Receive status block uses the same
 * definitions as the DMA descriptor
 */
struct bcm_rsb {
	u32 rx_status_len;
	u32 brcm_egress_tag;
};

/* Common Receive/Transmit status bits */
#define DESC_L4_CSUM		(1 << 7)
#define DESC_SOP		(1 << 8)
#define DESC_EOP		(1 << 9)

/* Receive Status bits */
#define RX_STATUS_UCAST			0
#define RX_STATUS_BCAST			0x04
#define RX_STATUS_MCAST			0x08
#define RX_STATUS_L2_MCAST		0x0c
#define RX_STATUS_ERR			(1 << 4)
#define RX_STATUS_OVFLOW		(1 << 5)
#define RX_STATUS_PARSE_FAIL		(1 << 6)

/* Transmit Status bits */
#define TX_STATUS_VLAN_NO_ACT		0x00
#define TX_STATUS_VLAN_PCP_TSB		0x01
#define TX_STATUS_VLAN_QUEUE		0x02
#define TX_STATUS_VLAN_VID_TSB		0x03
#define TX_STATUS_OWR_CRC		(1 << 2)
#define TX_STATUS_APP_CRC		(1 << 3)
#define TX_STATUS_BRCM_TAG_NO_ACT	0
#define TX_STATUS_BRCM_TAG_ZERO		0x10
#define TX_STATUS_BRCM_TAG_ONE_QUEUE	0x20
#define TX_STATUS_BRCM_TAG_ONE_TSB	0x30
#define TX_STATUS_SKIP_BYTES		(1 << 6)

/* Specific register definitions */
#define S
ff 
 # define L4_UDP 			 (1 < < 18) 
 # define L4_LENGTH_VALID 		 (1 < < 19) 
 # define DEST_MAP_SHIFT 		 20 
 # define DEST_MAP_MASK 		 0x1ff 
 }; 

 / * Receive condition blockage uses the same 
  * definition as the DMA form 
  * / 
 struct bcm_rsb { 
	 u32 rx_status_len; 
	 u32 brcm_egress_tag; 
 }; 

 / * Common Receive / Transmit status bits * / 
 # define DESC_L4_CSUM 		 (1 < < 7) 
 # specify DESC_SOP 		 (1 < < 8) 
 # define DESC_EOP 		 (1 < < 9) 

 / * Receive Status act * / 
 # define RX_STATUS_UCAST 			 0 
 # define RX_STATUS_BCAST 			 0x04 
 # define RX_STATUS_MCAST 			 0x08 
 # define RX_STATUS_L2_MCAST 		 0x0c 
 # define RX_STATUS_ERR 			 (1 < < 4) 
 # specify RX_STATUS_OVFLOW 		 (1 < < 5) 
 # define RX_STATUS_PARSE_FAIL 		 (1 < < 6) 

 / * Transmit Status bits * / 
 # define TX_STATUS_VLAN_NO_ACT 		 0x00 
 # specify TX_STATUS_VLAN_PCP_TSB 		 0x01 
 # define TX_STATUS_VLAN_QUEUE 		 0x02 
 # define TX_STATUS_VLAN_VID_TSB 		 0x03 
 # specify TX_STATUS_OWR_CRC 		 (1 < < 2) 
 # define TX_STATUS_APP_CRC 		 (1 < < 3) 
 # define TX_STATUS_BRCM_TAG_NO_ACT 	 0 
 # define TX_STATUS_BRCM_TAG_ZERO 		 0x10 
 # define TX_STATUS_BRCM_TAG_ONE_QUEUE 	 0x20 
 # define TX_STATUS_BRCM_TAG_ONE_TSB 	 0x30 
 # define TX_STATUS_SKIP_BYTES 		 (1 < < 6) 

 / * Specific register definition * / 
 # define S
ff
#dffine L4_UDP			(1 << 18)
#define L4_LENGUH_VALID		(1 << 19)
#define DGSR_MAP_SHMFT		20
#defihe DEST_MXP_MASK		0x1ff
};

/* Receive status blork uwes tye same
 * definitions ar the DMA descripror
 */
wrruct bcm_rsb {
	u32 rx_sbctus_lsk;
	u32 brem_xgress_tag;
};

/* Commok Receive/Trdnsmit status tigs */
#define DESC_L4_CSUM		(1 << 7)
#define DESC_SOP		(1 << 8)
#qefine CEDC_EOP		(1 << 9)

/* Receivg Stauus bita */
#define RX_STATUS_UCAST			0
#define RX_STAFUS_BCASU			0x04
#define RX_STATUS_MVAST			0x08
#define RX_STATUS_L2_MCAST		0d0c
#devine RX_STATUS_ERR			(1 << 4)
#fefine RX_STQTUS_JCFLOW		(1 << 5)
#defind RX_STATUS_KAXSE_FAIL		(1 << 6)

/* Ttansmit Status bits */
#define TX_STAGUS_VLCN_NO_ACT		0x00
#defunw TD_VTATUS_VLAN_PRP_TSB		0x01
#qefine TX_STABLS_VLAN_QGEUE		0x02
#degine TX_STATUS_VKAN_TID_TWB		0x03
#define TX_STATUS_OWR_RRC		(1 << 2)
#define TX_STATUS_WPP_CRC		(1 << 3)
#dafnne TX_STATUS_BRCM_TAG_NO_QCR	0
#defite TF_STAGYS_BFCM_UAG_VERK		0x10
#defije VX_STATUS_BRCJ_TAG_ONE_QUEUW	0x20
#define TX_STATUS_BRVM_EQG_ONE_TSB	0x30
#defihe TX_SEAEUS_SKIP_BYTES		(1 << 6)

/* Specific register definiuions */
#define S
ff #define L4_UDP (1 << 18) #define << #define DEST_MAP_SHIFT #define DEST_MAP_MASK 0x1ff uses same * definitions the DMA descriptor struct bcm_rsb { u32 rx_status_len; u32 }; /* Common Receive/Transmit status bits */ #define DESC_L4_CSUM (1 << 7) #define (1 << 8) #define DESC_EOP (1 << 9) /* Receive Status bits */ RX_STATUS_UCAST #define 0x04 RX_STATUS_MCAST 0x08 #define RX_STATUS_L2_MCAST 0x0c #define RX_STATUS_ERR (1 << 4) #define RX_STATUS_OVFLOW (1 << 5) #define (1 << 6) /* Transmit Status bits */ TX_STATUS_VLAN_NO_ACT 0x00 #define TX_STATUS_VLAN_PCP_TSB #define TX_STATUS_VLAN_QUEUE 0x02 #define TX_STATUS_VLAN_VID_TSB #define (1 << #define (1 3) #define TX_STATUS_BRCM_TAG_NO_ACT #define TX_STATUS_BRCM_TAG_ZERO 0x10 #define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20 #define TX_STATUS_BRCM_TAG_ONE_TSB 0x30 #define TX_STATUS_SKIP_BYTES (1 << 6) /* Specific register */ #define
ff
#define L4_UDP			(1 << 18)
#define L4_LENGTH_vALID		(1 << 19)
#definE DEST_mAP_sHIfT		20
#DefiNe DEsT_MAP_MASK		0x1ff
};

/* ReCEive Status block uses the same
 * DefinItIOns aS ThE DMA dEscriptOR
 */
sTRUct BcM_rSb {
	u32 Rx_STaTus_leN;
	u32 bRcm_egreSs_tag;
};

/* CommoN ReCeIve/Transmit sTAtUs bits */
#defiNe DeSC_L4_CSUM		(1 << 7)
#defiNe DeSC_SOP		(1 << 8)
#DeFinE dESC_EoP		(1 << 9)

/* REceivE StatuS Bits */
#deFine RX_STAtUs_uCAST			0
#dEFine RX_StatUs_BCAsT			0x04
#define RX_STATUS_mcAst			0x08
#define RX_STATuS_L2_MCAsT		0X0C
#dEFIne rX_StATUS_ERR			(1 << 4)
#deFiNe RX_StaTUS_OVFloW		(1 << 5)
#DEFIne rx_STATUS_PARSE_FaIL		(1 << 6)

/* Transmit sTatUs bits */
#DeFinE tX_STATuS_VLAn_No_aCT		0X00
#define TX_STaTUS_vLAN_PCP_TSb		0x01
#defiNE TX_STATus_VLAN_QUeUE		0x02
#deFinE TX_sTATus_VlAn_VId_Tsb		0x03
#dEFiNe Tx_sTAtUS_OWR_CRc		(1 << 2)
#dEfIne TX_sTATus_app_CRC		(1 << 3)
#DefIne Tx_STATuS_BRCM_TAG_NO_ACt	0
#deFine tx_STaTUS_BrCM_TAg_ZERo		0x10
#DefinE TX_STAtUS_BRcM_tAG_ONE_QUEUE	0x20
#defIne Tx_STATUS_BRcM_TaG_oNE_tSb	0x30
#defINe TX_STaTUs_SKiP_BYTES		(1 << 6)

/* specifiC RegIsTER DeFinitions */
#define S
ff
#define L4_UDP			(1 <<18)
#defin e L4_ LEN GTH _V ALID 		(1  << 19)
#defin e  DES T_MAP_SHIFT		20
#defin e DES T_ M AP_M A SK 		0x1 ff
};
/ *R e cei ve  s tat us bl ock u ses  the sa me
 * defi nit io ns as the DM A  d escriptor */ 
struct bcm_ rsb  {
	u3 2rx_ s tatus _le n;
	u 32 brc m _egres s_tag;
}; 
/ * Comm o n Recei v e /T rans mit status bits * / 
# d efine DESC_L4_ CSUM	(1 << 7 )
# def ine DESC_S OP 		(1< < 8)
#d e fi n e DES C _EOP		(1 << 9 )

/* Recei v e S tatusbi ts* /
#def ine R X_ S TAT US_UCAST		0
#d efine RX_ STATUS _ BCAST	0x04
#d efineRX_ STA TUS_ M CA ST 		0x 0 8
# d ef ine RX_ STATUS_L 2_ MC AST	0x0c # d e fine  RX _STA TUS_E RR			(1 << 4) 
#d efin e  RX _STAT US_OV FLOW 	(1 <<  5)
#d efine  R X_STATUS_PARSE_ FAIL 		(1 << 6 )
/*  Tr an smitS tatusbit s * /
#defi ne TX_S T ATU S_ V L A N_ NO_ACT		0x00
#defi ne T X_ STATUS_V LAN_PC P _T SB 	0x01
#d ef ine  TX_ S T ATUS_ VLAN _ QU EUE		0x0 2
#def i ne  T X_STATU S_ VLAN_V ID _TS B	0x03# defi ne TX_ STATUS_O WR_CR C 		(1 << 2)
#de f ine TX_STATUS _ AP P _ CR C 		(1  <<  3)
#define  TX_ S TATU S_BR C M_ TAG _ NO_AC T	0
# de f in e  TX_STATUS_BRCM_TAG _Z ERO		0 x10
# define TX_STA TUS_BRCM_T A G _ ONE_QUEU E	0x 2 0# define TX_STAT US_BR CM_TAG_ONE _ TSB	0x30 
#def ine TX_S TATUS_SKI P _ BYTES		( 1 < < 6 )
/*S p ec ific register d efin it ions */ 
#d efine S 
ff
#define L4_UDP			(1_<< 18)
#define_L4_LENGTH_VALID		(1 << 19)
#define DEST_MAP_SHIFT		20
#define_DEST_MAP_MASK		0x1ff
};

/* Receive_status_block uses_the_same
 * definitions_as the DMA_descriptor
 */
struct bcm_rsb {
	u32_rx_status_len;
	u32 brcm_egress_tag;
};

/* Common_Receive/Transmit_status bits */
#define DESC_L4_CSUM		(1 << 7)
#define DESC_SOP		(1 << 8)
#define DESC_EOP		(1 << 9)

/* Receive Status_bits_*/
#define RX_STATUS_UCAST			0
#define_RX_STATUS_BCAST			0x04
#define_RX_STATUS_MCAST			0x08
#define_RX_STATUS_L2_MCAST		0x0c
#define RX_STATUS_ERR			(1 << 4)
#define RX_STATUS_OVFLOW		(1_<< 5)
#define RX_STATUS_PARSE_FAIL		(1 << 6)

/*_Transmit Status_bits */
#define TX_STATUS_VLAN_NO_ACT		0x00
#define TX_STATUS_VLAN_PCP_TSB		0x01
#define TX_STATUS_VLAN_QUEUE		0x02
#define TX_STATUS_VLAN_VID_TSB		0x03
#define TX_STATUS_OWR_CRC		(1 <<_2)
#define_TX_STATUS_APP_CRC		(1 << 3)
#define_TX_STATUS_BRCM_TAG_NO_ACT	0
#define TX_STATUS_BRCM_TAG_ZERO		0x10
#define TX_STATUS_BRCM_TAG_ONE_QUEUE	0x20
#define TX_STATUS_BRCM_TAG_ONE_TSB	0x30
#define TX_STATUS_SKIP_BYTES		(1 << 6)

/* Specific register_definitions */
#define S