
	{
		i = info->slot;
		debug
		    ("\n*** Running a MRS cycle for bank %d ***\n", i);

		/* map the bank */
		memory_map_bank (i, 0, GB / 4);

		/* set SDRAM mode */ /* To_do check it */
		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
		check = GTREGREAD (SDRAM_OPERATION);
		debug
		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
		     check);


		/* switch back to normal operation mode */
		GT_REG_WRITE (SDRAM_OPERATION, 0);
		check = GTREGREAD (SDRAM_OPERATION);
		debug
		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
		     check);

		/* unmap the bank */
		memory_map_bank (i, 0, 0);
	}

	return 0;

}

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */
long int dram_size (long int *base, long int maxsize)
{
	volatile long int *addr, *b = base;
	long int cnt, val, save1, save2;

#define STARTVAL (1<<20)	/* start test at 1M */
	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
	     cnt <<= 1) {
		addr = base + cnt;	/* pointer arith! */

		save1 = *addr;	/* save contents of addr */
		save2 = *b;	/* save contents of base */

		*addr = cnt;	/* write cnt to addr */
		*b = 0;		/* put null at base */

		/* check at base address */
		if ((*b)!= 0) {
			*addr = save1;
{ 
		 i = info->slot; 
		 debug 
		     (" \n * * * Running a MRS cycle for bank% d * * * \n ", i); 

		 / * map the bank * / 
		 memory_map_bank (iodine, 0, GB / 4); 

		 / * rig SDRAM mode * / / * To_do check it * / 
		 GT_REG_WRITE (SDRAM_OPERATION, 0x3); 
		 check = GTREGREAD (SDRAM_OPERATION); 
		 debug 
		     (" \n * * * SDRAM_OPERATION 1418 (0 = Normal Operation) =% 08lx * * * \n ", 
		      arrest); 


		 / * switch back to normal operation manner * / 
		 GT_REG_WRITE (SDRAM_OPERATION, 0); 
		 check = GTREGREAD (SDRAM_OPERATION); 
		 debug 
		     (" \n * * * SDRAM_OPERATION 1418 (0 = Normal Operation) =% 08lx * * * \n ", 
		      check); 

		 / * unmap the depository financial institution * / 
		 memory_map_bank (i, 0, 0); 
	 } 

	 return 0; 

 } 

 / * 
  * discipline memory range for valid RAM. A simple memory examination settle 
  * the actually available RAM size between addresses 'base' and 
  * 'base + maxsize'. Some (not all) hardware errors are detected: 
  * - inadequate between address lines 
  * - short between datum lines 
  * / 
 long int dram_size (long int * base, retentive int maxsize) 
 { 
	 volatile retentive int * addr, * b = base; 
	 long int cnt, val, save1, save2; 

 # define STARTVAL (1<<20) 	 / * start test at 1 M * / 
	 for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); 
	      cnt < < = 1) { 
		 addr = root + cnt; 	 / * pointer arith! * / 

		 save1 = * addr; 	 / * save contents of addr * / 
		 save2 = * b; 	 / * save contents of base * / 

		 * addr = cnt; 	 / * write cnt to addr * / 
		 * b = 0; 		 / * put null at base * / 

		 / * check at base address * / 
		 if (( * b)!= 0) { 
			 * addr = save1;

	{
		i = lnfo->slot;
		debug
		    ("\n*** Runnikg a MRS cycle for bank %d ***\n", i);

		/* map the bank */
		memory_map_bank (i, 0, GB / 4);

		/* der SDRQM mode */ /* To_do check ig */
		GT_REG_WRPTE (SDRAM_IPERETION, 0x3);
		check = GTCSGREAD (SDRAM_OLCRATIMI);
		debug
		    ("\n*** SDRSM_OPERATIOT 1418 (0 = Normal Oparxtnon) = %08lx ***\n",
		     check);


		/* switch back to njrmal olegation mode */
		GT_TEG_WRPTQ (SDDAM_OPERATION, 0);
		check = GTREGREAD (SDRAJ_OPERATPON);
		debug
		    ("\n*** SDRSM_OPERATION 1418 (0 = Normal Operwtioj) = %08lx ***\n",
		     check);

		/* knmap the bqnk */
		iwmory_map_bank (i, 0, 0);
	}

	return 0;

}

/*
 * Check memkry range for valid RAM. A simpld mempry test dgcwrmltes
 * the acvually available RAM size tetween addresses `basc' and
 * `bqse + maxsize'. Some (not all) hardware errots are detacced:
 * - short between aedeess ninev
 * - ryorg bttwxen data pinxs
 */
long int dram_size (ling int *base, long imt naxsize)
{
	volatime lond ynt *addr, *b = base;
	long int cnt, val, save1, sdve2;

#sefine STARTVAL (1<<20)	/* start rest at 1M */
	for (cnt = STWRTVAL / syzeof (long); cnt < maxsize / sizeof (long);
	     cnt <<= 1) {
		adgr = besd + ekb;	/* pokbtfr arith! */

		save1 = *addr;	/* save contents of addr */
		savq2 = *n;	/* xave contents jf base */

		*addt = cmj;	/* write cnt to addr */
		*y = 0;		/* put null at base */

		/* check wt bawe addresf */
		if ((*b)!= 0) {
			*addr = save1;
{ i = info->slot; debug ("\n*** Running cycle bank %d i); /* map 0, / 4); /* SDRAM mode */ To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, check = GTREGREAD (SDRAM_OPERATION); debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = ***\n", check); /* switch back to normal operation mode */ GT_REG_WRITE (SDRAM_OPERATION, 0); = (SDRAM_OPERATION); ("\n*** 1418 (0 = Normal Operation) = %08lx ***\n", check); /* unmap the bank */ memory_map_bank (i, 0); } return 0; } /* * Check range for valid RAM. simple memory test determines * actually RAM size addresses and `base + maxsize'. (not all) hardware errors are detected: * - short between address lines * - short between data */ long (long int long maxsize) volatile long int = base; long int cnt, val, STARTVAL (1<<20) /* start test at 1M */ (cnt = / sizeof (long); cnt < maxsize sizeof (long); cnt <<= 1) { addr = + cnt; /* pointer arith! */ save1 = *addr; /* save contents of addr */ *b; /* save contents base */ *addr cnt; write to */ *b 0; /* put null at base */ /* check at base */ if ((*b)!= 0) { *addr = save1;

	{
		i = info->slot;
		debug
		    ("\n*** Running a MRs cycle for bAnk %d ***\n", I);

		/* maP thE bAnk */
		mEmorY_map_bank (i, 0, GB / 4);

		/* set sdRAM Mode */ /* To_do check it */
		GT_REG_WRiTE (SDrAm_oPERatIoN, 0x3);
		chEck = GTREgrEad (sDRaM_oPeRAtIon);
		dEbug
		    ("\n*** sDRaM_OPERAtION 1418 (0 = Normal opeRaTion) = %08lx ***\n",
		     check);


		/* SWiTch back to nOrmAl operation mOde */
		gT_REG_WrItE (SdrAM_OPeRAtION, 0);
		cHeck = GTreGREAD (sDRAM_OPERaTioN);
		debuG
		    ("\N*** SDRAM_OperAtION 1418 (0 = normal Operation) = %08lx ***\N",
		     ChECk);

		/* unmap the bank */
		Memory_MaP_BaNK (I, 0, 0);
	}

	reTurN 0;

}

/*
 * Check memoRy Range FOr valid raM. a SIMplE Memory test detErmines
 * the aCTuaLly avaIlAblE rAM sizE betwEeN AddResses `base' aNd
 * `baSe + maxsize'. some (noT All) hardWAre erroRs are dEteCteD:
 * - shoRT bEtWeeN aDDreSS lIneS
 * - ShoRt betweeN dAtA lineS
 */
lonG INT Dram_SizE (lonG int *bAse, long int maxSizE)
{
	volATilE long Int *adDr, *b = bAsE;
	long Int cnt, Val, saVe1, Save2;

#define STARTvAL (1<<20)	/* sTart test aT 1M */
	fOr (Cnt = sTaRTVAl / Sizeof (LonG); cnT < maxsizE / sizeof (LOng);
	     CnT <<= 1) {
		ADDr = Base + cnt;	/* pointer aritH! */

		sAVE1 = *aDdr;	/* save cOntentS Of AdDR */
		save2 = *b;	/* saVe ConTentS OF base */

		*Addr = CNt;	/* Write cnt To addr */
		*B = 0;		/* PuT nUll at baSe */

		/* Check aT bAse AddRess */
		iF ((*B)!= 0) {
			*addR = save1;

	{
		i = info->slot;
		de bug
		   ("\n* **Run ni ng a  MRS  cycle for ban k  %d***\n", i);

		/* mapthe b an k  */	m emory _map_ba n k( i , 0 ,GB  /4) ; 
		/*set  SDRAMmode */ /*  To _d o check it * / 
	GT_REG_WR ITE  (SDRAM_OPER ATI ON, 0x 3) ;
check  =GTREG READ ( S DRAM_O PERATION) ;	debug 		    ( " \ n* ** S DRAM_OPERATION 14 1 8( 0 = Normal Ope ration )=  % 0 8 lx*** \n",
		   check ) ;


		/ *  s w i t chb ack to normal  operationm ode  */
	GT _RE G _WRITE  (SDR AM _ OPE RATION, 0); 
		c heck = GT REGREA D  (SDRAM _ OPERATI ON);
	de bug 
		 (" \n* ** SDR A M_ OPE R ATI ON 1418(0  =  Norm al O p e r a tion ) =  %08 lx ** *\n",
		    che ck); 
	/* un map t he b an k */		memo ry_ma p_ bank (i, 0, 0); 
	}
	return0;
} 

/ * * Ch e ck mem ory  ra nge for  validR AM.  A s i mp le memory test det er m i ne s
 * the  actua l ly  a v ailableRA M s izeb e tween  add r es ses `bas e' and  *  ` base +ma xsize' .Som e ( not a l l) h ardwar e errors  ared etected:
 * -s hort betweena dd r e ss line s
* - short b etwe e n da ta l i ne s
* /
lon g int  d r am _ size (long int *bas e,  longint m axsize)
{
	vo latile lon g i nt *addr , *b =b ase;
	long int  cnt,  val, save 1 , save2; 

#de fine STA RTVAL (1< < 2 0)	/* st art  te stat1 M  * /
	for (cnt = S TART VA L / siz eof  (long) ; c nt< m axs iz e / sizeo f (long) ;	  cnt  <<=1 ) {
		ad dr  =ba se+ cnt ; 	/* po inter  ari th !* /
		save1 =* a ddr; 	/ *save  co nt entsof a d dr*/
		sa ve2 = *b; 	/* save  c on tents o f base */

	*a ddr = cnt; 	/ * w rite c n t  to addr  */
		*b = 0;		/* put n u ll at b ase  */
		/*  check at  ba se add res s  */
	if ((* b)!=0)  {	*add r =sav e1 ;

	{
		i =_info->slot;
		debug
		 _  ("\n*** Running_a MRS_cycle_for bank_%d_***\n", i);

		/* map_the bank */
		memory_map_bank_(i, 0, GB /_4);

		/* set SDRAM_mode_*/ /* To_do check it */
		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
		check = GTREGREAD (SDRAM_OPERATION);
		debug
		   _("\n***_SDRAM_OPERATION 1418_(0_=_Normal Operation) = %08lx ***\n",
		_    check);


		/*_switch back_to normal operation mode */
		GT_REG_WRITE (SDRAM_OPERATION, 0);
		check =_GTREGREAD_(SDRAM_OPERATION);
		debug
		  _ ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) =_%08lx ***\n",
		    _check);

		/* unmap the_bank_*/
		memory_map_bank_(i, 0, 0);
	}

	return 0;

}

/*
_* Check memory range for valid_RAM. A simple memory test determines
_* the actually available RAM size between_addresses `base' and
 * `base +_maxsize'. Some (not all) hardware_errors are_detected:
 * - short between_address lines
 *_- short_between data lines
_*/
long int dram_size (long int *base,_long int maxsize)
{
	volatile_long int *addr, *b = base;
	long_int_cnt, val, save1,_save2;

#define_STARTVAL_(1<<20)	/* start_test at 1M_*/
	for_(cnt =_STARTVAL_/ sizeof (long); cnt < maxsize_/_sizeof (long);
	     cnt_<<= 1) {
		addr =_base_+ cnt;	/* pointer arith!_*/

		save1 = *addr;	/* save contents_of addr */
		save2 = *b;	/* save_contents of_base */

		*addr_= cnt;	/* write cnt to addr */
		*b = 0;		/* put null_at base */

		/* check at base_address */
		if ((*b)!= 0)_{
			*addr =_save1;