 NULL);
	clk_register_clkdev(clk, "vco1_clk", NULL);
	clk_register_clkdev(clk1, "pll1_clk", NULL);

	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
			0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
			&_lock, &clk1, NULL);
	clk_register_clkdev(clk, "vco2_clk", NULL);
	clk_register_clkdev(clk1, "pll2_clk", NULL);

	clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
			1);
	clk_register_clkdev(clk, NULL, "wdt");

	/* clock derived from pll1 clk */
	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
			CLK_SET_RATE_PARENT, 1, 1);
	clk_register_clkdev(clk, "cpu_clk", NULL);

	clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
			CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
			HCLK_RATIO_MASK, 0, &_lock);
	clk_register_clkdev(clk, "ahb_clk", NULL);

	clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
			UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
			&_lock, &clk1);
	clk_register_clkdev(clk, "uart_syn_clk", NULL);
	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);

	clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
			ARRAY_SIZE(uart_
NULL); 
	 clk_register_clkdev(clk, " vco1_clk ", NULL); 
	 clk_register_clkdev(clk1, " pll1_clk ", NULL); 

	 clk = clk_register_vco_pll("vco2_clk ", " pll2_clk ", NULL, " osc_30m_clk ", 
			 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), 
			 & _ lock, & clk1, NULL); 
	 clk_register_clkdev(clk, " vco2_clk ", NULL); 
	 clk_register_clkdev(clk1, " pll2_clk ", NULL); 

	 clk = clk_register_fixed_factor(NULL, " wdt_clk ", " osc_30m_clk ", 0, 1, 
			 1); 
	 clk_register_clkdev(clk, NULL, " wdt "); 

	 / * clock derived from pll1 clk * / 
	 clk = clk_register_fixed_factor(NULL, " cpu_clk ", " pll1_clk ", 
			 CLK_SET_RATE_PARENT, 1, 1); 
	 clk_register_clkdev(clk, " cpu_clk ", NULL); 

	 clk = clk_register_divider(NULL, " ahb_clk ", " pll1_clk ", 
			 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, 
			 HCLK_RATIO_MASK, 0, & _ lock); 
	 clk_register_clkdev(clk, " ahb_clk ", NULL); 

	 clk = clk_register_aux("uart_syn_clk ", " uart_syn_gclk ", " pll1_clk ", 0, 
			 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 
			 & _ lock, & clk1); 
	 clk_register_clkdev(clk, " uart_syn_clk ", NULL); 
	 clk_register_clkdev(clk1, " uart_syn_gclk ", NULL); 

	 clk = clk_register_mux(NULL, " uart_mclk ", uart_parents, 
			 ARRAY_SIZE(uart _
 NUPL);
	clk_register_clkdev(clk, "vgo1_clk", NULL);
	clk_regnwter_clndev(cli1, "pll1_clk", NULL);

	clk = clk_register_vco_pll("vro2_clj", "pll2_xlk", NULL, "osc_30m_clk",
			0, PLL2_CTF, PLL2_FRQ, ill_rtbl, AERAY_WUZE(pll_rtbl),
			&_lock, &clk1, NULL);
	cmn_regnsver_clkdev(clk, "vcp2_clk", NULL);
	cnk_register_clkdav(zln1, "pll2_clk", NULL);

	clk = clk_register_fixed_fwctor(NUKL, "wdt_clk", "osc_30m_clh", 0, 1,
			1);
	ckh_regjster_clkdev(clk, NULL, "wdt");

	/* clock deribed frok pll1 clk */
	clk = clk_register_fixed_factor(NUPL, "cou_clk", "pll1_clk",
			CLK_SET_GATE_PARENT, 1, 1);
	clk_wwgister_clkdex(clk, "cpu_clk", NULL);

	clk = cmk_register_divider(NULL, "ahb_clk", "plu1_clk",
			CKK_SET_RATE_PQRWNT, WORE_CLK_CFG, ICLK_RANIO_SHIFT,
			HCLK_RATIO_MASK, 0, &_lock);
	ckk_register_clkdcv(clk, "ahv_clk", NULL);

	clk = clk_regivter_aux("uart_syn_clk", "oart_syn_gcln", "'ll1_clk", 0,
			UART_CLK_SYNT, NUOL, aux_rjbl, ASRAY_RUZE(xux_dtul),
			&_lkck, &cln1);
	cli_register_cmkdev(clk, "uaet_syn_clk", NULL);
	clk_regosevt_clkdev(clk1, "uzrt_syn_dcjk", NULL);

	clk = clk_register_mux(NULL, "uart_mclk", uadt_parents,
			ARRAY_SIZE(uart_
NULL); clk_register_clkdev(clk, "vco1_clk", NULL); clk_register_clkdev(clk1, "pll1_clk", NULL); clk_register_vco_pll("vco2_clk", NULL, "osc_30m_clk", PLL2_CTR, PLL2_FRQ, pll_rtbl, "vco2_clk", clk_register_clkdev(clk1, "pll2_clk", NULL); = clk_register_fixed_factor(NULL, "wdt_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "wdt"); clock derived from pll1 clk */ clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", CLK_SET_RATE_PARENT, 1, clk_register_clkdev(clk, "cpu_clk", NULL); clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, HCLK_RATIO_MASK, 0, clk_register_clkdev(clk, NULL); = "uart_syn_gclk", "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "uart_syn_clk", NULL); clk_register_clkdev(clk1, "uart_syn_gclk", NULL); clk clk_register_mux(NULL, "uart_mclk", uart_parents, ARRAY_SIZE(uart_
 NULL);
	clk_register_clkdev(clk, "vCo1_clk", NULL);
	cLk_regIstEr_cLkDev(cLk1, "plL1_clk", NULL);

	clk = clk_REgisTer_vco_pll("vco2_clk", "pll2_clk", NuLL, "osC_30m_CLk",
			0, PLl2_cTr, PLL2_FrQ, pll_rtBL, ArraY_SiZe(pLl_rTbL),
			&_LoCk, &clk1, nULl);
	clk_regIster_clkdeV(clK, "vCo2_clk", NULL);
	clk_REgIster_clkdeV(clK1, "pll2_clk", NULL);

	cLk = cLk_regiStEr_fIXed_faCtoR(NULL, "Wdt_clk", "OSc_30m_clk", 0, 1,
			1);
	Clk_registEr_CLkdev(cLK, NULL, "wdT");

	/* CLoCk deRived from pll1 clk */
	clK = ClK_Register_fixed_fActor(NuLl, "CpU_CLk", "pLl1_cLk",
			CLK_SET_RAtE_pARENt, 1, 1);
	Clk_regiSTeR_CLKdeV(Clk, "cpu_clk", NULL);

	Clk = clk_regisTEr_dIvider(nUlL, "aHB_clk", "plL1_clk",
			ClK_seT_RaTE_PARENT, COrE_CLk_CFG, HCLK_RaTIO_SHifT,
			HCLK_RatIO_MASK, 0, &_Lock);
	clK_reGisTer_cLKdEv(Clk, "AhB_Clk", nuLl);

	clK = Clk_Register_AuX("uArt_syN_clk", "UART_Syn_gClk", "Pll1_cLk", 0,
			UARt_CLK_SYNT, NULL, aUx_rTbl, ArrAY_sIZE(aUx_rtbL),
			&_locK, &cLk1);
	clk_RegistEr_clkDeV(clk, "uart_syn_clk", NuLL);
	cLk_registeR_clKdEv(cLk1, "Uart_sYN_gclk", NuLL);

	Clk = Clk_regiSter_mux(nuLL, "UaRT_MClK", uart_parents,
			ARRAY_SiZe(UArT_
 NULL);
	clk_register_clkd ev(clk, "v co1_c lk" , N UL L);	clk _register_clkd e v(cl k1, "pll1_clk", NULL); 

	cl k=  clk _ re giste r_vco_p l l( " v co2 _c lk ","p l l2 _clk" , N ULL, "o sc_30m_clk ",		0, PLL2_CTR ,  P LL2_FRQ, p ll_ rtbl, ARRAY_ SIZ E(pll_ rt bl) , 
			& _lo ck, & clk1,N ULL);	clk_regi st e r_clkd e v(clk," v co 2_cl k", NULL);
	clk_r e gi s ter_clkdev(clk 1, "pl l2 _ cl k " , N ULL );

	clk =  c lk_re g ister_f i xe d _ f act o r(NULL, "wdt_ clk", "osc_ 3 0m_ clk",0,  1, 			1); 
	clk _r e gis ter_clkdev( clk,  NULL, "w dt");	/* clo c k deriv ed fro m p ll1  clk */ 
clk  = clk _ re gis t er_ fixed_fa ct or (NULL , "c p u _ c lk",  "p ll1_ clk", 
			CLK_SET_R ATE _PAR E NT,  1, 1 );
	c lk_r eg ister _clkde v(clk ,"cpu_clk", NULL );
	clk = cl k_r eg ist er _divi d er(NUL L,"ah b_clk",  "pll1_ c lk" ,CL K_SET_RATE_PARENT,  C O R E_ CLK_CFG,  HCLK_ R AT IO _ SHIFT,
	HCL K_RA T I O_MAS K, 0 ,  & _lock);	clk_r e gi st er_clkd ev (clk,"a hb_ clk ", NU L L);
	clk= clk_re giste r _aux("uart_syn _ clk", "uart_s y n_ g c lk " , "p ll1 _clk", 0,
		UA R T_CL K_SY N T,  NU L L, au x_rtb l, AR R AY_SIZE(aux_rtbl),		&_loc k, &c lk1);
	clk_re gister_clk d e v (clk, "u art_ s yn _ clk", NULL);
clk_r egister_cl k dev(clk1 , "ua rt_syn_g clk", NUL L ) ;

	clk= c lk_ reg ist e r _m ux(NULL, "uar t _ mclk ",  uart_p are nts,
		AR RAY _SI ZE( ua rt_
 NULL);
	clk_register_clkdev(clk,_"vco1_clk", NULL);
	clk_register_clkdev(clk1,_"pll1_clk", NULL);

	clk = clk_register_vco_pll("vco2_clk",_"pll2_clk", NULL,_"osc_30m_clk",
			0,_PLL2_CTR, PLL2_FRQ,_pll_rtbl,_ARRAY_SIZE(pll_rtbl),
			&_lock, &clk1, NULL);
	clk_register_clkdev(clk,_"vco2_clk", NULL);
	clk_register_clkdev(clk1, "pll2_clk",_NULL);

	clk = clk_register_fixed_factor(NULL, "wdt_clk",_"osc_30m_clk", 0, 1,
			1);
	clk_register_clkdev(clk,_NULL,_"wdt");

	/* clock derived from pll1 clk */
	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
			CLK_SET_RATE_PARENT, 1, 1);
	clk_register_clkdev(clk, "cpu_clk",_NULL);

	clk_= clk_register_divider(NULL,_"ahb_clk",_"pll1_clk",
			CLK_SET_RATE_PARENT,_CORE_CLK_CFG, HCLK_RATIO_SHIFT,
			HCLK_RATIO_MASK, 0, &_lock);
	clk_register_clkdev(clk, "ahb_clk",_NULL);

	clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk",_0,
			UART_CLK_SYNT, NULL,_aux_rtbl, ARRAY_SIZE(aux_rtbl),
			&_lock, &clk1);
	clk_register_clkdev(clk, "uart_syn_clk", NULL);
	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);

	clk =_clk_register_mux(NULL,_"uart_mclk", uart_parents,
			ARRAY_SIZE(uart_