#define SRCCA_CA	0x0FFFFFFF
#define SRCCA_RS	0xE0000000

#define SRCSA_SA	0x0FFFFFFF

#define SRCLA_LA	0x0FFFFFFF

/* Mixer Parameter Ring ram Low and Hight register.
 * Fixed-point value in 8.24 format for parameter channel */
#define MPRLH_PITCH	0xFFFFFFFF

/* SRC resource register dirty flags */
union src_dirty {
	struct {
		u16 ctl:1;
		u16 ccr:1;
		u16 sa:1;
		u16 la:1;
		u16 ca:1;
		u16 mpr:1;
		u16 czbfs:1;	/* Clear Z-Buffers */
		u16 rsv:9;
	} bf;
	u16 data;
};

struct src_rsc_ctrl_blk {
	unsigned int	ctl;
	unsigned int 	ccr;
	unsigned int	ca;
	unsigned int	sa;
	unsigned int	la;
	unsigned int	mpr;
	union src_dirty	dirty;
};

/* SRC manager control block */
union src_mgr_dirty {
	struct {
		u16 enb0:1;
		u16 enb1:1;
		u16 enb2:1;
		u16 enb3:1;
		u16 enb4:1;
		u16 enb5:1;
		u16 enb6:1;
		u16 enb7:1;
		u16 enbsa:1;
		u16 rsv:7;
	} bf;
	u16 data;
};

struct src_mgr_ctrl_blk {
	unsigned int		enbsa;
	unsigned int		enb[8];
	union src_mgr_dirty	dirty;
};

/* SRCIMP manager control block */
#define SRCAIM_ARC	0x00000FFF
#define SRCAIM_NXT	0x00FF0000
#define SRCAIM_SRC	0xFF000000

struct srcimap
# define SRCCA_CA 	 0x0FFFFFFF 
 # define SRCCA_RS 	 0xE0000000 

 # define SRCSA_SA 	 0x0FFFFFFF 

 # define SRCLA_LA 	 0x0FFFFFFF 

 / * Mixer Parameter Ring jam Low and Hight cash register. 
  * Fixed - point value in 8.24 format for argument channel * / 
 # define MPRLH_PITCH 	 0xFFFFFFFF 

 / * SRC resource cross-file dirty flags * / 
 union src_dirty { 
	 struct { 
		 u16 ctl:1; 
		 u16 ccr:1; 
		 u16 sa:1; 
		 u16 la:1; 
		 u16 ca:1; 
		 u16 mpr:1; 
		 u16 czbfs:1; 	 / * Clear Z - Buffers * / 
		 u16 rsv:9; 
	 } bf; 
	 u16 datum; 
 }; 

 struct src_rsc_ctrl_blk { 
	 unsigned int 	 ctl; 
	 unsigned int 	 ccr; 
	 unsigned int 	 ca; 
	 unsigned int 	 sa; 
	 unsigned int 	 la; 
	 unsigned int 	 mpr; 
	 union src_dirty 	 cheating; 
 }; 

 / * SRC manager control block * / 
 union src_mgr_dirty { 
	 struct { 
		 u16 enb0:1; 
		 u16 enb1:1; 
		 u16 enb2:1; 
		 u16 enb3:1; 
		 u16 enb4:1; 
		 u16 enb5:1; 
		 u16 enb6:1; 
		 u16 enb7:1; 
		 u16 enbsa:1; 
		 u16 rsv:7; 
	 } bf; 
	 u16 data; 
 }; 

 struct src_mgr_ctrl_blk { 
	 unsigned int 		 enbsa; 
	 unsigned int 		 enb[8 ]; 
	 union src_mgr_dirty 	 dirty; 
 }; 

 / * SRCIMP coach control block * / 
 # specify SRCAIM_ARC 	 0x00000FFF 
 # specify SRCAIM_NXT 	 0x00FF0000 
 # define SRCAIM_SRC 	 0xFF000000 

 struct srcimap
#deflne SRCCA_CA	0x0FFFFFFF
#defint SRCCA_RS	0xE0000000

#define SRCSA_SE	0x0FFFFFRF

#define SRCLA_LA	0x0FFFFFFF

/* Mixer Paramxter Ring ram Low and Hight regkster.
 * Fiqed-point calut in 8.24 format for 'zrametev chahkel */
#dzfmne MPRLH_PITCH	0xNFFFFFFF

/* SRW resource reghsgex dirty flags */
union src_dirty {
	struct {
		t16 ctl:1;
		u16 vcg:1;
		u16 sa:1;
		u16 la:1;
		u16 ca:1;
		u16 mpr:1;
		l16 szbfa:1;	/* Clear Z-Buffers */
		u16 rsv:9;
	} bf;
	u16 data;
};

strhct src_gsc_ctrl_blk {
	unsignrd int	ctl;
	unsigned int 	ccr;
	ujsigjed int	ca;
	unsigned lnt	sa;
	unsigngs igr	la;
	unsigned knt	mpr;
	union src_dirty	ditty;
};

/* SRC manager control block */
unkon sxc_mgr_dirty {
	wteuch {
		u16 enb0:1;
		u16 enb1:1;
		n16 enb2:1;
		u16 enb3:1;
		u16 enb4:1;
		u16 ekn5:1;
		u16 enb6:1;
		g16 enb7:1;
		u16 rnbsa:1;
		u16 rsv:7;
	} bf;
	u16 dava;
};

steuct src_mgr_ctrl_blk {
	unvigned int		enbsa;
	unsygned int		any[8];
	union src_mgr_dirty	dirry;
};

/* SRCIKP mdnagde cuntdok glock */
#fefmne SRCAIM_ADC	0x00000FFF
#definw SRCAIM_NXT	0x00FF0000
#defint SWBSIM_SRC	0xFF000000

strhct srsiiap
#define SRCCA_CA 0x0FFFFFFF #define SRCCA_RS 0xE0000000 #define #define 0x0FFFFFFF /* Parameter Ring ram Fixed-point in 8.24 format parameter channel */ MPRLH_PITCH 0xFFFFFFFF /* SRC resource register flags */ union src_dirty { struct { u16 ctl:1; u16 ccr:1; u16 sa:1; la:1; u16 ca:1; u16 mpr:1; u16 czbfs:1; /* Clear Z-Buffers */ u16 rsv:9; bf; data; struct { unsigned int ctl; unsigned int ccr; unsigned int ca; unsigned int sa; unsigned int la; int mpr; union src_dirty dirty; }; /* SRC control block */ union { struct { u16 enb0:1; enb1:1; enb2:1; u16 u16 u16 u16 enb6:1; u16 u16 enbsa:1; u16 rsv:7; } bf; u16 data; }; struct src_mgr_ctrl_blk { unsigned int enbsa; unsigned int union src_mgr_dirty /* SRCIMP control */ SRCAIM_ARC 0x00000FFF #define #define SRCAIM_SRC 0xFF000000 struct srcimap
#define SRCCA_CA	0x0FFFFFFF
#defiNe SRCCA_RS	0xe0000000

#defiNe SrCSa_Sa	0x0FFfFFFf

#define SRCLA_LA	0X0fFFFfFF

/* Mixer Parameter Ring rAm Low AnD highT ReGisteR.
 * Fixed-pOInT VAluE iN 8.24 fOrmAt FOr ParamEteR channeL */
#define MPRlH_PiTcH	0xFFFFFFFF

/* Src rEsource regIstEr dirty flags */
UniOn src_dIrTy {
	sTRuct {
		u16 Ctl:1;
		U16 ccr:1;
		u16 Sa:1;
		u16 la:1;
		u16 CA:1;
		u16 mpr:1;
		u16 Czbfs:1;	/* CleaR Z-bUffers */
		U16 Rsv:9;
	} bf;
	u16 dATA;
};

sTrucT src_rsc_ctrl_blk {
	unsIGnED int	ctl;
	unsigneD int 	ccR;
	uNSiGNEd iNt	cA;
	unsigned iNt	Sa;
	unsIGned int	LA;
	uNSIGneD Int	mpr;
	union srC_dirty	dirty;
};

/* srC mAnager CoNtrOL block */
Union SrC_Mgr_Dirty {
	struct {
		U16 enb0:1;
		U16 enb1:1;
		u16 enb2:1;
		u16 Enb3:1;
		u16 enB4:1;
		U16 enb5:1;
		u16 enB6:1;
		U16 enb7:1;
		u16 enBsa:1;
		u16 rsV:7;
	} bf;
	U16 daTa;
};

stRUcT sRc_mGr_CTrl_BLk {
	UnsIGneD int		enbsA;
	uNsIgned Int		eNB[8];
	UNIon sRc_mGr_diRty	diRty;
};

/* SRCIMP manaGer ContROl bLock */
#dEfine sRCAiM_aRC	0x00000FfF
#defiNe SRCaIm_NXT	0x00FF0000
#define SRcAIM_sRC	0xFF000000

strUct SrCimAp
#define SRCCA_CA	0x0FFFFFF F
#defineSRCCA _RS 	0x E0 0000 00
#define SRCSA_ S A	0x 0FFFFFFF

#define SRCL A_LA0x 0 FFFF F FF 

/*Mixer P a ra m e ter  R in g r am Lo w and  Hi ght reg ister.
 *Fix ed -point value in  8.24 form atfor paramete r c hannel  * /
# d efine  MP RLH_P ITCH	0 x FFFFFF FF

/* SR Cr esourc e  regist e r  d irty  flags */
union s r c_ d irty {
	struct  {
		u 16 ct l : 1;		u 16 ccr:1;	u16 s a :1;
		u 1 6l a : 1;	u16 ca:1;
	u16 mpr:1;	u1 6 czbf s: 1;/ * Clea r Z-B uf f ers  */
		u16 r sv:9 ;
	} bf;	u16 d a ta;
};structsrc_rs c_c trl _blk {	u nsi gn e d i n tctl ; 
	u nsignedin t	ccr; 
	un s i g n ed i ntca;	unsi gned int	sa;	un sign e d i nt	la ;
	un sign ed  intmpr;
union  s rc_dirty	dirty; 
};
/* SRC m ana ge r c on trolb lock * /
u nio n src_m gr_dirt y  {	s t r u ct  {
		u16 enb0:1;
	u 1 6  e nb1:1;
	u16 e n b2 :1 ; 
		u16 e nb 3:1 ;
	u 1 6 enb 4:1; 	u16 enb5 :1;
	u 16  e nb6:1;	u16 en b7 :1; 
	u16 e n bsa: 1;
		u 16 rsv:7 ;
	}b f;
	u16 data;} ;

struct src _ mg r _ ct r l_bl k { 
	unsignedintenbs a;
u ns ign e d int 		enb [8 ] ;union src_mgr_dirty 	d irty;};

/ * SRCIMP mana ger contro l b lock */#def i ne SRCAIM_ARC	0x0 0000F FF
#define SRCAIM_N XT	0x 00FF0000 
#defineS R CAIM_SRC 	0x FF0 000 00s tr uct srcimap
#define SRCCA_CA	0x0FFFFFFF
#define_SRCCA_RS	0xE0000000

#define SRCSA_SA	0x0FFFFFFF

#define_SRCLA_LA	0x0FFFFFFF

/* Mixer Parameter Ring_ram Low_and_Hight register.
_*_Fixed-point value in_8.24 format for_parameter channel */
#define MPRLH_PITCH	0xFFFFFFFF

/*_SRC resource register_dirty_flags */
union src_dirty {
	struct {
		u16 ctl:1;
		u16 ccr:1;
		u16 sa:1;
		u16 la:1;
		u16 ca:1;
		u16 mpr:1;
		u16 czbfs:1;	/* Clear Z-Buffers_*/
		u16_rsv:9;
	} bf;
	u16_data;
};

struct_src_rsc_ctrl_blk_{
	unsigned int	ctl;
	unsigned int 	ccr;
	unsigned int	ca;
	unsigned_int	sa;
	unsigned int	la;
	unsigned int	mpr;
	union src_dirty	dirty;
};

/* SRC_manager control_block */
union src_mgr_dirty {
	struct {
		u16 enb0:1;
		u16 enb1:1;
		u16 enb2:1;
		u16_enb3:1;
		u16_enb4:1;
		u16 enb5:1;
		u16 enb6:1;
		u16_enb7:1;
		u16 enbsa:1;
		u16 rsv:7;
	} bf;
	u16 data;
};

struct src_mgr_ctrl_blk {
	unsigned int		enbsa;
	unsigned int		enb[8];
	union_src_mgr_dirty	dirty;
};

/* SRCIMP manager control block */
#define_SRCAIM_ARC	0x00000FFF
#define SRCAIM_NXT	0x00FF0000
#define SRCAIM_SRC	0xFF000000

struct_srcimap