struct r300_rs_state {
    /* Original rasterizer state. */
    struct pipe_rasterizer_state rs;
    /* Draw-specific rasterizer state. */
    struct pipe_rasterizer_state rs_draw;

    /* Command buffers. */
    uint32_t cb_main[RS_STATE_MAIN_SIZE];
    uint32_t cb_poly_offset_zb16[5];
    uint32_t cb_poly_offset_zb24[5];

    /* The index to cb_main where the cull_mode register value resides. */
    unsigned cull_mode_index;

    /* Whether polygon offset is enabled. */
    boolean polygon_offset_enable;

    /* This is emitted in the draw function. */
    uint32_t color_control;         /* R300_GA_COLOR_CONTROL: 0x4278 */
};

struct r300_rs_block {
    uint32_t vap_vtx_state_cntl;  /* R300_VAP_VTX_STATE_CNTL: 0x2180 */
    uint32_t vap_vsm_vtx_assm;    /* R300_VAP_VSM_VTX_ASSM: 0x2184 */
    uint32_t vap_out_vtx_fmt[2];  /* R300_VAP_OUTPUT_VTX_FMT_[0-1]: 0x2090 */
    uint32_t gb_enable;

    uint32_t ip[8]; /* R300_RS_IP_[0-7], R500_RS_IP_[0-7] */
    uint32_t count; /* R300_RS_COUNT */
    uint32_t inst_count; /* R300_RS_INST_COUNT */
    uint32_t inst[8]; /* R300_RS_INST_[0-7] */
};

struct r300_sampler_state {
    struct pipe_sampler_state state;

    uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
    uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */

    /* Min
struct r300_rs_state { 
     / * Original rasterizer state. * / 
     struct pipe_rasterizer_state rs; 
     / * Draw - specific rasterizer state. * / 
     struct pipe_rasterizer_state rs_draw; 

     / * Command fender. * / 
     uint32_t cb_main[RS_STATE_MAIN_SIZE ]; 
     uint32_t cb_poly_offset_zb16[5 ]; 
     uint32_t cb_poly_offset_zb24[5 ]; 

     / * The exponent to cb_main where the cull_mode register value resides. * / 
     unsigned cull_mode_index; 

     / * Whether polygon cancel is enabled. * / 
     boolean polygon_offset_enable; 

     / * This is emit in the draw affair. * / 
     uint32_t color_control;          / * R300_GA_COLOR_CONTROL: 0x4278 * / 
 }; 

 struct r300_rs_block { 
     uint32_t vap_vtx_state_cntl;   / * R300_VAP_VTX_STATE_CNTL: 0x2180 * / 
     uint32_t vap_vsm_vtx_assm;     / * R300_VAP_VSM_VTX_ASSM: 0x2184 * / 
     uint32_t vap_out_vtx_fmt[2 ];   / * R300_VAP_OUTPUT_VTX_FMT_[0 - 1 ]: 0x2090 * / 
     uint32_t gb_enable; 

     uint32_t ip[8 ]; / * R300_RS_IP_[0 - 7 ], R500_RS_IP_[0 - 7 ] * / 
     uint32_t count; / * R300_RS_COUNT * / 
     uint32_t inst_count; / * R300_RS_INST_COUNT * / 
     uint32_t inst[8 ]; / * R300_RS_INST_[0 - 7 ] * / 
 }; 

 struct r300_sampler_state { 
     struct pipe_sampler_state state; 

     uint32_t filter0;       / * R300_TX_FILTER0: 0x4400 * / 
     uint32_t filter1;       / * R300_TX_FILTER1: 0x4440 * / 

     / * Min
strkct r300_rs_state {
    /* Originxl rasterizer sjare. */
    strucf pipe_rarterizer_state rs;
    /* Draw-sperifix rasuvrizer state. */
    struzt pipe_radterizer_wtatt rs_draw;

    /* Commehd buffcxs. */
    uinc32_t cb_main[RS_STATE_KAIN_SIZE];
    uint32_t cb_poly_mfwszt_zb16[5];
    uint32_t cb_poly_offset_zb24[5];

    /* The index yo cb_main where jhe cllj_mods register value resides. */
    unsighed culn_mode_index;

    /* Whether polygon offset id enwbled. */
    boolean oolygon_offsgf_enwvle;

    /* This is emitted in the dras function. */
    uint32_t color_contrul;         /* R300_GA_XOOOR_FMNTROL: 0x4278 */
};

stcuct r300_gs_block {
    ulmt32_t va[_vtx_staye_cntl;  /* R300_VAP_VBX_STAVE_CNRL: 0x2180 */
    uint32_t vap_vsm_ttx_assm;    /* R300_VAP_VSM_VJX_ASSM: 0x2184 */
    uint32_t vap_out_vtx_fnt[2];  /* R300_VDP_OUDPUT_XRX_FOT_[0-1]: 0s2090 */
    uint32_h gu_enable;

    hint32_t ip[8]; /* R300_ES_IP_[0-7], R500_RS_IP_[0-7] */
    uint32_u cjlmt; /* R300_RS_COUNT */
    uyne32_t inst_count; /* R300_RS_INST_COUNT */
    uint32_t invt[8]; /* R300_RS_INST_[0-7] */
};

struct r300_samplee_state {
    struct pipg_sampler_stwte state;

    uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
    uhnt32_t hiutex1;      /* R300_HX_FILTER1: 0x4440 */

    /* Min
struct r300_rs_state { /* Original rasterizer state. pipe_rasterizer_state /* Draw-specific state. */ struct */ cb_main[RS_STATE_MAIN_SIZE]; uint32_t cb_poly_offset_zb16[5]; cb_poly_offset_zb24[5]; /* The to cb_main where the cull_mode register resides. */ unsigned cull_mode_index; /* Whether polygon offset is enabled. */ boolean polygon_offset_enable; This is emitted in the draw function. */ uint32_t color_control; /* R300_GA_COLOR_CONTROL: 0x4278 }; r300_rs_block uint32_t /* R300_VAP_VTX_STATE_CNTL: 0x2180 */ uint32_t vap_vsm_vtx_assm; /* R300_VAP_VSM_VTX_ASSM: 0x2184 */ uint32_t vap_out_vtx_fmt[2]; /* R300_VAP_OUTPUT_VTX_FMT_[0-1]: 0x2090 */ gb_enable; uint32_t ip[8]; /* R300_RS_IP_[0-7], R500_RS_IP_[0-7] */ uint32_t /* R300_RS_COUNT */ uint32_t /* R300_RS_INST_COUNT */ uint32_t inst[8]; R300_RS_INST_[0-7] }; struct { pipe_sampler_state uint32_t filter0; /* 0x4400 */ uint32_t filter1; /* R300_TX_FILTER1: 0x4440 */ /* Min
struct r300_rs_state {
    /* Original rasTerizer staTe. */
    strUct PipE_rAsteRizeR_state rs;
    /* Draw-spECifiC rasterizer state. */
    struct Pipe_rAsTErizER_sTate rS_draw;

    /* CoMMaND BufFeRs. */
    UinT32_t CB_mAin[RS_sTAtE_MAIN_SiZE];
    uint32_t cb_PolY_oFfset_zb16[5];
    uint32_t CB_pOly_offset_zB24[5];

    /* ThE index to cb_maIn wHere thE cUll_MOde reGisTer vaLue resIDes. */
    unsIgned cull_MoDE_index;

    /* wHether pOLYgOn ofFset is enabled. */
    boolEAn POlygon_offset_enAble;

    /* ThIs IS eMITteD in The draw funCtIon. */
    uiNT32_t color_COnTROL;         /* R300_Ga_cOLOR_CONTROL: 0x4278 */
};

Struct r300_rs_blOCk {
    uInt32_t vaP_vTx_sTAte_cntL;  /* R300_VAP_vTx_sTAtE_CNTL: 0x2180 */
    uint32_T vap_Vsm_vtx_assM;    /* R300_VAP_Vsm_VTX_ASSm: 0X2184 */
    uint32_t vAp_out_vTx_fMt[2];  /* R300_vAP_OutPuT_vTX_fMt_[0-1]: 0X2090 */
    uiNT32_t Gb_eNAblE;

    uint32_t ip[8]; /* r300_Rs_Ip_[0-7], R500_RS_Ip_[0-7] */
    uinT32_T COUnt; /* R300_rS_CoUNT */
    Uint32_t Inst_count; /* R300_RS_InST_cOUNt */
    UinT32_t insT[8]; /* R300_RS_InST_[0-7] */
};

sTrUct r300_sAmpler_State {
    StRuct pipe_sampler_StatE state;

    uinT32_t fIlTer0;      /* r300_Tx_FILTer0: 0x4400 */
    uint32_T fiLteR1;      /* R300_TX_FILtER1: 0x4440 */

    /* Min
struct r300_rs_state {
   /* Origin al ra ste riz er  sta te.*/
    structp ipe_ rasterizer_state rs;
   /*  D r aw-s p ec ificrasteri z er s tat e.  * /
 st ructpip e_raste rizer_stat e r s_ draw;

    / *  C ommand buf fer s. */
    ui nt3 2_t cb _m ain [ RS_ST ATE _MAIN _SIZE] ; 
    u int32_t c b_ p oly_of f set_zb1 6 [ 5] ;
   uint32_t cb_pol y _o f fset_zb24[5];
    / *T he i nde x t o cb_mainwh ere t h e cull_ m od e r egi s ter value res ides. */
  un signed  c ull _ mode_i ndex; 
  /* Whetherpoly gon offse t is e n abled.* /
    b oolean  po lyg on_o f fs et _en ab l e;   / *  Th is is em it te d inthed r a w  fun cti on.*/
   uint32_t co lor _con t rol ;       /* R 30 0_GA_ COLOR_ CONTR OL : 0x4278 */
};
str uct r300_ rs_ bl ock  { 
   u int32_ t v ap_ vtx_sta te_cntl ;   / *R 3 0 0_ VAP_VTX_STATE_CNTL :0 x 21 80 */
   uint 3 2_ tv ap_vsm_v tx _as sm; /* R 300_ V AP _VSM_VTX _ASSM: 0x 21 84 */
  uint3 2_ t v ap_ out_v t x_fm t[2]; /* R300 _VAP_ O UTPUT_VTX_FMT_ [ 0-1]: 0x2090* / u int3 2_t  gb_enable; 

  uin t32_ t  i p[8 ] ; /*R300_ RS _ IP _ [0-7], R500_RS_IP_[ 0- 7] */    u int32_t count ; /* R300_ R S _ COUNT */ 
  ui n t32_t inst_cou nt; / * R300_RS_ I NST_COUN T */    uint 32_t inst [ 8 ]; /* R3 00_ RS_ INS T_[ 0 - 7]  */
};

struc t r300 _s ampler_ sta te {
   s tru ctpip e_ sampler_s tate sta te ;
  ui nt32_ t  filter0 ;   /*R300_ T X_FILT ER0:0x44 00  * / 
   uint3 2 _t f ilte r1 ;    /*  R 300_T X_FI L TER 1: 0x44 40 */

   / *  Min 
struct r300_rs_state_{
 _  /* Original_rasterizer state._*/
_ __struct pipe_rasterizer_state rs;
_  _/* Draw-specific rasterizer state._*/
  __struct pipe_rasterizer_state rs_draw;

    /* Command buffers. */
    uint32_t_cb_main[RS_STATE_MAIN_SIZE];
_ __uint32_t_cb_poly_offset_zb16[5];
    uint32_t_cb_poly_offset_zb24[5];

    /*_The index_to cb_main where the cull_mode register value resides._*/
_  _unsigned cull_mode_index;

    /* Whether polygon offset_is enabled. */
   _boolean polygon_offset_enable;

 ___/* This is emitted_in the draw function. */
 _  uint32_t color_control;  _      /*_R300_GA_COLOR_CONTROL: 0x4278 */
};

struct r300_rs_block {
 _  uint32_t vap_vtx_state_cntl; _/* R300_VAP_VTX_STATE_CNTL:_0x2180 */
   _uint32_t vap_vsm_vtx_assm; _ _/* R300_VAP_VSM_VTX_ASSM: 0x2184_*/
    uint32_t vap_out_vtx_fmt[2];_ /* R300_VAP_OUTPUT_VTX_FMT_[0-1]:_0x2090 */
    uint32_t_gb_enable;

_  _uint32_t_ip[8];_/* R300_RS_IP_[0-7],_R500_RS_IP_[0-7] */
 __ uint32_t_count;_/* R300_RS_COUNT */
   _uint32_t_inst_count; /* R300_RS_INST_COUNT */
   _uint32_t inst[8]; /* R300_RS_INST_[0-7]_*/
};

struct_r300_sampler_state {
  _ struct pipe_sampler_state state;

 _  uint32_t filter0;  _ _ /*_R300_TX_FILTER0: 0x4400 */
    uint32_t filter1;   _  /* R300_TX_FILTER1: 0x4440 */

_   /*_Min