<https://www.edaboard.com/threads/negative-hold-timing-check-in-sdf-file.6317/>
<http://schema.org/articleBody>
"sdf negative timing\n\nAfter synthesizing a VHDL design with Synopsys DC I get negative values\nin the SDF file for HOLD check of the FFs . I am doing simulations with Modelsim and the simulator uses those negative HOLD values by substracting them from the setup time ( If i deliberately make a setup violation closer to the clock edge the simulator does not report any error ).\n\nAnyone can make me understand what neagtive values for the HOLD are intended for ?\nThanks!"
<https://www.edaboard.com/threads/negative-hold-timing-check-in-sdf-file.6317/>