<http://purl.org/dc/terms/description>
"As the gap between memory and processor performance continues to grow, more and more\r\nprograms will be limited in performance: by the memory latency of the system and by the branch\r\ninstructions (control flow of the programs). Meanwhile, due to the increase in complexity of\r\napplication programs over the last decade, object-oriented languages are replacing traditional\r\nlanguages because of convenient code reusability and maintainability. However, it has also been\r\nobserved that the run-time performance of object-oriented programs can be improved by\r\nreducing the impact caused by the memory latency, branch misprediction, and several other\r\nfactors. In this thesis, two new schemes are introduced for reducing the memory latency and\r\nbranch mispredictions for High Performance Computing (HPC).\r\nFor the first scheme, in order to reduce the memory latency, this thesis presents a new cache\r\nscheme called TAC (Thrashing-Avoidance Cache), which can effectively reduce instruction\r\ncache misses caused by procedure call/returns. The TAC scheme employs N-way banks and\r\nXOR mapping functions. The main function of the TAC is to place a group of instructions\r\nseparated by a call instruction into a bank according to the initial and final bank selection\r\nmechanisms. After the initial bank selection mechanism selects a bank on an instruction cache\r\nmiss, the final bank selection mechanism will determine the final bank for updating a cache line\r\nas a correction mechanism. These two mechanisms can guarantee that recent groups of\r\ninstructions exist in each bank safely. A simulation program, TACSim, has been developed by\r\nusing Shade and Spixtools, provided by SUN Microsystems, on an ultra SPARC/10 processor.\r\nOur experimental results show that TAC schemes reduce conflict misses more effectively than\r\nskewed-associative caches in both C (9.29% improvement) and C++ (44.44% improvement) programs on LI caches. In addition, TAC schemes also allow for a significant miss\r\nreduction on Branch Target Buffers (BTB).\r\nFor the second scheme to reduce branch mispredictions, this thesis also presents a new\r\nhybrid branch predictor called the GoStay2 that can effectively reduce misprediction\r\nrates for indirect branches. The GoStay2 has two different mechanisms compared to other\r\n2-stage hybrid predictors that use a Branch Target Buffer (BTB) as the first stage\r\npredictor: First, to reduce conflict misses in the first stage, an effective 2-way cache\r\nscheme is used instead of a 4-way set-associative scheme. Second, to reduce\r\nmispredictions caused by an inefficient predict and update rule, a new selection\r\nmechanism and update rule are proposed. A simulation program, GoS-Sim, has been\r\ndeveloped by using Shade and Spixtools, provided by SUN Microsystems, on an Ultra\r\nSPARC/10 processor. Our results show significant improvement with these mechanisms\r\ncompared to other hybrid predictors. For example, the GoStay2 improves indirect\r\nmisprediction rates of a 64-entry to 4K-entry BTB (with a 512- or lK-entry PHT) by\r\n14.9% to 21.53% compared to the Cascaded predictor (with leaky filter)."@en
<https://open.library.ubc.ca/cIRcle/collections/ubctheses/831/items/1.0065352>