<http://schema.org/description>
"...Technically Lead a Team of 2/3 Engineers\n\nTake Complete Ownership of Modules -\u00A0Microarchitecture,\u00A0Design,\u00A0Synthesis &amp; Timing Closure, FPGA Bring up\n\nAbility to Independently Contribute in as many\u00A0areas of ASIC &amp; FPGA design flow including Synthesis, STA, DFT, FPGA\n\nAbility to understand Protocols, Standards,\u00A0and Implementation\u00A0of the same in Verilog/System Verilog/VHDL\n\nExperience in Processor Based Designs, USB, Ethernet, Networking\n\n\u00A0\n\nJob Requirements\n\nStrong Skills and Aptitude for Design..."^^<http://www.w3.org/2001/XMLSchema#string>
<https://tapwage.com/city/1264520-madurantakam-india/managerial/jobs>