0110 Memory Read This performs a read cycle from memory space. Because the smallest memory space a PCI device is permitted to implement is 16 bytes, the two least significant bits of the address are not needed during the address phase; equivalent information will arrive during the data phases in the form of byte select signals. They instead specify the order in which burst data must be returned. If a device does not support the requested order, it must provide the first word and then disconnect. If a memory space is marked as "prefetchable", then the target device must ignore the byte-select signals on a memory read and always return 32 valid bits.
0110 Memory Read This performs a read cycle from memory space. Because the smallest memory space a PCI device is permitted to implement is 16 bytes the two least significant bits of the address are not needed during the address phase; equivalent information will arrive during the data phases in the form of byte select signals They instead specify the order in which burst data must be returned. If a device does not support the requested order, it must provide the first word and then disconnect. If a memory space is marked as "prefetchable" then the target device must ignore the byte-select signals on a memory read and always return 32 valid bits.