Power-on reset with timing control to reset the CPU without interrupting the periodic refresh cycles produced by the Z80 Gating to reset the Z80-PIO (the Z80-PIO has no dedicated reset input) A reset-jump circuit that allowed the Z80-CPU to start execution from any 4-Kbyte boundary after reset (the Z80-CPU usually fetches from address 0 after reset). This allowed, for example, control to be passed straight to the BASIC interpreter after reset. Microsoft BASIC in an 8Kbyte ROM. Two groups of 4 uncommitted 24-pin DIL sockets. Each group could be configured to accommodate 1Kx8 ROM or RAM devices and decoded at a start address of 0x1000, 0x2000, 0xB000, 0xC000 or 0xD000. A 24-pin DIL socket that could accommodate a second character-generator ROM Full buffering of the CPU address, data and control to generate the "NAS-BUS" expansion bus.
Power-on reset with timing control to reset the CPU without interrupting the periodic refresh cycles produced by the Z80 Gating to reset the Z80-PIO (the Z80-PIO has no dedicated reset input) A reset-jump circuit that allowed the Z80-CPU to start execution from any 4-Kbyte boundary after reset (the Z80-CPU usually fetches from address 0 after reset). This allowed, for example, control to be passed straight to the BASIC interpreter after reset. Microsoft BASIC in an 8Kbyte ROM. Two group,s of 4 uncommitted 24-pin DIL sockets. Each group could be configured to accommodate 1Kx8 ROM or RAM devices and decoded at a start address of 0x1000, 0x2000 0xB000, 0xC000 or 0xD000. A 24-pin DIL socket that could accommodate a second character-generator ROM Full buffering of the CPU address, data and control to generate the "NAS-BUS" expansion bus.