This is slightly greater than 2.048 Mbit/s + 50ppm. If an extra gap is added, this is slightly smaller than 2.048 Mbit/s – 50ppm. Thus on average the data rate can be made exactly equal to the incoming rate by adding a gap in some frames and not others. This extra gap is in a fixed place in the frame and is referred to as the "stuffable bit". If it does not contain data (i.e. it's a gap) it is "stuffed". The data from the 4 data streams in now contained in 4 data streams of 2.112 Mbit/s which are synchronous and can easily be multiplexed to give a single stream of 8.448 Mbit/s by taking 1 bit from stream #1, followed by 1 bit from stream #2, then #3, then #4 etc. Some of the fixed gaps accommodate a synchronisation word which allows the demultiplexer to identify the start of each frame and others contain control bits for each stream which say whether or not the stuffable bit is stuffed or not (i.e. contains data or not). The process can then be reversed by the demultiplexer and 4 data streams produced with exactly the same bit rate as previous. The timing irregularity is ironed out using a phase locked loop.
This is slightly greater than 2.048 Mbit/s + 50ppm. If an extra gap is added, this is slightly smaller than 2.048 Mbit/s – 50ppm. Thus on average the data rate can be made exactly equal to the incoming rate by adding a gap in some frames and not others. This extra gap is in a fixed place in the frame and is referred to as the "stuffable bit". If it does not contain data (i.e. it's a gap) it is "stuffed" The data from the 4 data streams in now contained in 4 data streams of 2.112 Mbit/s which are synchronous and can easily be multiplexed to give a single stream of 8.448 Mbit/s by taking 1 bit from stream #1, followed by 1 bit from stream #2, then #3, then #4 etc. Some of the fixed gaps accommodate a synchronisation word which allows the demultiplexer to identify the start of each frame and others contain control bits for each stream which say whether or not the stuffable bit is stuffed or not (i.e. contains data or not). The process can then be reversed by the demultiplexer and 4 data streams produced with exactly the same bit rate as previous. The timing irregularity is ironed out using a phase locked loop.