DMA can lead to cache coherency problems. Imagine a CPU equipped with a cache and an external memory that can be accessed directly by devices using DMA. When the CPU accesses location X in the memory, the current value will be stored in the cache. Subsequent operations on X will update the cached copy of X, but not the external memory version of X, assuming a write-back cache. If the cache is not flushed to the memory before the next time a device tries to access X, the device will receive a stale value of X.
dma can lead to cache coherency problems imagine a cpu equipped with a cache and an external memory that can be accessed directly by devices using dma when the cpu accesses location x in the memory the current value will be stored in the cache subsequent operations on x will update the cached copy of x but not the external memory version of x assuming a write-back cache if the cache is not flushed to the memory before the next time a device tries to access x the device will receive a stale value of x