Hidden refresh Given support of -before- refresh, it is possible to deassert while holding low to maintain data output. If is then asserted again, this performs a CBR refresh cycle while the DRAM outputs remain valid. Because data output is not interrupted, this is known as hidden refresh. Hidden refresh is no faster than a normal read followed by a normal refresh, but does maintain the data output valid during the refresh cycle.
Hidden refresh Given support of -before- refresh, it is possible to deassert while holding low to maintain data output If is then asserted again, this performs a CBR refresh cycle. while the DRAM outputs remain valid. Because data output is not interrupted, this is known as hidden refresh. Hidden refresh is no faster than a normal read followed by a normal refresh, but does maintain the data output valid during the refresh cycle.