IBM S/370 registers+ General Registers 0–15 Two's complement value 0 31+ Control Registers 0–15 See Principles of Operation 0 31+ Floating Point Registers 0–6 S Biased exponent Mantissa 0 1 7 8 31 Mantissa (continued) 32 63+ S/370 Basic Control mode PSW Chan.Mask IO EX Key 0 M W P Interruption Code 0 1 2 4 5 6 7 8 11 12 13 14 15 16 31 ILC CC ProgramMask Instruction Address 32 33 34 35 36 39 40 63+ Bits Field Meaning 0–5 Channel Masks for channels 0–5 6 IO I/O Mask for channels > 5 7 EX External Mask 8–11 Key PSW key 12 E=0 Basic Control mode 13 M Machine-check mask 14 W Wait state 15 P Problem state 16–31 IC Interruption Code 32–33 ILC Instruction-Length Code 34–35 CC Condition Code 36–39 PM Bit Meaning 36 Fixed-point overflow 37 Decimal overflow 38 Exponent underflow 39 Significance 40–63 IA Instruction Address+ S/370 Extended Control mode PSW 0 R 0 0 0 T IO EX Key 1 M W P S 0 CC ProgramMask 0 0 0 0 0 0 0 0 0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31 0 0 0 0 0 0 0 0 Instruction Address 32 63+ Bits Field Meaning 1 R PER Mask 5 T DAT mode 6 IO I/O Mask; subject to channel mask in CR2 7 EX External Mask; subject to external subclass mask in CR0 8–11 Key PSW key 12 E=1 Extended Control mode 13 M Machine-check mask 14 W Wait state 15 P Problem state 16 S Address-Space Control0=primary-space mode1=Secondary-space mode 18–19 CC Condition Code 20–23 PM Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 Exponent underflow 23 Significance 40–63 IA Instruction Address S/370 also refers to a computer system architecture specification, and is a direct and mostly backward compatible evolution of the System/360 architecture from which it retains most aspects. This specification does not make any assumptions on the implementation itself, but rather describes the interfaces and the expected behavior of an implementation. The architecture describes mandatory interfaces that must be available on all implementations and optional interfaces which may or may not be implemented.
ibm s/370 registers+ general registers 0–15 two's complement value 0 31+ control registers 0–15 see principles of operation 0 31+ floating point registers 0–6 s biased exponent mantissa 0 1 7 8 31 mantissa (continued) 32 63+ s/370 basic control mode psw chanmask io ex key 0 m w p interruption code 0 1 2 4 5 6 7 8 11 12 13 14 15 16 31 ilc cc programmask instruction address 32 33 34 35 36 39 40 63+ bits field meaning 0–5 channel masks for channels 0–5 6 io i/o mask for channels > 5 7 ex external mask 8–11 key psw key 12 e=0 basic control mode 13 m machine-check mask 14 w wait state 15 p problem state 16–31 ic interruption code 32–33 ilc instruction-length code 34–35 cc condition code 36–39 pm bit meaning 36 fixed-point overflow 37 decimal overflow 38 exponent underflow 39 significance 40–63 ia instruction address+ s/370 extended control mode psw 0 r 0 0 0 t io ex key 1 m w p s 0 cc programmask 0 0 0 0 0 0 0 0 0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31 0 0 0 0 0 0 0 0 instruction address 32 63+ bits field meaning 1 r per mask 5 t dat mode 6 io i/o mask; subject to channel mask in cr2 7 ex external mask; subject to external subclass mask in cr0 8–11 key psw key 12 e=1 extended control mode 13 m machine-check mask 14 w wait state 15 p problem state 16 s address-space control0=primary-space mode1=secondary-space mode 18–19 cc condition code 20–23 pm bit meaning 20 fixed-point overflow 21 decimal overflow 22 exponent underflow 23 significance 40–63 ia instruction address s/370 also refers to a computer system architecture specification and is a direct and mostly backward compatible evolution of the system/360 architecture from which it retains most aspects this specification does not make any assumptions on the implementation itself but rather describes the interfaces and the expected behavior of an implementation the architecture describes mandatory interfaces that must be available on all implementations and optional interfaces which may or may not be implemented