8. A non-transitory computer readable medium storing instructions that, when executed by a processor, perform a method for containing analog verification intellectual property (IP) for circuit simulation, the method comprising: using a computer, reading an analog verification file containing at least one analog verification unit (vunit) that contains properties describing analog circuit design verification requirements including checks for specified simulation results, wherein the analog verification file is separate from input design IP; binding the vunit to one of a top-level circuit, a subcircuit master, and a subcircuit instance during circuit hierarchy expansion, to set vunit scope; performing a circuit simulation with a computer-operated circuit simulation tool combining the input design IP and the analog circuit design verification requirements; and tangibly outputting circuit simulation and verification results.
8. A non-transitory computer readable medium storing instructions that, when executed by a processor, perform a method for containing analog verification intellectual property (IP) for circuit simulation, the method comprising: using a computer, reading an analog verification file containing at least one analog verification unit (vunit) that contains properties describing analog circuit design verification requirements including checks for specified simulation results, wherein the analog verification file is separate from input design IP; binding the vunit to one of a top-level circuit, a subcircuit master, and a subcircuit instance during circuit hierarchy expansion, to set vunit scope; performing a circuit simulation with a computer-operated circuit simulation tool combining the input design IP and the analog circuit design verification requirements; and tangibly outputting circuit simulation and verification results. 11. The medium of claim 8 wherein the vunit contents comprise at least one of static circuit checks, dynamic circuit checks, PSL assertions, clock statements, legacy assertions, and auxiliary instance statements that monitor signals and produce derived outputs.