8. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising: detecting a presence of a combinational loop in an expression netlist representation of a circuit design by identifying a portion of the expression netlist having at least one characteristic associated with the combinational loop, translating the identified portion of the expression netlist into a bit-level circuit representation, and utilizing the bit-level circuit representation to determine the identified portion of the expression netlist includes the combinational loop; and modifying the expression netlist corresponding to the detected presence of the combinational loop.
8. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising: detecting a presence of a combinational loop in an expression netlist representation of a circuit design by identifying a portion of the expression netlist having at least one characteristic associated with the combinational loop, translating the identified portion of the expression netlist into a bit-level circuit representation, and utilizing the bit-level circuit representation to determine the identified portion of the expression netlist includes the combinational loop; and modifying the expression netlist corresponding to the detected presence of the combinational loop. 11. The apparatus of claim 8 , wherein identifying the portion of the expression netlist having the at least one characteristic associated with the combinational loop further comprises computing a strongly connected component in the expression netlist, the strongly connected component corresponding to the identified portion of the expression netlist having the at least one characteristic associated with the combinational loop.