1. A distributive function information processing system made up of interconnected processing elements for use in combination with one or more input or output devices such as display devices, keyboards, printers, cathode ray tubes and data links, comprising: a. a plurality of processing elements including: (1) one or more data processors for receiving, transforming and transmitting data in response to control signals, and (2) two or more control processors for generating and transmitting control signals for operating said system; b. a plurality of control arcs interconnecting said processing elements into a system, each said control arc consisting of: (1) control arc logic circuitry for generating and transmitting said control signals constituting a control arc transmitter, (2) control arc logic circuitry for receiving and interpreting said control signals constituting a control arc receiver, and (3) electrical connectors constituting control arc communication lines interconnecting said control arc transmitter and said control arc receiver into a control arc for conveying said control signals from transmitter to the receiver and for conveying responses to said control signals from receiver to transmitter whereby each control arc can pass said control signals in the direction from transmitter to receiver, said control arc logic circuits being located in and forming a part of said processing elements with the two logic circuits of each control arc being located in a different processing element with control arc transmitters being located only in said control processors, with control arc receivers being located in either control processors or data processors and with at least one control processor containing a control arc receiver whereby each control arc interconnects two processing elements for interconnecting said processing elements into said system, wherein the number of control arcs is equal to or greater than the total number of control and data processors, wherein said control arcs interconnecting two or more of the processing elements in a system describe a loop and wherein one said control processor includes, in addition to the control arc logic circuitry constituting a portion of one or more said control arcs, state defined control circuitry permitting said one control processor to assume, in turn, two or more different states to have state defined control whereby the control function performed by said one control processor depends in part on its state; c. input and output data lines for connecting one or more processing elements with one or more said input or output devices wherein the network created by processing elements when interconnected by said control arcs defines a mathematical graph in the sense of graph mathematics over the processing elements and wherein said processing elements constitute the nodes of the graph; and d. data path means for movement of data among said processing elements, said electrical connectors constituting control arc communication lines also constituting means for movement of data in the same direction as said control signals are moved thereby constituting a portion of said data path means; whereby said system may accept data from said input device, operate and transform data using a control scheme based on graph theory mathematics and produce data usable by said output device.
1. A distributive function information processing system made up of interconnected processing elements for use in combination with one or more input or output devices such as display devices, keyboards, printers, cathode ray tubes and data links, comprising: a. a plurality of processing elements including: (1) one or more data processors for receiving, transforming and transmitting data in response to control signals, and (2) two or more control processors for generating and transmitting control signals for operating said system; b. a plurality of control arcs interconnecting said processing elements into a system, each said control arc consisting of: (1) control arc logic circuitry for generating and transmitting said control signals constituting a control arc transmitter, (2) control arc logic circuitry for receiving and interpreting said control signals constituting a control arc receiver, and (3) electrical connectors constituting control arc communication lines interconnecting said control arc transmitter and said control arc receiver into a control arc for conveying said control signals from transmitter to the receiver and for conveying responses to said control signals from receiver to transmitter whereby each control arc can pass said control signals in the direction from transmitter to receiver, said control arc logic circuits being located in and forming a part of said processing elements with the two logic circuits of each control arc being located in a different processing element with control arc transmitters being located only in said control processors, with control arc receivers being located in either control processors or data processors and with at least one control processor containing a control arc receiver whereby each control arc interconnects two processing elements for interconnecting said processing elements into said system, wherein the number of control arcs is equal to or greater than the total number of control and data processors, wherein said control arcs interconnecting two or more of the processing elements in a system describe a loop and wherein one said control processor includes, in addition to the control arc logic circuitry constituting a portion of one or more said control arcs, state defined control circuitry permitting said one control processor to assume, in turn, two or more different states to have state defined control whereby the control function performed by said one control processor depends in part on its state; c. input and output data lines for connecting one or more processing elements with one or more said input or output devices wherein the network created by processing elements when interconnected by said control arcs defines a mathematical graph in the sense of graph mathematics over the processing elements and wherein said processing elements constitute the nodes of the graph; and d. data path means for movement of data among said processing elements, said electrical connectors constituting control arc communication lines also constituting means for movement of data in the same direction as said control signals are moved thereby constituting a portion of said data path means; whereby said system may accept data from said input device, operate and transform data using a control scheme based on graph theory mathematics and produce data usable by said output device. 9. The distributive function information processing system of claim 1 wherein one or more processing elements constitute a programmable digital display machine subsystem providing for control and operation of visual images on at least two dissimilar display devices from a common string of data words which defines the images to be displayed and providing storage for and use of complex visual images made up of more simple display images which in turn may consist of still more simple display images comprising: a. a display control unit designated a DSPL control processor for generating instructions for portions of the subsystem from a higher level definition of display images originating within the display subsystem or elsewhere in said system including: (1) rule memory means for storing data representing rules defining the visual images to be generated, (2) instruction processing means for receiving and carrying out instructions received from another processing element in the system, (3) programmable control circuitry means responsive to data stored in said rule memory means for generating signals to cause said programmable digital display machine subsystem to perform operations, said signals including signals meaning: (a) scan display program characters from at least two sources, (b) convert strings of characters, (c) change rule states, (d) issue instructions to other portions of the subsystem, (e) access data from other portions of the subsystem, and (f) discontinue interpretation of display program, (4) comparator, stack and state register means for determining which rule is to be used, (5) means including control arc means for issuing instructions to other processing elements wherein at least one is a symbol processor, (6) data multiplexer and register accessing means for accessing data produced by said other processing elements including said symbol processor; whereby said DSPL control processor can define images to be displayed in a lower level machine language responsive to instructions received in a higher level language; b. a display interface unit designated a DIU data processor for interconnecting the display subsystem with at least two dissimilar display devices including: (1) means including a control arc receiver and an input instruction register for receiving instructions from said DSPL control processor, (2) means including a micro code generation memory and a timing generator circuit for controlling the execution of each instruction received from said DSPL control processor, (3) means including a memory and counters for accessing individual bits in said memory for data representing each dot of dots representing a primitive visual image for generating a dot pattern representing a predefined primitive visual image, (4) means including an adder, a four location random access memory and a cursor movement read only memory for computing and storing a cursor value representing the x and y coordinates of the desired location on the screen of a display device for showing a primitive visual image wherein said read only memory defines the numbers to be added to an existing cursor value to determine a new cursor value as a function of the instruction being executed and contains numbers which define exactly the value that one or more values of the random access locations are to assume for a given instruction, (5) means including counters, multiplexers, flip-flops and gates for generating addresses and control signals for creating a display on a flat panel plasma display, (6) counter and gating means for generating addresses and control signals for a refresh memory to allow construction of an x and y coordinate oriented dot image, (7) a refresh memory, and (8) counter and multiplexer means for reading out of said refresh memory a serial stream of data in the sequence needed by a raster-scan cathode ray display device to allow display of the image on said cathode ray display device; c. a symbols data processing element, designated a SYM data processor for generating symbols data including: (1) means including a control arc receiver and an input instruction register for receiving instructions from said DSPL control processor, (2) means including an output data register for holding data results for use by said DSPL processor, (3) means including a micro code generation read only memory and a timing circuit for controlling the execution of each instruction received from said DSPL, (4) symbol storage means, including a random access memory storage means, a symbol register and addressing circuitry for sequentially accessing data characters in a string, for storing character data representing the definition of a plurality of symbols wherein each symbol definition is a string having an associated start location in said storage means, wherein the last character for the definition of each string in the storage means is a symbol end character and wherein the other characters in such string represent characters for display controls, (5) symbol name starting address location memory means including a random access memory, a register, addressing circuitry and interconnections with other components of SYM for storing the starting address of symbols in the starting address memory, for allowing the output of said starting address memory means to be loaded into said symbol storage address register means and for allowing an output of said symbol storage means representing the name of a symbol to be used as the address of the starting address memory whereby one symbol may refer to yet another symbol in its definition, and (6) return address stack memory including an address stack circuit and interconnection with the symbol storage address register means for the transfer of memory addresses, for storing the addresses of symbol memory locations for use after completion of the execution of a symbol string in those instances in which the symbol is referred to by another more complex symbol.