1. A computer-implemented method for design analysis comprising: obtaining a high-level design which includes a word-level representation; obtaining a bit-level representation of the high-level design; determining, using one or more processors, a map between the word-level representation and the bit-level representation; optimizing the bit-level representation; and lifting results from the optimizing of the bit-level representation and including the results in the word-level representation based on the map wherein the lifting includes creating an isomorph of the bit-level representation within the word-level representation and where the creating an isomorph includes mapping bit-level nets to corresponding nets within the word-level representation where the bit-level nets are merged, identifying nets from the bit-level representation that are merged, and merging the corresponding nets within the word-level representation.
1. A computer-implemented method for design analysis comprising: obtaining a high-level design which includes a word-level representation; obtaining a bit-level representation of the high-level design; determining, using one or more processors, a map between the word-level representation and the bit-level representation; optimizing the bit-level representation; and lifting results from the optimizing of the bit-level representation and including the results in the word-level representation based on the map wherein the lifting includes creating an isomorph of the bit-level representation within the word-level representation and where the creating an isomorph includes mapping bit-level nets to corresponding nets within the word-level representation where the bit-level nets are merged, identifying nets from the bit-level representation that are merged, and merging the corresponding nets within the word-level representation. 19. The method of claim 1 further comprising evaluating the bit-level representation and the word-level representation for equivalence.