5. The system of claim 1 , wherein the processor is further configured to at least modify the output of the sequential content by increasing or decreasing a speed at which the sequential content is output.
5. The system of claim 1 , wherein the processor is further configured to at least modify the output of the sequential content by increasing or decreasing a speed at which the sequential content is output. 6. The system of claim 5 , wherein increasing the speed at which the sequential content is output includes skipping output of one or more segments of the sequential content.