1. A method to provide a capacitance to a design an integrated circuit comprising: receiving using a processor a layout of the integrated circuit; applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model representing a device having a plurality of first conductors to capture a first capacitance and a second type canonical model representing at least a portion of the device and one or more second conductors of the integrated circuit outside the device to capture a second capacitance; and determining a capacitance for the layout based on the applying.
1. A method to provide a capacitance to a design an integrated circuit comprising: receiving using a processor a layout of the integrated circuit; applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model representing a device having a plurality of first conductors to capture a first capacitance and a second type canonical model representing at least a portion of the device and one or more second conductors of the integrated circuit outside the device to capture a second capacitance; and determining a capacitance for the layout based on the applying. 2. The method of claim 1 , further comprising determining one or more third conductors of a first domain of the layout; selecting the first type canonical model for the first domain based on the one or more third conductors; determining one or more fourth conductors of a second domain of the layout; selecting the second type canonical model for the second domain based on the one or more fourth conductors.