3. The system of claim 3, wherein said register means includes a plurality of addressable storage locations for holding said words and means associated with each of said locations for pointing to the next of said locations receiving a word from said input source, so that as words in said register means are accepted by said output circuit in a substantially unpredictable sequence, storage locations holding the accepted words are reusable, while said means for pointing permits said initiating of said word transfers to be based on the order in which said words are received by the system from the input source.
3. The system of claim 3, wherein said register means includes a plurality of addressable storage locations for holding said words and means associated with each of said locations for pointing to the next of said locations receiving a word from said input source, so that as words in said register means are accepted by said output circuit in a substantially unpredictable sequence, storage locations holding the accepted words are reusable, while said means for pointing permits said initiating of said word transfers to be based on the order in which said words are received by the system from the input source. 4. The system of claim 3, further including means for sequentially storing addresses of locations in said register means corresponding to negatively acknowledged transfers.