9. A computer system in accordance with claim 3 wherein: said processor control programs and logic include command sequences that interpret the contents of said data vector memory to be the starting addresses of speech data segments in said speech data segment memory.
9. A computer system in accordance with claim 3 wherein: said processor control programs and logic include command sequences that interpret the contents of said data vector memory to be the starting addresses of speech data segments in said speech data segment memory. 10. A computer system in accordance with claim 9 wherein said speech processor includes: a time dealy mechanism within said processor control programs and logic arranged to cause said speech processor to pause for a variable length of time in response to th scanning of certain patterns of the command data entries within said command memory.