14. The distributed function programmable digital information processing system of claim 13 wherein: a. two or more control processors each include at least one system control logic signal receiver and are so interconnected by their control arcs and with at least one other processing element so that those processing elements along with their interconnecting control arcs describe a loop including three or more processing elements; and b. two or more control processors have state defined control of which at least one is one of said control processors forming said loop described by three or more processing elements and their interconnecting control arcs.
14. The distributed function programmable digital information processing system of claim 13 wherein: a. two or more control processors each include at least one system control logic signal receiver and are so interconnected by their control arcs and with at least one other processing element so that those processing elements along with their interconnecting control arcs describe a loop including three or more processing elements; and b. two or more control processors have state defined control of which at least one is one of said control processors forming said loop described by three or more processing elements and their interconnecting control arcs. 15. The distributed function programmable digital information system of claim 14 wherein: a. there is at least a third control processor having at least one system control logic signal receiver; b. said third control processor is a part of said loop formed by said two or more control processors; and c. said loop consists only of three or more control processors interconnected by control arcs which are oriented so that the direction of transmitter to receiver of the control arcs is continuous around the loop; whereby said loop constitutes a directed cycle permitting application of a theory of operation based on the directed graph theory of mathematics.