10. A distributed function programmable digital information processing system for use in combination with at least one input-output device such as a keyboard, a mass memory device, a display device, a cathode ray tube, a data link and the like to constitute a complete information processing system, said system comprising: a. a plurality of processing elements including: (1) a plurality of data processors for performing data transformations on data received from other said processing elements or from one or more input-output devices and for causing transfers of data to other said processing elements or to one or more said input-output devices, said data processors each including control logic circuitry including at least one control logic instruction receiver for receiving, interpreting, and initiating said data transformations or transfers in response to control logic instructions received, said receivers also having means for transmitting responses to control logic instructions received, and (2) a plurality of control processors for controlling said data processors, other said control processors and said system by means of control logic instructions, said control processors each including control logic circuitry including at least one control logic instruction transmitter for generating and transmitting control logic instructions in response to one or more of: (a) data received from one or more said input-output devices, (b) data received from another said processing element, and (c) control logic instructions received from another said control processor, said transmitters also having means for receiving responses to control logic instructions transmitted, at least one said control processor having control logic circuitry which also includes at least one control logic instruction receiver to permit that said control processor to receive as well as transmit control logic instructions whereby an instruction generated and transmitted may be in response to an instruction received, and at least one said control processor having control logic circuitry which also includes state defined control circuitry permitting said control processor to assume, in turn, two or more different states whereby said control processor is said to have state defined control and whereby a control logic instruction generated by it is in part a function of its state; and b. electrical circuit lines interconnecting said processing elements into a heterohierarchic functional grouping and interconnecting said processing elements with other devices including: (1) external lines for interconnecting processing elements of said system with input-output devices, (2) a plurality of dedicated control logic instruction line sets, each set having two or more electrical conductors and connecting one said instruction transmitter or one said control processor to one said instruction receiver of another said processing element to constitute with said transmitter and receiver a control arc for interconnecting two different processing elements for communication of said instructions, each of said plurality of sets connecting one processing element to one other processing element to connect all of the processing elements into a single system, and (3) data lines in addition to said dedicated control logic instruction line sets for carrying said data among said processing elements, whereby the network created by said processing elements when interconnected by said dedicated control logic instruction line sets defines a mathematical graph in the sense of graph mathematics over the processing elements with said processing elements constituting the nodes of the graph permitting a theory of operation based on the theory of mathematics.
10. A distributed function programmable digital information processing system for use in combination with at least one input-output device such as a keyboard, a mass memory device, a display device, a cathode ray tube, a data link and the like to constitute a complete information processing system, said system comprising: a. a plurality of processing elements including: (1) a plurality of data processors for performing data transformations on data received from other said processing elements or from one or more input-output devices and for causing transfers of data to other said processing elements or to one or more said input-output devices, said data processors each including control logic circuitry including at least one control logic instruction receiver for receiving, interpreting, and initiating said data transformations or transfers in response to control logic instructions received, said receivers also having means for transmitting responses to control logic instructions received, and (2) a plurality of control processors for controlling said data processors, other said control processors and said system by means of control logic instructions, said control processors each including control logic circuitry including at least one control logic instruction transmitter for generating and transmitting control logic instructions in response to one or more of: (a) data received from one or more said input-output devices, (b) data received from another said processing element, and (c) control logic instructions received from another said control processor, said transmitters also having means for receiving responses to control logic instructions transmitted, at least one said control processor having control logic circuitry which also includes at least one control logic instruction receiver to permit that said control processor to receive as well as transmit control logic instructions whereby an instruction generated and transmitted may be in response to an instruction received, and at least one said control processor having control logic circuitry which also includes state defined control circuitry permitting said control processor to assume, in turn, two or more different states whereby said control processor is said to have state defined control and whereby a control logic instruction generated by it is in part a function of its state; and b. electrical circuit lines interconnecting said processing elements into a heterohierarchic functional grouping and interconnecting said processing elements with other devices including: (1) external lines for interconnecting processing elements of said system with input-output devices, (2) a plurality of dedicated control logic instruction line sets, each set having two or more electrical conductors and connecting one said instruction transmitter or one said control processor to one said instruction receiver of another said processing element to constitute with said transmitter and receiver a control arc for interconnecting two different processing elements for communication of said instructions, each of said plurality of sets connecting one processing element to one other processing element to connect all of the processing elements into a single system, and (3) data lines in addition to said dedicated control logic instruction line sets for carrying said data among said processing elements, whereby the network created by said processing elements when interconnected by said dedicated control logic instruction line sets defines a mathematical graph in the sense of graph mathematics over the processing elements with said processing elements constituting the nodes of the graph permitting a theory of operation based on the theory of mathematics. 12. The distributed function programmable digital information processing system of claim 10 wherein: a. three or more said control processors have control logic circuitry having at least one said instruction receiver; b. two or more said control processors have state defined control; and c. three or more said control processors having an instruction receiver including at least one also having state defined control are so connected by control arcs into a loop with the control arc direction of the transmitter to receiver being continuous around said loop to cause said loop to constitute a directed cycle whereby the theory of operation based on the graph theory of mathematics is permitted to be that of the directed graph theory of mathematics.