17. The method of logic synthesis of claim 16, and further comprising: prior to transforming the nodes having the attribute indicating the structure dominance level, transforming the nodes having the attribute indicating the direct mapping level; and if direct mapping for a node fails, transforming the node as though it had the attribute for the structure dominance level.
17. The method of logic synthesis of claim 16, and further comprising: prior to transforming the nodes having the attribute indicating the structure dominance level, transforming the nodes having the attribute indicating the direct mapping level; and if direct mapping for a node fails, transforming the node as though it had the attribute for the structure dominance level. 18. The method of logic synthesis of claim 17, wherein if direct mapping and structure dominance level transforming steps fail to generate any matches, unconstrained technology mapping at the open control level is permitted thereby rendering the register transfer level statements describing the target logic system technology independent.