2. The method of claim 1 , further comprising creating placement data that defines locations of components in the part of the logic comprising the at least one time sensitive path.
2. The method of claim 1 , further comprising creating placement data that defines locations of components in the part of the logic comprising the at least one time sensitive path. 3. The method of claim 2 , further comprising: merging a new hardware description language design with the structured hardware description language design of the part of the logic comprising at least one time sensitive path to create a merged hardware description language design; and synthesizing the merged hardware description language design, using the placement data, to create a physical representation of the merged hardware description language design.