35. A data processing system according to claim 34 wherein said memory processor sequentially receives two first data packets from the first bus during two successive bus cycles of the first bus before said memory processor assembles the two first data packets into a group, the resulting group being transmitted over the second bus on a next succeeding bus cycle of the second bus.
35. A data processing system according to claim 34 wherein said memory processor sequentially receives two first data packets from the first bus during two successive bus cycles of the first bus before said memory processor assembles the two first data packets into a group, the resulting group being transmitted over the second bus on a next succeeding bus cycle of the second bus. 37. A data processing system according to claim 35 wherein each of the plurality of first sub-packets comprises a word.