16. The system of claim 12 , wherein: for at least a first node in the directed graph the system realizes the node by special purpose circuitry, and a model implementation associated with the first node is configured to be executed by the special purpose circuitry; and for at least a second node in the directed graph system realizes the node by a general purpose microprocessor, and a model implementation associated with the second node is configured to be executed by the general purpose microprocessor.
16. The system of claim 12 , wherein: for at least a first node in the directed graph the system realizes the node by special purpose circuitry, and a model implementation associated with the first node is configured to be executed by the special purpose circuitry; and for at least a second node in the directed graph system realizes the node by a general purpose microprocessor, and a model implementation associated with the second node is configured to be executed by the general purpose microprocessor. 17. The computer-implemented method of claim 16 , wherein the special purpose circuitry is an ASIC.