3. The computer implemented method recited in claim 1 , wherein the formal clock domain crossing verification process comprises: selecting a clock domain crossing boundary from the verification queue; extracting a portion of the device design, the extracted portion of the device design containing the selected clock domain crossing boundary; synthesizing a clock domain crossing assertion based at least in part on the selected clock domain crossing boundary and the extracted portion of the device design; applying a clock domain crossing protocol check on the synthesized clock domain crossing assertion, the clock domain crossing protocol check producing an outcome; and determining if the selected clock domain crossing boundary should be included in the set of clock domain crossing boundaries to be promoted based on the outcome.
3. The computer implemented method recited in claim 1 , wherein the formal clock domain crossing verification process comprises: selecting a clock domain crossing boundary from the verification queue; extracting a portion of the device design, the extracted portion of the device design containing the selected clock domain crossing boundary; synthesizing a clock domain crossing assertion based at least in part on the selected clock domain crossing boundary and the extracted portion of the device design; applying a clock domain crossing protocol check on the synthesized clock domain crossing assertion, the clock domain crossing protocol check producing an outcome; and determining if the selected clock domain crossing boundary should be included in the set of clock domain crossing boundaries to be promoted based on the outcome. 6. The computer implemented method recited in claim 3 , wherein the clock domain crossing protocol check is a gray code check, or a first in first out check, or a handshaking check, or an N-cycle stability check.