2. The method of testing according to claim 1 including providing additional input lines to each of said AND gates so that said AND gates can be individually and uniquely addressed.
2. The method of testing according to claim 1 including providing additional input lines to each of said AND gates so that said AND gates can be individually and uniquely addressed. 3. The method of testing according to claim 2 wherein said first test includes setting all of the programmable logic inputs to said AND gate matrix logic high and using said additional inputs to individually address said OR gates.