17. A stack according to claim 16, wherein within each linear array of data storage cells the output of each (n)th cell in the array from the top of the stack is connected to the input of the (n+1)th cell by a push gate and is connected to the input of the (n-1)th cell by a pop gate, and the input of each (n)th cell is connected to the output of the (n+1)th cell by a pop gate and is connected to the output of the (n-1)th cell by a push gate; wherein each push gate is connected to the control circuit for shifting data down from the top of the stack in response to a push signal from the control circuit; and wherein each pop gate is connected to the control circuit for shifting data up toward the top of the stack in response to a pop signal from the control circuit.
17. A stack according to claim 16, wherein within each linear array of data storage cells the output of each (n)th cell in the array from the top of the stack is connected to the input of the (n+1)th cell by a push gate and is connected to the input of the (n-1)th cell by a pop gate, and the input of each (n)th cell is connected to the output of the (n+1)th cell by a pop gate and is connected to the output of the (n-1)th cell by a push gate; wherein each push gate is connected to the control circuit for shifting data down from the top of the stack in response to a push signal from the control circuit; and wherein each pop gate is connected to the control circuit for shifting data up toward the top of the stack in response to a pop signal from the control circuit. 18. A stack according to claim 17, wherein the control cells are interconnected for communicating the storage state of the corresponding word levels to and from the adjacent control cells; and wherein each (n)th control cell in the array from the top of the stack includes a cell-state flip-flop for providing indication signals indicating the storage state of the (n)th word level; a first control gate connected to the push gate between the (n)th data storage cell and the (n+1)th data storage cell in each linear array of data storage cells for providing a push signal to said push gates in response to indication signals from the cell-state flip-flop of the (n)th control cell indicating that the (n)th word level is full, from the cell-state flip-flop of the (n+1)th control cell indicating that the (n+1)th word level is empty, and from the cell-state flip-flop of the (n-1)th control cell indicating that the (n-1)th word level is full; and a second control gate connected to the pop gate between the (n)th data storage cell and the (n+1)th data storage cell in each linear array of data storage cells for providing a pop signal to said pop gates in response to indication signals from the cell-state flip-flop of the (n)th control cell indicating that the (n)th word level is empty, from the cell-state flip-flop of the (n+1)th control cell indicating that the (n+1)th word level is full, and from the cell-state flip-flop of the (n-1)th control cell indicating that the (n-1)th word level is empty.