6. The computer-implemented method of claim 5 , wherein: the first module comprises a processor that is switchable between a low-power state and a high-power state; and the processor only performs the operation when it is in the high-power state.
6. The computer-implemented method of claim 5 , wherein: the first module comprises a processor that is switchable between a low-power state and a high-power state; and the processor only performs the operation when it is in the high-power state. 8. The computer-implemented method of claim 6 further comprising deactivating the first module, wherein deactivating the first module comprises switching the processor from the high-power state to the low-power state.