5. Serial binary number word to binary coded decimal (BCD) number word conversion apparatus comprising, in combination: generator means for supplying a series of constants, one each word time for a frame of N word times wherein N is equal to the number of bits in the BCD word, the value of the constants being equal to the corresponding bit position of a BCD word; input means for supplying an input serial binary number word to be converted; comparison means, connected to said generator means for receiving words therefrom and including a further input and first and second output means, said comparison means providing as an output signal at said first output means any serial binary words supplied to said further input when the serial binary word is of a lesser absolute value than the constant received at the word time of comparison and simultaneously supplying a given binary logic value signal at said second output means, said comparison means providing as an output signal at said first output means, when the serial binary word supplied to said further input is of a greater absolute value than the constant received at the word time of the comparison, the difference in absolute magnitudes and simultaneously supplying at said second output means a binary logic signal of a logic value opposite said given logic value; said comparison means comprising, in combination; summing means connected to receive said series of constants at a first input and having a second input connected to said further input of said comparison means, said summing means including an output means, J-k flip-flop means connected to receive signals from said output means of said summing means during the most significant bit time of each word time and having an output thereof connected to said second output means of said comparison means, gating means including first, second, and third input means wherein said first input means thereof is connected to said second output means of said comparison means and said output means of said gating means is connected to said first output means of said comparison means, first shift register means connected between said output means of said summing means and said second input means of said gating means, second shift register means connected between said first input means of said comparison means and said third input means of said gating means; and switch means connected to said input means, said first output means and said further input for supplying said serial binary word to be converted to said further input of said comparison means during the first word time of a frame time and returning output words from said first output means of said comparison means during the remaining word times of the frame time.
5. Serial binary number word to binary coded decimal (BCD) number word conversion apparatus comprising, in combination: generator means for supplying a series of constants, one each word time for a frame of N word times wherein N is equal to the number of bits in the BCD word, the value of the constants being equal to the corresponding bit position of a BCD word; input means for supplying an input serial binary number word to be converted; comparison means, connected to said generator means for receiving words therefrom and including a further input and first and second output means, said comparison means providing as an output signal at said first output means any serial binary words supplied to said further input when the serial binary word is of a lesser absolute value than the constant received at the word time of comparison and simultaneously supplying a given binary logic value signal at said second output means, said comparison means providing as an output signal at said first output means, when the serial binary word supplied to said further input is of a greater absolute value than the constant received at the word time of the comparison, the difference in absolute magnitudes and simultaneously supplying at said second output means a binary logic signal of a logic value opposite said given logic value; said comparison means comprising, in combination; summing means connected to receive said series of constants at a first input and having a second input connected to said further input of said comparison means, said summing means including an output means, J-k flip-flop means connected to receive signals from said output means of said summing means during the most significant bit time of each word time and having an output thereof connected to said second output means of said comparison means, gating means including first, second, and third input means wherein said first input means thereof is connected to said second output means of said comparison means and said output means of said gating means is connected to said first output means of said comparison means, first shift register means connected between said output means of said summing means and said second input means of said gating means, second shift register means connected between said first input means of said comparison means and said third input means of said gating means; and switch means connected to said input means, said first output means and said further input for supplying said serial binary word to be converted to said further input of said comparison means during the first word time of a frame time and returning output words from said first output means of said comparison means during the remaining word times of the frame time. 6. Apparatus as claimed in claim 5 comprising in addition: assembly means for assembling logic bits representative of given logic value input signals during each word time of a frame time and outputting the assembled word during the frame time following assembly; and means connected between said second output means of said comparison means and said assembly means for providing said binary logic value signals thereto.