9. The method of claim 8 , wherein the circuit design is to be implemented on a partially-reconfigurable FPGA.
9. The method of claim 8 , wherein the circuit design is to be implemented on a partially-reconfigurable FPGA. 10. The method of claim 9 , wherein: the configuration settings for the secret portion are provided in the form of a bitstream of programming bits to the user; and the programming bits for the secret portion are configured for programming into the partially-reconfigurable FPGA device during operation of the FPGA device.