11. A Satisfiability Modulo Theories (SMT) solver, comprising: one or more processors communicatively coupled to memory for executing components including: a Davis Putnam Longman Loveland (DPLL)-based Boolean satisfiability (SAT) solver for determining satisfiability of a received formula; a theories solver; and a relevancy propagation engine associated with the SAT solver that: creates a representation of the received formula by eliminating conjunctions associated with the received formula; determines which atomic constraints of the received formula are relevant for determining the satisfiability of the formula based in part on using a Tableau solving technique on the representation of the received formula as part of the DPLL-based Boolean SAT solver; propagates truth assignments of the relevant atomic constraints to the theories solver; and halts propagation of the truth assignments of irrelevant atomic constraints.
11. A Satisfiability Modulo Theories (SMT) solver, comprising: one or more processors communicatively coupled to memory for executing components including: a Davis Putnam Longman Loveland (DPLL)-based Boolean satisfiability (SAT) solver for determining satisfiability of a received formula; a theories solver; and a relevancy propagation engine associated with the SAT solver that: creates a representation of the received formula by eliminating conjunctions associated with the received formula; determines which atomic constraints of the received formula are relevant for determining the satisfiability of the formula based in part on using a Tableau solving technique on the representation of the received formula as part of the DPLL-based Boolean SAT solver; propagates truth assignments of the relevant atomic constraints to the theories solver; and halts propagation of the truth assignments of irrelevant atomic constraints. 17. The SMT solver as recited in claim 11 , wherein the relevancy propagation rules are applied to provide a reduction in search space covered during quantifier instantiation or to provide acceleration during reasoning about bit-vectors.