1. A processing chip comprising: a first hardware element that is configured to: receive a query that includes a database operation; generate, in response to receiving the query, a scan operation command that includes, as parameters of the scan operation command, address data that is used to identify input data and one or more values that are used to compare against the input data; a second hardware element that is configured to: read the scan operation command; cause the input data to be read from a location that is indicated by the address data; perform a comparison between the input data and the one or more values; generate a result data based on the comparison; cause the first hardware element to be notified of the result data.
1. A processing chip comprising: a first hardware element that is configured to: receive a query that includes a database operation; generate, in response to receiving the query, a scan operation command that includes, as parameters of the scan operation command, address data that is used to identify input data and one or more values that are used to compare against the input data; a second hardware element that is configured to: read the scan operation command; cause the input data to be read from a location that is indicated by the address data; perform a comparison between the input data and the one or more values; generate a result data based on the comparison; cause the first hardware element to be notified of the result data. 3. The processing chip of claim 1 , wherein the second hardware element is a coprocessor.