52. A data processing system according to claim 51 wherein said memory processor is further programmable such that the processor may receive a block of data from the memory, said memory processor formatting the block of data as the block of data is sequentially transferred.
52. A data processing system according to claim 51 wherein said memory processor is further programmable such that the processor may receive a block of data from the memory, said memory processor formatting the block of data as the block of data is sequentially transferred. 53. A data processing system according to claim 52 wherein said memory processor is further programmable such that the memory may send a block of data from the memory to said memory processor, said memory processor formatting the block of data and sending the block of data back to the memory.