1. A memory management unit for communicating with a CPU and a memory of a computer system to control said CPU's right to access said memory in order to initiate performance of an operation, wherein the memory comprises a single address space, said memory management unit comprising; a plurality of domains, each individual domain corresponding to an address-oriented service and a set of addresses in the single address space of the memory, wherein each address in the single address space is only associated with one of the plurality of domains; a plurality of environments, wherein an environment controls access by an associated task to the plurality of domains; a translator coupled to receive a virtual address signal and an access type signal issued by said CPU during execution of a task, wherein said translator translates said virtual address signal into a physical address signal and issues said physical address signal to said memory in order to initiate performance of said operation, and wherein said translator issues a domain number signal that indicates one of said plurality of domains in which said virtual address resides based on said virtual address, and further wherein said translator determines if faults occur during translation of said virtual address and issues a first fault indication if one or more faults occur during translation of said virtual address; and an environment controller coupled to receive said domain number signal, wherein said environment controller permits access by said task to said one of said plurality of domains if said one of said plurality of domains is within a set of allowed domains, said environment controller issuing a second fault indication if said domain number signal does not correspond to an allowed domain number, such that said CPU's right to access said memory is denied if said first fault indication, said second fault indication, or both said first fault indication and said second fault indication are generated.
1. A memory management unit for communicating with a CPU and a memory of a computer system to control said CPU's right to access said memory in order to initiate performance of an operation, wherein the memory comprises a single address space, said memory management unit comprising; a plurality of domains, each individual domain corresponding to an address-oriented service and a set of addresses in the single address space of the memory, wherein each address in the single address space is only associated with one of the plurality of domains; a plurality of environments, wherein an environment controls access by an associated task to the plurality of domains; a translator coupled to receive a virtual address signal and an access type signal issued by said CPU during execution of a task, wherein said translator translates said virtual address signal into a physical address signal and issues said physical address signal to said memory in order to initiate performance of said operation, and wherein said translator issues a domain number signal that indicates one of said plurality of domains in which said virtual address resides based on said virtual address, and further wherein said translator determines if faults occur during translation of said virtual address and issues a first fault indication if one or more faults occur during translation of said virtual address; and an environment controller coupled to receive said domain number signal, wherein said environment controller permits access by said task to said one of said plurality of domains if said one of said plurality of domains is within a set of allowed domains, said environment controller issuing a second fault indication if said domain number signal does not correspond to an allowed domain number, such that said CPU's right to access said memory is denied if said first fault indication, said second fault indication, or both said first fault indication and said second fault indication are generated. 10. A memory management unit as recited in claim 1, wherein said environment controller includes: a control register coupled to receive a data signal issued by said CPU and issuing a plurality of bits derived from said data signal; and a selector coupled to the control register and coupled to receive said domain number signal from said translator, wherein the selector selects a bit issued by said control register which corresponds to said domain number and issues said second fault indication so as to prevent initiation of performance of said operation if said bit selected by said selector indicates that said CPU is not allowed access to a domain corresponding to said domain number.