1. A processor comprising: an interface to perform a transaction to fetch information from a memory; and memory management logic to translate an untranslated address to a memory address, including: a storage location to store a first address of an initial data structure for a first walk through a first set of translation stages; a plurality of translation stages comprising the first set of translation stages and a second set of translation stages, the first set of translation stages reserved for a first context, the second set of translation stages reserved for a second context, each translation stage of the plurality of translation stages including translation logic and a data structure, the translation logic to find a particular entry of a plurality of entries in the data structure based on a corresponding portion of the untranslated address, each entry of the plurality of entries in the data structure to store a transition indicator to indicate a context switch from the first context to the second context; determination logic to: determine, during the first walk through the first set of translation stages, whether the particular entry of the plurality of entries in the data structure is a transition entry for the context switch from the first context to the second context based at least in part on the transition indicator of the particular entry; in response to a determination that the particular entry is a transition entry, initiate a second walk through the second set of translation stages to cause the context switch from the first context to the second context; and a translation lookaside buffer to store translations.
1. A processor comprising: an interface to perform a transaction to fetch information from a memory; and memory management logic to translate an untranslated address to a memory address, including: a storage location to store a first address of an initial data structure for a first walk through a first set of translation stages; a plurality of translation stages comprising the first set of translation stages and a second set of translation stages, the first set of translation stages reserved for a first context, the second set of translation stages reserved for a second context, each translation stage of the plurality of translation stages including translation logic and a data structure, the translation logic to find a particular entry of a plurality of entries in the data structure based on a corresponding portion of the untranslated address, each entry of the plurality of entries in the data structure to store a transition indicator to indicate a context switch from the first context to the second context; determination logic to: determine, during the first walk through the first set of translation stages, whether the particular entry of the plurality of entries in the data structure is a transition entry for the context switch from the first context to the second context based at least in part on the transition indicator of the particular entry; in response to a determination that the particular entry is a transition entry, initiate a second walk through the second set of translation stages to cause the context switch from the first context to the second context; and a translation lookaside buffer to store translations. 3. The processor of claim 1 , wherein the determination logic is also to, if the particular entry is a transition entry and the transaction is an instruction fetch, replace the first address of the initial data structure for the first set of translation stages stored in the storage location with a second address of an initial data structure for a second set of translation stages.