20. The system of claim 1 , wherein at least some of the one or more native instructions comprise a plurality of control signals, and wherein at least one processor of the plurality of processors further is to decode each operational code of the plurality of operational codes to generate a corresponding plurality of control signals to control a selected operation, of a plurality of operations, corresponding to a selected operational code of the plurality of operational codes.
20. The system of claim 1 , wherein at least some of the one or more native instructions comprise a plurality of control signals, and wherein at least one processor of the plurality of processors further is to decode each operational code of the plurality of operational codes to generate a corresponding plurality of control signals to control a selected operation, of a plurality of operations, corresponding to a selected operational code of the plurality of operational codes. 21. The system of claim 20 , wherein at least one processor of the plurality of processors further comprises a floating point circuit, and wherein at least one processor of the plurality of processors further is to generate a first corresponding control signal to enable the floating point circuit to perform the selected operation.