2. A stack according to claim 1, wherein within the linear array of data storage cells the output of each (n)th cell is connected to the input of the (n+1)th cell by a push gate and is connected to the input of the (n-1)th cell by a pop gate, and the input of each (n)th cell is connected to the output of (n+1)th cell by a pop gate and is connected to the output of the (n-1)th cell by a push gate; wherein each push gate is connected to the control circuit for shifting data down from the top of the stack in response to a push signal from the control circuit; and wherein each pop gate is connected to the control circuit for shifting data up toward the top of the stack in response to a pop signal from the control circuit.
2. A stack according to claim 1, wherein within the linear array of data storage cells the output of each (n)th cell is connected to the input of the (n+1)th cell by a push gate and is connected to the input of the (n-1)th cell by a pop gate, and the input of each (n)th cell is connected to the output of (n+1)th cell by a pop gate and is connected to the output of the (n-1)th cell by a push gate; wherein each push gate is connected to the control circuit for shifting data down from the top of the stack in response to a push signal from the control circuit; and wherein each pop gate is connected to the control circuit for shifting data up toward the top of the stack in response to a pop signal from the control circuit. 3. A stack according to claim 2, wherein the control cells are interconnected for communicating the storage state of the corresponding data storage cells to and from the adjacent control cells; and wherein each (n)th control cell in the array from the top of the stack includes a cell-state flip-flop for providing indication signals indicating the storage state of the (n)th data storage cell; a first control gate connected to the push gate between the (n)th data storage cell and the (n+1)th data storage cell for providing a push signal to said push gate in response to indication signals from the cell-state flip-flop of the (n)th control cell indicating that the (n)th data storage cell is full, from the cell-state flip-flop of the (n+1) the control cell indicating that the (n+1)th data storage cell is empty, and from the cell-state flip-flop of the (n-1)th control cell indicating that the (n-1)th data storage cell is full; and a second control gate connected to the pop gate between the (n)th data storage cell and the (n+1)th data storage cell for providing a pop signal to said pop gate in response to indication signals from the cell-state flip-flop of the (n)th control cell indicating that the (n)th data storage cell is empty, from the cell-state flip-flop of the (n+1)th control cell indicating that the (n+1)th data storage cell is full, and from the cell-state flip-flop of the (n-1)th control cell indicating that the (n-1)th data storage cell is empty.