7. A data processing system capable of use with one or more external devices, said system comprising memory means including a first storage region containing a plurality of instruction routines, each routine for performing one of a plurality of selectable interrupt operations; a second storage region containing a plurality of device control tables, each said table being associated with one of said external devices and including an interrupt routine address pointing to a selected one of said interrupt routines in said first storage region; a third storage region containing a plurality of device control table addresses each of said addresses being associated with one of said external devices and pointing to a selected one of said device control tables in said second storage region; a fourth storage region having a first selected location capable of storing information defining an instruction for transferring control of said system to a desired one of said plurality of interrupt routines associated with an external device and a second selected location containing an address pointing to a selected location in said third storage region; means connected to said external device and to said memory means and responsive to an interrupt request from an external device for examining the first selected location of said fourth storage region to determine whether or not the information defining said transfer instruction is present therein and for supplying the address in said second selected location where said information is present and means connected to said external device and to said memory means and responsive to coded information from said external device requesting said interrupt for providing to said third storage region an address offset from said selected location in said third storage region, the address at said offset location being the address pointing to said selected one of said device control tables in said second storage region.
7. A data processing system capable of use with one or more external devices, said system comprising memory means including a first storage region containing a plurality of instruction routines, each routine for performing one of a plurality of selectable interrupt operations; a second storage region containing a plurality of device control tables, each said table being associated with one of said external devices and including an interrupt routine address pointing to a selected one of said interrupt routines in said first storage region; a third storage region containing a plurality of device control table addresses each of said addresses being associated with one of said external devices and pointing to a selected one of said device control tables in said second storage region; a fourth storage region having a first selected location capable of storing information defining an instruction for transferring control of said system to a desired one of said plurality of interrupt routines associated with an external device and a second selected location containing an address pointing to a selected location in said third storage region; means connected to said external device and to said memory means and responsive to an interrupt request from an external device for examining the first selected location of said fourth storage region to determine whether or not the information defining said transfer instruction is present therein and for supplying the address in said second selected location where said information is present and means connected to said external device and to said memory means and responsive to coded information from said external device requesting said interrupt for providing to said third storage region an address offset from said selected location in said third storage region, the address at said offset location being the address pointing to said selected one of said device control tables in said second storage region. 8. A data processing system in accordance with claim 7 wherein the device control table in said second storage region includes coded masking information for preventing other external devices from requesting interrupts when an interrupt has already been requested by said external device and processor status information as to whether or not a fixed point overflow condition is to be enabled.