1. A trellis coded modulator (TCM) for generating an encoded word from an input word, the TCM comprising: a single encoder, wherein the single encoder comprises: a first logic branch configured to generate a data portion of the encoded word; and a second logic branch, coupled in parallel with the first logic branch, and configured to generate a corresponding parity portion of the encoded word sequentially after the generation of the data portion of the encoded word, wherein the second logic branch comprises a first register configured to hold a final bit of the input word until after the generation of the parity portion of the encoded word.
1. A trellis coded modulator (TCM) for generating an encoded word from an input word, the TCM comprising: a single encoder, wherein the single encoder comprises: a first logic branch configured to generate a data portion of the encoded word; and a second logic branch, coupled in parallel with the first logic branch, and configured to generate a corresponding parity portion of the encoded word sequentially after the generation of the data portion of the encoded word, wherein the second logic branch comprises a first register configured to hold a final bit of the input word until after the generation of the parity portion of the encoded word. 7. The TCM of claim 1 , wherein the second logic branch comprises: the first register having an input configured to receive the input word and an output; a first modulo 2 adder having a first input coupled to the output of the first register, a second input, a third input, and an output; a second register having an input coupled to the output of the first modulo 2 adder and an output coupled to the third input of the first modulo 2 adder; a second modulo 2 adder having a first input coupled to the output of the second register, a second input, and an output configured to output the parity portion of the encoded word; and a third register having an input coupled to the output of the second register, and an output coupled to the second input of the first modulo 2 adder and to the second input of the second modulo 2 adder.