16. A processor-implemented method for synthesizing a behavioral description of a circuit into a structural description of the circuit, the method comprising: receiving the behavioral description of the circuit, the behavioral description including a first statement synthesizable into sequential logic that is to be conditionally clocked based on an evaluation of a condition associated with the first statement; identifying the condition associated with the first statement; identifying one or more other statements associated with the condition, including: identifying a downstream statement synthesizable into downstream logic that is dependent on the sequential logic; and/or identifying an upstream statement synthesizable into upstream logic upon which the sequential logic depends; inferring one or more clock domains for the sequential logic, and for the downstream logic and/or the upstream logic, the one or more inferred clock domains being clock gated based on the identified condition; using a processor, scheduling the sequential logic, and the downstream logic and/or the upstream logic, according to the one or more inferred clock domains; and using a processor, generating the structural description of the circuit, the structural description of the circuit including a structural description of the scheduled sequential logic.
16. A processor-implemented method for synthesizing a behavioral description of a circuit into a structural description of the circuit, the method comprising: receiving the behavioral description of the circuit, the behavioral description including a first statement synthesizable into sequential logic that is to be conditionally clocked based on an evaluation of a condition associated with the first statement; identifying the condition associated with the first statement; identifying one or more other statements associated with the condition, including: identifying a downstream statement synthesizable into downstream logic that is dependent on the sequential logic; and/or identifying an upstream statement synthesizable into upstream logic upon which the sequential logic depends; inferring one or more clock domains for the sequential logic, and for the downstream logic and/or the upstream logic, the one or more inferred clock domains being clock gated based on the identified condition; using a processor, scheduling the sequential logic, and the downstream logic and/or the upstream logic, according to the one or more inferred clock domains; and using a processor, generating the structural description of the circuit, the structural description of the circuit including a structural description of the scheduled sequential logic. 20. The method of claim 16 , wherein the scheduling comprises: associating circuitry for potentially implementing the sequential logic to a plurality of pipelined stages associated with a first gated clock domain, the first gated clock domain being gated by the condition or a derivative thereof; and associating circuitry for potentially implementing the downstream logic and/or the upstream logic to a plurality of pipelined stages associated with a second gated clock domain, the second gated clock domain being gated by the condition or another derivative thereof.