10. A host computing device comprising: one or more microcontrollers; an accessory port connectable to a connector for an accessory device; one or more computer-readable storage media storing instructions that when executed via the one or more microcontrollers cause the host computing device to perform operations including: detecting insertion of the connector into the accessory port via a pair of detection pins integrated with the connector; obtaining a logic state combination of high and low logic states conveyed via the pair of detection pins; determining a device type for the accessory device as a one wire device or a two wire device based upon the logic state combination; ascertaining an orientation of the connector inserted in the accessory port including: when the device type is a one wire device, determining the orientation of the connection directly from the logic state combination; or when the device type is a two wire device, sampling resistor values for one or more identity resistors of the accessory device via the pair of detection pins to establish validity states indicative of the orientation; and setting-up signal routing according to the type of device and ascertained orientation.
10. A host computing device comprising: one or more microcontrollers; an accessory port connectable to a connector for an accessory device; one or more computer-readable storage media storing instructions that when executed via the one or more microcontrollers cause the host computing device to perform operations including: detecting insertion of the connector into the accessory port via a pair of detection pins integrated with the connector; obtaining a logic state combination of high and low logic states conveyed via the pair of detection pins; determining a device type for the accessory device as a one wire device or a two wire device based upon the logic state combination; ascertaining an orientation of the connector inserted in the accessory port including: when the device type is a one wire device, determining the orientation of the connection directly from the logic state combination; or when the device type is a two wire device, sampling resistor values for one or more identity resistors of the accessory device via the pair of detection pins to establish validity states indicative of the orientation; and setting-up signal routing according to the type of device and ascertained orientation. 15. A host computing device as described in claim 10 , wherein the instructions are implemented via firmware corresponding to the one or more microcontrollers of the host computing device and the one or more microcontrollers are configured to operate independently of a primary processing system of the host computing device.