19. An apparatus comprising: one or more computer processors implementing: a compiler adapted to: parse statements of input program code to generate custom instructions for an instruction set loadable upon a reconfigurable processor, wherein a single custom instruction of the instruction set is generated by aggregating the statements of input program code according to one or more constraints that, based upon physical limitations imposed by a framework generator, prevent a terminal conflict resulting from an assumption that, independently of hardware latency requirements of the reconfigurable processor, the single custom instruction may be accomplished in a single clock cycle of the reconfigurable processor; generate a custom instruction description file including the custom instructions; analyze the statements of the input program code to determine capabilities of the reconfigurable processor that are being utilized by the custom instructions, wherein the capabilities of the reconfigurable processor comprise information regarding: access capabilities of the custom instructions; calling capabilities of the custom instructions; and support capabilities of the custom instructions; generate a framework capabilities description file including information regarding capabilities of the reconfigurable processor that are being utilized by the custom instructions; a timing manager configured to: adapt the custom instruction description file for hardware timing of the reconfigurable processor, thereby generating a timing adapted custom instruction description file; and adapt the framework capabilities description file to include information regarding the adapting of the custom instruction description file, thereby generating a timing adapted framework capabilities description file; and at least one memory coupled to the one or more computer processors.
19. An apparatus comprising: one or more computer processors implementing: a compiler adapted to: parse statements of input program code to generate custom instructions for an instruction set loadable upon a reconfigurable processor, wherein a single custom instruction of the instruction set is generated by aggregating the statements of input program code according to one or more constraints that, based upon physical limitations imposed by a framework generator, prevent a terminal conflict resulting from an assumption that, independently of hardware latency requirements of the reconfigurable processor, the single custom instruction may be accomplished in a single clock cycle of the reconfigurable processor; generate a custom instruction description file including the custom instructions; analyze the statements of the input program code to determine capabilities of the reconfigurable processor that are being utilized by the custom instructions, wherein the capabilities of the reconfigurable processor comprise information regarding: access capabilities of the custom instructions; calling capabilities of the custom instructions; and support capabilities of the custom instructions; generate a framework capabilities description file including information regarding capabilities of the reconfigurable processor that are being utilized by the custom instructions; a timing manager configured to: adapt the custom instruction description file for hardware timing of the reconfigurable processor, thereby generating a timing adapted custom instruction description file; and adapt the framework capabilities description file to include information regarding the adapting of the custom instruction description file, thereby generating a timing adapted framework capabilities description file; and at least one memory coupled to the one or more computer processors. 26. The apparatus of claim 19 , wherein the one or more computer processors further implement: the framework generator, wherein the framework generator is adapted to generate a framework file comprising an executable description of the instruction set using the custom instructions of the timing adapted custom instruction description file and the information regarding capabilities of the reconfigurable processor of the timing adapted framework capabilities description file.