7. A content addressable memory cell apparatus, comprising: a plurality of magnetic tunnel junctions (MTJs), wherein a write polarity on each of the MTJs is controlled by modulating a direction of current; a plurality of transistors; a plurality of searchlines; a wordline; a bitline (BL); a sourceline (SrL); and a plurality of matchlines.
7. A content addressable memory cell apparatus, comprising: a plurality of magnetic tunnel junctions (MTJs), wherein a write polarity on each of the MTJs is controlled by modulating a direction of current; a plurality of transistors; a plurality of searchlines; a wordline; a bitline (BL); a sourceline (SrL); and a plurality of matchlines. 8. The content addressable memory cell apparatus of claim 7 , wherein a write operation is performed by turning on a first and a second transistors of the plurality of transistors, writing a ‘0’ bit-state by making (SrL, BL)=(1,0) and an ‘1’ bit-state by making (SrL, BL)=(0,1) via a complementary write; writing an ‘X’ bit-state by writing ‘1’ to the plurality of MTJs via a parallel write.