24. A computer implemented method comprising: receiving an executable, graphical model having a plurality of blocks including a block that process frame-based input data, the frame-based block implementable in hardware in a plurality of ways, the plurality of ways in which the frame-enabled block is implementable in hardware include: a fully parallelized way that uses a plurality of first parallel hardware components, a fully serialized way that uses a first serial hardware component, and a combination serialized and parallelized way that uses a plurality of second parallel hardware components and a second serial hardware component; determining a best option for describing frame-like behavior in hardware description language (HDL) code for the frame-based block through a block-by-block analysis of the model, wherein the best option causes the frame-based block to be implemented in hardware in a particular way of the plurality of ways; generating, using a processor of a computer, the HDL code for the model, wherein the generated HDL code implements the frame-based block in hardware in the particular way that utilizes the best option determined for the frame-based block, the particular way selected from the group consisting of: the fully parallelized way, in which the plurality of first parallel hardware components are included in the hardware implementation of the frame-enabled block, the fully serialized way, in which the first serial hardware component is included in the hardware implementation of the frame-enabled block, and the combination serialized and parallelized way, in which the second serial hardware component and the plurality of second parallel hardware components are included in the hardware implementation of the frame-enabled block.
24. A computer implemented method comprising: receiving an executable, graphical model having a plurality of blocks including a block that process frame-based input data, the frame-based block implementable in hardware in a plurality of ways, the plurality of ways in which the frame-enabled block is implementable in hardware include: a fully parallelized way that uses a plurality of first parallel hardware components, a fully serialized way that uses a first serial hardware component, and a combination serialized and parallelized way that uses a plurality of second parallel hardware components and a second serial hardware component; determining a best option for describing frame-like behavior in hardware description language (HDL) code for the frame-based block through a block-by-block analysis of the model, wherein the best option causes the frame-based block to be implemented in hardware in a particular way of the plurality of ways; generating, using a processor of a computer, the HDL code for the model, wherein the generated HDL code implements the frame-based block in hardware in the particular way that utilizes the best option determined for the frame-based block, the particular way selected from the group consisting of: the fully parallelized way, in which the plurality of first parallel hardware components are included in the hardware implementation of the frame-enabled block, the fully serialized way, in which the first serial hardware component is included in the hardware implementation of the frame-enabled block, and the combination serialized and parallelized way, in which the second serial hardware component and the plurality of second parallel hardware components are included in the hardware implementation of the frame-enabled block. 26. The method of claim 24 wherein the determining comprises: computing a cost function based on the best option; and converging on the best option when the computed cost function is minimized.