30. In a logic array having an input and an output, an AND gate matrix with a read-only-memory addressing mode and a programmable-logic-array addressing mode, an OR gate matrix connected to said AND gate matrix, and control means for determining the addressing mode of said array, the improvement comprising: a bypass means connecting said input of said logic array to said output of said OR gate matrix for providing an output of said logic array which is a combination of the input of said logic array and the output of said OR gate matrix.
30. In a logic array having an input and an output, an AND gate matrix with a read-only-memory addressing mode and a programmable-logic-array addressing mode, an OR gate matrix connected to said AND gate matrix, and control means for determining the addressing mode of said array, the improvement comprising: a bypass means connecting said input of said logic array to said output of said OR gate matrix for providing an output of said logic array which is a combination of the input of said logic array and the output of said OR gate matrix. 32. The logic array according to claim 30 including next address means connected to the output of said OR gate matrix and to the input of said AND gate matrix for providing a next address to said AND gate matrix as a function of the input words, the output of said OR gate matrix, computer status and test words.