5. An integrated circuit, comprising: a client circuit configured to: determine a plurality of virtual addresses to be specified in a prefetch request of the client circuit; send the prefetch requests to a prefetch processing unit in a memory management unit to cause table walk circuitry in the memory management unit to load translations for the plurality of virtual addresses into a translation table distinct from a translation lookaside buffer (TLB) of the memory management unit, wherein the table walk circuitry is configured to load the translations into the translation table without loading the translations into the TLB; and send, to the memory management unit, one or more memory requests specifying one or more of the plurality of virtual addresses.
5. An integrated circuit, comprising: a client circuit configured to: determine a plurality of virtual addresses to be specified in a prefetch request of the client circuit; send the prefetch requests to a prefetch processing unit in a memory management unit to cause table walk circuitry in the memory management unit to load translations for the plurality of virtual addresses into a translation table distinct from a translation lookaside buffer (TLB) of the memory management unit, wherein the table walk circuitry is configured to load the translations into the translation table without loading the translations into the TLB; and send, to the memory management unit, one or more memory requests specifying one or more of the plurality of virtual addresses. 8. The integrated circuit of claim 5 , wherein the client circuit includes: a first interface configured to send the one or more memory specifying one or more of the plurality of virtual addresses; and a second interface configured to send the memory request specifying a virtual address that does not have a prefetched translation, wherein the second interface is distinct from the first interface.