15. A computer program product comprising: a computer-usable medium having stored thereon computer-usable program code that profiles a hardware system, said computer program product including: computer-usable program code that compiles a high level language program into an assembly language representation of a hardware system, wherein the high level language program is specified using a language other than a hardware description language; computer-usable program code that translates instructions of an assembly language representation of the hardware system into a plurality of executable, software models; wherein each software model corresponds to a respective one of the assembly language instructions, and the models are communicatively linked by FIFOs to form a pipelined architecture; computer-usable program code that instruments at least one of the plurality of models with code that causes operational information relating to the model to be provided as output; wherein the operating state information includes read state data, the at least one model is in a read state while the at least one model is waiting for data from another model to appear on an input FIFO to the at least one model, and the read state data indicates a number of consecutive cycles the at least one model is in the read state; and computer-usable program code that indicates expected behavior of the circuit by executing the models.
15. A computer program product comprising: a computer-usable medium having stored thereon computer-usable program code that profiles a hardware system, said computer program product including: computer-usable program code that compiles a high level language program into an assembly language representation of a hardware system, wherein the high level language program is specified using a language other than a hardware description language; computer-usable program code that translates instructions of an assembly language representation of the hardware system into a plurality of executable, software models; wherein each software model corresponds to a respective one of the assembly language instructions, and the models are communicatively linked by FIFOs to form a pipelined architecture; computer-usable program code that instruments at least one of the plurality of models with code that causes operational information relating to the model to be provided as output; wherein the operating state information includes read state data, the at least one model is in a read state while the at least one model is waiting for data from another model to appear on an input FIFO to the at least one model, and the read state data indicates a number of consecutive cycles the at least one model is in the read state; and computer-usable program code that indicates expected behavior of the circuit by executing the models. 16. The computer program product of claim 15 , wherein the models are implemented using a high level modeling language for use with cycle accurate emulation, wherein the computer-usable program code that that translates instructions of the assembly language representation further comprises: computer-usable program code that creates models of hardware components for the circuit design according to instructions of the assembly language; and computer-usable program code that creates models of first-in-first-outs that couple the models of hardware components for the hardware system according to operands of the instructions of the assembly language representation.