7. The memory device of claim 6 , further storing instructions that, when executed by one or more processors, cause the one or more processors to: display the block diagram model.
7. The memory device of claim 6 , further storing instructions that, when executed by one or more processors, cause the one or more processors to: display the block diagram model. 8. The memory device of claim 7 , further storing instructions that, when executed by the one or more processors, cause the one or more processors to: highlight at least one of the instructions in the source design; and highlight an element in the block diagram model that corresponds to the at least one of the instructions in the source design.