15. A system comprising: a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to: detect a presence of a combinational loop in a word-level netlist representation of a circuit design by identifying a portion of the word-level netlist having at least one characteristic associated with the combinational loop, translating the identified portion of the word-level netlist into a bit-level circuit representation, and utilizing the bit-level circuit representation to determine the identified portion of the word-level netlist includes the combinational loop; and modify the word-level netlist corresponding to the detected presence of the combinational loop.
15. A system comprising: a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to: detect a presence of a combinational loop in a word-level netlist representation of a circuit design by identifying a portion of the word-level netlist having at least one characteristic associated with the combinational loop, translating the identified portion of the word-level netlist into a bit-level circuit representation, and utilizing the bit-level circuit representation to determine the identified portion of the word-level netlist includes the combinational loop; and modify the word-level netlist corresponding to the detected presence of the combinational loop. 16. The system of claim 15 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to modify the word-level netlist by replacing the identified portion of the word-level netlist that includes the combinational loop with a loop buffer element.