97. For use with a memory element containing compressed information time domain signals produced by predetermined signal compression techniques and instruction signals specifying the particular compression techniques applied to original information bearing time domain signals to produce corresponding portions of said compressed information time domain signals, said predetermined signal compression techniques including Mozer phase adjusting of said original information bearing time domain signals, a controller device for synthesizing said original information bearing time domain signals, said controller device comprising: controller storage means having an input adapted to be coupled to said memory element for sequentially receiving ordered ones of said compressed information time domain signals; means adapted to be coupled to said controller storage means for generating control signals enabling said ordered ones of said compressed information time domain signals to be coupled to said controller storage means, said control signal generator means including means for receiving corresponding ones of said instruction signals identifying the type of compression technique applied to said ordered ones of said compressed information time domain signals associated with said control signals; converter means coupled to said controller storage means for converting said ordered ones of said compressed information time domain signals to synthetic analog signals corresponding to said original information bearing time domain signals; and means responsive to receipt of a Mozer phase adjust instruction signal from said memory element for causing compressed information time domain signals stored in said controller storage means to be sequentially coupled to said converter means in a first ordered manner and subsequently causing the same signals stored in said controller storage means to be sequentially coupled to said converter means in a reverse manner from said first ordered manner.
97. For use with a memory element containing compressed information time domain signals produced by predetermined signal compression techniques and instruction signals specifying the particular compression techniques applied to original information bearing time domain signals to produce corresponding portions of said compressed information time domain signals, said predetermined signal compression techniques including Mozer phase adjusting of said original information bearing time domain signals, a controller device for synthesizing said original information bearing time domain signals, said controller device comprising: controller storage means having an input adapted to be coupled to said memory element for sequentially receiving ordered ones of said compressed information time domain signals; means adapted to be coupled to said controller storage means for generating control signals enabling said ordered ones of said compressed information time domain signals to be coupled to said controller storage means, said control signal generator means including means for receiving corresponding ones of said instruction signals identifying the type of compression technique applied to said ordered ones of said compressed information time domain signals associated with said control signals; converter means coupled to said controller storage means for converting said ordered ones of said compressed information time domain signals to synthetic analog signals corresponding to said original information bearing time domain signals; and means responsive to receipt of a Mozer phase adjust instruction signal from said memory element for causing compressed information time domain signals stored in said controller storage means to be sequentially coupled to said converter means in a first ordered manner and subsequently causing the same signals stored in said controller storage means to be sequentially coupled to said converter means in a reverse manner from said first ordered manner. 99. The combination of claim 97 wherein said predetermined signal compression techniques include X period zeroing of said original information bearing time domain signals, and wherein said controller device further includes means responsive to receipt of an X period zero instruction signal from said memory element for causing said converter means to output a signal of substantially constant amplitude as a portion of the synthetic analog signal generated thereby.