31. A data processing system having a first bus wherein the first bus has a first bus width, the first bus for sequentially transmitting a plurality of first data packets wherein the plurality of first data packets have a first data width, the data processing system further having a second bus wherein the second bus has a second width, the second bus for sequentially transmitting a plurality of second data packets wherein the plurality of second data packets have a second data width, the width of the first bus being less than the width of the second bus, comprising: a. a memory processor coupled to the first bus and further coupled to the second bus for programming one of a plurality of formatting functions and formatting the plurality of first data packets into a plurality of groups, said memory processor assembling the plurality of first data packets into the plurality of groups as the plurality of first data packets are sequentially transmitted over the first bus, each of the plurality of groups forming a corresponding one of the plurality of second data packets for sequential transmission over the second bus; the memory processor further controlling which of the plurality of first data packets are assembled into each of the plurality of groups.
31. A data processing system having a first bus wherein the first bus has a first bus width, the first bus for sequentially transmitting a plurality of first data packets wherein the plurality of first data packets have a first data width, the data processing system further having a second bus wherein the second bus has a second width, the second bus for sequentially transmitting a plurality of second data packets wherein the plurality of second data packets have a second data width, the width of the first bus being less than the width of the second bus, comprising: a. a memory processor coupled to the first bus and further coupled to the second bus for programming one of a plurality of formatting functions and formatting the plurality of first data packets into a plurality of groups, said memory processor assembling the plurality of first data packets into the plurality of groups as the plurality of first data packets are sequentially transmitted over the first bus, each of the plurality of groups forming a corresponding one of the plurality of second data packets for sequential transmission over the second bus; the memory processor further controlling which of the plurality of first data packets are assembled into each of the plurality of groups. 56. A data processing system according to claim 31 wherein the memory processor further formats a plurality of second data packets, said memory processor disassembling the plurality of second data packets into a plurality of first data packets as the plurality of second data packets are sequentially transmitted over the second bus, each of the plurality of first data packets being sequential transmitted over the first bus; said memory processor further controlling which of the plurality of second data packets are disassembled into each of the plurality of first data packets.