3. The control system of claim 9 or claim 2 wherein said means for activating a binary bit of a second polarity includes means for calculating a table of address points for said memory buffer based on the relative positioning of said binary signals of second polarity in said memory buffer and means for storing said table of address points.
3. The control system of claim 9 or claim 2 wherein said means for activating a binary bit of a second polarity includes means for calculating a table of address points for said memory buffer based on the relative positioning of said binary signals of second polarity in said memory buffer and means for storing said table of address points. 4. The control system of claim 3 wherein said means for calculating the modulo N value of the magnitude representation of said input character string includes means for accessing said table of address points for the memory buffer address nearest said calculated modulo N value for the input character string.