14. A method for performing a fuzzy inference operation, comprising the steps of: receiving a plurality of input labels, a plurality of grades, and a plurality of valid bits via a bussing means, each of the plurality of input labels corresponding to one of the plurality of grades; sorting a first portion of the plurality of grades in a first order based on magnitude and storing each of the plurality of input labels in a position relative to a corresponding one of the first portion of the plurality of grades, an input label sorter coupled to the bussing means for receiving the first portion of the plurality of grades; successively comparing each of the plurality of input labels with a first one of a plurality of antecedents of a first rule, a rule bits generating circuit coupled to the input label sorter for receiving the plurality of input labels; selectively asserting a first rule signal each time one of the plurality of input labels corresponds to the first one of the plurality of antecedents of the first rule; concurrently successively comparing each of the plurality of input labels with a first one of the plurality of antecedents of a second rule; selectively asserting a second rule signal each time one of the plurality of input labels corresponds to the first one of the plurality of antecedents of the second rule; determining a first minimum value corresponding to the first rule and a second minimum value corresponding to the second rule, a minimum determination circuit coupled to the rule bits generating circuit for indicating the first minimum value when the first rule signal is first asserted and a first corresponding one of the plurality of valid bits is in a first logic state which inhibits determination of the first minimum value, the minimum determination circuit indicating the second minimum value when the second rule signal is first asserted and a second corresponding one of the plurality of valid bits is in a second logic state which inhibits determination of the second minimum value; asserting an enable signal when one of the first minimum value and the second minimum value is asserted; and selectively storing a one of the plurality of grades in a latch circuit when the enable signal is asserted, wherein a last one of the plurality of grades latched by the latch circuit is a first maximum output value, the latch circuit being coupled to the minimum determination circuit for receiving the one of the plurality of grades.
14. A method for performing a fuzzy inference operation, comprising the steps of: receiving a plurality of input labels, a plurality of grades, and a plurality of valid bits via a bussing means, each of the plurality of input labels corresponding to one of the plurality of grades; sorting a first portion of the plurality of grades in a first order based on magnitude and storing each of the plurality of input labels in a position relative to a corresponding one of the first portion of the plurality of grades, an input label sorter coupled to the bussing means for receiving the first portion of the plurality of grades; successively comparing each of the plurality of input labels with a first one of a plurality of antecedents of a first rule, a rule bits generating circuit coupled to the input label sorter for receiving the plurality of input labels; selectively asserting a first rule signal each time one of the plurality of input labels corresponds to the first one of the plurality of antecedents of the first rule; concurrently successively comparing each of the plurality of input labels with a first one of the plurality of antecedents of a second rule; selectively asserting a second rule signal each time one of the plurality of input labels corresponds to the first one of the plurality of antecedents of the second rule; determining a first minimum value corresponding to the first rule and a second minimum value corresponding to the second rule, a minimum determination circuit coupled to the rule bits generating circuit for indicating the first minimum value when the first rule signal is first asserted and a first corresponding one of the plurality of valid bits is in a first logic state which inhibits determination of the first minimum value, the minimum determination circuit indicating the second minimum value when the second rule signal is first asserted and a second corresponding one of the plurality of valid bits is in a second logic state which inhibits determination of the second minimum value; asserting an enable signal when one of the first minimum value and the second minimum value is asserted; and selectively storing a one of the plurality of grades in a latch circuit when the enable signal is asserted, wherein a last one of the plurality of grades latched by the latch circuit is a first maximum output value, the latch circuit being coupled to the minimum determination circuit for receiving the one of the plurality of grades. 17. The method of claim 14 further comprising the step of: outputting the input labels corresponding to the first portion of the plurality of grades in a second order based on magnitude.