1. A computer implemented method for implementing analog behavioral modeling and IP (intellectual property) integration using a Hardware Description Language, comprising: at least one processor or at least one processor core executing a process, the process comprising: detecting an incompatible connection that interacts with a wire in a digital modeling environment that is represented using digital signals; representing a real-valued net of a built-in nettype in the digital modeling environment with 4-state logic signals; correlating the real-valued net with a corresponding resolution function that is defined natively in the digital modeling environment; and coercing the incompatible connection to the wire based at least in part upon the corresponding resolution function.
1. A computer implemented method for implementing analog behavioral modeling and IP (intellectual property) integration using a Hardware Description Language, comprising: at least one processor or at least one processor core executing a process, the process comprising: detecting an incompatible connection that interacts with a wire in a digital modeling environment that is represented using digital signals; representing a real-valued net of a built-in nettype in the digital modeling environment with 4-state logic signals; correlating the real-valued net with a corresponding resolution function that is defined natively in the digital modeling environment; and coercing the incompatible connection to the wire based at least in part upon the corresponding resolution function. 10. The computer implemented method of claim 1 , in which the implied interconnect resides in a parent block that includes two child blocks and connects the two child blocks in the digital modeling environment.