1. In a digital computer system (CS101) including: processor means (JP114) for performing operations upon operands, memory means (MEM 112) for storing said operands and procedures, said procedures including: S-Language instructions for controlling said operations; and, names referring to certain of said operands to be operated upon, and bus means (MOD 140, JPB 142) connected between the memory means and the processor means for conducting said instructions, names and operands between said memory means and said processor means; said processor means comprising: means for addressing said operands, including: name table means (10350) for storing name table entries, each of said name table entries corresponding to one of said names included in each one of said procedures and each of said name table entries comprising: first data from which may be determined an address of a location in said memory means of said operand referred to by one of said names, and second data identifying a format of said operand referred to by said one of said names; and, translation means (NAME TRANS UNIT 27015) connected to said bus means and responsive to said name table entries for providing outputs to said memory means representing said addresses in said memory means of said operands referred to by said names, ALU means (2034, 2074) for performing said operations, receiving means (INSTB 20262) connected to said bus means for receiving said instructions from said memory means, and microcode control means (10240, 27003, 27013) connected between said receiving means and said ALU means for providing sequences of microinstructions for controlling said ALU means, said sequences being selected from a plurality of sequences of microinstructions, one sequence corresponding to each of said instructions received by said receiving means.
1. In a digital computer system (CS101) including: processor means (JP114) for performing operations upon operands, memory means (MEM 112) for storing said operands and procedures, said procedures including: S-Language instructions for controlling said operations; and, names referring to certain of said operands to be operated upon, and bus means (MOD 140, JPB 142) connected between the memory means and the processor means for conducting said instructions, names and operands between said memory means and said processor means; said processor means comprising: means for addressing said operands, including: name table means (10350) for storing name table entries, each of said name table entries corresponding to one of said names included in each one of said procedures and each of said name table entries comprising: first data from which may be determined an address of a location in said memory means of said operand referred to by one of said names, and second data identifying a format of said operand referred to by said one of said names; and, translation means (NAME TRANS UNIT 27015) connected to said bus means and responsive to said name table entries for providing outputs to said memory means representing said addresses in said memory means of said operands referred to by said names, ALU means (2034, 2074) for performing said operations, receiving means (INSTB 20262) connected to said bus means for receiving said instructions from said memory means, and microcode control means (10240, 27003, 27013) connected between said receiving means and said ALU means for providing sequences of microinstructions for controlling said ALU means, said sequences being selected from a plurality of sequences of microinstructions, one sequence corresponding to each of said instructions received by said receiving means. 2. The digital computer system of claim 1, wherein all of said names are of uniform length and format.