10. A method for double programming a multi-level-cell (MLC) in a multi-bit-cell (MBC) of a charge trapping memory, the charge trapping memory having an array of charge trapping memory cells connecting to a plurality of word lines, each word line is connected to a plurality of charge trapping memory cells, each charge trapping memory cell having a first trapping site and a second trapping site, comprising: receiving a data pattern including a plurality of programming levels; programming a plurality of charge trapping cells along a word line, comprising: during a pre-program phase, conducting a pre-program operation to increase threshold voltages and a pre-program-verify operation to verify the increased threshold voltages of a plurality of charge trapping memory cells along the word line, the pre-program verify operation verifying the charge trapping memory cells to a pre-program-verify levels; and during a post-program phase, conducting a post-programming operation to farther increase threshold voltages and a post-program-verify operation to verify the farther increased threshold voltages of the plurality of charge trapping cells along the word line, the post-program verify operation verifying the charge trapping memory cells to corresponding predetermined program-verify levels; wherein the first program-verify levels are less than the corresponding predetermined program-verify levels.
10. A method for double programming a multi-level-cell (MLC) in a multi-bit-cell (MBC) of a charge trapping memory, the charge trapping memory having an array of charge trapping memory cells connecting to a plurality of word lines, each word line is connected to a plurality of charge trapping memory cells, each charge trapping memory cell having a first trapping site and a second trapping site, comprising: receiving a data pattern including a plurality of programming levels; programming a plurality of charge trapping cells along a word line, comprising: during a pre-program phase, conducting a pre-program operation to increase threshold voltages and a pre-program-verify operation to verify the increased threshold voltages of a plurality of charge trapping memory cells along the word line, the pre-program verify operation verifying the charge trapping memory cells to a pre-program-verify levels; and during a post-program phase, conducting a post-programming operation to farther increase threshold voltages and a post-program-verify operation to verify the farther increased threshold voltages of the plurality of charge trapping cells along the word line, the post-program verify operation verifying the charge trapping memory cells to corresponding predetermined program-verify levels; wherein the first program-verify levels are less than the corresponding predetermined program-verify levels. 19. The method of claim 10 , wherein the first program and first program-verify operations during the pre-program phase are conducted in parallel, comprising: simultaneously programming the plurality of charge trapping cells along the word line to a first pre-program level, a second pre-program level, and a third pre-program level; and simultaneously verifying the plurality of charge trapping cells along the word line to a first pre-program-verify level, a second pre-program-verify level and a third pre-program-verify level.