13. A data processing system to provide a capacitance to a design an integrated circuit comprising: a memory, and a processor coupled to the memory, the processor is configured to receive a layout of the integrated circuit; to apply canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model representing a device having a plurality of first conductors to capture a first capacitance and a second type canonical model representing at least a portion of the device and one or more second conductors of the integrated circuit outside the device to capture a second capacitance; and to determine a capacitance for the layout based on the applying.
13. A data processing system to provide a capacitance to a design an integrated circuit comprising: a memory, and a processor coupled to the memory, the processor is configured to receive a layout of the integrated circuit; to apply canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model representing a device having a plurality of first conductors to capture a first capacitance and a second type canonical model representing at least a portion of the device and one or more second conductors of the integrated circuit outside the device to capture a second capacitance; and to determine a capacitance for the layout based on the applying. 16. The data processing system of claim 13 , wherein the canonical hierarchical models are applied to the layout by a superposition operation, a scaling operation, a substitution operation, a direct application, or a combination thereof.