1. A method comprising: parsing, by a compiler, statements of input program code to generate custom instructions for an instruction set loadable upon a reconfigurable processor, wherein a single custom instruction of the instruction set is generated by aggregating the statements of input program code according to one or more constraints that, based upon physical limitations imposed by a framework generator, prevent a terminal conflict resulting from an assumption that, independently of hardware latency requirements of the reconfigurable processor, the single custom instruction may be accomplished in a single clock cycle of the reconfigurable processor; analyzing, by the compiler, the statements of input program code to determine capabilities of the reconfigurable processor that are being utilized by the custom instructions, wherein the capabilities of the reconfigurable processor comprise information regarding: access capabilities of the custom instructions; calling capabilities of the custom instructions; and support capabilities of the custom instructions; generating, by the compiler, a custom instruction description file including the custom instructions; generating, by the compiler, a framework capabilities description file including information regarding the capabilities of the reconfigurable processor that are being utilized by the custom instructions; adapting, by a timing manager, the custom instruction description file for hardware timing of the reconfigurable processor, thereby generating a timing adapted custom instruction description file; and adapting, by the timing manager, the framework capabilities description file to include information regarding the adapting of the custom instruction description file, thereby generating a timing adapted framework capabilities description file.
1. A method comprising: parsing, by a compiler, statements of input program code to generate custom instructions for an instruction set loadable upon a reconfigurable processor, wherein a single custom instruction of the instruction set is generated by aggregating the statements of input program code according to one or more constraints that, based upon physical limitations imposed by a framework generator, prevent a terminal conflict resulting from an assumption that, independently of hardware latency requirements of the reconfigurable processor, the single custom instruction may be accomplished in a single clock cycle of the reconfigurable processor; analyzing, by the compiler, the statements of input program code to determine capabilities of the reconfigurable processor that are being utilized by the custom instructions, wherein the capabilities of the reconfigurable processor comprise information regarding: access capabilities of the custom instructions; calling capabilities of the custom instructions; and support capabilities of the custom instructions; generating, by the compiler, a custom instruction description file including the custom instructions; generating, by the compiler, a framework capabilities description file including information regarding the capabilities of the reconfigurable processor that are being utilized by the custom instructions; adapting, by a timing manager, the custom instruction description file for hardware timing of the reconfigurable processor, thereby generating a timing adapted custom instruction description file; and adapting, by the timing manager, the framework capabilities description file to include information regarding the adapting of the custom instruction description file, thereby generating a timing adapted framework capabilities description file. 5. The method of claim 1 , wherein the adapting the custom instruction description file for hardware timing of the reconfigurable processor comprises: analyzing individual case statements of the custom instructions to determine how many physical clock cycles to spread those instructions over in order to make target hardware timing requirements with respect to the reconfigurable processor.