13. A computer implemented method for generating compiler code selector rules from an architecture description, the compiler code selector rules for use in a compiler that translates source code into machine instructions of a target processor, the method comprising: generating a plurality of semantic statements from semantic information included in a target processor architecture model of a target processor, the target processor architecture model described in a processor architecture description language, said semantic information describing an instruction set, wherein said target processor architecture model comprises semantic information and syntax information for the machine instructions, and description of non-terminals of the target processor; associating assembly syntax with semantic information; applying, to said semantic information, at least one semantic transformation from a library of pre-defined semantic transformations to generate a single semantic statement from a sequence of at least two of said plurality of semantic statements; accessing basic rules having tree patterns that map from source code operations to semantic patterns; permuting said basic rules based on said non-terminals to form set of permuted mapping rules; and matching semantic patterns of said permuted mapping rules to said semantic statements to form a description of said complier code selector rules comprising mappings from source code operations to associated assembly syntax; and mapping a sequence of two or more source code operations to a single machine instruction based on the accessed rules that matches from semantic statements to semantic patterns.
13. A computer implemented method for generating compiler code selector rules from an architecture description, the compiler code selector rules for use in a compiler that translates source code into machine instructions of a target processor, the method comprising: generating a plurality of semantic statements from semantic information included in a target processor architecture model of a target processor, the target processor architecture model described in a processor architecture description language, said semantic information describing an instruction set, wherein said target processor architecture model comprises semantic information and syntax information for the machine instructions, and description of non-terminals of the target processor; associating assembly syntax with semantic information; applying, to said semantic information, at least one semantic transformation from a library of pre-defined semantic transformations to generate a single semantic statement from a sequence of at least two of said plurality of semantic statements; accessing basic rules having tree patterns that map from source code operations to semantic patterns; permuting said basic rules based on said non-terminals to form set of permuted mapping rules; and matching semantic patterns of said permuted mapping rules to said semantic statements to form a description of said complier code selector rules comprising mappings from source code operations to associated assembly syntax; and mapping a sequence of two or more source code operations to a single machine instruction based on the accessed rules that matches from semantic statements to semantic patterns. 19. The method of claim 13 , further comprising creating a tree pattern for a rule not in said basic rules by analyzing a complex semantic statement of said extracted semantic information.