17. The circuit of claim 16 , wherein said transmit buffer is a first-in-first-out buffer; the circuit comprises a memory storing a sequence of descriptors; said code is arranged so as when executed to set up the data transfer engine by indicating to it the sequence of descriptors; the data transfer engine is arranged to process of the indicated sequence of descriptors; and the sequence of descriptors comprises: a first descriptor configured to operate the data transfer engine to input said read request word into the first-in-first-out transmit buffer; one or more subsequent descriptors configured to operate the data transfer engine to input a number of additional words into the first-in-first-out transmit buffer behind the read request word, the number being at least sufficient to fill said first-in-first-out transmit buffer to an upper stall threshold and arranged so as to generate a stall until said response word has been returned from the slave device; and following said subsequent descriptors in the sequence, one or more control descriptors configured to operate the data transfer engine to perform said disabling of the first-in-first-out receive buffer, wherein the data transfer engine is configured such that the processing of said one or more control descriptors is synchronized to release of said stall of the first-in-first-out transmit buffer.
17. The circuit of claim 16 , wherein said transmit buffer is a first-in-first-out buffer; the circuit comprises a memory storing a sequence of descriptors; said code is arranged so as when executed to set up the data transfer engine by indicating to it the sequence of descriptors; the data transfer engine is arranged to process of the indicated sequence of descriptors; and the sequence of descriptors comprises: a first descriptor configured to operate the data transfer engine to input said read request word into the first-in-first-out transmit buffer; one or more subsequent descriptors configured to operate the data transfer engine to input a number of additional words into the first-in-first-out transmit buffer behind the read request word, the number being at least sufficient to fill said first-in-first-out transmit buffer to an upper stall threshold and arranged so as to generate a stall until said response word has been returned from the slave device; and following said subsequent descriptors in the sequence, one or more control descriptors configured to operate the data transfer engine to perform said disabling of the first-in-first-out receive buffer, wherein the data transfer engine is configured such that the processing of said one or more control descriptors is synchronized to release of said stall of the first-in-first-out transmit buffer. 25. The circuit of claim 17 , wherein the upper stall threshold of the first-in-first-out transmit buffer is a programmable, such that it can be set to a number of words less than a maximum capacity of the transmit buffer.