11. A system comprising: a converter configured to receive, at an input of the converter, a first value of a short binary representation corresponding to a search space character, and to convert the short binary representation to a first long binary representation corresponding to the search space character, the first long binary representation having a bit at a first position set to a first bit value, the first position corresponding to the first value of the short binary representation, the converter being configured to generate a long binary representation having the bit at the first position set to the first bit value only when the value at the input of the converter is the first value of the short binary representation; a comparison circuit configured to receive at a first input the first long binary representation, and at a second input a second long binary representation, corresponding to a set of search characters, and to generate a binary output, the binary output having: a binary value indicating that the search space character matches a search character when a bit at the first position in the second long binary representation has a second bit value; and a binary value indicating that the search space character does not match a search character otherwise.
11. A system comprising: a converter configured to receive, at an input of the converter, a first value of a short binary representation corresponding to a search space character, and to convert the short binary representation to a first long binary representation corresponding to the search space character, the first long binary representation having a bit at a first position set to a first bit value, the first position corresponding to the first value of the short binary representation, the converter being configured to generate a long binary representation having the bit at the first position set to the first bit value only when the value at the input of the converter is the first value of the short binary representation; a comparison circuit configured to receive at a first input the first long binary representation, and at a second input a second long binary representation, corresponding to a set of search characters, and to generate a binary output, the binary output having: a binary value indicating that the search space character matches a search character when a bit at the first position in the second long binary representation has a second bit value; and a binary value indicating that the search space character does not match a search character otherwise. 13. The system of claim 11 , wherein the comparison circuit comprises a bit-wise AND gate having a first bus input, a second bus input, and a bus output, the bit-wise AND gate being configured to set to a value of binary 1 each bit of the bus output for which the corresponding bit at the first bus input has a value of binary 1 and the corresponding bit at the second bus input has a value of binary 1, and to set the remaining bits of the bus output to a value of binary 0.