17. A system for implementing multi-power domain digital or mixed-signal verification and low power simulation of an electronic circuit design, comprising: a non-transitory computer accessible medium having stored thereupon a computer program code for implementing the multi-domain digital or mixed signal verification and low power simulation of the electronic circuit design; at least one processor that is to execute the computer program code to: identify one or more schematics of the electronic circuit design; generate one or more one or more net or terminal sets or one or more overriding net or terminal sets for the one or more schematics of the electronic circuit design by referencing a power data file for the electronic circuit design, wherein the power data file for the electronic circuit design includes a specification of one or more power-saving techniques and data or information for power intent for at least a portion of the electronic circuit design to provide portability of the power intent across multiple electronic circuit design tools; and perform verification or simulation of the electronic circuit design by using at least the one or more net or terminal sets or the one or more overriding net or terminal sets.
17. A system for implementing multi-power domain digital or mixed-signal verification and low power simulation of an electronic circuit design, comprising: a non-transitory computer accessible medium having stored thereupon a computer program code for implementing the multi-domain digital or mixed signal verification and low power simulation of the electronic circuit design; at least one processor that is to execute the computer program code to: identify one or more schematics of the electronic circuit design; generate one or more one or more net or terminal sets or one or more overriding net or terminal sets for the one or more schematics of the electronic circuit design by referencing a power data file for the electronic circuit design, wherein the power data file for the electronic circuit design includes a specification of one or more power-saving techniques and data or information for power intent for at least a portion of the electronic circuit design to provide portability of the power intent across multiple electronic circuit design tools; and perform verification or simulation of the electronic circuit design by using at least the one or more net or terminal sets or the one or more overriding net or terminal sets. 23. The system of claim 17 , wherein the at least one processor that is to generate the one or more net or terminal sets or the one or more overriding net or terminal sets by referencing the power data file is further to: specify or cause to specify a net or terminal expression in a power or ground tap schematic; and specify a net or terminal set at a hierarchical level.