2. The converter of claim 1 wherein said first and second sections each receives the same number of bits in said digital word.
2. The converter of claim 1 wherein said first and second sections each receives the same number of bits in said digital word. 3. The converter of claim 2 in combination with a second converter of like structure and further comprising: means for dividing said digital word into four groups of bits with the most significant bit group and the next to the most significant bit group being applied respectively to said first and second sections of said converter and the least significant bit group and next to the least significant bit group being applied respectively to the second and first sections of said second converter; means for applying a fraction of the potential at said reference input terminals to said second converter, said fraction being equal to the ratio of resistors in said first and second resistor ladders; and means for combining said analog output of said converter with said fraction of the analog output of said second converter whereby said combining produces a response that represents the combined word bit response capability of all of said sections.