5. A system, comprising: a processor configured to: generate, for a hierarchical name set comprising a plurality of hierarchical names produced during hardware descriptor language (HDL) synthesis of a design, a directed graph and a tree using the hierarchical name set, wherein the directed graph and the tree each comprise a plurality of nodes, each of the plurality of hierarchical names includes a respective quantity of tokens, and each of the nodes corresponds to at least one of the respective quantity of tokens; generate a respective hierarchical path identifier for an original name in the hierarchical name set by using the directed graph and the tree, wherein the original name includes a first quantity of tokens, and the respective hierarchical path identifier includes a subset of the first quantity of tokens that includes fewer tokens than the first quantity of tokens; and associate the original name in the hierarchical name set with the respective hierarchical path identifier.
5. A system, comprising: a processor configured to: generate, for a hierarchical name set comprising a plurality of hierarchical names produced during hardware descriptor language (HDL) synthesis of a design, a directed graph and a tree using the hierarchical name set, wherein the directed graph and the tree each comprise a plurality of nodes, each of the plurality of hierarchical names includes a respective quantity of tokens, and each of the nodes corresponds to at least one of the respective quantity of tokens; generate a respective hierarchical path identifier for an original name in the hierarchical name set by using the directed graph and the tree, wherein the original name includes a first quantity of tokens, and the respective hierarchical path identifier includes a subset of the first quantity of tokens that includes fewer tokens than the first quantity of tokens; and associate the original name in the hierarchical name set with the respective hierarchical path identifier. 8. The system of claim 5 , wherein the design is configured for implementation on a programmable chip.