13. The integrated circuit chip of claim 12 , wherein the at least one state block of the plurality of state blocks is coupled to at least one current state of said current state vector, said at least one state block further comprising at least one of each of: a. a symbol memory circuit to store said ‘m’ bit symbol; b. a symbol evaluation circuit coupled to said symbol memory circuit to evaluate match of said ‘m’ bit symbol stored in said symbol memory circuit with said plurality of input symbols of said content; c. a state dependent vector memory circuit to store ‘n’ bit state transition control corresponding to said ‘n’ states; and d. a partial state evaluation circuit coupled to said symbol evaluation circuit, said at least one current state and said state dependent vector memory circuit to perform partial state transition evaluation and generate a partial state transition signal for transition of said current state from at least one first state of said ‘n’ states to at least one second state of said ‘n’ states.
13. The integrated circuit chip of claim 12 , wherein the at least one state block of the plurality of state blocks is coupled to at least one current state of said current state vector, said at least one state block further comprising at least one of each of: a. a symbol memory circuit to store said ‘m’ bit symbol; b. a symbol evaluation circuit coupled to said symbol memory circuit to evaluate match of said ‘m’ bit symbol stored in said symbol memory circuit with said plurality of input symbols of said content; c. a state dependent vector memory circuit to store ‘n’ bit state transition control corresponding to said ‘n’ states; and d. a partial state evaluation circuit coupled to said symbol evaluation circuit, said at least one current state and said state dependent vector memory circuit to perform partial state transition evaluation and generate a partial state transition signal for transition of said current state from at least one first state of said ‘n’ states to at least one second state of said ‘n’ states. 14. The integrated circuit chip of claim 13 , wherein the at least one state control block further comprises: a. a state transition evaluation circuit coupled to said plurality of partial state transition, signals to perform state transition evaluation for transition of said current state from at least one first state of said ‘n’ states to a next state of at least one second state of said ‘n’ states; b. at least one ‘n’ bit state initialization vector memory circuit to store an initial or start state value for said ‘n’ states of said at least one finite state automata; and c. at least one ‘n’ bit current state vector memory circuit coupled to said ‘n’ bit state initialization vector memory and said state transition evaluation circuit to load and store a current state value from a set of said ‘n’ states of said at least one finite state automata.