9. An apparatus for verifying a property of a design for a system, the apparatus comprising: instructions that when executed by a processor provide, a design description interface to receive a high level design description of the system; a model extractor in communication with the design description interface, the model extractor to extract a numeric model in response to the high level design description of the system, the numeric model including one or more numeric formulas; a bounded model checker in communication with the model extractor, the bounded model checker to perform bounded model checking on the numeric model, the bounded model checker including a constraint solver using a general numeric backtracking algorithm for searching in a space of non-Boolean structures for a satisfying assignment to one or more logical formulas generated by the bounded model checker; and a verification output interface in communication with the bounded model checker, the verification output interface to determine if a functional property of the system is verified or to prove that the system can not be verified.
9. An apparatus for verifying a property of a design for a system, the apparatus comprising: instructions that when executed by a processor provide, a design description interface to receive a high level design description of the system; a model extractor in communication with the design description interface, the model extractor to extract a numeric model in response to the high level design description of the system, the numeric model including one or more numeric formulas; a bounded model checker in communication with the model extractor, the bounded model checker to perform bounded model checking on the numeric model, the bounded model checker including a constraint solver using a general numeric backtracking algorithm for searching in a space of non-Boolean structures for a satisfying assignment to one or more logical formulas generated by the bounded model checker; and a verification output interface in communication with the bounded model checker, the verification output interface to determine if a functional property of the system is verified or to prove that the system can not be verified. 10. The apparatus of claim 9 , wherein the bounded model checker further includes an arithmetic satisfiability solver to search for a numeric assignment of numbers to variables in the one or more numeric formulas generated by the bounded model checker to find a solution to the numeric formulas.