21. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for implementing analog behavioral modeling and IP (intellectual property) integration using a Hardware Description Language, the set of acts comprising: determining or identifying, with a nettype and resolution function management module at least partially stored in memory and including or functioning in conjunction with at least one processor or at least one processor core, a set of built-in nettypes including at least one wire-real nettype in a SystemVerilog modeling environment; defining a discipline with a domain type of a domain into a set of native real modeling capabilities of the SystemVerilog modeling environment at least by binding one or more attributes of the domain; characterizing at least one real-valued net of one or more real-valued nets with the discipline associated with the at least one real-valued net and one or more characteristics of the discipline; determining or identifying plurality of resolution functions for the set of built-in nettypes into the set of native real modeling capabilities of the SystemVerilog modeling environment, the plurality of resolution functions including at least one built-in resolution function and at least one modified resolution function modified from a built-in resolution function; porting an analog or a mixed-signal portion including at least the at least one real-valued net of the one or more real-valued nets in an electronic design by using at least the set of native real modeling capabilities of the SystemVerilog modeling environment without recreating details of the analog or mixed-signal portion; and reducing computational resource utilization at least by elaborating the electronic design into an elaborated electronic design and by performing multiple verification or simulation tasks, at a simulation or verification module residing on one computing node and receiving the electronic design from a separate computing node, for the elaborated electronic design with the set of native real modeling capabilities of the SystemVerilog modeling environment.
21. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for implementing analog behavioral modeling and IP (intellectual property) integration using a Hardware Description Language, the set of acts comprising: determining or identifying, with a nettype and resolution function management module at least partially stored in memory and including or functioning in conjunction with at least one processor or at least one processor core, a set of built-in nettypes including at least one wire-real nettype in a SystemVerilog modeling environment; defining a discipline with a domain type of a domain into a set of native real modeling capabilities of the SystemVerilog modeling environment at least by binding one or more attributes of the domain; characterizing at least one real-valued net of one or more real-valued nets with the discipline associated with the at least one real-valued net and one or more characteristics of the discipline; determining or identifying plurality of resolution functions for the set of built-in nettypes into the set of native real modeling capabilities of the SystemVerilog modeling environment, the plurality of resolution functions including at least one built-in resolution function and at least one modified resolution function modified from a built-in resolution function; porting an analog or a mixed-signal portion including at least the at least one real-valued net of the one or more real-valued nets in an electronic design by using at least the set of native real modeling capabilities of the SystemVerilog modeling environment without recreating details of the analog or mixed-signal portion; and reducing computational resource utilization at least by elaborating the electronic design into an elaborated electronic design and by performing multiple verification or simulation tasks, at a simulation or verification module residing on one computing node and receiving the electronic design from a separate computing node, for the elaborated electronic design with the set of native real modeling capabilities of the SystemVerilog modeling environment. 29. The article of manufacture of claim 21 , wherein the act of resolving the multiple real-valued drivers comprises: identifying at least one of the plurality of resolution functions based at least upon the multiple real-valued drivers; identifying or declaring one or more disciplines for the multiple real-valued drivers; and correlating the at least one of the plurality of resolution functions with the one or more disciplines, wherein associating the resolution function is performed via a discipline declaration process, via a default setting, via direct declaration, or based at least in part upon connectivity or usage of wreal signals in a design.