15. A memory system comprising: a plurality of data storage cells; and a controller configured to: compute a first check code for first data, wherein the first check code corresponds to a first matrix multiplication of the first data and a matrix; selectively invert bits of the first check code to generate a second check code according to an inversion pattern, wherein the inversion pattern corresponds to a second matrix multiplication of an initial data comprising erased states and the matrix; and program the first data and the second check code to the plurality of data storage cells.
15. A memory system comprising: a plurality of data storage cells; and a controller configured to: compute a first check code for first data, wherein the first check code corresponds to a first matrix multiplication of the first data and a matrix; selectively invert bits of the first check code to generate a second check code according to an inversion pattern, wherein the inversion pattern corresponds to a second matrix multiplication of an initial data comprising erased states and the matrix; and program the first data and the second check code to the plurality of data storage cells. 18. The memory system of claim 15 , wherein the data storage cells comprise flash memory cells.