1. A multi-speed logic analyzer, comprising: first and second logic analyzer sections each including a memory circuit to store input data and a word recognizer to detect a predetermined word from said input data for controlling said memory circuit; and a counter to count a clock signal in accordance with the outputs from said word recognizers of said first and second logic analyzer sections, wherein said counter starts to count when said word recognizer of said first logic analyzer section detects a first predetermined word and stops counting when said word recognizer of said second logic analyzer section detects a second predetermined word; wherein clock signals for said first and second logic analyzer sections are different from each other.
1. A multi-speed logic analyzer, comprising: first and second logic analyzer sections each including a memory circuit to store input data and a word recognizer to detect a predetermined word from said input data for controlling said memory circuit; and a counter to count a clock signal in accordance with the outputs from said word recognizers of said first and second logic analyzer sections, wherein said counter starts to count when said word recognizer of said first logic analyzer section detects a first predetermined word and stops counting when said word recognizer of said second logic analyzer section detects a second predetermined word; wherein clock signals for said first and second logic analyzer sections are different from each other. 2. A logic analyzer according to claim 1 wherein said second logic analyzer section further comprises means for receiving and storing said clock signal for said first logic analyzer section.