1. An inherently microprogrammable high level language processor which includes an electrical interconnection with a storage device for executing an interpretable language string stored in said storage device, wherein said string includes machine level operation codes, and for executing one of a plurality of elementary language programs stored in said storage device, each program being represented by a machine level operation code, comprising: a. first extration means for extracting a machine level operation code via said electrical interconnection from said interpretable language string stored in said storage device for use in locating the one of the elementary language programs stored in said storage device which is represented by the extracted code; b. second extraction means for extracting an elementary language operation code via said electrical interconnection from said one elementary language program stored in said storage device; c. decoding means for decoding the extracted elementary language operation code; and d. logic means connected to said decoding means for executing the elementary operation which is represented by the elementary language operation code.
1. An inherently microprogrammable high level language processor which includes an electrical interconnection with a storage device for executing an interpretable language string stored in said storage device, wherein said string includes machine level operation codes, and for executing one of a plurality of elementary language programs stored in said storage device, each program being represented by a machine level operation code, comprising: a. first extration means for extracting a machine level operation code via said electrical interconnection from said interpretable language string stored in said storage device for use in locating the one of the elementary language programs stored in said storage device which is represented by the extracted code; b. second extraction means for extracting an elementary language operation code via said electrical interconnection from said one elementary language program stored in said storage device; c. decoding means for decoding the extracted elementary language operation code; and d. logic means connected to said decoding means for executing the elementary operation which is represented by the elementary language operation code. 8. A processor as set forth in claim 1 in which certain of said elementary language codes have parameters associated therewith, and wherein said second means for extracting further comprises: a. first register means for providing a word address which indicates an elementary language operation code to be extracted from said elementary language program; b. second register means for receiving via said electrical interconnection with said storage device at least one stored word uniquely identified by said word address; c. control means for outputting said elementary language operation code from said second register means and further register means for storing the parameters associated with said elementary language operation code as output from said second register means.