21. Apparatus according to claim 13, further comprising: a check line state generator connected to said word flag memory and connected to said computing unit, whereas said check line state generator is designed for generating output signals reflecting the results of checking operations taking place in said computing unit.
21. Apparatus according to claim 13, further comprising: a check line state generator connected to said word flag memory and connected to said computing unit, whereas said check line state generator is designed for generating output signals reflecting the results of checking operations taking place in said computing unit. 22. Apparatus according to claim 21, further comprising: a control circuit connected to said check line sate generator and to said word flag memory, said control circuit being designed for issuing block flags, word flags and control signals used for error correction.