7. A system comprising: one or more processing units configured to execute programming instructions; and one or more memory elements configured to store programming instructions executable by the one or more processing units to: parse a first file containing an original Register Transfer Language (RTL) code representative of one or more functional circuit blocks; automatically identify, according to information contained in a configuration file, specific sections of the original RTL code as the first file is parsed; automatically rewrite the identified specific sections of the original RTL code according to transformation definitions contained in the configuration file in a way that ensures that the transformed identified specific sections of the original RTL code synthesize to desired circuit structures; and output a second file containing a modified RTL code comprising the transformed identified specific sections of the original RTL code, wherein the modified RTL code and the original RTL code correspond to identical overall logic functionality.
7. A system comprising: one or more processing units configured to execute programming instructions; and one or more memory elements configured to store programming instructions executable by the one or more processing units to: parse a first file containing an original Register Transfer Language (RTL) code representative of one or more functional circuit blocks; automatically identify, according to information contained in a configuration file, specific sections of the original RTL code as the first file is parsed; automatically rewrite the identified specific sections of the original RTL code according to transformation definitions contained in the configuration file in a way that ensures that the transformed identified specific sections of the original RTL code synthesize to desired circuit structures; and output a second file containing a modified RTL code comprising the transformed identified specific sections of the original RTL code, wherein the modified RTL code and the original RTL code correspond to identical overall logic functionality. 9. The system of claim 7 , wherein the one or more memory elements are further configured to store programming instructions executable by the one or more processing units to: synthesize the modified RTL code to obtain a netlist corresponding to the modified RTL code implementing the identical logic functionality.