23. A speech recognition circuit comprising: an input buffer for receiving processed speech parameters; lexical memory containing lexical data for word recognition, said lexical data comprising a plurality of lexical tree data structures, each lexical tree data structure comprising a model of words having common prefix components, the initial component of each lexical tree data structure being unique; a plurality of lexical tree processors connected in parallel to said input buffer for processing the speech parameters in parallel to perform parallel lexical tree processing for word recognition by accessing said lexical data in said lexical memory; results memory connected to said lexical tree processors for storing processing results from said lexical tree processors and lexical tree identifiers to identify lexical trees to be processed by said lexical tree processors; and a control processor for controlling said lexical tree processors to process lexical trees identified in said results memory by performing parallel processing on a plurality of said lexical tree data structures.
23. A speech recognition circuit comprising: an input buffer for receiving processed speech parameters; lexical memory containing lexical data for word recognition, said lexical data comprising a plurality of lexical tree data structures, each lexical tree data structure comprising a model of words having common prefix components, the initial component of each lexical tree data structure being unique; a plurality of lexical tree processors connected in parallel to said input buffer for processing the speech parameters in parallel to perform parallel lexical tree processing for word recognition by accessing said lexical data in said lexical memory; results memory connected to said lexical tree processors for storing processing results from said lexical tree processors and lexical tree identifiers to identify lexical trees to be processed by said lexical tree processors; and a control processor for controlling said lexical tree processors to process lexical trees identified in said results memory by performing parallel processing on a plurality of said lexical tree data structures. 40. A speech recognition circuit according to claim 23 , wherein said input buffer receives said speech parameters as feature vectors.