9. The method of claim 8 , further comprising identifying at least one component instantiated by an instrumented HDL model that is in a read state for at least two consecutive cycles of a simulation; and indicating that the component of the hardware system is available for sharing in performing another function during at least a portion of the time the at least one model is in the read state.
9. The method of claim 8 , further comprising identifying at least one component instantiated by an instrumented HDL model that is in a read state for at least two consecutive cycles of a simulation; and indicating that the component of the hardware system is available for sharing in performing another function during at least a portion of the time the at least one model is in the read state. 10. The method of claim 9 , wherein compiling the high level language representation further comprises: identifying constructs of the high level language representation; and mapping the constructs to instructions and pseudo-instructions of the assembly language.