12. The apparatus of claim 1 , further comprising a decoder that generates the word line bias voltages, and a global bus for transmitting the word line voltages, wherein connections between the decoder and the global bus are routed within one or more metal layers above the three-dimensional non-volatile memory array.
12. The apparatus of claim 1 , further comprising a decoder that generates the word line bias voltages, and a global bus for transmitting the word line voltages, wherein connections between the decoder and the global bus are routed within one or more metal layers above the three-dimensional non-volatile memory array. 13. The apparatus of claim 12 , wherein the connections are routed to a first edge of the array, then to the global bus at a second edge of the array.