4. The invention in accordance with claim 3, wherein said P-processor includes N instruction addressing means responsive to a fetched microinstruction for fetching a selected one or more N instructions from said N memory.
4. The invention in accordance with claim 3, wherein said P-processor includes N instruction addressing means responsive to a fetched microinstruction for fetching a selected one or more N instructions from said N memory. 5. The invention in accordance with claim 4, wherein said N data section of said N-processor includes M command storage means for storing an M-level command produced thereby, and said P-processor includes N command storage means for storing an N-level command produced thereby.