15. A method of generating clock gating circuitry for a circuit design model, comprising: for each one of a plurality of interconnected flop gates in a first netlist of the circuit design model, determining a respective first Boolean expression of input don't toggle (IDT) conditions by performing steps using one or more programmed processors, the steps including: for each flop gate (X) in the transitive fan-in cone of flop gate (Y): determining a respective second Boolean expression of a conjunction of a non-inverting path sensitization from the output of X to the input of Y, a one flop delay of the non-inverting path sensitization from the output of X to the input of Y, and the Boolean expression of the IDT conditions of X; determining a respective third Boolean expression of a conjunction of a non-inverting path sensitization from an inverted output of X to the input of Y, a one flop delay of the non-inverting path sensitization from the inverted output of X to the input of Y, and the Boolean expression of the IDT conditions of X; and determining a disjunction of the respective second Boolean expressions with respective third Boolean expressions and with a non-inverting path sensitization from the output of Y to the input of Y to produce the respective first Boolean expression of the IDT conditions; inverting the respective first Boolean expressions of the IDT conditions of one or more of the plurality of interconnected flop gates to produce respective Boolean expressions of input toggle conditions; generating a second circuit design model implementing the input toggle conditions; and generating a second netlist that incorporates the second circuit design model with the first circuit design model.
15. A method of generating clock gating circuitry for a circuit design model, comprising: for each one of a plurality of interconnected flop gates in a first netlist of the circuit design model, determining a respective first Boolean expression of input don't toggle (IDT) conditions by performing steps using one or more programmed processors, the steps including: for each flop gate (X) in the transitive fan-in cone of flop gate (Y): determining a respective second Boolean expression of a conjunction of a non-inverting path sensitization from the output of X to the input of Y, a one flop delay of the non-inverting path sensitization from the output of X to the input of Y, and the Boolean expression of the IDT conditions of X; determining a respective third Boolean expression of a conjunction of a non-inverting path sensitization from an inverted output of X to the input of Y, a one flop delay of the non-inverting path sensitization from the inverted output of X to the input of Y, and the Boolean expression of the IDT conditions of X; and determining a disjunction of the respective second Boolean expressions with respective third Boolean expressions and with a non-inverting path sensitization from the output of Y to the input of Y to produce the respective first Boolean expression of the IDT conditions; inverting the respective first Boolean expressions of the IDT conditions of one or more of the plurality of interconnected flop gates to produce respective Boolean expressions of input toggle conditions; generating a second circuit design model implementing the input toggle conditions; and generating a second netlist that incorporates the second circuit design model with the first circuit design model. 18. The method of claim 15 , further comprising approximating the Boolean expressions of the input toggle conditions to decrease complexity of the Boolean expressions.