1. A semiconductor memory device for accessing data of a predetermined number of bits comprising: a single memory cell block means for storing a plurality of words, each word having the predetermined number of bits, said memory cell block means having a plurality of memory cell outputs; a column gate means connected to said memory cell outputs; a gate control means for controlling said column gate means to access and output a predetermined number of consecutive bits of said memory cell outputs, said predetermined number of consecutive bits, including a portion of one word and a portion of a subsequent word, being aligned such that said portion of said subsequent word is followed by said portion of said one word; and a data re-ordering means for re-ordering said predetermined number of consecutive bits to align them such that said portion of said one word is followed by said portion of said subsequent word; wherein said gate control means includes a single column decoder and a bit position decoder each providing signal outputs which, when logically combined, produce signals for controlling said column gate means, said bit position decoder producing a signal indicating a starting bit position in said one word from which the accessing of the predetermined number of bits is to start.
1. A semiconductor memory device for accessing data of a predetermined number of bits comprising: a single memory cell block means for storing a plurality of words, each word having the predetermined number of bits, said memory cell block means having a plurality of memory cell outputs; a column gate means connected to said memory cell outputs; a gate control means for controlling said column gate means to access and output a predetermined number of consecutive bits of said memory cell outputs, said predetermined number of consecutive bits, including a portion of one word and a portion of a subsequent word, being aligned such that said portion of said subsequent word is followed by said portion of said one word; and a data re-ordering means for re-ordering said predetermined number of consecutive bits to align them such that said portion of said one word is followed by said portion of said subsequent word; wherein said gate control means includes a single column decoder and a bit position decoder each providing signal outputs which, when logically combined, produce signals for controlling said column gate means, said bit position decoder producing a signal indicating a starting bit position in said one word from which the accessing of the predetermined number of bits is to start. 3. A semiconductor memory device as claimed in claim 1, wherein said gate control means comprises a selecting means for selecting said predetermined number of bits starting from said starting bit position.