1. An electronic code keyer for automatically generating an ordered arrangement of characters from a first and second sequence of coded signals wherein a plurality of keyer operating parameters may be varied over a wide range of values, said electronic code keyer comprising: input means for generating said first sequence of coded signals; control means for generating said second sequence of coded signals; processor means coupled to said input means and to said control means and responsive to said first sequence of coded signals for generating said ordered arrangement of characters and responsive to said second sequence of coded signals for generating a plurality of instructions for operating said keyer over said wide range of operating parameters; random access memory means coupled to said processor means, said random access memory means having a plurality of addressable memory locations for the storage and read out of said ordered arrangement of characters and said instructions, the read out of said ordered arrangement of characters being determined by said instructions; and output means coupled to said processor means for receiving said ordered arrangement of characters in accordance with said instructions and for transmitting said characters over a wide range of keyer operating parameters in accordance with said instructions.
1. An electronic code keyer for automatically generating an ordered arrangement of characters from a first and second sequence of coded signals wherein a plurality of keyer operating parameters may be varied over a wide range of values, said electronic code keyer comprising: input means for generating said first sequence of coded signals; control means for generating said second sequence of coded signals; processor means coupled to said input means and to said control means and responsive to said first sequence of coded signals for generating said ordered arrangement of characters and responsive to said second sequence of coded signals for generating a plurality of instructions for operating said keyer over said wide range of operating parameters; random access memory means coupled to said processor means, said random access memory means having a plurality of addressable memory locations for the storage and read out of said ordered arrangement of characters and said instructions, the read out of said ordered arrangement of characters being determined by said instructions; and output means coupled to said processor means for receiving said ordered arrangement of characters in accordance with said instructions and for transmitting said characters over a wide range of keyer operating parameters in accordance with said instructions. 9. An electronic code keyer in accordance with claim 1 wherein said second sequence of coded signals includes a pause instruction whereby the transmission of said ordered arrangement of characters may be automatically interrupted for the manual insertion of additional characters followed by the continued automatic transmission of said ordered arrangement of characters.