1. A method of facilitating executing an interpretive language in a system including a processing component, a memory component, and a hardware component, wherein the hardware component provides an interface between the processing component and the memory component, the method of the hardware component comprising: receiving an address from the processing component; determining whether the received address matches a fixed instruction fetch address; determining whether the received address matches one of a plurality of fixed operand fetch addresses; incrementing an interpreter language program counter and sending a current interpretive language address to the memory component when the received address matches the fixed instruction fetch address; sending an operand address to the memory component when the received address matches one of the plurality of fixed operand fetch addresses; sending the received address to the memory component when the received address fails to match the fixed instruction fetch address and any of the plurality of fixed operand fetch addresses; and receiving data from the memory component based on one of the fixed instruction fetch address, the operand address, and the received address.
1. A method of facilitating executing an interpretive language in a system including a processing component, a memory component, and a hardware component, wherein the hardware component provides an interface between the processing component and the memory component, the method of the hardware component comprising: receiving an address from the processing component; determining whether the received address matches a fixed instruction fetch address; determining whether the received address matches one of a plurality of fixed operand fetch addresses; incrementing an interpreter language program counter and sending a current interpretive language address to the memory component when the received address matches the fixed instruction fetch address; sending an operand address to the memory component when the received address matches one of the plurality of fixed operand fetch addresses; sending the received address to the memory component when the received address fails to match the fixed instruction fetch address and any of the plurality of fixed operand fetch addresses; and receiving data from the memory component based on one of the fixed instruction fetch address, the operand address, and the received address. 5. The method of claim 1 , further including: counting a number of times the received address matches the fixed instruction fetch address; and when the number reaches a predetermined threshold, sending a thread switch jump address to the processing component.