16. A host computing device comprising: a processing system; and one or more computer-readable storage media storing instructions that when executed via the processing system cause the host computing device to implement a security module that is configured to: detect connection of a connector for an accessory device to an accessory port of the host computing device based on a logic state combination obtained via a pair of detection pins integrated with the connector, the connector and accessory port configured to support reversible connection of the connector to the accessory port; identify a device type of the accessory device according to the logic state combination, the logic state combination indicating whether the accessory device is a one wire device or a two wire device; ascertain an orientation of the connection of the connector to the accessory port; and configure a switching mechanism of the host computing device to automatically route signals according to the identified device type and the ascertained orientation.
16. A host computing device comprising: a processing system; and one or more computer-readable storage media storing instructions that when executed via the processing system cause the host computing device to implement a security module that is configured to: detect connection of a connector for an accessory device to an accessory port of the host computing device based on a logic state combination obtained via a pair of detection pins integrated with the connector, the connector and accessory port configured to support reversible connection of the connector to the accessory port; identify a device type of the accessory device according to the logic state combination, the logic state combination indicating whether the accessory device is a one wire device or a two wire device; ascertain an orientation of the connection of the connector to the accessory port; and configure a switching mechanism of the host computing device to automatically route signals according to the identified device type and the ascertained orientation. 19. A host computing system as recited in claim 16 , wherein the logic state combination includes high and low logic states conveyed via the pair of detection pins.