1. A computer-implemented method of generating at least a portion of an integrated circuit design, the method comprising: providing a user with an integrated circuit design for a processor or processor peripheral device, the integrated circuit design described by a hardware description language model; assigning default values to a plurality of design parameters from a set of design parameters for the hardware description language model, the plurality of design parameters including at least a cache size parameter and a parameter indicating either to include or not include in the integrated circuit design an interface to memory external to the processor or processor peripheral device; providing a graphical user interface (GUI) displaying a representation of the cache size parameter and a representation of the parameter indicating either to include or not include in the integrated circuit design the interface to memory external to the processor or processor peripheral device; receiving, via the GUI, one or more inputs from the user for at least one of the set of design parameters to customize the integrated circuit design responsive to assigning the default values, the received set of design parameters including a cache size and an indication to include the interface to memory in the integrated circuit design; displaying, via the GUI, a plurality of memory extensions available to an extension algorithm for inclusion in the integrated circuit design based on the indication to include the interface to memory in the integrated circuit design, the plurality of memory extensions including a load and storage memory controller, an instruction fetch memory controller, a host interface for communication with the processor or processor peripheral device, an arbitration unit for memory access, and a random access memory sequencer; receiving, via the GUI, a selection of one or more of the plurality of memory extensions for inclusion in the integrated circuit design; determining, using the extension algorithm, the one or more of the plurality of memory extensions that were selected via the GUI; and generating, by a computer, an updated hardware description language model for the integrated circuit design based on the received set of design parameters and the hardware description language model, wherein the processor or processor peripheral device is fabricated based at least in part on the updated hardware description language model.
1. A computer-implemented method of generating at least a portion of an integrated circuit design, the method comprising: providing a user with an integrated circuit design for a processor or processor peripheral device, the integrated circuit design described by a hardware description language model; assigning default values to a plurality of design parameters from a set of design parameters for the hardware description language model, the plurality of design parameters including at least a cache size parameter and a parameter indicating either to include or not include in the integrated circuit design an interface to memory external to the processor or processor peripheral device; providing a graphical user interface (GUI) displaying a representation of the cache size parameter and a representation of the parameter indicating either to include or not include in the integrated circuit design the interface to memory external to the processor or processor peripheral device; receiving, via the GUI, one or more inputs from the user for at least one of the set of design parameters to customize the integrated circuit design responsive to assigning the default values, the received set of design parameters including a cache size and an indication to include the interface to memory in the integrated circuit design; displaying, via the GUI, a plurality of memory extensions available to an extension algorithm for inclusion in the integrated circuit design based on the indication to include the interface to memory in the integrated circuit design, the plurality of memory extensions including a load and storage memory controller, an instruction fetch memory controller, a host interface for communication with the processor or processor peripheral device, an arbitration unit for memory access, and a random access memory sequencer; receiving, via the GUI, a selection of one or more of the plurality of memory extensions for inclusion in the integrated circuit design; determining, using the extension algorithm, the one or more of the plurality of memory extensions that were selected via the GUI; and generating, by a computer, an updated hardware description language model for the integrated circuit design based on the received set of design parameters and the hardware description language model, wherein the processor or processor peripheral device is fabricated based at least in part on the updated hardware description language model. 5. The method of claim 1 , wherein the processor or processor peripheral device comprises a reduced instruction set computing (RISC) processor, and the hardware description language model comprises a VHDL model.