13. The method of claim 12, wherein the step of obtaining the error correction further comprises obtaining corrected test architecture topology information, wherein the corrected test architecture topology information includes the error correction.
13. The method of claim 12, wherein the step of obtaining the error correction further comprises obtaining corrected test architecture topology information, wherein the corrected test architecture topology information includes the error correction. 14. The method of claim 13 further comprises re-testing the integrated circuit using the corrected test architecture topology information.