5. The computer-implemented method of claim 1 , wherein: for at least a first node in the directed graph the node is realized by special purpose circuitry, and a model implementation associated with the first node is configured to be executed by the special purpose circuitry; and for at least a second node in the directed graph the node is realized by a general purpose microprocessor, and a model implementation associated with the second node is configured to be executed by the general purpose microprocessor.
5. The computer-implemented method of claim 1 , wherein: for at least a first node in the directed graph the node is realized by special purpose circuitry, and a model implementation associated with the first node is configured to be executed by the special purpose circuitry; and for at least a second node in the directed graph the node is realized by a general purpose microprocessor, and a model implementation associated with the second node is configured to be executed by the general purpose microprocessor. 6. The computer-implemented method of claim 5 , wherein the special purpose circuitry is an ASIC.