27. A computer system for verification analysis comprising: a memory which stores instructions; one or more processors coupled to the memory wherein the one or more processors are configured to: obtain a design description including set of constraints wherein the set of constraints includes a multiplication constraint; analyze the set of constraints to identify the multiplication constraint; perform factorization to produce factoring values that solve the multiplication constraint, wherein the factorization is performed on an overflow representation of the number; and solve a design problem within the design description based on the factoring values.
27. A computer system for verification analysis comprising: a memory which stores instructions; one or more processors coupled to the memory wherein the one or more processors are configured to: obtain a design description including set of constraints wherein the set of constraints includes a multiplication constraint; analyze the set of constraints to identify the multiplication constraint; perform factorization to produce factoring values that solve the multiplication constraint, wherein the factorization is performed on an overflow representation of the number; and solve a design problem within the design description based on the factoring values. 29. The system of claim 27 wherein the one or more processors are further configured to loop through the factoring values until one or more values are determined which satisfy other constraints.