1. A method of designing an integrated circuit for use in an application having standards having a plurality of primitives, each of said primitives having a corresponding response, the method comprising: generating a macros description of each of said primitives and the response corresponding to each of said primitives, said macros description including information relating to a number of first fields for each of said primitives and a number of second fields for the response corresponding to each of said primitives; receiving a specification of a behavior of said integrated circuit in response to said primitives, said specification specifying one or more values for each of said second fields; and generating a hardware description language representation for said integrated circuit based on said macros description and said specification.
1. A method of designing an integrated circuit for use in an application having standards having a plurality of primitives, each of said primitives having a corresponding response, the method comprising: generating a macros description of each of said primitives and the response corresponding to each of said primitives, said macros description including information relating to a number of first fields for each of said primitives and a number of second fields for the response corresponding to each of said primitives; receiving a specification of a behavior of said integrated circuit in response to said primitives, said specification specifying one or more values for each of said second fields; and generating a hardware description language representation for said integrated circuit based on said macros description and said specification. 5. The method according to claim 1 , wherein said integrated circuit is an FPGA, the method further comprising programming said FPGA based on said hardware description language representation.