7. A circuitry arrangement for effecting a decoding operation by translating coded word signals into data word signals for use with a data processing device, comprising in combustion: input means to receive coded word signals; translating circuitry means coupled to said input means and formed to translate coded word signals representing first, second and third bits into data word signals representing first and second bits in such a manner that the second and third bits of said coded words are respectively identical to the first and second bits of said data word and further formed to translate coded word signals representing first, second, third, fourth, fifth and sixth bits into data word signals representing first, second, third and fourth bits in such a manner that the second and sixth bits of said coded words are respectively identical to the third and fourth bits of said data words; and output means coupled to said translating circuitry means to receive data word signals therefrom to be transmitted to said data processing device.
7. A circuitry arrangement for effecting a decoding operation by translating coded word signals into data word signals for use with a data processing device, comprising in combustion: input means to receive coded word signals; translating circuitry means coupled to said input means and formed to translate coded word signals representing first, second and third bits into data word signals representing first and second bits in such a manner that the second and third bits of said coded words are respectively identical to the first and second bits of said data word and further formed to translate coded word signals representing first, second, third, fourth, fifth and sixth bits into data word signals representing first, second, third and fourth bits in such a manner that the second and sixth bits of said coded words are respectively identical to the third and fourth bits of said data words; and output means coupled to said translating circuitry means to receive data word signals therefrom to be transmitted to said data processing device. 9. A circuitry arrangement according to claim 7 wherein said input means is a four-stage shift register and wherein said translating circuitry means is formed such that the word boundary of coded data word entering said input means shift register is defined by signals in the third, second and first stages of said input means shift register.