4. A system for determining whether a latch is represented in a Hardware Description Language (HDL) expression of a circuit using data flow analysis, the system comprising: means for identifying a set of variables L.sub.p used in the expression; conducting means, for conducting, for a variable within the set L.sub.p, an uninitialized variable analysis for a given input signal; inferring means, for inferring, if the variable is accessed while uninitialized, a latch for that variable.
4. A system for determining whether a latch is represented in a Hardware Description Language (HDL) expression of a circuit using data flow analysis, the system comprising: means for identifying a set of variables L.sub.p used in the expression; conducting means, for conducting, for a variable within the set L.sub.p, an uninitialized variable analysis for a given input signal; inferring means, for inferring, if the variable is accessed while uninitialized, a latch for that variable. 6. The system of claim 4, further comprising determining means, for determining the conditions under which the variable is modified, and from the determined conditions inferring a clocking signal for the latch.