15. The apparatus of claim 14 , wherein the apparatus determines whether a dictionary memory array within the plurality of dictionary memory arrays stores a valid dictionary word that matches the input data word, comprising: for each dictionary memory array, DMA i , reading DMA, using N−i bits of the hash value as a read address to generate a read word, reading SA i using N−i bits of the hash value as a read address to generate a read status, comparing the read word to the input data word, and asserting an output signal if the read word matches the input data word and the read status indicates the read word is valid, wherein the plurality of dictionary memory arrays generate a plurality of output signals.
15. The apparatus of claim 14 , wherein the apparatus determines whether a dictionary memory array within the plurality of dictionary memory arrays stores a valid dictionary word that matches the input data word, comprising: for each dictionary memory array, DMA i , reading DMA, using N−i bits of the hash value as a read address to generate a read word, reading SA i using N−i bits of the hash value as a read address to generate a read status, comparing the read word to the input data word, and asserting an output signal if the read word matches the input data word and the read status indicates the read word is valid, wherein the plurality of dictionary memory arrays generate a plurality of output signals. 16. The apparatus of claim 15 , wherein determining whether a dictionary memory array within the plurality of dictionary memory arrays stores a valid dictionary word that matches the input data word further comprises: performing an OR operation on the plurality of output signals.