12. A computer system, comprising: an input interface operable to parse a high-level language program, the high-level language program configured to run on a conventional central processing unit, wherein the input interface is operable to identify a hardware resource count included in the high-level language program, wherein the hardware resource count is associated with a code sequence in the high-level language program; a processor operable to generate hardware acceleration logic for implementing the code sequence using the hardware resource count, wherein the hardware resource count specifies the number of resources to use to implement the code sequence on a programmable chip.
12. A computer system, comprising: an input interface operable to parse a high-level language program, the high-level language program configured to run on a conventional central processing unit, wherein the input interface is operable to identify a hardware resource count included in the high-level language program, wherein the hardware resource count is associated with a code sequence in the high-level language program; a processor operable to generate hardware acceleration logic for implementing the code sequence using the hardware resource count, wherein the hardware resource count specifies the number of resources to use to implement the code sequence on a programmable chip. 16. The computer system of claim 12 , wherein the hardware resource count is associated with a maximum resource count.