1. An apparatus of a transmitter, comprising: a bandpass filter (BPF) arranged to produce a transmitter output signal; and a digital front end (DFE) arranged to receive a carrier frequency signal, the DFE comprising: a zero crossing (ZC) pre-distorter (ZCPD) arranged to compensate for ZC distortion introduced by the BPF and produce code words to generate an input signal to be applied to the BPF; a linear phase interpolator (LPI) arranged to interpolate a first interpolated baseband in-phase quadrature-phase (IQ) signal and produce a second interpolated baseband IQ signal; ZC finder circuitry arranged to determine ZC positions of the second interpolated baseband IQ signal; Absolute Value Determiner (ABS) circuitry arranged to produce magnitudes of the second interpolated baseband IQ signal; Amplitude Determiner (AMP) circuitry arranged to determine the magnitudes of the second interpolated baseband IQ signal; and a synchronized First-In-First-Out (Sync FIFO) latch arranged to adjust clocking of the ZC positions and the magnitudes of the second interpolated baseband IQ signal to change a frequency of the ZC positions and the magnitudes of the second interpolated baseband IQ signal to a frequency of the carrier frequency signal and to produce output signals to the ZCPD.
1. An apparatus of a transmitter, comprising: a bandpass filter (BPF) arranged to produce a transmitter output signal; and a digital front end (DFE) arranged to receive a carrier frequency signal, the DFE comprising: a zero crossing (ZC) pre-distorter (ZCPD) arranged to compensate for ZC distortion introduced by the BPF and produce code words to generate an input signal to be applied to the BPF; a linear phase interpolator (LPI) arranged to interpolate a first interpolated baseband in-phase quadrature-phase (IQ) signal and produce a second interpolated baseband IQ signal; ZC finder circuitry arranged to determine ZC positions of the second interpolated baseband IQ signal; Absolute Value Determiner (ABS) circuitry arranged to produce magnitudes of the second interpolated baseband IQ signal; Amplitude Determiner (AMP) circuitry arranged to determine the magnitudes of the second interpolated baseband IQ signal; and a synchronized First-In-First-Out (Sync FIFO) latch arranged to adjust clocking of the ZC positions and the magnitudes of the second interpolated baseband IQ signal to change a frequency of the ZC positions and the magnitudes of the second interpolated baseband IQ signal to a frequency of the carrier frequency signal and to produce output signals to the ZCPD. 3. The apparatus of claim 1 , wherein: the code words comprise a Digital-To-Time Converter (DTC) code word and a Digital Power Amplifier (DPA) code word, and the DFE further comprises: ZC-to-DTC circuitry arranged to receive a value based on an output of the ZCPD to produce a DTC code word and indicate ZC position to a DTC of the transmitter using the DTC code word; and an Amplitude Determiner (AMP)-to-DPA converter arranged to receive a magnitude value to produce the DPA code word to indicate a magnitude to a DPA of the transmitter.