1. A method for comparing the output signals of a register transfer level (RTL) model simulation of a logic circuit and the output signals of a hardware description language (HDL) model simulation of the logic circuit, comprising the steps: starting said RTL model simulation of said logic circuit and said HDL model simulation of said logic circuit in a first process and a second process, respectively, of an operating system supporting an interprocess communication mechanism; and repeating the following steps until a predetermined number of simulation cycles are completed: (i) running said RTL model simulation for a predetermined simulation time period using an input test vector; (ii) retrieving, at the end of said predetermined simulation time period, values of output signals of said RTL model; (iii) sending to said second process, through said interprocess communication mechanism, said output values of said RTL model; (iv) running said HDL model simulation for said predetermined simulation period using said input test vector; (v) retrieving, at the end of said predetermined simulation time period, values of output signals of said HDL model; and (vi) comparing, at the end of said predetermined simulation time period, whether or not said values of said output signals of said RTL model equal said output values of said output signals of said HDL model.
1. A method for comparing the output signals of a register transfer level (RTL) model simulation of a logic circuit and the output signals of a hardware description language (HDL) model simulation of the logic circuit, comprising the steps: starting said RTL model simulation of said logic circuit and said HDL model simulation of said logic circuit in a first process and a second process, respectively, of an operating system supporting an interprocess communication mechanism; and repeating the following steps until a predetermined number of simulation cycles are completed: (i) running said RTL model simulation for a predetermined simulation time period using an input test vector; (ii) retrieving, at the end of said predetermined simulation time period, values of output signals of said RTL model; (iii) sending to said second process, through said interprocess communication mechanism, said output values of said RTL model; (iv) running said HDL model simulation for said predetermined simulation period using said input test vector; (v) retrieving, at the end of said predetermined simulation time period, values of output signals of said HDL model; and (vi) comparing, at the end of said predetermined simulation time period, whether or not said values of said output signals of said RTL model equal said output values of said output signals of said HDL model. 3. A method as in claim 1, wherein said RTL model comprises objects represented in an object-oriented programming language.