2. An apparatus for handling data code words, said apparatus comprising detecting means for detecting erroneous code words, estimating means coupled to said detecting means for estimating replacement code words both for said detected erroneous code words and for at least some code words within a selected interval of said erroneous words, and replacing means coupled to said detecting means and said estimating means for replacing said erroneous code word and said code words within said selected interval by said estimated code words respectively, whereby most undetected errors are thus concealed.
2. An apparatus for handling data code words, said apparatus comprising detecting means for detecting erroneous code words, estimating means coupled to said detecting means for estimating replacement code words both for said detected erroneous code words and for at least some code words within a selected interval of said erroneous words, and replacing means coupled to said detecting means and said estimating means for replacing said erroneous code word and said code words within said selected interval by said estimated code words respectively, whereby most undetected errors are thus concealed. 6. An apparatus as claimed in claim 2, wherein said replacing means comprises a delay line coupled to said detecting means, a shift register coupled to said delay line, an OR gate coupled to said shift register, and a multiplexer coupled to said gate and to said estimating means.