1. A method for extracting a representation of a state machine from a high-level integrated circuit description language, comprising: parsing the high-level integrated circuit description language using a recognition and extraction engine; using the recognition and extraction engine, identifying processes within the integrated circuit description language; determining whether an identified process is a clock process by searching for a condition that changes a state of the process on a clock transition; building a state machine based in part on the identified clock process; and outputting a state machine description based on the built state machine.
1. A method for extracting a representation of a state machine from a high-level integrated circuit description language, comprising: parsing the high-level integrated circuit description language using a recognition and extraction engine; using the recognition and extraction engine, identifying processes within the integrated circuit description language; determining whether an identified process is a clock process by searching for a condition that changes a state of the process on a clock transition; building a state machine based in part on the identified clock process; and outputting a state machine description based on the built state machine. 12. The method of claim 1 , wherein building the state machine comprises generating a textual description of the state machine.