8. A system for assuring a reliability of a chip comprising: a processor configured to: retrieve a design netlist; identify a logic structure in the design netlist; generate a driver based on the logic structure by: verifying a parity; traversing a netlist back from a plurality of netlist outputs; identifying one or more parity protected structures and one or more gates, wherein protected parity structures comprises a duplication protection; and generating an assertion indicative of a parity validity; apply a simulation and a formal model based on the driver; and test an output of the simulation and the formal model.
8. A system for assuring a reliability of a chip comprising: a processor configured to: retrieve a design netlist; identify a logic structure in the design netlist; generate a driver based on the logic structure by: verifying a parity; traversing a netlist back from a plurality of netlist outputs; identifying one or more parity protected structures and one or more gates, wherein protected parity structures comprises a duplication protection; and generating an assertion indicative of a parity validity; apply a simulation and a formal model based on the driver; and test an output of the simulation and the formal model. 9. The system of claim 8 wherein the processor is further configured to: statistically analyze the design netlist; extract checking logic information from the design netlist; and extract gating information from the design netlist; and identify the logic structure in the design netlist based on a statistical analysis of the design netlist, the logic information, and the gating information.