1. A laser diode driver (LDD), comprising: a first digital-to-analog converted (DAC) configured to receive a first color data word and produce, in dependence on the first color data word, a first output current to drive a light source of a first color; a second DAC configured to receive a second color data word and produce, in dependence on the second color data word, a second output current to drive a light source of a second color; a third DAC configured to receive a third color data word and produce, in dependence on the third color data word, a third output current to drive a light source of a third color; and interface circuitry configured to receive a data transfer clock signal, wherein each cycle of the data transfer clock signal includes a low-to-high portion and a high-to-low portion; receive and store a first transfer word in response to the low-to-high portion of a cycle of the data transfer clock signal; receive and store a second transfer word in response to the high-to-low portion of a cycle of the data transfer clock signal; produce the first color data word, the second color data word and the third color data word in dependence on the first and second stored transfer words; and drive the first DAC with the first color data word; drive the second DAC with second color data word; and drive the third DAC with the third color data.
1. A laser diode driver (LDD), comprising: a first digital-to-analog converted (DAC) configured to receive a first color data word and produce, in dependence on the first color data word, a first output current to drive a light source of a first color; a second DAC configured to receive a second color data word and produce, in dependence on the second color data word, a second output current to drive a light source of a second color; a third DAC configured to receive a third color data word and produce, in dependence on the third color data word, a third output current to drive a light source of a third color; and interface circuitry configured to receive a data transfer clock signal, wherein each cycle of the data transfer clock signal includes a low-to-high portion and a high-to-low portion; receive and store a first transfer word in response to the low-to-high portion of a cycle of the data transfer clock signal; receive and store a second transfer word in response to the high-to-low portion of a cycle of the data transfer clock signal; produce the first color data word, the second color data word and the third color data word in dependence on the first and second stored transfer words; and drive the first DAC with the first color data word; drive the second DAC with second color data word; and drive the third DAC with the third color data. 2. The LDD of claim 1 , wherein: the first color data word comprises a first M-bit word; the second color data word comprises a second M-bit word; the third color data word comprises a third M-bit word; the first transfer word comprises a first (3*M)/2 bit word; and the second transfer word comprises a second (3*M)/2 bit word.