1. A Static Random Access Memory (SRAM) memory device comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each row of memory cells being adapted to store a Random Access Memory (RAM) word, said RAM word including a corresponding data word, a corresponding Error Correction Code (ECC) word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations, a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device, a memory controller unit comprising means for selectively configuring the configurable port in one among a plurality of modes, said plurality of modes including: a first mode, wherein the configurable port is configured in such a way to disable the programming of the data word and of the corresponding ECC word of the received RAM word and at the same time enable the programming of the applicative word of the received RAM word during the writing access, and a second mode, wherein the configurable port is configured in such a way to disable the programming of the applicative word of the received RAM word and at the same time enable the programming of the data word and of the corresponding ECC word of the received RAM word during the writing access.
1. A Static Random Access Memory (SRAM) memory device comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each row of memory cells being adapted to store a Random Access Memory (RAM) word, said RAM word including a corresponding data word, a corresponding Error Correction Code (ECC) word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations, a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device, a memory controller unit comprising means for selectively configuring the configurable port in one among a plurality of modes, said plurality of modes including: a first mode, wherein the configurable port is configured in such a way to disable the programming of the data word and of the corresponding ECC word of the received RAM word and at the same time enable the programming of the applicative word of the received RAM word during the writing access, and a second mode, wherein the configurable port is configured in such a way to disable the programming of the applicative word of the received RAM word and at the same time enable the programming of the data word and of the corresponding ECC word of the received RAM word during the writing access. 2. The SRAM memory device of claim 1 , wherein each row of memory cells is subdivided in a first group of memory cells adapted to store a corresponding data word, a second group of memory cells adapted to store a corresponding ECC word and a third group of memory cells adapted to store a corresponding applicative word, the means for selectively configuring the configurable port includes means for: enabling the programming of the memory cells belonging to the third group and at the same time disabling the programming of the memory cells belonging to the first and second groups, and enabling the programming of the memory cells belonging to the first and second groups and at the same time disabling the programming of the memory cells belonging to the third group.