1. A speech recognition circuit comprising: input means for receiving processed speech parameters; a plurality of lexical memory means containing in combination complete lexical data for word recognition, each lexical memory means containing part of said complete lexical data; a plurality of processors connected in parallel to said input means for processing the speech parameters in parallel, said processors being arranged in groups of processors, each group of processors being connected to a lexical memory means; control processor means for controlling each processor to process said speech parameters using partial lexical data read from a said lexical memory means; and receiving means for receiving the results of the processing of the speech parameters from said processors.
1. A speech recognition circuit comprising: input means for receiving processed speech parameters; a plurality of lexical memory means containing in combination complete lexical data for word recognition, each lexical memory means containing part of said complete lexical data; a plurality of processors connected in parallel to said input means for processing the speech parameters in parallel, said processors being arranged in groups of processors, each group of processors being connected to a lexical memory means; control processor means for controlling each processor to process said speech parameters using partial lexical data read from a said lexical memory means; and receiving means for receiving the results of the processing of the speech parameters from said processors. 2. A speech recognition circuit according to claim 1 , wherein each lexical memory means stores lexical data as at least one lexical tree data structure, each lexical tree data structure comprises a model of words having common prefix components, and an initial component of each lexical tree data structure is unique.