1. A digital phase locked loop, comprising: a first terminal configured to receive a first frequency word and a second terminal configured to receive a second frequency word; a value-discretely tunable oscillator configured to generate and output a signal having a frequency; an integrator comprising an input coupled to the first and the second terminals, and comprising an output coupled to a loop filter that is configured to provide a digital multi-bit setting word to a set input of the value-discretely tunable oscillator; a feedback path comprising a counting device, the counting device configured to output a word derived from the signal of the value-discretely tunable oscillator and a reference signal, wherein an output of the counting device and the first frequency word combine at a combining element to form a third frequency word; and a correction circuit comprising an input coupled to an input of the integrator, and an output coupled to an output of the integrator, wherein the correction circuit is configured to generate a correction word derived from the third frequency word fed to the input of the integrator and a word derived from the second frequency word.
1. A digital phase locked loop, comprising: a first terminal configured to receive a first frequency word and a second terminal configured to receive a second frequency word; a value-discretely tunable oscillator configured to generate and output a signal having a frequency; an integrator comprising an input coupled to the first and the second terminals, and comprising an output coupled to a loop filter that is configured to provide a digital multi-bit setting word to a set input of the value-discretely tunable oscillator; a feedback path comprising a counting device, the counting device configured to output a word derived from the signal of the value-discretely tunable oscillator and a reference signal, wherein an output of the counting device and the first frequency word combine at a combining element to form a third frequency word; and a correction circuit comprising an input coupled to an input of the integrator, and an output coupled to an output of the integrator, wherein the correction circuit is configured to generate a correction word derived from the third frequency word fed to the input of the integrator and a word derived from the second frequency word. 13. The phase locked loop of claim 1 , wherein the counting device is configured to determine and output the number of clock periods of the signal output by the value-discretely tunable oscillator with respect to a clock period of the reference signal.