1. A computer-implemented method for verification analysis comprising: obtaining a word-level data flow graph and obtaining a bit-level data flow graph; searching the bit-level data flow graph to find partial-product encoding; removing redundancy from the bit-level data flow graph; checking the word-level data flow graph and the bit-level data flow graph for input correspondence; and performing, one or more processors, equivalence checking using the bit-level data flow graph and the word-level data flow graph.
1. A computer-implemented method for verification analysis comprising: obtaining a word-level data flow graph and obtaining a bit-level data flow graph; searching the bit-level data flow graph to find partial-product encoding; removing redundancy from the bit-level data flow graph; checking the word-level data flow graph and the bit-level data flow graph for input correspondence; and performing, one or more processors, equivalence checking using the bit-level data flow graph and the word-level data flow graph. 20. The method of claim 1 wherein the removing redundancy includes merging duplicate nodes.