1. A sequential logic integrated circuit for PCM compression, comprising: a first shift register temporarily storing uncompressed PCM words upon receipt of a first load signal and serially emitting said uncompressed PCM words on a first wire, said first shift register also emitting on a first bus, bits of a number of positions following the position of a bit emitted on said first wire; a second shift register temporarily storing compressed PCM words upon receipt of a second load signal and emitting the compressed PCM words to an output; a counter connected to said first shift register by said first wire counting the number of logic 0's present in the most significant positions of the absolute values of the uncompressed PCM words received from said first shift register on said first wire up to a maximum value and emitting a carry signal, said counter emitting on a second bus a count of said number; a first enabling circuit supplying said counter with a signal enabling the counting of the bits of the absolute value of said uncompressed PCM words; and a second enabling circuit connected to said second shift register for supplying said second load signal to said second shift register when on said first wire the most significant logic "1" of the absolute value of said uncompressed PCM words is present, or when said counter emits said carry signal, said second load signal being emitted for a single-bit duration per each uncompressed PCM word, and determining loading in said second shift register of a sign bit of the compressed PCM word and of the bits present respectively on said second and first buses, forming in said second register said compressed PCM word.
1. A sequential logic integrated circuit for PCM compression, comprising: a first shift register temporarily storing uncompressed PCM words upon receipt of a first load signal and serially emitting said uncompressed PCM words on a first wire, said first shift register also emitting on a first bus, bits of a number of positions following the position of a bit emitted on said first wire; a second shift register temporarily storing compressed PCM words upon receipt of a second load signal and emitting the compressed PCM words to an output; a counter connected to said first shift register by said first wire counting the number of logic 0's present in the most significant positions of the absolute values of the uncompressed PCM words received from said first shift register on said first wire up to a maximum value and emitting a carry signal, said counter emitting on a second bus a count of said number; a first enabling circuit supplying said counter with a signal enabling the counting of the bits of the absolute value of said uncompressed PCM words; and a second enabling circuit connected to said second shift register for supplying said second load signal to said second shift register when on said first wire the most significant logic "1" of the absolute value of said uncompressed PCM words is present, or when said counter emits said carry signal, said second load signal being emitted for a single-bit duration per each uncompressed PCM word, and determining loading in said second shift register of a sign bit of the compressed PCM word and of the bits present respectively on said second and first buses, forming in said second register said compressed PCM word. 4. The circuit defined in claim 1, wherein at the input of said second register a logic circuit is connected which receives at the input said compressed PCM words and, prior to supplying them to said second register, complements the logic level of the bits of predetermined positions in said words.