6. A memory management unit as recited in claim 5, wherein said translation means includes: a translation look-aside buffer for receiving said virtual page number signal, comparing said virtual page number signal to a page number table of said translation look-aside buffer and if said virtual page number signal corresponds to a page number entry in said page number table, then issuing said physical page number signal and said domain number signal and said permission signal, but if said virtual page number component does not correspond to a page number entry in said page number table, then issuing a no-match signal; and translation table look-up logic for receiving said no-match signal and said virtual page number signal and transmitting a page number entry to said translation look-aside buffer if an entry stored in said memory corresponds to said virtual page number signal, but issuing said translation fault signal if no entry stored in said memory corresponds to said virtual page number signal.
6. A memory management unit as recited in claim 5, wherein said translation means includes: a translation look-aside buffer for receiving said virtual page number signal, comparing said virtual page number signal to a page number table of said translation look-aside buffer and if said virtual page number signal corresponds to a page number entry in said page number table, then issuing said physical page number signal and said domain number signal and said permission signal, but if said virtual page number component does not correspond to a page number entry in said page number table, then issuing a no-match signal; and translation table look-up logic for receiving said no-match signal and said virtual page number signal and transmitting a page number entry to said translation look-aside buffer if an entry stored in said memory corresponds to said virtual page number signal, but issuing said translation fault signal if no entry stored in said memory corresponds to said virtual page number signal. 7. A memory management unit as recited in claim 6, wherein said environment controller includes: a control register coupled to receive a data signal issued by said CPU and issuing a plurality of bits derived from said data signal; and a selector coupled to the control register and coupled to receive said domain number signal from said translator, wherein the selector selects a bit issued by said control register which corresponds to said domain number and issues said second fault indication so as to prevent initiation of performance of said operation if said bit selected by said selector indicates that said CPU is not allowed access to a domain corresponding to said domain number.