19. A device formed by the process comprising: generating a hardware description language (HDL) implementation of a first circuit design; receiving an HDL or netlist implementation of a public portion of a second circuit design, the second circuit design also including a secret portion not included with the public portion; receiving an HDL or netlist implementation of an interface between the public portion and the secret portion, the interface including one or more boundary locations between the secret portion and the public portion; generating an HDL implementation of an integrated design formed by integrating the HDL implementation of the first circuit design with the public portion of the second design and the interface; receiving an exclusion list of resources to be reserved for a secret portion of the second circuit design; generating a programming file for the integrated design including programming bits for configuring the integrated design into the device; programming the programming bits in the programming file for the integrated design into the device; receiving programming bits for the secret portion of the second circuit design; and programming the programming bits for the secret portion of the second circuit design into the device after the programming bits for the integrated circuit design have been programmed into the device.
19. A device formed by the process comprising: generating a hardware description language (HDL) implementation of a first circuit design; receiving an HDL or netlist implementation of a public portion of a second circuit design, the second circuit design also including a secret portion not included with the public portion; receiving an HDL or netlist implementation of an interface between the public portion and the secret portion, the interface including one or more boundary locations between the secret portion and the public portion; generating an HDL implementation of an integrated design formed by integrating the HDL implementation of the first circuit design with the public portion of the second design and the interface; receiving an exclusion list of resources to be reserved for a secret portion of the second circuit design; generating a programming file for the integrated design including programming bits for configuring the integrated design into the device; programming the programming bits in the programming file for the integrated design into the device; receiving programming bits for the secret portion of the second circuit design; and programming the programming bits for the secret portion of the second circuit design into the device after the programming bits for the integrated circuit design have been programmed into the device. 21. The device of claim 19 , wherein the interface includes one or more boundary lookup tables (LUTs) for mapping signals from the secret portion to the public portion and from the public portion to the secret portion.