13. The semiconductor memory cell MWA encoding apparatus of claim 12 , further comprising: a second binary weight encoder to transform the m-bit DATA_I to a second (2^m)−1 bit trial code word component DELTA_C_TRIAL_2, the DELTA_C_TRIAL_2 having a single bit set at a bit position corresponding to an integer value of the DATA_I.
13. The semiconductor memory cell MWA encoding apparatus of claim 12 , further comprising: a second binary weight encoder to transform the m-bit DATA_I to a second (2^m)−1 bit trial code word component DELTA_C_TRIAL_2, the DELTA_C_TRIAL_2 having a single bit set at a bit position corresponding to an integer value of the DATA_I. 14. The semiconductor memory cell MWA encoding apparatus of claim 13 , further comprising: OR logic coupled to the first and second binary weight encoders to perform a bitwise OR operation on the DELTA_C_TRIAL_1 and the DELTA_C_TRIAL_2 in order to combine the DELTA_C_TRIAL_1 and the DELTA_C_TRIAL_2 to form the DELTA_C_TRIAL.