20. An apparatus implemented in hardware, comprising: a semantic structure identifier unit to identify semantic structures in a system design; and a semantic structure signal activity unit to derive signal activities for signals output from semantic structures or input to semantic structures that describes toggle rates of the semantic structures according to a characteristic of the semantic structure; and a system design manager to coordinate optimizing power for the design of the system according to the signal activity of the semantic structure by modifying one of synthesis, placement, and routing of the system on the target device.
20. An apparatus implemented in hardware, comprising: a semantic structure identifier unit to identify semantic structures in a system design; and a semantic structure signal activity unit to derive signal activities for signals output from semantic structures or input to semantic structures that describes toggle rates of the semantic structures according to a characteristic of the semantic structure; and a system design manager to coordinate optimizing power for the design of the system according to the signal activity of the semantic structure by modifying one of synthesis, placement, and routing of the system on the target device. 22. The apparatus of claim 20 , wherein the semantic structure identifier unit identifies asynchronous reset pins.