13. The system of claim 7, wherein a second of said plurality of translator means comprises: first detector means, for generating latch command signals indicative of the occurrence of relatively long duration supervisory signals having durations longer than a predetermined period; latch means, responsive to said latch command signals, for responsively storing indicia of at least a portion of said first code word corresponding to said long duration supervisory signals for application to said memory means as said second code word; and means, responsive to relatively short duration supervisory signals, for responsively generating a strobe control signal to said means for selectively transmitting, to effect transmission of the symbol code indicia from the instantaneously addressed location in said memory means.
13. The system of claim 7, wherein a second of said plurality of translator means comprises: first detector means, for generating latch command signals indicative of the occurrence of relatively long duration supervisory signals having durations longer than a predetermined period; latch means, responsive to said latch command signals, for responsively storing indicia of at least a portion of said first code word corresponding to said long duration supervisory signals for application to said memory means as said second code word; and means, responsive to relatively short duration supervisory signals, for responsively generating a strobe control signal to said means for selectively transmitting, to effect transmission of the symbol code indicia from the instantaneously addressed location in said memory means. 14. The system of claim 13, wherein said latch means includes means responsive to a predetermined particular supervisory signal, for selectively resetting said latch means stored indicia to a predetermined count.