1. Apparatus for processing data comprising: translation buffer circuitry to store translation data to translate an input address of a memory access transaction to an output address; and translation control circuitry to provide said translation data to said translation buffer circuitry, wherein said translation buffer circuitry is responsive to receipt of a memory access transaction for which translation data is unavailable in said translation buffer circuitry to issue a request to said translation control circuitry to provide translation data for said memory access transaction; said translation control circuitry is responsive to a change in enablement of address translation for a given type of memory access transaction to issue an invalidate command to said translation buffer circuitry to invalidate any translation data for said given type of memory access transaction stored in said translation buffer circuitry; and said translation control circuitry is responsive to receipt of a request for translation data from said translation buffer circuitry for a memory access of said given type for which memory address translation is disabled to return global translation data to be used by said translation buffer circuitry for all memory access transactions of said given type.
1. Apparatus for processing data comprising: translation buffer circuitry to store translation data to translate an input address of a memory access transaction to an output address; and translation control circuitry to provide said translation data to said translation buffer circuitry, wherein said translation buffer circuitry is responsive to receipt of a memory access transaction for which translation data is unavailable in said translation buffer circuitry to issue a request to said translation control circuitry to provide translation data for said memory access transaction; said translation control circuitry is responsive to a change in enablement of address translation for a given type of memory access transaction to issue an invalidate command to said translation buffer circuitry to invalidate any translation data for said given type of memory access transaction stored in said translation buffer circuitry; and said translation control circuitry is responsive to receipt of a request for translation data from said translation buffer circuitry for a memory access of said given type for which memory address translation is disabled to return global translation data to be used by said translation buffer circuitry for all memory access transactions of said given type. 14. Apparatus as claimed in claim 1 , comprising a main interconnect and wherein said memory access transaction including said output address is communicated via said main interconnect.