9. The system of claim 8 in which during execution of said assembly language code in the data parallel computer elements of the arrays are evenly distributed to the processing elements, wherein the code generator comprises: (a) means for selecting one of the code blocks; (b) means for generating subgrid loop creation instructions to create a subgrid loop, wherein said subgrid loop creation instructions when executed in said processing element enable said processing element to process, over a predetermined number of iterations of said subgrid loop, the elements of the arrays distributed to said processing element, wherein X represents a value of an iteration counter; and (c) means for providing said subgrid loop creation instruction in said assembly language code.
9. The system of claim 8 in which during execution of said assembly language code in the data parallel computer elements of the arrays are evenly distributed to the processing elements, wherein the code generator comprises: (a) means for selecting one of the code blocks; (b) means for generating subgrid loop creation instructions to create a subgrid loop, wherein said subgrid loop creation instructions when executed in said processing element enable said processing element to process, over a predetermined number of iterations of said subgrid loop, the elements of the arrays distributed to said processing element, wherein X represents a value of an iteration counter; and (c) means for providing said subgrid loop creation instruction in said assembly language code. 10. The system of claim 9 in which said selected code block comprises a plurality of elemental vector instructions designating particular operations to perform using elements of a plurality of arrays, wherein said means for generating subgrid loop creation instructions comprises: means for determining an array size of arrays which are processed by said processing element during execution in said processing element of low-level vector instructions corresponding to said elemental vector instructions in said selected code block; means for calculating said value, X, of said iteration counter as a function of said array size and as a function of predetermined indicia indicating the number of array elements processed by said processing element during each iteration of said subgrid loop; and means for generating said subgrid loop creation instructions such that said processing element processes the elements of the arrays distributed to said processing element over X iterations of said subgrid loop.