1. A system for regulating voltage to a plurality of circuit elements in a datapath to maximize power efficiency in a desynchronized circuit, the system, comprising: a first controller circuit, the first controller circuit comprising at least a first pulsed latch enable signal, a request signal output and an acknowledge signal input; a second controller circuit, the second controller circuit comprising at least second pulsed latch enable signal, a request signal input and an acknowledge signal output; a request event conductor to transmit the request signal output of the first controller circuit to the request signal input of the second controller circuit; an acknowledge event conductor to transmit the acknowledge signal output of the second controller circuit to the acknowledge signal input of the first controller circuit; a detector component, comprising a filter circuit, to detect a speed mismatch over a selectable period of time to determine a time separation between a first time of arrival of a request event signal assertion on the request signal output and a second time of arrival of an acknowledge event signal assertion on the acknowledge signal output, wherein the selectable period of time is based at least in part on a selectable number of samples; and a compensator circuit to adjust a supply voltage to the plurality of circuit elements in the data path based on the detected time separation.
1. A system for regulating voltage to a plurality of circuit elements in a datapath to maximize power efficiency in a desynchronized circuit, the system, comprising: a first controller circuit, the first controller circuit comprising at least a first pulsed latch enable signal, a request signal output and an acknowledge signal input; a second controller circuit, the second controller circuit comprising at least second pulsed latch enable signal, a request signal input and an acknowledge signal output; a request event conductor to transmit the request signal output of the first controller circuit to the request signal input of the second controller circuit; an acknowledge event conductor to transmit the acknowledge signal output of the second controller circuit to the acknowledge signal input of the first controller circuit; a detector component, comprising a filter circuit, to detect a speed mismatch over a selectable period of time to determine a time separation between a first time of arrival of a request event signal assertion on the request signal output and a second time of arrival of an acknowledge event signal assertion on the acknowledge signal output, wherein the selectable period of time is based at least in part on a selectable number of samples; and a compensator circuit to adjust a supply voltage to the plurality of circuit elements in the data path based on the detected time separation. 2. The system as set forth in claim 1 , wherein the compensator circuit is operable for being initialized using at least one of, a hardware initialization, a software initialization, or an external initialization.