31. A circuit for sensing the presence of a frequency component F.sub.0 in an input signal comprising: a clock providing clock signals at a rate of N times the frequency F.sub.0 to be sensed, where N is any integer greater than one; means, coupled to said clock, for sampling said input signal and providing an amplitude sample of said input signal for each clock signal; an adder having a first input for receiving said amplitude samples, a second input and an output; feedback means coupling the output of said adder to its seconds input, said feedback means consisting of: (a) delay means for providing a delay of one-half the time period T.sub.0 of said frequency F.sub.0 ; (b) a multiplier for multiplying signal magnitudes by a multiplier constant that it less than one and greater than zero; and (c) means coupling said delay means and said multiplier in series; and means coupled to said frequency sensing circuit for deriving an output signal therefrom having a magnitude indicative of the frequency sensed.
31. A circuit for sensing the presence of a frequency component F.sub.0 in an input signal comprising: a clock providing clock signals at a rate of N times the frequency F.sub.0 to be sensed, where N is any integer greater than one; means, coupled to said clock, for sampling said input signal and providing an amplitude sample of said input signal for each clock signal; an adder having a first input for receiving said amplitude samples, a second input and an output; feedback means coupling the output of said adder to its seconds input, said feedback means consisting of: (a) delay means for providing a delay of one-half the time period T.sub.0 of said frequency F.sub.0 ; (b) a multiplier for multiplying signal magnitudes by a multiplier constant that it less than one and greater than zero; and (c) means coupling said delay means and said multiplier in series; and means coupled to said frequency sensing circuit for deriving an output signal therefrom having a magnitude indicative of the frequency sensed. 36. A circuit according to claim 31 wherein said feedback means provides signals to said second input of said adder that are in phase with signals applied to said first input of said adder.