10. The device of claim 1 , further comprising: demodulator circuitry configured to read the memory cells of the memory device; and decoder circuitry configured to decode the inner code words and the outer code words and to correct errors in the inner code words and the outer code words.
10. The device of claim 1 , further comprising: demodulator circuitry configured to read the memory cells of the memory device; and decoder circuitry configured to decode the inner code words and the outer code words and to correct errors in the inner code words and the outer code words. 11. The device of claim 10 , wherein the decoder circuitry is configured to iterate between correcting the outer code words and correcting the inner code words.