15. A modeling environment executing on a computer comprising: a memory storing a model space configured to receive an executable model having a plurality of blocks including a frame-enabled block, the frame-enabled block implementable in hardware in a plurality of ways, the plurality of ways in which the frame-enabled block is implementable in hardware include: a fully parallelized way that uses a plurality of first parallel hardware components, a fully serialized way that uses a first serial hardware component, and a combination serialized and parallelized way that uses a plurality of second parallel hardware components and a second serial hardware component; a user interface configured to receive one or more input parameters from a user, the one or more input parameters specifying at least one hardware implementation optimization goal for the frame-enabled block of the model, the one or more input parameters free from affecting execution of the frame-enabled block and to cause the frame-enabled block to be implemented in hardware in a particular way of the plurality of ways; and a code generator coupled to the model space and the user interface, the code generator configured to receive the one or more input parameters, and to generate hardware description language (HDL) code for the frame-enabled block of the model, the generated HDL code implementing the frame-enabled block in hardware in the particular way that meets the optimization goal, the particular way selected from the group consisting of: the fully parallelized way, in which the plurality of first parallel hardware components are included in the hardware implementation of the frame-enabled block, the fully serialized way, in which the first serial hardware component is included in the hardware implementation of the frame-enabled block, and the combination serialized and parallelized way, in which the second serial hardware component and the plurality of second parallel hardware components are included in the hardware implementation of the frame-enabled block.
15. A modeling environment executing on a computer comprising: a memory storing a model space configured to receive an executable model having a plurality of blocks including a frame-enabled block, the frame-enabled block implementable in hardware in a plurality of ways, the plurality of ways in which the frame-enabled block is implementable in hardware include: a fully parallelized way that uses a plurality of first parallel hardware components, a fully serialized way that uses a first serial hardware component, and a combination serialized and parallelized way that uses a plurality of second parallel hardware components and a second serial hardware component; a user interface configured to receive one or more input parameters from a user, the one or more input parameters specifying at least one hardware implementation optimization goal for the frame-enabled block of the model, the one or more input parameters free from affecting execution of the frame-enabled block and to cause the frame-enabled block to be implemented in hardware in a particular way of the plurality of ways; and a code generator coupled to the model space and the user interface, the code generator configured to receive the one or more input parameters, and to generate hardware description language (HDL) code for the frame-enabled block of the model, the generated HDL code implementing the frame-enabled block in hardware in the particular way that meets the optimization goal, the particular way selected from the group consisting of: the fully parallelized way, in which the plurality of first parallel hardware components are included in the hardware implementation of the frame-enabled block, the fully serialized way, in which the first serial hardware component is included in the hardware implementation of the frame-enabled block, and the combination serialized and parallelized way, in which the second serial hardware component and the plurality of second parallel hardware components are included in the hardware implementation of the frame-enabled block. 16. The modeling environment of claim 15 wherein the one or more input parameters include reducing implementation area on a target device, reducing power consumption of the target device, improving latency, or increasing throughput.