25. An apparatus, comprising: a processor circuit on a device; a data store; a memory storing instructions operable on the processor circuit, the instructions, when executed, cause the processor circuit to: execute one or more task commands in a simulated environment; receive a task hierarchy from a data store, the task hierarchy comprising a plurality of task entries, each task entry comprising a list of task entries or a task command, the list of task entries comprising probabilities associated with each task entry in the list of task entries, wherein task commands are executed in the simulated environment to cause actual performance of events to cause usage of physical computing resources, and wherein each probability provides a weight for selection of an associated task entry when traversing the task hierarchy; determine the one or more task commands for execution by traversing through the task hierarchy based on the associated probabilities until the one or more task commands are reached; and execute the one or more task commands to cause actual performance of an event to cause usage of at least one of the physical computing resources in the simulated environment.
25. An apparatus, comprising: a processor circuit on a device; a data store; a memory storing instructions operable on the processor circuit, the instructions, when executed, cause the processor circuit to: execute one or more task commands in a simulated environment; receive a task hierarchy from a data store, the task hierarchy comprising a plurality of task entries, each task entry comprising a list of task entries or a task command, the list of task entries comprising probabilities associated with each task entry in the list of task entries, wherein task commands are executed in the simulated environment to cause actual performance of events to cause usage of physical computing resources, and wherein each probability provides a weight for selection of an associated task entry when traversing the task hierarchy; determine the one or more task commands for execution by traversing through the task hierarchy based on the associated probabilities until the one or more task commands are reached; and execute the one or more task commands to cause actual performance of an event to cause usage of at least one of the physical computing resources in the simulated environment. 33. The apparatus of claim 25 , the processor circuit to receive a desired level of activity and evaluate the task hierarchy iteratively to determine task commands to execute and executing the determined task commands, the task entries evaluated iteratively at a rate determined based on the desired level of activity.