7. A digital data processor comprising an instruction unit, said instruction unit comprising a code page that is partitioned for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, in a second section thereof an extension to said at least one instruction word, further comprising at least one page table entry bit having a state for indicating, on a code page by code page basis, whether the code page is partitioned into said first and second sections for storing instruction words and at least one instruction word extension, or whether the code page is comprised instead of a single section storing only instruction words, wherein each of the first and second section is comprised of contiguous storage locations.
7. A digital data processor comprising an instruction unit, said instruction unit comprising a code page that is partitioned for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, in a second section thereof an extension to said at least one instruction word, further comprising at least one page table entry bit having a state for indicating, on a code page by code page basis, whether the code page is partitioned into said first and second sections for storing instruction words and at least one instruction word extension, or whether the code page is comprised instead of a single section storing only instruction words, wherein each of the first and second section is comprised of contiguous storage locations. 11. A digital data processor as in claim 7 , further comprising circuitry, coupled to an output of said code page, to selectively combine, in response to the state of said at least one page table entry bit, an addressed instruction word read out of said code page with a corresponding instruction word extension that is also read out of said code page.