15. A decoding apparatus, comprising: a memory that retains instructions for receiving sequence data requiring sequence translation; front-loading an estimated future distortion penalty in translating a remainder of the sequence of data; creating a search space of possible next-phrase translations; reducing the search space based in part on the estimated future distortion penalty; and selecting a translation candidate for the sequence data; and a processor that is configured to execute the instructions within the memory.
15. A decoding apparatus, comprising: a memory that retains instructions for receiving sequence data requiring sequence translation; front-loading an estimated future distortion penalty in translating a remainder of the sequence of data; creating a search space of possible next-phrase translations; reducing the search space based in part on the estimated future distortion penalty; and selecting a translation candidate for the sequence data; and a processor that is configured to execute the instructions within the memory. 16. The decoding apparatus of claim 15 , the memory further retains instruction for statistical machine translation.