27. The apparatus of claim 23 in which said control means writes said page refresh RAM with a different multi-bit sequence for each different formatted multi-character array to be displayed.
27. The apparatus of claim 23 in which said control means writes said page refresh RAM with a different multi-bit sequence for each different formatted multi-character array to be displayed. 28. The apparatus of claim 27 in which said character array is two by two, and four bits of said multi-bit sequence identify one of sixteen different multi-character arrays.