1. A processor-executed method of testing comprising: mapping Testing and Test Control Notation Version 3 (TTCN-3) test language to a SystemVerilog test bench; storing the mapped TTCN-3 test language with a SystemVerilog syntax compiler; and running the SystemVerilog test bench, with the mapped TTCN-3 test language.
1. A processor-executed method of testing comprising: mapping Testing and Test Control Notation Version 3 (TTCN-3) test language to a SystemVerilog test bench; storing the mapped TTCN-3 test language with a SystemVerilog syntax compiler; and running the SystemVerilog test bench, with the mapped TTCN-3 test language. 2. The method of claim 1 , further comprising: generating a database including the mapping of the TTCN-3 test language, the database used by the SystemVerilog test bench to implement the mapped TTCN-3 test language.