9. A machine implemented data bit error management method comprising: selecting a set of parity bit positions for parity bits to protect a set of data bits, each data bit having a data bit position in said data bit set, said number of parity bits being at least four; associating each data bit position with a different syndrome, each syndrome comprising a sub-set of at least three parity bit positions, such that each said sub-set has at least one parity bit position shared with at least one other said sub-set and wherein said associating is such that a syndrome associated with a lower order data bit position equates to a word with a lower numerical value than does a syndrome associated with a next higher order data bit position; calculating a parity bit value for each parity bit position from all data bit positions associated with said each parity bit position; and transmitting said set of data bits and said set of parity bit.
9. A machine implemented data bit error management method comprising: selecting a set of parity bit positions for parity bits to protect a set of data bits, each data bit having a data bit position in said data bit set, said number of parity bits being at least four; associating each data bit position with a different syndrome, each syndrome comprising a sub-set of at least three parity bit positions, such that each said sub-set has at least one parity bit position shared with at least one other said sub-set and wherein said associating is such that a syndrome associated with a lower order data bit position equates to a word with a lower numerical value than does a syndrome associated with a next higher order data bit position; calculating a parity bit value for each parity bit position from all data bit positions associated with said each parity bit position; and transmitting said set of data bits and said set of parity bit. 14. The method of claim 9 further comprising choosing each said sub-set so as to maximize the number of sub-sets of equal size.