13. A method for verifying a hardware design for an electronic circuit, comprising: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of constraints with uninterpreted functions; property checking the abstraction model in relation to one or more design properties using a satisfiability modulo theories solver, where the satisfiability modulo theories solver outputs an assignment of variables that represent a violation of the design properties; replacing select variable assignments with relationships between variables to form a set of constraints that represent the violation; conjoining the set of constraints that represent the violation with the set of design constraints to form a conjoined set of constraints; and checking feasibility of the violation by inputting the conjoined set of constraints into a satisfiability modulo theories solver, wherein at least the steps of creating an abstraction model, property checking and checking feasibility are executed by a computer processor.
13. A method for verifying a hardware design for an electronic circuit, comprising: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of constraints with uninterpreted functions; property checking the abstraction model in relation to one or more design properties using a satisfiability modulo theories solver, where the satisfiability modulo theories solver outputs an assignment of variables that represent a violation of the design properties; replacing select variable assignments with relationships between variables to form a set of constraints that represent the violation; conjoining the set of constraints that represent the violation with the set of design constraints to form a conjoined set of constraints; and checking feasibility of the violation by inputting the conjoined set of constraints into a satisfiability modulo theories solver, wherein at least the steps of creating an abstraction model, property checking and checking feasibility are executed by a computer processor. 14. The method of claim 13 wherein creating an abstraction model further comprises abstracting one or more signals that are multi-bit while leaving signals that are single bit unabstracted.