11. A method of designing instruction extensions to supplement an existing processor instruction set architecture (ISA), the method comprising: receiving an instruction extension description for a new instruction from a user to supplement the existing processor ISA, the received instruction extension description excluding a description for the existing instruction set of the existing processor; and modifying, by a processor build software, a plurality of existing software tools to support the new instruction based on the received instruction extension description—, wherein the code for modifying includes code for modifying an existing assembler, wherein the existing assembler encoding and decoding is grouped in a separate software library which is generated automatically using information in the ISA description.
11. A method of designing instruction extensions to supplement an existing processor instruction set architecture (ISA), the method comprising: receiving an instruction extension description for a new instruction from a user to supplement the existing processor ISA, the received instruction extension description excluding a description for the existing instruction set of the existing processor; and modifying, by a processor build software, a plurality of existing software tools to support the new instruction based on the received instruction extension description—, wherein the code for modifying includes code for modifying an existing assembler, wherein the existing assembler encoding and decoding is grouped in a separate software library which is generated automatically using information in the ISA description. 14. The method of claim 11 , wherein the step of receiving an instruction extension description includes receiving a functional description that specifies the operation performed by the new instruction.