11. The circuit arrangement of claim 1 , wherein the allocation of the second check word depends on a succession of instruction words within the protected data record, which succession is to be processed by the arithmetic and logic unit.
11. The circuit arrangement of claim 1 , wherein the allocation of the second check word depends on a succession of instruction words within the protected data record, which succession is to be processed by the arithmetic and logic unit. 13. The circuit anangement of claim 11 , wherein the arithmetic and logic unit outputs more than one first check word, and the checking unit compares whether one of the plurality of first check words matches the second check word.