1. A computer implemented method for performing verification of a device design comprising: identifying a plurality of clock domain crossing boundaries within a device design; performing on a computer a formal clock domain crossing verification process on ones of the plurality of clock domain crossing boundaries, the formal clock domain crossing verification process generating a set of clock domain crossing boundaries to be promoted; and saving the set of clock domain crossing boundaries to a memory storage location.
1. A computer implemented method for performing verification of a device design comprising: identifying a plurality of clock domain crossing boundaries within a device design; performing on a computer a formal clock domain crossing verification process on ones of the plurality of clock domain crossing boundaries, the formal clock domain crossing verification process generating a set of clock domain crossing boundaries to be promoted; and saving the set of clock domain crossing boundaries to a memory storage location. 2. The computer implemented method recited in claim 1 , wherein the method act of identifying a plurality of clock domain crossing boundaries within the device design comprises: performing a structural analysis process on the device design, wherein the plurality of clock domain crossing boundaries are identified; and placing the identified clock domain crossing boundaries into a verification queue.