12. The data processing system for performing the fuzzy inference operation of claim 11 wherein the decoder decodes the second plurality of rule codes to generate a second plurality of decoded signals.
12. The data processing system for performing the fuzzy inference operation of claim 11 wherein the decoder decodes the second plurality of rule codes to generate a second plurality of decoded signals. 13. The data processing system for performing the fuzzy inference operation of claim 12 wherein the rule bits generating circuit further comprises: second logic means coupled to the decoder for receiving the second plurality of decoded signals, the second logic means logically combining the first plurality of decoded signals and the second plurality of decoded signals to generate a second plurality of rule signals.