1. A method of profiling a hardware system comprising: compiling a high level language program into an assembly language representation of a hardware system, wherein the high level language program is specified using a language other than a hardware description language; translating instructions of the assembly language representation of the hardware system into a plurality of cycle-accurate, software-emulation models; wherein each software-emulation model corresponds to a respective one of the assembly language instructions, and the models are communicatively linked by FIFOs to form a pipelined architecture; instrumenting at least one of the plurality of models with code that, when executed, provides operating state information relating to the model as output; wherein the operating state information includes read state data, the at least one model is in a read state while the at least one model is waiting for data from another model to appear on an input FIFO to the at least one model, and the read state data indicates a number of consecutive cycles of an emulation the at least one model is in the read state; and indicating expected behavior of the hardware system by executing the models in an emulation environment on a computer system.
1. A method of profiling a hardware system comprising: compiling a high level language program into an assembly language representation of a hardware system, wherein the high level language program is specified using a language other than a hardware description language; translating instructions of the assembly language representation of the hardware system into a plurality of cycle-accurate, software-emulation models; wherein each software-emulation model corresponds to a respective one of the assembly language instructions, and the models are communicatively linked by FIFOs to form a pipelined architecture; instrumenting at least one of the plurality of models with code that, when executed, provides operating state information relating to the model as output; wherein the operating state information includes read state data, the at least one model is in a read state while the at least one model is waiting for data from another model to appear on an input FIFO to the at least one model, and the read state data indicates a number of consecutive cycles of an emulation the at least one model is in the read state; and indicating expected behavior of the hardware system by executing the models in an emulation environment on a computer system. 3. The method of claim 1 , wherein compiling the high level language program further comprises: identifying constructs of the high level language program; and mapping the constructs to instructions and pseudo-instructions of the assembly language.