1. A method of generating clock gating circuitry for a circuit design model, comprising: using one or more programmed processors to perform steps including: for each one of a plurality of interconnected gate elements in a netlist of the circuit design model, the plurality of gate elements arranged in a number of levels beginning with a first gate element in a first level, the first gate element being a flop gate element, and each subsequent level including one or more second gate elements receiving an input signal directly or transitively from a third gate element included in a previous level, determining a respective Boolean expression of observability conditions for the third gate element by performing steps including: determining a Boolean expression of path sensitization of the second gate element from an input to an output of the second gate element; determining a Boolean expression of path sensitization from the third gate element to the second gate element; for the third gate element, determining a conjunction of the Boolean expression of the path sensitization of the second gate element, the Boolean expression of path sensitization from the third gate element to the second gate element, and a Boolean expression of a disjunction of the respective Boolean expressions of observability conditions of the second gate elements in a subsequent level that receive input from the third gate element to produce an intermediate Boolean expression; for the second gate element being in the last level, assigning a logic one as the Boolean expression of observability conditions of the second gate element; and performing backward retiming of the intermediate Boolean expression to produce the respective Boolean expression of the observability conditions of the first gate element; and generating clock gating circuits that implement the respective Boolean expression of the observability conditions of one or more of the plurality of interconnected gate elements, and incorporating the clock gating circuits into the circuit design model.
1. A method of generating clock gating circuitry for a circuit design model, comprising: using one or more programmed processors to perform steps including: for each one of a plurality of interconnected gate elements in a netlist of the circuit design model, the plurality of gate elements arranged in a number of levels beginning with a first gate element in a first level, the first gate element being a flop gate element, and each subsequent level including one or more second gate elements receiving an input signal directly or transitively from a third gate element included in a previous level, determining a respective Boolean expression of observability conditions for the third gate element by performing steps including: determining a Boolean expression of path sensitization of the second gate element from an input to an output of the second gate element; determining a Boolean expression of path sensitization from the third gate element to the second gate element; for the third gate element, determining a conjunction of the Boolean expression of the path sensitization of the second gate element, the Boolean expression of path sensitization from the third gate element to the second gate element, and a Boolean expression of a disjunction of the respective Boolean expressions of observability conditions of the second gate elements in a subsequent level that receive input from the third gate element to produce an intermediate Boolean expression; for the second gate element being in the last level, assigning a logic one as the Boolean expression of observability conditions of the second gate element; and performing backward retiming of the intermediate Boolean expression to produce the respective Boolean expression of the observability conditions of the first gate element; and generating clock gating circuits that implement the respective Boolean expression of the observability conditions of one or more of the plurality of interconnected gate elements, and incorporating the clock gating circuits into the circuit design model. 3. The method of claim 1 , wherein the steps included in determining the Boolean expression of the observability conditions for the plurality of interconnected gate elements are performed topologically.