17. A frequency sensing circuit according to either of claims 14 or 15 wherein said delay means comprises a digital circuit clocked by said means for clocking.
17. A frequency sensing circuit according to either of claims 14 or 15 wherein said delay means comprises a digital circuit clocked by said means for clocking. 25. A frequency sensing circuit according to claim 17 wherein N is at least four, and wherein said integral number of periods of delay 1/2F.sub.0 provided by said delay means is two.