4. A translator as claimed in claim 1 wherein certain ones of the characters in said first code do not have a corresponding character in said second code, said translator including means for identifying said certain ones of said characters; and, said translate control means including a means responsive to said identifying means for requesting that a new input data character be supplied and means for emitting a signal that the translator has a character ready for output, said last named means being inhibited by a signal from said identifying means.
4. A translator as claimed in claim 1 wherein certain ones of the characters in said first code do not have a corresponding character in said second code, said translator including means for identifying said certain ones of said characters; and, said translate control means including a means responsive to said identifying means for requesting that a new input data character be supplied and means for emitting a signal that the translator has a character ready for output, said last named means being inhibited by a signal from said identifying means. 5. A translator as claimed in claim 4 wherein each address in said memory means that is addressable by an input data character in said first code has stored therein two identification bits, said identification bits having a special configuration if there is no character in said second code corresponding to the addressing character, said identification bits being applied to said identifying means when said memory is addressed.