4. A digital data processor as in claim 1 , further comprising circuitry, coupled to an output of said code page, to combine an addressed instruction word read out of said code page with a corresponding instruction word extension that is also read out of said code page.
4. A digital data processor as in claim 1 , further comprising circuitry, coupled to an output of said code page, to combine an addressed instruction word read out of said code page with a corresponding instruction word extension that is also read out of said code page. 5. A digital data processor as in claim 4 , where said combining circuitry comprises an input stage of an instruction pipeline.