4. The combination in accordance with claim 3 wherein said preamble constituting a series of identical bits followed by alternating bits and said control code detector is enabled responsive to the detection of the required series of identical bits and produces an output indicative of the detection of a control code upon the detection of the required number of alternate bits.
4. The combination in accordance with claim 3 wherein said preamble constituting a series of identical bits followed by alternating bits and said control code detector is enabled responsive to the detection of the required series of identical bits and produces an output indicative of the detection of a control code upon the detection of the required number of alternate bits. 5. The combination in accordance with claim 4 wherein said control word detector comprises a counter and logic means responsive to a series of identical bits to produce an output pulse and said last means connected to reset said counter, said counter responsive to alternating bits and having a number of stages equal to the number of alternating bits in said preamble, the output of said counter connected to introduce a pulse into the stream of data.