9. Within a computer-based Electronic Design Automation (EDA) tool executing within a computer, a method of macro inference comprising: selecting a plurality of templates written in a hardware description language (HDL); converting the plurality of HDL templates into a plurality of macro templates using an elaboration process of the EDA tool; storing the plurality of macro templates in a macro template library, wherein each of the plurality of macro templates is associated with a macro; converting a circuit design into a format that conforms to an internal data structure utilized by the EDA tool using the elaboration process of the EDA tool; identifying a portion of the converted circuit design that matches a selected macro template from the plurality of macro templates using the EDA tool; generating, using the EDA tool, an updated circuit design by replacing the portion of the converted circuit design that matches the selected macro template with a macro associated with the selected macro template; and outputting the updated circuit design.
9. Within a computer-based Electronic Design Automation (EDA) tool executing within a computer, a method of macro inference comprising: selecting a plurality of templates written in a hardware description language (HDL); converting the plurality of HDL templates into a plurality of macro templates using an elaboration process of the EDA tool; storing the plurality of macro templates in a macro template library, wherein each of the plurality of macro templates is associated with a macro; converting a circuit design into a format that conforms to an internal data structure utilized by the EDA tool using the elaboration process of the EDA tool; identifying a portion of the converted circuit design that matches a selected macro template from the plurality of macro templates using the EDA tool; generating, using the EDA tool, an updated circuit design by replacing the portion of the converted circuit design that matches the selected macro template with a macro associated with the selected macro template; and outputting the updated circuit design. 10. The method of claim 9 , wherein converting the plurality of HDL templates comprises: parsing each of the plurality of HDL templates; and processing each of the plurality of HDL templates through a register-transfer-level elaboration process.