13. An interface according to claim 10 wherein the scratchpad memory temporarily stores the digital signals corresponding to the digital outputs from the instrument, the digital signals in the scratchpad memory being directed toward the host computer in response to a corresponding instruction by the host computer to the microprocessor means.
13. An interface according to claim 10 wherein the scratchpad memory temporarily stores the digital signals corresponding to the digital outputs from the instrument, the digital signals in the scratchpad memory being directed toward the host computer in response to a corresponding instruction by the host computer to the microprocessor means. 18. An interface according to claim 13 wherein digital signals entering the scratchpad memory either (a) wraparound or (b) do not wraparound once the scratchpad memory is filled, the wraparound mode being established by the executive means in response to one corresponding instruction from the host computer and the not wraparound mode being established by the executive means in response to a differing corresponding instruction from the host computer.