46. A speech recognition circuit comprising: an input buffer receiving processed speech parameters; a plurality of lexical memories containing in combination complete lexical data for word recognition, each lexical memory containing part of said complete lexical data; a plurality of processors connected in parallel to said input buffer for processing the speech parameters in parallel, said processors being arranged in groups of processors, each group of processors being connected to a lexical memory; a control processor controlling each processor to process said speech parameters using partial lexical data read from a respective said lexical memory; and a results memory storing the results of the processing of the speech parameters from said processors.
46. A speech recognition circuit comprising: an input buffer receiving processed speech parameters; a plurality of lexical memories containing in combination complete lexical data for word recognition, each lexical memory containing part of said complete lexical data; a plurality of processors connected in parallel to said input buffer for processing the speech parameters in parallel, said processors being arranged in groups of processors, each group of processors being connected to a lexical memory; a control processor controlling each processor to process said speech parameters using partial lexical data read from a respective said lexical memory; and a results memory storing the results of the processing of the speech parameters from said processors. 58. A speech recognition circuit according to claim 46 , wherein said processors determine and output scores in the processing results during the processing of said speech parameters.