13. The system of claim 11 , wherein the comparison circuit comprises a bit-wise AND gate having a first bus input, a second bus input, and a bus output, the bit-wise AND gate being configured to set to a value of binary 1 each bit of the bus output for which the corresponding bit at the first bus input has a value of binary 1 and the corresponding bit at the second bus input has a value of binary 1, and to set the remaining bits of the bus output to a value of binary 0.
13. The system of claim 11 , wherein the comparison circuit comprises a bit-wise AND gate having a first bus input, a second bus input, and a bus output, the bit-wise AND gate being configured to set to a value of binary 1 each bit of the bus output for which the corresponding bit at the first bus input has a value of binary 1 and the corresponding bit at the second bus input has a value of binary 1, and to set the remaining bits of the bus output to a value of binary 0. 16. The system of claim 13 , wherein the short binary representation has a length of n bits, and m=2 n .