18. The semiconductor memory cell MWA encoding apparatus of claim 17 , the validity test logic further comprising: a memory cell reset avoidance (MCRA) decoder coupled to the OR logic to receive the NEW_C_TRIAL and to decode the NEW_C_TRIAL to generate a trial new data word (NEW_D_TRIAL).
18. The semiconductor memory cell MWA encoding apparatus of claim 17 , the validity test logic further comprising: a memory cell reset avoidance (MCRA) decoder coupled to the OR logic to receive the NEW_C_TRIAL and to decode the NEW_C_TRIAL to generate a trial new data word (NEW_D_TRIAL). 19. The semiconductor memory cell MWA encoding apparatus of claim 18 , the validity test logic further comprising: second DELTA_C validity test logic coupled to the MCRA decoder to receive the NEW_D_TRIAL and the NEW_D, to perform a bitwise compare operation on the NEW_D_TRIAL and the NEW_D, and to request a different DELTA_C_TRIAL from the pattern generator if the NEW_D_TRIAL is not equal to the NEW_D.