7. The method of claim 4 wherein receiving pipelined output data comprises: receiving a first set of output data from the called HDL module during a first clock cycle; and receiving a second set of output data from the called HDL module during a second clock cycle.
7. The method of claim 4 wherein receiving pipelined output data comprises: receiving a first set of output data from the called HDL module during a first clock cycle; and receiving a second set of output data from the called HDL module during a second clock cycle. 8. The method of claim 7 wherein formatting the receiving pipelined output data comprises: storing the first set of output data and the second set of output data into one or more arrays.