13. A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware unit for controlling said digital circuit as a unit, said method comprising: a first step of creating a functional model functionally expressing a plurality of said divided digital circuits by a hardware description language; a second step of verifying the logic of said functional models by hardware description language simulation means and simultaneously executing substitution of said functional models to corresponding structural models without waiting for the verification of said logic, until creation of said functional models are completed; and a third step of independently executing automatic generation of layout for arranging said structural models in a physical space in said digital circuit, for example, on a printed board or on an integrated circuit by an automatic placing and routing tool on the basis of the dimensions of components expressed by said structural model and the amount of wiring, and verification of the logic of said hardware units.
13. A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware unit for controlling said digital circuit as a unit, said method comprising: a first step of creating a functional model functionally expressing a plurality of said divided digital circuits by a hardware description language; a second step of verifying the logic of said functional models by hardware description language simulation means and simultaneously executing substitution of said functional models to corresponding structural models without waiting for the verification of said logic, until creation of said functional models are completed; and a third step of independently executing automatic generation of layout for arranging said structural models in a physical space in said digital circuit, for example, on a printed board or on an integrated circuit by an automatic placing and routing tool on the basis of the dimensions of components expressed by said structural model and the amount of wiring, and verification of the logic of said hardware units. 14. A digital circuit design assist method according to claim 13, wherein said third step independently executes automatic generation of a test pattern for fault analysis of said structural models, analysis of any fault of said structural models and verification of the logic of said hardware units by an automatic test pattern tool and a fault analysis tool; on the basis of said digital circuit for which verification of said logic is under way or is completed, and wherein all of said functional models have already been converted to said structural models.