9. A compression device as claimed in claim 5, wherein there is provided a sequential logic element which has at least two states in order to activate the shift control (ISE) of said first and second shift register in a first state until a group of significant compression bits has been formed, to deactivate in reacation thereto said shift control in a second state, to activate said first output (IES) until said group of significant compression bits has been presented compltely on said first output, and to return in reaction thereto to said first state.
9. A compression device as claimed in claim 5, wherein there is provided a sequential logic element which has at least two states in order to activate the shift control (ISE) of said first and second shift register in a first state until a group of significant compression bits has been formed, to deactivate in reacation thereto said shift control in a second state, to activate said first output (IES) until said group of significant compression bits has been presented compltely on said first output, and to return in reaction thereto to said first state. 11. A compression device as claimed in claim 9, wherein said compression translator comprises programmable logic array means for receiving the information of at least two pixels (x, x-1) of the actual line, of at least two pixels in corresponding positions on the directly preceding line (y, y-1), and of at least three further adjacent pixels (BY-2, BY-3, BY-4) on the same directly preceding line, said programmable logic array means having first generating means for generating transistion-dependent pixel line status signals (LSTO:3), second generating means for receiving said pixel line status signals, and being coupled by a hold element for constituting an end around sequencer and generating horizontal code status signals, and code word rest length signals (C.0.DLO:3) which are generated by a counter to generate the group of compression code bits as output signals.