1. In a computer system comprising a formal specification of a logic circuit having at least one finite state machine (FSM) and at least one set of functional vectors for simulating the logic circuit, an apparatus for analyzing and verifying said at least one FSM's design and implementation, said apparatus comprising: a) synthesis means for generating a gate level specification of said logic circuit in response to said formal specification of said logic circuit; b) state table generation means comprising: b.1) command script generation means for generating at least one state table extraction command script file for said at least one FSM in response to said formal specification of said logic circuit: and b.2) state table extraction means for generating said at least one state table for said at least one FSM in response to said gate level specification of said logic circuit and said at least one state table extraction command script file; c) simulation means for simulating and generating simulation results of said at least one FSM in response to said gate level specification of said logic circuit, said at least one state table for said at least one FSM, and said at least one set of functional vectors; and d) reporting means for generating analysis reports in response to said simulation results of said at least one FSM and user inputs.
1. In a computer system comprising a formal specification of a logic circuit having at least one finite state machine (FSM) and at least one set of functional vectors for simulating the logic circuit, an apparatus for analyzing and verifying said at least one FSM's design and implementation, said apparatus comprising: a) synthesis means for generating a gate level specification of said logic circuit in response to said formal specification of said logic circuit; b) state table generation means comprising: b.1) command script generation means for generating at least one state table extraction command script file for said at least one FSM in response to said formal specification of said logic circuit: and b.2) state table extraction means for generating said at least one state table for said at least one FSM in response to said gate level specification of said logic circuit and said at least one state table extraction command script file; c) simulation means for simulating and generating simulation results of said at least one FSM in response to said gate level specification of said logic circuit, said at least one state table for said at least one FSM, and said at least one set of functional vectors; and d) reporting means for generating analysis reports in response to said simulation results of said at least one FSM and user inputs. 5. The apparatus as set forth in claim 1, wherein said reporting means comprises: d.1) a command interpreter for interpreting user commands; d.2) a loader cooperating with said command interpreter for loading said at least one state table and simulation results for said at least one FSM; d.3) a database for storing said loaded at least one state table and said simulation results; and d.4) a plurality of function routines cooperating with said command interpreter and said database for performing a plurality of reporting and related functions.