9. The system of claim 7 wherein the second memory comprises further instructions executable by the second processor to generate the first class of error identifiers using a set of stateless error parsers.
9. The system of claim 7 wherein the second memory comprises further instructions executable by the second processor to generate the first class of error identifiers using a set of stateless error parsers. 10. The system of claim 9 wherein the second memory comprises further instructions executable by the second processor to determine whether the one or more output entries corresponds to the first class of identifiers by being further configured to: generate a concatenated regular expression comprising each of the first class of error identifiers; and compare each of the one or more output entries to the concatenated regular expression.