11. An electronic design and verification system for synthesizing a behavioral description of a circuit to generate a structural description of the circuit, the system comprising: a storage apparatus to store a state node and the behavioral description of the circuit; and a processor including: a path annotation component configured to: parse the behavioral description of the circuit to identify a first text and/or a second text; define a path annotation based on the identified first text and/or the identified second text; and annotate the state node with the path annotation; and an output generator component configured to generate the structural description of the circuit based on the path annotation.
11. An electronic design and verification system for synthesizing a behavioral description of a circuit to generate a structural description of the circuit, the system comprising: a storage apparatus to store a state node and the behavioral description of the circuit; and a processor including: a path annotation component configured to: parse the behavioral description of the circuit to identify a first text and/or a second text; define a path annotation based on the identified first text and/or the identified second text; and annotate the state node with the path annotation; and an output generator component configured to generate the structural description of the circuit based on the path annotation. 15. The system of claim 11 , wherein the processor further includes a naming component, the naming component configured to: receive a name and a path annotation for the state node; responsive to a determination that more than one state node match the received path annotation, create a unique name for each of the matching state nodes based on the received name and associating each of the created unique names with a respective one of the matching state nodes; and responsive to a determination that a unique state node matches the received path annotation, associate the unique state node with the received name; wherein each of the created unique names associated with the respective one of the matching state nodes persists through at least two runs of the electronic design and verification tool.