7. A method comprising: executing, by a dispatcher via a dispatcher table, a first translated binary, the dispatcher table mapping a subset of instructions from a source binary to corresponding instructions in the first translated binary; upon encountering a branch instruction in the first translated binary with a target that is addressable in the first translated binary, branching, by a processor, to a target address in the first translated binary and executing an instruction at the target address in the first translated binary; upon encountering a branch instruction in the first translated binary with a target that is not addressable in the first translated binary, accessing a second translated binary, the second translated binary including one or more marker values corresponding to a second set of instructions in the second translated binary; wherein the processor is programmed to branch to a target address, in the second translated binary, described by a marker value in a second marker table and execute an instruction at the target address in the second translated binary; and returning to the first translated binary from the second translated binary after reaching a subsequent branch instruction in the second translated binary by branching directly to the dispatcher for every branch instruction that leaves a current function from the second translated binary.
7. A method comprising: executing, by a dispatcher via a dispatcher table, a first translated binary, the dispatcher table mapping a subset of instructions from a source binary to corresponding instructions in the first translated binary; upon encountering a branch instruction in the first translated binary with a target that is addressable in the first translated binary, branching, by a processor, to a target address in the first translated binary and executing an instruction at the target address in the first translated binary; upon encountering a branch instruction in the first translated binary with a target that is not addressable in the first translated binary, accessing a second translated binary, the second translated binary including one or more marker values corresponding to a second set of instructions in the second translated binary; wherein the processor is programmed to branch to a target address, in the second translated binary, described by a marker value in a second marker table and execute an instruction at the target address in the second translated binary; and returning to the first translated binary from the second translated binary after reaching a subsequent branch instruction in the second translated binary by branching directly to the dispatcher for every branch instruction that leaves a current function from the second translated binary. 14. The method of claim 7 , wherein the dispatcher table is a hash table.