14. A system for reasonable functional verification of a design of an integrated circuit (IC), the system comprising: a processing unit; a storage coupled to the processing unit; and, a memory coupled to the processing unit, the memory containing instructions that when executed by the processing unit: retrieve from storage a description of the design of at least a portion of the IC; bring the at least a portion of the IC in the received description to a state close to a suspected point of failure respective of a setup for failure (SFF) property; execute a set of instructions by functional verification of the at least a portion of the design of the IC from the suspected point of failure respective of at least a trigger for failure (TFF) property; and, providing a report respective of a result of execution of the functional verification.
14. A system for reasonable functional verification of a design of an integrated circuit (IC), the system comprising: a processing unit; a storage coupled to the processing unit; and, a memory coupled to the processing unit, the memory containing instructions that when executed by the processing unit: retrieve from storage a description of the design of at least a portion of the IC; bring the at least a portion of the IC in the received description to a state close to a suspected point of failure respective of a setup for failure (SFF) property; execute a set of instructions by functional verification of the at least a portion of the design of the IC from the suspected point of failure respective of at least a trigger for failure (TFF) property; and, providing a report respective of a result of execution of the functional verification. 22. The system of claim 14 , wherein the memory further contains instructions that, when executed by the processing unit, provide for determination of a coverage metric that is a ratio between a number of operations actually performed for function verification and a minimum number of operations necessary for a desired level of coverage.