11. A memory controller, comprising: a memory access circuit for reading a first code word and a second code word from one or more memory devices, wherein the first code word and the second code word respectively comprises a plurality of coded bits; and a low density parity check (LDPC) decoding circuit for decoding the first code word according to the hard information of the coded bits of the first code word; wherein when the LDPC decoding circuit does not decode the first code word successfully according to the hard information of the coded bits of the first code word, the LDPC decoding circuit configures the memory access circuit to read the soft information of the coded bits of the first code word and the soft information of the coded bits of the second code word, and decodes the first code word and the second code word according to the soft information of the coded bits of the first code word and the soft information of the coded bits of the second code word.
11. A memory controller, comprising: a memory access circuit for reading a first code word and a second code word from one or more memory devices, wherein the first code word and the second code word respectively comprises a plurality of coded bits; and a low density parity check (LDPC) decoding circuit for decoding the first code word according to the hard information of the coded bits of the first code word; wherein when the LDPC decoding circuit does not decode the first code word successfully according to the hard information of the coded bits of the first code word, the LDPC decoding circuit configures the memory access circuit to read the soft information of the coded bits of the first code word and the soft information of the coded bits of the second code word, and decodes the first code word and the second code word according to the soft information of the coded bits of the first code word and the soft information of the coded bits of the second code word. 12. The memory controller of claim 11 , wherein the LDPC decoding circuit generate a plurality of check node messages and a plurality of variable node messages according to the hard information of the first code word to determine whether the LDPC decoding circuit decodes the first code word successfully.