2. The processing apparatus in accordance with claim 1 wherein said binary words applied to said second portion of said memory addressing inputs are grouped into messages that are being checked to locate said predetermined sequences of characters and further comprising a buffer memory in which each of said messages are stored while its binary words are being processed, said stored messages being read out for transfer depending upon the results of processing of its binary word content.
2. The processing apparatus in accordance with claim 1 wherein said binary words applied to said second portion of said memory addressing inputs are grouped into messages that are being checked to locate said predetermined sequences of characters and further comprising a buffer memory in which each of said messages are stored while its binary words are being processed, said stored messages being read out for transfer depending upon the results of processing of its binary word content. 3. The processing apparatus in accordance with claim 2 wherein each predetermined character sequence receipt indication is a single binary bit which starts in a zero state and changes to a one state output upon the receipt of each complete character sequence.