1. An integrated circuit, comprising: a static random access memory array; said static random access memory array comprising at least two cores, wherein only one of said at least two cores is written at a time; a tristate driver; and said tristate driver being configured to apply a high impedance state to one of said at least two cores that is not being written, in response to a signal from a logic NOR, wherein said logic NOR receives a first input signal from a write clock and a second input signal based on at least a portion of a write address, wherein said write address is directed to said static random access memory array.
1. An integrated circuit, comprising: a static random access memory array; said static random access memory array comprising at least two cores, wherein only one of said at least two cores is written at a time; a tristate driver; and said tristate driver being configured to apply a high impedance state to one of said at least two cores that is not being written, in response to a signal from a logic NOR, wherein said logic NOR receives a first input signal from a write clock and a second input signal based on at least a portion of a write address, wherein said write address is directed to said static random access memory array. 4. The integrated circuit of claim 1 , wherein said logic NOR replaces an inline transistor from said tristate driver.