8. A system for analyzing an RTL-level circuit description netlist to produce a higher level circuit description, the system comprising: one or more hardware processors; a memory that contains instructions for execution by the one or more hardware processors; and a database for storing the RTL-level circuit description netlist and the higher-level circuit description, wherein: the one or more hardware processors are configured to: receiving the netlist, the netlist including a hierarchy of IP block instances on two or more levels, the IP block instances having one or more ports with signal names and properties attached, wherein at least some of the signal names or properties on at least one net in the circuit descriptions netlist are dissimilar; propagate signal names and properties from at least a first IP block instance to a second IP block instance according to connectivity between the first and second IP block instances as represented in the netlist, wherein by said propagating at least one signal name or property on the first IP block instance is assigned to the second IP block instance, thereby replacing an existing signal name or property on the second IP block instance; group together the signal names into a plurality of groups according to the signal properties and the connectivity; assign at least one of the groups of signal names to a higher-level interface definition; and save the grouped signal names in the database.
8. A system for analyzing an RTL-level circuit description netlist to produce a higher level circuit description, the system comprising: one or more hardware processors; a memory that contains instructions for execution by the one or more hardware processors; and a database for storing the RTL-level circuit description netlist and the higher-level circuit description, wherein: the one or more hardware processors are configured to: receiving the netlist, the netlist including a hierarchy of IP block instances on two or more levels, the IP block instances having one or more ports with signal names and properties attached, wherein at least some of the signal names or properties on at least one net in the circuit descriptions netlist are dissimilar; propagate signal names and properties from at least a first IP block instance to a second IP block instance according to connectivity between the first and second IP block instances as represented in the netlist, wherein by said propagating at least one signal name or property on the first IP block instance is assigned to the second IP block instance, thereby replacing an existing signal name or property on the second IP block instance; group together the signal names into a plurality of groups according to the signal properties and the connectivity; assign at least one of the groups of signal names to a higher-level interface definition; and save the grouped signal names in the database. 14. The system of claim 8 , wherein after performing propagation of signal names and properties by traversing a design hierarchy resulting in differing signal groupings between multiple interconnected IP block instances, a single signal grouping is chosen from said differing signal groupings by heuristic analysis, wherein: a signal grouping is chosen that appears maximally in all of said multiple interconnected IP block instances; or a signal grouping is chosen that is the intersection of all signals appearing in signal groupings at each of said multiple interconnected IP block instances; or a signal grouping is chosen that is the union of all signals appearing in signal groupings at each of said multiple interconnected IP block instances.