6. Apparatus according to claim 1 and further including means to convert the data rate of data flowing through said apparatus comprising a FIFO memory receiving input data at a first rate and providing an output at a rate which is equal to N over M of said input rate.
6. Apparatus according to claim 1 and further including means to convert the data rate of data flowing through said apparatus comprising a FIFO memory receiving input data at a first rate and providing an output at a rate which is equal to N over M of said input rate. 7. Apparatus according to claim 6 and further including means for generating said output rate comprising a phase-locked loop having as an input said input rate and dividing said input rate by said ratio of N over M to provide said output rate.