8. A modulus encoder comprising: first means for obtaining a number of moduli; second means for obtaining a binary input having a plurality of bits; and processing means configured to: represent said binary input as a plurality of short words; and perform a short-word division procedure in connection with said short words to thereby determine a plurality of index values associated with said moduli, where said plurality of index values and said plurality of moduli are capable of representing said binary input.
8. A modulus encoder comprising: first means for obtaining a number of moduli; second means for obtaining a binary input having a plurality of bits; and processing means configured to: represent said binary input as a plurality of short words; and perform a short-word division procedure in connection with said short words to thereby determine a plurality of index values associated with said moduli, where said plurality of index values and said plurality of moduli are capable of representing said binary input. 11. A modulus encoder according to claim 8, wherein said processing means is configured to represent said binary input as l short words, each of said short words having b bits.