3. An apparatus comprising: a computer usable medium containing program code, said program code including: instructions for running a testcase against a simulation model of an electronic design, wherein: the simulation model is formed of representations of instances of a plurality of design entities, the instances of the design entities contain a plurality of signals and functional logic that define functional operation of the electronic design, each instance of at least a particular design entity of the plurality of design entities contains an instance of an instrumentation entity that monitors the containing instance of the particular design entity but does not contribute to functional operation of the electronic design, and each instance of the instrumentation entity contains a trace array logically coupled to receive a monitored signal set including at least one signal among the plurality of signals, wherein the trace array is further logically coupled to receive a control signal among the plurality of signals; and instructions for recording trace data for the monitored signal set within the trace array during the running of the testcase, wherein the recording includes concurrently storing within the trace array multiple values of the monitored signal set obtained over multiple cycles of functional operation of the simulation model, wherein the instructions for recording trace data include: instructions for recording, within the trace array, values assumed by the monitored signal set during only those cycles of functional operation during which the control signal is asserted and for refraining from recording values assumed by the monitored signal set during those cycles of functional operation during which the control signal is not asserted, such that no values assumed by the monitored signal set are recorded for those cycles of functional operation during which the control signal is not asserted; instructions for recording in the trace array a number of functional cycles elapsed between said values assumed by the monitored signal set; and instructions for exporting said trace data from said trace array in a trace file and storing said trace file in data storage.
3. An apparatus comprising: a computer usable medium containing program code, said program code including: instructions for running a testcase against a simulation model of an electronic design, wherein: the simulation model is formed of representations of instances of a plurality of design entities, the instances of the design entities contain a plurality of signals and functional logic that define functional operation of the electronic design, each instance of at least a particular design entity of the plurality of design entities contains an instance of an instrumentation entity that monitors the containing instance of the particular design entity but does not contribute to functional operation of the electronic design, and each instance of the instrumentation entity contains a trace array logically coupled to receive a monitored signal set including at least one signal among the plurality of signals, wherein the trace array is further logically coupled to receive a control signal among the plurality of signals; and instructions for recording trace data for the monitored signal set within the trace array during the running of the testcase, wherein the recording includes concurrently storing within the trace array multiple values of the monitored signal set obtained over multiple cycles of functional operation of the simulation model, wherein the instructions for recording trace data include: instructions for recording, within the trace array, values assumed by the monitored signal set during only those cycles of functional operation during which the control signal is asserted and for refraining from recording values assumed by the monitored signal set during those cycles of functional operation during which the control signal is not asserted, such that no values assumed by the monitored signal set are recorded for those cycles of functional operation during which the control signal is not asserted; instructions for recording in the trace array a number of functional cycles elapsed between said values assumed by the monitored signal set; and instructions for exporting said trace data from said trace array in a trace file and storing said trace file in data storage. 23. The apparatus of claim 3 , wherein said instructions for storing comprises instructions for automatically naming the trace file in data storage by a filename indicating the containing instance of the particular design entity.