7. A processor-implemented method for generating a circuit for converting a first network packet into a second network packet, the processor-implemented method comprising: inputting a textual language specification that includes a plurality of modification actions, each modification action being one of an insertion action for inserting a data segment into the first network packet and a removal action for removing a data segment from the first network packet; concurrently scanning through a first plurality of data units in a first sequence of data words in the first network packet and a second plurality of data units in a second sequence of data words in the second network packet, each data word in the first and second network packets including a same number of the data units, wherein the scanning through the first plurality of data units in the first sequence of data words is suspended throughout each insertion action of the modification actions, and the scanning through the second plurality of data units in the second sequence of data words is suspended throughout each removal action of the modification actions; generating a respective one of a plurality of states of a state machine of the circuit for each pairing, which is encountered during the concurrently scanning, of a first data word from the first sequence and a second data word from the second sequence, the respective state for selecting the data units of the second data word from the data segment of each insertion action of the at least one modification action and the data units of both the first data word and a prior data word to the first data word in the first sequence; generating a look-ahead stage, an operation stage coupled to the look-ahead stage, an insert/remove stage that includes the state machine and is coupled to the operation stage, and an interleave stage that is coupled to the insert/remove stage; and outputting a specification of the state machine, the look-ahead stage, the operation stage, the insert/remove stage, and the interleave stage in a hardware description language.
7. A processor-implemented method for generating a circuit for converting a first network packet into a second network packet, the processor-implemented method comprising: inputting a textual language specification that includes a plurality of modification actions, each modification action being one of an insertion action for inserting a data segment into the first network packet and a removal action for removing a data segment from the first network packet; concurrently scanning through a first plurality of data units in a first sequence of data words in the first network packet and a second plurality of data units in a second sequence of data words in the second network packet, each data word in the first and second network packets including a same number of the data units, wherein the scanning through the first plurality of data units in the first sequence of data words is suspended throughout each insertion action of the modification actions, and the scanning through the second plurality of data units in the second sequence of data words is suspended throughout each removal action of the modification actions; generating a respective one of a plurality of states of a state machine of the circuit for each pairing, which is encountered during the concurrently scanning, of a first data word from the first sequence and a second data word from the second sequence, the respective state for selecting the data units of the second data word from the data segment of each insertion action of the at least one modification action and the data units of both the first data word and a prior data word to the first data word in the first sequence; generating a look-ahead stage, an operation stage coupled to the look-ahead stage, an insert/remove stage that includes the state machine and is coupled to the operation stage, and an interleave stage that is coupled to the insert/remove stage; and outputting a specification of the state machine, the look-ahead stage, the operation stage, the insert/remove stage, and the interleave stage in a hardware description language. 18. The processor-implemented method of claim 7 , further comprising sorting the modification actions from the textual language specification into an order of the scanning through the first plurality of data units in the first sequence of data words in the first network packet.