4. The method of claim 1 further comprises checking feasibility of a violation in the electronic circuit by conjoining the violation with the set of design constraints to form a conjoined set of constraints, and inputting the conjoined set of constraints into a satisfiability solver.
4. The method of claim 1 further comprises checking feasibility of a violation in the electronic circuit by conjoining the violation with the set of design constraints to form a conjoined set of constraints, and inputting the conjoined set of constraints into a satisfiability solver. 5. The method of claim 4 wherein checking feasibility of a violation further comprises replacing select variable assignments in the assignment with relationships between variables to form a set of constraints that represent the violation, conjoining the set of constraints that represent the violation with the set of design constraints to form a conjoined set of constraints; and inputting the conjoined set of constraints into the satisfiability solver.