21. The hardware module of claim 18 , further comprising: a hardware finite state machine configured to control the parsing; wherein the finite state machine changes from a current state of the parsing to a next state based on: said current state; and an XML delimiter identified in the document.
21. The hardware module of claim 18 , further comprising: a hardware finite state machine configured to control the parsing; wherein the finite state machine changes from a current state of the parsing to a next state based on: said current state; and an XML delimiter identified in the document. 22. The hardware module of claim 21 , wherein said validation circuitry validates a character based on said current state of the parsing.