1. A computer implemented method for generating a description of compiler code selector rules from an architecture description, the compiler code selector rules for use in a compiler that translates source code into machine instructions of a target processor, the method comprising: accessing a target processor architecture model of the target processor, the target processor architecture model described in a processor architecture description language, the target processor architecture model comprising semantic information and syntax information for the machine instructions, and description of non-terminals of the target processor; generating a plurality of semantic statements from semantic information included in the processor architecture model; applying, to said semantic information, at least one semantic transformation from a library of pre-defined semantic transformations to generate a single semantic statement from a sequence of at least two of said plurality of semantic statements; generating a plurality of basic rules that map from source code operations to machine instructions comprising: accessing rules that map from source code operations to semantic patterns, searching said semantic statements for matches to said semantic patterns, and mapping a sequence of two or more source code operations to a single machine instruction based on the accessed rules that matches from semantic statements to semantic patterns; and permuting said basic rules with non-terminals to generate a plurality of mappings that serve as said description of said compiler code selector rules.
1. A computer implemented method for generating a description of compiler code selector rules from an architecture description, the compiler code selector rules for use in a compiler that translates source code into machine instructions of a target processor, the method comprising: accessing a target processor architecture model of the target processor, the target processor architecture model described in a processor architecture description language, the target processor architecture model comprising semantic information and syntax information for the machine instructions, and description of non-terminals of the target processor; generating a plurality of semantic statements from semantic information included in the processor architecture model; applying, to said semantic information, at least one semantic transformation from a library of pre-defined semantic transformations to generate a single semantic statement from a sequence of at least two of said plurality of semantic statements; generating a plurality of basic rules that map from source code operations to machine instructions comprising: accessing rules that map from source code operations to semantic patterns, searching said semantic statements for matches to said semantic patterns, and mapping a sequence of two or more source code operations to a single machine instruction based on the accessed rules that matches from semantic statements to semantic patterns; and permuting said basic rules with non-terminals to generate a plurality of mappings that serve as said description of said compiler code selector rules. 6. The method of claim 1 , further comprising creating a tree pattern for a rule not in said accessed rules by analyzing a complex semantic statement of said plurality of semantic statements.