8. The device of claim 1 , wherein the memory cells comprise multiple level memory cells capable of storing x bits, where x>1.
8. The device of claim 1 , wherein the memory cells comprise multiple level memory cells capable of storing x bits, where x>1. 9. The device of claim 8 , wherein the pages of the memory cell array are physical pages and each of the physical pages comprises a logical page for each of the x bits.