10. The detector of claim 9 wherein the first and second transistors are each n-channel FETs and are closely matched, the first and second current sources being first and second p-channel FETs controlled by a current mirror arrangement.
10. The detector of claim 9 wherein the first and second transistors are each n-channel FETs and are closely matched, the first and second current sources being first and second p-channel FETs controlled by a current mirror arrangement. 11. The detector of claim 10 further comprising: an amplifier stage comprising a p-channel FET and an n-channel FET connected as an inverter amplifier with common gates connected to the second capacitor, and common drains connected to an output lead such that when the voltage on the second capacitor changes sufficiently from its quiescent value, the output lead is switched in polarity.