15. A system for register-transfer level (RTL) design checking for exploring simulation mismatches, synthesis mismatches, or ambiguous language semantics associated with generating a derived design from RTL design code, the system comprising: at least one processor configured to generate an internal representation of an RTL design for an electronic circuit design by using the RTL design code; a design violation pattern database to contain design violation patterns, wherein the design violation patterns identify violations relating to the simulation mismatches, synthesis mismatches, or ambiguous language semantics associated with generating the derived design that are otherwise undetected during equivalence checking between the derived design and the RTL design code; and a design match engine configured to compare the RTL design code with the design violation patterns contained in the design violation pattern database, and wherein the at least one processor is further configured to assign a rule object to a design pattern in the RTL design code, when the design match engine determines that the design pattern in the RTL design code matches one of the design violation patterns in the design violation pattern database, and to generate a violation report comprising the rule objects and their corresponding design violation patterns.
15. A system for register-transfer level (RTL) design checking for exploring simulation mismatches, synthesis mismatches, or ambiguous language semantics associated with generating a derived design from RTL design code, the system comprising: at least one processor configured to generate an internal representation of an RTL design for an electronic circuit design by using the RTL design code; a design violation pattern database to contain design violation patterns, wherein the design violation patterns identify violations relating to the simulation mismatches, synthesis mismatches, or ambiguous language semantics associated with generating the derived design that are otherwise undetected during equivalence checking between the derived design and the RTL design code; and a design match engine configured to compare the RTL design code with the design violation patterns contained in the design violation pattern database, and wherein the at least one processor is further configured to assign a rule object to a design pattern in the RTL design code, when the design match engine determines that the design pattern in the RTL design code matches one of the design violation patterns in the design violation pattern database, and to generate a violation report comprising the rule objects and their corresponding design violation patterns. 16. The system of claim 15 , wherein the at least one processor is further configured to perform an equivalence check of the derived design compared to a golden RTL design for the electronic circuit design.