21. An apparatus for generating hardware description language (HDL) code, the apparatus comprising: means for receiving an executable, graphical model having a plurality of blocks, wherein the model includes a frame-based interface between at least two of the blocks, the frame-based interface implementable in hardware in a plurality of ways, the plurality of ways in which the frame-enabled block is implementable in hardware include: a fully parallelized way that uses a plurality of first parallel hardware components, a fully serialized way that uses a second serial hardware component, and a combination serialized and parallelized way that uses a plurality of second parallel hardware components and a second serial hardware component; means for receiving a selected preference for a hardware implementation of the frame-based interface between the at least two blocks of the model, the selected preference free from affecting execution of the frame-based interface in the model and to cause the frame-based interface to be implemented in hardware in a particular way of the plurality of ways; means for generating the HDL code for the frame-based interface, the generated HDL code implementing the frame-based interface in hardware in the particular way that satisfies the selected preference, the particular way selected from the group consisting of: the fully parallelized way, in which the plurality of first parallel hardware components are included in the hardware implementation of the frame-enabled block, the fully serialized way, in which the first serial hardware component is included in the hardware implementation of the frame-enabled block, and the combination serialized and parallelized way, in which the second serial hardware component and the plurality of second parallel hardware components are included in the hardware implementation of the frame-enabled block.
21. An apparatus for generating hardware description language (HDL) code, the apparatus comprising: means for receiving an executable, graphical model having a plurality of blocks, wherein the model includes a frame-based interface between at least two of the blocks, the frame-based interface implementable in hardware in a plurality of ways, the plurality of ways in which the frame-enabled block is implementable in hardware include: a fully parallelized way that uses a plurality of first parallel hardware components, a fully serialized way that uses a second serial hardware component, and a combination serialized and parallelized way that uses a plurality of second parallel hardware components and a second serial hardware component; means for receiving a selected preference for a hardware implementation of the frame-based interface between the at least two blocks of the model, the selected preference free from affecting execution of the frame-based interface in the model and to cause the frame-based interface to be implemented in hardware in a particular way of the plurality of ways; means for generating the HDL code for the frame-based interface, the generated HDL code implementing the frame-based interface in hardware in the particular way that satisfies the selected preference, the particular way selected from the group consisting of: the fully parallelized way, in which the plurality of first parallel hardware components are included in the hardware implementation of the frame-enabled block, the fully serialized way, in which the first serial hardware component is included in the hardware implementation of the frame-enabled block, and the combination serialized and parallelized way, in which the second serial hardware component and the plurality of second parallel hardware components are included in the hardware implementation of the frame-enabled block. 23. The apparatus of claim 21 wherein the frame-based interface has a plurality of channels of data samples, and the data samples are one of scalars, vectors or matrices.