14. A processor, comprising: an address translator configured to support a plurality of memory virtualization techniques; and a virtualization technique selector; wherein said address translator is configured to translate, on behalf of a first application executing on said processor, a memory request directed to a first virtual memory address to a first physical memory address according to a first memory virtualization technique; wherein said virtualization technique selector is configured to dynamically select a second memory virtualization technique for translating virtual addresses to physical addresses on behalf of said first application during said executing; wherein said first memory virtualization technique comprises translating virtual addresses to physical addresses using one or more look-up operations on a stored mapping of virtual addresses to physical addresses; wherein said second memory virtualization technique comprises translating virtual addresses to physical addresses by generating physical addresses from respective virtual addresses using a mathematical or logical function applied to the respective virtual addresses without performing a look-up operation on a stored mapping of virtual addresses to physical addresses; wherein, during said executing and subsequent to said virtualization technique selector selecting a second memory virtualization technique, said address translator is configured to translate a second memory request directed to a second virtual memory address to a second physical memory address on behalf of said first application according to said second memory virtualization technique; and wherein said dynamically selecting and said translating according to said second memory virtualization technique are performed transparently to said first application.
14. A processor, comprising: an address translator configured to support a plurality of memory virtualization techniques; and a virtualization technique selector; wherein said address translator is configured to translate, on behalf of a first application executing on said processor, a memory request directed to a first virtual memory address to a first physical memory address according to a first memory virtualization technique; wherein said virtualization technique selector is configured to dynamically select a second memory virtualization technique for translating virtual addresses to physical addresses on behalf of said first application during said executing; wherein said first memory virtualization technique comprises translating virtual addresses to physical addresses using one or more look-up operations on a stored mapping of virtual addresses to physical addresses; wherein said second memory virtualization technique comprises translating virtual addresses to physical addresses by generating physical addresses from respective virtual addresses using a mathematical or logical function applied to the respective virtual addresses without performing a look-up operation on a stored mapping of virtual addresses to physical addresses; wherein, during said executing and subsequent to said virtualization technique selector selecting a second memory virtualization technique, said address translator is configured to translate a second memory request directed to a second virtual memory address to a second physical memory address on behalf of said first application according to said second memory virtualization technique; and wherein said dynamically selecting and said translating according to said second memory virtualization technique are performed transparently to said first application. 15. The processor of claim 14 , further comprising a performance analyzer configured to analyze performance of said first memory virtualization technique as applied to said first application executing on said processor during said executing, wherein said dynamically selecting a second memory virtualization technique is dependent on said analyzing.