24. A dictation transcription interface as recited in claim 18 further comprising a processor clock having a bus clock period, said processor clock connected to said processor system.
24. A dictation transcription interface as recited in claim 18 further comprising a processor clock having a bus clock period, said processor clock connected to said processor system. 30. A dictation transcription interface as recited in claim 24, wherein said processor system writes said message signal via said host bus to said memory storage means during a second cycle of said bus clock period, whereby said memory storage means generates said stored message signal by storing said message signal.