10. The digital computer system of claim 9, wherein said input format means further comprises: input multiplexer means connected from said bus means for receiving said third certain of said operands, and input register means connected from said input multiplexer means and to said inputs of said gating means for (1) extracting first certain information bits from said third certain of said operands, (2) transferring said first certain information bits into first certain information bit positions of said corresponding first certain of said operands and (3) providing said corresponding first certain of said operands to said inputs of said gating means.
10. The digital computer system of claim 9, wherein said input format means further comprises: input multiplexer means connected from said bus means for receiving said third certain of said operands, and input register means connected from said input multiplexer means and to said inputs of said gating means for (1) extracting first certain information bits from said third certain of said operands, (2) transferring said first certain information bits into first certain information bit positions of said corresponding first certain of said operands and (3) providing said corresponding first certain of said operands to said inputs of said gating means. 11. The digital computer system of claim 10, wherein said output format means further comprises: output register means connected from said output register means and to said bus means for transferring said selected bits of said result into selected bit positions and providing the bits in said selected bit positions to said bus means.