56. A data processing system according to claim 31 wherein the memory processor further formats a plurality of second data packets, said memory processor disassembling the plurality of second data packets into a plurality of first data packets as the plurality of second data packets are sequentially transmitted over the second bus, each of the plurality of first data packets being sequential transmitted over the first bus; said memory processor further controlling which of the plurality of second data packets are disassembled into each of the plurality of first data packets.
56. A data processing system according to claim 31 wherein the memory processor further formats a plurality of second data packets, said memory processor disassembling the plurality of second data packets into a plurality of first data packets as the plurality of second data packets are sequentially transmitted over the second bus, each of the plurality of first data packets being sequential transmitted over the first bus; said memory processor further controlling which of the plurality of second data packets are disassembled into each of the plurality of first data packets. 57. A data processing system according to claim 56 wherein the first bus operates at a higher frequency than the second bus.