16. A computer system in accordance with claim 15 wherein said time delay mechanism includes: a counting mechanism that is initialized to a count value equal to the numeric value of at least a portion of one of said command data entries in said command memory and that counts the passage of a number of fixed-length time intervals equal to the count value.
17. A computer system in accordance with claim 16 wherein: the fixed length time interval is a multiple of 12.5 milliseconds.