15. A vital decoder for a digital message which digital message includes a pair of multi-bit words separated from other words by a predetermined multi-bit framing sequence, a second word of said message complementary to a first word, said decoder including a single central processing means, said central processing means including: means responsive to said framing sequence for identifying each multi-bit word; means responsive to each said multi-bit word for determining a command represented thereby; checking means for checking control of said central processing means over its own output ports, said checking means producing one of two distinctive multi-bit words in response to completion of said checking after receipt of each said message word, said distinctive multi-bit words being complementary if said message words are valid and said checks are favorable, said decoder further including; logic means responsive to said distinctive multi-bit words for validating operation of said central processing means, said logic means including a multi-bit comparator for comparing said distinctive words to predetermined bit patterns and validating said operation if, and only if, said distinctive words are produced alternately and in sequence, and means responsive to validation by said logic means for enabling utilization of a command provided by said central processing means.
16. The apparatus of claim 15 which further includes isolation means coupling outputs of said central processing means to inputs thereof, said outputs coupled through said isolation means to said inputs with a right shift said checking means setting the lowest order output bit, and cyclically reading output to input and writing input to output until the lowest order output is again set, said checking means further recording the number of cycles employed and using said number in producing said distinctive multi-bit words.