1. A machine implemented data bit error management method comprising: for a set of data bits, each data bit having a data bit position in said data bit set, generating a set of at least four parity bits, each parity bit having a parity bit position in said parity bit set, said generating comprising, for a given parity bit position: calculating a parity bit for said given parity bit position from data bits at selected data bit positions such that each data bit position is selected for inclusion in the calculation of parity bits in at least three parity bit positions, said at least three parity bit positions being a sub-set of all possible parity bit positions, and such that, for a selected data bit position included in the calculation of a given sub-set of parity bit positions, said given subset of parity bit positions is unique to said selected data bit position, a base 2 number defined by said given sub-set has a lower numerical value than does a base 2 number defined by a sub-set unique to any next higher order data bit position, and at least one other data bit position is included in the calculation of at least one parity bit position of said given sub-set of parity bit positions; and transmitting said set of data bits and said set of parity bits.
2. The method of claim 1 wherein each data bit position is included in the calculation of 2n+1 parity bits, where n is a positive integer.