7. The circuit of claim 6 further comprising a reset unit for placing the circuit in quiescent state when there is no signal, and for enabling the circuit to active state when there is a signal, the reset unit being connected to receive binary "0" and "1" bits and on receipt of a given plurality of consecutive "1" bits enabling the circuit to active state, and for generating a synchronizing pulse to insure the accurate framing of the binary bits into proper sequences of words.
6. The circuit of claim 1 in further combination with means for generating clock pulses, each clock pulse occurring after a binary "0" and during a binary "1" from the amplifier stage.