7. The data processing system for performing the fuzzy inference operation of claim 6 wherein the rule bits generating circuit further comprises: a second plurality of label code registers, each of the second plurality of label code registers storing one of the plurality of antecedents of the second rule; a second plurality of comparators, each of the second plurality of comparators being coupled to one of the second plurality of label code registers for a corresponding one of the plurality of antecedents of the second rule, each of the second plurality of comparators being coupled to the input label sorter for receiving each of the plurality of input labels, each of the second plurality of comparators comparing a one of the plurality of antecedents of the second rule stored therein with each of the plurality of input labels, each of the second plurality of comparators asserting one of a plurality of second match signals when the one of plurality of antecedents of the second rule stored therein equals one of the plurality of input labels; and second logic means coupled to each of the second plurality of comparators for receiving the plurality of second match signals, the second logic means asserting the second rule signal when one of the plurality of second match signals is asserted.
6. The data processing system for performing the fuzzy inference operation of claim 1 wherein the rule bits generating circuit, comprises: a first plurality of label code registers, each of the first plurality of label code registers storing one of the plurality of antecedents of the first rule; a first plurality of comparators, each of the first plurality of comparators being coupled to one of the first plurality of label code registers for a corresponding one of the plurality of antecedents of the first rule, each of the first plurality of comparators being coupled to the input label sorter for receiving each of the plurality of input labels, each of the first plurality of comparators comparing a one of the plurality of antecedents of the first rule stored therein with each of the plurality of input labels, each of the first plurality of comparators asserting one of a plurality of first match signals when the one of plurality of antecedents of the first rule stored therein equals one of the plurality of input labels; and first logic means coupled to each of the first plurality of comparators for receiving the plurality of first match signals, the first logic means asserting the first rule signal when one of the plurality of first match signals is asserted.