13. The method of claim 12 , wherein the memory device includes multiple memory chips and each of the multiple blocks is arranged respectively on one of the multiple chips.
12. A method of operating a solid state memory device including multiple blocks, each block comprising an array of memory cells arranged in a plurality of pages, the method comprising: encoding data into inner code words and outer code words, the inner code words comprising data and parity information, each page of each block storing at least one inner code word, the outer code words comprising data symbols and parity symbols, one or more pages of each block storing one or more symbols of each outer code word; reading the inner code words and the outer code words from the memory device; correcting errors in the data using the inner code words and the outer code words; and providing an error corrected output from the corrected data.