12. A method for datapath synthesis as recited in claim 11 wherein said step of generating a plurality of IC expression trees further includes the step of: partitioning said IC expression trees into a random logic category and a datapath category, where only said IC expression trees in said datapath category are subject to said matching step.
11. A method for datapath synthesis as recited in claim 10 wherein said step of generating a plurality of IC expression trees includes the steps of: parsing said hardware description language into a control data flow graphs; and generating an IC expression tree for each output of said control data flow graphs.