1. A computer implemented method for implementing multi-power domain digital or mixed-signal verification and low power simulation of a hierarchical electronic circuit design, comprising: using a computer system which comprises at least one processor and is programmed for performing a process, the process comprising: identifying a first hierarchical level and a second hierarchical level in the hierarchical electronic circuit design; referencing a power data file, which includes power specific data for at least a portion of a transistor level netlist in a digital or mixed-signal block of the hierarchical electronic circuit design, to obtain a first connectivity information; determining or identifying power intent data or information, which includes data or information for power intent for the at least the portion of the transistor level netlist, in a schematic of the hierarchical electronic circuit design based at least in part upon one or more criteria to infer a second connectivity information for at least a part of the schematic; and performing schematic level verification or simulation by using at least the schematic modified by using at least some of the power intent data or information and the second connectivity information, instead of the transistor level netlist.
3. The computer implemented method of claim 1 , wherein the power data file is in a common power format or a unified power format.