3. The semiconductor memory cell MWA encoding apparatus of claim 2 , the MCRA decoder further comprising: a data word generator to generate a series of m-bit data words D, each data word having a binary weighted value K, from K=1 through K=2^m−1; a data word index generator to generate a series of data word bit position indices i from i=0 through i=m−1; a data bit indexer coupled to the data word index generator and to the data word generator to receive a current value of the index i from the data word index generator and to receive a current value of the data word K from the data word generator and to output a state of the i th bit of the current K, B(K,i); a code bit indexer coupled to the data word generator to receive the current K and coupled to a decoder input terminal to receive a code word C to be decoded, the code bit indexer to output a state of the (K−1) th bit of C, C(K−1); and intersection XOR logic communicatively coupled to the data bit indexer and to the code bit indexer to perform, for each i, an XOR operation on all bits for which B(K,i) and C(K−1) are both logical “1” in order to generate a corresponding bit D(i) of a decoded data word D.
5. The semiconductor memory cell MWA encoding apparatus of claim 3 , the MCRA decoder further comprising: data value tracking logic coupled to the data word generator to determine whether all possible data words have been generated while i is set to a current value, to request a next K if all possible data words have not been generated for a current value of i, and to initiate the XOR operation if all possible data words have been generated while i is set to the current value; and data word index tracking logic coupled to the data word index generator to determine whether all values of i have been generated following an XOR operation, to request a next i if all values of i have not been generated, and to terminate decoding if all value of i have been generated.