15. The word detection circuit of claim 14, wherein said comparison circuit includes: a comparator having a first input, a second input forming said second input of said comparison circuit, and an output forming said output of said comparison circuit, wherein said output of said comparator is adapted for indicating whether a value on said second input of said comparator is less than a value on said first input of said comparator; and a multiplier having an input forming said first input of said comparison circuit and an output coupled to said first input of said comparator, said multiplier being adapted for providing a comparison value on said output of said multiplication circuit, wherein said comparison value is equal to a value provided on said input of said multiplier multiplied by said predetermined percentage.
14. A word detection circuit for determining a word value, said word detection circuit comprising: a delay element having a data input for receiving a value for a character, a first output adapted for providing a value received on said data input after a first predetermined period of time, a second output adapted for providing a value received on said data input after a second predetermined period of time, a load input coupled to said data input, and a load enable input, wherein asserting said load enable input causes a value on said load input to be provided on said second output; and a comparison circuit having a first input coupled to said data input of said delay element, a second input coupled to said first output of said delay element, and an output coupled to said load enable, said output being adapted for indicated whether a value on said second input of said comparison circuit is less than a predetermined percentage of a value on said first input of said comparison circuit.