45. A frequency sensing circuit according to claim 44 wherein said control signals include signals representing expP and manP, where EQU P=K+1, and EQU P=manP.times.2.sup.-expP
46. A frequency sensing circuit according to claim 45 wherein said multiplier comprises: a first shift register having an input coupled to the output of said delay means; a first multiplexer coupled to each stage of said shift register, said first multiplexer controlled by said expP signal; a second shift register coupled to the output of said first multiplexer; a second multiplexer coupled to each stage of said second shift register; logic means, controlled by said manP signal for gating the outputs of said second multiplexer; a summer coupled to the outputs of said logic means; and a subtracter for subtracting the input signal to said multiplier from the output of said summer.