9. The method according to claim 8 further comprising the step of: storing the translation data for the first virtual address from the master translation memory into the second translation buffer whenever translation data for the first virtual address from the master translating memory is stored into the first translation buffer.
8. A method for translating virtual addresses in a computing system having at least a first and a second instruction pipeline and a direct address translation unit for translating virtual addresses into real addresses, the direct address translation unit including a master translation memory for storing translation data, the direct address translation unit for translating a virtual address into a corresponding real address, comprising the steps of: storing a first subset of translation data from the master translation memory into a first translation buffer associated with the first instruction pipeline; translating a first virtual address received from the first instruction pipeline into a corresponding first real address, wherein the first virtual address translating step comprises the steps of: accessing the first translation buffer; indicating whether translation data for the first virtual address is stored in the first translation buffer; activating the direct address translation unit to translate the first virtual address when the translation data for the first virtual address is not stored in the first translation buffer; and storing the translation data for the first virtual address from the master translation memory into the first translation buffer; storing a second subset of translation data from the master translation memory into a second translation buffer associated with the second instruction pipeline; and translating a second virtual address received from the second instruction pipeline into a corresponding second real address, wherein the second virtual address translating step comprises the steps of: accessing the second translation buffer; indicating whether translation data for the second virtual address is stored in the second translation buffer; activating the direct address translation unit to translate the second virtual address when the translation data for the second virtual address is not stored in the second translation buffer; and storing the translation data for the second virtual address from the master translation memory into the second translation buffer.