7. A computer-implemented system for generating hardware description language (HDL) code for an executable model of a hardware system, said computer-implemented system comprising: a model comprising a first component that accepts frame-based input data, the first component representing a computational element of the hardware system, wherein a frame is a temporal collection of data samples acquired over a predetermined time period; and generated HDL code for the model, the generated HDL code serializing the first component wherein the generated HDL code serializing the first component further comprises: HDL code for a buffer storing at least a portion of the frame-based input data to the first component; and HDL code for at least one delay unit delaying processing of the at least a portion of the frame-based input data to the first component.
9. The computer-implemented system of claim 7 , further comprising: generated HDL code linearizing the at least a portion of the frame-based input data to the first component.