5. The memory device of claim 4 further comprising a second memory cell configurable to one of the states and resources which execute a process including: programming the second memory cell and verifying the second memory cell according to a second voltage level; and programming the second memory cell and verifying the second memory cell according to a second predetermined voltage level which is associated with another one of the states, wherein the second voltage level is less than the second predetermined voltage level and is not one of the predetermined voltages.
4. A memory device comprising: a first memory cell which is configurable to one of a plurality of states each associated with a pre-determined voltage level; and resources which execute a process including programming the first memory cell and verifying the first memory cell according to a first voltage level; and programming the first memory cell and verifying the first memory cell according to a first predetermined voltage level which is associated with one of the states, wherein the first voltage level is less than the first predetermined voltage level and is not one of the predetermined voltages.