11. A system comprising: a converter configured to receive, at an input of the converter, a first value of a short binary representation corresponding to a search space character, and to convert the short binary representation to a first long binary representation corresponding to the search space character, the first long binary representation having a bit at a first position set to a first bit value, the first position corresponding to the first value of the short binary representation, the converter being configured to generate a long binary representation having the bit at the first position set to the first bit value only when the value at the input of the converter is the first value of the short binary representation; a comparison circuit configured to receive at a first input the first long binary representation, and at a second input a second long binary representation, corresponding to a set of search characters, and to generate a binary output, the binary output having: a binary value indicating that the search space character matches a search character when a bit at the first position in the second long binary representation has a second bit value; and a binary value indicating that the search space character does not match a search character otherwise.
18. The system of claim 11 , further comprising a processing circuit configured to: convert each of a plurality of short binary representations corresponding to respective search characters, to a corresponding long binary representation; and combine the long binary representations corresponding to respective search character to form the second long binary representation.