18. A memory control method, comprising: reading a first code word and a second code word from one or more memory devices by utilizing a memory access circuit, wherein the first code word and the second code word respectively comprises a plurality of coded bits; performing a low density parity check (LDPC) decoding by utilizing a low density LDPC decoding circuit according to the hard information of the coded bits of the first code word; when the first code word is not decoded successfully, reading the soft information of the coded bits of the first code word and the soft information of the coded bits of the second code word by utilizing the memory access circuit, and decoding the first code word and the second code word by utilizing the LDPC decoding, circuit according to the soft information of the coded bits of the first code word and the soft information of the coded bits of the second code word.
20. The memory control method of claim 18 , further comprising: decoding the second code word by utilizing the LDPC decoding circuit according to the hard information of the coded bits of the second code word.