8. A speech analysis and synthesis system comrising: an analyzer including, means for analyzing an electrical speech signal by Cepstrum technique to generate a pitch period parameter, means for analyzing said speech signal to generate a voiced/unvoiced decision parameter, and means for analyzing said speech signal by linear prediction technique to generate a predetermined number of coefficient parameters and a power parameter; and a synthesizer including, pitch pulse generator means for receiving said pitch period parameter and generating pitch pulses having a corresponding pitch period, random noise generator means, switch means connected to said pitch pulsed generator means to said random noise generator means for receiving said voiced/unvoiced decision parameter, an output of said switch means being derived from said pitch pulse generator means if said decision is voiced, and from said random noise generator means if said decision is unvoiced, gain control means connected to said output of said switch means for receiving said power parameter, an output level of said gain control means being dependent upon said power parameter, and linear prediction filter means connected to said output of said gain control means for receiving and applying said coefficient parameters to said filter means to generate a replica or said speech signal at an output of said filter means; wherein said means for analyzing an electrical speech signal by Cepstrum technique includes means for conditioning a Cepstrum signal generated by said Cepstrum technique, said signal conditioning means generating a weighting signal which linearly increases in value during the time span of said Cepstrum and said means for conditioning said Cepstrum further adding said weighting signal to said Cepstrum during said time span to create a weighted Cepstrum signal.
9. A speech analysis and synthesis system as defined in claim 8 wherein said signal conditioning means includes: means for generating said weighting signal having a first adder with an output connected as an input to a register, said register having an output connected as a first input to said first adder, said first adder having as a second input an incrementing constant connected to said first adder through a first gate, said gate being enabled as an incremental element of said Cepstrum signal is gated through a second gate to a first input to a second adder, whereby said register is incremented for each element of said Cepstrum signal which is gated into said second adder; and means for adding said weighting signal to said Cepstrum by connecting the output of said register as a second input to said second adder, whereby the incremented output of said register is added to each element of said Cepstrum signal and an output of said second adder is said weighted Cepstrum signal.