15. A program product for making a computer system execute an analysis of a control flow graph, the program product comprising a non-transitory computer readable media including a memory of the computer system, and having, recorded therein, a program for analyzing the control flow graph, the program comprising the program codes of: extracting a program state of the program from a program state buffer, the program state including a program counter; generating an edge of a control flow graph from a branch instruction associated with the program counter to a target address of the branch instruction in an abstract interpretation for an assignment instruction to a branch target variable of a program; the program allocating a particular branch target variable to each branch instruction having a plurality of branch targets configured to store branch target addresses of each of the plurality of branch targets, with a branch target address for one of the plurality of branch targets being loaded from the branch target variable upon branching; a branch address of a branch instruction having one branch target as well as the target address assigned by the assignment instruction to the branch target variable being determined as certain constant values determined by compiling the program; adding the target address assigned by the assignment instruction to a program counter of a new program state of the abstract interpretation, and setting a flag for the particular program counter associated with the branch instruction; and terminating a current abstract interpretation in the case that the abstract interpretation reaches to program state already subjected to the abstract interpretation, as indicated by a flag set for a program state.
19. The program product of claim 15 , further comprising: loading a virtual address of a target top address of the branch instruction to a virtual address register; computing a virtual address of the branch target by adding an immediate operand of the assignment instruction to the virtual address of the target top address of the branch instruction; and defining the edge of the control flow graph between the branch instruction to the branch target.