3. The method of claim 1 , further comprising: responsive to receiving a request from one of the one or more interpretive computer programming language modules of the circuit design, calling one of the one or more HDL modules.
4. The method of claim 3 , wherein performing the simulation comprises: enabling the called HDL module; pipelining input arguments from the an interpretive computer programming language module into the called HDL module; receiving pipelined output data from the called HDL module; formatting the receiving pipelined output data; and returning the formatted data to the interpretive computer programming language module.