3. A method for fabricating an integrated circuit as recited in claim 2 wherein said netlist further includes random logic, wherein said random logic includes logic of said circuit specifications that is not included in datapaths of said circuit specifications.
4. A method for fabricating an integrated circuit as recited in claim 3 wherein said step of synthesizing a netlist comprises the steps of: parsing said hardware description language into a control data flow graph; generating an IC expression tree for each output of the control data flow graph; partitioning each IC expression tree into a random logic category and a datapath category; synthesizing random logic using logic synthesis, said logic synthesis utilizing a provided gate library; synthesizing datapath using datapath synthesis, said datapath synthesis utilizing said datapath library; and combining said datapath and said random logic to form said netlist.