4. The method of claim 3 further including the step of distributing cascode signal regenerating repeaters at periodic intervals along said pull down chains.
3. The method of claim 1 wherein said integrated circuit is CMOS cascode combinational logic having pull down transistor chains, and further including the steps of mapping said expressions and sub-expressions to logic voltage levels so that the true values of said expressions and sub-expressions correspond to ground voltage, and grouping said operators in said pull down transistor chains.