14. The system of claim 13 , wherein: the first long binary representation has a length of m bits, m being a positive integer; the second long binary representation has a length of m bits; the first bus input of the bit-wise AND gate has a width of m bits; the second bus input of the bit-wise AND gate has a width of m bits; and the bus output of the bit-wise AND gate has a width of m bits.
15. The system of claim 14 , further comprising a unary OR gate having m inputs and one output, the m inputs of the unary OR gate being connected to respective bits of the bus output of the bit-wise AND gate, the unary OR gate being configured to set the output of the unary OR gate: to a value of binary 1 when at least one of the m inputs is set to a value of binary 1; and to a value of binary 1 when each of the m inputs is set to a value of binary 0.