1. A memory unit comprising: a row decoder that includes decoding circuitry configured to receive address information and generate a set of word line control signals, and a set of word line drivers coupled to the decoding circuitry and responsive to the word line control signals, wherein each word line driver is configured to provide at least pull-up drive capability; a set of word lines, each word line coupled to at least one word line driver; and at least one word line pull-down driver coupled to the set of word lines and located away from the word line drivers, each word line pull-down driver configured to provide additional pull-down drive capability for the word line to which it couples.
2. The memory unit of claim 1 wherein the at least one word line pull-down driver is controlled by a common control signal.