22. A circuit arrangement for processing a succession of machine words in an arithmetic and logic unit, the circuit arrangement comprising: a first memory having a plurality of memory locations with respective associated addresses, the first memory being designed to store a set of machine words, with each machine word being able to be stored at one of the memory locations; a second memory for storing a succession of instruction words which prescribes a succession of machine words which are to be processed in the arithmetic and logic unit; and a buffer store having buffer store locations for buffer-storing machine words, wherein the arithmetic and logic unit for processing the succession of machine words is coupled to the first memory, the second memory, and the buffer store, and is designed to load a machine word which is to be processed from the buffer store if the machine word is available there or to load the machine word from the first memory and to store the machine word at one of the buffer-store locations in the buffer store, and wherein the circuit arrangement alters the association between at least one portion of the set of machine words and at least one portion of the set of address words and changes the succession of instruction words, so that the accordingly prescribed succession of machine words which are to be processed is unaltered.
23. The circuit arrangement as claimed in claim 22 , wherein the buffer store is designed to associate the buffer-store locations with the machine words which are to be buffer-stored based on the addresses of the memory locations at which the machine words are stored.