6. The method of claim 1 , wherein the second program and second program-verify operations during the second programming phase are conducted in a sequential order, comprising: programming one or more of the plurality of charge trapping memory cells along the word line to a first program level; verifying one or more of the plurality of charge trapping memory cells along the word line to a first program-verify level (PV 1 B); programming one or more of the plurality of charge trapping memory cells along the word line to a second program level; verifying one or more of the plurality of charge trapping memory cells along the word line to a second program-verify level (PV 2 B); programming one or more of the plurality of charge trapping memory cells along the word line to third program level; and verifying one or more of the plurality of charge trapping memory cells along the word line to a third program-verify level (PV 3 B).
1. A method for double programming a multi-level-cell (MLC) in a multi-bit-cell (MBC) of a charge trapping memory, the charge trapping memory having an array of charge trapping memory cells connecting to a plurality of word lines, each word line is connected to a plurality of charge trapping memory cells, each charge trapping memory cell having a first trapping site and a second trapping site, comprising: receiving a data pattern including a plurality of programming levels; during a first programming phase, conducting a first program operation and a first program-verify operation to a plurality of charge trapping memory cells along a word line, the first program operation programming the plurality of charge trapping memory cells along the word line to first voltage program levels that are less than corresponding predetermined program voltage levels, the first program-verify operation verifying charge trapping memory cells in the plurality of charge trapping memory cells along the word line to first voltage verifying levels that are less than corresponding predetermined program-verify levels; and during a second programming phase, conducting a second programming operation and a second program-verify operation of the plurality of charge trapping memory cells along the word line, the second programming operation programming the plurality of charge trapping memory cells along the word line to second voltage programming levels that are substantially equal to the predetermined program voltage levels, the second program-verify operation verifying the plurality of charge trapping memory cells along the word line to second voltage verifying levels that substantially equal to the predetermined program-verify levels.