9. A circuitry arrangement according to claim 7 wherein said input means is a four-stage shift register and wherein said translating circuitry means is formed such that the word boundary of coded data word entering said input means shift register is defined by signals in the third, second and first stages of said input means shift register.
10. A circuitry arrangement according to claim 9 wherein said output means is a shift register having at least three stages and wherein said translating circuitry means is formed to transfer the bit signal residing in the fourth stage of said input means shift register into the first stage of said output means shift register when said first, second and third stages of said input means shift register each contains a second bit signal.