3. The apparatus of claim 1 , wherein a word line switch transistor region comprising the word line switch transistors is disposed under the word line contact regions.
1. An apparatus comprising: a stack of word line layers comprising word lines for a three-dimensional non-volatile memory array, the stack of word line layers comprising a plurality of tiers; a plurality of word line switch transistors for transferring word line bias voltages to the word lines; a plurality of word line contact regions for coupling the word line switch transistors to the word lines, a word line contact region comprising a stepped structure for a tier of the word line layers, wherein a level region separates a word line contact region for a first tier from a word line contact region for a second tier; and a plurality of connectors coupling the word line switch transistors to the word lines, the connectors comprising vertical conductors, wherein connectors for a single word line contact region comprise vertical conductors disposed within the single word line contact region, at a first side of the single word line contact region, and at a second side of the single word line contact region.