50. A data processing system according to claim 49 further comprising a processor wherein the processor is coupled to the first bus.
54. A data processing system according to claim 50 wherein the memory comprises a plurality of memory devices wherein each one of the plurality of memory devices is coupled to a corresponding one of the plurality of sub-packet of the plurality of second data packets and wherein the corresponding one of the plurality of memory device stores the corresponding one of the plurality of sub-packets.