25. A computer system for verification analysis comprising: a memory which stores instructions; one or more processors coupled to the memory wherein the one or more processors are configured to: obtain a word-level data flow graph and obtain a bit-level data flow graph; search the bit-level data flow graph to find partial-product encoding; remove redundancy from the bit-level data flow graph; check the word-level data flow graph and the bit-level data flow graph for input correspondence; and perform equivalence checking between the bit-level data flow graph and the word-level data flow graph.
26. The system of claim 25 wherein the one or more processors are further configured to generate a reference model based on the word-level data flow graph.