7. An electronic dataset product, comprising an electronically represented design for an integrated circuit stored on an electronic data storage medium and expressed in a hardware description language, said electronically represented design comprising designs for: a static random access memory array; said static random access memory array comprising at least two cores, wherein only one of said at least two cores is written at a time; a tristate driver; and said tristate driver being configured to apply a high impedance state to one of said at least two cores that is not being written, in response to a signal from a logic NOR, wherein said logic NOR receives a first input signal from a write clock and a second input signal based on at least a portion of a write address, wherein said write address is directed to said static random access memory array.
9. The electronic dataset product of claim 7 , wherein: said at least two cores comprise a first core and a second core; said first core is associated with a first state of a most significant bit of said write address; said second core is associated with a second state of said most significant bit of said write address; and said second input signal is driven by said most significant bit of said write address.