44. A data processing system according to claim 40 wherein said memory processor further controls which of the plurality of sub-packets of each of said plurality of first data packets are assembled into each of the plurality of groups.
48. A data processing system according to claim 44 wherein said memory processor is instruction programmable, said instruction having control bits for programmable control such that any predetermined one of the plurality of sub-packets of the plurality of first data packets may be assembled together with any other predetermined one of the plurality of sub-packets of the plurality of fist data packets to form one of the plurality of groups.