19. The method of claim 14 , further comprising: defining an input hardware interface associated with the element of the integrated circuit, the input hardware interface being defined in a high level programming language, and defining an output hardware interface associated with the element of the integrated circuit, the output hardware interface being defined in the high level programming language.
14. A method for designing an integrated circuit using a high-level synthesis (HLS) tool, the method comprising: defining, by a synthesis tool module, a library component based on a first register-transfer level (RTL) configured to define an element of the integrated circuit, replacing, by the synthesis tool module, a portion of a source code corresponding to a first program model with the library component, the source code defining the integrated circuit, and generating, by the synthesis tool module, a second RTL description representing the integrated circuit based on the source code, wherein during the generating of the second RTL description, an output is written to a first memory location in a same clock cycle as reading an input from a second memory location.