5. Apparatus as defined in claim 4 wherein said means for processing the stored segment bits and interval bits further includes a down counter means responsive to said maximum segment value for an initial setting of said down counter means, said down counter means having an enable input which is responsive to means for selectively enabling said shift register means.
4. Apparatus as defined in claim 2 wherein said means for processing the stored segment bits and interval bits includes means for selectively enabling said shift register means.