4. Apparatus as set forth in claim 1 wherein said first extraction means further comprises: a. first register means for providing a word address and a bit address within said word which indicates the machine level operation code in said interpretable language string to be extracted; b. second register means for receiving via said electrical interconnection with said storage device the stored word uniquely identified by said word address; c. third register means connected to said second register means for receiving bits of the stored word from said second register means; d. first control means for controlling shifting of bits from said second register to said third register means;
6. A processor as set forth in claim 4 wherein said first control means further comprises: a. an x register in which 2.sup.x is a maximum number of bits which may be shifted during any one sequential extraction; and b. test for zero logic connected to said x bit register providing a signal to terminate shifting responsive to all x bits being zero.