12. The computer system of claim 8 , wherein said first one of said plurality of address translation techniques and said second one of said plurality of address translation techniques differ in one or more of: a page size, a segment size, and a virtual-to-physical address space mapping.
8. A computer system, comprising: a processor configured to support a plurality of memory virtualization techniques; and a memory configured to communicate with said processor; wherein said processor is further configured to: determine a first one of said plurality of address translation techniques dependent on a predicted distribution of virtual memory locations to be accessed by a first application; translate, on behalf of said first application executing on said processor, a memory request directed to a first virtual memory address to a first physical memory address of said memory according to said first one of said plurality of memory virtualization techniques; during said executing, dynamically select a second one of said plurality of memory virtualization techniques for translating virtual addresses, on behalf of said first application, to corresponding physical addresses of said memory; during said executing and subsequent to said selecting a second one of said plurality of memory virtualization techniques, translate, on behalf of said first application, a second memory request directed to a virtual memory address to a corresponding physical memory address of said memory according to said second one of said plurality of memory virtualization techniques; wherein said dynamically selecting and said translating according to said second one of said plurality of memory virtualization techniques are performed transparently to said first application.