27. In a logic array having an input connected to an AND gate matrix with a read-only-memory addressing mode and a programmable-logic-array addressing mode, an OR gate matrix connected to said AND gate matrix and having an output, and control means for determining the addressing mode of said array, the improvement comprising: latch means at the read-only-memory input to said AND gate array for maintaining an address at said read-only-memory input; and said control means operates said latch means during a test sequence for permitting addressing said AND gate matrix in both modes simultaneously.
29. The logic array according to claim 27 including next address means connected to the output of said OR gates matrix and to the input of said AND gate matrix for providing a next address to said AND gate matrix as a function of the input words, the output of said OR gate matrix, computer status and test words.