5. The circuit of claim 1 in further combination with switchable current supply means for supplying additional current to the second detector transistor, the switchable current supply means being actuated by the binary bits outputted from the amplifier stage such that the efficiency of the input stage is enhanced.
1. A circuit for receiving and responding to digital bit signals, the circuit comprising: an input stage comprising first and second MOS detector transistors each having a gate, a source and a drain with their gates connected in common to the drain of the first transistor, the sources of the transistors being connected respectively to a first rail and to an input terminal for receiving the digital bit signals; first and second MOS transistors connected as controlled current sources respectively to the drains of the first and second detector transistors, a first small capacitor connected between the drain of the first detector transistor and the first rail, a second capacitor connected between the drain of the second detector transistor and the first rail, the voltage across the second capacitor in the absence of an incoming signal being substantially different from the voltage across the first capacitor; and at least one amplifier stage of a p-channel field effect transistor (FET) and an n-channel FET series connected with common gate input and common drain output, the common gate input of the stage being connected in parallel with the second small capacitor, the output of the amplifier stage switching between the first rail and a second rail potential when the voltage across the second capacitor changes sufficiently in response to the microwave signal such that the output of the amplifier stage produces binary "0" and "1" bits in accordance with the signals.