17. The method as set forth in claim 10, wherein, said step (d.4) comprises the steps of: d.4.1) tracing operation of a FSM from start to end; and d.4.2) resuming tracing of operation of a FSM from its current state.
10. In a computer system comprising a formal specification of a logic circuit having at least one finite state machine (FSM) and at least one set of functional vectors for simulating the logic circuit, a method for analyzing and verifying said at least one FSM's design and implementation, said method comprising the steps of: a) generating a gate level specification of said logic circuit in response to said formal specification of said logic circuit; b) generating a state table for each of said at least one FSM in response to said formal specification of said logic circuit; c) simulating and generating simulation results of said at least one FSM in response to said gate level specification of said logic circuit, said at least one state table for said at least one FSM, and said at least one set of functional vectors; and d) generating analysis reports by the following steps: d.1) interpreting user commands; d.2) loading said at least one state table and simulation results for said at least one FSM responsive to said user commands; d.3) storing said loaded at least one state table and said simulation results; and d.4) performing a plurality of reporting and related functions responsive to said user commands.