1. In a digital computer system including arithmetic processor means for performing arithmetic operations on operands, memory means for storing operands and instructions for directing said operations, bus means for conducting operands and instructions between said memory means and said processor means, and I/O means for conducting operands between said digital computer system and devices external to said digital computer system, said arithmetic processor means comprising: arithmetic ALU means for performing arithmetic operations on first certain of said operands expressed in a first format to produce arithmetic results in said first format, input format means comprising input multiplexer means connected from said bus means for receiving second certain of said operands expressed in a second format, and input register means connected from said input multiplexer means and to said inputs of said arithmetic ALU means for (1) extracting first certain information bits from said second certain of said operands, (2) transferring said first certain information bits into first certain information bit positions of said corresponding first certain of said operands and (3) providing said corresponding first certain of said operands to said inputs of said arithmetic ALU means, and output format means comprising output register means connected from said arithmetic ALU means for receiving said arithmetic results expressed in said first format, and output multiplexer means connected from said output register means and to said bus means for transferring second certain information bits of said first certain of said results into second certain information bit positions and providing said results expressed in said second format to said bus means.
2. The digital computer system of claim 1, wherein said output format means further comprises: intermediate register means connected from said output register means and to said inputs of said arithmetic ALU means for storing third certain of said operands expressed in intermediate format wherein said second certain information bits occupy said second certain information bit positions and third certain information bit positions are occupied by blank information bits, constant memory means connected to said inputs of said arithmetic ALU means for providing third certain information bits to be written into said third certain information bit positions of said third certain of said operands expressed in said intermediate format, and said arithmetic ALU means for combining said third certain of said operands from said intermediate register means and said third certain information bits from said constant memory means and providing said corresponding second certain of said operands expressed in said second format.