6. The method of claim 1 wherein the model operates under a time-based model of computation.
1. A computer-implemented method for generating hardware description language (HDL) code, the method comprising: receiving an executable, graphical model having a plurality of blocks including a frame-enabled block that processes frame-based input data, the frame-enabled block implementable in hardware in a plurality of ways, the plurality of ways in which the frame-enabled block is implementable in hardware include: a fully parallelized way that uses a plurality of first parallel hardware components, a fully serialized way that uses a first serial hardware component, and a combination serialized and parallelized way that uses a plurality of second parallel hardware components and a second serial hardware component; receiving a selected preference for influencing a way in which the frame-enabled block is implemented in hardware, where: the selected preference is free from affecting execution of the frame-enabled block in the model, and the selected preference causes the frame-enabled block to be implemented in hardware in a particular way of the plurality of ways; and generating, using a processor of a computer, the HDL code for the frame-enabled block of the model, the generating including implementing the frame-enabled block in hardware in the particular way that satisfies the selected preference, the particular way selected from the group consisting of: the fully parallelized way, in which the plurality of first parallel hardware components are included in the hardware implementation of the frame-enabled block, the fully serialized way, in which the first serial hardware component is included in the hardware implementation of the frame-enabled block, and the combination serialized and parallelized way, in which the second serial hardware component and the plurality of second parallel hardware components are included in the hardware implementation of the frame-enabled block.