1. A system with memory error correction and detection comprising: an error detection and correction (EDC) module configured to receive a code word derived from a plurality of smaller code words that represent a data word of 2 m data bits and a plurality of error correction code bits, wherein the EDC module comprises: segmentation logic coupled receive the code word, the segmentation logic configured to convert the code word into a plurality of smaller code words; syndrome computation logic configured to multiply each of the plurality of smaller code words by a check matrix to form a plurality of syndromes words; a control block coupled to receive and process the plurality of syndrome words to determine a number of errors that exist in each of the plurality of smaller code words; a plurality of equation solver modules coupled to each receive and process a portion of the plurality of syndrome words in parallel with the control block to determine locations of possible errors within the plurality of smaller code words; and an error correction block coupled to receive the number of errors from the control block and the locations of possible errors from the equation solver module, the error correction block being configured to correct up to two errors and to detect up to three errors in the code word.
4. The system of claim 1 , wherein the received code word polynomial has roots at −1, 0 and 1 powers of primitive Galois Field element α.