8. A method for testing an integrated circuit, the method comprising the steps of: a) receiving integrated circuit topology information of the integrated circuit, wherein the integrated circuit has a test architecture which allows the integrated circuit to participate in system-level testing operations, the integrated circuit topology information including test architecture topology information, the integrated circuit topology information being stored as a circuit netlist via computer-readable media; b) obtaining a boundary scan description of the test architecture of the integrated circuit wherein the boundary scan description defines various physical features of the test architecture and is stored via computer readable media; c) generating, based on the boundary scan description, test parameters for use by a logic simulation, wherein the logic simulation is used to test the integrated circuit; d) exercising the integrated circuit via the logic simulation and the monitoring the excerising of the integrated circuit for any occurrence of an error the error being detected based on at least a portion of the test parameters; and e) obtaining an error correction for the error in response to the error being detected.
9. The method of claim 8, wherein the step of (d) comprises monitoring for a definition error in the boundary scan description.