8. A system for assuring a reliability of a chip comprising: a processor configured to: verify a parity; traverse a design netlist back from a plurality of netlist outputs; identify one or more parity protected structures and one or more gates, wherein protected parity structures comprises a duplication protection; and generate a driver based on a logic structure and an assertion indicative of a parity validity.
10. The system of claim 8 wherein the processor is further configured to: retrieve the design netlist; statistically analyze the design netlist; extract checking logic information from the design netlist; extract gating information from the design netlist; and identify a logic structure in the design netlist based on a statistical analysis of the design netlist, the logic information, and gating information.