15. An apparatus according to claim 7, wherein the control unit supplies a byte control signal to the output register to select which of its four bytes is enabled to read the output of the normalisation circuit.
16. An apparatus according to claim 15, wherein the control unit further includes counter means to record a bit position corresponding to a bit currently selected to be read from the input register, and a byte position corresponding to a byte currently selected to be written to in the output register, such that, if the FIFO buffer becomes empty during an instruction being processed, further input data may be read into the FIFO buffer and normalisation resumed on the basis of a status of the counter means.