3. The combination according to claim 2 wherein said data processing system includes a main memory, said combination further comprising: main memory addressing means to receive said memory addresses and fetch data from said main memory.
2. The combination according to claim 1 wherein said forming means includes means for receiving said imperative code in sequential form, determining when an operator does not require a result of a previous operation thus indicating a logical independency and forming strings of said logically dependent operators into logically independent queues.