11. The testing harness of claim 10 , further comprising: a system adapter to adapt the run time system to a system under test.
10. A testing harness comprising: a translator stored in a memory to map Testing and Test Control Notation, Version 3 (TTCN-3) language to a SystemVerilog test bench; a SystemVerilog syntax compiler and a simulator database, including the mapped TTCN-3 language; and a run time system using the SystemVerilog test bench with the simulator database including the mapped TTCN-3 language.