45. A data processing system according to claim 43 wherein said memory processor is instruction programmable, said instruction having control bits for programmable control such that a predetermined number of the plurality of sub-packets of the plurality of first data packets may be assembled together by said formatting means to form one of the plurality of groups.
43. A data processing system according to claim 41 wherein each of the plurality of first data packets comprises a MSB sub-packet and an LSB sub-packet.