4. The processor of claim 3 , wherein the determination logic is also to initiate the second walk through the second set of translation stages using the second address stored in the storage location.
3. The processor of claim 1 , wherein the determination logic is also to, if the particular entry is a transition entry and the transaction is an instruction fetch, replace the first address of the initial data structure for the first set of translation stages stored in the storage location with a second address of an initial data structure for a second set of translation stages.