7. The computer implemented method of claim 1 , the process further comprising: migrating or porting a Verilog-AMS model, which is written in Verilog-AMS language, into the SystemVerilog modeling environment based at least in part upon the set of built-in nettypes; identifying a Verilog-AMS wreal net in the Verilog-AMS model; and coercing the Verilog-AMS wreal net to the at least one wire-real nettype in the SystemVerilog modeling environment.
8. The computer implemented method of claim 7 , the process further comprising: determining whether a port size mismatch exists; determining whether an unsupported wreal concatenation exists; and determining one or more additional requirements based at least in part upon existence of the port size mismatch or of the unsupported wreal concatenation.