15. The system of claim 14 , further comprising: at least one microarchitecture optimization operatively connected with the PUMP, wherein the microarchitecture optimization is selected from a group comprising grouped instruction operation codes, tag compression, tag translation, and miss handler acceleration.
16. The system of claim 15 , further comprising: a tag compression logic utilizing a spatial tag locality to compress tag bits, and after compression transfer the compressed tag bits to and from the off-chip memory.