5. The method of claim 4 , wherein translating the identified portion of the word-level netlist into the bit-level circuit representation further comprises performing bit-blasting operations on the strongly connected component to generate the bit-level circuit representation.
4. The method of claim 1 , wherein identifying the portion of the word-level netlist having the at least one characteristic associated with the combinational loop further comprises computing a strongly connected component in the word-level netlist, the strongly connected component corresponding to the identified portion of the word-level netlist having the at least one characteristic associated with the combinational loop.