23. A computer program product of claim 1 , wherein analyzing data flow through the circuit design based on the deadlock property further comprises: identifying one or more buffers that store payload data; identifying one or more signals that control how data propagates through the one or more buffers; identifying one or more trackers; and generating a waveform that represents propagation of a transaction, the waveform including one or more indicators that when activated generate subsequent helper assertions.
24. The computer program product of claim 23 , wherein analyzing data flow through the circuit design based on the deadlock property further comprises: identifying a first subsystem and a second subsystem as being similar subsystems, the first subsystem being associated with a first helper assertion; generating a second helper assertion corresponding to the first helper assertion and associated with the second subsystem; identifying a first payload and a second payload as being two consecutive steps in the data flow, the first payload or a first tracker being associated with a first helper assertion, the first tracker being related to the first payload; generating a second helper assertion corresponding to the first helper assertion and associated with the second payload or a second tracker, the second tracker being related to the second payload; and checking for an absence of the deadlock condition using the first and the second helper assertions.