13. The computer system of claim 12 , wherein the hardware device is to limit a bit width the Boolean expression input to the Boolean satisfiablility engine.
12. A computer system comprising: a hardware device to identify a path in target source code of a program, wherein the path is a potential sequence of operations carried out when the program is executed, to extract constraints associated with the path, to convert the constraints to a Boolean expression, to process the Boolean expression with a Boolean satisfiability engine to identify either a feasible path or an infeasible path, wherein the infeasible path is a sequence of operations that is never carried out when the program is executed and a feasible path is a sequence of operations that is carried out when the program is executed, and to perform a static analysis of a feasible path to report any bugs in the feasible path and omit static analysis of an infeasible path.