11. The method of claim 9 wherein said logic circuitry operates in synchronism with a clock signal and wherein the step of changing the value of said second portion is performed in response to said clock signal.
9. A method of selectively storing, in a plurality of successive storage locations contained in a data storage device, a plurality of groups of successive data words which are present on logic circuitry of a system under test, each said group comprising at least one particular data word and no more than a predetermined number of data words which precede said particular data word on said logic circuitry, each said storage location having a storage address, said method comprising the steps of: (a) providing predetermined most significant bits to form a first portion of each said address; (b) providing a predetermined number of least significant bits to form a second portion of each said address; (c) changing the value of said second portion in response to the presence of said data words on said data bus; (d) storing successive data words at storage locations having addresses determined according to (a), (b), and (c); and (e) changing the value of said first portion in response to the presence of said particular data word on said data bus.