12. The non-transitory computing device readable media of claim 9 further comprising instructions executable by the computing device to compile the model before generating the HDL code.
9. A non-transitory computing device readable media comprising instructions executable by a computing device to: receive an executable, graphical model having a plurality of blocks including a frame-enabled block configured to process a collection of data samples acquired over a period of time during each execution of the frame-enabled block, the frame-enabled block implementable in hardware in a plurality of ways, the plurality of ways in which the frame-enabled block is implementable in hardware include: a fully parallelized way that uses a plurality of first parallel hardware components, a fully serialized way that uses a first serial hardware component, and a combination serialized and parallelized way that uses a plurality of second parallel hardware components and a second serial hardware component; receive a selected option for a hardware implementation of at least a portion of the received model including the frame-enabled block, the selected option free from affecting execution of the frame-enabled block in the model and to cause the frame-enabled block to be implemented in hardware in a particular way of the plurality of ways; and generate hardware description language (HDL) code for the portion of the model for which the selected option was received, the generated HDL code implementing the frame-enabled block in the particular way that satisfies the selected option, the particular way selected from the group consisting of: the fully parallelized way, in which the plurality of first parallel hardware components are included in the hardware implementation of the frame-enabled block, the fully serialized way, in which the first serial hardware component is included in the hardware implementation of the frame-enabled block, and the combination serialized and parallelized way, in which the second serial hardware component and the plurality of second parallel hardware components are included in the hardware implementation of the frame-enabled block.