14. A word detection circuit for determining a word value, said word detection circuit comprising: a delay element having a data input for receiving a value for a character, a first output adapted for providing a value received on said data input after a first predetermined period of time, a second output adapted for providing a value received on said data input after a second predetermined period of time, a load input coupled to said data input, and a load enable input, wherein asserting said load enable input causes a value on said load input to be provided on said second output; and a comparison circuit having a first input coupled to said data input of said delay element, a second input coupled to said first output of said delay element, and an output coupled to said load enable, said output being adapted for indicated whether a value on said second input of said comparison circuit is less than a predetermined percentage of a value on said first input of said comparison circuit.
16. The word detection circuit of claim 14 further including: a character comparator having a first input coupled to the second output of said delay element for receiving values of characters in a series of characters, a second input, and an output adapted for indicating whether a value on said first input is less than a second predetermined percentage of a value on said second input of said character comparator; a multiplexer having a first input coupled to said first input of said character comparator, a second input, an output, and a select input coupled to said output of said character comparator; and a register having an input coupled to said output of said multiplexer and an output coupled to said second input of said multiplexer and said second input of said character comparator, said output of said register being adapted for providing a value from said input of said register after a predetermined period of time.