19. A method for producing an integrated circuit, the method comprising the steps of: receiving integrated circuit topology information for the integrated circuit from an integrated circuit netlist stored in computer readable memory, wherein the integrated circuit has a boundary scan test architecture, and the integrated circuit topology information includes test architecture topology information; generating a boundary scan description of the test architecture based on the test architecture topology information; selecting a selected test from a predetermined set of test methodologies for testing the test architecture; generating test parameters for a logic simulation based on the boundary scan description and the selected test; testing the test architecture via simulation by utilizing a logic simulation which exercises the integrated circuit netlist based on the test parameters and the integrated circuit topology information; and fabricating the integrated circuit including the test architecture when the step of testing indicates that no errors occurred within the test architecture.
22. The method of claim 19, wherein the step of testing further comprises: while testing the test architecture, detecting an error; obtaining an error correction; and re-testing the test architecture, using the error correction.