1. A method for containing analog verification intellectual property (IP) for circuit simulation, the method comprising: using a computer, reading an analog verification file containing at least one analog verification unit (vunit) that contains properties describing analog circuit design verification requirements including checks for specified simulation results, wherein the analog verification file is separate from input design IP; binding the vunit to one of a top-level circuit, a subcircuit master, and a subcircuit instance during circuit hierarchy expansion, to set vunit scope; performing a circuit simulation with a computer-operated circuit simulation tool combining the input design IP and the analog circuit design verification requirements; and tangibly outputting circuit simulation and verification results.
7. The method of claim 1 wherein the circuit simulation tool, via the vunit, coordinates the input design IP and the analog circuit design verification requirements with no manual netlist editing.