20. The testing apparatus of claim 18 , wherein the mapping comprises one or both of: mapping TTCN-3 files directly into SystemVerilog files and mapping an abstract syntax tree of the TTCN-3 files into an abstract syntax tree of SystemVerilog.
18. A testing apparatus comprising: a Testing and Test Control Notation, Version 3 (TTCN-3) standardized testing language stored in a memory; a SystemVerilog testing harness; a SystemVerilog syntax compiler and a simulator database, including a mapped TTCN-3 standardized testing language; and a testing set-up including the SystemVerilog testing harness with the TTCN-3 standardized testing language, including mapping functions and communications from the TTCN-3 standardized testing language to SystemVerilog format, such that a runtime system using the SystemVerilog testing harness uses the mapped TTCN-3 standardized testing language.