3. The apparatus according to claim 2: wherein the second direct address translating means further comprises first translation buffer storage means, coupled to the first translation buffer, for storing the translation data for the second virtual address from the master translation memory into the first translation buffer.
2. The apparatus according to claim 1, wherein the first direct address translating means further comprises second translation buffer storing means, coupled to the second translation buffer, for storing the translation data for the first virtual address from the master translation memory into the second translation buffer.