19. The memory system of claim 15 , wherein the controller is further configured to: compute a first matrix multiplication of the first data and a matrix to generate a third check code; compute a first matrix multiplication of the second data and the matrix to generate a fourth check code; generate an inversion pattern based on a second matrix multiplication of an initial data comprising erased states and the matrix; selectively invert bits of the third check code based on the inversion pattern to generate the first check code, wherein the inversion pattern comprises a plurality of bits having a first state or a second state, wherein selectively inverting comprises inverting bits of the first check code corresponding to bit positions of the inversion pattern having the first state and not inverting bit positions corresponding to the second state; and selectively invert bits of the fourth check code based on the inversion pattern to generate the second check code.
20. The memory system of claim 19 , wherein the matrix comprises: [ 0010 1011 1111 1110 1011 0010 0001 1101 1110 1000 0100 1111 1101 1011 0111 0111 ] .