3. The method of claim 1 , wherein building the set of timing constraints comprises: making a table lookup to determine a path between a set of source and destination cells; making a table lookup to determine a path between each corresponding pair of source and destination cells in the set of cells; determining a delay for a signal to travel through each determined path from the source cell to the corresponding destination cell; and building a timing constraint to ensure that a required time of the signal at an input of the destination cell is greater than or equal to an arrival time of the signal at an output of the source cell plus the determined delay for the signal to travel through the path between the source and destination cells.
1. A method for placement of a plurality of cells of a user design on an integrated circuit (IC), the method comprising: building a set of timing constraints for placement of the plurality of cells on a plurality of sites on the IC; with a placer, sending the set of timing constraints to a satisfiability solver; with the placer, receiving a placement that satisfies the set of timing constraints for the plurality of cells from the satisfiability solver; and configuring the integrated circuit with configuration data that includes the placement that satisfies the set of timing constraints.