3. A code-converter as defined in claim 2 wherein the memory means is a read-only-memory.
2. A code-converter as defined in claim 1 wherein the code conversion circuit comprises a memory means having a plurality of locations each one having an address corresponding to a respective combination of the input M-bits and each location having a converted data word comprising B-bits plus a secondary parity bit which gives the converted data word a parity value which is the same as that of the input M-bits forming the address for that location.