5. A method for representing analog connectivity in a design written in a hardware description language, comprising: detecting a circuit component that does not have explicit connection path in the design, wherein the circuit component includes a Verilog-AMS out-of-module-reference, a Verilog-AMS defined parameter, and a VHDL-AMS package reference, and wherein the circuit component includes one or more lower-level circuit instances arranged in one or more branches in a hierarchical graph; creating one or more instances of the circuit component having at least one additional port than the circuit component; creating one or more ports in the corresponding one or more instances of the circuit component for providing at least an explicit connection path; representing the design using at least the explicit connection path and the one or more ports of the corresponding one or more instances; creating multiple copies of the circuit component based on the design represented, wherein representations of a lower-level circuit instance vary from one branch to another branch due to out-of-module-reference, automatic inserted connection module, Verilog-AMS defined parameter, VHDL-AMS package reference, VHDL-AMS entity, VHDL-AMS architecture, and VHDL-AMS instance; and simulating the design using the multiple copies of the circuit component.
7. The method of claim 5 , further comprising: optimizing the design by reducing the number of copies of the circuit component.