18. Apparatus according to claim 13, further comprising: a read error detector and fading generator connected to said word flag memory.
13. Apparatus for coding an/or decoding or combining of data words and correction words arriving in a first sequence and arranged in a first ordering into a second sequence with a second ordering, said data words and correction words in said first ordering forming blocks and a block error detection code word is added to each block, comprising: a memory where said words are written in said first ordering and read-out in said second ordering: a computing unit connected to said memory for computing sums of data words and correction words and for comparing said computed sums with preset values; an error detection code computing unit arranged upstream of said memory for computing block error detection code words from arriving data words and comparing the computed code words with inputed existing block error code words; connected downstream of said error detection code computing unit; and said assignment circuit comprising a block flag memory and a word flag memory connected downstream to said block flag memory and whereas the contents of said word flag memory and said block flag memory can be changed independently.