10. The integrated circuit chip according to claim 8 , wherein the global control network circuit further comprises at least one shared signal to perform transition into at least one of a set of said first states or a set of said fourth states and further comprising circuits to couple said shared signal to a set of signals detecting the presence of a set of symbols of said plurality of finite state automata of said at least two or more programmable search engines in said content being searched.
8. The integrated circuit chip according to claim 5 , wherein the row-wise FSA extension architecture further comprises of at least one of each of: a. a global state dependent vector memory circuit to store global state transition controls for enabling transition into a first state within one of said two or more programmable search engines from a second state external to said one of said two or more programmable search engines; b. a global control vector memory circuit to store global out state transition control for enabling transition out of a third state within one of said two or more programmable search engines to a fourth state external to said one of said two or more programmable search engines; c. a global transition logic circuit to couple said global control vector memory circuit and at least one state of one of said two or more programmable search engines to at least one state external to said one of said two or more programmable search engines; and d. a global control network circuit to couple said global transition logic circuit and said global state dependent vector memory circuit to perform transition into said first state or the fourth state of said one of said two or more programmable search engines from said second state or said third state within a second programmable search engine of said two or more programmable search engines.