2. The system of claim 1 , further comprising means for analyzing the HDL implementation to generate a hierarchical implementation of the circuit design, wherein partitioning the circuit design into the public portion and the secret portion is performed at the hierarchical representation level.
1. A system comprising: means for generating a hardware description language (HDL) implementation of a circuit design to be implemented on a programmable logic device (PLD) device; means for partitioning the circuit design into a public portion and a secret portion; means for generating an HDL implementation or a netlist implementation of the public portion without the secret portion included; means for generating an HDL implementation or a netlist implementation of an interface for coupling the public portion and the secret portion; and means for generating a programming file including configuration settings for only the secret portion based on the HDL implementation of the secret portion of the circuit design for use in programming the secret portion of the circuit design into a PLD device.