11. A differential memory device comprising: a plurality of memory locations each one comprising a direct memory cell and a complementary memory cell; circuitry to receive a request of reading a selected data word associated with a selected code word comprising a plurality of logic values stored in at least one selected memory location of the plurality of memory locations with an error correction code; circuitry to reading a differential code word representing a differential version of the selected code word by comparing a state of the direct memory cell with a state of the complementary memory cell of each selected memory location; circuitry to verify the differential code word according to the error correction code; circuitry to set the selected data word according to the differential code word in response to a positive verification of the differential code word; circuitry to read at least one single-ended code word representing a single-ended version of the selected code word by at least one of comparing the state of the direct memory cell of each selected memory location with a direct reference and comparing the state of the complementary memory cell of each selected memory location with a complementary reference; circuitry to verify the single-ended code word according to the error correction code; and circuitry to set the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.
14. The memory device according to claim 11 , wherein the circuitry to set the selected data word according to the single-ended code word comprises circuitry to compare the single-ended code word with the differential code word, and circuitry to enable the setting of the selected data word according to the single-ended code word according to a result of the comparison.