14. The method as set forth in claim 13, wherein, said step (c.1) comprises the steps of: c.1.1) upon start up, loading said at least one state table for said at least one FSM; c.1.2) iteratively generating simulation commands for said simulator, and recording applicable signals generated by said simulator, for each FSM; c.1.3) upon completion of simulation, further generating said simulation results for said at least one FSM based on said recorded applicable signals.
13. The method as set forth in claim 11, wherein, said step (c) comprises the steps of: c.1) generating simulation commands, monitoring simulated signal changes, and generating simulation results for said at least one FSM, in response to said at least one state table for said at least one FSM; and c.2) simulating said logic circuit in response to said simulation commands, said gate level specification of said logic circuit and said at least one set of functional vectors.