19. The system of claim 17 , in which the at least one processor or at least one processor core that is to identify, generate, or modify the standardized power data in the standardized power format with the illegal signal in the mixed-signal electronic design is further to: parse at least a part of the standardized power data in the standardized power format including the illegal signal; maintain one or more pertinent elements of the at least a part of the standardized power data in one or more databases; and evaluate the at least a part of the standardized power data.
17. A system for implementing a mixed-signal electronic design using standardized power data, comprising: at least one processor or at least one processor core that is at least to: identify a mixed-signal electronic design; identify, generate, or modify, with an aid of a standardized power format mechanism including or coupled with the at least one processor, standardized power data in a standardized power format with illegal signal in the mixed-signal electronic design by introducing one or more changes to generate updated standardized power data from the standardized power data; implement the mixed-signal electronic design by using the updated standardized power data including the illegal signal for manufacturing of a mixed signal electronic circuit, wherein the illegal signal is not recognized by a standardized power format framework for the standardized power format and comprises at least one of a power control signal or an expression including an incompatible or illegal signal to implement power intent for the mixed-signal electronic design; and one or more non-transitory computer accessible storage media that are to: store the power data and the mixed-signal electronic design.