11. The method of claim 1 , further comprising: determining a Boolean expression of input toggle conditions for one or more flop gates in the plurality of interconnected gate elements; and wherein the generating clock gating circuits that implement the respective Boolean expression of the observability conditions implements a conjunction of the Boolean expression of the observability condition with the Boolean expression of the input toggle conditions for each gate of the plurality of interconnected gate elements.
12. The method of claim 11 , wherein the Boolean expression of input toggle conditions of each of the one or more flop gates is the non-inverting path sensitization along the feedback path from the flop gate output to the flop gate input.