1. A processing device for executing an instruction sequence, wherein the processing device comprises: a status register arranged to provide a status word, the status word comprises a total of K status flags; a set of valid status words, the set of valid status words is provided in the form of a bit string of length 2**K; and a status flag monitor, the processing device is arranged to update the status word in response to execution of an instruction, the instruction sequence comprises a subsequence of one or more selected instructions, upon execution of one of the selected instructions by the processing device, the processing device is further arranged to trigger a status check by the status flag monitor, the status flag monitor is arranged to: verify whether the updated status word in the status register is in a set of valid status words, the processing device is further arranged to provide the set of valid status words to the status flag monitor; and to assert an alert action if the updated status word is not in the set of valid status words.
6. The processing device of claim 1 , where the instruction sequence comprises one or more non-selected instructions, which are not in the subsequence of selected instructions.