1. A processor-implemented method for an electronic design and verification tool to synthesize a behavioral description of a circuit into a structural description of the circuit, the method comprising: using a processor: facilitating generation of the structural description of the circuit by: parsing the behavioral description of the circuit to identify a first text and/or a second text; defining a path annotation based on the identified first text and/or the identified second text; and annotating a state node with the path annotation; and generating the structural description of the circuit based on the facilitating.
3. The method of claim 1 , wherein the defining the path annotation includes, for each function call: responsive to a determination, by the processor, that a first text is specified, modifying the path annotation to include the first text; and responsive to a determination that a second text is associated with a wait statement, modifying the path annotation to include the second text associated with the wait statement.