4. The circuit of claim 1 , wherein the processor is further configured to detect a deletion of an entry in the second logical portion and invalidate corresponding entries in the second and third caches.
1. A circuit comprising: a first cache configured to store translations between address domains, the first cache including first and second logical portions, the first logical portion configured to store translations between a first address domain and a second address domain, the second logical portion configured to store translations between the second address domain and a third address domain; a second cache configured to store translations between the first address domain and the third address domain based on entries in the first cache; a third cache configured to store tags associated with the translations of the first and second cache; and a processor configured to 1) write an entry to the third cache, the entry including a subset of fields populated from a corresponding translation stored at the second cache, and 2) detect a deleted entry in at least one of the first logical portion and the second logical portion and invalidate corresponding entries in the second and third caches; wherein the processor is further configured, in response to detecting an absence of a matching entry in the second cache, to match the address request against the first cache, the address result corresponding to an entry in the first cache.