17. A computer program product for representing analog connectivity in a design written in a hardware description language, comprising a medium storing executable program code, the computer program product comprising: code for detecting a circuit component that does not have explicit connection path in the design, wherein the circuit component includes a Verilog-AMS out-of-module-reference, a Verilog-AMS defined parameter, and a VHDL-AMS package reference, and wherein the circuit component includes one or more lower-level circuit instances arranged in one or more branches in a hierarchical graph, representations of a lower-level circuit instance vary from one branch to another branch due to out-of-module-reference, automatic inserted connection module, Verilog-AMS defined parameter, VHDL-AMS package reference, VHDL-AMS entity, VHDL-AMS architecture, and VHDL-AMS instance; code for creating one or more instances of the circuit component having at least one additional port than the circuit component; code for creating one or more ports in the corresponding one or more instances of the circuit component for providing at least an explicit connection path; and code for simulating the design using at least the explicit connection path and the one or more ports of the corresponding one or more instances.
19. The computer program product of claim 17 further comprising: code for creating multiple copies of the circuit component, wherein representations of a lower-level circuit instance vary from one branch to another branch due to at least out-of-module-reference, automatic inserted connection module, Verilog-AMS defined parameter, or VHDL-AMS package reference; and code for representing the design using the multiple copies of the circuit component.