3. The computer implemented method of claim 2 , wherein the act of associating the resolution function is performed via a discipline declaration process, via a default setting, via direct declaration, or based at least in part upon connectivity or usage of the wreal in a design.
2. The computer implemented method of claim 1 , the process further comprising: determining a mapping between the plurality of resolution functions and the set of built-in nettypes; resolving multiple real-valued drivers that drive a receiver in the SystemVerilog modeling-environment based at least in part upon the mapping; creating or defining a wreal to be a discrete signal having four states natively in the SystemVerilog modeling environment, wherein the wreal is used to model an analog signal in the SystemVerilog modeling environment; and associating a resolution function of the plurality of resolution functions with the wreal.