46. A data processing system according to claim 45 wherein said memory processor is further programmable such that the plurality of sub-packets of the plurality of first data packets may be assembled together in an order from the MSB sub-packet to the LSB sub-packet.
47. A data processing system according to claim 46 wherein said memory processor is further programmable such that the plurality of sub-packets of the plurality of first data packets may be assembled together in an order from the LSB sub-packet to the MSB sub-packet.