20. A combination as in claim 19, further comprising multiplex means for selectively supplying input information to said micro processor from said memory and from said input data bus.
19. A combination as in claim 13, wherein said stored program controlled central processor includes a micro processor, plural processor output registers for receiving output signals from said micro processor, signal propagation means for coupling the signals stored in one of said registers to said memory operand storing second portion, a device selection register loaded by one of said processor output registers, and means responsive to the stored contents of said device selection register for energizing said selector bus.