19. A stack according to claim 18 wherein the control gates of the (n)th control cell are connected to the control gates of the (n+1)th control cell for inhibiting the control gates of the (n+1)th control cell from providing push and pop signals whenever the control gates of the (n)th control cell provide either push or pop signals.
18. A stack according to claim 17, wherein the control cells are interconnected for communicating the storage state of the corresponding word levels to and from the adjacent control cells; and wherein each (n)th control cell in the array from the top of the stack includes a cell-state flip-flop for providing indication signals indicating the storage state of the (n)th word level; a first control gate connected to the push gate between the (n)th data storage cell and the (n+1)th data storage cell in each linear array of data storage cells for providing a push signal to said push gates in response to indication signals from the cell-state flip-flop of the (n)th control cell indicating that the (n)th word level is full, from the cell-state flip-flop of the (n+1)th control cell indicating that the (n+1)th word level is empty, and from the cell-state flip-flop of the (n-1)th control cell indicating that the (n-1)th word level is full; and a second control gate connected to the pop gate between the (n)th data storage cell and the (n+1)th data storage cell in each linear array of data storage cells for providing a pop signal to said pop gates in response to indication signals from the cell-state flip-flop of the (n)th control cell indicating that the (n)th word level is empty, from the cell-state flip-flop of the (n+1)th control cell indicating that the (n+1)th word level is full, and from the cell-state flip-flop of the (n-1)th control cell indicating that the (n-1)th word level is empty.