1. A method comprising: detecting, by a computing system, a presence of a combinational loop in a word-level netlist representation of a circuit design by identifying a portion of the word-level netlist having at least one characteristic associated with the combinational loop, translating the identified portion of the word-level netlist into a bit-level circuit representation, and utilizing the bit-level circuit representation to determine the identified portion of the word-level netlist includes the combinational loop; and modifying, by the computing system, the word-level netlist corresponding to the detected presence of the combinational loop.
3. The method of claim 1 , wherein modifying the word-level netlist further comprises annotating the word-level netlist to annunciate the presence of the combinational loop included in the identified portion of the word-level netlist.