14. The method of claim 11 , further comprising approximating the Boolean expression of the input toggle conditions of one or more of the plurality of gate elements to decrease complexity of the Boolean expression of the input toggle conditions without decreasing the number of input toggle conditions represented by the Boolean expression.
11. The method of claim 1 , further comprising: determining a Boolean expression of input toggle conditions for one or more flop gates in the plurality of interconnected gate elements; and wherein the generating clock gating circuits that implement the respective Boolean expression of the observability conditions implements a conjunction of the Boolean expression of the observability condition with the Boolean expression of the input toggle conditions for each gate of the plurality of interconnected gate elements.