1. A method for modeling characteristics of a logical circuit block, comprising: receiving input of a first plurality of values corresponding to times at which an output voltage of said logical circuit block reaches selected predetermined fractions of a supply voltage; and generating a second time value for which said output voltage reaches a different predetermined fraction of said supply voltage by multiplying each of said plurality of values by a corresponding one of a set of coefficients that statistically relate said first plurality of input values to said second time value, and summing the multiplied values to produce a resulting time at which said output voltage reaches said different predetermined fraction of said supply voltage.