1. A method of executing a packet of chained instructions in a processor, the method comprising: executing a first instruction selected from the packet of chained instructions to access a first data operand from a first memory at a memory address specified by the first instruction for delivery from the first memory through a first path in a first network to a first output port, wherein the first path in the first network to the first output port is determined according to the first instruction, wherein the first network is a load network that comprises a network of nodes organized in stages according to dimensions of a G×H matrix of elements having connectivity within the stages according to a 1 to N adjacency of connections between the elements in corresponding dimensions of the G×H matrix which includes wrap around adjacent elements, the connectivity within the stages includes connections between nodes in the same position, N a positive odd integer, and G≧N and H≧N; executing a second instruction selected from the packet of chained instructions to receive the first data operand from the first output port, to operate on the received first data operand according to the second instruction, and to generate a result for delivery to a second output port; and executing a third instruction selected from the packet of chained instructions to receive the result from the second output port and to deliver the result from the second output port through a first path in a second network to a second memory, wherein the delivered result is stored in the second memory at a memory address specified by the third instruction and wherein the first path in the second network to the second memory is determined according to information contained in the packet of chained instructions.