1. A microprocessor, comprising: a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource; wherein a first core of the plurality of processing cores is configured to: encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction; and in response to encountering the architectural instruction: provide the value to each of the other of the plurality of processing cores; and update the respective architecturally-visible storage resource of the first core with the value; and wherein each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.