1. An integrated injection logic circuit comprising at least one threshold logic gate having a plurality of weighted logic inputs and a weighted fixed input determining the threshold, said gate comprising first and second transistors connected as a bistable with the collector zone of the first transistor connected to the base zone of the second transistor and the collector zone of the second transistor connected to the base zone of the first transistor, at least one of said first and second transistors having a further collector zone provided with a conductive, output connection, a plurality of current injector structures being present for determining the bias currents supplied to the first and second transistors, the state of said bistable being determined in accordance with the difference in magnitude of total bias current supplied to the first transistor and total bias current supplied to the second transistor, said plurality of current injector structures comprising injector structures associated with the logic inputs and at least one injector structure associated with a fixed input.