1. A processor comprising: a plurality of 64-bit general-purpose registers; a plurality of 128-bit single instruction, multiple data (SIMD) registers; a data cache; an instruction cache; a level 2 (L2) cache coupled to the data cache and coupled to the instruction cache; a branch prediction unit; an instruction translation lookaside buffer (TLB) coupled to the instruction cache; an instruction fetch unit; a decode unit coupled to the instruction fetch unit, the decode unit to decode a plurality of instructions, including a first instruction, the first instruction to indicate a 128-bit operand size, the first instruction having a first field to specify a first 128-bit SIMD source register of the plurality of 128-bit SIMD registers, the first instruction having a second field to specify a 64-bit general-purpose register of the plurality of 64-bit general-purpose registers to store a base address, and the first instruction to indicate a data element width of 64-bits; and an execution unit coupled to the decode unit, coupled to the plurality of 128-bit SIMD registers, and coupled to the plurality of 64-bit general-purpose registers, the execution unit to: store a first structure and a second structure to a memory based on the base address, a first 64-bit data element of the first structure to include a first 64-bit data element of the first 128-bit SIMD source register, which is to include least significant bits of the first 128-bit SIMD source register, a second 64-bit data element of the first structure to include a first 64-bit data element of a second 128-bit SIMD source register, which is to include least significant bits of the second 128-bit SIMD source register, a third 64-bit data element of the first structure to include a first 64-bit data element of a third 128-bit SIMD source register, which is to include least significant bits of the third 128-bit SIMD source register, wherein the first, second, and third 64-bit data elements of the first structure are to be consecutive data elements in the memory, a first 64-bit data element of the second structure to include a second 64-bit data element of the first 128-bit SIMD source register, a second 64-bit data element of the second structure to include a second 64-bit data element of the second 128-bit SIMD source register, and a third 64-bit data element of the second structure to include a second 64-bit data element of the third 128-bit SIMD source register, wherein the first, second, and third 64-bit data elements of the second structure are to be consecutive data elements in the memory.