1. A method of characterizing global routing congestion in an integrated circuit design, comprising: receiving a global routing of the circuit design, the global routing having multiple tiles with global edges and wiring track assignments for the global edges, by executing first instructions in a computer system; computing global edge congestions for the global edges based on wiring track usage, by executing second instructions in the computer system; and constructing at least one histogram of averages of the global edge congestions for varying percentages of worst edge congestion, by executing third instructions in the computer system.