1. A method for estimating the fair cache miss rate of a thread executing on a chip multiprocessor having a plurality of processing cores, the method comprising: identifying a thread for determining the fair cache miss rate of the thread; executing the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates of the respective threads while executing concurrently; computing the fair cache miss rate of the thread based on the relationship between the actual miss rate of the thread and the actual miss rates of the plurality of peer threads; and applying the fair cache miss rate of the thread to a scheduling policy of the chip multiprocessor.