1. A microprocessor integrated circuit comprising: first memory interface means for reading information from a first memory means and for storing information within the first memory means, the first memory means storing at least data and macroinstructions, the first memory interface means comprising a first address bus and a first data bus, the first address bus being coupled at least to the first memory means for supplying addresses thereto; macroinstruction decoding means, coupled to the first data bus, for decoding a macroinstruction read from the first memory means into a corresponding microinstruction or microinstructions, said macroinstruction decoding means including, second memory interface means for interfacing to second memory means that is disposed external to the microprocessor integrated circuit, the second memory means storing microinstructions, the second memory interface means comprising means for converting a macroinstruction read from the first memory means into an address within the second memory means of a corresponding microinstruction; a second address bus for coupling between the converting means and the second memory means for providing an address of a microinstruction to the second memory means; and a second data bus for coupling between the second memory means and the microprocessor integrated circuit for conveying an addressed microinstruction to the microprocessor integrated circuit; condition code register means comprising a plurality of condition bits, the condition code register means being responsive to a content of a condition code field of a microinstruction for selectively setting the plurality of condition bits in accordance with one of a result of an operation that occurs within the microprocessor integrated circuit and a result of an operation that occurs external to the microprocessor integrated circuit; at least one input signal terminal; and means having an input coupled to the at least one input signal terminal and being responsive to a logical state of the at least one input signal terminal and also being responsive to a content of the condition code field of a microinstruction for setting a logical state of at least one of the plurality of condition bits to a state that is a function of the logical state of the input signal terminal, whereby said at least one of the plurality of condition bits is selectively set to a logical state that is a function of a result of an operation that occurs within the microprocessor integrated circuit and a function of a result of an operation that occurs external to the microprocessor integrated circuit, as a function of the content of the condition code field of a microinstruction.