1. In an instruction set architecture, an instruction for performing partial bitwise permutations, the instruction being part of the instruction set architecture and including: an opcode identifying the instruction as a partial permutation instruction; and a permutation operation specification including: a destination specifier identifying a destination register; a partial value source specifier; a destination subset specifier identifying one or more destination bits of the destination register; and a control specifier identifying a source for each of the one or more destination bits identified by the destination subset specifier; wherein the instruction is processed by performing a partial bitwise permutation defined by the permutation operation specification.