1. A multi-thread processor comprising: a plurality of hardware threads for generating a plurality of mutually independent instruction streams, respectively; a scheduler for specifying a hardware thread that is to be performed next among the hardware threads; and a thread waste counter that is provided for each hardware thread in the first group and counts up each time a nondispatchable state occurs when the hardware thread is specified by the thread scheduling, wherein the scheduler performs a thread scheduling of repeating to specify each hardware thread included in a first group among the hardware threads by a number of times set up in advance for the hardware thread and to specify any one of the hardware threads in a second group by a number of times set up in advance for the second group that includes other hardware threads, wherein, when a hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs a rescheduling of respecifying a hardware thread in the second group instead of the hardware thread of the first group that is nondispatchable, wherein an increasing of execution time of each hardware thread in the first group is predetermined to be less than an increasing of execution time of the second group, and wherein, in a case where the hardware thread in the second group is specified by the thread scheduling, when a count value of any one of the thread waste counters is one or more and the hardware thread in the first group corresponding to the thread waste counter is dispatchable, the scheduler further performs a thread restoration scheduling of respecifying the hardware thread instead of a hardware thread specified by the thread scheduling, and the thread waste counter counts down each time the corresponding hardware thread in the first group is specified by the thread restoration scheduling.