1. A processor connected to a different processor via an interconnection network and also connected to a main storage device, the processor comprising: a data cache configured to hold data; a memory directory configured to hold directory information indicating whether or not data stored in the main storage device is held in a data cache of a different processor; a directory cache configured to hold dirty information indicating whether or not the held directory information is the same as the directory information held in the memory directory and local information indicating whether the directory information of the memory directory is indicating that the data stored in the main storage device is not held in a data cache of a different processor when the directory information from the memory directory is registered; and a control circuit configured to make a setting such that the dirty information of the directory cache indicates that the directory information of the directory cache is the same as directory information of the memory directory in a case in which the local information indicates that the directory information of the memory directory is indicating that the data stored in the main storage device is not held in a data cache of a different processor when the directory information of the directory cache is updated to indicate that the data stored in the main storage device is not held in the data cache of the different processor.