1. An electronic device comprising: memory capable of being shared between two processing units; a first processing unit having a first characteristic memory usage rate; and a second processing unit having a second characteristic memory usage rate, wherein the second characteristic memory usage rate is lower than the first characteristic memory usage rate; and wherein the first processing unit and the second processing unit are configured to share at least a portion of the memory and wherein the first processing unit or the second processing unit, or a combination thereof, is configured to maintain internal cache coherence at a first granularity and to maintain cache coherence between the first processing unit and the second processing unit at a second granularity, wherein the first granularity is finer than the second granularity; and wherein the second processing unit is further configured to: generate a page fault exception responsive to the second processing unit requesting access to a memory region owned by the first processing unit; denote the time the page fault exception occurs; halt execution of the second processing unit for a threshold amount of time, dependent upon the denoted time; resume processing of the second processing unit in response to the threshold amount of time elapsing; and transfer ownership of the memory region to the second processing unit.