1. A single-chip multiprocessor for executing programs compiled using a static clock-precise macro-scheduling program such that a compiled source program is a set of consecutive super-wide instructions, comprising: K explicit parallelism architecture processors each of which may decode no more than N operations each clock cycle, wherein the K processors are configured to execute no more than K parallel streams, wherein the K parallel streams are created by partitioning each super-wide instruction into no more than K wide instructions, and wherein each wide instruction contains no more than N operations and belongs to only one parallel stream; and a register exchanger for providing data exchange between the streams at a processor register file or control register level using special exchange processor operations added in wide instructions of specified streams, wherein the exchange processor operations include: “transmit” operations defined between each processor, wherein the “transmit” operations send data from a given internal processor register to respective other processors; and “receive” operations defined for each processor, wherein the “receive” operations read data accepted from the respective other processor and lock the processor from running while transmitted data is absent, wherein K and N are integers, and wherein K is greater than one.