1. A processor comprising: a first core and a second core; and thread remapping logic coupled to the first and second cores to: track hardware thread interrupt equivalence information for a first hardware thread and a second hardware thread via a first table including a plurality of entries each to identify one or more hardware threads capable of handling a given interrupt type; track power state information for the first and second hardware threads, including whether the first or second hardware thread is in a power savings state via a second table including a plurality of entries each to identify a current power state of a given hardware thread; receive an interrupt issued from a device while the first hardware thread is in the power savings state, wherein the interrupt is targeted to the first hardware thread; and responsive to a determination that the first hardware thread is in the power savings state, redirect the interrupt to the second hardware thread when the thread remapping logic determines that the second hardware thread is capable of handling the interrupt.