1. A method of operation of a multi-slice processor, the multi-slice processor including a translation cache, a plurality of execution slices, and a plurality of load/store slices, the method comprising: determining, at a load/store slice, a real address from a cache hit in the translation cache for an effective address for an instruction received at the load/store slice; determining, at the load/store slice, an error condition corresponding to an access of the real address; determining, at the load/store slice, a process type indicating a source of the instruction to be a guest process; and responsive to determining the error condition, initiating, in dependence upon the process type indicating a source of the instruction to be a guest process, an effective address translation corresponding to a cache miss in the translation cache for the effective address for the instruction.