1. An apparatus, for extending address modes within a microprocessor, the apparatus comprising: translation logic, for translating an extended instruction into an associated micro instruction sequence for execution by the microprocessor, wherein said extended instruction comprises: an extended prefix, for specifying an extended address mode for an address calculation corresponding to an operation, wherein said extended address mode cannot be specified by an existing instruction set; and an extended prefix tag, for indicating said extended prefix, wherein said extended prefix tag is an otherwise architecturally specified opcode within said existing instruction set; and extended execution logic, coupled to said translation logic, for receiving said associated micro instruction sequence, and for performing said address calculation to generate an extended address according to said extended address mode.