1. A method for mapping a netlist of an integrated circuit to a design, said method comprising steps of: using chaos algorithm to obtain most favorable places in said design for cells from said netlist; utilizing Kuhn's algorithm to assign each cell of said netlist a cell in a template so that, for said each cell of said netlist, its place in said template is as close as possible to its place obtained by said chaos algorithm; and applying simulating annealing optimization technique to reduce a sum of wire length of said design.