1. A tuning method for a memory device, comprising: operating least two memory ranks sharing input/output lines to generate pulses having a same phase from different DQ and DQS pins; generating a reference DQS pulse having a phase difference of 90 degrees from a latest DQ pulse among DQ pulses of the at least two memory ranks; aligning phases of DQ pulses of the at least two memory ranks by increasing or decreasing DQ delays based on the latest DQ pulse; aligning phases of DQS pulses with the at least two ranks by increasing or decreasing DQS delays based on the reference DQS pulse; and storing increasing or decreasing results of the DQ delay and the DQS delay in a nonvolatile memory.