1. An apparatus comprising: a programming circuit which applies a total number of programming pulses to a solid-state memory cell which transitions the memory cell from a first programming state to a second programming state, wherein the total number of programming pulses is an integer greater than one, and a random number generator circuit comprising a counter which accumulates a programming pulse parameter based on the total number of programming pulses and a buffer which stores the programming pulse parameter, wherein the random number generator circuit generates a random number based on the programming pulse parameter.