1. A memory device comprising: a plurality of bit lines; a plurality of word lines overlying the plurality of bit lines; a plurality of field effect transistors, field effect transistors in the plurality of field effect transistors comprising: a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines; a second terminal overlying the first terminal; a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines, the corresponding word line acting as a gate of the field effect transistor, and wherein the channel region has a top view cross-sectional channel area; a dielectric separating the corresponding word line from the channel region; and a memory plane comprising programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage, wherein the memory plane comprises a plurality of memory patches of programmable resistance memory material, memory patches in the plurality of memory patches having a top view cross-sectional patch area greater than or equal to ten times the top view cross-sectional channel area.