1. A method of scheduling an instruction to a processor having a plurality of memory cache banks, comprising: predicting, utilizing a memory cache bank prediction unit, which of the plurality of memory cache banks is associated with the instruction utilizing at least one of bank history information, control flow information, and load target-address information; and after said predicting, assigning the instruction for execution to one of the plurality of cache memory banks based on the predicted memory cache bank, wherein if a confidence level for a bank prediction is low, the instruction is dispatched to each of the plurality of memory cache banks, and once a proper memory cache bank is known, canceling the instruction in remaining memory cache banks.