1. A circuit comprising: A. a test data input lead, a test data output lead, a test mode select lead, a test clock lead, a wrapper serial input lead, and a wrapper serial output lead; B. test access port controller circuitry having inputs connected to the test mode select and test clock leads and having an instruction register control bus output and a data register control bus output; C. instruction register circuitry having a test data input connected to the test data input lead, control inputs connected to the instruction register control bus, and control outputs; D. an auxiliary test control bus having a shift lead and a capture lead; E. first gating circuitry having inputs connected to the shift lead and the capture lead of the auxiliary test control bus, and having a gated auxiliary test control bus output; F. second gating circuitry having a first input connected to a control output of the instruction register circuitry, a second input connected to the data register control bus output, a third input connected to the gated auxiliary test control bus output, and a gated data register control bus output; and G. data register circuitry having a first input connected to a control output of the instruction register circuitry, a second input connected to the gated data register control bus output, a test data input connected to the test data input lead, a test data output connected to the test data output lead, a wrapper serial input connected to the wrapper serial input lead, and a wrapper serial output connected to the wrapper serial output lead.