1. An apparatus for providing indirect access to very long instruction words (VLIWs) allowing both sequential code, comprising a sequence of short instruction words (SIWs), and parallel operations, in the form of VLIWs, to be encoded efficiently, the apparatus comprising: a short instruction memory (SIM) fetch logic; a short instruction memory (SIM); an instruction decoder; a VLIW instruction memory (VIM); a VLIW memory address unit (VIM AGU); associated VIM address registers; and a VIM address generation mechanism for selecting a VLIW in a VIM by generating a VIM address.