1. A multi-slice processor comprising: a plurality of execution slices, and a load/store superslice, wherein the load/store superslice comprises a set predict array, a first load/store slice, a second load/store slice, and wherein the multi-slice processor is configured to carry out: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array, output for performing the two-target load instruction in parallel with generating output for performing the store instruction, wherein: the logic corresponding to the set predict array comprises less logic than logic required to implement an entire load/store slice; and the first load/store slice comprises a first load/store slice multiplexer, a first formatter, a first data cache directory, a first effective address to real address translation cache, a first load miss queue, a first load reorder queue, a first store reorder queue, and a first data cache, and wherein the second load/store slice comprises a second load/store slice multiplexer, a second formatter, a second data cache directory, a second effective address to real address translation cache, a second load miss queue, a second load reorder queue, a second store reorder queue, and a second data cache.