1. A computer system comprising: a DRAM memory; a reconfigurable logic device having a memory controller coupled to selected inputs and outputs of said DRAM memory; and a data maintenance block collocated with said DRAM memory and coupled to said reconfigurable logic device and self-refresh command inputs of said DRAM memory, said data maintenance block operative to provide stable input levels on said self-refresh command inputs while said reconfigurable logic device is reconfigured.