1. A method of inter-processor communication in a multiprocessor data processing system in which each processor includes internal paths for control and data information and which includes a plurality of common registers which are accessible by any one of the processors through said internal paths at rates commensurate with intra-processor operation and which further includes for each processor a plurality of local registers connected thereto, said method comprising the steps of: (a) organizing said common registers into a plurality of clusters, said registers for holding information indicative of the operational status of software tasks being executed by the processors; (b) restricting the access of each processor to no more than one of said clusters; (c) communicating between different processors permitted to access the same cluster by setting or clearing individual bits of the status information maintained in individual ones of the associated common registers; (d) maintaining in said plurality of local registers connected to each processor a local copy of the status information held in the cluster of common registers to which the respective processor has access; (e) signalling said local registers that the status information held in the cluster of common registers has changed; (f) controlling the issue of a test and set instruction by a processor by testing the status of the selected bit in said local copy and causing said instruction to issue immediately and causing the corresponding bit to be set in said corresponding common register if said bit in said local copy is clear and causing said instruction to hold on issue if said bit is set until the corresponding bit is cleared in the common register and the local registers are signalled of such change.