1. A processor, comprising: a plurality of processing cores; snoop filter logic circuitry coupled to said plurality of processing cores, said snoop filter logic circuitry having translation circuitry and a shadow tag array, said translation logic circuitry to identify a physical address for a cache line in response to receipt at said snoop filter logic circuitry of a snoop request from any one of said processing cores having a virtual address of said cache line, said shadow tag array to identify not only which of any one of said processing cores is caching said cache line, but also, where said cache line is cached in a respective cache of said whichever one of said processing cores is caching said cache line.