1. A plural bit, D-type master/slave up-down counter/shift register with reset, load, and parity check capabilities, comprising: a plurality of data stages; a parity section coupled to the last of said plurality of data stages for enabling said last data stage to act as a parity bit; a control section coupled to each of said plurality of data stages for providing control signals to each of said stages; and a clocking section, coupled to each of said plurality of data stages for providing clock signals thereto, each of said data stages further comprising: an input section; a master/slave latch section responsive to said input section; a buffered output section coupled to said master/slave latch section; and a count control section responsive to the output of said buffered output section for providing count-up and count-down control signals.