1. A method of operating a multiple execution unit processor having an instruction pipeline and a loop cache memory capable of storing N execute packets, wherein N is an integer greater than zero, said method comprising the steps of: providing a loop cache memory for storing N execute packets wherein N is an integer greater than zero; building a software pipelined loop kernel of length n execute packets in said loop cache memory, wherein n is an integer greater than 0 and less than or equal to N; stalling said instruction pipeline; executing at least one iteration of said software pipelined loop kernel by issuing for each iteration said software pipelined loop kernel of n execute packets in said loop cache memory; detecting a loop exit condition; and resuming said instruction pipeline.