1. A multicore processor, comprising: a plurality of cache memories; a plurality of processor cores, each processor core associated with one of the cache memories, the plurality of processor cores configured by the system into at least one group including eight processor cores to maintain coherence among respective cache memories in that group of the processor cores, and with the group of the processor cores having at least two but less than the plurality of processor cores, and with each cache line dynamically managed as either local to the associated processor core or shared among multiple processor cores of the group of processor cores; and wherein each of the processors further include an L2 cache and with L2 cache having L2 cache tags that include an owner/shared field per cache block to maintain a coherence state for the associated cache block when the corresponding processor is a home location for the cache block, with the owner/shared field per cache block being a four bit owner/shared field that either encodes the unique owner of the associated cache block or indicates that the associated cache block is shared by more than one processor core to maintain the coherence state for the associated cache block when the corresponding processor is a home location for the cache block, and with a first one of the bits indicating whether there is a unique writer or whether the block is read shared, and with remaining three bits encoded the unique writer to the block.