1. A computer-readable memory storing a plurality of instructions for causing a processor to perform operations, the plurality of instructions comprising: instructions that cause the processor to determine that multiple portions of a continuous event processing (CEP) query can be executed concurrently relative to an event in an event stream, the instructions comprising: instructions that cause the processor to split the CEP query into a plurality of separate operators; instructions that cause the processor to determine a separate constraint for each operator within the plurality of separate operators; and instructions that cause the processor to determine, based at least in part on the separate constraint for each operator within the plurality of separate operators, whether at least a part of the CEP query can be executed in a concurrent manner; instructions that cause the processor to execute the multiple portions of the CEP query concurrently against a first event received via the event stream in response to determining that at least part of the CEP query can be executed in a concurrent manner; and instructions that cause the processor to merge, into a single shared operator, (a) a first operator that is used by a first CEP query that processes at least the first event in the event stream, and (b) a second operator that is used by a second CEP query that also processes at least the first event in the event stream, in response to determining that the first operator and the second operator both perform a particular type of operation.