1. A computer-implemented method, comprising: reducing an amount of programmable logic needed to implement instructions on programmable logic of an integrated circuit (IC) by: identifying and mapping one or more operationally shareable sub-functions of two or more fixed-point operations, floating-point operations, or a combination thereof, by: processing a kernel description to obtain a representation of the two or more fixed-point operations, floating-point operations, or the combination thereof; analyzing the representation for patterns between the two or more fixed-point operations, floating-point operations, or the combination thereof; wherein the operationally sharable sub-functions comprise a common sub-portion of components between the two or more fixed-point operations, floating-point operations, or combination thereof; and mapping the one or more operationally shareable sub-functions to the two or more fixed-point operations, floating-point operations, or combination thereof, such that the operationally shareable sub-functions are shared between the two or more fixed-point operations, floating-point operations, or the combination thereof, by: determining whether the patterns may be shared based upon mutually exclusive calls of the two or more fixed-point operations, floating-point operations, or the combination thereof; determining whether the patterns may be overclocked when the patterns may not be shared; and implementing a shared overclocked pattern for the two or more fixed-point operations, floating-point operations, or the combination thereof, when the patterns may be overclocked.