1. A memory comprising: a plurality of storage arrays each configured to provide data on a respective plurality of bit lines; an input/output (I/O) unit configured to output via a plurality of data output signal paths, the data received from the plurality of storage arrays; a plurality of isolation units, each coupled to provide a data path between the respective plurality of bit lines of a corresponding respective one of the plurality of storage arrays and the I/O unit when the corresponding respective storage array is operating in a normal operational mode; wherein in response to a given storage array of the plurality of storage arrays being placed in a low-voltage operational mode, the corresponding respective isolation unit is configured to isolate the respective plurality of bit lines from the I/O unit.