1. A method, comprising: extracting state groups of a circuit design by deriving state groups from each logical hierarchy of the circuit design, wherein at each level, available state points are grouped by similarity and stored in a state groups collection alongside grouping terms; generating a state bounds file that bounds locations of the state points in the circuit design, wherein the state bounds file is based on the extracted state groups and the grouping terms stored in the state groups collection; and generating an integrated circuit layout by controlling physical placement of the circuit design using the state bounds file.