1. An apparatus for supporting thread level speculative execution in a computing environment having multiple processing units each adapted for concurrent execution of threads in speculative and non-speculative modes, each processing unit having a cache memory hierarchy of caches operatively connected therewith, the apparatus comprising: a means executing logic for managing said threads, said logic comprising: state buffering logic for tracking speculative accesses between multiple cores executing in a multi-core multithreading system, and logic directed at tracking and establishing a sequence of operations for said speculative threads; a means for detecting speculative thread coherence violations at one or more processors and providing associated notifications; and wherein said thread managing means controls speculative thread activity at said one or more processors in response to said notifications.