1. An apparatus comprising: a processor core having an application; an input/output (I/O) controller hub coupled to the processor core and to provide data network, data storage, and application access for the processing core; and a graphics processor coupled to the I/O controller hub and to implement logic including reception/detection logic to detect an application programming interface (API) call to perform a plurality of transactions, wherein the API call is issued by the application at a first command buffer, wherein the plurality of transactions include a first set of transactions and a second set of transactions; patch phase logic to create a second command buffer and append the second command buffer to the first command buffer, wherein the patch phase logic is further to separate the first set transactions into the second command buffer and the second set of transactions into the first command buffer; and application/execution logic to execute, the first set of transactions via the second command buffer prior to executing the second set of transactions via the first command buffer, and wherein the first set of transactions comprise patch transactions relating to one or more patch processes including compute shading of graphics contents, wherein the second set of transactions comprise submit transactions relating to one or more submit processes including three-dimensional (3D) rendering of graphics contents.