1. A liquid state machine pulse domain neural processor circuit comprising: an asynchronous input filter circuit provided for, at any given time, receiving a series of analog input signals and generating in response a set of time-encoded values that depend on the series of analog input signals received at said given time and before said given time; and an asynchronous trainable readout map circuit for transforming at least a portion of said set of time encoded values into output signals; wherein: said generating a set of time-encoded values that depend on the series of analog input signals received at said given time and before said given time comprises receiving each analog input signal on a distinct input driver input port and outputting a corresponding pulse signal comprising a series of pulses having a predetermined frequency and having a duty cycle that depends on the value of the analog input signal.