1. A computing platform, comprising: a first memory storage device having instructions for an operating system (OS) including OS performance and power management (PPM) components for a PPM interface; a second memory storage device having instructions for a firmware boot program including firmware PPM components for a PPM interface, the OS and firmware PPM instructions, when executed, to establish a PPM interface between the OS and platform hardware; and a memory controller coupled to physical memory, the memory controller to provide the physical memory to the OS and to enable the OS to control power states for one or more nodes of the physical memory through the PPM interface, wherein the PPM interface facilitates the physical memory to be divided into multiple memory nodes, wherein the PPM interface allows the OS to place the multiple memory nodes into different power states, wherein the different power states are characterized by non-zero exit latency for exiting from a power state to an active MPS0 state, wherein the different power states include the active MPS0 state, a less active MPS1 state, and an even less active MPS2 state, wherein the PPM interface is to provide that to transition from the less active MPS1 state to an even less active MPS2 state, a node is to transition from the less active MPS1 state to the active MPS0 state and then to the even less active MPS2 state, wherein the PPM interface is to prevent the node from transitioning from the less active MPS1 state directly to the even less active MPS2 state, by bypassing the active MPS0 state, and wherein the active MPS0 state, the less active MPS1 state, and the even less active MPS2 state represent three respective states of the memory nodes while the computing platform is in a G0 working state.