1. A multi-nary OR logic device for carrying out the multi-nary OR logic operation of k (herein, k is an. integer) binary inputs having the designated bit, respectively, and one binary input, said k binary inputs and one binary input having the designated bits, respectively, comprising: an arithmetic summer for sequentially summing the k binary inputs inputted in bit units, thereby calculating the multi-nary value corresponding to said k binary inputs; and a binary multi-nary OR logic operator for receiving the output of the arithmetic summer and the binary input.