1. A data processing apparatus comprising: execution circuitry to execute a sequence of program instructions; checkpoint circuitry to identify an instance of a predetermined type of instruction in said sequence of program instructions and to store checkpoint information associated with said instance of said predetermined type of instruction, said checkpoint information identifying a state of said data processing apparatus prior to execution of said instance of said predetermined type of instruction, wherein said predetermined type of instruction has an expected long completion latency, and said execution circuitry to perform speculative execution of at least some of said program instructions before they are confirmed to be required to be executed, wherein said data processing apparatus further comprises a pending instruction table to store a sequence of entries indicative of pending instructions for which execution has started but not yet completed and said checkpoint circuitry is responsive to identification of said instance of said predetermined type of instruction to mark said instance of said predetermined type of instruction in said pending instruction table as a branch instruction, and wherein when said execution circuitry does not complete execution of said instance of said predetermined type of instruction due to occurrence of a predetermined event, said data processing apparatus is arranged to reinstate said state of said data processing apparatus with reference to said checkpoint information by treating the expected long completion latency instruction as a mispredicted branch instruction, such that said execution circuitry is configured to recommence execution of said sequence of program instructions at said instance of said predetermined type of instruction.