1. A processing element (PE) structure comprising: at least two processing elements in communication with each other to form a floating point unit (FPU)-processing element, wherein each processing element comprises: each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data; and an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU.