1. A computer program product made by recording, on a recording medium, a data structure used for processing executed by a computer system to analyze the circuit connection structure of a plurality of mutually connected assign cells where one assign statement described in intermediate data obtained by logic synthesis of an HDL-described circuit is associated with one assign cell, the data structure including a plurality of records corresponding one-to-one with the assign cells, wherein each record includes: a data unit for storing a logic depth that indicates the largest number of assign cells aligned on a circuit connection path from an input port of the intermediate data to the assign cell associated with the record; and a pointer for indicating an assign cell to be connected to the assign cell associated with the record.