1. A data processor that includes a multi-stage pipeline for executing a multi-functional instruction at high speed, with said multi-functional instruction for transferring data to a selected plurality of registers in a register set, with each register indicated by a register number, with said instruction including a register list in the form of a bit string of binary digits, each binary digit having either a first bit value or a second bit value and the bit string including a plurality of ordered bit positions holding the binary digits, with each bit position in said bit string corresponding to one of the registers in said register set and when a bit value in a bit position is said first bit value the corresponding register is included in said selected plurality of registers, said data processor comprising: an instruction decoding unit including: a decoding circuit for decoding an operation code field of said multi-functional instruction for loading data to plural registers from a memory area of an external memory and for generating a decoded result from said operation code field, and an encoding circuit, coupled to receive said bit string included in said multi-functional instruction, for successively searching said bit string for bit positions having said first bit value indicating particular registers included in said selected plurality of registers and for successively encoding bit positions having said first bit value as a series of destination register numbers, and each register number indicating one of said particular registers in a series of destination registers which are the transferring destinations of data to be transferred, and for successively outputting a series of control codes, each including said decoded result of said operation code field and at least one of said series of said register numbers; an instruction executing unit which accesses said memory and executes said multi-functional instruction; and an instruction execution control unit, coupled to said instruction decoding unit to receive said series of control codes, which controls said instruction executing unit, in accordance with each of said control codes output from said instruction decoding unit, and, for each received control code, to load data from said memory area to at least one of said destination registers indicated by said control code received from said instruction decoding unit while said encoding unit encodes said other bit positions of said bit string which indicate other destination register numbers in said series of destination register numbers.