1. An apparatus for executing application code having multiple instruction set architectures, the apparatus comprising: one or more processors; physical memory, coupled with the one or more processors, to store application code to be loaded into the physical memory for execution by the one or more processors, including first code compiled according to a first instruction set architecture and second code compiled according a second extended instruction set architecture of the first instruction set architecture; and a runtime environment, to be loaded into the physical memory and operated by the one or more processors, to: insert a switch gate associated with a switch between the first and second instruction set architectures; insert a return gate associated with return from the switch between the first instruction set architecture and the second instruction set architecture; intercept, during execution of the application code, an interaction associated with the first code or the second code; and adapt, during the execution of the application code and using the switch gate, the intercepted interaction to switch from the first instruction set architecture to the second instruction set architecture or from the second instruction set architecture to the first instruction set architecture; wherein the runtime environment is to adapt the intercepted interaction via a conversion of a call from a first application binary interface associated with the first instruction set architecture to a second application binary interface associated with the second instruction set architecture or from the second application binary interface to the first application binary interface, and wherein the runtime environment is to return to the second application binary interface from the first application binary interface or return to the first application binary interface from the second application binary interface.