1. A processor comprising: an execution unit; and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state; responsive to detecting a pre-defined subcode comprised by a first control transfer instruction, remain in the first execution state upon executing the first control transfer instruction, wherein the pre-defined subcode comprises a pre-defined opcode prefix; responsive to failing to detect the pre-defined subcode comprised by a second control transfer instruction, transition into a second execution state upon executing the second control transfer instruction; and raise an execution exception responsive to determining, while in the second execution state, that a next instruction to be executed differs from an ENDBRANCH instruction.