1. A memory controller, comprising: a memory access circuit for reading a hard information of a first code word and a hard information of a second code word; and a low density parity check (LDPC) decoding circuit for decoding the first code word according to the hard information of the first code word, and for comparing a check value generated according to the hard information of the first code word with a decoding indicator; wherein the LDPC decoding circuit determines whether decoding the first code word according the hard information of the first code word is successful according to the check value and the decoding indicator; and when decoding the first code word according the hard information of the first code word is not successful, the LDPC decoding circuit configures the memory access circuit to read a soft information of the first code word and decodes the first code word according to the soft information of the first code word.