1. A processor, comprising: a core including locally-gated circuitry; a decode unit including a first logic to decode a store broadcast instruction of a specified width; a local power gate (LPG) coupled to the locally gated circuitry and including: a second logic to selectively provide power to the locally-gated circuitry; a third logic to activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations; a fourth logic to deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry an execution unit including a fifth logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor.