1. In a pipeline-control-system data-processing apparatus having a main memory for storing an instruction and an operand, an instruction processing unit for decoding the instruction, calculating an operand address and reading out the operand, and an arithmetic unit for processing the instruction under the control of a microprogram and for generating an initial address of the operand, said instruction processing unit comprising: an instruction register for storing the instruction read out from said main memory; a register file, addressed in accordance with register designation data of the instruction, for storing at least one of index address data and base address data; an address register for storing the operand address; a first data selector for receiving the address generated from said address register and data read out from said register file and for selecting one of the address generated from said address register and the data read out from said register file; an increment register for storing increment data calculated by said arithmetic unit; a second data selector for receiving data read out from said increment register and destination field data read out from said instruction register and for selecting one of the data read out from said increment register and the destination field data; decoding means for generating a signal for specifying data to be selected by said first and second data selectors; an adder for receiving the data selected from said first and second data selectors and for calculating an operand address; and a third data selector for receiving the operand address generated from said adder and the initial address generated from said arithmetic unit and for selecting one of the operand addresses and the generated address such that selected data is supplied to said address register.