1. A method of validating a pipelined processor, comprising: receiving a functional description of a processor architecture; creating a graph-theoretic model of the processor architecture using the functional description, wherein the graph-theoretic model comprises a structure graph and a behavior graph; constructing a set of functional fault models for the processor architecture, which model a set of functional faults; and constructing a plurality of test programs, wherein each test program covers a functional fault for the processor architecture.