1. In a reduced instruction set computer (RISC) system, an apparatus for performing a computational operation multiple times, comprising: an instruction memory that stores computer instructions; a program counter coupled to the instruction memory that indicates an instruction to be executed, wherein the instruction directs the operation; a decode and control circuit coupled to the instruction memory and to the program counter that decodes the instruction, including an opcode that indicates that the operation is to be performed a number of times, the decode and control circuit causing the program counter to indicate a next instruction when the operation has been performed the number of times; and a data path within a RISC processor including multiple functional units that operate on data in parallel according to the instruction each time the operation is performed, configured to process multiple parameters for a singal pixel.