1. A method of pre-decoding instructions for execution in a multi-core processing environment, comprising: receiving a first line of instructions for execution by a first processor core; predecoding the first line of instructions with a shared predecoder; sending the predecoded first line of instructions from the shared predecoder to the first processor core for execution; receiving a second line of instructions for execution by a second processor core; predecoding the second line of instructions with the shared predecoder; and sending the predecoded first line of instructions from the shared predecoder to the second processor core for execution.