1. A memory apparatus, comprising: a variable resistive memory cell electrically between a read bit line and a read source line, the variable resistive memory cell is configured to switch between a high resistance state and a low resistance state; a read transistor electrically between the read bit line and the variable resistive memory cell or electrically between the read source line the variable resistive memory cell, the read transistor electrically coupled to a word line; a low resistance state reference variable resistive memory cell electrically between a low resistance state reference bit line and a low resistance state reference source line; a low resistance state reference transistor electrically between the low resistance state reference bit line and the low resistance state reference variable resistive memory cell or electrically between the low resistance state reference source line the low resistance state reference variable resistive memory cell, the low resistance state reference transistor electrically coupled to the word line; a high resistance state reference variable resistive memory cell electrically between a high resistance state reference bit line and a high resistance state reference source line; and a high resistance state reference transistor electrically between the high resistance state reference bit line and the high resistance state reference variable resistive memory cell or electrically between the high resistance state reference source line the high resistance state reference variable resistive memory cell, the high resistance state reference transistor electrically coupled to the word line; wherein the low resistance state reference variable resistive memory cell and the high resistance state reference variable resistive memory cell provide an average voltage reference value when a read current is applied through the low resistance state reference variable resistive memory cell and the high resistance state reference variable resistive memory cell.