1. A processor comprising: an execution unit; a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each respective thread, each thread represented in a respective one of a plurality of sets of thread registers; and a plurality of event sources being hardware resources comprising one or more ports for transferring data between the processor and a device external to the processor, and/or one or more channels of an interconnect system for communicating between one of said plurality of sets of thread registers representing one of said plurality of threads and another set of thread registers representing another thread; wherein the execution unit is configured to execute thread scheduling instructions being instructions of an instruction set of the execution unit which manage said runnable statuses; wherein the thread scheduling instructions of the instruction set include a source event enable instruction, the execution unit being configured to be operated by an opcode of the event enable instruction to send a signal to a specified one of said ports or channels via a direct hardwired connection between the execution unit and the specified port or channel in order to set the specified port or channel to a mode in which it generates a respective event dependent on activity occurring at the specified port or channel, the direct hardwired connection being a connection not via a bus; wherein each of said ports or channels is operable to be associated with one of the plurality of threads and with a specified one of a plurality of different potential code locations; and wherein the thread scheduling instructions also include a wait instruction which sets one of said runnable statuses to suspend the respective thread until an associated one of said ports or channels generates its respective event, such that execution of the respective thread continues from the specified one of the plurality of different potential code locations.