1. Circuitry for carrying out an arithmetic operation requiring a plurality of iterations, said circuitry comprising: N sets of iteration circuitry arranged one after the other so that at least one of said sets of iteration circuitry receives an output from a preceding one of said sets of iteration circuitry, each of said sets of iteration circuitry comprising at least one adder part, wherein a full adder is provided by at least one part in one of said sets of iteration circuitry and a second part in a succeeding one of said sets of iteration circuitry.