1. A programmable logic device comprising: a central processing unit (CPU); on-chip peripheral bus; a programmable interface coupled between the CPU an the on-chip peripheral bus, wherein the programmable interface includes a core designated by a user, the programmable interface comprising an address decoder for accessing devices coupled to the on-chip peripheral bus; and a first device coupled to the on-chip peripheral bus for one of providing information to and receiving information from the CPU via the programmable interface using an address decoded by the address decoder of the programmable interface.