1. A combination of circuits for use in a memory device, comprising: a decode circuit responsive to a first portion of address information for identifying a word to be read or written, said decode circuit further responsive to a second portion of the address information for identifying an order in which one or more portions of said identified word are to be read or written, wherein each of said portions is comprised of a plurality of data bits and wherein for sequential burst mode operation each portion is comprised of a specific group of data bits; an address sequencer for routing at least one bit of the address information; and a sequencer circuit responsive to said address sequencer for ordering said plurality of data bits within each portion of said identified word.