1. A processor, comprising: a cache including a plurality of cache banks; a plurality of processor cores, wherein during a first mode of processor operation, each of said plurality of processor cores is configurable to access any of said plurality of cache banks; and core/bank mapping logic coupled to said plurality of cache banks and said plurality of processor cores; wherein during a second mode of processor operation, said core/bank mapping logic is configured to implement a plurality of virtual processors within said processor; wherein a first one of said plurality of virtual processors includes a first subset of said plurality of processor cores and a first subset of said cache banks; wherein a second one of said plurality of virtual processors includes a second subset of said plurality of processor cores and a second subset of said cache banks; and wherein processor cores and cache banks included in said first virtual processor are distinct from processor cores and cache banks included in said second virtual processor.