1. A method for reducing color conflicts in triple patterned Integrated Circuit (IC) designs, the method comprising: using a computing device to perform actions including: applying a design rule check (DRC) on a proposed IC layout, wherein the DRC applies a set of restrictive design rules (RDRs) in response to the proposed IC layout being a local interconnect (CA) layout, the set of RDRs including: forbidding two opposing pairs of shape line ends from being positioned less than a minimum different color distance apart, wherein the minimum different color distance is a minimum separation between two shapes assigned to different colors; forbidding each shape line from being at less than a mask layer distance from more than two shapes in a particular adjacent row, wherein the mask layer distance is a minimum separation between two shapes assigned to a single color; and forbidding two pairs of opposing ends of each shape line from being at less than the mask layer distance from an adjacent shape; computing a conflict graph for the proposed IC layout in response to one of the IC layout being a metal layer and the set of RDRs being satisfied; determining whether the conflict graph is one of non-colorable, indeterminate, partially colorable, and fully colorable; and partially coloring the IC layout and identifying non-colorable shapes in response to the conflict graph being indeterminate or partially colorable.