1. Circuit for the generation of combinatorial logic variables, formed of multiplexers having multiple data and address inputs and multiple binary input and output states and inverters , said circuit having for each input state defined by a combination of input variables of lowest binary weight, a uniquely defined output state defining at least one output variable, said circuit comprising first means for receiving a plurality of first input variables of lowest binary weight; second means connected to said first means for generating intermediate variables of equal binary weight being a logic function of the input variables of lowest binary weight, and third means connected to said second means including logic combinations having further input variables of higher binary weights to generate said at least one output variable.