1. A cache coherency mechanism in a computer system comprising a processor, a cache and main memory wherein a plurality of addresses in main memory have access to each location in the cache, wherein a process being run by the processor includes a cache coherency instruction which specifies (i) an operation to be executed on the contents of a location in the cache and (ii) an address in main memory, the operation being executed for the contents of the location in the cache which could be filled by an access to said address in main memory, if the running process normally has access to said address in main memory, regardless of whether or not the contents of the specified address in main memory are held at that location in the cache.