1. A method of interfacing a pipeline with two or more interfaces in a hardware processor, the method comprising: providing a single pipeline in a hardware processor, the single pipeline presenting at least two visible units, the single pipeline including replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures; receiving a request from one of a plurality of interfaces at one of the at least two visible units; tagging the request with an identifier based on the one of the at least two visible units that received the request; and processing the request in the single pipeline by propagating the request through the single pipeline through the replicated architecturally visible structures that correspond with the identifier.