1. An instruction fetch unit for a processor, comprising: a first recoder to map an instruction from one instruction format to another instruction format; and a second recoder to map an instruction from one instruction format to another instruction format, the second recoder coupled to the first recoder, wherein the first recoder passes information regarding a first instruction belonging to a first instruction set architecture to the second recoder, and the second recoder recodes a second instruction belonging to the first instruction set architecture using the passed information to form a recoded instruction belonging to a second instruction set architecture.