1. A method for laying out a circuit design, comprising the steps of: obtaining a bipartite graph representing a circuit design in nodes and edges; and processing the bipartite graph to generate a layout file, such processing further including the steps of: selecting a starting point within the bipartite graph to ensure that each edge is visited only once; initiating a constraint greedy walk through the bipartite graph to identify paired NMOS and PMOS chains; and after the first walk is completed, initiating at least one additional walk through the bipartite graph for the remaining graph edges to optimize the remaining chains in the circuit.