1. A servo controller interface for a disk controller, wherein the disk controller includes a servo controller, the servo controller interface comprising: a first interface configured to communicate with a first processor over a first bus in a first frequency domain; a second interface configured to communicate with a second processor over a second bus in a second frequency domain that is different than the first frequency domain; a speed matching first in first out (FIFO) memory module configured to receive first data from the first processor over the first bus via the first interface in the first frequency domain, and receive second data from the second processor over the second bus via the second interface in the second frequency domain; and a pipeline control module configured to select which of the first data and the second data is transmitted to the speed matching FIFO memory module in response to no conflicts existing between the first processor and the second processor, and selectively insert wait cycles during transmission of one of the first data and the second data in response to a conflict existing between the first processor and the second processor.