1. A system comprising: a memory to store an enhancer to identify a branch instruction in a first executing thread, the branch instruction having a miss-prediction rate above a threshold, wherein threads executing on the system have an instruction fetch priority to determine a rate at which instructions belonging to a respective executing thread are retrieved from an instruction cache, and the instruction fetch priority of the first executing thread initially specifies a default rate for fetching instructions; an instruction update unit to modify an operation code (opcode) of the branch instruction of the first executing thread, wherein a modified opcode of a branch instruction indicates an instruction fetch priority for an executing thread; and a processor, including: an instruction decode unit to set a modified instruction fetch priority of the first executing thread based on the modified opcode of the branch instruction, and an instruction fetch unit to retrieve instructions for the first executing thread from the instruction cache at a first rate, the first rate indicated by the modified instruction fetch priority of the first executing thread.