1. A processor comprising: a plurality of cores including a first core and a second core, and a turbo mode logic to increase an operating frequency of the second core if the first core is in an idle state, wherein increasing the operating frequency of the second core is to use available power capacity of the first core resulting from the first core being in the idle state; performance computing logic to calculate performance losses associated with selecting among the plurality of cores for handling an event, wherein calculating a performance loss of said performance losses comprises dividing a processing time for servicing the event by a total runtime to complete a workload being executed by the second core; a first cache coupled to the first core, and coupled to a second cache coupled to the second core, and coupled to a cache coherent bus interconnect; a memory interface logic coupled to the first and second cores; and a bus interface logic coupled to the first and second cores.