1. An apparatus comprising: a processor comprising multiple functional units operative to execute executable instructions that when executed by the multiple functional units cause the multiple functional units to: store variable length code information among a plurality of general purpose registers of the processor; generate decoded variable length code information by decoding the at least one variable length code; and store the decoded variable length code information among the plurality of general purpose registers, wherein the variable length code information is associated with a number of macroblocks, and wherein the executable instructions share the general purpose registers by causing the multiple functional units to share, using the general purpose registers, information used in executing the executable instructions when the multiple functional units generate the decoded variable length code information.