1. A data-directed scrambler for processing digital signals having an unequally-weighted code, comprising: inputs for receiving unequally-weighted bits of an input signal; outputs for supplying N scrambled bits of an output signal; and two or more scrambler columns connected in series between said inputs and said outputs, one or more of said scrambler columns including a swapper cell and a digital fanout, wherein least significant bits in the unequally-weighted code are input to a swapper cell and higher order bits in the unequally-weighted code are input to respective digital fanouts.