1. A processing system for allowing a processor to selectively access at least one of its associated internal storage registers, said system comprising: a bus; a processor having input and output ports coupled to said bus, said processor having at least one internal storage register, said at least one internal storage register having an address within said processor; and means, responsive to a signal indicating that said processor is controlling the bus and to a portion of address data on said bus, for issuing a control signal to give said processor having control of the bus access to said at least one internal storage register, said address data on said bus including bits for identifying said processor and said address within said processor, and said portion of address data on said bus not including said bits for identifying said processor.