1. A method comprising: receiving multiple data input values in parallel at an input tier of a selection circuit; and generating, by a combinatorial gate multiplexer, a delayed version of an output clock signal, wherein the output clock signal is provided to a control input of the combinatorial gate multiplexer, and selecting an output value at an output tier of the selection circuit based in part on the delayed version of the output clock signal, wherein the input tier includes multiple combinatorial gate multiplexers and wherein the output tier includes at least one combinatorial gate multiplexer.