1. A multi-core processor, comprising: a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache comprising a first type of metal tunnel junctions (MTJs) having a first size and associated with a first core of the multi-core processor and tuned according to first attributes; and a second STT-MRAM cache comprising a second type of MTJs having a second size that is greater than the first type of MTJs and associated with a second core of the multi-core processor and tuned according to second attributes, wherein the first attributes are different from the second attributes, at least one other core is associated with the first STT-MRAM cache or the second STT-MRAM cache, and each of the first STT-MRAM cache and the second STT-MRAM cache is configurable as a lower level cache, a mid-level cache or a high level cache.