1. A method for verifying the architectural integrity of a processor under test having a limited instruction set, said method comprising the steps of: (a) providing a test support processor connected to communicate with the processor under test; (b) providing input/output support, including at least the capability for a display terminal, a printer and a disk drive, connected to said test support processor for use in association with said processor under test; (c) providing a minimally sized test control program to read test cases and initialize memory with data for an instruction to be tested, said test control program initializing the registers of said processor under test; (d) providing storage means, connected between said processor under test and said test processor, that is accessible and is to be shared by both of the processors; (e) loading said test control program into said shared memory and loading data sufficient to test one of the instructions of said limited instruction set of said processor under test into said shared memory, said test control program initiating execution of said one of the instructions by initiating execution of said data loaded into said shared memory; (f) passing verification test control to said processor under test to thereby cause execution of said instruction thereof; and thereafter (g) said test control program capturing and storing the results of execution of said instruction in said shared memory for subsequent inspection and comparison to desired results.