1. Cache logic for generating a cache address from a binary input memory address that includes a first binary string of a first sequence of bits of a first predefined length and a second binary string of a second sequence of bits of a second predefined length, the cache logic comprising: a hashing engine configured to generate a third binary string from the first binary string, the third binary string having the second predefined length, and the hashing engine being further configured to form each bit of the third binary string by combining a respective subset of bits of the first binary string by means of a first bitwise operation, wherein the subsets of bits of the first binary string are defined at the hashing engine such that each subset is unique and on average comprises approximately half of the bits of the first binary string; and a combination unit arranged to combine the third binary string with the second binary string by a reversible operation so as to form a binary output string for use as at least part of a cache address in a cache memory.