1. A neural core circuit, comprising: a memory device that maintains neuronal attributes for multiple neurons, wherein the memory device has multiple entries, and each entry maintains neuronal attributes for a corresponding neuron; and a controller that manages the memory device and processes neuronal firing events targeting each neuron; wherein the controller multiplexes computation and control logic for said neurons; and wherein, in response to neuronal firing events targeting one of said neurons, the controller retrieves neuronal attributes for the target neuron from a corresponding entry of the memory device, and integrates said firing events based on the retrieved neuronal attributes to generate a firing event for the target neuron.