1. An apparatus, comprising: at least two processors; at least one memory including computer program code; the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to: store with a shared inter-core communication unit in a multi-core processor, first data produced by a producer processor core, in a first token memory located at a first memory address of a memory address space; connect with the shared inter-core communication unit, the first token memory to a consumer processor core of the multi-core processor, to load the first data from the first token memory into the consumer processor core, in response to a first-type command from the producer processor core; connect with the shared inter-core communication unit, an input token memory located at an input token memory address of the memory address space, to the producer processor core of the multi-core processor, to load input data from the first token memory into the producer processor core, in response to a second-type command from the producer processor core; store with the shared inter-core communication unit, result data produced by the producer processor core from the input data, the result data being the first data stored in the first token memory; and connect with the shared inter-core communication unit, the first token memory to the consumer processor core of the multi-core processor, to load the result data from the first token memory into the consumer processor core, in response to the first-type command from the producer processor core.