1. A method for promoting semiconductor manufacturing yield of a multilayered device, comprising steps of: inspecting a processed layer of the multilayered device to identify defects such that an inspected image with the defects thereon is generated; aligning the inspected image to an original design layout information of the processed layer to determine the locations of the defects in the processed layer; and classifying the defects on the inspected image according to the locations of the defects, patterned geometric features of the original design layout information of the processed layer and patterned geometric features of at least one previous layer and/or at least one next layer of the multilayered device.