1. A memory device comprising: a memory controller having at least a first interface to a main memory and at least a second interface to two or more processing entities, wherein said memory controller is configured to enable said processing entities to access said main memory according to a cache coherency protocol, the cache coherency protocol comprising an in-process state and a committed state; wherein the in-process state indicates that information in the main memory is being updated, and the memory controller is configured to: select between and perform actions of: a). waiting to load the information updated during the in-process state from the main memory to a cache until the committed state indicates that a memory update is complete and the cache may reload information from the main memory, or b). ignoring an update causing the in-process state and loading a previous cache content of the information; wherein at least a portion of said main memory comprises persistent memory; and wherein said memory controller is configured to enable a memory hierarchy including one or more levels of cache memory shared among said two or more processing entities, wherein at least a portion of said one or more levels of cache memory comprise persistent memory.