1. A processor, comprising: a plurality of first memories configured to store virtual address tag bits and physical address tag bits; a plurality of second memories configured to store data bits, each of the second memories corresponding to one of the plurality of first memories; and a third memory configured to store alias way prediction values, wherein data bits are retrieved from a particular second memory specified by an alias way prediction value stored in the third memory, and forwarded to an execution unit when a determination is made that no match exists between selected bits of a virtual address and virtual address tag bits stored in the plurality of first memories at locations indexed by bits of the virtual address.