1. A processor that determines memory ownership on a cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction, comprising: an ownership queue that comprises a plurality of entries; a fetch system that provides cache line data of a plurality of cache lines to a processing front end, wherein for each of said plurality of cache lines, said fetch system determines an ownership index and enters said ownership index and a corresponding cache line address into one of said plurality of entries of said ownership queue; wherein said processing front end translates said cache line data from said plurality of cache lines into a plurality of instructions, includes with each instruction an ownership index of an entry of said ownership queue storing a cache line address that corresponds with cache line data from which said each instruction is derived, issues said instruction for execution, and sets an executing bit of said corresponding entry when said instruction is issued; an execution system that determines a destination address for each store instruction that has been issued; a new destination address comparator that compares each newly determined destination address, when determined by said execution system, with each cache line address of valid entries stored in said ownership queue to determine any matching entries; an executing stale detector that evaluates said executing bit of each said matching entry determined by said new destination address comparator, and when any executing bit of any matching entry is set, causes a store instruction that corresponds with said determined destination address to be marked to invoke an executing exception; and wherein said execution system performs said executing exception when a store instruction that is ready to retire is marked to invoke said executing exception.