1. A method comprising: providing a first integrated circuit design netlist; mapping groupings of components within the first integrated circuit netlist as corresponding to one or more cells in a first library of cells, stored on a computer-readable medium; removing from the mapping at least one grouping of components to a first cell, wherein the mapping will not include any first cell mappings; and generating a second library comprising only the cells identified in the mapping, wherein the second library does not include any first cell mappings and is stored on a computer-readable medium.