1. A computer comprising: a segmented read/write memory having a separate segment corresponding to each discrete level of secure data to be processed; an I/O processor having access to said segmented read/write memory; a segmented instruction memory unalterable by said computer having a separate segment corresponding to each discrete level of secure data to be processed; a programmable processor element having an interface to said I/O processor only for the exchange of command and status signals; and means responsively coupled to said segmented instruction memory, said segmented read/write memory and said programmable processor element for restricting the access of said programmable processor element to writing in only said separate segment of said segmented read/write memory corresponding to said discrete level of secure data being processed and to reading from only said separate segments of said segmented read/write memory corresponding to said discrete level of secure data being processed or lower levels.