1. A method for coordinating source data for an instruction in a processor, comprising the steps of: receiving the instruction comprising at least one logical register source, and generating a physical register source by renaming the logical register source, such that the physical register source specifies a physical register or a committed state register; reading a speculative result data value and a speculative source valid flag from the physical register if the physical register source specifies the physical register, the speculative source valid flag indicating whether the speculative source data value is valid; reading a committed result data value from the committed state register if physical register source specifies the committed state register; storing the speculative result data value into a dispatch buffer and storing the speculative source valid flag into a valid flag in the dispatch buffer if the physical register source specifies the physical register; storing the committed result data value into the dispatch buffer and storing a committed source valid flag indicating that the committed result data value is valid into the valid flag of the dispatch buffer if the physical register source specifies the committed state register; scheduling execution of the instruction according to the valid flag in the dispatch buffer.