1. A processor, comprising: an execution unit configured to execute instructions; and an instruction fetch buffer configured to store instructions for execution by the execution unit, the instruction fetch buffer comprising: a loop buffer configured to store instructions of an instruction loop for execution by the execution unit, the loop buffer comprising buffer control logic configured to: predecode a loop jump instruction; identify loop start and loop end instructions using the predecoded loop jump instruction and pointers; and control non-sequential instruction execution of the instruction loop using the pointers; wherein width of the pointers is determined by loop buffer length and is less than a width of an address bus for fetching the instructions stored in the loop buffer from an instruction memory.