1. A Nonvolatile SRAM (NVSRAM) cell with marginal threshold level detection, the NVSRAM cell comprising: a SRAM cell comprising a first inverter having a first output node and a second inverter having a second output node, the first output node and the second output node being coupled to a first word line and two bit lines respectively via a first access transistor and a second access transistor, the first inverter and the second inverter being respectively associated with a first current and a second current sharing a common power line configured to add an adjustable resistor; a first Flash cell comprising a first string having at least a first flash transistor sandwiched by a first select transistor and a second select transistor connected in series from a first drain terminal to a first source terminal, and comprising a second string having a second flash transistor sandwiched by a third select transistor and a fourth select transistor connected in series from a second drain terminal to a second source terminal, the first select transistor and the third select transistor being commonly gated by a first select control signal, the second select transistor and the fourth select transistor being commonly gated by a second select control signal, the first flash transistor and the second flash transistor having their gates commonly coupled to a second word line signal to control a third current through the first string from the first drain terminal to the first source terminal and a fourth current through the second string from the second drain terminal to the second source terminal, the first source terminal and the second source terminal being respectively coupled to a first source line and a second source line; wherein the first drain terminal and the second drain terminal of the first Flash cell are coupled to either the first output node or the second output node of the SRAM cell to form a differential amplifier having one paired driver device made by the first string and the second string of the first Flash cell and one paired load device made by the first inverter and the second inverter of the SRAM cell, the second word line being configured to provide one paired input of the differential amplifier for yielding one paired output respectively to the first output node and the second output node, the adjustable resistor being configured to be substantially larger than an effective resistance of either the first string or the second string for providing a greater than 3:1 ratio between a largest one of the third current and the fourth current over a largest one of the first current and the second current when writing a first logic state associated with a combination of two threshold levels of the first flash transistor and the second flash transistor into a second logic state associated with a combination of either a VSS=0V or a low-voltage VDD level at the first output node and the second output node.