1. In a microprocessor including an address bus coupled to an address output circuit and a data bus coupled to a data input-output circuit, said microprocessor being suitable for executing a plurality of instructions stored in a memory in accordance with a plurality of machine cycles, each of said instructions including an operational code, circuitry comprising: program register storage means coupled between said address bus and said data bus for storing an address of an operational code of a first instruction during a first machine cycle; said program register storage means including first means for transferring said address of said operational code to said address bus during said first machine cycle; incrementor means coupled between said address bus and said data bus for receiving an address from said data bus or said address bus in response to one of said instructions; said incrementor means including second means for transferring said address to said address bus during said first machine cycle in response to one of said instructions; said incrementor means also including third means for incrementing said address during said first machine cycle; said incrementor means also including fourth means for transferring said incremented address into said program register storage means during a second machine cycle; transfer bus means coupled between said program register storage means and said incrementor means for effecting said transfer of said incremented address; and control and timing circuitry coupled to said program register means and said incrementor means for effecting said first and second machine cycles.