1. A processor comprising: a first processor core to be placed in a low power mode, in which at least modified information stored within the first processor core's local cache is to be stored in a shared cache prior to entering the low power mode; a second processor core to initiate a snoop to the first processor core to access information stored within the first processor core's local cache; and logic of the first processor core including a memory to store a power state of the first processor core and to direct the snoop for information stored within the first processor core's local cache to either the first processor core's local cache or to the shared cache depending upon a power state of the first processor core at a given time, wherein the logic is to direct the snoop to the first processor core's local cache when the first processor core is active and to the shared cache when the first processor core is in the low power mode.