1. A method of scan chain diagnosis, executed by at least one processor of a computer, comprising: receiving faulty scan chain information of an integrated circuit, the faulty scan chain information including information identifying one or more faulty scan chains and fault models associated with the one or more faulty scan chains; masking scan patterns based on the faulty scan chain information to filter out loading-caused failures, the scan patterns being applied to the integrated circuit; simulating the masked scan patterns to determine failing probability information for cells on one of the one or more faulty scan chains; and determining defective cell information based on the failing probability information.