1. A method for increasing the manufacturing yield of a programmable logic device (PLD) integrated circuit comprising: configuring the PLD in a first section and a second section, each section having independent power and input/output (I/O) connections; testing the PLD in the first section and the second section to identify defects and characterize each section as at least one of a functional section and a non-functional section; sorting the PLD in accordance with the functional and non-functional test results; and assigning a code to the PLD corresponding to the functional and non-functional test results.