1. A device, comprising: a plurality of processors, wherein each of the plurality of processors comprises a chip select pin adapted to receive a chip select signal determined based on address signals received from a first portion of an address bus and a universal select pin adapted to receive a universal select signal based on a second address signal received from a second portion of the address bus, wherein the chip select signal is one of a plurality of chip select signals, each of which being adapted to activate a respective one of the plurality of processors, and the universal select signal is adapted to activate the plurality of processors concurrently.