1. A method of clock-gating for multicycle instructions, the method comprising: enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks, wherein the enabling is based on a combination of a valid signal and an MC running signal; computing a precise enable computation value in a pipeline domain after a plurality of cycles of executing an instruction; determining that no instructions correspond to the subset of MC logic blocks, disabling one or more of the subset of MC logic blocks based on the precise enable computation value, wherein the precise enable computation value includes a decoded instruction, identification of a type, and a location of the decoded instruction, wherein at least the subset of pipeline logic blocks needed to compute the instruction remain on; and holding the plurality of logic blocks enabled for the plurality of cycles needed to compute the precise enable computation value using at least a control latch and an OR gate, wherein the OR gate receives both the valid bit and an MC running signal from the control latch, wherein the OR gate and the pipeline clock domain simultaneously receive the valid bit, wherein the control latch receives the precise enable computation value.