1. An apparatus, comprising: a first register file comprising a plurality of registers; caching circuitry configured to store information that indicates threads that correspond to data stored in registers of the plurality of registers; and a memory, wherein the apparatus is configured to use first and second backing memory regions in the memory for respective first and second threads; wherein the apparatus is configured to store, at a point in time at which a first register of the plurality of registers includes first valid data corresponding to a first thread, second valid data corresponding to a second thread in a second register of the plurality of registers; and wherein the apparatus is configured to, based on information stored in the caching circuitry, store the second valid data in the second backing memory region in response to an access of the second register by the first thread; and wherein the apparatus is configured to: migrate the first thread from a first processor core that includes the first register file for execution on a second, different processor core that includes a second register file; maintain the first valid data in the first register while executing at least a portion of the first thread on the second processor core; and access the first valid data in the first register file after migrating the first thread back to the first processor core.