1. An apparatus, comprising: a memory device configured to store a data record identifying information corresponding to memory cells in the memory device having relatively weak data retention characteristics; and a memory controller, the memory controller including: an address generating circuit configured to sequentially output addresses; an address comparator configured to stored addresses corresponding to memory cells in the memory device having relatively low retention times, the address comparator coupled to the address generating circuit to receive each of the addresses from the address generating circuit, the address comparator configured to invert at least one of the bits of the address received, from the address generating circuit to provide respective comparison addresses, the address comparator further configured to compare the comparison addresses to the stored addresses and to generate an indicating signal responsive to a match between one of the comparison addresses and one of the stored addresses, and a memory control state machine coupled to receive the indicating signal from the address comparator, the memory control state machine being configured to output the stored address that matches the comparison address, the memory control state machine further being configured to output a refresh command signal responsive to the indicating signal.