1. A microprocessor on a chip comprising: a plurality of arithmetic units; a register file comprising a plurality of data registers communicatively connected to the plurality of arithmetic units; and an instruction fetcher and instruction decoder supplying instructions of one or more software threads to the plurality of arithmetic units; wherein the microprocessor is capable of executing the one or more software threads in at least one mode of a plurality of modes, the plurality of modes including: i) the arithmetic units are operating jointly on one of the one or more software threads using a single program pointer; and ii) a plurality of groups of arithmetic units are operating on different software threads of the one or more software threads using a plurality of program pointers, each group of arithmetic units having one of the plurality of program pointers dedicated to that group of arithmetic units; wherein the microprocessor further comprises a plurality of instruction decode units supplying instructions to the plurality of arithmetic units according to the single program pointer or the plurality of program pointers.