1. A reconfigurable processing apparatus, comprising: a plurality of clusters, each cluster comprising an operation unit group with a plurality of operation units, a configuration memory, and a sequencer for controlling an instruction of each of the operation units and a connection of the operation unit group; at least one shared functional unit, each said at least one shared functional unit being provided independently from the clusters and being an application specific engine for carrying out a unique operation in order to improve operation efficiency, and including: an input unit having a plurality of input ports for accepting input data transmitted from the clusters and an input valid signal corresponding to the input data and indicating that each of the input data is valid, a functional unit for carrying out an operation processing based on the input data and the input valid signal, and for generating output data and an output valid signal as an operational result, and an output unit having a plurality of output ports for transmitting the output data and the output valid signal generated at the functional unit to the clusters; and an inter-cluster network for connecting the input ports and the output ports of the clusters and the shared functional units, wherein the at least one shared functional unit carries out the operation processing by utilizing a pipeline configuration, and the pipeline executes a fixed operation processing, wherein the functional unit includes an input data transform processing stage, an operation processing stage, and an output data transform processing stage, wherein when the functional unit is configured to functions as a divider, a two's complement processing is carried out in the input data transform processing stage, a division pipeline is carried out in the operation processing stage, and a two's complement processing is carried out in the output data transform processing stage, wherein when the functional unit functions as a sin and cos functional unit, a processing for transforming a value of input data into a value from 0 to n/2 is carried out in the input data transform processing stage, a sin/cos processing is performed in the operation processing stage, and a processing for returning to an original quadrant is carried out in the output data transform processing stage, wherein when the functional unit functions as an arctangent functional unit, a data rounding processing is carried out in the input data transform processing stage, an arctangent processing is carried out in the operation processing stage, and a n/4 transform processing is carried out in the output data transform processing stage, and wherein when the functional unit functions as a square root functional unit, a processing for determining an input divisor is carried out in the input data transform processing stage, a division processing is carried out in the operation processing stage, and a processing for determining a square root from a quotient and a divisor is carried out in the output data transform processing stage.