1. A video decoding apparatus, comprising: a first memory to store first data associated with a reference picture received in a bitstream; a second memory to store second data indicative of a plurality of requests to read the first data, each request associated with a motion vector received in the bitstream; and a memory access circuit to: process the second data by performing at least one of: consolidating two or more of the read requests that are associated with a same portion of the first data; or ordering the read requests based on a width of a portion of the first data associated with each of the read requests; and perform one or more direct memory access (DMA) transfers of one or more portions of the first data stored in the first memory across a data bus coupled to the first memory, the one or more DMA transfers based on the processed second data.