1. A method for evaluating a probability of memory access conflict of bus masters while a program expressed in a simulation model is in operation, in a system in which the bus masters including a processor, an accelerator, and a controller can access a memory, the method comprising the steps of: measuring, for the simulation model, an execution time and a number of memory accesses for each simulation step for each of the different bus masters or preparing measurement values in advance; calculating an utilization factor of a memory bandwidth for each of the different bus masters using the values of the execution time and the number of memory accesses; and calculating the probability of memory access conflict among the different bus masters using a formula including the product of the utilization factors of the memory bandwidths of the different bus masters.