1. In a data processor including an instruction decoder (12) and a floating point unit (22) connected together by a microinstruction bus (29) which carries a current microinstruction generated by said decoder in the course of the decoding of a macroinstruction by said decoder, said macroinstruction including a source address field, a destination address field, and an opcode field, said opcode field including first means (LL0, LL1) specifying the precision of arithmetic operations specified by said macroinstruction, the improvement characterized by: said microinstruction generated by said instruction decoder (12) including second means (opcode 1) for indicating that the address range of said source or destination address in said macroinstruction includes the address of a floating point register (44) in said floating point unit 22; and, third means (73, 75) responsive to said second means (opcode 1) for modifying said first means (LL0, LL1) to specify extended precision.