1. An equalizer to equalize an analog signal responsive to previously resolved bits of the analog signal, the equalizer comprising: storage to store N of the previously resolved bits; an analog-to-digital converter (ADC) to sample the analog signal during a given symbol time to produce M speculative samples; and select logic to select one of the M speculative samples as a presently resolved bit, the select logic including: a programmable switch having M switch inputs to receive respective ones of the M speculative samples, and 2^N switch outputs to convey the speculative samples; and a multiplexer having 2^N multiplexer inputs coupled to respective ones of the 2^N switch outputs, a multiplexer output coupled to the storage, and N select inputs coupled to the storage to receive the N previously resolved bits; the select logic to decode all of the N previously resolved bits and select the presently resolved bit from among the M speculative samples responsive to the decoded N previously resolved bits, wherein M is less than 2^N.