1. A processor, comprising: a first and second processor core, each having a plurality of pipelined execution units for executing an issue group of multiple instructions; and scheduling logic configured to issue a first issue group of instructions to the first processor core for execution and a second issue group of instructions to the second processor core for execution when the processor is in a first mode of operation and configured to issue one or more vector instructions for concurrent execution on the first and second processor cores when the processor is in a second mode of operation.