1. A method of modeling asynchronous behavior of a circuit stored as a netlist in a computer system, comprising: identifying at least one driving element in the stored netlist for the circuit wherein the driving element has an output which is connected to downstream logic; and modifying the stored netlist by inserting additional logic whose output is based on a combination of a present output from the driving element, a delayed output from the driving element, and a random value, to drive the downstream logic.