1. A computer-implemented method for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout, the method comprising: mapping, by using a computer, a plurality of violations of the integrated circuit design layout to a graph; partitioning the graph into a plurality of sub-graphs, wherein each of the plurality of sub-graphs include a plurality of edges and a plurality of nodes, wherein at least one set of the plurality of nodes are collapsible into a single node to enable more accurate inspection of an individual loop; detecting a plurality of odd loops in each of the plurality of sub-graphs; and visualizing the plurality of odd loops in both at least one of the plurality of sub-graphs and a corresponding integrated circuit design layout.