1. A microprocessor coupled to a system memory, the microprocessor comprising: a load request signal, for requesting data be loaded from the system memory into the microprocessor in response to a load instruction, said load request signal including a load virtual page address; a prefetch request signal, for requesting a cache line be prefetched from the system memory into the microprocessor in response to a prefetch instruction, said prefetch request signal including a prefetch virtual page address; and a memory subsystem, comprising: a first translation look-aside buffer (TLB), coupled to said load request signal, for translating said load virtual page address into a load physical page address; a second TLB, coupled to said prefetch request signal, for translating said prefetch virtual page address into a prefetch physical page address; and a third TLB, coupled to said load request signal, for translating said load virtual page address into said load physical page address if said load virtual page address misses in said first TLB, and coupled to said prefetch request signal, for translating said prefetch virtual page address into said prefetch physical page address if said prefetch virtual page address misses in said second TLB.