1. A radar signal processor, having an FFT circuit for processing receiver signal data, said data including a plurality of information-bearing range gates, said FFT circuit disposed for applying one of a plurality of weighting functions to a respective individual range gate, said FFT circuit thereby producing an output signal generally resulting in amplitude difference between various respective individual range gates, said radar signal processor comprising: an input buffer for determining the magnitude of each of said range gates, wherein said input buffer makes an input buffer magnitude determination in the form of a maximum amplitude for each said range gate over a discrete period using a magnitude detector and a Log.sub.2 computer computing the Log.sub.2 of such detected vector magnitude for each said range gate, said input buffer including a Log.sub.2 interim maximum amplitude memory and a comparator, said comparator and said Log.sub.2 memory cooperating to determine a largest Log.sub.2 value per range gate per discrete period, a weighting function selecting circuit connected between said input buffer and said FFT circuit, responsive to said input buffer magnitude determination, said weighting function selecting circuit selecting a weighting function to be applied to each said respective individual range gate, and a normalization circuit connected with and receiving the output signal of said FFT circuit, said normalization circuit normalizing amplitude differences in the output signal of said FFT circuit.