1. A method for controlling cycle-by-cycle interleaving of instructions between a number of instruction threads in a simultaneous multithreading processor, the method including the steps of: (a) generating a base thread selection signal based at least partially on an instruction interleave enforcement rule, the base thread selection signal indicating a first instruction thread for processing from among the number of instruction threads; (b) generating a final thread selection signal based upon the base thread selection signal and based upon a feedback signal associated with one of the instruction threads included in the number of instruction threads, the final thread selection signal indicating a particular instruction thread included in the number of instruction threads; and (c) applying the final thread selection signal in the selection of one of the number of instruction threads for interleaving an instruction into an interleaved stream of instructions.