1. An apparatus comprising: a processor having a pipeline; and a circuit configured to (i) detect a first write instruction in said pipeline that writes to a resource, (ii) stall a read instruction in said pipeline where (a) a first read-after-write conflict exists between said first write instruction and said read instruction and (b) no other write instruction to said resource is scheduled between said first write instruction and said read instruction and (iii) not stall said read instruction where (a) said first read-after-write conflict exists and (b) a second write instruction to said resource is scheduled between said first write instruction and said read instruction.