1. An apparatus for processing data, said apparatus comprising: a physical set of hardware registers; an instruction pipeline for concurrently processing a plurality of program instructions; register renaming circuitry for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set; prediction circuitry comprising a branch predictor responsive to a conditional branch instruction of said instruction set to be subject to mapping by said register renaming circuitry to generate a prediction for said conditional branch instruction as one of: (i) an executed prediction being a prediction that said conditional branch instruction will be executed and result in a taken branch; (ii) a not-executed prediction being a prediction that said conditional branch instruction will not be executed and will result in a not taken branch, said conditional branch instruction being processed by said instruction pipeline regardless of whether said executed prediction or said not-executed prediction is generated by said branch predictor; renaming control circuitry responsive to said not-executed prediction for said conditional branch instruction to suppress said register renaming circuitry performing a mapping for a register specified by said conditional branch instruction being processed by said instruction pipeline; prediction resolving circuitry responsive to an execution outcome for said conditional branch instruction to determine if said prediction is correct or is incorrect; and recovery circuitry responsive to said not-executed prediction for said conditional branch instruction being incorrect to control said register renaming circuitry to perform said mapping for said conditional branch instruction and to reverse any incorrect changes of architectural state consequent upon said not-executed prediction for said conditional branch instruction being incorrect.