1. A semiconductor device comprising: mode memory to store information indicative of one of a plurality of modes, each mode of the plurality of modes corresponding to a different interconnect topology; one or more request interfaces operable to receive requests to memory; one or more response interfaces operable to send responses to the requests to the memory; and a first fabric coupled to the one or more request interfaces and one or more response interfaces and operable in the plurality of modes, the fabric comprising: ordering and coherency logic coupled to the mode memory to control processing of read and write requests to the memory received by the first fabric according to one mode of the plurality of modes identified by the information indicative stored in the mode memory, and wherein the ordering and coherency logic is operable to control timing of the requests on the memory from the one or more request interfaces and timing of the responses on the one or more response interfaces to the requests.