1. A method for fault isolation in semiconductors with devices thereon comprising: determining test data from a plurality of semiconductor devices by testing said plurality of semiconductor devices; identifying test failure data from said test data, said test failure data corresponding to defects of said plurality of semiconductor devices; and creating a failure bitmap in a vector graphic computer-aided design (CAD) format, said failure bitmap including locations of said defects, said failure bitmap further including said test failure data; said locations of said defects and said test failure data stored in said vector graphic CAD format.