1. A data processing apparatus comprising: a single instruction multiple data (SIMD) array of processing elements, each of which includes an internal memory unit, the processing elements being divided into a plurality of processing blocks, wherein the processing blocks are operable to process respective groups of data items; an array controller operable to receive instructions from a plurality of instruction streams, and to transfer instructions from said instruction streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads in parallel with one another; and a channel controller operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array, wherein the channel controller is operable to control access to the memory external to the array using external memory location information supplied by each of the processing elements in the array, the supplied external memory location information associated with an external memory location, the supplied external memory location information from a selected processing element in the array being transmitted to each of a plurality of non-selected processing elements, wherein each of the plurality of non-selected processing elements also requiring access to the external memory location registers a transaction identifier associated with a memory access to the external memory location and wherein the channel controller is operable to optimize data transfer operations to remove multiple accesses to the external memory location when a plurality of processing elements requires access to the external memory location by using corresponding transaction identifiers and wherein using corresponding transaction identifiers comprises at least one of the plurality of non-selected processing elements comparing a registered transaction identifier with incoming transaction identifiers for recovering data.