1. A cache memory system, comprising: a plurality of control sections, wherein each of the plurality of control sections includes a cache unit; a shared cache section configured to connect to the plurality of control sections via a bus, wherein the shared cache section includes a tag storage section, a tag control section, and a data storage section, and wherein the tag storage section includes a plurality of entries each including a tag address; a main memory section configured to connect to the shared cache section, wherein the main memory section includes a first-in first-out (FIFO) storage region and a reference number storage region; circuitry configured to: find, based on a comparison of a first address segment of an access address with the tag address included in at least one entry of the plurality of entries, an entry of the plurality of entries having the tag address that matches the first address segment; and invalidate the found entry in a read access, wherein the found entry is invalidated after the read access based on a determination that a remaining number of times for reference included in the found entry is equal to one; and a region designation register configured to designate a specific region in the cache memory system, wherein, upon an execution of a write access, the tag control section is configured to store data to be written in the write access into an external memory based on a determination that the access address belongs to the specific region and the remaining number of times for reference is greater than zero.