1. A method performed by an asynchronous processor, the method comprising: issuing a plurality of instruction bundles from a feedback engine to a plurality of corresponding bundle registers (BRs) associated with a plurality of sets of arithmetic and logic units (ALUs) in the asynchronous processor; processing, in the ALUs in each set of the sets of ALUs, a plurality of instructions in an instruction bundle received, from the feedback engine, in a corresponding BR associated with the each set; and accessing, by the ALUs in the each set, resources for processing the instructions using gating and passing of a plurality of tokens.