1. A processor comprising: a first register; a decoder to decode an instruction; a functional unit coupled with the decoder and the first register to convert, responsive to the instruction being decoded, a first packed first format value in a first format selected from a first plurality of packed first format values in the first format to a first plurality of second format values, said first packed first format value having a plurality of sub elements each having a first number of bits, each of the first plurality of second format values being a number represented in a second format and having a second number of bits which is greater than the first number of bits, said functional unit to store all of said first plurality of second format values into said first register.