1. A method of testing a module of a circuit design, comprising: simulating the module a first time using a testbench on a programmed processor; capturing event data to a first file during the simulating, for each event the event data describing a signal identifier, an associated signal value, and an associated timestamp; and transforming the event data of the first file into a hardware description language (HDL) replay module that drives input signals to the module of the circuit design, wherein the transforming includes the programmed processor: selecting data from the first file for translation into the replay module; writing HDL statements that recreate port transition events of the first file in the replay module; and inserting delay statements into the replay module for retaining timing of events of the first file.