1. In a pipelined computer architecture, a method for detecting instruction queue status at a cycle K, wherein instructions may be removed from the queue out of sequence, the method comprising: determining a number of invalid instructions in the queue during cycle K−2; determining a number of instructions issued for cycle K−1; determining a number of instructions enqueued for cycle K−1; and responsive to the number of invalid instructions, the number of instructions issued, and the number of enqueued instructions, determining a value indicative of a number of free rows in the queue cycle K.