1. A memory array comprising: a resistive-switching memory element including: a first electrode and a second electrode; a resistive-switching layer between the first electrode and the second electrode; a diode having an anode connected to the first electrode of the resistive-switching memory element; a signal line connected to the second electrode of the resistive-switching memory element, the signal line is configured to provide a negative set voltage relative to a common electrical reference for the resistive-switching memory element and a positive reset voltage relative to the common electrical reference for the resistive-switching memory element, wherein a magnitude of a breakdown voltage of the diode is greater than a magnitude of the set voltage, and wherein the set voltage comprises a transient pulse voltage having a pulse length less than 10 Î¼s.