1. A processor, comprising: a predictor to issue a prediction whether a lock instruction is contended; a scheduler to issue a set of micro-operations corresponding to said lock instruction speculatively when said prediction is that said lock instruction is not contended; and monitor logic to determine if a contended indication occurs, wherein said contended indication is when a store with unlock micro-operation misses in a cache and said processor restarts processing of said lock instruction when said monitor logic determines that a contended indication occurs.