1. An apparatus comprising: at least two asymmetric processing elements of a multiple core processor having different instruction set architectures (ISAs), different maximum performance capabilities and different power consumption properties; and logic to cause a first of the at least two asymmetric processing elements to transition to a low-power state, wherein a portion of local information for one or more of the at least two asymmetric processing elements may be stored in a shared resource in case that processing element is placed into the low-power state, and to cause a second of the at least two asymmetric processing elements to transition to an operating power state in response to an interrupt signal, wherein a thread of instructions of a first ISA being executed by the first processing element, but not being executable by the second processing element, is transferred as instructions of a second ISA, different from the first ISA, to be executed by the second processing element.