1. A magnetic memory sensing circuit comprising: a sense amplifier circuit having a first and a second node through which a magnetic memory element is sensed; a first current source coupled to the first node and operative to provide current; a second current source coupled to the second node and operative to provide current; a reference magnetic memory element having a resistance associated therewith and coupled to the first node, the reference magnetic memory element operative to receive current from the first current source; at least one magnetic memory element that is to be read, having a resistance associated therewith, coupled to the second node, the at least one memory element operative to receive current from the second current source, current from the first current source and current from the second current source are substantially the same, wherein the logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.