1. A method of executing an instruction in a processor including predication logic coupled to instruction decode logic, wherein the predication logic includes a mask register, a match register and a counter register, the method comprising: executing at least one instruction to store mask data in the mask register, match data in the match register, and a counter value in the counter register; in parallel with decoding a first instruction for execution, masking the first instruction using the mask data to generate a masked portion of the first instruction, comparing the masked portion of the first instruction to the match data to determine whether the masked portion of the first instruction matches the match data, and determining whether the counter register is greater than zero; in response to determining that the counter value in the counter register is greater than zero and determining that the masked portion of the first instruction matches the match data, communicating a first predication signal indicating that the first instruction should be predicated to an execution unit of the processor and decrementing the counter value in the counter register; and in response to the execution unit receiving the first predication signal, predicating the first instruction.