1. A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand, comprising: a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand; a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand; and a result generator circuit coupled to the analysis circuits and configured to produce at least three possible result signals indicating whether the first floating point operand is greater, less than, or equal to the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand, wherein the format represents a combination of at least two of a group comprising: not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact.