1. A method for triangulating multiple failed processing elements, the method comprising: simultaneously scanning multiple processing elements of a chip circuit in a parallel scan mode and a delayed scan mode; and comparing a parity value representing a parity of all scan outputs scanned out from all processing elements against an expected value to determine whether the chip circuit includes one or more failed processing elements; wherein, in the parallel scan mode, the multiple processing elements are scanned simultaneously and in parallel; and wherein, in the delayed scan mode, at least one processing element of the multiple processing elements is scanned after one or more clock delays has elapsed.