1. An apparatus, comprising: a central processing unit (CPU), the CPU to generate a pointer that is point to a virtual memory address; at least one graphics processing unit (GPU), the at least one GPU coupled to the CPU, the at least one GPU to receive the pointer from the CPU; and control logic to translate the virtual memory address to a physical memory address based on a page table mapping, the control logic to share the page table mapping with the at least one GPU, wherein based on the page table mapping, the at least one GPU is to access the physical memory address by use of the pointer that is to point to the virtual memory address.