1. A computer-executed method for facilitating floorplanning for three-dimensional integrated circuits (3D ICs), the method comprising: receiving a number of circuit blocks; receiving a set of parameters for a 3D structure, wherein the parameters include one or more of: die area; maximum total wirelength; maximum number of through-silicon vias (TSVs) on a respective layer; and aspect ratio of a respective layer in the 3D structure; and computing a floorplan for the circuit blocks across the layers in the 3D structure by optimizing a cost function, wherein the cost function is based on the total area, wirelength, and TSVs used by the circuit blocks, the aspect ratio of the area occupied by the circuit blocks in each layer, and the highest temperature produced by the circuit blocks for a given floorplan.