1. A memory cell for an integrated circuit memory, the cell having components mounted on a semiconductor substrate and further comprising: a control gate; a floating gate, controlled by the control gate and insulated from the control gate; an insulation layer for insulating the floating gate from the substrate and including at least one tunnel window made of a tunnel oxide; a transistor having a channel region, as well as drain and source regions diffused in the substrate and located adjacent the channel region; and a conductor overlying and forming a permanent connection between the drain and source regions, the conductor extending in spaced overlying relation to the substrate and the floating gate.