1. A programmable logic device comprising: a logic block including a plurality of logic cells organized into a first stage of logic cells and a second stage of logic cells; a programmable logic device (PLD) routing architecture providing inputs to the logic block and receiving outputs from the logic block, wherein the first stage of logic cells operates as a carry-save adder, wherein each logic cell in the first stage of logic cells is operable to receive a bit associated with a bit position a plurality of bit numbers and operable to provide a sum bit and carry bit for the corresponding plurality of bit numbers at two outputs of the logic cell, wherein the logic block further includes internal routing logic that is separate from the PLD routing architecture, and wherein the internal routing logic routes the sum bit and the carry bit from the first stage of logic cells to the second stage of logic cells in response to the first stage of logic cells providing the sum bit and the carry bit.