1. A computer-implemented method of generating a representation of a logic circuit, the method comprising: (A) identifying a hazardous transition in an initial representation of the logic circuit; and (B) modifying the initial representation of the logic circuit based on transition polarity of the identified hazardous transition to generate a modified representation of the logic circuit, wherein said modification is aimed at preventing the identified hazardous transition from producing a glitch at an output terminal of a logic gate whose input terminal received said hazardous transition in the initial representation.