1. A processor, comprising: a plurality of processing cores; a cache memory subsystem, comprising: a plurality of core caches, each of the core caches corresponding to one of the processing cores; a shared cache, common to each of the processing cores; trip count (TC) logic to increment a thread-aware trip count for a block recalled from the shared cache to a first core cache; use count (UC) logic to increment a UC for a block responsive to each access of the block in the first core cache; shared block logic to set a shared block bit for a block accessed by multiple core caches; bin logic to maintain live block counts and dead block counts for each bin, wherein: a bin corresponds to a (UC, TC) pair; a live block count indicates a number of valid, unshared blocks associated with a bin; and a dead block count indicates a number of blocks evicted from a corresponding bin; and eviction logic to select a shared cache block to evict, from a plurality of eviction candidates, based on at least one of: trip count values, UC values, live bin counts, and dead bin counts.