1. A vector processing engine (VPE) configured to in-flight merge a resultant output vector data sample set generated by at least one execution unit executing a vector processing operation, comprising: at least one vector data file configured to: provide an input vector data sample set in at least one input data flow path for a vector processing operation; and receive at least one merged resultant output vector data sample set from at least one output data flow path to be stored; the at least one execution unit provided in the at least one input data flow path, the at least one execution unit configured to: receive the input vector data sample set on the at least one input data flow path; and execute the vector processing operation on the input vector data sample set to provide the resultant output vector data sample set on the at least one output data flow path; and at least one merging circuitry configured to: receive the resultant output vector data sample set; merge resultant output vector data samples in the received resultant output vector data sample set to provide the at least one merged resultant output vector data sample set without the resultant output vector data sample set being stored in the at least one vector data file, wherein the at least one merging circuitry is configured to merge the resultant output vector data samples by adding the resultant output vector data samples, determining a maximum vector data sample among the resultant output vector data samples, or determining a minimum vector data sample among the resultant output vector data samples; store the at least one merged resultant output vector data sample set in selected one or more latches among a plurality of latches; and provide the at least one merged resultant output vector data sample set stored in the selected one or more latches on the at least one output data flow path; and wherein the at least one merging circuitry further comprises a plurality of parallel selectors corresponding to the plurality of latches, wherein the at least one merging circuitry is configured to control the plurality of selectors to store the at least one merged resultant output vector data sample set in the selected one or more latches among the plurality of latches.