1. A computer system comprising: A. a pipelined processor with a program counter, coupled with a main memory, and a static memory via a bus; B. an encoder module coupled with the processor, the encoder module having an event coding module with input leads receiving trace-worthy event data and sync register data, the event coding module including: i. a start/end detector module coupled to the input leads to determine a beginning and/or an end of a program counter event associated with each trace-worthy event data and each sync event data; ii. a speculative store module coupled to the start/end detector module to capture and store individual program counter events in anticipation of them being trace-worthy events and sync events; and iii. a simultaneous module coupled to the start/end detector module to encode sync events and trace-worthy events that occur simultaneously and concurrently in the processor.