1. A master bus-master for use in a bus-based computer system having a system memory, the master bus-master being configured for caching data and for operation alone or in association with at least one other bus-master capable of caching data, said master bus-master comprising: a processing unit; a local cache arrangement coupled to said system memory by a bus and coupled to said processing unit, said local cache arrangement including a cache memory for caching data between said processing unit and said system memory; a control line being set to a first initial state, said control line being capable of being set to a second state; input means coupled to the control line for detecting whether the control line is in the first state or the second state, the control line being set to the second state by said at least one other bus-master when said at least one other bus-master capable of caching data is present in said computer system and is presently caching data, said local cache arrangement including control means for controlling transmission of data between said bus and said cache memory in response to whether said control line is in said first state or said second state, wherein said at least one other bus-master sets the control line to the first state when said at least one other bus-master is not presently caching data.