1. An apparatus for sampling instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages, comprising: means for fetching instructions into a first stage of the pipeline; means for identifying any subset of the fetched instructions as selected instructions by augmenting the selected instructions with one or more indicator fields; means for providing state information of the system while any of the selected instructions are in any stage of the pipeline; and means for informing a software application that all of the selected instructions have left the pipeline so that the software application can read any of the state information.