1. A pipelined microprocessor comprising circuitry adapted for store forwarding, the microprocessor comprising circuits for performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load or store request, where the load request may require at least one updated completed block of data and the store request may require the most recent value for at least one complete block of data for merging with store data and forming a new most recent value and an updated complete block of data: determining if store forwarding is appropriate for the load or store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load or store request.