1. A signal output adjustment circuit that adjusts output of control data corresponding to command data, the signal output adjustment circuit comprising: a decoder that decodes the command data read from a memory; a control register in which control data corresponding to first command data is set when the decoder determines that the command data is the first command data for setting control data; a buffer in which control data corresponding to second command data is stored when the decoder determines that the command data is the second command data for outputting control data; and an output adjustment circuit that reads the control data stored in the buffer and outputs the read control data in synchronization with a data fetch signal, based on a value set in the control register, the output adjustment circuit setting at least one of permission/rejection of inversion output of the data fetch signal and output timing of the data fetch signal, based on the value set in the control register, and the output adjustment circuit including a data phase selection circuit that selects one of a plurality of phase clock signals of different phases based on the value set in the control register, a data-signal-output-logic-level conversion circuit that outputs the one of the plurality of the phase clock signals selected by the data phase selection circuit or an inverted signal of the selected phase clock signal, based on the value set in the control register, and a data output control circuit that generates the data fetch signal by delaying output from the data-signal-output-logic-level conversion circuit for a period corresponding to the value set in the control register.