1. In a multi-bit adder wherein digital numbers, each having N bits, where N is an even number greater than four, may be added in connected stages so that appropriate carry signals may be propagated from stage to stage, the improvement comprising: (a) first control circuitry, responsive to a first signal having either a logic one or a logic zero level, for electrically separating selected ones of the connected stages to allow digital numbers, each having less than N bits, to be processed simultaneously; and (b) second control circuitry, responsive to a second signal having either a logic one or logic zero level, for converting one of the numbers applied to each one of the connected stages to its "two's complement" so that the result of addition in each one of the connected stages is the subtraction of one of the applied numbers from the other numbers.