1. A receiver circuit for receiving a data signal, comprising: a first comparator receiving the data signal and a first reference voltage to provide a first output signal representing a first detected logic state of the data signal; a second comparator receiving the data signal and a second reference voltage to provide a second output signal representing a second detected logic state of the data signal; and a detector circuit receiving the first and second output signals and providing a third output signal, the third output signal changes state when the first and the second detected logic states agree, wherein the first comparator provides the first output signal sooner than the second comparator provides the second output signal when the data signal transitions to a first logic state, and the second comparator provides the second output signal sooner than the first comparator provides the first output signal when the data signal transitions to a second logic state opposite the first logic state.