1. A glitch block circuit for reducing information leakage due to combinatorial logic glitches, the glitch blocker circuit comprising: a multiplexer, wherein the multiplexer is configured to receive: a first input signal having one or more combinatorial logic glitches, wherein combinatorial logic glitches of the one or more combinatorial logic glitches are correlated to cryptographic data being processed; a second input signal, wherein the second input signal is uncorrelated to the cryptographic data being processed; and a glitch block enable signal, wherein the multiplexer is configured to output an output signal, such that the output signal is either: the first input signal; or the second input signal, depending on a value of the glitch block enable signal, wherein the glitch block circuit further comprises: (i) steady to unpredictable logic, wherein the glitch block enable signal is generated via the steady to unpredictable logic; (ii) a glitch block enable signal generator, wherein the glitch block enable signal generator generates the glitch block enable signal, and wherein the glitch block enable signal generator comprises one or more delay buffers; (iii) a glitch block enable signal generator, wherein the glitch block enable signal generator generates the glitch block enable signal, and wherein the glitch block enable signal generator comprises: a first toggle register having a main clock signal with respect to which the cryptographic data being processed is processed as a first toggle register input; and one or more additional toggle registers having a corresponding one or more additional clock signals as a corresponding one or more additional toggle register inputs, wherein the one or more additional clock signals have a corresponding one or more phase delays with respect to the main clock signal; or (iv) a glitch block enable signal generator, wherein the glitch block enable signal generator generates the glitch block enable signal, and wherein the glitch block enable signal generator comprises one or more high speed clock shift registers.