1. In a data processing system wherein a processor executes a series of addressable microinstructions to control the functions performed by the system and wherein the execution of a microinstruction by the processor generates the address of the next microinstruction to be executed and a next address selection signal having either a first value or a second value, a microinstruction storage and transfer apparatus comprising: a microinstruction output register; a control store comprising: a first memory for storing microinstructions in a first plurality of storage locations, said first memory being addressed by said microinstruction addresses generated by said processor, said first memory for selectively outputting from a first output terminal microinstructions stored in said first plurality of storage locations responsive to said addresses generated by said processor and having a first output enable terminal for controlling the outputting of a said addressed microinstruction from said first output terminal; a second memory for storing microinstructions in a second plurality of storage locations, said second memory normally being addressed by said microinstruction addresses generated by said processor concurrently with said addressing of said first memory, said second memory for selectively outputting from a second output terminal microinstructions stored in said second plurality of storage locations responsive to said addresses generated by said processor and said second memory having a second output enable terminal for controlling the outputting of said addressed microinstructions from said second output terminal; means for coupling said outputs of said first memory and said second memory to said microinstruction output register; and means for concurrently supplying said next address selection signal to said first output enable terminal and said second enable terminal to enable said first memory to output said addressed microinstructions when said next address selection signal has said first value and to enable said second memory to output said addressed microinstructions when said next address selection signal has said second value.