1. A microprocessor, comprising: hardware registers that instantiate the IA-32 Architecture EDX and EAX general purpose registers (GPRs); and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs; wherein the microprocessor associates with each of the R8-R15 GPRs a respective unique Model Specific Register (MSR) address; wherein in response to an IA-32 Architecture Read from Model Specific Register (RDMSR) instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers.