1. A memory device comprising: a plurality of bit lines; a plurality of word lines overlying the plurality of bit lines; a plurality of field effect transistors, field effect transistors in the plurality of field effect transistors comprising: a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines; a second terminal overlying the first terminal; a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines, the corresponding word line acting as a gate of the field effect transistor; and a dielectric separating the corresponding word line from the channel region; and a memory plane comprising programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.