1. A memory controller, comprising: a bank decoder for determining a destination bank of a memory for each memory request of a plurality of memory requests in a received order responsive to a memory address for each of the memory requests; a plurality of bank queues, each bank queue for storing pending memory requests for one or more memory banks associated with that bank queue; an ordering unit for tracking the received order and determining a memory cycle order different from the received order responsive to a presence of at least two memory requests in a same bank queue; a memory interface for executing each memory request in the memory cycle order; and a read-modify-write (RMW) unit for: detecting an RMW request to a portion of a requested memory word; reading the requested memory word from the memory and storing it in a data buffer if it is not present in the data buffer; and retaining the requested memory word in the data buffer for future RMW requests.