1. A system for computing narrow bounds on a modal interval polynomial function parameterized by a modal interval function variable U and a control polygon comprising a set of modal interval coefficients B 0 , B 1 ,. . ., B n , the modal interval function variable U and the modal interval coefficients B 0 , B 1 ,. . ., B n being modal intervals, each modal interval delimited by first and second marks of a digital scale representing two set theoretical numbers and an implicitly specified quantifier value, the system comprising: a. a memory addressing unit allowing access to said modal interval function variable U and modal interval coefficients of said set of modal interval coefficients B 1 , B 1 ,. .. B n ; b. a hardware circuit wherein modal interval coefficients of said set of modal interval coefficients are encoded in an input signal comprising i =0.. .n−1 pairs of said modal interval coefficients; c. a modal interval processor characterized by a plurality of arithmetic functional units, arithmetic functional units of said plurality of arithmetic functional units comprising hardware circuits for addition, subtraction and multiplication of modal interval operands and for establishing a dual of a modal interval operand; and, d. a modal interval linear interpolation hardware circuit comprised of a select operative union of said hardware circuits of said arithmetic functional units, said modal interval linear interpolation hardware circuit performing a modal interval linear interpolation operation upon said modal interval function variable U and select pairs of modal interval coefficients of said set of modal interval coefficients B 0 , B 1 ,. .. B n , said i=0. .. n−1 pairs of said modal interval coefficients of said input signal connected to said modal interval linear interpolation hardware circuit so as to produce a modal interval result encoded in a result signal Li, each Li connected to an output signal r=1 comprising result signals L 0 , L 1 ,. .. , L n-1 corresponding to each Li of said i =0. .. n−1 pairs of said modal interval coefficients of said input signal, said memory addressing unit operatively linking said hardware circuit and said modal interval processor.