1. A method for presenting synchronous cell connectivity in a semiconductor chip design, the method comprising: receiving, at a microprocessor, a semiconductor chip design that comprises a plurality of objects therein, the objects including at least one of blocks, modules, macros, and cells; bypassing, with the microprocessor, combinational logic of the objects in the semiconductor chip design to obtain a representation of the semiconductor chip design that includes connectivity of synchronous cells and ports thereof; and providing, with the microprocessor, a presentation of the semiconductor chip design based on the representation of the semiconductor chip design with the bypassed combinational logic of the objects.