1. An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a computer program residing in the memory, the computer program including a plurality of instructions; and an optimizing compiler residing in the memory and executed by the at least one processor, the optimizing compiler including a strength reduction mechanism that performs the steps of: (A) generating a control flow graph of the computer program, the control flow graph comprising a plurality of basic blocks; (B) generating a dominator tree that represents which basic blocks in the control flow graph dominate other basic blocks in the control flow graph; (C) processing the instructions in the control flow graph in an order determined by the dominator tree to generate a candidate table of instructions with corresponding data; (D) selecting a root candidate from the candidate table; (E) processing the candidate table of instructions to generate an increment table for the selected root candidate and related candidates in the candidate table; (F) computing cost of each increment in the increment table; and (G) for each selected increment in the increment table, when the cost for the selected increment indicates the selected increment is profitable, performing the steps of: inserting an initializer instruction for a temporary variable; substituting at least one alternative instruction that references the temporary variable for at least one of the plurality of instructions in the computer program; and removing at least one unneeded instruction from the computer program, wherein an instruction is unneeded due to the insertion of the initializer instruction for the temporary variable and the replacement of the at least one of the plurality of instructions with the at least one alternative instruction.