1. An aggregate symmetric multiprocessor (SMP) data processing system, comprising: a first SMP computer including at least first and second processing units and a first system memory pool; a second SMP computer including at least third and fourth processing units and second and third system memory pools, wherein the second system memory pool is a restricted access memory pool inaccessible to the fourth processing unit and accessible to at least the second and third processing units and the third system memory pool is accessible to both the third and fourth processing units; an interconnect coupling the second processing unit in the first SMP computer for load-store coherent, ordered access to the second system memory pool in the second SMP computer, wherein the second processing unit in the first SMP computer and the second system memory pool in the second SMP computer form a synthetic third SMP computer, and wherein the first SMP computer system and the second SMP computer system employ hardware transaction tag aliasing such that a first component in the first SMP computer system and a second component in the second SMP computer system that are not within the third SMP computer system append a shared hardware transaction tag to memory access transactions.