1. A memory collar comprising: a first circuit comprising a command decoder and configured to generate one or more data sequences in response to one or more test commands, wherein said one or more data sequences are presented to a memory during a test mode; and a second circuit configured to pre-process one or more outputs generated by said memory in response to said one or more data sequences, wherein said command decoder is configured to (i) receive the one or more test commands, (ii) present a signal indicating a current metaphase, (iii) present an address generation control signal configured to control generation of one or more addresses, (iv) present a signal indicating a data encoding scheme in use, (v) present a signal configured to control which bits received from the memory are processed by said second circuit, and (vi) present a signal comprising data-related parts of said one or more test commands.