1. A programmable integrated circuit comprising: configurable circuitry in a first region of the programmable integrated circuit; an array of signal processing accelerators (SPAs) in a second region of the programmable integrated circuit that is separate from the first region, wherein the array of SPAs is configured to receive input data from the configurable circuitry and is programmable to perform at least a filtering function on the input data to obtain output data; and a configurable interconnect network that configures connections between pairs of SPAs in the array of SPAs.