1. A method for generating a circuit description for a multi-die field-programmable gate array (FPGA) comprising a first FPGA die and at least one further FPGA die, the method being performed in an FPGA design tool and comprising: evaluating, automatically, a first partition and a second partition of a partitioned circuit description, the first partition being associated with the first FPGA die and the second partition being associated with the at least one further FPGA die; and inserting at least one multiplexing element into the first partition and a corresponding de-multiplexing element into the second partition based on the automated evaluation.