1. A data processor including a central processing unit (CPU) and memory for executing instructions including a conditional branch instruction, said data processor having a branch predicting function, comprising: fetching and decoding means for fetching and decoding said conditional branch instruction stored at a predetermined address in said memory and supplying an instruction length of said conditional branch instruction and a branch displacement specified by a branch displacement portion of said conditional branch instruction, instruction executing means for executing said conditional branch instruction decoded by said fetching and decoding means, branch predicting means for supplying a prediction signal indicating if said conditional branch instruction is predicted to result in taking a branch or not taking a branch, first replacing means responsive to said prediction signal for replacing said instruction length with said branch displacement, and second replacing means responsive to said prediction signal for replacing said branch displacement with said instruction length, a branch operation being executed by said instruction executing means to a destination specified by the predetermined address of said conditional branch instruction incremented by said instruction length in response to (i) a prediction by said predicting means of taking a branch and (ii) said prediction being found to be incorrect when said conditional branch instruction has been executed by said instruction executing means, said second radiating means including a first register for storing the instruction length decoded by said fetching and decoding means, a second register for storing the displacement decoded said fetching and decoding means, and first selecting means, responsive to said prediction signal for supplying the instruction length stored in said first register to said instruction executing means.