1. A microprocessor having a memory coupled thereto, the microprocessor comprising: a storage element, configured to accumulate a variable number of bytes of random data; a counter, coupled to said storage element, for maintaining a count of said variable number of bytes accumulated in said storage element; an instruction translator, coupled to said storage element, for translating an instruction specifying an address in the memory; and a store unit, coupled to said storage element, configured to store to the memory at said address said variable number of bytes of random data from said storage element, in response to said instruction translator translating said instruction.