1. A method for a hierarchical barrier synchronization of cores and nodes on a multiprocessor system, comprising: providing a mask bit register and a status bit register for each of a plurality of threads on a chip; receiving from a thread on the chip, an input bit signal to the status bit register associated with the thread, in response to reaching a barrier; for each of the plurality of threads, “AND”ing at least the input bit signal with a mask signal stored in the mask bit register associated with the thread to produce a first output, and “OR”ing at least an inverted mask signal associated with the thread with the first output to produce a second output; determining whether all participants in synchronization process reached the barrier by “AND”ing the second outputs associated with the plurality of threads; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the participants on the chip reached the barrier, notifying the participants on the chip if it is determined that only on-chip synchronization is needed; and after all of the participants on the chip reached the barrier, communicating the synchronization signal to outside of the chip if it is determined that inter-node synchronization is needed.