1. A microprocessor, comprising: a scheduler configured to issue operations; and a load store unit coupled to receive memory operations issued by the scheduler and configured to execute the memory operations; wherein the load store unit is configured to store information identifying a plurality of memory operations issued to the load store unit, wherein in response to detection of incorrect data speculation for one of the plurality of memory operations, the load store unit is configured to provide a replay indication to the scheduler indicating that at least one of the plurality of memory operations within the load store unit should be reissued; wherein the scheduler is configured to reissue the at least one of the plurality of memory operations in response to the indication from the load store unit.