1. A hardware three-tiered translation lookaside buffer (TLB) apparatus in a multithreading microprocessor that concurrently fetches and executes instructions of a plurality of threads, for providing virtual-to-physical address translation information for a memory page in response to an instruction cache virtual fetch address for a selected one of the plurality of threads, the apparatus comprising: a third-level TLB, for caching virtual-to-physical address translation information for a plurality of memory pages for the plurality of threads; a second-level TLB, coupled to said third-level TLB, having a plurality of entries for caching said virtual-to-physical address translation information for a subset of said plurality of memory pages cached in said third-level TLB; and a first-level TLB for each of a respective one of the plurality of threads, each said first-level TLB having at least one entry for caching virtual-to-physical address translation information only for said respective one of the plurality of threads.