1. A computer-implemented method for dynamic configuration of hardware computing resources comprising: generating a flow graph, wherein the flow graph is generated by translating a high-level description into the flow graph; configuring a first plurality of hardware processing elements within a reconfigurable array for computational purposes, based on the flow graph; configuring a second plurality of hardware processing elements within the reconfigurable array, based on the flow graph, for communication purposes including communication between the first plurality of processing elements, and wherein communication from one processing element to a second processing element is accomplished via an accumulator input on the second processing element; and configuring a third plurality of processing elements within the reconfigurable array for storage purposes, wherein elements from the first plurality of processing elements, elements from the second plurality of processing elements, and elements from the third plurality of processing elements are interchangeable on subsequent time steps, wherein the configuring of the first plurality of processing elements, the second plurality of processing elements, and the third plurality of processing elements is accomplished by static scheduling, and further comprising identifying conflicts based on the flow graph and performing time slicing to handle identified conflicts.