1. A cache memory apparatus comprising; a cache memory that caches an instruction code corresponding to a fetch address; and a cache control circuit that controls the instruction code to be cached in the cache memory, wherein the cache control circuit: caches the instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine, and disables the instruction code to be cached when a number of instruction codes to be cached exceeds a previously set maximum number; and wherein the previously set maximum number of the instruction codes is obtained by dividing a number of clocks since a CPU outputs the fetch address to a memory until the memory outputs the instruction code by a number of clocks necessary for the CPU to execute one instruction code.