1. An emulator comprising: a plurality of design field-programmable gate arrays (FPGAs) configured to collectively emulate a design under test (DUT) and produce a first signal of the DUT, wherein a first design FPGA of the plurality of design FPGAs is configured to emulate a section of the DUT; and a system FPGA in communication with the plurality of design FPGAs and configured to receive the first signal from the first design FPGA, the system FPGA comprising: a plurality of virtual FPGAs, at least one of the plurality of virtual FPGAs configured to receive the first signal, emulate substantially the same section of the DUT that the first design FPGA is configured to emulate, and produce a second signal of the DUT based on the first signal, and a logic analyzer configured to perform logic analysis based on the second signal.