1. A bus system produced by bundling several individual lines or buses or subbuses (see FIGS. 4, 5 ) within a unit of the DFP, FPGA or DPGA type as well as all units having a two- or multi-dimensional programmable cell architecture (see FIGS. 1, 2, 3 ) by means of which multiple units can be combined and/or memories and/or peripherals can be connected (see FIG. 10 ).