1. A programmable logic device comprising: a plurality of input/output blocks having boundary scan cells, wherein the boundary scan cells are adapted to precondition registers within a logic area of the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration; a plurality of logic blocks; configuration memory cells adapted to store first configuration data for configuration of the logic blocks and the input/output blocks of the programmable logic device; non-volatile memory adapted to store second configuration data and transfer the second configuration data to the configuration memory cells for the reconfiguration of the programmable logic device; and at least a first data port adapted to receive commands for controlling the reconfiguration of the programmable logic device.