1. A computer system for performing permutations comprising: a source register; a configuration register; a destination register; in response to a GRP instruction dividing n bits in said source register into a first group and a second group, wherein each of said n bits is selected into said first group if a corresponding bit in the configuration register is “0” and each of said n bits is selected into said second group if a corresponding bit in the configuration register is “1”, concatenating the bits of said first group and the bits of said second group and placing the concatenated bits in said destination register.