1. A method of coherency management in a multiprocessor data processing system having a multi-level cache hierarchy including at least upper and lower levels, said method comprising: holding a cache line in an upper level cache memory in an exclusive ownership coherency state; thereafter, removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory, said castout request including an indication of a shared ownership coherency state; and in response to the castout request, placing the cache line in the lower level cache memory in a coherency state determined in accordance with the castout request.