1. A multi-planar memory system consisting of a plurality of memory circuit planes in a three dimensional (3D) stem on a chip (SoC) with through silicon vias (TSVs) comprised of: a multi-circuit set of memory circuit layers arranged in a 3D configuration; a plurality of memory circuit layers, each layer of which includes memory circuit component types; at least one logic circuit layer connected to the memory circuit layers by TSVs; wherein the types of memory on memory circuit layers are used by at least one logic circuit layer, which are configured to access at least one memory type on each memory circuit layer using the TSVs; wherein when at least one memory type on a memory circuit layer is sandwiched between at least two logic circuit layers, the memory types on the memory circuit layers are connected with TSVs; and wherein the memory circuit layers store data and instructions.