1. A memory device, comprising: a memory core block; a data patch unit configured to patch parallel data read from the memory core block in response to a first read pulse; a Cyclic Redundancy Check (CRC) generating unit configured to generate a CRC code based on the parallel data in response to a second read pulse, the second read pulse delayed by a period of time from if the first read pulse is generated; and a serializer configured to convert the parallel data to serial data in response to the first read pulse, and arrange the CRC code in a order for a number of bits of the serial data to generate a systematic code.