1. A system comprising: a plurality of programmable logic devices, including at least a first and a second programmable logic device, the first and second programmable logic devices coupled to receive programmable logic device configuration code from a first and a second EEPROM associated therewith; a first serial bus coupling the first EEPROM with a common configuration logic, and a second serial bus coupling the second EEPROM with the common configuration logic; a processor coupled to the common configuration logic, wherein the processor is also coupled to a memory subsystem; wherein the processor is capable of transferring programmable logic configuration code from its memory subsystem into the first EEPROM.