1. A processor comprising: an instruction cache configured to fetch a first instruction from a program stored in a memory; a decoding section, connected to the instruction cache, configured to decode the first instruction fetched in the cache; an executing section, connected to the decoding section, configured to execute the decoded first instruction; and an address computing section, connected between the instruction cache and the execute section, configured to compute an address of a second instruction to be fetched into the instruction cache when the decoded first instruction is a branch instruction, the address computing section including: a section configured to detect a result of a former branch prediction of the first instruction; a section configured to compute the address according to the result of the former branch prediction unless the result represents an impossibility of prediction; a section configured to confirm a successful prediction by comparing the result of the former branch prediction with a branch condition result ascertained from an execution of the first instruction; and a register in which the computed address is set when the successful prediction is confirmed.