1. A monolithic, autonomous processor chip for selected data processing, said chip including: an array of at least 16 bit-serial multipliers; a plurality of input/output ports for supplying selected complex data and complex coefficients to said multipliers for multiplication; means for receiving and latching complex data and coefficients supplied to said multipliers and for parity checking of the data and coefficients; a bit-serial adder/substractor matrix connected to said multiplier array for combining the multiplier output data results; shift register means receiving and temporarily storing signals from said adder/subtractor matrix and for serial to parallel conversion of stored signals for delivery of said stored signals to input/output ports; scaling control means for scaling said signals from said adder/subtractor matrix before storage in said shift register means; sequencer control means having control outputs connected to said multiplier array, to said adder/subtractor matrix, to said shift register means, and to said scaling control means for controlling internal step-by-step operations of said chip; mode controller means connected to said sequencer control means for controlling and selecting the operational modes of said chip and for activating said sequencer control means to provide repetitive sequencing of selected operations, said mode controller being connectable for communication with a host processor; and address generator means on said chip and connected to said sequencer control means and to said mode control means for selecting complex data and complex coefficients for multiplication in said multipliers.