1. A processing apparatus comprising a plurality of processors, each arranged to perform an instruction and to output data and control tokens, and a bus arranged to carry the data and the control tokens between the processors, wherein each processor is arranged, if it receives a one of the control tokens via the bus, to carry out the instruction, and on carrying out the instruction, to perform an operation on the data to produce a result, to identify any of the processors which are to be data target processors, and to transmit output data to any identified data target processors, to identify any of the processors which are to be control target processors, and to transmit a control token to any identified control target processors, wherein each processor is arranged to select at least one of the target processors on the basis of the result.