1. Integrated circuit storing clock configuration logic for a memory block, the logic comprising: a first set of clock configuration logic configurable to provide a first port input clock signal operable to control input registers of a first port of the memory block; and a second set of clock configuration logic configurable to provide a second port input clock signal operable to control input registers of a second port of the memory block, wherein the second set of clock configuration logic is configurable to provide a second port core clock signal for controlling the core of the memory block.