1. An apparatus comprising: memory cells in a package; volatile memory configured to store defective address data responsive to entering a soft post-package repair mode; a match logic circuit configured to generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory; and a decoder configured to select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory, wherein the second group of the memory cells corresponds to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.