1. An integrated circuit (IC) design, comprising: a plurality of embedded memories each having a plurality of memory instances, wherein each memory instance is associated with a reconfiguration register and a repair register; a shared nonvolatile storage (NVS) container disposed outside said embedded memories, said shared NVS container for storing compressed repair data associated with said plurality of embedded memories; and a shared NVS processor for executing a compression engine operable to compress repair data scanned out from each of said repair registers.