1. A multithreaded processor comprising: means for permitting a thread to issue one or more instructions on a processor clock cycle; means for varying the thread permitted to issue instructions over a plurality of clock cycles in accordance with an instruction issuance sequence; and means for pipelining the instructions to permit the threads to support multiple concurrent instruction pipelines, wherein the pipelined instructions comprise at least a vector multiplication and reduction instruction that includes an instruction decode stage, a vector register file read stage, at least two multiply stages, at least two add stages, an accumulator read stage, a plurality of reduction stages, and an accumulator writeback stage; wherein the vector multiplication and reduction instruction is pipelined using a number of stages which is greater than a total number of threads of the processor; and wherein vector multiplication and reduction instruction pipelines are shifted relative to one another to permit computation cycles which are longer than issue cycles without forwarding logic to allow lengthening of execution phases without causing bubbles in the pipelines.