1. A design method for logic circuit, comprising: a first process for determining, with fuzzy reasoning, an optimization algorithm candidate of a circuit block given with a logic circuit description based on a hardware description language; a second process for grouping, with the fuzzy reasoning, a common circuit block of the optimization algorithm candidate determined in said first process; and a third process for optimizing, with hereditary algorithm, the grouping of a plurality of circuit blocks by reflecting the result of grouping by said second process on an initial condition.