1. A processor comprising: a) a control store for producing microinstructions in response to microaddresses applied to an input of the control store, the processor operating in machine cycles and the control store producing one of said microinstructions each machine cycle; each microinstruction executing during a plurality of successive machine cycles; b) a plurality of execution stages, each execution stage using each one of said microinstructions in said successive machine cycles whereby execution of each of said microinstructions overlaps execution of other of said microinstructions, with latch means in each of said execution stages receiving said microinstructions to store and shift each microinstruction for said successive machine cycles; c) means for generating condition information in response to a condition at an output of one of said execution stages in each of said successive machine cycles; d) means for generating a next microaddress using said condition information, and for applying said next microaddress to said input of the control store; e) and means for selecting said condition information generated in a selected machine cycle, for use by said means for generating a next micro-address after a designated number of said successive machine cycles, said designated number of said successive machine cycles being dependent upon a decoded field of one of said microinstructions.