1. A memory device comprising: an array of data storage cells; a control circuit connected to the array of data storage cells, wherein the data storage cells can be electrically programmed and erased by applying a first programming voltage and programming pulse sequence to achieve a first charge transfer and a first threshold voltage having a first signal-to-noise ratio, the control circuit adapted to: program the data storage cells by applying a second programming voltage and programming pulse sequence to achieve a second charge transfer that is less than the first charge transfer and a second threshold voltage that is less than the first threshold voltage, the second threshold voltage providing a second signal-to-noise ratio that is lower than the first signal-to-noise ratio.