1. An execution slice circuit for use within a processor core, the execution slice circuit comprising: a master execution slice having a first issue queue for receiving instructions of a first instruction stream; a slave execution slice having a second issue queue for receiving instructions of a second instruction stream and instructions of the first instruction stream that require a greater execution width greater than a lesser width of the master execution slice and the slave execution slice; and control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.