1. A method for formally verifying a hardware/software co-design, the method comprising: providing in a co-design, a first model, and a second model, wherein the first model is one of a hardware model, and the second model is one of a software model, or vice versa; providing a safety property expected to be satisfied by the co-design; combining an abstraction of the first model and the safety property to obtain an abstracted first model; composing the abstracted first model and the second model to obtain a composed model; checking if the composed model satisfies the safety property; and signaling that the hardware/software co-design violates the safety property if the safety property is violated in the composed model.