1. A memory device comprising; an interface circuit coupled to receive a command latch enable signal, a write enable signal, and an external data input, the external data input to receive a test command signal representing a test mode request and to receive a filter command signal representing a filter setting mode request, the interface circuit to provide a register access signal at a first interface circuit output indicating a test mode on a register access signal line and to provide a filter access signal at a second interface circuit output indicating a filter setting mode on a filter access signal line; a controller to provide one or more controller address data signals and to provide controller register data; a first switching device including a first input, a second input, a first control input, and a first switched output, the first switching device coupled to receive the controller register data at the first input, and coupled to receive an actuator signal at the second input, and coupled to receive a filter setting status signal at the first control input, the first switching device providing a filtered data output signal at the first switched output, wherein for the filtered data output signal, the first switching device couples the filtered data output signal to either the controller register data signal or to the actuator signal based on a status provided by one of the filter setting status signal; a second switching device including a third input, a fourth input, a second control input, and a second switched output, the second switching device coupled to receive the external data input at the third input, and coupled to receive the filtered data output signal at the fourth input, and coupled to receive a mode signal at the second control input, the mode signal coupled to the register access signal and coupled to the filter access signal, the second switching device providing a plurality of output data signal lines at the second switched output; a register including a register enable input coupled to a register enable input signal to receive a register enable input signal, and a register data input coupled to receive the output data signal, wherein the output data signal includes data provided by the external data input during the test mode, and wherein the output data signal includes data provided by the filtered data output signal during a time when the interface circuit is not indicating the test mode and is not indicating the filter setting mode, and a register output providing the actuator signal; and A filter register including a filter enable input coupled to receive a filter enable input signal, and a filter data input coupled to receive the output data signal, wherein the output data signal includes data provided by the external data input during the filter setting mode, the filter register including a filter output providing the filter setting status signal.