1. A computer system comprising: a central processor; a memory arrangement that further comprises a flash EEPROM memory array including a plurality of floating gate field effect transistor devices, a charge pump for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a comparator connected to receive a data word to be programmed into the flash EEPROM memory array for comparing each bit of the data word with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed, control circuitry responding to the output signals from the comparator for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump; and a system bus for transferring data and addresses between the central processor and the memory arrangement.