1. A unified microprocessor pick queue comprising: control circuitry; and an array configured to dynamically allocate any available entry of a plurality of entries for an instruction, wherein each allocated entry of said entries comprises for a given instruction a separate dependency bit for each other instruction in the array, wherein each dependency bit indicates whether the given instruction depends on a result of a corresponding other instruction; wherein during each pipe stage prior to resolving a speculative load instruction, the circuitry is configured to: determine whether each entry of the plurality of entries corresponds to an instruction with a direct dependency on the load instruction and whether each entry corresponds to an instruction with an indirect dependency on the load instruction, based at least in part on said separate dependency bits already stored in the array and a dependency vector corresponding to the load instruction, wherein the dependency vector is stored separate from the array; update and store the dependency vector with the direct and the indirect determined dependencies; and wherein responsive to the speculative load resolving to a misspeculation, the circuitry is further configured to: utilize the dependency vector to identify both picked instructions which are directly dependent and picked instructions which are indirectly dependent on the speculative load, wherein the picked instructions are picked in a same cycle or a previous cycle to a cycle during which the speculative load is resolving and reset an instruction state of the identified instructions in said same cycle; and utilize the dependency vector to selectively cancel execution of only the identified instructions.