1. A pattern recognition apparatus which includes a pattern preprocessing part having a plurality of outputs, a clock oscillator, and an information consolidator and a memory having a plurality of nonlinear oscillating circuits, respectively, characterized in that each of the oscillating circuits includes a plurality of inputs for controlling the oscillation condition and at least one output; the output of each oscillating circuit in the information consolidator being interconnected to predetermined inputs of other oscillating circuits in a predetermined relation, and the inputs of the oscillating circuits being coupled to the outputs of the pattern preprocessing part in a predetermined distribution; the clock oscillator being connected to receive as a main exciting signal, the sum of a group of signals obtained by phase-adjusting the outputs of a substantial part of oscillating circuits contained in the information consolidator; the respective oscillating circuits in the memory being connected to receive, as a main exciting signal, the output of the clockoscillator, and said oscillating circuits also being divided into a predetermined number of groups so that the sum of the outputs of the oscillating circuits in each group given an elementary signal of a pattern reference memory data; and further including waveform comparison means for comparing the elementary signal of the memory data with the direct sum of the outputs of the said substantial part of oscillating circuits in the information consolidator, so that the result of comparison is applied to inputs of the oscillating circuits of the memory.