1. A unified microprocessor pick queue comprising: control circuitry; and an array configured to dynamically allocate an entry of a plurality of entries for an instruction, wherein each entry of said entries includes a picked field and a trigger field, wherein the picked field indicates a corresponding instruction is eligible to be picked for issue, and the trigger field indicates a result of the instruction will be available in M clock cycles; wherein for a first instruction dependent upon a second instruction whose results are not yet available, the circuitry is configured to determine the first instruction is eligible to be picked for issue responsive to detecting the second instruction has associated picked and trigger fields have a designated state.