1. A system for integrated circuit design comprising: a high level design comprising a chip architecture, a floor plan, and one or more critical interconnect wire topologies; a schematic design comprising one or more circuit components and one or more critical interconnect wire models; a physical layout comprising said one or more circuit components and said one or more critical interconnect wire topologies; extracted parameters of said one or more circuit components and calculated parameters of said critical interconnect wire models; and results of a simulation of a schematic design comprising said extracted parameters and said calculated parameters.