1. A computer-implemented method for generating automated assumption for compositional verification of an electronic circuit design, comprising: using a processor for: identifying a first set and a second set of behaviors of the electronic circuit design; iteratively computing a minimal incomplete deterministic finite automaton (IDFA) based at least in part upon the first and the second sets of behaviors; determining a deterministic finite automaton (DFA) by generalizing from the minimal IDFA, wherein the DFA is determined by performing a learning process to gather information from the IDFA; and storing the DFA on a tangible computer readable medium or displaying the DFA on a display device.