1. A processor comprising: a completion mask register comprising a first plurality of data fields, wherein each of the first plurality of data fields in the completion mask register corresponds to a multiple of a stride length from a beginning address for a corresponding data element in a memory, wherein for each data field in the completion mask register, a first value indicates the corresponding element has not yet been loaded from the memory and a second value indicates that the corresponding data element does not need to be loaded, or has already been loaded from the memory; a decode stage to decode a first instruction specifying the completion mask register, the stride length and a set of load operations corresponding to one or more of the first plurality of data fields; and one or more execution units, responsive to the decoded first instruction, to: read the values of each of the data fields in the completion mask register; for each data field of the first plurality of data fields in the completion mask register having the first value, compute the corresponding multiple of said stride length according to a position of the data field in the completion mask register to load the corresponding data element from the memory and store the corresponding data element into a destination register, the destination register having a second plurality of data fields, a portion of which to store the loaded data elements, and to change the value of the corresponding data field in the completion mask register from the first value to the second value.