1. A system comprising: processor cores including heterogeneous processor cores, the heterogeneous processor cores comprising multiple central processing unit (CPU) cores and at least one graphics engine core; and a first cache connected to and shared by a first plurality of the processor cores; a second cache connected to and shared by a second plurality of the processor cores, the second cache being connected to the first cache by an interconnect that couples the first cache to the second cache and, when in operation, operates in a manner that ensures the first cache and the second cache are kept coherent; the interconnect; wherein at least the first plurality of processor cores and the first cache are integrated on a single integrated die.