1. A method of testing an electronic circuit comprising a plurality of data transfer operators operating on memory resources defining a shared memory space, comprising the steps of: initializing a phase the memory space, in which each address of the shared memory space is initialized with a data item which is unique in the memory space, defining a phase partitioning of all or some of the memory space into a plurality of disjoint memory blocks, organized into groups of blocks, at least one group, such that a block belongs to a single group; and the blocks of a group all have the same size; and one phase of executing a test scenario comprising at least one data transfer operation, each data transfer being a transfer defined on a given transfer operator and on a given group of blocks, for writing the content of a source block, to a destination block of the same group; a phase of verifying the content of the shared memory space.