1. An apparatus comprising: a processor adapted to execute a first transaction comprising a read operation referencing a memory address to be associated with a cache line in a cache memory of the processor, wherein an attribute field is adapted to be associated with the cache line, and wherein a load is to be serviced from: the cache line without checking a write-space, in response to the attribute field holding a first value to indicate a current value is held in the cache line, the write space in response to the attribute field holding a second value to indicate the current value is held in the write space, and from higher-level memory than the cache memory as a miss to the cache memory in response to the attribute field holding a third value.