1. A ferroelectric memory ( 636 ) comprising a memory cell ( 12, 202, 302, 402 ), and a circuit ( 11, 211, 311, 411 ) for reading and writing to said memory cell, wherein said circuit for reading and writing includes a drive line ( 22, 122, 322, 422 ) on which a voltage for writing information to said memory cell is placed, a bit line ( 25, 125, 325, 425 ) on which information to be read out of said memory cell is placed, a preamplifier ( 20, 42, 120, 320, 420 ) between said memory cell and said bit line, a set switch ( 14, 114, 314, 414 ) connected between said drive line and said memory cell, and a reset switch ( 16, 116, 316, 416 ) connected to said memory cell.