1. A computer-generated method, comprising: generating a model of hardware components making up an interconnect that facilitates communications between IP blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect; simulating sub-components of the model at the high level of abstraction in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction to verify the functional accuracy and cycle timing between the two models; and after simulating the sub-components, aggregating the sub-components of the model at the high level of abstraction into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction, wherein the generating, simulating and after simulating are performed by a computing device.