1. A processor, comprising: an instruction decoder to decode instructions; an execution unit coupled to the instruction decoder to execute decoded instructions, the execution unit being associated with a capture logic to periodically capture operating heuristics of the execution unit, wherein the operating heuristics comprise instructions retired, misses per instruction, and branch mispredictions; a detection logic coupled to the execution unit to evaluate the captured operating heuristics to determine whether there is a need to adjust an operating point of the execution unit, wherein the detection logic is to determine a number of instructions retired per clock cycle (IPC) based on the captured operating heuristics to determine whether there is a need to adjust the clock signal to the execution unit; and a control logic coupled to the detection logic and the execution unit to adjust the operating point of the execution unit based on the evaluation of the operating heuristics, wherein the adjusted operating point comprises an adjusted rate level and an adjusted allocation of a shared hardware resources; wherein the control logic is further to configure the execution unit to operate in different modes based on the evaluation of the operating heuristics; and wherein the different modes include at least one of a 4-wide mode, a 3-wide mode, a 2-wide mode, and a 1-wide mode.