1. A processor comprising: mask physical registers to store a vector conditions mask; vector physical registers to store: a source vector having a first plurality of n data fields having a variable partition size of m bytes, and a destination vector comprising a second plurality of data fields corresponding to the first plurality of data fields, wherein each of the second plurality of data fields in the destination vector corresponds to a mask value in said vector conditions mask; a decode stage to decode processor instructions, a first processor instruction specifying a vector expand operation and a data partition size; and one or more execution units, responsive to the decoded processor instructions, to: set elements of the source vector to n count values; obtain a decisions vector; generate said vector conditions mask according to the decisions vector; and responsive to executing the first processor instruction, copy data from consecutive vector elements in the source vector, into unmasked vector elements of the destination vector, without copying data from the source vector into masked vector elements of the destination vector.