1. A non-transitory storage medium holding computing-device readable instructions that, when executed by one or more processors, cause a target computing device having forwarding or switching capability to: receive, from a controller, by a Hardware Abstraction Layer (HAL) for the target computing device, an abstract candidate device model describing intended packet forwarding or switching behavior for the target computing device; map, by the HAL, the abstract candidate device model to an existing architecture of the target computing device, the architecture of the target computing device including at least one of an Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), Application Specific Instruction Set Processor (ASIP), Complex Programmable Logic Device (CPLD), graphics processing unit (GPU), processor or microprocessor; determine, by the HAL, which of the intended packet forwarding or switching behavior is supported by the target computing device; send a response to the controller indicating what behavior is supported by the target computing device; and implement the supported behavior from the abstract candidate device model on the target computing device.