1. A method comprising: determining, by a processor, whether a given input to a logic circuit is coupled to both an input of a cone of logic that is coupled to a data input of a clocked state element and a clock gate circuit that is coupled to disable a clock input to the clocked state element; and in response to determining that the given input is coupled to both the input of the cone of logic and the clock gate circuit: removing the given input from the cone of logic such that the given input is no longer coupled to the input of the cone of logic coupling a reference voltage to the input of the cone of logic that was previously coupled to a signal path for the given input; and preserving the given input to the clock gate circuit such that the given input continues to be coupled to the clock gate circuit after being removed from the input of the cone of logic.