1. In a superscalar processor, a method of processing successive pipelined instructions comprising: fetching an operand specified by a first instruction in a first pipestage; computing in the first pipestage an address of a source operand specified by a subsequent instruction wherein the source operand is a destination register of the first instruction; determining if the first instruction uses multiple execution stages; executing the first instruction in consecutive pipestages following the first pipestage to generate a result, and only if the first instruction uses multiple execution stages freezing the processing of subsequent instructions during the multiple execution stages; generating the result in a first phase of a last execute pipestage; providing the result as the source operand specified by the subsequent instruction through a bypass operation in a second phase of the last execute pipestage; and advancing the subsequent instruction to an execution pipestage.