1. An apparatus comprising: a memory array having a plurality of storage segments, the plurality of storage segments including: a plurality of bitcells each to store a data bit; a first local bitline coupled to a first collection of the plurality of bitcells to output read data from the first collection of the plurality of bitcells; a second local bitline coupled to a second collection of the plurality of bitcells to output read data from the second collection of the plurality of bitcells; and a latch circuit having a first input coupled to the first local bitline and a second input coupled to the second local bitline, the latch circuit to output a segment output, the segment output comprising a static signal.