1. A method for instruction fetching in a processor using a loop predictor, the method comprising: detecting a loop based on a repeated pattern of access to a data structure used for branch prediction; capturing a sequence of instruction addresses in one iteration of the detected loop in a buffer on a determination that the detected loop is locked, wherein the detected loop is determined to be locked if it is determined based on the repeated pattern of access to the data structure that instructions stay in the loop for at least a duration sufficient to disable the branch prediction; and generating a sequence of instruction addresses for instruction fetching from the buffer.