1. A driving circuit, comprising a scanning driving circuit and at least one group of combinational logic circuits, a first group of scanning signals output by an output terminal of the scanning driving circuit, an input terminal of the at least one group of combinational logic circuits connected to the output terminal of the scanning driving circuit or connected to an output terminal of a preceding group of combinational logic circuits, at least one second group of scanning signals output by the output terminal of the at least one group of combinational logic circuits for the driving circuit to output more groups of scanning signals; the at least one group of logic circuits comprising a first group of combinational logic circuits and a second group of combinational logic circuits, an input terminal of the second group of combinational logic circuits connected to an output terminal of the first group of combinational logic circuits, both of the first group of combinational logic circuits and the second group of combinational logic circuits comprising at least one logic circuit, the logic circuit comprising a first input terminal, a second input terminal, a third input terminal, a selector, an inverter, a first NAND gate, a second NAND gate, and an AND gate, the first input terminal, the second input terminal, and the third input terminal all receive three consecutive scanning signals from the first group of scanning signals output by the scanning driving circuit, a scanning signal generated by the logic circuit according to the three consecutive scanning signals, an input terminal of the selector comprising a first input terminal and a third input terminal of the logic circuit, an output terminal of the selector connected to an input terminal of the first NAND gate, another one input terminal of the first NAND gate connected to an output terminal of the inverter, an input terminal of the second NAND gate used as the second input terminal, an output terminal of the first NAND gate and an output terminal of the second NAND gate connected to an input terminal of the AND gate, and an output terminal of the AND gate outputting the scanning signal.