1. A cache memory including a plurality of addressable locations, said cache memory further comprising: an effective address cache for storing a plurality of effective addresses; a segment register array for storing a plurality of address segments; a memory array, said memory array being a physical memory for storing cached data and instructions; and means for combining a selected effective address with a selected segment to provide a physical memory address to said physical memory, wherein a program executing said data and instructions in a plurality of executions occupies the same effective address space for each of said plurality of executions thereby achieving consistent execution within a specified time period.