1. A parallel processing device, the processing device comprising: a plurality of processing elements each configured to execute instructions; a memory subsystem comprising a plurality of memory slices including a first memory slice associated with one of the plurality of processing elements, wherein the first memory slice comprises a plurality of random access memory (RAM) tiles each having individual read and write ports; and an interconnect system configured to couple the plurality of processing elements and the memory subsystem, wherein the interconnect system includes: a local interconnect configured to couple the first memory slice and the one of the plurality of processing elements, and a global interconnect configured to couple the first memory slice and the remaining of the plurality of processing elements.