1. A data processor comprising: C execution clusters, each of said C execution clusters comprising an instruction execution pipeline having N processing stages capable of executing instruction bundles comprising from one to S syllables, wherein each said instruction execution pipelines is L lanes wide, each of said L lanes capable of receiving one of said one to S syllables of said instruction bundles; an instruction cache capable of storing a plurality of cache lines, each of said cache lines comprising C*L syllables; an instruction issue unit capable of receiving fetched ones of said plurality of cache lines and issuing complete instruction bundles toward said C execution clusters; and alignment and dispersal circuitry capable of receiving said complete instruction bundles from said instruction issue unit and routing each said received complete instruction bundles to a correct one of said C execution clusters as a function of at least one address bit associated with each of said complete instruction bundles.