1. A calculation apparatus for performing algebraic and logic computations that are based upon a plurality of iterative calculations and the storage of intermediate results, comprising: A) arithmetic computation means (80) for generating at an output the algebraic manipulation results of one or more input values from a plurality of inputs, the arithmetic computation means responsive to an arithmetic logic unit control signal (90) at a control input for controlling the signed arithmetic operation of said arithmetic computation means; B) input control means comprising a plurality of gates (118, 120, 122, 124) for selecting said input values, each gate responsive to a multiplexer control encoder signal (131) at a control input so as to output a particular input value on the output of the respective gate; C) intermediate storage means comprising a plurality of registers (132) connected to the output of the arithmetic computation means for the storage of algebraic manipulation results therefrom representing said intermediate results, said storage means having outputs connected to the input control means, each register responsive to a register control signal (129) at a control input so as to output a particular intermediate result; D) result output control means (133) connected to the output of the arithmetic computation means (80) for outputting a final computational result of the calculation apparatus, the result output control means responsive to a control signal at a control input so as to output a particular output of the arithmetic computation means that is the final computational results of the calculation apparatus; E) a sequencer (92) for generating sequence signals to control the overall operation of the calculation apparatus; F) an arithmetic logic unit control encoder (126), responsive to the sequence signals, for generating said arithmetic logic unit control signal (90); G) a register control encoder (128), responsive to the sequence signals, for generating said register control signal (129); and H) a multiplexer control encoder (130), responsive to the sequence signals. for generating said multiplexer control encoder signal (131).