1. A cross-point memory cell comprising: a word line extending in a first direction; a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other; and a capacitor capable of being repeatedly programmed to at least two different capacitance states formed between the word line and the bit line where such cross, the capacitor comprising a capacitor dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.