1. A microprocessor comprising: a plurality of processing cores; and a cache coherence manager adapted to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, said cache coherence manager comprising: a request unit configured to receive a coherent request from a first one of the plurality of cores and to selectively issue a speculative request in response; an intervention unit configured to send an intervention message associated with the coherent request to the plurality of cores; a memory interface unit configured to receive the speculative request and to selectively forward the speculative request to a memory; and a response unit configured to supply data associated with the coherent request to the first one of the plurality of cores.