1. A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an control input node of one of said input/output modules.