1. A computer implemented method for managing cache line evictions during a transaction executing in a transactional memory environment, the method comprising: executing, by a processor, a non-conflict address range setting instruction, wherein: the non-conflict address range setting instruction is a read-and-do-not-track instruction; wherein data fetched into a cache line that contains data from the non-conflict address range is not marked as a read-set cache line of the transaction; wherein the cache line that contains data from the non-conflict address range is protected by protection facilities, the protection facilities including Dynamic Address Translation, access list control, and hardware key; and wherein storing, by another processor, into a cache line containing at least a portion of the non-conflict address range, is not permitted; in response to the processor executing a memory data accessing instruction during the transaction, determining, by a cache manager, whether a pre-defined maximum number of read-set cache lines is reached; based on the pre-defined maximum number of read-set cache lines being reached, determining, by the cache manager, whether a memory address operand of the memory data accessing instruction is within the non-conflict address range; based on the pre-defined maximum number of read-set cache lines being reached, and based on the memory address operand of the memory data accessing instruction being within the non-conflict address range, evicting a read-set cache line having data from a memory address in the non-conflict address range; and completing, by the processor, the memory data accessing instruction.