1. A system comprising: a first processor; a second processor; a dataport, said processors coupled in parallel to the dataport; and a shared memory shared by said processors, said dataport coupled to said shared memory, said dataport to perform memory access operations on said shared memory for each of said processors, each processor to send a message to the dataport and to specify a location where a response from said dataport is to be stored and to enable the thread to lock said location when the thread sends the message to the dataport, wherein said dataport further comprises: an input bus to receive a message from at least one of said processors for executing one or more threads requesting an operation on said shared memory; a message decoder to determine solely from said message which steps are to be performed in order to execute said operation and to identify requester of said operation; and a data processor to perform said steps.