1. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; a second metallization structure over said passivation layer and over said first and second pads, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, and wherein said first pad is connected to said second pad through said second metallization structure; and a first polymer layer between said third and fourth metal layers.