1. A pipeline processor comprising: a pipeline processing unit to process an instruction according to a plurality of stages; and an equal model compensator to directly store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the processing results in a register file based on the latency of each instruction, wherein the equal model compensator comprises a FIFO unit, wherein the equal model compensator stores the processing results in the FIFO unit, in response to a backup signal for flushing the pipeline processing unit, and wherein the equal model compensator stores the processing results in the register file, in response to the backup signal for flushing the pipeline processing unit and a restore signal for restarting the pipeline processing unit being set to null.