1. A modular arithmetic coprocessor designed to perform computations according to the Montgomery method comprising a division circuit, the division circuit comprising a test circuit having one input and one output to perform integer divisions by numbers that are different from a power of two, wherein the integer division circuit computes the division of a binary code A encoded on n'+n" bits by a binary data element B encoded on n bits, A, B, n, n' and n" being non-zero integers, and wherein the integer division circuit comprises: a first n'-bit register and a second n"-bit register to contain the binary data element A and the result of the division, an output of the first register being connected to an input of the second register, the output of the test circuit being connected to the input of the first register; a third n-bit register to contain an intermediate result, an output of the second register being connected to an input of the third register; a fourth n-bit register to contain the binary data element B, the output of the fourth register is connected to its input; and two cascade-connected subtraction circuits each having a first series input and a second series input and a series output, the output of the third register is connected to the first input of the first subtraction circuit; the output of the fourth register is connected to the second input of the second subtraction circuit; the output of the second subtraction circuit is connected to the input of the test circuit; the output of the second register is connected to the first input of the second subtraction circuit; the output of the first subtraction circuit is connected to the input of the third register; the output of the fourth register is connected to the second input of the first subtraction circuit; the output of the first subtraction circuit is connected to the first input of the second subtraction circuit.