1. A computer implemented method, comprising: testing to failure a plurality of semiconductor test structures; measuring parameters of each of the plurality of semiconductor test structures before and after experiencing a failure; generating a cumulative probability distribution function (CPDF) of cumulative probability versus the measured parameter after failure for the plurality of semiconductor test structures tested; performing simulations using a computer system for a circuit, injecting at a single transistor location, a model of a transistor that mimics the failure to determine a parameter threshold value that defines a minimum acceptable performance level of the circuit; determining a cumulative probability value from the CPDF that a transistor will not have the parameter at a level below the parameter threshold value; adjusting a value of the area of the circuit based on the cumulative probability value; and computing a first reliability value based on the adjusted area value.