1. An integrated circuit, comprising: processing logic operable to perform data processing operations on data; a number of memory units operable to store data for access by the processing logic; and a memory test controller operable to execute test events in order to seek to detect any memory defects in the number of memory units; the memory test controller comprising: a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed; an interface operable during a single programming operation to receive the event defining information for each of said plurality of test events and to cause that event defining information to be stored in the storage; and event processing logic operable, following said single programming operation, to execute said sequence of test events.