1. A processor for a computer system, the processor including at least one central processing unit and a resource access mechanism controlling access to resources addressed by at least one said central processing unit, the resource access mechanism including: an address control mechanism for receiving addresses, the address control mechanism having a plurality of address control entries, each address control entry being associated with one or more addresses and providing a fake response identification as to whether or not a response for a received address associated therewith is to be faked; and a fake response generator configured to generate a faked response where a fake response identification of an address control entry for a received address indicates that a response is to be faked.