1. An apparatus comprising: a floating-point (FP) multiplier circuit to multiply a first operand multiplicand mantissa by a second operand multiplier mantissa to generate a product; a FP alignment circuit to align a third operand mantissa according to the product of the FP multiplier circuit; an overflow detection circuit to detect an overflow condition in the product of the FP multiplier circuit; a first FP adder circuit to add together the aligned third operand mantissa and the product of the FP multiplier circuit using a first rounding input to generate a first sum or difference based on an assumption that the overflow condition in the product of the FP multiplier circuit was not detected; a second FP adder circuit to add together the aligned third operand mantissa and the product of the FP multiplier circuit using a second rounding input to generate a second sum or difference based on an assumption that the overflow condition in the product of the FP multiplier circuit was detected; and a multiplexer circuit to select between the second sum or difference and the first sum or difference based on the overflow detection circuit detecting, or not detecting the overflow condition, respectively, in the product of the FP multiplier circuit.