1. A One-Time Programmable (OTP) memory, comprising: a plurality of OTP memory cells, at least one of the OTP memory cells including at least: an OTP element including at least one portion formed of MOS gates and coupled to a first supply voltage line; and a selector including at least a first active region and a second active region built upon at least one fin structure divided by at least one MOS gate, where the first active region having a first or a second type of source/drain implant and the second region having the second type, or no source/drain implant, the first active region providing a first terminal of the selector, the second active region providing a second terminal of the selector, the at least one MOS gate providing a third terminal of the selector; both the first and second active regions residing in a common CMOS well or isolated substrate, the second active region being coupled to the OTP element, the first active region coupled to a second supply voltage line, and the MOS gate coupled to a third voltage supply line.