1. A general purpose set theoretic processor having a recognition matrix with a plurality of detection cells, said detection cells being coupled to receive output of a latent response memory, the improvement comprising: a latch matrix coupled said recognition matrix; a latch state save and restore memory coupled to said latch matrix, said latch state save and restore memory for retaining state of said latch matrix; an activity matrix with a plurality of activity cells coupled to said plurality of detection cells; said detection cells apply detection output to said activity matrix; and wherein connection among said activity cells and among said detection cells is effected only through said activity matrix.