1. A method for testing a device under test (DUT) by subjecting the DUT to a succession of stimulus signals with no substantial delays between said stimulus signals and by validating that acceptable response signals were returned from the DUT, where said lack of substantial delays between the stimulus signals allows the DUT to be tested at or substantially close to a prespecified maximum input rate for stimuli of the DUT, and where said DUT is one of mass produced devices, the method comprising: (a) logically assigning unique identifications to respective ones of the stimulus signals in said succession of stimulus signals to which the DUT is subjected with no substantial delays between the stimulus signals of said succession; (b) logically associating returned ones of response signals returned from the DUT with corresponding ones of the unique identifications assigned to respective stimulus signals of the respectively returned response signals, wherein logically associating comprises storing said response signals in memory locations used to compute memory locations of corresponding unique identifications; and (c) using the unique identifications to access the returned ones of the response signals when validating the returned response signals.