1. A microprocessor for executing instructions, wherein the microprocessor fetches a group of instructions comprising at least one control flow instruction and at least one non-control flow instruction, the microprocessor comprising: at least one decoder to pre-decode the group of instructions to generate control instruction identification information identifying the at least one control flow instruction and the at least one non control flow instruction; a control instruction identification unit that stores control instruction identification information; and a branch prediction unit that, based on the control instruction identification information, checks for branch prediction information corresponding to the at least one control flow instruction and does not check for branch prediction information corresponding to the at least one non control flow instruction.