1. A processor architecture ( 1 ), comprising: a first plurality of data processing elements ( 3 ; 3. 1 , 3. 2 ,. .. ), each data processing element of said first plurality of data processing elements comprising a respective synchronization unit ( 3 e , 3 f , 3 r ), a data link structure ( 4 ) adapted for dynamically interconnecting a number of the data processing elements from said first plurality of data processing elements, at least one configuration register ( 3 s , 5. 2 i , 5. 3 j ), and, at least one control unit ( 7 ) in operative connection with said configuration register for controlling a contents thereof, wherein, based on the contents of said configuration register, said first plurality of data processing elements ( 3 ; 3. 1 , 3. 2 ,. .. ) is adapted for temporarily constituting at runtime at least one group ( 2 ) of one or more of said data processing elements from said first plurality of data processing elements dynamically via said data link structure, wherein said synchronization units are adapted for synchronizing data processing by individual ones of the data processing elements within said group of data processing elements.