1. A method of analyzing an asynchronously clocked system having independently clocked subsystems with clock boundaries therebetween, comprising: a. identifying a boundary between two independently clocked subsystems; b. identifying behavior at the boundary between the two independently clocked subsystems; and c. modeling a latch at the boundary between the two independently clocked subsystems with a behavior model, said behavioral model comprising data receiver time delays and including a random number generator to select receiver time delays.