1. A method of simulating a logic network having multiple clocks, the method comprising the steps of: identifying one or more combinational logic elements in the logic network having input signals that do not derive from sequential logic elements controlled by a single clock signal; and re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, such that each of the one or more combinational logic elements has input signals that derive from sequential logic elements controlled by a single clock signal.