1. A method of operating a processor, comprising: fetching, by a fetch unit, a plurality of instruction threads, the instruction threads including load/store instructions; decoding, by a decode unit, the load/store instructions; dispatching, by a dispatch unit, each of the load/store instructions to an issue queue depending on availability of space in the issue queue; designating, by the issue queue, each of the load/store instructions in the issue queue as being a real load/store instruction or a virtual load/store instruction via a respective real/virtual indicator for each load/store instruction; and populating a load/store tag unit, with head, virtual and tail pointer information to indicate a next virtual load/store instruction in the issue queue to become a real load/store instruction and issue from the issue queue to a load/store unit.