1. A processor, comprising: fetch logic adapted to fetch instructions from memory; and decode logic coupled to said fetch logic and adapted to decode said fetched instructions; wherein, if a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or more instructions is executed in lieu of the particular fetched instruction; wherein, if the bit is in a second state, said group is executed in lieu of the particular fetched instruction and said particular fetched instruction is executed after said group is executed.