1. A vector processing, comprising: main storage means for storing vectors including plural vector elements; instruction means connected to said main storage means and responsive to an instruction requiring execution of an operation on a vector for generating first to third addresses, the first address being an address of one of the vector elements of a first vector held by said mainsstorage means, the second address being an address of one of the vector elements of a second vector held thereby and the third address being an address of one of the vector elements of a third vector to be held thereby; operation means for performing an operation on respective input pairs of vector elements supplied thereto; first operand control means connected to said main storage means and said instruction means and responsive to the generated first address for sequentially supplying vector elements of the first vector from said main storage means to said operation means, each as one vector element of an input pair of vector elements supplied to said operation means, starting from the one vector element having said first address, and in such a manner that a vector element next in element number or the same vector element as currently supplied to said operation means is supplied next, depending upon whether or not a first increment signal is supplied to said first operand control means; second operand control means connected to said main storage means and said instruction means and responsive to the generated second address for sequentially supplying vector elements of the second vector from said main storage to said operation means, each as the other vector element of the input pair of vector elements supplied to said oeration means, starting from the one vector element having said second address, and in such a manner that a vector element next in element number or the same vector element as currently supplied to said operation is supplied next, depending upon whether or not a second increment signal is applied to said second operand control means; third operand control means connected to said main storage means and said instruction means and responsive to the generated third address for sequentially writing sequential outputs of said operation means into said main storage means as vector elements of a third vector, starting from the one vector element having the third address and in such a manner that an output of said operation means is written as a vector element next in element number in response to receipt of a third increment signal; compare means connected to receive a pair of vector elements supplied to said oeration means from said first and second operand control means for comparing at least a part of one vector element of the pair with at least a part of the other vector element of the pair; and operation control means connected to said compare means and said first to third operand control means for selectively supplying said first to third increment signals respectively to said first to third operand control means depending upon a comparison result by said compare means.