1. A neuromorphic memory circuit comprising: a programmable resistive memory element; a conductive axon leaky integrate and fire (LIF) line configured to transmit an axon LIF pulse; a conductive dendrite LIF line configured to build up a dendrite LIF charge over time; a first transistor electrically coupled to the dendrite LIF line and the programmable resistive memory element, the first transistor providing a discharge path for the dendrite LIF charge through the programmable resistive memory element when the axon LIF line transmits the axon LIF pulse; a conductive axon spike timing dependent plasticity (STDP) line configured to transmit an axon STDP pulse, the axon STDP pulse being longer than the axon LIF pulse; a conductive dendrite STDP line configured to transmit a dendrite STDP pulse after voltage at the dendrite LIF line falls below a threshold voltage; and a second transistor electrically coupled to the axon STDP line and the programmable resistive memory element, the second transistor providing an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.