1. A method for performing size independent optimization of a logic circuit design comprising the steps of: creating a gain-based model for each cell type in a logic library; deriving initial conditions for a gain and a delay for each of said cell types, said deriving step includes the steps of: selecting an initial gain value for a selected cell type; calculating an initial scalable delay for said selected cell type; setting the initial scalable delay for the remaining cell types equal to said calculated initial scalable delay; and calculating an initial gain value for said remaining cell types; performing gain-based optimization of the circuit design; and transforming the optimized circuit design into a discrete solution with conventional library elements, resulting in an optimized circuit embodiment.