1. A data processor having a clustered architecture comprising: a branching cluster and a non-branching cluster, each capable of computing branch conditions, said branching cluster operable to perform branch address computations for said branching cluster and said non-branching cluster; and remote conditional branching control circuitry that causes said branching cluster to perform a branch address computation in response to sensing a conditional branch instruction in said non-branching cluster, and that communicates a computed branch condition from said non-branching cluster to said branching cluster.