1. An apparatus comprising: a first memory die comprising a first memory core; a second memory die comprising a second memory core; and a periphery die coupled to the first memory die and to the second memory die, wherein the periphery die comprises periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core, and wherein the periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.