1. An apparatus for controlling a non-volatile memory device, the apparatus comprising: a 3D array of nonvolatile memory cells, the 3D array including: a plurality of layers, each layer comprising (1) a plurality of NAND strings of nonvolatile memory cells, each of plurality of NAND strings coupled to a bit line and (2) a plurality of string select lines (SSL) and one or more word lines, the plurality of SSLs and the one or more word lines arranged orthogonally to the plurality of NAND strings, the plurality of string select lines (SSL) connected to the bit line, the one more word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of stacks and the one or more word lines, each of the plurality of NAND strings further comprising a plurality of string-select-line (SSL) transistors coupling the SSLs to the NAND strings, a first SSL transistor and a second SSL transistor forming a SSL string adjacent to a second SSL string comprised of an SSL transistor sharing a bias condition with the first SSL transistor and another SSL transistor sharing a bias condition with the second SSL transistor and repeated every four bit lines, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive a second voltage, a first SSL string belonging to a first bit line and a second SSL string belonging to a second bit line, the second bit line being adjacent to the first bit line, the first SSL string and the second SSL string forming a SSL string pair which is separated from a second SSL sting pair by a SSL string pair biasing with VDD, the first voltage and the second voltage being different than VDD, and wherein the second SSL being nearer to the one or more word lines.