1. A pipelined processor comprising: an instruction selector capable of selecting a sequence of instructions for execution, the instructions executing out-of-order; a data source coupled to the instruction selector and capable of supplying data for execution by the instructions; and a dependency scoreboard that tracks dependency of the out-of-order executing instructions, the dependency scoreboard including a table of storage cells that tracks producer instructions and consumer instructions and designates whether a particular instruction is dependent on a producer instruction using multiple-level dependency tracking.