1. A memory array, comprising: an N×M array of memory cells, each memory cell comprising: an n-type transistor connected to a first terminal, comprising a low injection-barrier material gate dielectric; a p-type transistor connected in serial between the n-type transistor and a second terminal, comprising a low injection-barrier material gate dielectric, wherein the first and second transistor share a common floating gate and a common output node; and an access transistor connected in serial between the first terminal and a high voltage terminal, the access transistor being configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate; and N bitline terminals connected to the output nodes of respective columns of memory cells; M upper wordline terminals connected to the high voltage terminals of respective rows of memory cells; M access wordline terminals connected to access transistor gates of respective rows of memory cells; and M lower wordline terminals connected to the second terminals of respective memory cells.