1. A method for designing a digital circuit using a hardware description language (HDL) having Term Rewriting System (TRS) rules, an HDL compiler defining a Term Rewriting System Compiler (TRSC), the method comprising the steps of: defining, using a computer, a signal to be of a clock data type, the clock data type distinct from a plurality of other data types provided by the HDL, the plurality of other data types including data types for defining level-sampled signals; specifying, using a computer, one or more modules with the HDL, each of the one or more modules accepting the signal of the clock data type as a condition for execution to render the module synchronous with the signal; specifying, using a computer, one or more TRS rules adapted to interact with the one or more modules, each of the one or more TRS rules having a predicate and an action body; and generating a synchronizer, using a computer, the synchronizer having ports in both a first clock domain and in a second clock domain, the first clock domain and the second clock domain being of different clock families; wherein the first clock domain and second clock domain being of different clock families are driven by different oscillator; implementing, by using the TRSC, a first TRS rule that interfaces with ports of the synchronizer in the first clock domain; implementing, by using the TRSC, a second TRS rule that interfaces with ports of the synchronizer in the second clock domain; and wherein the synchronizer is a FIFO-based synchronizer, the first TRS rule is an enqueue rule, and the second TRS rule is a dequeue rule.