1. A method for thread allocation in multi-stage, multi-thread digital processing, comprising: generating an address in a sequence of addresses, each address in the sequence enabling access to the contents of a different memory location, each memory location containing an instruction for a different thread, so that each address in the sequence corresponds to a different thread in a sequence of threads; determining if execution of a first thread corresponding to the generated address in the sequence of addresses is stalled; selecting the memory location corresponding to the generated address if execution of the first thread is not stalled; determining and selecting a memory location corresponding to a complementary thread instruction if execution of the first thread is stalled; and submitting for execution the thread instruction from the selected memory location.