1. An integrated circuit comprising: an array of flash memory cells organized into rows and columns, each cell in each row coupled to a row line and a column line; a programming circuitry for programming the array of flash memory cells, said programming circuitry implementing a method for programming the array of flash memory cells, comprising: performing a gate disturb on the flash memory cells; if cells fail to meet a predetermined threshold following the gate disturb, recording data for the cells; performing a column disturb on the flash memory cells; if cells fail to meet a predetermined threshold following the column disturb, recording data for the cells; and determining at least one programming parameter based on the recorded data.