1. A method for register-transfer level (RTL) design checking for exploring simulation mismatches, synthesis mismatches, or ambiguous language semantics associated with generating a derived design from RTL design code, the method comprising: providing the RTL design code, to at least one processor, to generate an internal representation for verification of an electronic circuit design; comparing, by a design match engine, the RTL design code with design violation patterns contained in a design violation pattern database, wherein the design violation patterns identify violations relating to the simulation mismatches, synthesis mismatches, or ambiguous language semantics associated with generating the derived design that are otherwise undetected during equivalence checking between the derived design and the RTL design code; assigning a rule object to a design pattern in the RTL design code, by the at least one processor, when the design match engine determines that the design pattern in the RTL design code matches one of the design violation patterns in the design violation pattern database; and generating, with the at least one processor, a violation report comprising the rule objects and their corresponding design violation patterns.