1. A load/store pipeline in a scalar processor for loading data to registers and storing data from said registers, the pipeline comprising: a) a register file which holds the results of an arithmetic logic operation; b) a translation buffer and a cache tag look up which are both coupled in parallel to the register file and receive a virtual address from the register file, said translation buffer performing a translation of the virtual address into a physical address, the cache tag look up performing a look up on untranslated bits of said virtual address; c) a comparator for comparing an output of said cache tag look up and an output of said translation buffer and producing a hit or miss signal based on said comparison; d) a data cache coupled to said register file which stores or retrieves data when there is a hit signal generated by said comparator; e) an output fifo coupled to said translation buffer which sends information out of said pipeline when there is a miss signal generated by said comparator to request data which is to be filled into said data cache; f) an input buffer coupled to said data cache which receives data from out of said pipeline which is to be filled into said data cache; and g) a memory reference tag which sends the tag corresponding to the data received by the input buffer to be stored in said cache tag look up.