1. A computer-implemented method for analyzing and adjusting a chip under analysis through statistical timing analysis, the method being performed with a computing device for generating a modified chip design for the chip under analysis, the method comprising: receiving a canonical form representing a timing quantity for a first timing region of the chip; propagating the canonical form through the first timing region of the chip; collapsing a first set of terms of the canonical form; propagating the canonical form having the collapsed first set of terms through a second timing region of the chip; determining results of the statistical timing analysis; wherein: the collapsed first set of terms corresponds to one or more sources of variation sensitive to, and present within, the first timing region of the chip but absent from, and not sensitive to, the second timing region of the chip, wherein the one or more sources of variation includes a specification voltage of the chip; and the collapsing involves placing the first set of terms in a cache and replacing the first set of terms in the canonical form with a single combined term using the collapsed first set of terms, and referencing the cached first set of terms; automatically generating, in a design program communicatively connected to the computing device, a modified operating specification for the chip under analysis, based on the results of the statistical timing analysis; and adjusting the chip to include the modified operating specification, wherein the modified operating specification causes the chip to operate with a voltage different from the specification voltage.