1. A hybrid programmable logic device, comprising: transceivers that receive data packets, wherein the data packets comprise header data and payload data; programmable logic fabric comprising programmable logic elements, wherein a first portion of the programmable logic elements provide hardware acceleration functions; processors interleaved with the programmable logic elements, wherein each of the processors process the received header data using the hardware acceleration functions and processing threads, and a second portion of the programmable logic elements schedule the distribution of header data to the processing threads, wherein each processing thread of the processors is associated with a unique address received by each of the processors via an interconnect shared by each of the processors, wherein each of the processors comprises a memory interface that monitors the received header data for the unique address associated with each respective processing thread and stores the received header data in a local memory when the received header data is marked with the unique address.