1. An address recall system coupled to a data processor system which includes a data processor, memory means and at least one peripheral unit for detecting and retrieving a predetermined number of processor system executed memory address signals, comprising: a. switch means for generating a first set of signals corresponding to a predetermined address within said processor system; b. control means for receiving address signals executed in said processor system and for detecting said predetermined address; c. storing means comprising a group of registers for storing a predetermined number of said processor system executed address signals received by said control means; and, d. means for retrieving said processor system executed address signals contained in said group of registers when said predetermined address is detected in said control means.