1. A computer processing system comprising: a hierarchical memory system having at least one cache; and a processor having execution logic that generates load memory requests that are supplied to the hierarchical memory system; wherein the at least one cache stores a plurality of cache lines as well as a plurality of valid bits for each cache line, wherein each cache line includes a plurality of data bytes, and wherein the plurality of valid bits for a given cache line correspond to the plurality of data bytes of the given cache line and provide an indication of the validity of the corresponding data bytes of the given cache line; wherein each given load memory request includes a cache line address that specifies a particular cache line as well as a request byte data that specifies at least one particular data byte of the cache line specified by the cache line address, and the cache is configured to process the given load memory request by i) accessing at least one cache line stored by the cache that putatively matches the cache line address of the load memory request, and ii) processing the valid bits of the accessed cache line together with the request byte data in order to output from the cache for supply to the execution logic only valid data bytes of the accessed cache line for those data bytes specified by the request byte data of the memory request.