1. A processor comprising: a plurality of simultaneous multi-threading (SMT) cores coupled over an interconnect to simultaneously execute multiple threads, each of the SMT cores including a Level 1 instruction cache and a Level 1 data cache; a Level 2 cache and a Level 3 cache shared by at least two of the cores; at least one of the cores comprising: an instruction fetch circuit to fetch instructions from a memory subsystem; a decoder to decode the instructions; a source register to store a plurality of 64-bit packed data elements; a destination register to store a plurality of packed data elements; execution circuitry to execute a vector leading zero count instruction to generate plurality of count values indicating a number of consecutive zeroes in each of the 64-bit packed data elements starting at a most significant bit position in each of the 64-bit packed data elements, the execution circuitry to store each count value in a packed data element location in the destination vector register corresponding to one of the 64-bit packed data elements.