1. A memory controller, comprising: a back end channel, wherein the back end channel includes: a command queue configured to hold commands; and circuitry configured to: modify at least a number of commands in the queue; and execute the modified commands; and a front end channel, wherein the front end channel includes circuitry configured to: receive commands from a host; send commands to the back end channel; and perform a number of functions selected from the group of functions including: changing the order in which the commands are sent to the back end channel; combining a number of combinable commands received from the host into a command; and deleting a command received from the host which will be overwritten by an other command received from the host.