1. An integrated circuit (IC), comprising: a logic region comprising a logic device disposed over a substrate and including a first metal gate electrode disposed over a high-k gate dielectric layer, a logic gate oxide layer and a memory gate oxide layer; and an embedded memory region disposed adjacent to the logic region and comprising a non-volatile memory (NVM) device including a second metal gate electrode disposed over the high-k gate dielectric layer; wherein the NVM device comprises a select transistor and a control transistor laterally spaced apart on the substrate, wherein the control transistor comprises a control gate electrode separated from the substrate by a charge trapping layer and the high-k gate dielectric layer, and the select transistor comprises a select gate electrode separated from the substrate by the high-k gate dielectric layer and the memory gate oxide layer; wherein the memory gate oxide layer is arranged between the high-k gate dielectric layer and the logic gate oxide layer below the first metal gate electrode.